mirror of
https://github.com/nathanriggs/AppleIIAsm-Collection.git
synced 2024-12-02 12:52:03 +00:00
9b12b6fd9b
- getting ready for major changes for 0.6.0. - be sure to download the 0.5.0 release to ensure proper functionality, as these rountines will not work together in the SRC or BIN folder during the transition - Beginning to significantly alter documentation
257 lines
5.8 KiB
NASM
257 lines
5.8 KiB
NASM
]RIGHT DS 1
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]LEFT DS 1
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]LENGTH DS 1
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]A DS 1
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]X DS 1
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]Y DS 1
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]C DS 1
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]Z DS 1
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]N DS 1
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]O DS 1
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]HEXTAB ASC "0123456789ABCDEF"
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]COUT EQU $FDF0
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]KYBD EQU $C000
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]STROBE EQU $C010
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__DUMP
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STY ]LENGTH
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STA ADDR1
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STX ADDR1+1
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LDA #$8D
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JSR ]COUT
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LDA ADDR1+1
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CLRHI
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TAX
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LDA ]HEXTAB,X
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JSR ]COUT
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LDA ADDR1+1
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AND #$0F
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TAX
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LDA ]HEXTAB,X
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JSR ]COUT
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LDA ADDR1
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CLRHI
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TAX
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LDA ]HEXTAB,X
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JSR ]COUT
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LDA ADDR1
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AND #$0F
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TAX
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LDA ]HEXTAB,X
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JSR ]COUT
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LDA #":"
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JSR ]COUT
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LDA "#"
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JSR ]COUT
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LDY #0
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:LP
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LDA (ADDR1),Y
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CLRHI ; ++<[16C10B] AT COUNTER OFFSET
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STA ]LEFT
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LDA (ADDR1),Y
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AND #$0F
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STA ]RIGHT
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LDX ]LEFT
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LDA ]HEXTAB,X
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JSR ]COUT
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LDX ]RIGHT
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LDA ]HEXTAB,X
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JSR ]COUT
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LDA #160
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JSR ]COUT
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INY
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CPY ]LENGTH
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BNE :LP
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RTS
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__ERRH
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LDA #1
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STA $AAB6
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STA $75+1
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STA $33
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STA ADDR1
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STX ADDR1+1
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LDA #$FF
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STA $D8
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LDY #0
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LDA (ADDR1),Y
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STA $9D5A
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INY
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LDA (ADDR1),Y
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STA $9D5B
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RTS
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__P
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PLA
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STA ADDR1
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PLA
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STA ADDR1+1
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LDY #1
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:LP LDA (ADDR1),Y
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BEQ :DONE
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JSR ]COUT
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INY
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BNE :LP
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:DONE CLC
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TYA
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ADC ADDR1
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STA ADDR1
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LDA ADDR1+1
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ADC #0
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PHA ; ++<3C1B> IF NEEDED
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LDA ADDR1
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PHA
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RTS
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DELAYMS
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]MSCNT EQU $0CA
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:DELAY
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CPY #0
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BEQ :EXIT
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NOP
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CPY #1
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BNE :DELAYA
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JMP :LAST1
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:DELAYA
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DEY
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:DELAY0
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LDX #]MSCNT
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:DELAY1
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DEX
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BNE :DELAY1
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NOP
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NOP
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DEY
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BNE :DELAY0
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:LAST1
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LDX #]MSCNT-3
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:DELAY2
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DEX
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BNE :DELAY2
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:EXIT
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RTS
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]FILL EQU BPAR1
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]SIZE EQU WPAR2
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]ADDR EQU WPAR1
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MEMFILL
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LDA ]FILL
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LDX ]SIZE+1
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BEQ :PARTPG
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LDY #0
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:FULLPG
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STA (]ADDR),Y
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INY
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BNE :FULLPG
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INC ]ADDR+1
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DEX
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BNE :FULLPG
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:PARTPG
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LDX ]SIZE
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BEQ :EXIT
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LDY #0
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:PARTLP
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STA (]ADDR),Y
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INY
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DEX
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BNE :PARTLP
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:EXIT
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RTS
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]SIZE EQU WPAR3
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]ADDR1 EQU WPAR1
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]ADDR2 EQU WPAR2
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MEMMOVE
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LDA ]ADDR2
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SEC
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SBC ]ADDR1
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TAX
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LDA ]ADDR2+1
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SBC ]ADDR1+1
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TAY
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TXA
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CMP ]SIZE
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TYA
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SBC ]SIZE+1
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BCS :DOLEFT
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JSR :MVERHT
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JMP :MREXIT
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:DOLEFT
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JSR :MVELEFT
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:EXIT
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JMP :MREXIT
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:MVELEFT
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LDY #0
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LDX ]SIZE+1
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BEQ :MLPART
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:MLPAGE
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LDA (]ADDR1),Y
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STA (]ADDR2),Y
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INY
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BNE :MLPAGE
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INC ]ADDR1+1
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INC ]ADDR2+1
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DEX
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BNE :MLPAGE
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:MLPART
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LDX ]SIZE
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BEQ :MLEXIT
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:MLLAST
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LDA (]ADDR1),Y
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STA (]ADDR2),Y
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INY
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DEX
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BNE :MLLAST
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:MLEXIT
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JMP :MREXIT
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:MVERHT
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LDA ]SIZE+1
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CLC
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ADC ]ADDR1+1
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STA ]ADDR1+1
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LDA ]SIZE+1
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CLC
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ADC ]ADDR2+1
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STA ]ADDR2+1
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LDY ]SIZE
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BEQ :MRPAGE
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:MR0
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DEY
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LDA (]ADDR1),Y
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STA (]ADDR2),Y
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CPY #0
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BNE :MR0
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:MRPAGE
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LDX ]SIZE+1
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BEQ :MREXIT
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:MR1
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DEC ]ADDR1+1
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DEC ]ADDR2+1
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:MR2
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DEY
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LDA (]ADDR1),Y
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STA (]ADDR2),Y
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CPY #0
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BNE :MR2
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DEX
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BNE :MR1
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:MREXIT
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RTS
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]SIZE EQU BPAR1
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]ADDR1 EQU WPAR1
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]ADDR2 EQU WPAR2
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MEMSWAP
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LDY #255
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:LP
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INY
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LDA (]ADDR1),Y
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TAX
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LDA (]ADDR2),Y
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STA (]ADDR1),Y
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TXA
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STA (]ADDR2),Y
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CPY ]SIZE
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BNE :LP
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RTS
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RTS
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