diff --git a/auxmem.audio.s b/auxmem.audio.s index ad4c0c6..1a7ba57 100644 --- a/auxmem.audio.s +++ b/auxmem.audio.s @@ -74,26 +74,117 @@ INSHND PHP ; Save flags, turn off interrupts * OSBYTE &07 - Make a sound * On entry: (OSCTRL),Y points to eight byte parameter block (2 bytes each for * channel, amplitude, pitch, duration) -WORD07 LDA (OSCTRL),Y ; Get channel number 0-3 - ORA #$04 ; Convert to buffer number 4-7 +WORD07 LDA (OSCTRL),Y ; Get channel number 0-3 + ORA #$04 ; Convert to buffer number 4-7 TAX ; Into X INY ; Point to channel num MSB INY ; Point to amplitude LSB - LDA (OSCTRL),Y - JSR INSHND ; SHOULD CALL THIS THRU VECTOR INSV + LDA (OSCTRL),Y + JSR INSHND ; Insert into queue X INY ; Point to amplitude MSB - LDA (OSCTRL),Y - JSR INSHND ; SHOULD CALL THIS THRU VECTOR INSV INY ; Point to pitch LSB - LDA (OSCTRL),Y - JSR INSHND ; SHOULD CALL THIS THRU VECTOR INSV + LDA (OSCTRL),Y + JSR INSHND ; Insert into queue X INY ; Point to pitch MSB - LDA (OSCTRL),Y - JSR INSHND ; SHOULD CALL THIS THRU VECTOR INSV INY ; Point to duration LSB - LDA (OSCTRL),Y - JSR INSHND ; SHOULD CALL THIS THRU VECTOR INSV - INY ; Point to duration MSB - LDA (OSCTRL),Y - JMP INSHND ; SHOULD CALL THIS THRU VECTOR INSV + JSR INSHND ; Insert into queue X + RTS + +* OSBYTE &08 - Envelope +* On entry: (OSCTRL),Y points to 14 byte parameter block +WORD08 +* TODO: IMPLEMENT THIS!!! + RTS + +* Called from Ensoniq interrupt handler - process audio queue +* +ENSQIRQ +* TODO: IMPLEMENT THIS!!! + RTS + +* Initialize Ensoniq +ENSQSNDCTL EQU $C03C +ENSQSNDDAT EQU $C03D +ENSQADDRL EQU $C03E +ENSQADDRH EQU $C03F + +ENSQINIT LDA ENSQSNDCTL ; Get settings + ORA #$60 ; DOC RAM, autoincrement on + STA ENSQSNDCTL ; Set it + LDA #$00 + STA ENSQADDRL ; DOC RAM addr $0000 + STA ENSQADDRH ; DOC RAM addr $0000 + LDA #120 ; High value of square wave + LDX #$00 +:L1 STA ENSQSNDDAT ; 128 cycles of high value + INX + CPX #128 + BNE :L1 + LDA #80 ; Low value of square wave +:L2 STA ENSQSNDDAT ; 128 cycles of low value + INX + CPX #0 + BNE :L2 + LDX #$E1 ; DOC Osc Enable register $E1 + LDY #8 ; Four oscillators enabled + JSR ENSQWRTDOC + LDX #$00 ; Amplitude + LDA #$80 ; Frequency + LDY #$03 +:L3 JSR ENSQOSCIL ; Initialize channel Y + DEY + BPL :L3 + RTS + +* Configure Ensoniq oscillator +* On entry: Y - oscillator number 0-3 , A - frequency, X - amplitude +* Preserves all registers +* TODO: ALWAYS USES OSCILLATOR CHANNEL 0 FOR NOW +ENSQOSCIL PHA + PHY + PHX + LDX #$00 ; DOC register $00 (Freq Lo) + TAY ; Frequency value LS byte + JSR ENSQWRTDOC + LDX #$20 ; DOC register $20 (Freq Hi) + LDY #$00 ; Frequency value MS byte + JSR ENSQWRTDOC + LDX #$40 ; DOC register $40 (Volume) + PLY ; Frequency value orig in X + PHY + JSR ENSQWRTDOC + LDX #$80 ; DOC register $80 (Wavetable) + LDY #$00 ; Wavetable pointer $00 + JSR ENSQWRTDOC + LDX #$A0 ; DOC register $A0 (Control) + LDY #$00 ; Free run, no IRQ, start + JSR ENSQWRTDOC + LDX #$C0 ; DOC register $C0 (WT size) + LDY #$00 ; For 256 byte wavetable + JSR ENSQWRTDOC + PLX + PLY + PLA + RTS + +* Wait for Ensoniq to be ready +ENSQWAIT LDA ENSQSNDDAT + AND #$80 + BNE ENSQWAIT + RTS + +* Write to DOC registers +* On entry: Value in Y, register in X +* Preserves all registers +ENSQWRTDOC PHA + JSR ENSQWAIT ; Wait for DOC to be ready + LDA ENSQSNDCTL + AND #$90 ; DOC register, no autoincr + ORA #$0F ; Master volume maximum + STA ENSQSNDCTL + STX ENSQADDRL ; Select DOC register + STZ ENSQADDRH + STY ENSQSNDDAT ; Write data + PLA + RTS diff --git a/auxmem.bytwrd.s b/auxmem.bytwrd.s index 8c88756..1c3964c 100644 --- a/auxmem.bytwrd.s +++ b/auxmem.bytwrd.s @@ -95,7 +95,7 @@ OSWBASE DW WORD00 ; OSWORD 0 - Read input line DW WORD05 ; OSWORD 5 - Read I/O memory DW WORD06 ; OSWORD 6 - Write I/O memory DW WORD07 ; OSWORD 7 - SOUND -* DW WORD08 ; OSWORD 8 - ENVELOPE + DW WORD08 ; OSWORD 8 - ENVELOPE * DW WORD09 ; OSWORD 9 - POINT * DW WORD0A ; OSWORD 10 - Read character bitmap * DW WORD0B ; OSWORD 11 - Read palette diff --git a/auxmem.init.s b/auxmem.init.s index 06bfa31..139f3a8 100644 --- a/auxmem.init.s +++ b/auxmem.init.s @@ -134,6 +134,8 @@ MOSHIGH SEI ; Disable IRQ while initializing DEX BNE :INITSND + JSR ENSQINIT ; Initialize Ensoniq DOC + LDA $C036 ; GS speed register AND #$80 ; Speed bit only STA GSSPEED ; In Alt LC for IRQ/BRK hdlr diff --git a/mame_applecorn b/mame_applecorn index 1afa9dd..f821621 100755 --- a/mame_applecorn +++ b/mame_applecorn @@ -1,2 +1,2 @@ -#mame -w apple2ee -debug -sl7 cffa2 -harddisk1 ~/Personal/Development/Applecorn/applecorn.po +#mame -w apple2ee -debug -sl5 mouse -sl7 cffa2 -harddisk1 ~/Personal/Development/Applecorn/applecorn.po mame -w apple2gs -debug -sl7 cffa2 -harddisk1 ~/Personal/Development/Applecorn/applecorn.po