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Cleanup use of memory macros in auxmem (part 2/2)
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Bobbi Webber-Manners
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applecorn.po
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applecorn.po
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76
auxmem.vdu.s
76
auxmem.vdu.s
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@ -361,16 +361,16 @@ PRCHR4 JSR CHARADDR ; Find character address
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TXA ; Get character back
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BIT VDUBANK
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BPL PRCHR5 ; Not AppleGS, use short write
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA [VDUADDR],Y
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STA $C005 ; Write to aux
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>>> WRTAUX
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BRA PRCHR8
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PRCHR5 PHP ; Disable IRQs while
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SEI ; toggling memory
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BCC PRCHR6 ; Aux memory
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STA $C004 ; Switch to main memory
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>>> WRTMAIN
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PRCHR6 STA (VDUADDR),Y ; Store it
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PRCHR7 STA $C005 ; Back to aux memory
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PRCHR7 >>> WRTAUX
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PLP ; Restore IRQs
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PRCHR8 PLA
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BIT VDUSCREEN
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@ -388,9 +388,9 @@ GETCHRC JSR CHARADDR ; Find character address
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PHP ; Disable IRQs while
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SEI ; toggling memory
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BCC GETCHR6 ; Aux memory
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STA $C002 ; Switch to main memory
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STA $C002 ; Read main memory
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GETCHR6 LDA (VDUADDR),Y ; Get character
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STA $C003 ; Back to aux memory
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STA $C003 ; Read aux memory
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PLP ; Restore IRQs
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TAY ; Convert character
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AND #$A0
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@ -406,9 +406,9 @@ GETCHROK RTS
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GETCHRGS PHP ; Disable IRQs while
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SEI ; toggling memory
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BCC GETCHR8 ; Aux memory
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STA $C002 ; Switch to main memory
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STA $C002 ; Read main memory
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GETCHR8 LDA [VDUADDR],Y ; Get character
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STA $C003 ; Back to aux memory
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STA $C003 ; Read aux memory
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PLP ; Restore IRQs
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TAY ; Convert character
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AND #$A0
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@ -668,9 +668,9 @@ CLREOL JSR CHARADDR ; Set VDUADDR=>start of line
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BRA :SKIPMAIN
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:MAIN PHP
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SEI
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA (VDUADDR),Y
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STA $C005 ; Write to aux
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>>> WRTAUX
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PLP
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:SKIPMAIN INX
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CPX TXTWINRGT
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@ -679,9 +679,9 @@ CLREOL JSR CHARADDR ; Set VDUADDR=>start of line
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:FORTY LDA #$A0
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:L2 PHP
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SEI
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA (VDUADDR),Y
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STA $C005 ; Write to aux
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>>> WRTAUX
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PLP
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INY
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CPY TXTWINRGT
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@ -701,16 +701,16 @@ CLREOLGS BIT $C01F
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LDA #$E1
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STA VDUBANK
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LDA #$A0
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA [VDUADDR],Y ; Even cols in bank $E1
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STA $C005 ; Write to aux
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>>> WRTAUX
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BRA :SKIPE0
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:E0 LDA #$E0
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STA VDUBANK
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LDA #$A0
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA [VDUADDR],Y ; Odd cols in bank $E0
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STA $C005 ; Write to aux
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>>> WRTAUX
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:SKIPE0 INX
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CPX TXTWINRGT
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BMI :L1
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@ -718,9 +718,9 @@ CLREOLGS BIT $C01F
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:FORTY LDA #$E0
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STA VDUBANK
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LDA #$A0
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:L2 STA $C004 ; Write to main
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:L2 >>> WRTMAIN
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STA [VDUADDR],Y
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STA $C005 ; Write to aux
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>>> WRTAUX
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INY
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CPY TXTWINRGT
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BMI :L2
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@ -812,12 +812,12 @@ DOSCR1LINE INC TXTWINRGT
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BRA :SKIPMAIN
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:MAIN PHP
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SEI
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STA $C002 ; Read from main
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA $C002 ; Read main memory
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LDA (VDUADDR),Y
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STA (VDUADDR2),Y
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STA $C003 ; Read from aux
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STA $C005 ; Write to aux
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STA $C003 ; Read aux memory
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>>> WRTAUX
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PLP
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:SKIPMAIN INX
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CPX TXTWINRGT
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@ -827,12 +827,12 @@ DOSCR1LINE INC TXTWINRGT
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TAY
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:L2 PHP
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SEI
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STA $C002 ; Read from main
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA $C002 ; Read main memory
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LDA (VDUADDR),Y
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STA (VDUADDR2),Y
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STA $C003 ; Read from aux
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STA $C005 ; Write to aux
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STA $C003 ; Read aux memory
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>>> WRTAUX
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PLP
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INY
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CPY TXTWINRGT
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@ -851,22 +851,22 @@ SCR1LINEGS LDX TXTWINLFT
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LDA #$E1
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STA VDUBANK
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STA VDUBANK2
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STA $C002 ; Read from main
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA $C002 ; Read main memory
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LDA [VDUADDR],Y ; Even cols in bank $E1
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STA [VDUADDR2],Y
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STA $C003 ; Read from aux
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STA $C005 ; Write to aux
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STA $C003 ; Read aux memory
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>>> WRTAUX
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BRA :SKIPE0
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:E0 LDA #$E0
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STA VDUBANK
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STA VDUBANK2
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STA $C002 ; Read from main
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STA $C004 ; Write to main
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>>> WRTMAIN
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STA $C002 ; Read main memory
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LDA [VDUADDR],Y ; Odd cols in bank $E0
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STA [VDUADDR2],Y
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STA $C003 ; Read from aux
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STA $C005 ; Write to aux
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STA $C003 ; Read aux memory
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>>> WRTAUX
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:SKIPE0 INX
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CPX TXTWINRGT
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BMI :L1
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@ -875,12 +875,12 @@ SCR1LINEGS LDX TXTWINLFT
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TAY
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LDA #$E0
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STA VDUBANK
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:L2 STA $C002 ; Read from main
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STA $C004 ; Write to main
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:L2 >>> WRTMAIN
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STA $C002 ; Read main memory
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LDA [VDUADDR],Y
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STA [VDUADDR2],Y
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STA $C003 ; Read from aux
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STA $C005 ; Write to aux
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STA $C003 ; Read aux memory
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>>> WRTAUX
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INY
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CPY TXTWINRGT
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BMI :L2
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