Apple-2-SW/Applecorn
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Updated build date.

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Bobbi Webber-Manners 2021-10-10 14:18:26 -04:00
parent f11aedbb29
commit 281360de93
4 changed files with 3 additions and 3 deletions
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BIN
applecorn.po
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2
auxmem.init.s
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@ -177,7 +177,7 @@ BYTE00XX BEQ BYTE00A ; OSBYTE 0,0 - generate error
RTS ; %000x1xxx host type, 'A'pple
BYTE00A BRK
DB $F7
HELLO ASC 'Applecorn MOS 2021-09-29'
HELLO ASC 'Applecorn MOS 2021-10-10'
DB $00 ; Unify MOS messages

2
auxmem.misc.s
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@ -415,7 +415,7 @@ IRQBRKHDLR PHA
:IRQ >>> XF2MAIN,A2IRQ ; Bounce to Apple IRQ handler
IRQBRKRET
>>> IENTAUX ; IENTAUX does not do CLI
PLA ; TODO: Pass on to IRQ1V
PLA ; TO DO: Pass on to IRQ1V
TAX
PLA
NULLRTI RTI

2
mainmem.wild.s
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@ -93,7 +93,7 @@ WILDNEXT LDX MFTEMP ; Length of MFTEMP
* Different version of WILDNEXT which is used by the *INFO handler
* Because it needs to intercept each block.
* TODO: Once this works, refactor/cleanup
* TO DO: Refactor/cleanup
WILDNEXT2 LDX MFTEMP ; Length of MFTEMP
:L1 CPX #$00 ; Find final segment (previous match)
BEQ :AGAIN