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Minor code cleanup after merging JGH PR
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applecorn.po
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applecorn.po
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@ -23,9 +23,6 @@ ZP1 EQU $90 ; $90-$9f are spare Econet space
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ZP2 EQU $92
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ZP3 EQU $94
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*STRTBCKL EQU $9D ; *TO DO* No longer needed to preserve
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*STRTBCKH EQU $9E
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MOSSHIM
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ORG AUXMOS ; MOS shim implementation
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@ -45,7 +42,9 @@ MOSSHIM
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MOSINIT SEI ; Ensure IRQs disabled
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LDX #$FF ; Initialize Alt SP to $1FF
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TXS
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* Ensure memory map set up:
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* Ensure memory map setup ...
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STA WRCARDRAM ; Make sure we are writing aux
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STA 80STOREOFF ; Make sure 80STORE is off
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STA SET80VID ; 80 col on
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@ -57,10 +56,9 @@ MOSINIT SEI ; Ensure IRQs disabled
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LDY #$00 ; $00=Soft Reset
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:MODBRA SEC ; Changed to CLC after first run
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BCC :NORELOC ; Subsequent run, skip to code
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* BRA :RELOC ; NOPped out on first run
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* BRA :NORELOC
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* Copy code to high memory, (OSCTRL)=>source, (OSLPTR)=>dest
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:RELOC LDA #<AUXMOS1 ; Source
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STA OSCTRL+0
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LDA #>AUXMOS1
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@ -83,20 +81,9 @@ MOSINIT SEI ; Ensure IRQs disabled
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LDA #$18 ; CLC opcode, next time around, we're
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STA :MODBRA ; already in high memory
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* Changing only one byte ensures against a RESET happening halfway between
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* two bytes being changed - and is five bytes shorter!
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* LDA #$EA ; NOP opcode
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* STA :MODBRA+0 ; Next time around, we're already
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* STA :MODBRA+1 ; in high memory
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LDY #$02 ; $02=PowerOn
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:NORELOC
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* STA SET80VID ; 80 col on
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* STA CLRALTCHAR ; Alt charset off
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* STA PAGE2 ; PAGE2
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JMP MOSHIGH ; Ensure executing in high memory from here
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:NORELOC JMP MOSHIGH ; Ensure executing in high memory from here
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* From here onwards we are always executing at $D000 onwards
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* Y=ResetType
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@ -231,8 +218,6 @@ BYTE00 BEQ BYTE00A ; OSBYTE 0,0 - generate error
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RTS ; %000x1xxx host type, 'A'pple
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BYTE00A BRK
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DB $F7
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HELLO ASC 'Applecorn MOS 2022-11-08'
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HELLO ASC 'Applecorn MOS 2022-12-14'
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DB $00 ; Unify MOS messages
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* TO DO: Move into RAM
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* GSSPEED DB $00 ; $80 if GS is fast, $00 for slow
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