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INIT sets ResetType OSBYTE variable

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When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak.
The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P
And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
This commit is contained in:
jgharston 2022-11-08 15:11:55 +00:00 committed by GitHub
parent eccc83d8b4
commit e58f305525
1 changed files with 60 additions and 44 deletions
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104
auxmem.init.s
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@ -2,6 +2,8 @@
* (c) Bobbi 2021 GPL v3 * (c) Bobbi 2021 GPL v3
* *
* Initialization code running in Apple //e aux memory * Initialization code running in Apple //e aux memory
* 08-Nov-2022 ResetType OSBYTE set
*********************************************************** ***********************************************************
* BBC Micro 'virtual machine' in Apple //e aux memory * BBC Micro 'virtual machine' in Apple //e aux memory
@ -26,26 +28,27 @@ MOSSHIM
* This code is initially loaded into aux mem at AUXMOS1 * This code is initially loaded into aux mem at AUXMOS1
* Then relocated into aux LC at AUXMOS by MOSINIT * Then relocated into aux LC at AUXMOS by MOSINIT
* *
* Initially executing at $3000 until copied to $D000 * Initially executing at $2000 until copied to $D000
*
* When running with BRUN APPLECORN:
* Code will be at $2000-$4FFF, then copied to $D000-$FFFF
* When Ctrl-Reset pressed:
* AUX RESET code jumps to MAIN $D000
*
MOSINIT SEI ; Ensure IRQs disabled MOSINIT SEI ; Ensure IRQs disabled
LDX #$FF ; Initialize Alt SP to $1FF LDX #$FF ; Initialize Alt SP to $1FF
TXS TXS
STA WRCARDRAM ; Make sure we are writing aux STA WRCARDRAM ; Make sure we are writing aux
STA 80STOREOFF ; Make sure 80STORE is off STA 80STOREOFF ; Make sure 80STORE is off
LDA LCBANK1 ; LC RAM Rd/Wt, 1st 4K bank LDA LCBANK1 ; LC RAM Rd/Wt, 1st 4K bank
LDA LCBANK1 LDA LCBANK1
LDY #$00 ; $02=Soft Reset
:MODBRA BRA :RELOC ; NOPped out on first run :MODBRA BRA :RELOC ; NOPped out on first run
BRA :NORELOC BRA :NORELOC
LDA #$EA ; NOP opcode :RELOC LDA #<AUXMOS1 ; Relocate MOS shim
STA :MODBRA
STA :MODBRA+1
:RELOC LDA #<AUXMOS1 ; Relocate MOS shim
STA A1L STA A1L
LDA #>AUXMOS1 LDA #>AUXMOS1
STA A1H STA A1H
@ -103,52 +106,66 @@ MOSINIT SEI ; Ensure IRQs disabled
INC A4H INC A4H
:S7 BRA :L2 :S7 BRA :L2
:NORELOC :S8
:S8 STA SET80VID ; 80 col on LDA #$EA ; NOP opcode
STA CLRALTCHAR ; Alt charset off STA :MODBRA+0 ; Next time around, we're already
STA PAGE2 ; PAGE2 STA :MODBRA+1 ; in high memory
JMP MOSHIGH ; Ensure executing in high memory here LDY #$02 ; $02=PowerOn
MOSHIGH SEI ; Ensure IRQs disabled :NORELOC STA SET80VID ; 80 col on
STA CLRALTCHAR ; Alt charset off
STA PAGE2 ; PAGE2
JMP MOSHIGH ; Ensure executing in high memory from here
* From here onwards we are always executing at $D000 onwards
* Y=ResetType
MOSHIGH SEI ; Ensure IRQs disabled
LDX #$FF LDX #$FF
TXS ; Initialise stack TXS ; Initialise stack
INX ; X=$00 INX ; X=$00
TXA TXA
:SCLR STA $0000,X ; Clear Kernel memory :SCLR STA $0000,X ; Clear Kernel memory
STA $0200,X STA $0200,X
STA $0300,X STA $0300,X
INX INX
BNE :SCLR BNE :SCLR
INC BYTEVARBASE+$FD ; Last reset=Hard STY BYTEVARBASE+$FD ; Set ResetType
* TO DO: Do this properly
LDX #ENDVEC-DEFVEC-1 LDX #ENDVEC-DEFVEC-1
:INITPG2 LDA DEFVEC,X ; Set up vectors :INITPG2 LDA DEFVEC,X ; Set up vectors
STA $200,X STA $200,X
DEX DEX
BPL :INITPG2 BPL :INITPG2
LDA CYAREG ; GS speed register LDA CYAREG ; GS speed register
AND #$80 ; Speed bit only AND #$80 ; Speed bit only
STA GSSPEED ; In Alt LC for IRQ/BRK hdlr STA GSSPEED ; In Alt LC for IRQ/BRK hdlr
JSR ROMINIT ; Build list of sideways ROMs JSR ROMINIT ; Build list of sideways ROMs
JSR KBDINIT ; Returns A=startup MODE JSR KBDINIT ; Returns A=startup MODE
JSR VDUINIT ; Initialise VDU driver JSR VDUINIT ; Initialise VDU driver
JSR PRHELLO JSR PRHELLO
LDA #7 LDA BYTEVARBASE+$FD ; Get ResetType
BEQ :INITSOFT
LDA #7 ; Beep on HardReset
JSR OSWRCH JSR OSWRCH
JSR OSNEWL * AppleII MOS beeps anyway, so always get a Beep
* BRUN APPLECORN -> BBC Beep
* Ctrl-Reset -> AppleII Beep
*
:INITSOFT JSR OSNEWL
LDX MAXROM ; *TEMP* X=language to enter LDX MAXROM ; *TEMP* X=language to enter
CLC * TO DO: SoftReset->Use CURRLANG, HardReset->Search for language
*
CLC ; CLC=Entering from RESET
* OSBYTE $8E - Enter language ROM * OSBYTE $8E - Enter language ROM
********************************* *********************************
* X=ROM number to select * X=ROM number to select, CC=RESET, CS=*COMMAND/OSBYTE
* *
BYTE8E PHP ; Save CLC=RESET, SEC=Not RESET BYTE8E PHP ; Save CLC=RESET, SEC=Not RESET
JSR ROMSELECT ; Bring ROM X into memory JSR ROMSELECT ; Bring ROM X into memory
STX BYTEVARBASE+$FC ; Set current language ROM
LDA #$00 LDA #$00
STA FAULT+0 STA FAULT+0
LDA #$80 LDA #$80
@ -158,6 +175,7 @@ BYTE8E PHP ; Save CLC=RESET, SEC=Not RESET
STY FAULT+0 ; FAULT pointing to version string STY FAULT+0 ; FAULT pointing to version string
JSR OSNEWL JSR OSNEWL
JSR OSNEWL JSR OSNEWL
STX BYTEVARBASE+$FC ; Set current language ROM
PLP ; Get entry type back PLP ; Get entry type back
LDA #$01 ; $01=Entering code with a header LDA #$01 ; $01=Entering code with a header
JMP ROMAUXADDR JMP ROMAUXADDR
@ -198,20 +216,18 @@ SERVICEX LDA $F4 ; Enter here with X=Service Number
TXA ; Return in A and X and set EQ/NE TXA ; Return in A and X and set EQ/NE
RTS RTS
PRHELLO LDX #<HELLO PRHELLO LDX #<HELLO
LDY #>HELLO LDY #>HELLO
JSR OSPRSTR JSR OSPRSTR
JMP OSNEWL JMP OSNEWL
* BYTE00XX BYTE00 BEQ BYTE00A ; OSBYTE 0,0 - generate error
BYTE00 BEQ BYTE00A ; OSBYTE 0,0 - generate error LDX #$0A ; Identify Host
LDX #$0A ; Identify Host RTS ; %000x1xxx host type, 'A'pple
RTS ; %000x1xxx host type, 'A'pple
BYTE00A BRK BYTE00A BRK
DB $F7 DB $F7
HELLO ASC 'Applecorn MOS 2022-11-07' HELLO ASC 'Applecorn MOS 2022-11-04'
DB $00 ; Unify MOS messages DB $00 ; Unify MOS messages
* TO DO: Move into RAM * TO DO: Move into RAM
GSSPEED DB $00 ; $80 if GS is fast, $00 for slow GSSPEED DB $00 ; $80 if GS is fast, $00 for slow