mirror of
https://github.com/bobbimanners/Applecorn.git
synced 2025-01-19 05:30:35 +00:00
e58f305525
When first run, ResetType=PowerOn, when Ctrl-Reset pressed, ResetType=SoftBreak. The symantics are odd because the AppleII requires you to press CTRL, which in Beeb-land means HardBreak, but in Apple-land means SoftBreak. :P And in Apple-land, you can't read the Shift key, LAlt forces an AppleII restart, RAlt enters Apple test code.
234 lines
7.4 KiB
ArmAsm
234 lines
7.4 KiB
ArmAsm
* AUXMEM.INIT.S
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* (c) Bobbi 2021 GPL v3
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*
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* Initialization code running in Apple //e aux memory
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* 08-Nov-2022 ResetType OSBYTE set
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***********************************************************
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* BBC Micro 'virtual machine' in Apple //e aux memory
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***********************************************************
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MAXROM EQU $F9 ; Max sideways ROM number
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ZP1 EQU $90 ; $90-$9f are spare Econet space
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; so safe to use
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ZP2 EQU $92
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ZP3 EQU $94
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*STRTBCKL EQU $9D ; *TO DO* No longer needed to preserve
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*STRTBCKH EQU $9E
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MOSSHIM
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ORG AUXMOS ; MOS shim implementation
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*
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* Shim code to service Acorn MOS entry points using
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* Apple II monitor routines
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* This code is initially loaded into aux mem at AUXMOS1
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* Then relocated into aux LC at AUXMOS by MOSINIT
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*
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* Initially executing at $2000 until copied to $D000
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*
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* When running with BRUN APPLECORN:
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* Code will be at $2000-$4FFF, then copied to $D000-$FFFF
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* When Ctrl-Reset pressed:
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* AUX RESET code jumps to MAIN $D000
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*
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MOSINIT SEI ; Ensure IRQs disabled
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LDX #$FF ; Initialize Alt SP to $1FF
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TXS
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STA WRCARDRAM ; Make sure we are writing aux
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STA 80STOREOFF ; Make sure 80STORE is off
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LDA LCBANK1 ; LC RAM Rd/Wt, 1st 4K bank
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LDA LCBANK1
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LDY #$00 ; $02=Soft Reset
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:MODBRA BRA :RELOC ; NOPped out on first run
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BRA :NORELOC
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:RELOC LDA #<AUXMOS1 ; Relocate MOS shim
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STA A1L
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LDA #>AUXMOS1
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STA A1H
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LDA #<EAUXMOS1
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STA A2L
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LDA #>EAUXMOS1
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STA A2H
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LDA #<AUXMOS
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STA A4L
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LDA #>AUXMOS
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STA A4H
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:L1 LDA (A1L)
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STA (A4L)
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LDA A1H
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CMP A2H
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BNE :S1
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LDA A1L
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CMP A2L
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BNE :S1
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BRA :S4
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:S1 INC A1L
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BNE :S2
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INC A1H
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:S2 INC A4L
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BNE :S3
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INC A4H
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:S3 BRA :L1
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:S4 LDA #<MOSVEC-MOSINIT+AUXMOS1
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STA A1L
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LDA #>MOSVEC-MOSINIT+AUXMOS1
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STA A1H
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LDA #<MOSVEND-MOSINIT+AUXMOS1
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STA A2L
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LDA #>MOSVEND-MOSINIT+AUXMOS1
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STA A2H
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LDA #<MOSAPI
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STA A4L
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LDA #>MOSAPI
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STA A4H
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:L2 LDA (A1L)
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STA (A4L)
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LDA A1H
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CMP A2H
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BNE :S5
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LDA A1L
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CMP A2L
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BNE :S5
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BRA :S8
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:S5 INC A1L
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BNE :S6
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INC A1H
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:S6 INC A4L
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BNE :S7
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INC A4H
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:S7 BRA :L2
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:S8
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LDA #$EA ; NOP opcode
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STA :MODBRA+0 ; Next time around, we're already
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STA :MODBRA+1 ; in high memory
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LDY #$02 ; $02=PowerOn
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:NORELOC STA SET80VID ; 80 col on
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STA CLRALTCHAR ; Alt charset off
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STA PAGE2 ; PAGE2
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JMP MOSHIGH ; Ensure executing in high memory from here
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* From here onwards we are always executing at $D000 onwards
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* Y=ResetType
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MOSHIGH SEI ; Ensure IRQs disabled
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LDX #$FF
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TXS ; Initialise stack
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INX ; X=$00
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TXA
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:SCLR STA $0000,X ; Clear Kernel memory
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STA $0200,X
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STA $0300,X
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INX
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BNE :SCLR
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STY BYTEVARBASE+$FD ; Set ResetType
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LDX #ENDVEC-DEFVEC-1
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:INITPG2 LDA DEFVEC,X ; Set up vectors
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STA $200,X
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DEX
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BPL :INITPG2
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LDA CYAREG ; GS speed register
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AND #$80 ; Speed bit only
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STA GSSPEED ; In Alt LC for IRQ/BRK hdlr
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JSR ROMINIT ; Build list of sideways ROMs
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JSR KBDINIT ; Returns A=startup MODE
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JSR VDUINIT ; Initialise VDU driver
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JSR PRHELLO
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LDA BYTEVARBASE+$FD ; Get ResetType
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BEQ :INITSOFT
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LDA #7 ; Beep on HardReset
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JSR OSWRCH
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* AppleII MOS beeps anyway, so always get a Beep
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* BRUN APPLECORN -> BBC Beep
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* Ctrl-Reset -> AppleII Beep
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*
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:INITSOFT JSR OSNEWL
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LDX MAXROM ; *TEMP* X=language to enter
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* TO DO: SoftReset->Use CURRLANG, HardReset->Search for language
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*
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CLC ; CLC=Entering from RESET
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* OSBYTE $8E - Enter language ROM
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*********************************
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* X=ROM number to select, CC=RESET, CS=*COMMAND/OSBYTE
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*
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BYTE8E PHP ; Save CLC=RESET, SEC=Not RESET
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JSR ROMSELECT ; Bring ROM X into memory
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LDA #$00
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STA FAULT+0
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LDA #$80
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STA FAULT+1
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LDY #$09
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JSR PRERRLP ; Print ROM name with PRERR to set
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STY FAULT+0 ; FAULT pointing to version string
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JSR OSNEWL
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JSR OSNEWL
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STX BYTEVARBASE+$FC ; Set current language ROM
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PLP ; Get entry type back
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LDA #$01 ; $01=Entering code with a header
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JMP ROMAUXADDR
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* OSBYTE $8F - Issue service call
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*********************************
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* X=service call, Y=parameter
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*
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* SERVICE TAX ; Enter here with A=Service Num
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BYTE8F
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SERVICEX LDA $F4 ; Enter here with X=Service Number
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PHA ; Save current ROM
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*DEBUG
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LDA $E0
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AND #$20 ; Test debug *OPT255,32
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BEQ :SERVDEBUG
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CPX #$06
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BEQ :SERVDONE ; If debug on, ignore SERV06
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:SERVDEBUG
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*DEBUG
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TXA ; A=service number
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LDX MAXROM ; Start at highest ROM
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:SERVLP JSR ROMSELECT ; Bring it into memory
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BIT $8006
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BPL :SERVSKIP ; No service entry
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JSR $8003 ; Call service entry
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TAX
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BEQ :SERVDONE
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:SERVSKIP LDX $F4 ; Restore X=current ROM
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DEX ; Step down to next
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BPL :SERVLP ; Loop until ROM 0 done
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:SERVDONE PLA ; Get caller's ROM back
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PHX ; Save return from service call
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TAX
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JSR ROMSELECT ; Restore caller's ROM
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PLX ; Get return value back
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TXA ; Return in A and X and set EQ/NE
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RTS
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PRHELLO LDX #<HELLO
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LDY #>HELLO
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JSR OSPRSTR
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JMP OSNEWL
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BYTE00 BEQ BYTE00A ; OSBYTE 0,0 - generate error
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LDX #$0A ; Identify Host
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RTS ; %000x1xxx host type, 'A'pple
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BYTE00A BRK
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DB $F7
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HELLO ASC 'Applecorn MOS 2022-11-04'
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DB $00 ; Unify MOS messages
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* TO DO: Move into RAM
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GSSPEED DB $00 ; $80 if GS is fast, $00 for slow
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