221 lines
3.5 KiB
ArmAsm
221 lines
3.5 KiB
ArmAsm
.syntax unified
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.cpu cortex-m0
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.align 2
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.thumb
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.thumb_func
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.extern basic_rom
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.extern uart_putd
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.section .rodata
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dump0:
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.ascii "*** dump *** PC=$\000"
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dump1:
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.ascii " A=$\000"
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dump2:
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.ascii " X=$\000"
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dump3:
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.ascii " Y=$\000"
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dump4:
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.ascii " SP=$\000"
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dump5:
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.ascii " NV-B_DIZC=\000"
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ascii:
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.ascii "@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_ !\"#$%&'()*+,-./0123456789:;<=>?"
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.text
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.global cpu6502_dump
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.type cpu6502_dump, %function
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cpu6502_dump:
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push {r4-r7, lr}
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mov r4, r0
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mov r5, r1
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mov r6, r2
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mov r7, r3
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ldr r0, =#dump0
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bl uart_putstr
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mov r0, r4
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bl uart_puthex16
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ldr r0, =#dump1
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bl uart_putstr
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mov r0, r5
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bl uart_puthex
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ldr r0, =#dump2
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bl uart_putstr
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mov r0, r6
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bl uart_puthex
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ldr r0, =#dump3
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bl uart_putstr
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mov r0, r7
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bl uart_puthex
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ldr r0, =#dump4
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bl uart_putstr
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ldr r0, [sp, #20]
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bl uart_puthex
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ldr r0, =#dump5
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bl uart_putstr
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ldr r4, [sp, #24]
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mov r0, r4
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lsrs r0, #7
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bl uart_putx
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mov r0, r4
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movs r5, #1
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lsrs r0, #6
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ands r0, r5
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bl uart_putx
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movs r0, #'-'
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bl uart_putc
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mov r0, r4
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lsrs r0, #4
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ands r0, r5
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bl uart_putx
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movs r0, #'_'
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bl uart_putc
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mov r0, r4
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lsrs r0, #3
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ands r0, r5
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bl uart_putx
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mov r0, r4
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lsrs r0, #2
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ands r0, r5
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bl uart_putx
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mov r0, r4
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lsrs r0, #1
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ands r0, r5
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bl uart_putx
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mov r0, r4
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ands r0, r5
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bl uart_putx
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movs r0, #'\n'
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bl uart_putc
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pop {r4-r7, pc}
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.global cpu6502_load
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.type cpu6502_load, %function
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cpu6502_load:
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movs r2, r0
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lsrs r0, #8
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cmp r0, #0xd0
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bhs 1f
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cmp r0, #0x04
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blo 2f
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cmp r0, #0x08
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blo 3f
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cmp r0, #0xc0
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bhs 4f
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// Load from Fake RAM (0x0800-0xbfff)
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ldr r0, =#ramfake
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ldrb r0, [r0]
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mov pc, lr
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1:
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// Load from ROM (0xd000-0xffff)
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movs r0, #0xd0
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lsls r0, #8
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subs r2, r2, r0
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ldr r0, =#basic_rom
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adds r0, r0, r2
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ldrb r0, [r0]
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mov pc, lr
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2:
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// Load from RAM (0x0000-0x03ff)
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ldr r0, =#ram0000
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adds r0, r0, r2
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ldrb r0, [r0]
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mov pc, lr
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3:
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// Load from VRAM (0x0400-0x07ff)
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movs r0, #0xff
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mov pc, lr
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4:
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// Load from I/O (0xc000-0xcfff)
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movs r0, #0
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mov pc, lr
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.global cpu6502_store
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.type cpu6502_store, %function
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cpu6502_store:
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movs r2, r0
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lsrs r0, #8
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cmp r0, #0xd0
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bhs 1f
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cmp r0, #0x04
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blo 2f
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cmp r0, #0x08
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blo 3f
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cmp r0, #0xc0
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bhs 4f
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// Store to Fake RAM (0x0800-0xbfff)
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ldr r0, =#ramfake
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strb r1, [r0]
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mov pc, lr
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1:
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// Store to ROM (0xd000-0xffff)
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mov pc, lr
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2:
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// Store to RAM (0x0000-0x0400)
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ldr r0, =#ram0000
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adds r0, r0, r2
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strb r1, [r0]
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mov pc, lr
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3:
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// Store to VRAM (0x0400-0x07ff)
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cmp r1, #0x7f
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bne 1f
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mov pc, lr
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1:
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push {lr}
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push {r1-r2}
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movs r0, #0x1b
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bl uart_putc
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movs r0, #'['
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bl uart_putc
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pop {r1-r2}
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movs r3, #0x04
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lsls r3, r3, #8
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subs r3, r2, r3
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movs r2, r3
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movs r0, #0x7f
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ands r2, r2, r0
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lsrs r3, r3, #7
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cmp r2, #0x50
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blo 1f
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subs r2, r2, #0x50
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adds r3, r3, #0x10
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1:
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cmp r2, #0x28
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blo 1f
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subs r2, r2, #0x28
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adds r3, r3, #0x08
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1:
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mov r0, r3
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adds r0, r0, #1
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push {r1-r2}
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bl uart_putd
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movs r0, #';'
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bl uart_putc
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pop {r1-r2}
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mov r0, r2
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adds r0, r0, #1
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push {r1}
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bl uart_putd
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movs r0, #'H'
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bl uart_putc
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pop {r1}
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ldr r2, =#ascii
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movs r3, #0x3f
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ands r3, r1, r3
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adds r3, r3, r2
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ldrb r0, [r3]
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bl uart_putc
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pop {pc}
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4:
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// Load from I/O (0xc000-0xcfff)
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movs r0, #0
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mov pc, lr
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.bss
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ram0000:
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.skip 0x400
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ramfake:
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.byte 0
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