mirror of https://github.com/callapple/LLUCE.git
156 lines
3.3 KiB
ArmAsm
156 lines
3.3 KiB
ArmAsm
LST OFF
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TR
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TR ADR
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*-------------------------------
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* //c System Clock - 24 hr
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*-------------------------------
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* Revised Date: 08/02/87
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*-------------------------------
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rel
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dsk rel/iicsys
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lnbuf equ $200
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ZBUF EQU $41
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PTR EQU $42
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stat1 equ $c099
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comm1 equ $c09a
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stat2 equ $c0a9
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comm2 equ $c0aa
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bytcnt equ $0e03
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nullptr equ $0a
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iicsys ent
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org $0a00
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*-------------------------------
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slot hex 20
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jmp getdate
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jmp gettime
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jmp setdate
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; get the date in prodos/gbbs format
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getdate jsr $bf00 ; read date from MLI
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hex 82
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hex 0000
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ldx $bf90
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lda $bf91
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setdate rts
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; get the current time
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gettime jsr rdclock ; read the clock
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lda #':'
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sta timestr+2 ; put time dividers in
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sta timestr+5
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ldx #<timestr ; point to string
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lda #>timestr
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rts
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; read the date time from clock
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rdclock lda slot
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cmp #$10
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beq init1
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lda #<stat2 ; set status port to slot 2
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sta init3_2+1
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lda #<comm2 ; set comm port to slot 2
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sta init1_3+1
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sta init2+1
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sta init3_3+1
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init1 lda #64
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init1_1 pha
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init1_2 sbc #1
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bne init1_2
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pla
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sbc #1 ; give plenty of setup delay
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bne init1_1
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php
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sei
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init1_3 lda comm1 ; get current setting
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pha
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ldy #3
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ldx #22
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lda #8
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init2 sta comm1 ; send init sequence to clock
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init2_1 dex ; intra-bit delay
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bne init2_1
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eor #$a ; toggle back and forth
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ldx #11
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dey
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bne init2 ; keep looping
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ldy #4
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ldx #8
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bne init3_2 ; skip initial delay
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init3 lda #$34
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sta timer ; delay while clock sets up
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init3_1 dec timer ; to send the date/time
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bne init3_1
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init3_2 lda stat1 ; shift bit data into nibble
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rol
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rol
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rol
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ror datestr
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dex
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bne init3 ; go back to delay
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lda datestr
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eor #0 ; save the nibble
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sta datestr,y
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ldx #8
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dey
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bpl init3
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pla
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init3_3 sta comm1 ; retore uart to initial settings
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ldy #15
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ldx #4
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init4 lda datestr,x
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pha
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and #$f ; process digit (make into ascii)
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ora #$30
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sta datestr,y
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dey
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pla
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lsr
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lsr
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lsr ; process top of nibble
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lsr
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ora #$30 ; turn into ascii
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sta datestr,y
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dey
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dey
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dex
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bpl init4
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plp
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rts
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timer hex 00
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datestr asc '00 00 00'
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timestr asc '00:00:00 '
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date hex 0000
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