mirror of
https://github.com/rigreco/Runge-Kutta-Simulation.git
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115 lines
2.8 KiB
Plaintext
115 lines
2.8 KiB
Plaintext
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# ---------------------------------------------------------------------
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# makefile by bill buckels 2007
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# ---------------------------------------------------------------------
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rcrk.sys: rcrk.r mainm.r ov1.r ov2.r ov2f.r ov3.r outf.r ginit.r saveg.r p8file.r dcmotor.r outdc.r indc.r
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LN65 -t -r +s +h 4000,6004 rcrk.R +C 2800 +D 400 ovld.r samain.r -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del rcrk.R
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MAKEPRO rcrk
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del rcrk
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@echo rcrk.SYS now created!
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LN65 -t mainm.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del mainm.R
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@echo mainm.OVR now created!
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LN65 -t OV1.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del OV1.R
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@echo OV1.OVR now created!
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LN65 -t OV2.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del OV2.R
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@echo OV2.OVR now created!
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LN65 -t OV2f.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del OV2f.R
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@echo OV2f.OVR now created!
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LN65 -t OV3.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del OV3.R
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@echo OV3.OVR now created!
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LN65 -t outf.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del outf.R
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@echo outf.OVR now created!
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LN65 -t ginit.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del ginit.R
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@echo ginit.OVR now created!
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LN65 -t saveg.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del saveg.R
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@echo saveg.OVR now created!
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LN65 -t p8file.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del p8file.R
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@echo p8file.OVR now created!
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LN65 -t dcmotor.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del dcmotor.R
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@echo dcmotor.OVR now created!
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LN65 -t outdc.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del outdc.R
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@echo outdc.OVR now created!
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LN65 -t indc.R ovbgn.r rcrk.RSM -lSYSIO -lg2 -lm -ls -lc -lSYSIO -lg2 -lm -ls -lc
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del indc.R
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@echo indc.OVR now created!
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del rcrk.RSM
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del rcrk.SYM
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del mainm.SYM
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del OV1.SYM
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del OV2.SYM
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del OV2f.SYM
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del OV3.SYM
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del outf.SYM
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del ginit.SYM
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del saveg.sym
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del p8file.sym
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del dcmotor.sym
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del outdc.sym
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del indc.sym
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rcrk.r: rcrk.c
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c65 rcrk.c
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mainm.r: mainm.c
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c65 mainm.c
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ov1.r: ov1.c
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c65 ov1.c
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ov2.r: ov2.c
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c65 ov2.c
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ov2f.r: ov2f.c
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c65 ov2f.c
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ov3.r: ov3.c
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c65 ov3.c
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outf.r: outf.c
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c65 outf.c
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ginit.r: ginit.c
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c65 ginit.c
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saveg.r: saveg.c
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c65 saveg.c
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p8file.r: p8file.c
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c65 p8file.c
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dcmotor.r: dcmotor.c
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c65 dcmotor.c
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outdc.r: outdc.c
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c65 outdc.c
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indc.r: indc.c
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c65 indc.c
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