+prerr$0009;; E0009: We wrote $44 to main RAM in the three test locations used by the LC test. They should have been unaffected by the LC test while it was using auxmem, but at least one of them was modified.
;;; Main data-driven test. PCL,PCH holds the address of the next
;;; data-driven test routine. We expect the various softswitches
;;; to be reset each time we loop at .ddloop.
.datadriventests
lda#<.auxtests
staPCL
lda#>.auxtests
staPCH
;;; Main data-drive-test loop.
.ddloop
ldy#0
lda(PCL),Y
beq.success
lda#3
staSET_ALTZP
staSET_RAMWRT
staSET_RAMRD
.initloop; Loop twice: initialize aux to $3 and main to $1.
ldy#.memorylen
-ldx.memorylocs,y
stx++1
ldx.memorylocs+1,y
stx++2
+sta$ffff;; this address gets replaced
dey
dey
bpl-
staRESET_ALTZP
staRESET_RAMWRT
staRESET_RAMRD
sec
sbc#2
bcs.initloop
jmp(PCL); Jump to test routine.
;; Test routine will JSR back to here, so the check data address is on the stack.
;; .checkdata (tmp1/tmp2) is the pointer to the current checkdata byte
;; .ismain (tmp3) is the main/aux loop counter.
;; .region (tmp4) is the zp/main/text/hires loop counter
.check
;; Increment all the test memory locations, so we can see what we were reading and writing.
inc$ff
inc$100
inc$200
inc$3ff
inc$427
inc$7ff
inc$800
inc$1fff
inc$2000
inc$3fff
inc$4000
inc$5fff
inc$bfff
;; pull address off of stack: it points just below check data for this test.
pla
sta.checkdata
pla
sta.checkdata+1
;; First checkdata byte is for Cxxx tests.
jsr.nextcheck
jsr.checkCxxx
ldx.checkdata
ldy.checkdata+1
jsrRESETALL
stx.checkdata
sty.checkdata+1
;; Do the next part twice.
lda#1
sta.ismain
jsr.nextcheck
.checkloop; Loop twice here: once for main, once for aux.
lda#4
sta.region
ldx#$fe
ldy#0
.memlpinx
inx
lda.memorylocs,x
staSRC
lda.memorylocs+1,x
staSRC+1
oraSRC
beq.memlpinc
;; Perform the actual memory check.
lda(SRC),y
cmp(.checkdata),y
bne.checkerr
beq.memlp
.memlpinc
jsr.nextcheck
dec.region; loop four times: zero, main, text, hires
bne.memlp
dec.ismain
bmi.checkdone
ldx.checkdata
ldy.checkdata+1
lda.ismain
staSET_ALTZP
staSET_RAMRD
staSET_RAMWRT
stx.checkdata
sty.checkdata+1
sta.ismain
jmp.checkloop
.checkdone
;; Jump PCL,PCH to next test, and loop.
ldx.checkdata
ldy.checkdata+1
jsrRESETALL
stxPCL
styPCH
jmp.ddloop
.checkerr
;; X = index of memory location
;; A = actual
;; Y = 0
;; desired = (.checkdata),y
pha
lda.ismain
clc
ror
ror
ora(.checkdata),y
tay
pla
;; Now:
;; X = index of memory location
;; A = actual
;; Y = desired | (high bit set if main, unset=aux)
jsrRESETALL
sta.actual
sty.desired
lda.memorylocs,x
staSRC
lda.memorylocs+1,x
staSRC+1
+print
!text"GOT $"
+printed
lda.actual
jsrPRBYTE
+print
!text" AT $"
+printed
ldxSRC
ldySRC+1
jsrPRNTYX
lda.desired
bpl+
eor#$80
sta.desired
+print
!text" OF MAIN MEM (WANT $"
+printed
beq++
++print
!text" OF AUX MEM (WANT $"
+printed
++
lda.desired
jsrPRBYTE
lda#')'
jsrCOUT
lda#$8D
jsrCOUT
jsr.printtest
+prerr$000A;; E000A: This is a data-driven test of main and auxiliary memory softswitch operation. We initialize $FF, $100, $200, $3FF, $427, $7FF, $800, $1FFF, $2000, $3FFF, $4000, $5FFF, and $BFFF in main RAM to value 1, and in auxiliary RAM to value 3. Then, we perform a testdata-driven sequence of instructions. Finally we (try to) increment all test locations. Then we test the expected values of the test locations in main and auxiliary memory. For more information on the operation of the auxiliary memory soft-switches, see Understanding the Apple IIe, by James Fielding Sather, Pg 5-22 to 5-28.
!text"FOLLOWED BY INC OF TEST LOCATIONS. SEE"
+prerred
sec
rts
;;; Check that the expected ROM areas are visible.
.checkCxxx
rts
;;; Increment .checkdata pointer to the next memory location, and load
;;; it into the accumulator. X and Y are preserved.