a2audit/audit/notes.org

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2016-12-14 02:26:18 +00:00
* Common bytes in FP and INT D0 ROMS
D17B 53
D1B3 54
D267 54
D273 54
D307 20
D32A 20
D337 20
D347 20
D51C 00
D57C F0
D665 20
D667 D6
D694 85
D69B FF
D6DC B1
D6F7 84
D729 4C
D72B D7
D747 F0
D74B D7
D768 85
D76E 65
* TODOs and Links to things to test
2016-12-15 01:16:55 +00:00
** TODO [[https://groups.google.com/d/msg/comp.sys.apple2/RMnus8p6xp8/TDfD2HVtDwAJ][csa2: question on HGR behavior with enhanced 128K Apple //e]]
** TODO Check whether c8-cf sticks after reading c3xx but c3 is only active due to the whole c3 ROM switch
2016-12-18 01:49:28 +00:00
* Language card operation
| Bank 2 | Bank 1 | | Action | RAM | Alt Bank 2 | Alt Bank 1 |
|--------+--------+-----+------------+--------------+------------+------------|
| C080 | C088 | R/W | WRTCOUNT=0 | READ ENABLE | C084 | C08C |
| C081 | C089 | R | WRTCOUNT++ | READ DISABLE | C085 | C08D |
| | | W | WRTCOUNT=0 | READ DISABLE | | |
| C082 | C08A | R/W | WRTCOUNT=0 | READ DISABLE | C086 | C08E |
| C083 | C08B | R | WRTCOUNT++ | READ ENABLE | C087 | C08F |
| | | W | WRTCOUNT=0 | READ ENABLE | | |
Writing to high RAM is enabled when WRTCOUNT >= 2
Source: UtA2e, pg 5-24.
* Floating bus notes
17030 cycles for repeat: 2*5*13*131
UtAIIe: 5-40: Reading video data from a program
UtAII: 3-16: Switching screen modes in timed loops
My plan:
- A. Check that the floating bus works at all
- B. Save the address at each tick
- Write the screen full of the lower byte of its address (0x00 -> 0xFF, so we can use 0 for timing)
- Synch to a run of zeros, then delay to 000000000 counter.
- Read 17030 values in a fixed-cycle, prime-relative-to-17030 cycles loop, and write to RAM
- Write the screen full of the upper byte of its address (+ 0x80 if the lower byte is 0, so we can check 0x00->0xFF bytes)
- Read the upper bytes
- Check that they all match - should be able to add cycle count, then mod 17030 to find actual cycle number.
17030 * 2 = 34060 (0x850C)
If we end at 0xC000, we have to start at 0x3af4.
Perhaps we do lower bytes first, then upper? Then we can start at 0x7d7a
* Printing disassembly notes
$3A - PCL
$3B - PCH
Call PCADJ to update with length of currently-pointed-to instruction, then save A to PCL, Y to PCH.
Disassemble an instruction:
FE5E (LIST): Set counter to 20, call disassembler 20 times:
FE5E: 20 75 FE 920 LIST JSR A1PC ;MOVE A1 (2 BYTES) TO
FE61: A9 14 921 LDA #$14 ; PC IF SPEC'D AND
FE63: 48 922 LIST2 PHA ; DISEMBLE 20 INSTRS
FE64: 20 D0 F8 923 JSR INSTDSP
FE67: 20 53 F9 924 JSR PCADJ ;ADJUST PC EACH INSTR
FE6A: 85 3A 925 STA PCL
FE6C: 84 3B 926 STY PCH
FE6E: 68 927 PLA
FE6F: 38 928 SEC
FE70: E9 01 929 SBC #$01 ;NEXT OF 20 INSTRS
FE72: D0 EF 930 BNE LIST2
FE74: 60 931 RTS
FE75: 8A 932 A1PC TXA ;IF USER SPEC'D ADR
FE76: F0 07 933 BEQ A1PCRTS ; COPY FROM A1 TO PC
FE78: B5 3C 934 A1PCLP LDA A1L,X
FE7A: 95 3A 935 STA PCL,X
FE7C: CA 936 DEX
FE7D: 10 F9 937 BPL A1PCLP
FE7F: 60 938 A1PCRTS RTS
F8D0: 20 82 F8 225 INSTDSP JSR INSDS1 ;GEN FMT, LEN BYTES
F8D3: 48 226 PHA ;SAVE MNEMONIC TABLE INDEX
F8D4: B1 3A 227 PRNTOP LDA (PCL),Y
F8D6: 20 DA FD 228 JSR PRBYTE
F8D9: A2 01 229 LDX #$01 ;PRINT 2 BLANKS {ACTUALLY JUST 1}
F8DB: 20 4A F9 230 PRNTBL JSR PRBL2
F8DE: C4 2F 231 CPY LENGTH ;PRINT INST (1-3 BYTES)
F8E0: C8 232 INY ;IN A 12 CHR FIELD
F8E1: 90 F1 233 BCC PRNTOP
F8E3: A2 03 234 LDX #$03 ;CHAR COUNT FOR MNEMONIC PRINT
F8E5: C0 04 235 CPY #$04
F8E7: 90 F2 236 BCC PRNTBL
F8E9: 68 237 PLA ;RECOVER MNEMONIC INDEX
F8EA: A8 238 TAY
F8EB: B9 C0 F9 239 LDA MNEML,Y
F8EE: 85 2C 240 STA LMNEM ;FETCH 3-CHAR MNEMONIC
F8F0: B9 00 FA 241 LDA MNEMR,Y ; (PACKED IN 2-BYTES)
F8F3: 85 2D 242 STA RMNEM
...
...
F882: A6 3A 180 INSDS1 LDX PCL ;PRINT PCL,H {PRECEDED BY CR, FOLLOWED BY '-'}
F884: A4 3B 181 LDY PCH
F886: 20 96 FD 182 JSR PRYX2
F889: 20 48 F9 183 JSR PRBLNK ;FOLLOWED BY A BLANK {3 SPACES, FINISH WITH X=0}
F88C: A1 3A 184 LDA (PCL,X) ;GET OP CODE
F88E: A8 185 INSDS2 TAY
...
...
300: LDA #0
STA PCL
LDA #3
STA PCH
LDX #0
LDA (PCL,X)
PHA
2017-01-23 02:26:47 +00:00
JSR F88E (INSDS2)
LDX #3
JSR F8EA
JSR F953
STA PCL
STY PCH
RTS
* Auxmem tests
0000-01ff Zero
0200-03ff Main
0400-07ff Text
0800-1fff Main
2000-3fff Hires
4000-bfff Main
2017-01-20 03:28:04 +00:00
Plan:
Each test is a set of actual instructions, followed by a jsr, and a list of memory check data.
Keep test locations in PCL,PCH.
Check data:
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- zero/main/text/hires main mem
- zero/main/text/hires aux mem
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- zero page current/main/aux: $ff, $100
- main current/main/aux: $200, $3ff, $800, $1fff, $4000, $5fff, $bfff
- text: $400, $7ff
- hires: $2000, $3fff
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- CXXX ROM: 1=c300-c3ff, 2=c100-c2ff+c400-c7ff, 4=c800-cffe
2017-01-20 03:28:04 +00:00
For each test:
- Test location is in PCL,PCH.
- JMP to the start of the test (we know where we're coming back to)
- end of test jsr's to CHECK
- CHECK:
- try to increment all memory locations
- pull address off the stack, so it knows where the check data is
- compare with check data
- if we get a problem:
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X=index of memory address in a table, Y=desired | high-bit-set=main/unset=aux, A=actual
2017-01-20 03:28:04 +00:00
JMP to error routine:
- restore normal memory configuration
- save xya
- disassemble from PCL,PCH to JMP instruction
- print out memory address, current/main/aux, desired, actual
- quit test
- check rom
- if we see a problem:
Y = index of memory location
X = ROM-value
A = actual
X==A if we wanted RAM
JMP to error routine 2
- restore normal memory configuration
- save xya,carry
- disassemble from PCL,PCH to JMP instruction
- want ROM?
- yes: print out memory address, desired, actual
- no: print out memory address, non-desired value
- quit test
- increment PCL,PCH past check data
- if it's pointing at a JMP, we're done.
- otherwise, loop
* Softswitch tests
Just switch them on and off, and test each, one at a time.
2017-01-23 02:26:47 +00:00
* Auxmem with mame
On entry into AUXMEMTESTS
SP: 01FE
returned to 02A0
2017-01-27 02:46:38 +00:00
* 80 column details
Lores80 color differences: UtA2e: 8-29
* apple2e.rom
4000-40ff is zeros. I believe this corresponds to C000-C0ff