2016-12-14 02:26:18 +00:00
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* Common bytes in FP and INT D0 ROMS
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D17B 53
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D1B3 54
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D267 54
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D273 54
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D307 20
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D32A 20
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D337 20
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D347 20
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D51C 00
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D57C F0
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D665 20
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D667 D6
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D694 85
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D69B FF
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D6DC B1
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D6F7 84
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D729 4C
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D72B D7
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D747 F0
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D74B D7
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D768 85
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D76E 65
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2016-12-15 01:16:55 +00:00
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* Links to things to test
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** TODO [[https://groups.google.com/d/msg/comp.sys.apple2/RMnus8p6xp8/TDfD2HVtDwAJ][csa2: question on HGR behavior with enhanced 128K Apple //e]]
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2016-12-18 01:49:28 +00:00
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* Language card operation
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| Bank 2 | Bank 1 | | Action | RAM | Alt Bank 2 | Alt Bank 1 |
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|--------+--------+-----+------------+--------------+------------+------------|
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| C080 | C088 | R/W | WRTCOUNT=0 | READ ENABLE | C084 | C08C |
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| C081 | C089 | R | WRTCOUNT++ | READ DISABLE | C085 | C08D |
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| | | W | WRTCOUNT=0 | READ DISABLE | | |
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| C082 | C08A | R/W | WRTCOUNT=0 | READ DISABLE | C086 | C08E |
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| C083 | C08B | R | WRTCOUNT++ | READ ENABLE | C087 | C08F |
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| | | W | WRTCOUNT=0 | READ ENABLE | | |
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Writing to high RAM is enabled when WRTCOUNT >= 2
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Source: UtA2e, pg 5-24.
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2017-01-17 03:45:29 +00:00
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* Floating bus notes
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17030 cycles for repeat: 2*5*13*131
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UtAIIe: 5-40: Reading video data from a program
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UtAII: 3-16: Switching screen modes in timed loops
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My plan:
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- A. Check that the floating bus works at all
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- B. Save the address at each tick
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- Write the screen full of the lower byte of its address (0x00 -> 0xFF, so we can use 0 for timing)
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- Synch to a run of zeros, then delay to 000000000 counter.
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- Read 17030 values in a fixed-cycle, prime-relative-to-17030 cycles loop, and write to RAM
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- Write the screen full of the upper byte of its address (+ 0x80 if the lower byte is 0, so we can check 0x00->0xFF bytes)
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- Read the upper bytes
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- Check that they all match - should be able to add cycle count, then mod 17030 to find actual cycle number.
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17030 * 2 = 34060 (0x850C)
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If we end at 0xC000, we have to start at 0x3af4.
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Perhaps we do lower bytes first, then upper? Then we can start at 0x7d7a
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* Printing disassembly notes
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$3A - PCL
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$3B - PCH
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Call PCADJ to update with length of currently-pointed-to instruction, then save A to PCL, Y to PCH.
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Disassemble an instruction:
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FE5E (LIST): Set counter to 20, call disassembler 20 times:
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FE5E: 20 75 FE 920 LIST JSR A1PC ;MOVE A1 (2 BYTES) TO
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FE61: A9 14 921 LDA #$14 ; PC IF SPEC'D AND
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FE63: 48 922 LIST2 PHA ; DISEMBLE 20 INSTRS
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FE64: 20 D0 F8 923 JSR INSTDSP
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FE67: 20 53 F9 924 JSR PCADJ ;ADJUST PC EACH INSTR
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FE6A: 85 3A 925 STA PCL
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FE6C: 84 3B 926 STY PCH
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FE6E: 68 927 PLA
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FE6F: 38 928 SEC
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FE70: E9 01 929 SBC #$01 ;NEXT OF 20 INSTRS
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FE72: D0 EF 930 BNE LIST2
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FE74: 60 931 RTS
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FE75: 8A 932 A1PC TXA ;IF USER SPEC'D ADR
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FE76: F0 07 933 BEQ A1PCRTS ; COPY FROM A1 TO PC
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FE78: B5 3C 934 A1PCLP LDA A1L,X
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FE7A: 95 3A 935 STA PCL,X
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FE7C: CA 936 DEX
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FE7D: 10 F9 937 BPL A1PCLP
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FE7F: 60 938 A1PCRTS RTS
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F8D0: 20 82 F8 225 INSTDSP JSR INSDS1 ;GEN FMT, LEN BYTES
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F8D3: 48 226 PHA ;SAVE MNEMONIC TABLE INDEX
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F8D4: B1 3A 227 PRNTOP LDA (PCL),Y
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F8D6: 20 DA FD 228 JSR PRBYTE
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F8D9: A2 01 229 LDX #$01 ;PRINT 2 BLANKS {ACTUALLY JUST 1}
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F8DB: 20 4A F9 230 PRNTBL JSR PRBL2
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F8DE: C4 2F 231 CPY LENGTH ;PRINT INST (1-3 BYTES)
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F8E0: C8 232 INY ;IN A 12 CHR FIELD
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F8E1: 90 F1 233 BCC PRNTOP
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F8E3: A2 03 234 LDX #$03 ;CHAR COUNT FOR MNEMONIC PRINT
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F8E5: C0 04 235 CPY #$04
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F8E7: 90 F2 236 BCC PRNTBL
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F8E9: 68 237 PLA ;RECOVER MNEMONIC INDEX
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F8EA: A8 238 TAY
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F8EB: B9 C0 F9 239 LDA MNEML,Y
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F8EE: 85 2C 240 STA LMNEM ;FETCH 3-CHAR MNEMONIC
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F8F0: B9 00 FA 241 LDA MNEMR,Y ; (PACKED IN 2-BYTES)
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F8F3: 85 2D 242 STA RMNEM
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...
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...
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F882: A6 3A 180 INSDS1 LDX PCL ;PRINT PCL,H {PRECEDED BY CR, FOLLOWED BY '-'}
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F884: A4 3B 181 LDY PCH
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F886: 20 96 FD 182 JSR PRYX2
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F889: 20 48 F9 183 JSR PRBLNK ;FOLLOWED BY A BLANK {3 SPACES, FINISH WITH X=0}
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F88C: A1 3A 184 LDA (PCL,X) ;GET OP CODE
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F88E: A8 185 INSDS2 TAY
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...
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...
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300: LDA #0
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STA PCL
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LDA #3
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STA PCH
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LDX #0
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LDA (PCL,X)
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PHA
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JSR F88E
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LDX #3
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JSR F8EA
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JSR F953
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STA PCL
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STY PCH
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PLA
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RTS
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* Auxmem tests
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0000-01ff Zero
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0200-03ff Main
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0400-07ff Text
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0800-1fff Main
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2000-3fff Hires
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4000-bfff Main
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2017-01-20 03:28:04 +00:00
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Plan:
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Each test is a set of actual instructions, followed by a jsr, and a list of memory check data.
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Keep test locations in PCL,PCH.
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Check data:
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- zero page current/main/aux: $ff, $100
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- main current/main/aux: $200, $3ff, $800, $1fff, $4000, $5fff, $bfff
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- text: $400, $7ff
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- hires: $2000, $3fff
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- CXXX ROM: 1=c300-c3ff, 2=c100-c2ff+c400-c7ff, 3=c800-cffe
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For each test:
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- Test location is in PCL,PCH.
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- JMP to the start of the test (we know where we're coming back to)
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- end of test jsr's to CHECK
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- CHECK:
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- try to increment all memory locations
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- pull address off the stack, so it knows where the check data is
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- compare with check data
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- if we get a problem:
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Y=index of memory address in a table, X=desired | current/main/aux, A=actual
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JMP to error routine:
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- restore normal memory configuration
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- save xya
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- disassemble from PCL,PCH to JMP instruction
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- print out memory address, current/main/aux, desired, actual
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- quit test
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- check rom
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- if we see a problem:
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Y = index of memory location
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X = ROM-value
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A = actual
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X==A if we wanted RAM
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JMP to error routine 2
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- restore normal memory configuration
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- save xya,carry
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- disassemble from PCL,PCH to JMP instruction
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- want ROM?
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- yes: print out memory address, desired, actual
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- no: print out memory address, non-desired value
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- quit test
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- increment PCL,PCH past check data
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- if it's pointing at a JMP, we're done.
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- otherwise, loop
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* Softswitch tests
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Just switch them on and off, and test each, one at a time.
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