mirror of
https://github.com/zellyn/a2audit.git
synced 2024-11-28 07:49:26 +00:00
275 lines
4.1 KiB
NASM
275 lines
4.1 KiB
NASM
;;; Apple IIe softswitch-reading tests
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;;; Copyright © 2017 Zellyn Hunter <zellyn@gmail.com>
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!zone softswitch {
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.resetloc = tmp1
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.setloc = tmp3
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.readloc = tmp5
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.loopcount = tmp0
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.switch = SRC
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.testtimes = 8
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SOFTSWITCHTESTS
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lda #1
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sta SOFTSWITCHRESULT
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lda MACHINE
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cmp #4
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bcs +
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+print
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!text "NOT IIE OR IIC:SKIPPING SOFTSWITCH TEST",$8D
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+printed
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sec
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rts
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+ +print
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!text "TESTING SOFTSWITCHES",$8D
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+printed
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;; Test write-softswitches
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lda #<.writeswitches
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sta SRC
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lda #>.writeswitches
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sta SRC+1
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lda #(.readswitches-.writeswitches)/6
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sta .loopcount
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;; Check memory: <= 65K: don't test RAMRD
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lda MEMORY
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cmp #66
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bcs .wrtloop ; Enough memory: continue
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;; Not enough: skip one loop iteration, and increment SRC past RAMRD addresses
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dec .loopcount
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clc
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lda SRC
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adc #6
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sta SRC
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lda SRC+1
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adc #0
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sta SRC+1
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.wrtloop
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;; Copy reset/set/read locations to .resetloc, .setloc, .readloc
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ldy #0
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ldx #0
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- lda (SRC),y
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sta .resetloc,x
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inc SRC
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bne +
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inc SRC+1
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+ inx
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cpx #6
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bne -
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jsr RESETALL
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jsr zptoaux
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;; Initial RESET
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ldy #0
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sta (.resetloc),y
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ldx #.testtimes ; test `.testtimes` times
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- lda (.readloc),y
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bpl + ;ok
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ldx #$80
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jsr RESETALL
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jsr .fail
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beq .wrtloopend
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+ dex
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bne -
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;; Ensure that reading doesn't do anything.
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ldy #0
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lda (.setloc),y
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ldx #.testtimes ; test `.testtimes` times
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- lda (.readloc),y
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bpl + ;ok
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ldx #$42
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jsr RESETALL
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jsr .fail
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beq .wrtloopend
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+ dex
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bne -
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;; Actual SET
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ldy #0
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sta (.setloc),y
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ldx #.testtimes ; test `.testtimes` times
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- lda (.readloc),y
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bmi + ;ok
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ldx #$82
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jsr RESETALL
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jsr .fail
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beq .wrtloopend
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+ dex
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bne -
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;; RESET again
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ldy #0
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sta (.resetloc),y
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ldx #.testtimes ; test `.testtimes` times
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- lda (.readloc),y
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bpl + ;ok
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ldx #$80
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jsr RESETALL
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jsr .fail
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beq .wrtloopend
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+ dex
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bne -
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.wrtloopend
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dec .loopcount
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bne .wrtloop
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lda #(.endswitches-.readswitches)/6
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sta .loopcount
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.readloop
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;; Copy reset/set/read locations to .resetloc, .setloc, .readloc
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ldy #0
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ldx #0
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- lda (SRC),y
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sta .resetloc,x
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inc SRC
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bne +
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inc SRC+1
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+ inx
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cpx #6
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bne -
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jsr RESETALL
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jsr zptoaux
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;; Initial RESET
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ldy #0
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lda (.resetloc),y
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ldx #.testtimes ; test `.testtimes` times
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- lda (.readloc),y
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bpl + ;ok
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ldx #$00
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jsr RESETALL
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jsr .fail
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beq .readloopend
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+ dex
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bne -
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;; Actual SET
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ldy #0
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lda (.setloc),y
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ldx #.testtimes ; test `.testtimes` times
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- lda (.readloc),y
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bmi + ;ok
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ldx #$02
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jsr RESETALL
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jsr .fail
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beq .readloopend
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+ dex
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bne -
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;; RESET again
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ldy #0
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lda (.resetloc),y
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ldx #.testtimes ; test `.testtimes` times
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- lda (.readloc),y
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bpl + ;ok
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ldx #$00
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jsr RESETALL
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jsr .fail
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beq .readloopend
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+ dex
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bne -
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.readloopend
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dec .loopcount
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bne .readloop
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.end
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jsr RESETALL
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lda SOFTSWITCHRESULT
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bne .success
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sec
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rts
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.success
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+print
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!text "SOFTSWITCH TESTS SUCCEEDED",$8D
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+printed
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clc
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rts
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;;; Print failure message.
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;;; High bit of X = write. Low two bits of X: 0 = .resetloc, 2 = .setloc
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;;; A = actual value read (which tells what we expected: the opposite)
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.fail
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sta SCRATCH
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stx SCRATCH2
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txa
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bmi +
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+print
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!text "READ"
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+printed
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beq ++
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+ +print
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!text "WRITE"
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+printed
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++ +print
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!text " AT "
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+printed
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txa
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and #$3
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tax
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ldy .resetloc+1,x
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lda .resetloc,x
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tax
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jsr PRNTYX
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+print
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!text " SHOULD "
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+printed
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lda SCRATCH2
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and #$40
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beq +
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+print
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!text "NOT SET "
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+printed
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beq ++
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+ lda SCRATCH
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bpl +
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+print
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!text "RE"
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+printed
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+ +print
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!text "SET "
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+printed
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++ ldx .readloc
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ldy .readloc+1
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jsr PRNTYX
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+print
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!text ";GOT "
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+printed
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lda SCRATCH
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jsr PRBYTE
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lda #$8D
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jsr COUT
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lda #0
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sta SOFTSWITCHRESULT
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rts
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.writeswitches
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!word RESET_RAMRD, SET_RAMRD, READ_RAMRD
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!word RESET_RAMWRT, SET_RAMWRT, READ_RAMWRT
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!word RESET_80STORE, SET_80STORE, READ_80STORE
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!word RESET_ALTZP, SET_ALTZP, READ_ALTZP
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!word RESET_INTCXROM, SET_INTCXROM, READ_INTCXROM
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!word RESET_SLOTC3ROM, SET_SLOTC3ROM, READ_SLOTC3ROM
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!word RESET_80COL, SET_80COL, READ_80COL
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!word RESET_ALTCHRSET, SET_ALTCHRSET, READ_ALTCHRSET
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.readswitches
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!word RESET_TEXT, SET_TEXT, READ_TEXT
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!word RESET_MIXED, SET_MIXED, READ_MIXED
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!word RESET_PAGE2, SET_PAGE2, READ_PAGE2
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!word RESET_HIRES, SET_HIRES, READ_HIRES
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.endswitches
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} ;softswitch
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