mirror of
https://github.com/zellyn/a2audit.git
synced 2024-11-24 11:31:01 +00:00
351 lines
7.8 KiB
NASM
351 lines
7.8 KiB
NASM
;;; Apple II Language Card audit routines
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;;; Copyright © 2016 Zellyn Hunter <zellyn@gmail.com>
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!zone langcard {
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.checkdata = tmp1
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LANGCARDTESTS
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lda #0
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sta LCRESULT
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lda MEMORY
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cmp #49
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bcs LANGCARDTESTS_NO_CHECK
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+print
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!text "48K:SKIPPING LANGUAGE CARD TEST",$8D
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+printed
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sec
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rts
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LANGCARDTESTS_NO_CHECK:
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+print
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!text "TESTING LANGUAGE CARD",$8D
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+printed
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;; Setup - store differing values in bank first and second banked areas.
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lda $C08B ; Read and write bank 1
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lda $C08B
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lda #$11
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sta $D17B ; $D17B is $53 in Apple II/plus/e/enhanced
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cmp $D17B
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beq +
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+prerr $0004 ;; E0004: We tried to put the language card into read bank 1, write bank 1, but failed to write.
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!text "CANNOT WRITE TO LC BANK 1 RAM"
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+prerred
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sec
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rts
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+ lda #$33
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sta $FE1F ; FE1F is $60 in Apple II/plus/e/enhanced
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cmp $FE1F
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beq +
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+prerr $0005 ;; E0005: We tried to put the language card into read RAM, write RAM, but failed to write.
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!text "CANNOT WRITE TO LC RAM"
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+prerred
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sec
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rts
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+ lda $C083 ; Read and write bank 2
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lda $C083
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lda #$22
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sta $D17B
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cmp $D17B
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beq +
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+prerr $0006 ;; E0006: We tried to put the language card into read bank 2, write bank 2, but failed to write.
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!text "CANNOT WRITE TO LC BANK 2 RAM"
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+prerred
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sec
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rts
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+ lda $C08B ; Read and write bank 1 with single access (only one needed if banked in already)
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lda #$11
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cmp $D17B
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beq +
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+prerr $000D ;; E000D: We tried to put the language card into read bank 1, but failed to read.
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!text "CANNOT READ FROM LC BANK 1 RAM"
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+prerred
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sec
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rts
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+ lda $C081 ; Read ROM with single access (only one needed to bank out)
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lda #$53
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cmp $D17B
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beq .datadriventests
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+prerr $000E ;; E000E: We tried to put the language card into read ROM, but failed to read.
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!text "CANNOT READ FROM ROM"
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+prerred
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sec
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rts
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;;; Main data-driven test. PCL,PCH holds the address of the next
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;;; data-driven test routine. We expect the various softswitches
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;;; to be reset each time we loop at .ddloop.
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.datadriventests
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lda #<.tests
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sta PCL
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lda #>.tests
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sta PCH
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;;; Main data-drive-test loop.
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.ddloop
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ldy #0
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;; Initialize to known state:
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;; - $11 in $D17B bank 1 (ROM: $53)
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;; - $22 in $D17B bank 2 (ROM: $53)
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;; - $33 in $FE1F (ROM: $60)
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lda $C08B ; Read and write bank 1
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lda $C08B
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lda #$11
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sta $D17B
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lda #$33
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sta $FE1F
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lda $C083 ; Read and write bank 2
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lda $C083
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lda #$22
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sta $D17B
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lda $C080
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jmp (PCL) ; Jump to test routine
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;; Test routine will JSR back to here, so the check data address is on the stack.
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.test ;; ... test the quintiple of test values
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inc $D17B
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inc $FE1F
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;; pull address off of stack: it points just below check data for this test.
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pla
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sta .checkdata
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pla
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sta .checkdata+1
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;; .checkdata now points to d17b-current,fe1f-current,bank1,bank2,fe1f-ram test quintiple
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;; Test current $D17B
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jsr NEXTCHECK
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cmp $D17B
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beq +
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lda $D17B
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pha
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jsr .printseq
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+print
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!text "$D17B TO CONTAIN $"
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+printed
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jsr CURCHECK
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jsr PRBYTE
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+print
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!text ", GOT $"
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+printed
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pla
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jsr PRBYTE
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lda #$8D
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jsr COUT
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jmp .datatesturl
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+ ;; Test current $FE1F
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jsr NEXTCHECK
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cmp $FE1F
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beq +
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lda $FE1F
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pha
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jsr .printseq
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+print
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!text "$FE1F=$"
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+printed
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jsr CURCHECK
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jsr PRBYTE
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+print
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!text ", GOT $"
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+printed
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pla
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jsr PRBYTE
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lda #$8D
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jsr COUT
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jmp .datatesturl
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+ ;; Test bank 1 $D17B
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lda $C088
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jsr NEXTCHECK
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cmp $D17B
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beq +
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lda $D17B
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pha
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jsr .printseq
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+print
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!text "$D17B IN RAM BANK 1 TO CONTAIN $"
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+printed
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jsr CURCHECK
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jsr PRBYTE
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+print
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!text ", GOT $"
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+printed
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pla
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jsr PRBYTE
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lda #$8D
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jsr COUT
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jmp .datatesturl
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+ ;; Test bank 2 $D17B
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lda $C080
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jsr NEXTCHECK
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cmp $D17B
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beq +
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lda $D17B
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pha
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jsr .printseq
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+print
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!text "$D17B IN RAM BANK 2 TO CONTAIN $"
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+printed
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jsr CURCHECK
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jsr PRBYTE
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+print
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!text ", GOT $"
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+printed
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pla
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jsr PRBYTE
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lda #$8D
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jsr COUT
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jmp .datatesturl
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+ ;; Test RAM $FE1F
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lda $C080
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jsr NEXTCHECK
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cmp $FE1F
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beq +
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lda $FE1F
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pha
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jsr .printseq
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+print
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!text "RAM $FE1F=$"
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+printed
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jsr CURCHECK
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jsr PRBYTE
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+print
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!text ", GOT $"
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+printed
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pla
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jsr PRBYTE
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lda #$8D
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jsr COUT
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jmp .datatesturl
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+ ;; Jump PCL,PCH up to after the test data, and loop.
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jsr NEXTCHECK
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bne +
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jmp .success
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+ ldx .checkdata
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ldy .checkdata+1
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stx PCL
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sty PCH
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jmp .ddloop
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.datatesturl
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+prerr $0007 ;; E0007: This is a data-driven test of Language Card operation. We initialize $D17B in RAM bank 1 to $11, $D17B in RAM bank 2 to $22, and $FE1F in RAM to $33. Then, we perform a testdata-driven sequence of LDA and STA to the $C08X range. Finally we (try to) increment $D17B and $FE1F. Then we test (a) the current live value in $D17B, (b) the current live value in $FE1F, (c) the RAM bank 1 value of $D17B, (d) the RAM bank 2 value of $D17B, and (e) the RAM value of $FE1F, to see whether they match expected values. $D17B is usually $53 in ROM, and $FE1F is usally $60. For more information on the operation of the language card soft-switches, see Understanding the Apple IIe, by James Fielding Sather, Pg 5-24.
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!text "DATA-DRIVEN TEST FAILED"
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+prerred
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sec
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rts
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.printseq
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+print
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!text "AFTER SEQUENCE OF:",$8D,"- LDA $C080",$8D
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+printed
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jsr PRINTTEST
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+print
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!text "- INC $D17B",$8D,"- INC $FE1F",$8D,"EXPECTED "
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+printed
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rts
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.tests
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;; Format:
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;; Sequence of test instructions, finishing with `jsr .test`.
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;; - quint: expected current $d17b and fe1f, then d17b in bank1, d17b in bank 2, and fe1f
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;; (All sequences start with lda $C080, just to reset things to a known state.)
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;; 0-byte to terminate tests.
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lda $C088 ; Read $C088 (RAM read, write protected)
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jsr .test ;
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!byte $11, $33, $11, $22, $33 ;
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;
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lda $C080 ; Read $C080 (read bank 2, write disabled)
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jsr .test ;
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!byte $22, $33, $11, $22, $33 ;
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;
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lda $C081 ; Read $C081 (ROM read, write disabled)
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jsr .test ;
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!byte $53, $60, $11, $22, $33 ;
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;
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lda $C081 ; Read $C081, $C089 (ROM read, bank 1 write)
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lda $C089 ;
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jsr .test ;
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!byte $53, $60, $54, $22, $61 ;
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;
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lda $C081 ; Read $C081, $C081 (read ROM, write RAM bank 2)
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lda $C081 ;
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jsr .test ;
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!byte $53, $60, $11, $54, $61 ;
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;
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lda $C081 ; Read $C081, $C081, write $C081 (read ROM, write RAM bank bank 2)
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lda $C081 ; See https://github.com/zellyn/a2audit/issues/3
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sta $C081 ;
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jsr .test ;
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!byte $53, $60, $11, $54, $61 ;
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;
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lda $C081 ; Read $C081, $C081; write $C081, $C081
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lda $C081 ; See https://github.com/zellyn/a2audit/issues/4
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sta $C081 ;
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sta $C081 ;
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jsr .test ;
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!byte $53, $60, $11, $54, $61 ;
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;
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lda $C08B ; Read $C08B (read RAM bank 1, no write)
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jsr .test ;
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!byte $11, $33, $11, $22, $33 ;
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;
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lda $C083 ; Read $C083 (read RAM bank 2, no write)
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jsr .test ;
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!byte $22, $33, $11, $22, $33 ;
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;
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lda $C08B ; Read $C08B, $C08B (read/write RAM bank 1)
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lda $C08B ;
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jsr .test ;
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!byte $12, $34, $12, $22, $34 ;
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;
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lda $C08F ; Read $C08F, $C087 (read/write RAM bank 2)
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lda $C087 ;
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jsr .test ;
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!byte $23, $34, $11, $23, $34 ;
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;
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lda $C087 ; Read $C087, read $C08D (read ROM, write bank 1)
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lda $C08D ;
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jsr .test ;
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!byte $53, $60, $54, $22, $61 ;
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;
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lda $C08B ; Read $C08B, write $C08B, read $C08B (read RAM bank 1, no write)
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sta $C08B ; (this one is tricky: reset WRTCOUNT by writing halfway)
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lda $C08B ;
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jsr .test ;
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!byte $11, $33, $11, $22, $33 ;
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;
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sta $C08B ; Write $C08B, write $C08B, read $C08B (read RAM bank 1, no write)
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sta $C08B ;
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lda $C08B ;
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jsr .test ;
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!byte $11, $33, $11, $22, $33 ;
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;
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clc ; Read $C083, $C083 (read/write RAM bank 2)
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ldx #0 ; Uses "6502 false read"
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inc $C083,x ;
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jsr .test ;
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!byte $23, $34, $11, $23, $34 ;
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;
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!byte 0 ; End of tests
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nop ; Provide clean break after data when viewing disassembly
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nop
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.success
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;; Success
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+print
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!text "LANGUAGE CARD TESTS SUCCEEDED",$8D
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+printed
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lda #1
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sta LCRESULT
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clc
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rts
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} ;langcard
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