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176 lines
10 KiB
C
176 lines
10 KiB
C
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/*
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* Copyright (c) 2013, University of Michigan.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-spi cc2538 Synchronous Serial Interface
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*
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* Driver for the cc2538 SPI peripheral
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*
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* Register and bitmask definitions based on the Foundation Firmware from
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* Texas Instruments.
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* @{
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*
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* \file
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* Header file for the cc2538 Synchronous Serial Interface
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*/
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#ifndef SSI_H_
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#define SSI_H_
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/*---------------------------------------------------------------------------*/
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/** \name Base register memory locations.
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* @{
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*/
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#define SSI0_BASE 0x40008000 /**< Base address for SSI0 */
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#define SSI1_BASE 0x40009000 /**< Base address for SSI1 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SSI register offsets
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* @{
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*/
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#define SSI_CR0 0x00000000 /**< Control register 0 */
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#define SSI_CR1 0x00000004 /**< Control register 1 */
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#define SSI_DR 0x00000008 /**< Access the TX and RX FIFO */
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#define SSI_SR 0x0000000C /**< Meta information about FIFO */
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#define SSI_CPSR 0x00000010 /**< Clock divider */
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#define SSI_IM 0x00000014 /**< Interrupt mask */
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#define SSI_RIS 0x00000018 /**< Raw interrupt status */
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#define SSI_MIS 0x0000001C /**< Masked interrupt status */
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#define SSI_ICR 0x00000020 /**< Interrupt clear register */
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#define SSI_DMACTL 0x00000024 /**< DMA control register */
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#define SSI_CC 0x00000FC8 /**< Clock configuration */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SSI Bitmasks and shifts
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* @{
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*/
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#define SSI_CR0_SCR_M 0x0000FF00 /**< Serial clock rate mask */
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#define SSI_CR0_SCR_S 8 /**< Serial clock rate shift */
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#define SSI_CR0_SPH 0x00000080 /**< Serial clock phase (H) */
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#define SSI_CR0_SPH_M 0x00000080 /**< Serial clock phase (H) mask */
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#define SSI_CR0_SPH_S 7 /**< Serial clock phase (H) shift */
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#define SSI_CR0_SPO 0x00000040 /**< Serial clock phase (O) */
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#define SSI_CR0_SPO_M 0x00000040 /**< Serial clock phase (O) mask */
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#define SSI_CR0_SPO_S 6 /**< Serial clock phase (O) shift */
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#define SSI_CR0_FRF_M 0x00000030 /**< Frame format select mask */
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#define SSI_CR0_FRF_S 4 /**< Frame format select shift */
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#define SSI_CR0_DSS_M 0x0000000F /**< Data size select mask */
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#define SSI_CR0_DSS_S 0 /**< Data size select shift */
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#define SSI_CR1_SOD 0x00000008 /**< Slave mode output disable */
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#define SSI_CR1_SOD_M 0x00000008 /**< Slave mode output disable mask */
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#define SSI_CR1_SOD_S 3 /**< Slave mode output disable shift */
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#define SSI_CR1_MS 0x00000004 /**< Master and slave select */
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#define SSI_CR1_MS_M 0x00000004 /**< Master and slave select mask */
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#define SSI_CR1_MS_S 2 /**< Master and slave select shift */
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#define SSI_CR1_SSE 0x00000002 /**< Synchronous serial port enable */
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#define SSI_CR1_SSE_M 0x00000002 /**< Synchronous serial port enable mask */
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#define SSI_CR1_SSE_S 1 /**< Synchronous serial port enable shift */
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#define SSI_CR1_LBM 0x00000001 /**< Loop-back mode */
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#define SSI_CR1_LBM_M 0x00000001 /**< Loop-back mode mask */
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#define SSI_CR1_LBM_S 0 /**< Loop-back mode shift */
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#define SSI_DR_DATA_M 0x0000FFFF /**< FIFO data mask */
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#define SSI_DR_DATA_S 0 /**< FIFO data shift */
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#define SSI_SR_BSY 0x00000010 /**< Busy bit */
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#define SSI_SR_BSY_M 0x00000010 /**< Busy bit mask */
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#define SSI_SR_BSY_S 4 /**< Busy bit shift */
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#define SSI_SR_RFF 0x00000008 /**< Receive FIFO full */
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#define SSI_SR_RFF_M 0x00000008 /**< Receive FIFO full mask */
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#define SSI_SR_RFF_S 3 /**< Receive FIFO full shift */
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#define SSI_SR_RNE 0x00000004 /**< Receive FIFO not empty */
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#define SSI_SR_RNE_M 0x00000004 /**< Receive FIFO not empty mask */
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#define SSI_SR_RNE_S 2 /**< Receive FIFO not empty shift */
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#define SSI_SR_TNF 0x00000002 /**< Transmit FIFO not full */
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#define SSI_SR_TNF_M 0x00000002 /**< Transmit FIFO not full mask */
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#define SSI_SR_TNF_S 1 /**< Transmit FIFO not full shift */
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#define SSI_SR_TFE 0x00000001 /**< Transmit FIFO empty */
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#define SSI_SR_TFE_M 0x00000001 /**< Transmit FIFO empty mask */
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#define SSI_SR_TFE_S 0 /**< Transmit FIFO empty shift */
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#define SSI_CPSR_CPSDVSR_M 0x000000FF /**< Clock prescale divisor mask */
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#define SSI_CPSR_CPSDVSR_S 0 /**< Clock prescale divisor shift */
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#define SSI_IM_TXIM 0x00000008 /**< Transmit FIFO interrupt mask */
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#define SSI_IM_TXIM_M 0x00000008 /**< Transmit FIFO interrupt mask mask */
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#define SSI_IM_TXIM_S 3 /**< Transmit FIFO interrupt mask shift */
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#define SSI_IM_RXIM 0x00000004 /**< Receive FIFO interrupt mask */
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#define SSI_IM_RXIM_M 0x00000004 /**< Receive FIFO interrupt mask mask */
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#define SSI_IM_RXIM_S 2 /**< Receive FIFO interrupt mask shift */
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#define SSI_IM_RTIM 0x00000002 /**< Receive time-out interrupt mask */
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#define SSI_IM_RTIM_M 0x00000002 /**< Receive time-out interrupt mask mask */
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#define SSI_IM_RTIM_S 1 /**< Receive time-out interrupt mask shift */
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#define SSI_IM_RORIM 0x00000001 /**< Receive overrun interrupt mask */
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#define SSI_IM_RORIM_M 0x00000001 /**< Receive overrun interrupt mask mask */
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#define SSI_IM_RORIM_S 0 /**< Receive overrun interrupt mask shift */
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#define SSI_RIS_TXRIS 0x00000008 /**< SSITXINTR raw state */
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#define SSI_RIS_TXRIS_M 0x00000008 /**< SSITXINTR raw state mask */
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#define SSI_RIS_TXRIS_S 3 /**< SSITXINTR raw state shift */
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#define SSI_RIS_RXRIS 0x00000004 /**< SSIRXINTR raw state */
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#define SSI_RIS_RXRIS_M 0x00000004 /**< SSIRXINTR raw state mask */
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#define SSI_RIS_RXRIS_S 2 /**< SSIRXINTR raw state shift */
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#define SSI_RIS_RTRIS 0x00000002 /**< SSIRTINTR raw state */
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#define SSI_RIS_RTRIS_M 0x00000002 /**< SSIRTINTR raw state mask */
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#define SSI_RIS_RTRIS_S 1 /**< SSIRTINTR raw state shift */
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#define SSI_RIS_RORRIS 0x00000001 /**< SSIRORINTR raw state */
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#define SSI_RIS_RORRIS_M 0x00000001 /**< SSIRORINTR raw state mask */
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#define SSI_RIS_RORRIS_S 0 /**< SSIRORINTR raw state shift */
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#define SSI_MIS_TXMIS 0x00000008 /**< SSITXINTR masked state */
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#define SSI_MIS_TXMIS_M 0x00000008 /**< SSITXINTR masked state mask */
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#define SSI_MIS_TXMIS_S 3 /**< SSITXINTR masked state shift */
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#define SSI_MIS_RXMIS 0x00000004 /**< SSIRXINTR masked state */
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#define SSI_MIS_RXMIS_M 0x00000004 /**< SSIRXINTR masked state mask */
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#define SSI_MIS_RXMIS_S 2 /**< SSIRXINTR masked state shift */
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#define SSI_MIS_RTMIS 0x00000002 /**< SSIRTINTR masked state */
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#define SSI_MIS_RTMIS_M 0x00000002 /**< SSIRTINTR masked state mask */
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#define SSI_MIS_RTMIS_S 1 /**< SSIRTINTR masked state shift */
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#define SSI_MIS_RORMIS 0x00000001 /**< SSIRORINTR masked state */
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#define SSI_MIS_RORMIS_M 0x00000001 /**< SSIRORINTR masked state mask */
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#define SSI_MIS_RORMIS_S 0 /**< SSIRORINTR masked state shift */
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#define SSI_ICR_RTIC 0x00000002 /**< Receive time-out interrupt clear */
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#define SSI_ICR_RTIC_M 0x00000002 /**< Receive time-out interrupt clear mask */
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#define SSI_ICR_RTIC_S 1 /**< Receive time-out interrupt clear shift */
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#define SSI_ICR_RORIC 0x00000001 /**< Receive overrun interrupt clear */
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#define SSI_ICR_RORIC_M 0x00000001 /**< Receive overrun interrupt clear mask */
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#define SSI_ICR_RORIC_S 0 /**< Receive overrun interrupt clear shift */
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#define SSI_DMACTL_TXDMAE 0x00000002 /**< Transmit DMA enable */
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#define SSI_DMACTL_TXDMAE_M 0x00000002 /**< Transmit DMA enable mask */
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#define SSI_DMACTL_TXDMAE_S 1 /**< Transmit DMA enable shift */
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#define SSI_DMACTL_RXDMAE 0x00000001 /**< Receive DMA enable */
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#define SSI_DMACTL_RXDMAE_M 0x00000001 /**< Receive DMA enable mask */
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#define SSI_DMACTL_RXDMAE_S 0 /**< Receive DMA enable shift */
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#define SSI_CC_CS_M 0x00000007 /**< Baud and system clock source mask */
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#define SSI_CC_CS_S 0 /**< Baud and system clock source shift */
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/** @} */
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#endif
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/**
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* @}
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* @}
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*/
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