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546 lines
22 KiB
C
546 lines
22 KiB
C
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/**
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******************************************************************************
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* @file stm32l1xx_hal_flash_ramfunc.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 5-September-2014
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* @brief FLASH RAMFUNC driver.
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* This file provides a Flash firmware functions which should be
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* executed from internal SRAM
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*
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* @verbatim
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*** ARM Compiler ***
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--------------------
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[..] RAM functions are defined using the toolchain options.
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Functions that are be executed in RAM should reside in a separate
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source module. Using the 'Options for File' dialog you can simply change
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the 'Code / Const' area of a module to a memory space in physical RAM.
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Available memory areas are declared in the 'Target' tab of the
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Options for Target' dialog.
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*** ICCARM Compiler ***
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-----------------------
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[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
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*** GNU Compiler ***
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--------------------
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[..] RAM functions are defined using a specific toolchain attribute
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"__attribute__((section(".RamFunc")))".
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_hal.h"
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/** @addtogroup STM32L1xx_HAL_Driver
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* @{
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*/
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/** @defgroup FLASHRamfunc FLASHRamfunc
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* @brief FLASH functions executed from RAM
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* @{
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*/
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#ifdef HAL_FLASH_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup FLASHRamfunc_Exported_Functions FLASH RAM Exported Functions
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*
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@verbatim
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===============================================================================
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##### ramfunc functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions that should be executed from RAM
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transfers.
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@endverbatim
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* @{
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*/
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/** @defgroup FLASHRamfunc_Exported_Functions_Group1 FLASH RAM Peripheral features functions
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* @{
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*/
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/**
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* @brief Enable the power down mode during RUN mode.
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* @note This function can be used only when the user code is running from Internal SRAM.
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* @retval None
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*/
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__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
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{
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/* Enable the Power Down in Run mode*/
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__HAL_FLASH_POWER_DOWN_ENABLE();
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return HAL_OK;
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}
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/**
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* @brief Disable the power down mode during RUN mode.
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* @note This function can be used only when the user code is running from Internal SRAM.
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* @retval None
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*/
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__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
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{
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/* Disable the Power Down in Run mode*/
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__HAL_FLASH_POWER_DOWN_DISABLE();
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return HAL_OK;
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}
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/**
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* @}
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*/
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/** @defgroup FLASHRamfunc_Exported_Functions_Group2 FLASH RAM Programming and erasing operation functions
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*
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@verbatim
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@endverbatim
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* @{
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*/
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#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
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defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
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/**
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* @brief Erases a specified 2 page in program memory in parallel.
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* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
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* To correctly run this function, the HAL_FLASH_Unlock() function
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* must be called before.
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* Call the HAL_FLASH_Lock() to disable the flash memory access
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* (recommended to protect the FLASH memory against possible unwanted operation).
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* @param Page_Address1: The page address in program memory to be erased in
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* the first Bank (BANK1). This parameter should be between FLASH_BASE
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* and FLASH_BANK1_END.
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* @param Page_Address2: The page address in program memory to be erased in
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* the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
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* and FLASH_BANK2_END.
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* @note A Page is erased in the Program memory only if the address to load
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* is the start address of a page (multiple of 256 bytes).
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* @retval HAL Status: The returned value can be:
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* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
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*/
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__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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if(status == HAL_OK)
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{
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/* If the previous operation is completed, proceed to erase the page */
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/* Set the PARALLBANK bit */
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FLASH->PECR |= FLASH_PECR_PARALLBANK;
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/* Set the ERASE bit */
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FLASH->PECR |= FLASH_PECR_ERASE;
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/* Set PROG bit */
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FLASH->PECR |= FLASH_PECR_PROG;
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/* Write 00000000h to the first word of the first program page to erase */
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*(__IO uint32_t *)Page_Address1 = 0x00000000;
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/* Write 00000000h to the first word of the second program page to erase */
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*(__IO uint32_t *)Page_Address2 = 0x00000000;
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
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}
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/* Return the Erase Status */
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return status;
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}
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/**
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* @brief Programs 2 half page in program memory in parallel.
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* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
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* @param Address1: specifies the first address to be written in the first bank
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* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
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* @param pBuffer1: pointer to the buffer containing the data to be written
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* to the first half page in the first bank.
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* @param Address2: specifies the second address to be written in the second bank
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* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
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* @param pBuffer2: pointer to the buffer containing the data to be written
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* to the second half page in the second bank.
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* @note To correctly run this function, the HAL_FLASH_Unlock() function
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* must be called before.
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* Call the HAL_FLASH_Lock() to disable the flash memory access
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* (recommended to protect the FLASH memory against possible unwanted operation).
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* @note Half page write is possible only from SRAM.
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* @note If there are more than 32 words to write, after 32 words another
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* Half Page programming operation starts and has to be finished.
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* @note A half page is written to the program memory only if the first
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* address to load is the start address of a half page (multiple of 128
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* bytes) and the 31 remaining words to load are in the same half page.
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* @note During the Program memory half page write all read operations are
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* forbidden (this includes DMA read operations and debugger read
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* operations such as breakpoints, periodic updates, etc.).
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* @note If a PGAERR is set during a Program memory half page write, the
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* complete write operation is aborted. Software should then reset the
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* FPRG and PROG/DATA bits and restart the write operation from the
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* beginning.
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* @retval HAL Status: The returned value can be:
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* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
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*/
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__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
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{
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uint32_t count = 0;
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HAL_StatusTypeDef status = HAL_OK;
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/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
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This bit prevents the interruption of multicycle instructions and therefore
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will increase the interrupt latency. of Cortex-M3. */
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SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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if(status == HAL_OK)
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{
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/* If the previous operation is completed, proceed to program the new
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half page */
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FLASH->PECR |= FLASH_PECR_PARALLBANK;
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FLASH->PECR |= FLASH_PECR_FPRG;
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FLASH->PECR |= FLASH_PECR_PROG;
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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if(status == HAL_OK)
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{
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/* Write the first half page directly with 32 different words */
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while(count < 32)
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{
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*(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *(pBuffer1++);
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count ++;
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}
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count = 0;
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/* Write the second half page directly with 32 different words */
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while(count < 32)
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{
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*(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *(pBuffer2++);
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count ++;
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}
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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}
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/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
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}
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SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
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/* Return the Write Status */
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return status;
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}
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#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
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/**
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* @brief Programs a half page in program memory.
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* @param Address: specifies the address to be written.
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* @param pBuffer: pointer to the buffer containing the data to be written to
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* the half page.
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* @note To correctly run this function, the HAL_FLASH_Unlock() function
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* must be called before.
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* Call the HAL_FLASH_Lock() to disable the flash memory access
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* (recommended to protect the FLASH memory against possible unwanted operation)
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* @note Half page write is possible only from SRAM.
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* @note If there are more than 32 words to write, after 32 words another
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* Half Page programming operation starts and has to be finished.
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* @note A half page is written to the program memory only if the first
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* address to load is the start address of a half page (multiple of 128
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* bytes) and the 31 remaining words to load are in the same half page.
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* @note During the Program memory half page write all read operations are
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* forbidden (this includes DMA read operations and debugger read
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* operations such as breakpoints, periodic updates, etc.).
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* @note If a PGAERR is set during a Program memory half page write, the
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* complete write operation is aborted. Software should then reset the
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* FPRG and PROG/DATA bits and restart the write operation from the
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* beginning.
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* @retval HAL Status: The returned value can be:
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* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
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*/
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__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
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{
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uint32_t count = 0;
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HAL_StatusTypeDef status = HAL_OK;
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/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
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This bit prevents the interruption of multicycle instructions and therefore
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will increase the interrupt latency. of Cortex-M3. */
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SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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if(status == HAL_OK)
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{
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/* if the previous operation is completed, proceed to program the new
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half page */
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FLASH->PECR |= FLASH_PECR_FPRG;
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FLASH->PECR |= FLASH_PECR_PROG;
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/* Write one half page directly with 32 different words */
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while(count < 32)
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{
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*(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *(pBuffer++);
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count ++;
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}
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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/* if the write operation is completed, disable the PROG and FPRG bits */
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
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FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
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}
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SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
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/* Return the Write Status */
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return status;
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}
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/**
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* @}
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*/
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/** @defgroup FLASHRamfunc_Exported_Functions_Group3 FLASH RAM DATA EEPROM functions
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*
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@verbatim
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@endverbatim
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* @{
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*/
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/**
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* @brief Erase a double word in data memory.
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* @param Address: specifies the address to be erased.
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* @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
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* must be called before.
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* Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
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* and Flash program erase control register access(recommended to protect
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* the DATA_EEPROM against possible unwanted operation).
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* @note Data memory double word erase is possible only from SRAM.
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* @note A double word is erased to the data memory only if the first address
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* to load is the start address of a double word (multiple of 8 bytes).
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* @note During the Data memory double word erase, all read operations are
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* forbidden (this includes DMA read operations and debugger read
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* operations such as breakpoints, periodic updates, etc.).
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* @retval HAL Status: The returned value can be:
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* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
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*/
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__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
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This bit prevents the interruption of multicycle instructions and therefore
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will increase the interrupt latency. of Cortex-M3. */
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||
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SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
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/* Wait for last operation to be completed */
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status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
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if(status == HAL_OK)
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{
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/* If the previous operation is completed, proceed to erase the next double word */
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/* Set the ERASE bit */
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FLASH->PECR |= FLASH_PECR_ERASE;
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||
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|
||
|
/* Set DATA bit */
|
||
|
FLASH->PECR |= FLASH_PECR_DATA;
|
||
|
|
||
|
/* Write 00000000h to the 2 words to erase */
|
||
|
*(__IO uint32_t *)Address = 0x00000000;
|
||
|
Address += 4;
|
||
|
*(__IO uint32_t *)Address = 0x00000000;
|
||
|
|
||
|
/* Wait for last operation to be completed */
|
||
|
status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
|
||
|
|
||
|
/* If the erase operation is completed, disable the ERASE and DATA bits */
|
||
|
FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
|
||
|
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
|
||
|
}
|
||
|
|
||
|
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||
|
|
||
|
/* Return the erase status */
|
||
|
return status;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @brief Write a double word in data memory without erase.
|
||
|
* @param Address: specifies the address to be written.
|
||
|
* @param Data: specifies the data to be written.
|
||
|
* @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
|
||
|
* must be called before.
|
||
|
* Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
|
||
|
* and Flash program erase control register access(recommended to protect
|
||
|
* the DATA_EEPROM against possible unwanted operation).
|
||
|
* @note Data memory double word write is possible only from SRAM.
|
||
|
* @note A data memory double word is written to the data memory only if the
|
||
|
* first address to load is the start address of a double word (multiple
|
||
|
* of double word).
|
||
|
* @note During the Data memory double word write, all read operations are
|
||
|
* forbidden (this includes DMA read operations and debugger read
|
||
|
* operations such as breakpoints, periodic updates, etc.).
|
||
|
* @retval HAL Status: The returned value can be:
|
||
|
* HAL_ERROR, HAL_OK or HAL_TIMEOUT.
|
||
|
*/
|
||
|
__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
|
||
|
{
|
||
|
HAL_StatusTypeDef status = HAL_OK;
|
||
|
|
||
|
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||
|
This bit prevents the interruption of multicycle instructions and therefore
|
||
|
will increase the interrupt latency. of Cortex-M3. */
|
||
|
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||
|
|
||
|
/* Wait for last operation to be completed */
|
||
|
status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
|
||
|
|
||
|
if(status == HAL_OK)
|
||
|
{
|
||
|
/* If the previous operation is completed, proceed to program the new data*/
|
||
|
FLASH->PECR |= FLASH_PECR_FPRG;
|
||
|
FLASH->PECR |= FLASH_PECR_DATA;
|
||
|
|
||
|
/* Write the 2 words */
|
||
|
*(__IO uint32_t *)Address = (uint32_t) Data;
|
||
|
Address += 4;
|
||
|
*(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
|
||
|
|
||
|
/* Wait for last operation to be completed */
|
||
|
status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
|
||
|
|
||
|
/* If the write operation is completed, disable the FPRG and DATA bits */
|
||
|
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
|
||
|
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
|
||
|
}
|
||
|
|
||
|
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||
|
|
||
|
/* Return the Write Status */
|
||
|
return status;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/** @defgroup FLASHRamfunc_Private_Functions FLASH RAM Private Functions
|
||
|
* @{
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @brief Wait for a FLASH operation to complete.
|
||
|
* @param Timeout: maximum flash operationtimeout
|
||
|
* @retval HAL status
|
||
|
*/
|
||
|
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
|
||
|
{
|
||
|
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||
|
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||
|
flag will be set */
|
||
|
|
||
|
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00))
|
||
|
{
|
||
|
Timeout--;
|
||
|
}
|
||
|
|
||
|
if(Timeout == 0x00 )
|
||
|
{
|
||
|
return HAL_TIMEOUT;
|
||
|
}
|
||
|
|
||
|
if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) ||
|
||
|
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) ||
|
||
|
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) ||
|
||
|
#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
|
||
|
defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
|
||
|
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) ||
|
||
|
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
|
||
|
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
|
||
|
defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
|
||
|
defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
|
||
|
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) ||
|
||
|
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
|
||
|
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) )
|
||
|
{
|
||
|
return HAL_ERROR;
|
||
|
}
|
||
|
|
||
|
/* If there is an error flag set */
|
||
|
return HAL_OK;
|
||
|
}
|
||
|
|
||
|
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* @}
|
||
|
*/
|
||
|
|
||
|
|
||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|