2013-01-12 22:44:42 +00:00
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/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-ioc cc2538 I/O Control
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*
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2015-02-14 01:09:24 +00:00
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* Driver for the cc2538 I/O Control Module
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2013-01-12 22:44:42 +00:00
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* @{
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*
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* \file
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* Header file with declarations for the I/O Control module
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*/
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#ifndef IOC_H_
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#define IOC_H_
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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/** \name IOC Signal Select Registers
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* @{
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*/
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#define IOC_PA0_SEL 0x400D4000
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#define IOC_PA1_SEL 0x400D4004
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#define IOC_PA2_SEL 0x400D4008
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#define IOC_PA3_SEL 0x400D400C
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#define IOC_PA4_SEL 0x400D4010
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#define IOC_PA5_SEL 0x400D4014
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#define IOC_PA6_SEL 0x400D4018
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#define IOC_PA7_SEL 0x400D401C
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#define IOC_PB0_SEL 0x400D4020
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#define IOC_PB1_SEL 0x400D4024
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#define IOC_PB2_SEL 0x400D4028
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#define IOC_PB3_SEL 0x400D402C
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#define IOC_PB4_SEL 0x400D4030
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#define IOC_PB5_SEL 0x400D4034
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#define IOC_PB6_SEL 0x400D4038
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#define IOC_PB7_SEL 0x400D403C
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#define IOC_PC0_SEL 0x400D4040
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#define IOC_PC1_SEL 0x400D4044
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#define IOC_PC2_SEL 0x400D4048
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#define IOC_PC3_SEL 0x400D404C
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#define IOC_PC4_SEL 0x400D4050
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#define IOC_PC5_SEL 0x400D4054
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#define IOC_PC6_SEL 0x400D4058
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#define IOC_PC7_SEL 0x400D405C
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#define IOC_PD0_SEL 0x400D4060
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#define IOC_PD1_SEL 0x400D4064
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#define IOC_PD2_SEL 0x400D4068
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#define IOC_PD3_SEL 0x400D406C
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#define IOC_PD4_SEL 0x400D4070
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#define IOC_PD5_SEL 0x400D4074
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#define IOC_PD6_SEL 0x400D4078
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#define IOC_PD7_SEL 0x400D407C
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name IOC Override Configuration Registers
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* @{
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*/
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#define IOC_PA0_OVER 0x400D4080
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#define IOC_PA1_OVER 0x400D4084
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#define IOC_PA2_OVER 0x400D4088
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#define IOC_PA3_OVER 0x400D408C
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#define IOC_PA4_OVER 0x400D4090
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#define IOC_PA5_OVER 0x400D4094
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#define IOC_PA6_OVER 0x400D4098
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#define IOC_PA7_OVER 0x400D409C
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#define IOC_PB0_OVER 0x400D40A0
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#define IOC_PB1_OVER 0x400D40A4
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#define IOC_PB2_OVER 0x400D40A8
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#define IOC_PB3_OVER 0x400D40AC
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#define IOC_PB4_OVER 0x400D40B0
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#define IOC_PB5_OVER 0x400D40B4
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#define IOC_PB6_OVER 0x400D40B8
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#define IOC_PB7_OVER 0x400D40BC
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#define IOC_PC0_OVER 0x400D40C0
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#define IOC_PC1_OVER 0x400D40C4
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#define IOC_PC2_OVER 0x400D40C8
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#define IOC_PC3_OVER 0x400D40CC
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#define IOC_PC4_OVER 0x400D40D0
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#define IOC_PC5_OVER 0x400D40D4
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#define IOC_PC6_OVER 0x400D40D8
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#define IOC_PC7_OVER 0x400D40DC
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#define IOC_PD0_OVER 0x400D40E0
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#define IOC_PD1_OVER 0x400D40E4
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#define IOC_PD2_OVER 0x400D40E8
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#define IOC_PD3_OVER 0x400D40EC
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#define IOC_PD4_OVER 0x400D40F0
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#define IOC_PD5_OVER 0x400D40F4
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#define IOC_PD6_OVER 0x400D40F8
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#define IOC_PD7_OVER 0x400D40FC
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name IOC Input Pin Select Registers
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* @{
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*/
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#define IOC_UARTRXD_UART0 0x400D4100 /**< UART0 RX */
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#define IOC_UARTCTS_UART1 0x400D4104 /**< UART1 CTS */
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#define IOC_UARTRXD_UART1 0x400D4108 /**< UART1 RX */
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#define IOC_CLK_SSI_SSI0 0x400D410C /**< SSI0 Clock */
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#define IOC_SSIRXD_SSI0 0x400D4110 /**< SSI0 RX */
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#define IOC_SSIFSSIN_SSI0 0x400D4114 /**< SSI0 FSSIN */
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#define IOC_CLK_SSIIN_SSI0 0x400D4118 /**< SSI0 Clock SSIIN */
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#define IOC_CLK_SSI_SSI1 0x400D411C /**< SSI1 Clock */
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#define IOC_SSIRXD_SSI1 0x400D4120 /**< SSI1 RX */
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#define IOC_SSIFSSIN_SSI1 0x400D4124 /**< SSI1 FSSIN Select */
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#define IOC_CLK_SSIIN_SSI1 0x400D4128 /**< SSI1 Clock SSIIN */
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#define IOC_I2CMSSDA 0x400D412C /**< I2C SDA */
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#define IOC_I2CMSSCL 0x400D4130 /**< I2C SCL */
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#define IOC_GPT0OCP1 0x400D4134 /**< GPT0OCP1 */
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#define IOC_GPT0OCP2 0x400D4138 /**< GPT0OCP2 */
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#define IOC_GPT1OCP1 0x400D413C /**< GPT1OCP1 */
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#define IOC_GPT1OCP2 0x400D4140 /**< GPT1OCP2 */
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#define IOC_GPT2OCP1 0x400D4144 /**< GPT2OCP1 */
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#define IOC_GPT2OCP2 0x400D4148 /**< GPT2OCP2 */
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#define IOC_GPT3OCP1 0x400D414C /**< GPT3OCP1 */
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#define IOC_GPT3OCP2 0x400D4150 /**< GPT3OCP2 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name I/O Control Register Bit Masks
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* @{
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*/
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#define IOC_OVR_MASK 0x0000000F /**< IOC_Pxn_OVER registers */
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#define IOC_PXX_SEL_MASK 0x0000001F /**< IOC_Pxn_SEL registers */
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#define IOC_INPUT_SEL_MASK 0x0000001F /**< All other IOC registers */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name INPUT_SEL Values (For Pin Selection Registers)
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* @{
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*/
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#define IOC_INPUT_SEL_PA0 0x00000000
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#define IOC_INPUT_SEL_PA1 0x00000001
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#define IOC_INPUT_SEL_PA2 0x00000002
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#define IOC_INPUT_SEL_PA3 0x00000003
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#define IOC_INPUT_SEL_PA4 0x00000004
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#define IOC_INPUT_SEL_PA5 0x00000005
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#define IOC_INPUT_SEL_PA6 0x00000006
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#define IOC_INPUT_SEL_PA7 0x00000007
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#define IOC_INPUT_SEL_PB0 0x00000008
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#define IOC_INPUT_SEL_PB1 0x00000009
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#define IOC_INPUT_SEL_PB2 0x0000000A
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#define IOC_INPUT_SEL_PB3 0x0000000B
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#define IOC_INPUT_SEL_PB4 0x0000000C
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#define IOC_INPUT_SEL_PB5 0x0000000D
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#define IOC_INPUT_SEL_PB6 0x0000000E
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#define IOC_INPUT_SEL_PB7 0x0000000F
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#define IOC_INPUT_SEL_PC0 0x00000010
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#define IOC_INPUT_SEL_PC1 0x00000011
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#define IOC_INPUT_SEL_PC2 0x00000012
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#define IOC_INPUT_SEL_PC3 0x00000013
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#define IOC_INPUT_SEL_PC4 0x00000014
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#define IOC_INPUT_SEL_PC5 0x00000015
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#define IOC_INPUT_SEL_PC6 0x00000016
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#define IOC_INPUT_SEL_PC7 0x00000017
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#define IOC_INPUT_SEL_PD0 0x00000018
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#define IOC_INPUT_SEL_PD1 0x00000019
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#define IOC_INPUT_SEL_PD2 0x0000001A
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#define IOC_INPUT_SEL_PD3 0x0000001B
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#define IOC_INPUT_SEL_PD4 0x0000001C
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#define IOC_INPUT_SEL_PD5 0x0000001D
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#define IOC_INPUT_SEL_PD6 0x0000001E
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#define IOC_INPUT_SEL_PD7 0x0000001F
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name Peripheral Signal Select Values (for IOC_Pxx_SEL registers)
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* @{
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*/
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#define IOC_PXX_SEL_UART0_TXD 0x00000000
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#define IOC_PXX_SEL_UART1_RTS 0x00000001
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#define IOC_PXX_SEL_UART1_TXD 0x00000002
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#define IOC_PXX_SEL_SSI0_TXD 0x00000003
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#define IOC_PXX_SEL_SSI0_CLKOUT 0x00000004
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#define IOC_PXX_SEL_SSI0_FSSOUT 0x00000005
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#define IOC_PXX_SEL_SSI0_STXSER_EN 0x00000006
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#define IOC_PXX_SEL_SSI1_TXD 0x00000007
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#define IOC_PXX_SEL_SSI1_CLKOUT 0x00000008
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#define IOC_PXX_SEL_SSI1_FSSOUT 0x00000009
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#define IOC_PXX_SEL_SSI1_STXSER_EN 0x0000000A
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#define IOC_PXX_SEL_I2C_CMSSDA 0x0000000B
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#define IOC_PXX_SEL_I2C_CMSSCL 0x0000000C
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#define IOC_PXX_SEL_GPT0_ICP1 0x0000000D
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#define IOC_PXX_SEL_GPT0_ICP2 0x0000000E
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#define IOC_PXX_SEL_GPT1_ICP1 0x0000000F
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#define IOC_PXX_SEL_GPT1_ICP2 0x00000010
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#define IOC_PXX_SEL_GPT2_ICP1 0x00000011
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#define IOC_PXX_SEL_GPT2_ICP2 0x00000012
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#define IOC_PXX_SEL_GPT3_ICP1 0x00000013
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#define IOC_PXX_SEL_GPT3_ICP2 0x00000014
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name Values for IOC_PXX_OVER
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* @{
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*/
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#define IOC_OVERRIDE_OE 0x00000008 /**< Output Enable */
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#define IOC_OVERRIDE_PUE 0x00000004 /**< Pull Up Enable */
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#define IOC_OVERRIDE_PDE 0x00000002 /**< Pull Down Enable */
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#define IOC_OVERRIDE_ANA 0x00000001 /**< Analog Enable */
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#define IOC_OVERRIDE_DIS 0x00000000 /**< Override Disabled */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name IOC Functions
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* @{
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*/
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/** \brief Initialise the IOC driver */
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void ioc_init();
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/**
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* \brief Set Port:Pin override function
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* \param port The port as a number (PA: 0, PB: 1 etc)
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* \param pin The pin as a number
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* \param over The desired override configuration
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*
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* \e over can take the following values:
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*
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* - IOC_OVERRIDE_OE: Output
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* - IOC_OVERRIDE_PUE: Pull-Up
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* - IOC_OVERRIDE_PDE: Pull-Down
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* - IOC_OVERRIDE_ANA: Analog
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* - IOC_OVERRIDE_DIS: Disabled
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*/
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void ioc_set_over(uint8_t port, uint8_t pin, uint8_t over);
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/**
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* \brief Function select for Port:Pin
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* \param port The port as a number (PA: 0, PB: 1 etc)
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* \param pin The pin as a number
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* \param sel The desired function
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*
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* The value of \e sel can be any of the IOC_PXX_SEL_xyz defines. For example
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* IOC_PXX_SEL_UART0_TXD will set the port to act as UART0 TX
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*/
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void ioc_set_sel(uint8_t port, uint8_t pin, uint8_t sel);
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/**
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* \brief Generates an IOC_INPUT_SEL_PXn value from a port/pin number
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* \param port The port as a number (PA: 0, PB: 1 etc)
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* \param pin The pin as a number
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* \return A value which can be written in the INPUT_SEL bits of various IOC
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* registers
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*/
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#define ioc_input_sel(port, pin) ((port << 3) | pin)
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/** @} */
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#endif /* IOC_H_ */
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/**
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* @}
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* @}
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*/
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