From d87f6f67e21df977886115436ff33bee617e4500 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 24 Jul 2015 16:23:13 +0200 Subject: [PATCH 01/23] Added new stm32nucleo-spirit1 platform --- regression-tests/01-compile-base/Makefile | 3 +++ regression-tests/15-compile-arm-apcs-ports/Makefile | 1 + regression-tests/18-compile-arm-ports/Makefile | 8 ++++++++ 3 files changed, 12 insertions(+) diff --git a/regression-tests/01-compile-base/Makefile b/regression-tests/01-compile-base/Makefile index e756bf5a6..878d4324a 100644 --- a/regression-tests/01-compile-base/Makefile +++ b/regression-tests/01-compile-base/Makefile @@ -2,6 +2,7 @@ EXAMPLESDIR=../../examples TOOLSDIR=../../tools EXAMPLES = \ +hello-world/stm32nucleo-spirit1 \ hello-world/avr-raven \ hello-world/exp5438 \ hello-world/eval-adf7xxxmb4z \ @@ -14,6 +15,7 @@ hello-world/z1 \ eeprom-test/native \ collect/sky \ er-rest-example/sky \ +er-rest-example/stm32nucleo-spirit1 \ example-shell/native \ netperf/sky \ powertrace/sky \ @@ -34,6 +36,7 @@ wget/minimal-net \ z1/z1 \ settings-example/avr-raven \ ipv6/multicast/sky \ +ipv6/multicast/stm32nucleo-spirit1 \ TOOLS= diff --git a/regression-tests/15-compile-arm-apcs-ports/Makefile b/regression-tests/15-compile-arm-apcs-ports/Makefile index e73a9a39f..61f37d47e 100644 --- a/regression-tests/15-compile-arm-apcs-ports/Makefile +++ b/regression-tests/15-compile-arm-apcs-ports/Makefile @@ -4,6 +4,7 @@ TOOLSDIR=../../tools EXAMPLES = \ hello-world/econotag \ hello-world/mbxxx \ +hello-world/stm32nucleo-spirit1 \ ipv6/rpl-border-router/econotag \ er-rest-example/econotag \ webserver-ipv6/econotag \ diff --git a/regression-tests/18-compile-arm-ports/Makefile b/regression-tests/18-compile-arm-ports/Makefile index 217b5eef9..3dd5058d7 100644 --- a/regression-tests/18-compile-arm-ports/Makefile +++ b/regression-tests/18-compile-arm-ports/Makefile @@ -17,6 +17,14 @@ cc2538dk/udp-ipv6-echo-server/cc2538dk \ cc2538dk/sniffer/cc2538dk \ cc2538dk/mqtt-demo/cc2538dk \ ipv6/multicast/cc2538dk \ +er-rest-example/stm32nucleo-spirit1 \ +ipv6/rpl-border-router/stm32nucleo-spirit1 \ +ipv6/rpl-udp/stm32nucleo-spirit1 \ +ipv6/simple-udp-rpl/stm32nucleo-spirit1 \ +stm32nucleo-spirit1/sensor-demo/stm32nucleo-spirit1 \ +ipv6/multicast/stm32nucleo-spirit1 \ +udp-ipv6/stm32nucleo-spirit1 \ +hello-world/stm32nucleo-spirit1 \ TOOLS= From 86f35536a4f770dea3df8d7242d9f289c853488c Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 24 Jul 2015 16:30:10 +0200 Subject: [PATCH 02/23] Added new stm32nucleo-spirit1 platform --- .../CMSIS END USER LICENCE AGREEMENT.pdf | Bin 0 -> 24914 bytes cpu/arm/stm32l152/CMSIS/README.txt | 37 + cpu/arm/stm32l152/CMSIS/index.html | 14 + cpu/arm/stm32l152/CMSIS/stm32l152xb.h | 5300 +++++++ cpu/arm/stm32l152/CMSIS/stm32l152xba.h | 5312 +++++++ cpu/arm/stm32l152/CMSIS/stm32l152xc.h | 5793 ++++++++ cpu/arm/stm32l152/CMSIS/stm32l152xca.h | 5981 ++++++++ cpu/arm/stm32l152/CMSIS/stm32l152xd.h | 6355 +++++++++ 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z2RUp7J>HB{R*N;<<(`f=2cvhF7QXooz92haRn&uhUpL;`#Eorz&AxckUZMHxmrpm_ zzAu-yb`eM*pln@d@ptY-ITY;n_LY?_c!fr!QWjoaEDiJjd=&YXg}q8Mf;a?>kU&Vw zLS-bRC6G=s2w6uoR2n7gD2;MNOF|u$?EXwmj7f^r*RC^=IG=6Ck(h)WV#&)j3t+Oh zx)^7#F{I=k+C!$MfJ^|#Yo^(EC>U-W_Qf$8O4`rSCxaeg4o%<1t_>?n;9N+`hbV_* wTW*X86VK}cX{_CEiX2h2{6nC8eDO=K0Q`pv@E=W(l!8i7Q3wcV7->@dA5p` + + +Redirect to the CMSIS main page after 0 seconds + + + + + + +If the automatic redirection is failing, click open CMSIS Documentation. + + + diff --git a/cpu/arm/stm32l152/CMSIS/stm32l152xb.h b/cpu/arm/stm32l152/CMSIS/stm32l152xb.h new file mode 100644 index 000000000..8e0f9327b --- /dev/null +++ b/cpu/arm/stm32l152/CMSIS/stm32l152xb.h @@ -0,0 +1,5300 @@ +/** + ****************************************************************************** + * @file stm32l152xb.h + * @author MCD Application Team + * @version V2.0.0 + * @date 5-September-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xb + * @{ + */ + +#ifndef __STM32L152xB_H +#define __STM32L152xB_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xba + * @{ + */ + +#ifndef __STM32L152xBA_H +#define __STM32L152xBA_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xc + * @{ + */ + +#ifndef __STM32L152xC_H +#define __STM32L152xC_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xca + * @{ + */ + +#ifndef __STM32L152xCA_H +#define __STM32L152xCA_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xd + * @{ + */ + +#ifndef __STM32L152xD_H +#define __STM32L152xD_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + SDIO_IRQn = 45, /*!< SDIO global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + UART4_IRQn = 48, /*!< UART4 global Interrupt */ + UART5_IRQn = 49, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xe + * @{ + */ + +#ifndef __STM32L152xE_H +#define __STM32L152xE_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + UART4_IRQn = 48, /*!< UART4 global Interrupt */ + UART5_IRQn = 49, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*! 0x7C */ + __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */ + __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */ +} OB_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief General Purpose IO + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ + __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ + __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ +} RCC_TypeDef; + +/** + * @brief Routing Interface + */ + +typedef struct +{ + __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ +} RI_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + uint32_t RESERVED12; /*!< Reserved, 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + uint32_t RESERVED17; /*!< Reserved, 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define FLASH_BANK2_BASE ((uint32_t)0x08040000) /*!< FLASH BANK2 base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH BANK1 address */ +#define FLASH_BANK2_END ((uint32_t)0x0807FFFF) /*!< Program end FLASH BANK2 address */ +#define FLASH_EEPROM_END ((uint32_t)0x08083FFF) /*!< FLASH EEPROM end address (16KB) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) +#define LCD_BASE (APB1PERIPH_BASE + 0x00002400) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x00005000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) + +/* USB device FS */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ + +/* USB device FS SRAM */ +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400) +#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00) +#define RI_BASE (APB1PERIPH_BASE + 0x00007C04) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) +#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800) +#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00) +#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002700) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) + +/*!< AHB peripherals */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) +#define RCC_BASE (AHBPERIPH_BASE + 0x00003800) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058) +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +/* USB device FS */ +#define USB ((USB_TypeDef *) USB_BASE) +/* USB device FS SRAM */ +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define COMP ((COMP_TypeDef *) COMP_BASE) +#define COMP1 ((COMP_TypeDef *) COMP_BASE) +#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001)) +#define RI ((RI_TypeDef *) RI_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001)) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + + /** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ +#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ + +#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ +#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ +#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ +#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ +#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR3 register *******************/ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR4 register *******************/ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR5 register *******************/ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ + +/****************** Bit definition for ADC_SMPR0 register *******************/ +#define ADC_SMPR0_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */ +#define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR0_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */ +#define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +/******************* Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ +#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ + +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for COMP_CSR register ********************/ +#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ +#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ +#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ +#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ +#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ + +#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ +#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ +#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for OPAMP_CSR register ******************/ +#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ +#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ +#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ +#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ +#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ +#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ +#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ +#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ +#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ +#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ +#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ +#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ +#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ +#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ +#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ +#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ +#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ +#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ + +/******************* Bit definition for OPAMP_OTR register ******************/ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ +#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ + +/******************* Bit definition for OPAMP_LPOTR register ****************/ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx + * @{ + */ + +#ifndef __STM32L1XX_H +#define __STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ + !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \ + !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \ + !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE) + /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ + /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ + /* #define STM32L100xC */ /*!< STM32L100RC Devices */ + /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ + /* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ + /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ + /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ + /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ + /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ + /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ + /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ + /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ + /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ + /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ + /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ + /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ + /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ + /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ + /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.0.0 + */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ + |(__CMSIS_DEVICE_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32L100xB) + #include "stm32l100xb.h" +#elif defined(STM32L100xBA) + #include "stm32l100xba.h" +#elif defined(STM32L100xC) + #include "stm32l100xc.h" +#elif defined(STM32L151xB) + #include "stm32l151xb.h" +#elif defined(STM32L151xBA) + #include "stm32l151xba.h" +#elif defined(STM32L151xC) + #include "stm32l151xc.h" +#elif defined(STM32L151xCA) + #include "stm32l151xca.h" +#elif defined(STM32L151xD) + #include "stm32l151xd.h" +#elif defined(STM32L151xE) + #include "stm32l151xe.h" +#elif defined(STM32L152xB) + #include "stm32l152xb.h" +#elif defined(STM32L152xBA) + #include "stm32l152xba.h" +#elif defined(STM32L152xC) + #include "stm32l152xc.h" +#elif defined(STM32L152xCA) + #include "stm32l152xca.h" +#elif defined(STM32L152xD) + #include "stm32l152xd.h" +#elif defined(STM32L152xE) + #include "stm32l152xe.h" +#elif defined(STM32L162xC) + #include "stm32l162xc.h" +#elif defined(STM32L162xCA) + #include "stm32l162xca.h" +#elif defined(STM32L162xD) + #include "stm32l162xd.h" +#elif defined(STM32L162xE) + #include "stm32l162xe.h" +#else + #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.c b/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.c new file mode 100644 index 000000000..4bd19a874 --- /dev/null +++ b/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.c @@ -0,0 +1,416 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l1xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** @addtogroup STM32L1xx_System_Private_Includes + * @{ + */ + +#include "stm32l1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM32L152D_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 32000000; +__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x88FFC00C; + + /*!< Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xEEFEFFFE; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFF; + + /*!< Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in SystemInit() function before jump to main. + * This function configures the external SRAM mounted on STM32L152D_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ + | PD15 <-> FSMC_D1 |--------------------+ + +-------------------+ +*/ + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHBENR = 0x000080D8; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00CC00CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A0A; + /* Configure PDx pins speed to 40 MHz */ + GPIOD->OSPEEDR = 0xFFFF0F0F; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 40 MHz */ + GPIOE->OSPEEDR = 0xFFFFC00F; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 40 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x00000C00; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00200AAA; + /* Configure PGx pins speed to 40 MHz */ + GPIOG->OSPEEDR = 0x00300FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHBENR = 0x400080D8; + + /* Configure and enable Bank1_SRAM3 */ + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000300; + FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; +/* + Bank1_SRAM3 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 3; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); +*/ + +} +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.h b/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.h new file mode 100644 index 000000000..3ad18770d --- /dev/null +++ b/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.h + * @author MCD Application Team + * @version V2.0.0 + * @date 5-September-2014 + * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L1XX_H +#define __SYSTEM_STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L1xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L1xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L1XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/Makefile.stm32l152 b/cpu/arm/stm32l152/Makefile.stm32l152 new file mode 100644 index 000000000..a6011749d --- /dev/null +++ b/cpu/arm/stm32l152/Makefile.stm32l152 @@ -0,0 +1,186 @@ +# Makefile for the STM32L152VB Cortex M3 medium-density microcontroller +# author Marcus Lunden + +.SUFFIXES: + +# CPU folder +CONTIKI_CPU=$(CONTIKI)/cpu/arm/stm32l152 + +# Source folders for ST HAL libraries, ARM CMSIS and IAR conf files +CONTIKI_CPU_DIRS = . \ + STM32L1xx_HAL_Driver \ + STM32L1xx_HAL_Driver/Src \ + CMSIS \ + STM32L1xx_HAL_Driver/Inc + +# source files: proprietary sources for startup. Refer to CMSIS docs. +PROP_SYS_ARCH_C = system_stm32l1xx.c + + +ifdef IAR +include $(CONTIKI_CPU)/Makefile.stm32l152.iar +else +include $(CONTIKI_CPU)/Makefile.stm32l152.gnu +endif + + +# source files: Contiki arch source files +CONTIKI_CPU_ARCH= watchdog.c \ + rtimer-arch.c \ + clock.c + +ifdef GCC +CONTIKI_CPU_PORT= sysmem.c \ + console.c \ + crt.c \ + uart.c +else +CONTIKI_CPU_PORT= +endif + + + +UIPDRIVERS= + +# to be implemented +ELFLOADER= + + +STM32L1XX_HAL =\ + stm32l1xx_hal.c\ + stm32l1xx_hal_adc_ex.c\ + stm32l1xx_hal_adc.c\ + stm32l1xx_hal_comp.c\ + stm32l1xx_hal_cortex.c\ + stm32l1xx_hal_crc.c\ + stm32l1xx_hal_cryp_ex.c\ + stm32l1xx_hal_cryp.c\ + stm32l1xx_hal_dac_ex.c\ + stm32l1xx_hal_dac.c\ + stm32l1xx_hal_dma.c\ + stm32l1xx_hal_flash_ex.c\ + stm32l1xx_hal_flash.c\ + stm32l1xx_hal_flash_ramfunc.c\ + stm32l1xx_hal_gpio.c\ + stm32l1xx_hal_i2c.c\ + stm32l1xx_hal_i2s.c\ + stm32l1xx_hal_irda.c\ + stm32l1xx_hal_iwdg.c\ + stm32l1xx_hal_lcd.c\ + stm32l1xx_hal_nor.c\ + stm32l1xx_hal_opamp_ex.c\ + stm32l1xx_hal_opamp.c\ + stm32l1xx_hal_pcd_ex.c\ + stm32l1xx_hal_pcd.c\ + stm32l1xx_hal_pwr_ex.c\ + stm32l1xx_hal_pwr.c\ + stm32l1xx_hal_rcc_ex.c\ + stm32l1xx_hal_rcc.c\ + stm32l1xx_hal_rtc_ex.c\ + stm32l1xx_hal_rtc.c\ + stm32l1xx_hal_sd.c\ + stm32l1xx_hal_smartcard.c\ + stm32l1xx_hal_spi_ex.c\ + stm32l1xx_hal_spi.c\ + stm32l1xx_hal_sram.c\ + stm32l1xx_hal_tim_ex.c\ + stm32l1xx_hal_tim.c\ + stm32l1xx_hal_uart.c\ + stm32l1xx_hal_usart.c\ + stm32l1xx_hal_wwdg.c\ + stm32l1xx_ll_fsmc.c\ + stm32l1xx_ll_sdmmc.c + + + +# add CPU folder to search path for .s (assembler) files +vpath %.s $(CONTIKI_CPU) + + + +# include all files above +ssubst = ${patsubst %.s,%.o,${patsubst %.s79,%.o,$(1)}} +CONTIKI_TARGET_SOURCEFILES += $(PROP_SYS_ARCH_C) $(PROP_USB_ARCH) $(CONTIKI_CPU_ARCH) $(CONTIKI_CPU_PORT) $(ELFLOADER) $(UIPDRIVERS) $(STM32L1XX_HAL) +CONTIKI_SOURCEFILES += $(CONTIKI_TARGET_SOURCEFILES) +PROJECT_OBJECTFILES += ${addprefix $(OBJECTDIR)/,$(CONTIKI_TARGET_MAIN:.c=.o)} +PROJECT_OBJECTFILES += ${addprefix $(OBJECTDIR)/,${call ssubst, $(PROP_SYS_ARCH_S)}} +#CONTIKI_OBJECTFILES += ${addprefix $(OBJECTDIR)/,${call ssubst, $(PROP_SYS_ARCH_S)}} + +#------------------------------------------------ defines common for IAR and GCC +# set CPU speed in Hz, NB this might have unexpected side-effects if not at 32 +# Mhz as it is not immediately clear how specialized the startup code etc is. +# That being said, setting to 24MHz seems to work fine, looking at Contiki clocks +# at least. +F_CPU = 32000000 + +CFLAGS+=\ + -DHSE_VALUE=$(F_CPU)ul \ + -DUSE_STDPERIPH_DRIVER \ + -DSTM32L1XX_MD \ + -DIAR_ARM_CM3 \ + -DVECT_TAB_FLASH \ + -DWITH_UIP6 + +# ------------------------------------------------------------------ Build rules +CUSTOM_RULE_C_TO_CE=yes +CUSTOM_RULE_C_TO_CO=yes +CUSTOM_RULE_C_TO_O=yes +CUSTOM_RULE_S_TO_OBJECTDIR_O=yes +CUSTOM_RULE_LINK=yes + +%.o: %.c + $(CC) $(CFLAGS) $< -o $@ + +%.o: %.s + $(AS) $(ASFLAGS) $< -o $@ + +define FINALIZE_CYGWIN_DEPENDENCY +sed -e 's/ \([A-Z]\):\\/ \/cygdrive\/\L\1\//' -e 's/\\\([^ ]\)/\/\1/g' \ + <$(@:.o=.P) >$(@:.o=.d); \ +rm -f $(@:.o=.P) +endef + +$(OBJECTDIR)/%.o: %.s + $(AS) $(ASFLAGS) $< -o $@ + +%.ce: %.o + $(LD) $(LDFLAGS) --relocatable -T $(CONTIKI_CPU)/merge-rodata.ld $< -o $@ $(LDLIBS) + $(STRIP) -K _init -K _fini --strip-unneeded -g -x $@ + +%-stripped.o: %.c + $(CC) $(CFLAGS) $< -o $@ + $(STRIP) --strip $@ + +%-stripped.o: %.o + $(STRIP) --strip $@ $< + +%.o: ${CONTIKI_TARGET}/loader/%.S + $(AS) -o $(notdir $(<:.S=.o)) $< + +ifdef IAR +%.$(TARGET): %.co $(PROJECT_OBJECTFILES) contiki-$(TARGET).a $(STARTUPFOLDER) # $(OBJECTDIR)/empty-symbols.o + $(LD) $(LDFLAGS) -o $@ $(filter-out %.a,$^) $(filter %.a,$^) $(LDLIBS) +else +#CONTIKI_CPU_OBJS=$(CONTIKI_CPU_PORT:%.c=obj_stm32nucleo-spirit1/%.o) +CONTIKI_CPU_OBJS=$(CONTIKI_CPU_PORT:%.c=$(OBJECTDIR)/%.o) +%.$(TARGET): %.co $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) contiki-$(TARGET).a $(OBJECTDIR)/symbols.o + $(TRACE_LD) + $(Q)$(LD) $(LDFLAGS) $(TARGET_STARTFILES) ${filter-out %.a,$^} -Wl,-\( ${filter %.a,$^} $(TARGET_LIBFILES) -Wl,-\) $(CONTIKI_CPU_OBJS) -o $@ + @echo >> contiki-$(TARGET).map + @$(SIZE) $(SIZEFLAGS) $@ >> contiki-$(TARGET).map +endif + +%.hex: %.ihex + # @rm $*.hex + @mv -f $*.ihex $*.hex + +.PHONY: symbols.c + +symbols.c: + cp ${CONTIKI}/tools/empty-symbols.c symbols.c + cp ${CONTIKI}/tools/empty-symbols.h symbols.h + +# Don't use core/loader/elfloader.c, use elfloader-otf.c instead +$(OBJECTDIR)/elfloader.o: + echo -n >$@ + diff --git a/cpu/arm/stm32l152/Makefile.stm32l152.gnu b/cpu/arm/stm32l152/Makefile.stm32l152.gnu new file mode 100644 index 000000000..bb72d88f8 --- /dev/null +++ b/cpu/arm/stm32l152/Makefile.stm32l152.gnu @@ -0,0 +1,65 @@ +PROP_SYS_ARCH_S = startup_stm32l152xe.s + +### Compiler definitions +GCC = 1 +CC = arm-none-eabi-gcc +LD = arm-none-eabi-gcc +SIZE = arm-none-eabi-size +AS = arm-none-eabi-as +AR = arm-none-eabi-ar +NM = arm-none-eabi-nm +OBJCOPY = arm-none-eabi-objcopy +STRIP = arm-none-eabi-strip + +%.ihex: %.$(TARGET) + $(OBJCOPY) -O ihex $^ $@ +%.bin: %.$(TARGET) + $(OBJCOPY) -O binary $^ $@ +%.co: %.c + $(CC) $(CFLAGS) -c -DAUTOSTART_ENABLE $< -o $@ + + +ifndef LDSCRIPT +LDSCRIPT = $(CONTIKI_CPU)/STM32L152RETx_FLASH.ld +endif + +#ASFLAGS += -mcpu=cortex-m3 -mthumb + +# this platform wields a STM32L152VB medium-density device +CFLAGS+=-DSTM32L1XX_MD=1 + +CFLAGS+=\ + -I$(CONTIKI)/cpu/arm/common/CMSIS \ + -Wall -g -O0 \ + -DWITH_UIP -DWITH_ASCII \ + -mcpu=cortex-m3 \ + -mthumb \ + -mno-unaligned-access \ + -mfix-cortex-m3-ldrd \ + -std=gnu99 \ + -Wl,-cref \ + -D __SOURCEFILE__=\"$*.c\" + + +LDFLAGS += -Wl,-Map=contiki-$(TARGET).map,--cref,--no-warn-mismatch + + +LDLIBS += $(CONTIKI_CPU)/smallprintf_thumb2.a + + + +LDFLAGS += -mcpu=cortex-m3 -mthumb -mfloat-abi=soft -T$(LDSCRIPT) -Wl,-Map=output.map -Wl,--gc-sections -lm + + +LDFLAGS += $(LDLIBS) + +SMALL=1 +ifeq ($(SMALL),1) +CFLAGS += -ffunction-sections +CFLAGS += -fdata-sections + +LDFLAGS += -Wl,--undefined=_reset_vector__,--undefined=InterruptVectors,--undefined=_copy_data_init__,--undefined=_clear_bss_init__,--undefined=_end_of_init__ + +endif # /SMALL + + diff --git a/cpu/arm/stm32l152/Makefile.stm32l152.iar b/cpu/arm/stm32l152/Makefile.stm32l152.iar new file mode 100644 index 000000000..17165b748 --- /dev/null +++ b/cpu/arm/stm32l152/Makefile.stm32l152.iar @@ -0,0 +1,86 @@ +PROP_SYS_ARCH_S = \ + startup_stm32l152xe-IAR.s + + +# Compiler definitions +IAR = 1 +CC = iccarm +LD = ilinkarm +AS = iasmarm +AR = iarchive +OBJCOPY = ielftool +STRIP = iobjmanip +SIZE = +NM = + +%.ihex: %.$(TARGET) + $(OBJCOPY) $^ --ihex $@ +%.bin: %.$(TARGET) + $(OBJCOPY) --bin $@ + + +# Find the path to compiler; this works with cygwin +ifndef IAR_PATH +IAR_BIN_PATH := $(shell dirname "`which $(CC)`") +IAR_PATH_C := $(shell dirname "$(IAR_BIN_PATH)") +IAR_PATH := $(shell cygpath -m "$(IAR_PATH_C)") +endif + +# ------------compiler flags +CFLAGS+=\ + -I"$(IAR_PATH)/CMSIS/Include" \ + --diag_suppress Pa050 \ + --no_unroll \ + --no_inline \ + --no_tbaa \ + --no_scheduling \ + --debug \ + --endian=little \ + --cpu=Cortex-M3 \ + -Om \ + -e \ + --fpu=None \ + --dlib_config "$(IAR_PATH)/inc/c/DLib_Config_Normal.h" \ + -DIAR=1 \ + -DWITH_USB_PRINTF=1 + +# -I$(CONTIKI)/cpu/arm/common/CMSIS \ + +# ------------assembler flags +ASFLAGS+= -s+ -r -DIAR_ARM_CM3 -cAOM -B -t8 --cpu Cortex-M3 --fpu None + +#iasmarm -s+ -w+ -r -DIAR_ARM_CM3 -cAOM -B -t8 --cpu Cortex-M3 --fpu None startup_stm32l1xx_md.s + +# ------------archive creation flags +AROPTS= --create --output + +# ----------linker flags +# this will also generate log and symbol map files +#MGR: check which +ICF_FILE="$(CONTIKI_CPU)/stm32l1xx_flash.icf" +LDFLAGS+= \ + --config $(ICF_FILE) \ + --entry __iar_program_start \ + --redirect _Printf=_PrintfLarge \ + --redirect _Scanf=_ScanfLarge \ + --semihosting \ + --no_exceptions \ + --no_remove \ + --cpu=Cortex-M3 \ + --log libraries,initialization,modules,redirects,sections,veneers,unused_fragments \ + --log_file contiki-$(TARGET).log \ + --map contiki-$(TARGET).map \ + --vfe + +CUSTOM_RULE_C_TO_OBJECTDIR_O=yes +$(OBJECTDIR)/%.o: %.c | $(OBJECTDIR) + $(CC) $(CFLAGS) --dependencies=m $(@:.o=.P) $< -o $@ +ifeq ($(HOST_OS),Windows) + @$(FINALIZE_CYGWIN_DEPENDENCY) +endif + +%.co: %.c + $(CC) $(CFLAGS) -DAUTOSTART_ENABLE $< -o $@ + + + diff --git a/cpu/arm/stm32l152/STM32L152RETx_FLASH.ld b/cpu/arm/stm32l152/STM32L152RETx_FLASH.ld new file mode 100644 index 000000000..7de0e5c58 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L152RETx_FLASH.ld @@ -0,0 +1,169 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L152RETx Device with +** 512KByte FLASH, 80KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20014000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h new file mode 100644 index 000000000..f6f71d969 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h @@ -0,0 +1,955 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_H +#define __STM32L1xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_conf.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ + +#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) +#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0) +#if defined(FSMC_R_BASE) +#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1) +#endif /* FSMC_R_BASE */ +#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RI_Constants RI: Routing Interface + * @{ + */ + +/** @defgroup RI_InputCapture Input Capture + * @{ + */ + +#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ +#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ +#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ +#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ + +/** + * @} + */ + +/** @defgroup TIM_Select TIM Select + * @{ + */ + +#define TIM_SELECT_NONE ((uint32_t)0x00000000) /*!< None selected */ +#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */ +#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */ +#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */ + +#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \ + ((__TIM__) == TIM_SELECT_TIM2) || \ + ((__TIM__) == TIM_SELECT_TIM3) || \ + ((__TIM__) == TIM_SELECT_TIM4)) + +/** + * @} + */ + +/** @defgroup RI_InputCaptureRouting Input Capture Routing + * @{ + */ + /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ +#define RI_INPUTCAPTUREROUTING_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */ +#define RI_INPUTCAPTUREROUTING_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */ +#define RI_INPUTCAPTUREROUTING_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */ +#define RI_INPUTCAPTUREROUTING_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */ +#define RI_INPUTCAPTUREROUTING_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */ +#define RI_INPUTCAPTUREROUTING_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */ +#define RI_INPUTCAPTUREROUTING_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */ +#define RI_INPUTCAPTUREROUTING_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */ +#define RI_INPUTCAPTUREROUTING_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */ +#define RI_INPUTCAPTUREROUTING_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */ +#define RI_INPUTCAPTUREROUTING_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */ +#define RI_INPUTCAPTUREROUTING_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */ +#define RI_INPUTCAPTUREROUTING_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */ +#define RI_INPUTCAPTUREROUTING_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */ +#define RI_INPUTCAPTUREROUTING_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */ +#define RI_INPUTCAPTUREROUTING_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */ + +#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15)) + +/** + * @} + */ + +/** @defgroup RI_IOSwitch IO Switch + * @{ + */ +#define RI_ASCR1_REGISTER ((uint32_t)0x80000000) +/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ +#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0) +#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1) +#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2) +#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3) +#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4) +#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5) +#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6) +#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7) +#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8) +#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9) +#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10) +#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11) +#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12) +#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13) +#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14) +#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15) +#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18) +#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19) +#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20) +#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21) +#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22) +#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23) +#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24) +#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25) +#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */ +#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ +#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27) +#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28) +#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29) +#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30) +#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31) +#endif /* RI_ASCR2_CH1b */ + +/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ +#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1) +#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2) +#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3) +#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4) +#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1) +#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2) +#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1) +#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2) +#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3) +#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1) +#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2) +#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3) +#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */ +#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b) +#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ +#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b) +#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b) +#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b) +#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b) +#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b) +#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b) +#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b) +#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b) +#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b) +#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b) +#endif /* RI_ASCR2_CH1b */ +#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3) +#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4) +#endif /* RI_ASCR2_CH0b */ + + +#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ + +#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ + ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12b)) + +#else /* !RI_ASCR2_CH1b */ + +#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */ + +#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ + ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b)) + +#else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */ + +#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ + ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)) + +#endif /* RI_ASCR2_CH0b */ +#endif /* RI_ASCR2_CH1b */ + +/** + * @} + */ + +/** @defgroup RI_Pin PIN define + * @{ + */ +#define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU + * @{ + */ + +/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode + * @brief Freeze/Unfreeze Peripherals in Debug mode + * @{ + */ + +/** + * @brief TIM2 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_FREEZE_TIM2_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_UNFREEZE_TIM2_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#endif + +/** + * @brief TIM3 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_FREEZE_TIM3_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_UNFREEZE_TIM3_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#endif + +/** + * @brief TIM4 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define __HAL_FREEZE_TIM4_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define __HAL_UNFREEZE_TIM4_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#endif + +/** + * @brief TIM5 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#define __HAL_FREEZE_TIM5_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#define __HAL_UNFREEZE_TIM5_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#endif + +/** + * @brief TIM6 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_FREEZE_TIM6_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_UNFREEZE_TIM6_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#endif + +/** + * @brief TIM7 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_FREEZE_TIM7_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_UNFREEZE_TIM7_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#endif + +/** + * @brief RTC Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_FREEZE_RTC_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_UNFREEZE_RTC_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#endif + +/** + * @brief WWDG Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_FREEZE_WWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_UNFREEZE_WWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#endif + +/** + * @brief IWDG Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_FREEZE_IWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_UNFREEZE_IWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#endif + +/** + * @brief I2C1 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#endif + +/** + * @brief I2C2 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#endif + +/** + * @brief TIM9 Peripherals Debug mode + */ +#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#define __HAL_FREEZE_TIM9_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#define __HAL_UNFREEZE_TIM9_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#endif + +/** + * @brief TIM10 Peripherals Debug mode + */ +#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define __HAL_FREEZE_TIM10_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define __HAL_UNFREEZE_TIM10_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#endif + +/** + * @brief TIM11 Peripherals Debug mode + */ +#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#define __HAL_FREEZE_TIM11_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#define __HAL_UNFREEZE_TIM11_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#endif + +/** + * @brief Enables or disables the output of internal reference voltage + * (VREFINT) on I/O pin. + * The VREFINT output can be routed to any I/O in group 3: + * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). + * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). + * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), + * CH1b (PF11) or CH2b (PF12). + * Note: Comparator peripheral clock must be preliminarility enabled, + * either in COMP user function "HAL_COMP_MspInit()" (should be + * done if comparators are used) or by direct clock enable: + * Refer to macro "__COMP_CLK_ENABLE()". + * Note: In addition with this macro, Vrefint output buffer must be + * connected to the selected I/O pin. Refer to macro + * "__HAL_RI_IOSWITCH_CLOSE()". + * @note ENABLE: Internal reference voltage connected to I/O group 3 + * @note DISABLE: Internal reference voltage disconnected from I/O group 3 + * @retval None + */ +#define __HAL_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) +#define __HAL_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG + * @{ + */ + +/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration + * @{ + */ + +/** + * @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) + +#if defined(FSMC_R_BASE) +/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) + +#endif /* FSMC_R_BASE */ + +/** + * @brief Returns the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg SYSCFG_BOOT_MAINFLASH + * @arg SYSCFG_BOOT_SYSTEMFLASH + * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD) + * @arg SYSCFG_BOOT_SRAM + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE) + +/** + * @} + */ + +/** @defgroup SYSCFG_USBConfig USB DP line Configuration + * @{ + */ + +/** + * @brief Control the internal pull-up on USB DP line. + */ +#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) + +#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RI_Macris RI: Routing Interface + * @{ + */ + +/** @defgroup RI_InputCaputureConfig Input Capture configuration + * @{ + */ + +/** + * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin. + * @param __TIMSELECT__: Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__: selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * e.g. + * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1) + * allows routing of Input capture IC1 of TIM2 to PA4. + * For details about correspondence between RI_INPUTCAPTUREROUTING_x + * and I/O pins refer to the parameters' description in the header file + * or refer to the product reference manual. + * @note Input capture selection bits are not reset by this function. + * To reset input capture selection bits, use SYSCFG_RIDeInit() function. + * @note The I/O should be configured in alternate function mode (AF14) using + * GPIO_PinAFConfig() function. + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \ + MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \ + }while(0) + +/** + * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin. + * @param __TIMSELECT__: Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__: selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \ + MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \ + }while(0) + +/** + * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin. + * @param __TIMSELECT__: Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__: selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \ + MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \ + }while(0) + +/** + * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin. + * @param __TIMSELECT__: Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__: selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \ + MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \ + }while(0) + +/** + * @} + */ + +/** @defgroup RI_SwitchControlConfig Switch Control configuration + * @{ + */ + +/** + * @brief Enable or disable the switch control mode. + * @note ENABLE: ADC analog switches closed if the corresponding + * I/O switch is also closed. + * When using COMP1, switch control mode must be enabled. + * @note DISABLE: ADC analog switches open or controlled by the ADC interface. + * When using the ADC for acquisition, switch control mode + * must be disabled. + * @note COMP1 comparator and ADC cannot be used at the same time since + * they share the ADC switch matrix. + * @retval None + */ +#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM) + +#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM) + +/* + * @brief Close or Open the routing interface Input Output switches. + * @param __IOSWITCH__: selects the I/O analog switch number. + * This parameter must be a value of @ref RI_IOSwitch + * @retval None + */ +#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ + if ((__IOSWITCH__) >> 31 != 0 ) \ + { \ + SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ + } \ + else \ + { \ + SET_BIT(RI->ASCR2, (__IOSWITCH__)); \ + } \ + }while(0) + +#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ + if ((__IOSWITCH__) >> 31 != 0 ) \ + { \ + CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ + } \ + else \ + { \ + CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \ + } \ + }while(0) + +#if defined (COMP_CSR_SW1) +/** + * @brief Close or open the internal switch COMP1_SW1. + * This switch connects I/O pin PC3 (can be used as ADC channel 13) + * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel + * 26) and COMP1 non-inverting input. + * Pin PC3 connection depends on another switch setting, refer to + * macro "__HAL_ADC_CHANNEL_SPEED_FAST()". + * @retval None. + */ +#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1) + +#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1) +#endif /* COMP_CSR_SW1 */ + +/** + * @} + */ + +/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation + * @{ + */ + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR1, (__IOPIN__)); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR2, (__IOPIN__)); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ + } while(0) + +#if defined (GPIOE_BASE) + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR3, (__IOPIN__)); \ + } while(0) + +#endif /* GPIOE_BASE */ + +#if defined(GPIOF_BASE) || defined(GPIOG_BASE) + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR4, (__IOPIN__)); \ + } while(0) + +#endif /* GPIOF_BASE || GPIOG_BASE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(__IO uint32_t Delay); +uint32_t HAL_GetTick(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +void HAL_EnableDBGSleepMode(void); +void HAL_DisableDBGSleepMode(void); +void HAL_EnableDBGStopMode(void); +void HAL_DisableDBGStopMode(void); +void HAL_EnableDBGStandbyMode(void); +void HAL_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h new file mode 100644 index 000000000..e4f548339 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h @@ -0,0 +1,1107 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_adc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file containing functions prototypes of ADC HAL library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_ADC_H +#define __STM32L1xx_HAL_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC and regular group initialization + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. + * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. + * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler. + This parameter can be a value of @ref ADC_ClockPrescaler + Note: In case of usage of channels on injected group, ADC frequency should be low than AHB clock frequency /4 for resolution 12 or 10 bits, + AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. + Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */ + uint32_t Resolution; /*!< Configures the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) + or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). + This parameter can be a value of @ref ADC_Data_align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). + Scan direction is upward: from rank1 to rank 'n'. + This parameter can be a value of @ref ADC_Scan_mode */ + uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. + This parameter can be a value of @ref ADC_EOCSelection. + Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. + Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) + or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. + Note: If overrun feature is intending to be used in ADC mode 'interruption' (function HAL_ADC_Start_IT() ), parameter EOCSelection must be set to each conversion (this is not needed for ADC mode 'transfer by DMA', with function HAL_ADC_Start_DMA()) */ + uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous + conversion (for regular group) or previous sequence (for injected group) has been treated by user software. + This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. + This parameter can be a value of @ref ADC_LowPowerAutoWait. + Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed + and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. + Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */ + uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). + This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */ + uint32_t ChannelsBank; /*!< Selects the ADC channels bank. + This parameter can be a value of @ref ADC_ChannelsBank. + Note: Banks availability depends on devices categories. + Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */ + uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. + To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 28. */ +#else + uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. + To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 27. */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADC_External_trigger_source_Regular */ + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. + If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ + uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */ +}ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC can be either disabled or enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. + Maximum number of channels by device category (without taking in account each device package constraints): + STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26. + STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. + STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. + Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '. + Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */ + uint32_t Rank; /*!< Specifies the rank in the regular group sequencer + This parameter can be a value of @ref ADC_regular_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ +}ADC_ChannelConfTypeDef; + +/** + * @brief ADC Configuration analog watchdog definition + * @note The setting of these parameters with function is conditioned to ADC state. + * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. + */ +typedef struct +{ + uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. + This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) + This parameter can be a value of @ref ADC_channels. */ + uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC States structure definition + */ +typedef enum +{ + HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ + HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ + HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ + HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ + HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ + HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ + HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ + HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ + HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ + HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ + HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ + HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32L1xx devices (kept for compatibility with other devices featuring several AWD) */ + HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32l1xx devices (kept for compatibility with other devices featuring several AWD) */ +}HAL_ADC_StateTypeDef; + +/** + * @brief ADC handle Structure definition + */ +typedef struct +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ +}ADC_HandleTypeDef; +/** + * @} + */ + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ + +/** + * @} + */ + +/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler + * @{ + */ +#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */ +#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */ + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) ) +/** + * @} + */ + +/** @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */ +#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */ +#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */ + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ + ((RESOLUTION) == ADC_RESOLUTION10b) || \ + ((RESOLUTION) == ADC_RESOLUTION8b) || \ + ((RESOLUTION) == ADC_RESOLUTION6b) ) + +#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \ + ((RESOLUTION) == ADC_RESOLUTION6b) ) +/** + * @} + */ + +/** @defgroup ADC_Data_align ADC Data_align + * @{ + */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC Scan mode + * @{ + */ +#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) +#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ + ((SCAN_MODE) == ADC_SCAN_ENABLE) ) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular + * @{ + */ +/* List of external triggers with generic trigger name, sorted by trigger */ +/* name: */ + +/* External triggers of regular group for ADC1 */ +#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3 +#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2 +#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO +#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1 +#define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3 +#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO +#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4 +#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO +#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO +#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2 +#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO +#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 + +#define ADC_SOFTWARE_START ((uint32_t)0x00000010) + +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) +/** + * @} + */ + +/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular + * @{ + */ + +/* List of external triggers of regular group for ADC1: */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ + +/* External triggers of regular group for ADC1 */ +#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000) +#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) +#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 )) +#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) +#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 )) +#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 )) +#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) + +/** + * @} + */ + +/** @defgroup ADC_EOCSelection ADC EOCSelection + * @{ + */ +#define EOC_SEQ_CONV ((uint32_t)0x00000000) +#define EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS) + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == EOC_SEQ_CONV) ) +/** + * @} + */ + +/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait + * @{ + */ +/*!< Note : For compatibility with other STM32 devices with ADC autowait */ +/* feature limited to enable or disable settings: */ +/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */ + +#define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000) +#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */ +#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */ +#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */ +#define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */ +#define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */ +#define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */ +#define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */ + +#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \ + ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) ) +/** + * @} + */ + +/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff + * @{ + */ +#define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000) +#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */ +#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */ +#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */ + +#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \ + ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \ + ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \ + ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) ) +/** + * @} + */ + + +/** @defgroup ADC_ChannelsBank ADC ChannelsBank + * @{ + */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) +#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) + +#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ + ((BANK) == ADC_CHANNELS_BANK_B) ) +#else +#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) + +#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup ADC_channels ADC channels + * @{ + */ +/* Note: Depending on devices, some channels may not be available on package */ +/* pins. Refer to device datasheet for channels availability. */ +#define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */ +#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ +#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */ +#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */ +#define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ +#define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */ +#define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ +#define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ +#define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ +#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ +#define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */ +#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) +#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_19) || \ + ((CHANNEL) == ADC_CHANNEL_20) || \ + ((CHANNEL) == ADC_CHANNEL_21) || \ + ((CHANNEL) == ADC_CHANNEL_22) || \ + ((CHANNEL) == ADC_CHANNEL_23) || \ + ((CHANNEL) == ADC_CHANNEL_24) || \ + ((CHANNEL) == ADC_CHANNEL_25) || \ + ((CHANNEL) == ADC_CHANNEL_26) ) +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_19) || \ + ((CHANNEL) == ADC_CHANNEL_20) || \ + ((CHANNEL) == ADC_CHANNEL_21) || \ + ((CHANNEL) == ADC_CHANNEL_22) || \ + ((CHANNEL) == ADC_CHANNEL_23) || \ + ((CHANNEL) == ADC_CHANNEL_24) || \ + ((CHANNEL) == ADC_CHANNEL_25) || \ + ((CHANNEL) == ADC_CHANNEL_26) || \ + ((CHANNEL) == ADC_CHANNEL_27) || \ + ((CHANNEL) == ADC_CHANNEL_28) || \ + ((CHANNEL) == ADC_CHANNEL_29) || \ + ((CHANNEL) == ADC_CHANNEL_30) || \ + ((CHANNEL) == ADC_CHANNEL_31) ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup ADC_sampling_times ADC sampling times + * @{ + */ +#define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /*!< Sampling time 4 ADC clock cycles */ +#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */ +#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */ +#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */ +#define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */ +#define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */ +#define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */ +#define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */ + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_9CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_16CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_24CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_48CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_96CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_192CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_384CYCLES) ) +/** + * @} + */ + +/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels + * @{ + */ +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \ + (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \ + ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \ + ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ + (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \ + ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \ + ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2) +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ + (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \ + ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ + (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \ + ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \ + ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \ + (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \ + (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \ + ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \ + ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ + (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \ + ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \ + ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1) +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ + (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \ + ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ + (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \ + ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \ + ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \ + (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \ + (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \ + ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \ + ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ + (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \ + ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \ + ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0) +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ + (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \ + ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ + (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \ + ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \ + ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) +#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \ + (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup ADC_regular_rank ADC regular rank + * @{ + */ +#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) +#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) +#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) +#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) +#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) +#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) +#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) +#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) +#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) +#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) +#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) +#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) +#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) +#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) +#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) +#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) +#define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011) +#define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012) +#define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013) +#define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014) +#define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015) +#define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016) +#define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017) +#define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018) +#define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019) +#define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A) +#define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B) +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C) + +#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_10) || \ + ((CHANNEL) == ADC_REGULAR_RANK_11) || \ + ((CHANNEL) == ADC_REGULAR_RANK_12) || \ + ((CHANNEL) == ADC_REGULAR_RANK_13) || \ + ((CHANNEL) == ADC_REGULAR_RANK_14) || \ + ((CHANNEL) == ADC_REGULAR_RANK_15) || \ + ((CHANNEL) == ADC_REGULAR_RANK_16) || \ + ((CHANNEL) == ADC_REGULAR_RANK_17) || \ + ((CHANNEL) == ADC_REGULAR_RANK_18) || \ + ((CHANNEL) == ADC_REGULAR_RANK_19) || \ + ((CHANNEL) == ADC_REGULAR_RANK_20) || \ + ((CHANNEL) == ADC_REGULAR_RANK_21) || \ + ((CHANNEL) == ADC_REGULAR_RANK_22) || \ + ((CHANNEL) == ADC_REGULAR_RANK_23) || \ + ((CHANNEL) == ADC_REGULAR_RANK_24) || \ + ((CHANNEL) == ADC_REGULAR_RANK_25) || \ + ((CHANNEL) == ADC_REGULAR_RANK_26) || \ + ((CHANNEL) == ADC_REGULAR_RANK_27) || \ + ((CHANNEL) == ADC_REGULAR_RANK_28) ) +#else + +#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ + ((CHANNEL) == ADC_REGULAR_RANK_10) || \ + ((CHANNEL) == ADC_REGULAR_RANK_11) || \ + ((CHANNEL) == ADC_REGULAR_RANK_12) || \ + ((CHANNEL) == ADC_REGULAR_RANK_13) || \ + ((CHANNEL) == ADC_REGULAR_RANK_14) || \ + ((CHANNEL) == ADC_REGULAR_RANK_15) || \ + ((CHANNEL) == ADC_REGULAR_RANK_16) || \ + ((CHANNEL) == ADC_REGULAR_RANK_17) || \ + ((CHANNEL) == ADC_REGULAR_RANK_18) || \ + ((CHANNEL) == ADC_REGULAR_RANK_19) || \ + ((CHANNEL) == ADC_REGULAR_RANK_20) || \ + ((CHANNEL) == ADC_REGULAR_RANK_21) || \ + ((CHANNEL) == ADC_REGULAR_RANK_22) || \ + ((CHANNEL) == ADC_REGULAR_RANK_23) || \ + ((CHANNEL) == ADC_REGULAR_RANK_24) || \ + ((CHANNEL) == ADC_REGULAR_RANK_25) || \ + ((CHANNEL) == ADC_REGULAR_RANK_26) || \ + ((CHANNEL) == ADC_REGULAR_RANK_27) ) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) +#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) +/** + * @} + */ + +/** @defgroup ADC_conversion_group ADC conversion group + * @{ + */ +#define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) +#define INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) +#define REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) + +#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP) || \ + ((CONVERSION) == INJECTED_GROUP) || \ + ((CONVERSION) == REGULAR_INJECTED_GROUP) ) +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ +#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ + ((EVENT) == ADC_FLAG_OVR) ) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ +#define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */ +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ +#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ +#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ +#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ +#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ +#define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */ +#define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */ +#define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Regular group ready status flag */ + +/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \ + ADC_FLAG_OVR) +/** + * @} + */ + +/** @defgroup ADC_range_verification ADC range verification + * For a unique ADC resolution: 12 bits + * @{ + */ +#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF)) +/** + * @} + */ + +/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification + * @{ + */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28))) +#else +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27))) +#endif +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification + * @{ + */ +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +#define __HAL_ADC_IS_ENABLED(__HANDLE__) \ + ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__: ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC interrupt source to check + * @retval State of interruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (( ((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__) \ + )? SET : RESET \ + ) + +/** + * @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) + +/** + * @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) + +/** + * @brief Get the selected ADC's flag status. + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the ADC's pending flags + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * @retval None + */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +/** @brief Reset ADC handle state + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) + +/** + * @} + */ + +/* Include ADC HAL Extension module */ +#include "stm32l1xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + */ + + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +/** + * @} + */ + +/* IO operation functions *****************************************************/ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @{ + */ + + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +/** + * @} + */ + + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/** + * @} + */ + + +/* Internal HAL driver functions **********************************************/ +/** @addtogroup ADC_Private_Functions + * @{ + */ + +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_ADC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h new file mode 100644 index 000000000..255a1051d --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h @@ -0,0 +1,693 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_adc_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of ADC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_ADC_EX_H +#define __STM32L1xx_HAL_ADC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADCEx Exported Types + * @{ + */ + +/** + * @brief ADC Configuration injected Channel structure definition + * @note Parameters of this structure are shared within 2 scopes: + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset + * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, + * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. + * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. + * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. + */ +typedef struct +{ + uint32_t InjectedChannel; /*!< Selection of ADC channel to configure + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ + uint32_t InjectedRank; /*!< Rank in the injected group sequencer + This parameter must be a value of @ref ADCEx_injected_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. + To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. + To maintain JAUTO always enabled, DMA must be configured in circular mode. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADCEx_External_trigger_source_Injected + Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. + This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. + If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ +}ADC_InjectionConfTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants + * @{ + */ + +/** @defgroup ADCEx_injected_rank ADCEx injected rank + * @{ + */ +#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) +#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) +#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) +#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) + +#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ + ((CHANNEL) == ADC_INJECTED_RANK_2) || \ + ((CHANNEL) == ADC_INJECTED_RANK_3) || \ + ((CHANNEL) == ADC_INJECTED_RANK_4) ) +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx External trigger edge Injected + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) + +#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected + * @{ + */ +/* External triggers for injected groups of ADC1 */ +#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 +#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO +#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 +#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO +#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1 +#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2 +#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3 +#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO +#define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1 +#define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO +#define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 +#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 + +#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000010) + +#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) +/** + * @} + */ + +/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected + * @{ + */ + +/* List of external triggers of injected group for ADC1: */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ +#define ADC_EXTERNALTRIGINJEC_T9_CC1 ((uint32_t) 0x00000000) +#define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) +#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 )) +#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) +#define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 )) +#define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) +#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) + +/** + * @} + */ + + +/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification + * @{ + */ +#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** + * @brief Selection of channels bank. + * Note: Banks availability depends on devices categories. + * This macro is intended to change bank selection quickly on the fly, + * without going through ADC init structure update and execution of function + * 'HAL_ADC_Init()'. + * @param __HANDLE__: ADC handle + * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank. + * @retval None + */ +#define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Configures the ADC channels speed. + * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. + * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is + * in power down mode. + * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is + * in power down mode. + * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in + * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and + * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. + * (Note: OPAMP3 is available on STM32L1 Cat.4 only). + * @param __CHANNEL__: ADC channel + * This parameter can be one of the following values: + * @arg ADC_CHANNEL_3: Channel 3 is selected. + * @arg ADC_CHANNEL_8: Channel 8 is selected. + * @arg ADC_CHANNEL_13: Channel 13 is selected. + * @retval None + */ +#define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \ + ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ + )? \ + (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \ + : \ + ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ + )? \ + (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \ + : \ + ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ + )? \ + (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \ + : \ + (SET_BIT(COMP->CSR, 0x00000000)) \ + ) \ + ) \ + ) + +#define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \ + ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ + )? \ + (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \ + : \ + ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ + )? \ + (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \ + : \ + ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ + )? \ + (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \ + : \ + (SET_BIT(COMP->CSR, 0x00000000)) \ + ) \ + ) \ + ) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +/* Private macro ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macro ADCEx Private Macro + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Set ADC number of ranks into regular channel sequence length. + * @param _NbrOfConversion_: Regular channel sequence length + * @retval None + */ +#define __ADC_SQR1_L(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) + +/** + * @brief Set ADC ranks available in register SQR1. + * Register SQR1 bits availability depends on device category. + * @param _NbrOfConversion_: Regular channel sequence length + * @retval None + */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __ADC_SQR1_SQXX ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25 +#else +#define __ADC_SQR1_SQXX ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25 +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Set the ADC's sample time for channel numbers between 30 and 31. + * Register SMPR0 availability depends on device category. If register is not + * available on the current device, this macro does nothing. + * @retval None + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) +#else +#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((uint32_t)0x00000000) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Set the ADC's sample time for channel numbers between 20 and 29. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) +#else +/** + * @brief Set the ADC's sample time for channel numbers between 20 and 26. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Defines the highest channel available in register SMPR1. Channels + * availability depends on device category: + * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3 + * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5 + * @param None + * @retval None + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 +#else +#define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Set the ADC's sample time for channel numbers between 10 and 18. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define __ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) + +/** + * @brief Set the ADC's sample time for channel numbers between 0 and 9. + * @param _SAMPLETIME_: Sample time parameter. + * @param _CHANNELNB_: Channel number. + * @retval None + */ +#define __ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) + +/** + * @brief Set the selected regular channel rank for rank between 1 and 6. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define __ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) + +/** + * @brief Set the selected regular channel rank for rank between 7 and 12. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define __ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) + +/** + * @brief Set the selected regular channel rank for rank between 13 and 18. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define __ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) + +/** + * @brief Set the selected regular channel rank for rank between 19 and 24. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define __ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19))) + +/** + * @brief Set the selected regular channel rank for rank between 25 and 28. + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @retval None + */ +#define __ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25))) + +/** + * @brief Set the injected sequence length. + * @param _JSQR_JL_: Sequence length. + * @retval None + */ +#define __ADC_JSQR_JL(_JSQR_JL_) (((_JSQR_JL_) -1) << 20) + +/** + * @brief Set the selected injected Channel rank (channels sequence starting from 4-JL) + * @param _CHANNELNB_: Channel number. + * @param _RANKNB_: Rank number. + * @param _JSQR_JL_: Sequence length. + * @retval None + */ +#define __ADC_JSQR_RK(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ + ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) + + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @retval None + */ +#define __ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS)) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_: Continuous mode. + * @retval None + */ +#define __ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) + +/** + * @brief Define mask of configuration bits of ADC and regular group in + * register CR2 (bits of ADC enable, conversion start and injected group are + * excluded of this mask). + * @retval None + */ +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __ADC_CR2_MASK_ADCINIT() \ + (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) +#else +#define __ADC_CR2_MASK_ADCINIT() \ + (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) +#endif + +/** + * @brief Configures the number of discontinuous conversions for the regular group channels. + * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. + * @retval None + */ +#define __ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) + +/** + * @brief Enable ADC scan mode to convert multiple ranks with sequencer. + * @param _SCAN_MODE_: Scan conversion mode. + * @retval None + */ +#define __ADC_CR1_SCAN(_SCAN_MODE_) \ + ( ( (_SCAN_MODE_) == (ADC_SCAN_ENABLE) \ + )? (ADC_CR1_SCAN) : (0x00000000) \ + ) + +/** + * @brief Get the maximum ADC conversion cycles on all channels. + * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) + * Approximation of sampling time within 2 ranges, returns the higher value: + * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} + * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} + * Unit: ADC clock cycles + * @param __HANDLE__: ADC handle + * @retval ADC conversion cycles on all channels + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ + (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ + (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ + (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ + (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \ + \ + ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ + ) +#else +#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ + (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ + (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ + (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ + \ + ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ + ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Get the ADC clock prescaler from ADC common control register + * and convert it to its decimal number setting (refer to reference manual) + * @retval None + */ +#define __ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ + ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) + +/** + * @brief Clear register SMPR0. + * Register SMPR0 availability depends on device category. If register is not + * available on the current device, this macro performs no action. + * @param __HANDLE__: ADC handle + * @retval None + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __ADC_SMPR0_CLEAR(__HANDLE__) \ + (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) +#else +#define __ADC_SMPR0_CLEAR(__HANDLE__) __NOP() +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Clear register CR2. + * @param __HANDLE__: ADC handle + * @retval None + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __ADC_CR2_CLEAR(__HANDLE__) \ + (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ + ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ + ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ + ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \ + ADC_CR2_CONT | ADC_CR2_ADON )) \ + ) +#else +#define __ADC_CR2_CLEAR(__HANDLE__) \ + (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ + ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ + ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ + ADC_CR2_DMA | ADC_CR2_DELS | \ + ADC_CR2_CONT | ADC_CR2_ADON )) \ + ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Set the sampling time of selected channel on register SMPR0 + * Register SMPR0 availability depends on device category. If register is not + * available on the current device, this macro performs no action. + * @param __HANDLE__: ADC handle + * @param _SAMPLETIME_: Sample time parameter. + * @param __CHANNEL__: Channel number. + * @retval None + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ + MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ + __ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ + __ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) +#else +#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + +/** + * @brief Enable the ADC peripheral + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __ADC_ENABLE(__HANDLE__) \ + (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON + +/** + * @brief Disable the ADC peripheral + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __ADC_DISABLE(__HANDLE__) \ + (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); +/** + * @} + */ + + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup ADCEx_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_ADC_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h new file mode 100644 index 000000000..39eb773aa --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h @@ -0,0 +1,520 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_comp.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of COMP HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_COMP_H +#define __STM32L1xx_HAL_COMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Types COMP Exported Types + * @{ + */ + +/** + * @brief COMP Init structure definition + */ +typedef struct +{ + + uint32_t InvertingInput; /*!< Selects the inverting input of the comparator. + This parameter can be a value of @ref COMP_InvertingInput + Note: Inverting input can be changed on the fly, while comparator is running. + Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded (On COMP1, inverting input is fixed to Vrefint). */ + + uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator. + This parameter can be a value of @ref COMPEx_NonInvertingInput */ + + uint32_t Output; /*!< Selects the output redirection of the comparator. + This parameter can be a value of @ref COMP_Output + Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */ + + uint32_t Mode; /*!< Selects the operating consumption mode of the comparator + to adjust the speed/consumption. + This parameter can be a value of @ref COMP_Mode + Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */ + + uint32_t WindowMode; /*!< Selects the window mode of the 2 comparators. + If enabled, non-inverting inputs of the 2 comparators are connected together and are using inputs of COMP2 only (COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP). + This parameter can be a value of @ref COMP_WindowMode + Note: This feature must be enabled from COMP2 instance. If COMP1 is selected, this parameter is discarded. */ + + uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator when using interruption on EXTI line (interrupt mode). + This parameter can be a value of @ref COMP_TriggerMode + Note: This feature is used with function "HAL_COMP_Start_IT()". In all other functions, this parameter is discarded. */ + + uint32_t NonInvertingInputPull; /*!< Selects the internal pulling resistor connected on non inverting input. + This parameter can be a value of @ref COMP_NonInvertingInputPull + Note: To avoid extra power consumption, only one resistor should be enabled at a time. + Note: This feature is available on COMP1 only. If COMP2 is selected, this parameter is discarded. */ + +}COMP_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */ + HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */ + HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ + HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */ +}HAL_COMP_StateTypeDef; + +/** + * @brief COMP Handle Structure definition + */ +typedef struct +{ + COMP_TypeDef *Instance; /*!< Register base address */ + COMP_InitTypeDef Init; /*!< COMP required parameters */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ +} COMP_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup COMP_Exported_Constants COMP Exported Constants + * @{ + */ + +/** @defgroup COMP_Output COMP Output + * @{ + */ +#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00000000) /*!< COMP2 output connected to TIM2 Input Capture 4 */ +#define COMP_OUTPUT_TIM2OCREFCLR ( COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC4 ( COMP_CSR_OUTSEL_1 ) /*!< COMP2 output connected to TIM3 Input Capture 4 */ +#define COMP_OUTPUT_TIM3OCREFCLR ( COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM3 OCREF Clear */ +#define COMP_OUTPUT_TIM4IC4 (COMP_CSR_OUTSEL_2 ) /*!< COMP2 output connected to TIM4 Input Capture 4 */ +#define COMP_OUTPUT_TIM4OCREFCLR (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM4 OCREF Clear */ +#define COMP_OUTPUT_TIM10IC1 (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 ) /*!< COMP2 output connected to TIM10 Input Capture 1 */ +#define COMP_OUTPUT_NONE (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output is not connected to other peripherals */ + +#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \ + ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \ + ((OUTPUT) == COMP_OUTPUT_TIM3IC4) || \ + ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \ + ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \ + ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \ + ((OUTPUT) == COMP_OUTPUT_TIM10IC1) || \ + ((OUTPUT) == COMP_OUTPUT_NONE) ) +/** + * @} + */ + +/** @defgroup COMP_InvertingInput COMP InvertingInput + * @{ + */ +/* Inverting Input specific to COMP2 */ +#define COMP_INVERTINGINPUT_IO ( COMP_CSR_INSEL_0) /*!< External I/O (COMP2_INM connected to pin PB3) connected to comparator 2 inverting input */ +#define COMP_INVERTINGINPUT_VREFINT ( COMP_CSR_INSEL_1 ) /*!< VREFINT connected to comparator 2 inverting input */ +#define COMP_INVERTINGINPUT_3_4VREFINT ( COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< 3/4 VREFINT connected to comparator 2 inverting input */ +#define COMP_INVERTINGINPUT_1_2VREFINT (COMP_CSR_INSEL_2 ) /*!< 1/2 VREFINT connected to comparator 2 inverting input */ +#define COMP_INVERTINGINPUT_1_4VREFINT (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_0) /*!< 1/4 VREFINT connected to comparator 2 inverting input */ +#define COMP_INVERTINGINPUT_DAC1 (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1 ) /*!< DAC_OUT1 (PA4) connected to comparator 2 inverting input */ +#define COMP_INVERTINGINPUT_DAC2 (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< DAC2_OUT (PA5) connected to comparator 2 inverting input */ + +#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_IO) || \ + ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC2) ) +/** + * @} + */ + +/** @defgroup COMP_Mode COMP Mode + * @{ + */ +/* Please refer to the electrical characteristics in the device datasheet for + the power consumption values */ +#define COMP_MODE_LOWSPEED ((uint32_t)0x00000000) /*!< Low Speed */ +#define COMP_MODE_HIGHSPEED COMP_CSR_SPEED /*!< High Speed */ + +#define IS_COMP_MODE(SPEED) (((SPEED) == COMP_MODE_LOWSPEED) || \ + ((SPEED) == COMP_MODE_HIGHSPEED)) +/** + * @} + */ + +/** @defgroup COMP_WindowMode COMP WindowMode + * @{ + */ +#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled: COMP1 non-inverting input is independant */ +#define COMP_WINDOWMODE_ENABLED COMP_CSR_WNDWE /*!< Window mode enabled: COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP) (connected to COMP2 non-inverting input) */ + +#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \ + ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED)) +/** + * @} + */ + +/** @defgroup COMP_OutputLevel COMP OutputLevel + * @{ + */ +/* Comparator output is low when the non-inverting input is at a lower */ +/* voltage than the inverting input. */ +#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) + +/* Comparator output is high when the non-inverting input is at a higher */ +/* voltage than the inverting input. */ +#define COMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup COMP_TriggerMode COMP TriggerMode + * @{ + */ +#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */ +#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \ + ((MODE) == COMP_TRIGGERMODE_IT_RISING) || \ + ((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \ + ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING) ) +/** + * @} + */ + +/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent + * @{ + */ +#define COMP_EXTI_LINE_COMP1_EVENT EXTI_RTSR_TR21 /*!< External interrupt line 21 Connected to COMP1 */ +#define COMP_EXTI_LINE_COMP2_EVENT EXTI_RTSR_TR22 /*!< External interrupt line 22 Connected to COMP2 */ + +/** + * @} + */ + +/** @defgroup COMP_NonInvertingInputPull COMP NonInvertingInputPull + * @{ + */ +#define COMP_NONINVERTINGINPUT_NOPULL ((uint32_t)0x00000000) /*!< No internal pull-up or pull-down resistor connected to comparator non inverting input */ +#define COMP_NONINVERTINGINPUT_10KPU COMP_CSR_10KPU /*!< Internal 10kOhm pull-up resistor connected to comparator non inverting input */ +#define COMP_NONINVERTINGINPUT_10KPD COMP_CSR_10KPD /*!< Internal 10kOhm pull-down resistor connected to comparator non inverting input */ +#define COMP_NONINVERTINGINPUT_400KPU COMP_CSR_400KPU /*!< Internal 400kOhm pull-up resistor connected to comparator non inverting input */ +#define COMP_NONINVERTINGINPUT_400KPD COMP_CSR_400KPD /*!< Internal 400kOhm pull-down resistor connected to comparator non inverting input */ + +#define IS_COMP_NONINVERTINGINPUTPULL(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_NOPULL) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_10KPU) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_10KPD) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_400KPU) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_400KPD) ) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Macro COMP Exported Macro + * @{ + */ + +/** @brief Reset COMP handle state + * @param __HANDLE__: COMP handle. + * @retval None + */ +#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) + +/** + * @brief Enables the specified comparator + * @param __HANDLE__: COMP handle. + * @retval None. + */ +#define __HAL_COMP_ENABLE(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance == COMP1) \ + )? \ + SET_BIT(COMP->CSR, COMP_CSR_CMP1EN) \ + : \ + MODIFY_REG(COMP->CSR, COMP_CSR_INSEL, (__HANDLE__)->Init.InvertingInput ) \ + ) + +/** + * @brief Disables the specified comparator + * @param __HANDLE__: COMP handle. + * @retval None. + */ +#define __HAL_COMP_DISABLE(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance == COMP1) \ + )? \ + CLEAR_BIT(COMP->CSR, COMP_CSR_CMP1EN) \ + : \ + CLEAR_BIT(COMP->CSR, COMP_CSR_INSEL) \ + ) + + +/** @brief Checks whether the specified COMP flag is set or not. + * @param __HANDLE__: specifies the COMP Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg COMP_FLAG_LOCK: lock flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->CSR, (__FLAG__)) == (__FLAG__)) + + +/** + * @brief Enable the Exti Line rising edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->RTSR, (__EXTILINE__))) + +/** + * @brief Disable the Exti Line rising edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))) + +/** + * @brief Enable the Exti Line falling edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->FTSR, (__EXTILINE__))) + +/** + * @brief Disable the Exti Line falling edge trigger. + * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))) + +/** + * @brief Get the specified EXTI line for a comparator instance + * @param __INSTANCE__: specifies the COMP instance. + * @retval value of @ref COMP_ExtiLineEvent + */ +#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) \ + ( ( ((__INSTANCE__) == COMP1) \ + )? \ + (COMP_EXTI_LINE_COMP1_EVENT) \ + : \ + (COMP_EXTI_LINE_COMP2_EVENT) \ + ) + +/** + * @brief Enable the COMP Exti Line. + * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (SET_BIT(EXTI->IMR, (__EXTILINE__))) + +/** + * @brief Disable the COMP Exti Line. + * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (CLEAR_BIT(EXTI->IMR, (__EXTILINE__))) + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __FLAG__: specifies the COMP Exti sources to be checked. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval The state of __FLAG__ (SET or RESET). + */ +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (READ_BIT(EXTI->PR, (__FLAG__))) + +/** + * @brief Clear the COMP Exti flags. + * @param __FLAG__: specifies the COMP Exti sources to be cleared. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None. + */ +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTILINE__: specifies the COMP Exti sources to trig. + * This parameter can be a value of @ref COMP_ExtiLineEvent + * @retval None + */ +#define __HAL_COMP_EXTI_GENERATE_SWIT(__EXTILINE__) (SET_BIT(EXTI->SWIER, (__EXTILINE__))) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup COMP_Private_Macro COMP Private Macro + * @{ + */ + +/** + * @brief Select the COMP register CSR bit CMPxOUT corresponding to the + * selected COMP instance. + * @param __HANDLE__: COMP handle + * @retval Comparator register CSR bit COMP_CSR_CMP1OUT or COMP_CSR_CMP2OUT + */ +#define __COMP_CSR_CMPXOUT(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance == COMP1) \ + )? \ + (COMP_CSR_CMP1OUT) \ + : \ + (COMP_CSR_CMP2OUT) \ + ) + +/** + * @brief Verification of COMP state: enabled or disabled + * @param __HANDLE__: COMP handle + * @retval SET (COMP enabled) or RESET (COMP disabled) + */ +#define __COMP_IS_ENABLED(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance == COMP1) \ + )? \ + (((READ_BIT(COMP->CSR , COMP_CSR_CMP1EN) == COMP_CSR_CMP1EN) \ + ) ? SET : RESET) \ + : \ + (((READ_BIT(COMP->CSR , COMP_CSR_INSEL) != RESET) \ + ) ? SET : RESET) \ + ) + +/** + * @} + */ + + +/* Include COMP HAL Extension module */ +#include "stm32l1xx_hal_comp_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +/** @addtogroup COMP_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup COMP_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp); +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup COMP_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); + +/* Callback in Interrupt mode */ +void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/* Peripheral State functions **************************************************/ +/** @addtogroup COMP_Exported_Functions_Group4 + * @{ + */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_COMP_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h new file mode 100644 index 000000000..731c9e45d --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h @@ -0,0 +1,336 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_comp_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of COMP HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_COMP_EX_H +#define __STM32L1xx_HAL_COMP_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup COMPEx COMPEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup COMPEx_Exported_Constants COMPEx Exported Constants + * @{ + */ + +/** @defgroup COMPEx_NonInvertingInput COMPEx NonInvertingInput + * @{ + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/* Non-inverting inputs specific to COMP2 */ +#define COMP_NONINVERTINGINPUT_PB4 RI_IOSWITCH_GR6_1 /*!< I/O pin PB4 connection to COMP2 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB6 RI_IOSWITCH_GR6_3 /*!< I/O pin PB6 connection to COMP2 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB7 RI_IOSWITCH_GR6_4 /*!< I/O pin PB7 connection to COMP2 non-inverting input */ + +/* Non-inverting inputs specific to COMP1 */ +#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */ +#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA3 RI_IOSWITCH_CH3 /*!< I/O pin PA3 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA4 RI_IOSWITCH_CH4 /*!< I/O pin PA4 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA5 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA6 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA7 RI_IOSWITCH_CH7 /*!< I/O pin PA7 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB0 RI_IOSWITCH_CH8 /*!< I/O pin PB0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB1 RI_IOSWITCH_CH9 /*!< I/O pin PB1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC0 RI_IOSWITCH_CH10 /*!< I/O pin PC0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC1 RI_IOSWITCH_CH11 /*!< I/O pin PC1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC2 RI_IOSWITCH_CH12 /*!< I/O pin PC2 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC3 RI_IOSWITCH_CH13 /*!< I/O pin PC3 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC4 RI_IOSWITCH_CH14 /*!< I/O pin PC4 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC5 RI_IOSWITCH_CH15 /*!< I/O pin PC5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB12 RI_IOSWITCH_CH18 /*!< I/O pin PB12 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB13 RI_IOSWITCH_CH19 /*!< I/O pin PB13 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB14 RI_IOSWITCH_CH20 /*!< I/O pin PB14 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB15 RI_IOSWITCH_CH21 /*!< I/O pin PB15 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE7 RI_IOSWITCH_CH22 /*!< I/O pin PE7 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE8 RI_IOSWITCH_CH23 /*!< I/O pin PE8 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE9 RI_IOSWITCH_CH24 /*!< I/O pin PE9 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE10 RI_IOSWITCH_CH25 /*!< I/O pin PE10 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PF6 RI_IOSWITCH_CH27 /*!< I/O pin PF6 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PF7 RI_IOSWITCH_CH28 /*!< I/O pin PF7 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PF8 RI_IOSWITCH_CH29 /*!< I/O pin PF8 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PF9 RI_IOSWITCH_CH30 /*!< I/O pin PF9 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PF10 RI_IOSWITCH_CH31 /*!< I/O pin PF10 connection to COMP1 non-inverting input */ + +#define COMP_NONINVERTINGINPUT_OPAMP1 COMP_NONINVERTINGINPUT_PA3 /*!< OPAMP1 output connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_OPAMP2 COMP_NONINVERTINGINPUT_PB0 /*!< OPAMP2 output connection to COMP1 non-inverting input */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) +#define COMP_NONINVERTINGINPUT_OPAMP3 COMP_NONINVERTINGINPUT_PC3 /*!< OPAMP3 output connection to COMP1 non-inverting input */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +/* Non-inverting inputs specific to COMP2 */ +#define COMP_NONINVERTINGINPUT_PB4 RI_IOSWITCH_GR6_1 /*!< I/O pin PB4 connection to COMP2 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB6 RI_IOSWITCH_GR6_3 /*!< I/O pin PB6 connection to COMP2 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB7 RI_IOSWITCH_GR6_4 /*!< I/O pin PB7 connection to COMP2 non-inverting input */ + +/* Non-inverting inputs specific to COMP1 */ +#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */ +#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA3 RI_IOSWITCH_CH3 /*!< I/O pin PA3 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA4 RI_IOSWITCH_CH4 /*!< I/O pin PA4 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA5 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA6 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA7 RI_IOSWITCH_CH7 /*!< I/O pin PA7 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB0 RI_IOSWITCH_CH8 /*!< I/O pin PB0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB1 RI_IOSWITCH_CH9 /*!< I/O pin PB1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC0 RI_IOSWITCH_CH10 /*!< I/O pin PC0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC1 RI_IOSWITCH_CH11 /*!< I/O pin PC1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC2 RI_IOSWITCH_CH12 /*!< I/O pin PC2 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC3 RI_IOSWITCH_CH13 /*!< I/O pin PC3 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC4 RI_IOSWITCH_CH14 /*!< I/O pin PC4 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC5 RI_IOSWITCH_CH15 /*!< I/O pin PC5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB12 RI_IOSWITCH_CH18 /*!< I/O pin PB12 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB13 RI_IOSWITCH_CH19 /*!< I/O pin PB13 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB14 RI_IOSWITCH_CH20 /*!< I/O pin PB14 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB15 RI_IOSWITCH_CH21 /*!< I/O pin PB15 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE7 RI_IOSWITCH_CH22 /*!< I/O pin PE7 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE8 RI_IOSWITCH_CH23 /*!< I/O pin PE8 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE9 RI_IOSWITCH_CH24 /*!< I/O pin PE9 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE10 RI_IOSWITCH_CH25 /*!< I/O pin PE10 connection to COMP1 non-inverting input */ + +#define COMP_NONINVERTINGINPUT_OPAMP1 COMP_NONINVERTINGINPUT_PA3 /*!< OPAMP1 output connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_OPAMP2 COMP_NONINVERTINGINPUT_PB0 /*!< OPAMP2 output connection to COMP1 non-inverting input */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ + +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) +/* Non-inverting inputs specific to COMP2 */ +#define COMP_NONINVERTINGINPUT_PB4 RI_IOSWITCH_GR6_1 /*!< I/O pin PB4 connection to COMP2 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */ + +/* Non-inverting inputs specific to COMP1 */ +#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */ +#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA3 RI_IOSWITCH_CH3 /*!< I/O pin PA3 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA4 RI_IOSWITCH_CH4 /*!< I/O pin PA4 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA5 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA6 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PA7 RI_IOSWITCH_CH7 /*!< I/O pin PA7 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB0 RI_IOSWITCH_CH8 /*!< I/O pin PB0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB1 RI_IOSWITCH_CH9 /*!< I/O pin PB1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC0 RI_IOSWITCH_CH10 /*!< I/O pin PC0 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC1 RI_IOSWITCH_CH11 /*!< I/O pin PC1 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC2 RI_IOSWITCH_CH12 /*!< I/O pin PC2 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC3 RI_IOSWITCH_CH13 /*!< I/O pin PC3 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC4 RI_IOSWITCH_CH14 /*!< I/O pin PC4 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PC5 RI_IOSWITCH_CH15 /*!< I/O pin PC5 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB12 RI_IOSWITCH_CH18 /*!< I/O pin PB12 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB13 RI_IOSWITCH_CH19 /*!< I/O pin PB13 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB14 RI_IOSWITCH_CH20 /*!< I/O pin PB14 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PB15 RI_IOSWITCH_CH21 /*!< I/O pin PB15 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE7 RI_IOSWITCH_CH22 /*!< I/O pin PE7 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE8 RI_IOSWITCH_CH23 /*!< I/O pin PE8 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE9 RI_IOSWITCH_CH24 /*!< I/O pin PE9 connection to COMP1 non-inverting input */ +#define COMP_NONINVERTINGINPUT_PE10 RI_IOSWITCH_CH25 /*!< I/O pin PE10 connection to COMP1 non-inverting input */ + +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ + +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB6) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_NONE) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA2) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA3) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA6) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC2) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC3) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB12) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB13) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB14) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB15) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE8) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE9) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE10) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PF6) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PF7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PF8) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PF9) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PF10) ) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB6) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_NONE) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA2) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA3) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA6) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC2) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC3) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB12) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB13) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB14) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB15) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE8) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE9) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE10) ) +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ + +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) +#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_NONE) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA2) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA3) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA6) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PA7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC0) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC2) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC3) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC4) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PC5) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB12) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB13) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB14) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PB15) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE7) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE8) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE9) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_PE10) ) +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup COMPEx_Private_Macro COMP Private Macro + * @{ + */ + +/** + * @brief Specifies whether Routing Interface (RI) needs to be configured for + * switches of comparator non-inverting input. + * @param __HANDLE__: COMP handle. + * @retval None. + */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__) \ + (((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) && \ + (READ_BIT(COMP->CSR, COMP_CSR_SW1) == RESET) ) +#else +#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__) \ + ((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_COMP_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h new file mode 100644 index 000000000..c6d0dd67e --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_conf_template.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l1xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CONF_H +#define __STM32L1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LCD_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_OPAMP_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/*#define USE_FULL_ASSERT 1*/ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l1xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l1xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l1xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32l1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l1xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l1xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l1xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h new file mode 100644 index 000000000..8323d6bde --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cortex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CORTEX_H +#define __STM32L1xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ + +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported Macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source_Macro_Exported CORTEX SysTick clock source + * @{ + */ + +/** @brief Configures the SysTick clock source. + * @param __CLKSRC__: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \ + do { \ + if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \ + { \ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \ + } \ + else \ + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \ + } while(0) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source + * @{ + */ +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h new file mode 100644 index 000000000..a3c807d40 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h @@ -0,0 +1,192 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_crc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CRC_H +#define __STM32L1xx_HAL_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ + +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ + +}HAL_CRC_StateTypeDef; + +/** + * @brief CRC handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + HAL_LockTypeDef Lock; /*!< CRC locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + +}CRC_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state + * @param __HANDLE__: CRC handle + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Resets CRC Data Register. + * @param __HANDLE__: CRC handle + * @retval None + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET)) + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @param __VALUE__: 8-bit value to be stored in the ID register + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)) + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @retval 8-bit value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CRC_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); + +/** + * @} + */ + +/** @addtogroup CRC_Exported_Functions_Group2 + * @{ + */ + +/** @addtogroup CRC_Exported_Functions_Group3 + ** @{ + */ +/* Peripheral Control functions ************************************************/ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); + +/* Peripheral State functions **************************************************/ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CRC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h new file mode 100644 index 000000000..2b0405a6e --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cryp.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of CRYP HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CRYP_H +#define __STM32L1xx_HAL_CRYP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRYP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Types CRYP Exported Types + * @{ + */ + +/** + * @brief CRYP Configuration Structure definition + */ +typedef struct +{ + uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. + This parameter can be a value of @ref CRYP_Data_Type */ + + uint8_t* pKey; /*!< The key used for encryption/decryption */ + + uint8_t* pInitVect; /*!< The initialization vector used also as initialization + counter in CTR mode */ + +}CRYP_InitTypeDef; + +/** + * @brief HAL CRYP State structures definition + */ +typedef enum +{ + HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */ + HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */ + HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */ + HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */ + HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */ + +}HAL_CRYP_STATETypeDef; + +/** + * @brief HAL CRYP phase structures definition + */ +typedef enum +{ + HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ + HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */ +}HAL_PhaseTypeDef; + +/** + * @brief CRYP handle Structure definition + */ +typedef struct +{ + CRYP_InitTypeDef Init; /*!< CRYP required parameters */ + + uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + + uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + + __IO uint16_t CrypInCount; /*!< Counter of inputed data */ + + __IO uint16_t CrypOutCount; /*!< Counter of outputed data */ + + HAL_StatusTypeDef Status; /*!< CRYP peripheral status */ + + HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */ + + DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ + + DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< CRYP locking object */ + + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ + +}CRYP_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Constants CRYP Exported Constants + * @{ + */ + +/** @defgroup CRYP_Data_Type CRYP Data Type + * @{ + */ +#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) +#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 +#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 +#define CRYP_DATATYPE_1B AES_CR_DATATYPE + +#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \ + ((DATATYPE) == CRYP_DATATYPE_16B) || \ + ((DATATYPE) == CRYP_DATATYPE_8B) || \ + ((DATATYPE) == CRYP_DATATYPE_1B)) +/** + * @} + */ + +/** @defgroup CRYP_AlgoModeDirection CRYP Algo Mode Direction + * @{ + */ +#define CRYP_CR_ALGOMODE_DIRECTION (uint32_t)(AES_CR_MODE|AES_CR_CHMOD) + +#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT (AES_CR_MODE) +#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT (AES_CR_CHMOD_0) +#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE)) +#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT (AES_CR_CHMOD_1) +#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)(AES_CR_CHMOD_1 | AES_CR_MODE_1)) +/** + * @} + */ + +/** @defgroup CRYP_AES_Interrupts AES Interrupts + * @{ + */ +#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */ +#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */ + +/** + * @} + */ + + +/** @defgroup CRYP_AES_Flags AES Flags + * @{ + */ +#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */ +#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */ +#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */ + +/** + * @} + */ + +/** @defgroup CRYP_AES_Clear_Flags AES Clear Flags + * @{ + */ +#define AES_CLEARFLAG_CCF AES_CR_CCFC /*!< Computation Complete Flag Clear */ +#define AES_CLEARFLAG_RDERR AES_CR_ERRC /*!< Read Error Clear */ +#define AES_CLEARFLAG_WRERR AES_CR_ERRC /*!< Write Error Clear */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Macros CRYP Exported Macros + * @{ + */ + +/** @brief Reset CRYP handle state + * @param __HANDLE__: specifies the CRYP Handle. + * @retval None + */ +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) + +/** + * @brief Enable/Disable the CRYP peripheral. + * @retval None + */ +#define __HAL_CRYP_ENABLE() SET_BIT(AES->CR, AES_CR_EN) +#define __HAL_CRYP_DISABLE() CLEAR_BIT(AES->CR, AES_CR_EN) + +/** + * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,... + * @param __MODE__: The algorithm mode. + * @retval None + */ +#define __HAL_CRYP_SET_MODE(__MODE__) SET_BIT(AES->CR, (__MODE__)) + + +/** @brief Check whether the specified CRYP flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg AES_FLAG_CCF : Computation Complete Flag + * @arg AES_FLAG_RDERR : Read Error Flag + * @arg AES_FLAG_WRERR : Write Error Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the CRYP pending flag. + * @param __HANDLE__: specifies the CRYP handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg AES_CLEARFLAG_CCF : Computation Complete Clear Flag + * @arg AES_CLEARFLAG_RDERR : Read Error Clear + * @arg AES_CLEARFLAG_WRERR : Write Error Clear + * @retval None + */ +#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(AES->CR, (__FLAG__)) + +/** + * @brief Enable the CRYP interrupt. + * @param __INTERRUPT__: CRYP Interrupt. + * @retval None + */ +#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__)) + +/** + * @brief Disable the CRYP interrupt. + * @param __INTERRUPT__: CRYP interrupt. + * @retval None + */ +#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(AES->CR, (__INTERRUPT__)) + +/** @brief Checks if the specified CRYP interrupt source is enabled or disabled. + * @param __HANDLE__: CRYP handle + * @param __INTERRUPT__: CRYP interrupt source to check + * This parameter can be one of the following values: + * @arg AES_IT_CC : Computation Complete interrupt + * @arg AES_IT_ERR : Error interrupt (used for RDERR and WRERR) + * @retval State of interruption (SET or RESET) + */ +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (( (AES->CR & (__INTERRUPT__)) == (__INTERRUPT__) \ + )? SET : RESET \ + ) + +/** @brief Clear the CRYP pending IT. + * @param __HANDLE__: specifies the CRYP handle. + * @param __IT__: specifies the IT to clear. + * This parameter can be one of the following values: + * @arg AES_CLEARFLAG_CCF : Computation Complete Clear Flag + * @arg AES_CLEARFLAG_RDERR : Read Error Clear + * @arg AES_CLEARFLAG_WRERR : Write Error Clear + * @retval None + */ +#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT(AES->CR, (__IT__)) + +/** + * @} + */ + +/* Include CRYP HAL Extension module */ +#include "stm32l1xx_hal_cryp_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CRYP_Exported_Functions + * @{ + */ + +/** @addtogroup CRYP_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions *********************************/ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); + +/* MSP functions *************************************************************/ +void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group2 + * @{ + */ + +/* AES encryption/decryption using polling ***********************************/ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); + +/* AES encryption/decryption using interrupt *********************************/ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); + +/* AES encryption/decryption using DMA ***************************************/ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group3 + * @{ + */ + +/* CallBack functions ********************************************************/ +void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group4 + * @{ + */ + +/* Processing functions ********************************************************/ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group5 + * @{ + */ + +/* Peripheral State functions **************************************************/ +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CRYP_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h new file mode 100644 index 000000000..26a989e56 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cryp_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of CRYPEx HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CRYP_EX_H +#define __STM32L1xx_HAL_CRYP_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRYPEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CRYPEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group1 + * @{ + */ + +/* CallBack functions ********************************************************/ +void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CRYP_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h new file mode 100644 index 000000000..e86b57236 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h @@ -0,0 +1,385 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dac.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of DAC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_DAC_H +#define __STM32L1xx_HAL_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Types DAC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + +}HAL_DAC_StateTypeDef; + +/** + * @brief DAC handle Structure definition + */ +typedef struct +{ + DAC_TypeDef *Instance; /*!< Register base address */ + + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ + + HAL_LockTypeDef Lock; /*!< DAC locking object */ + + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + + __IO uint32_t ErrorCode; /*!< DAC Error code */ + +}DAC_HandleTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ + +}DAC_ChannelConfTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_Error_Code DAC Error Code + * @{ + */ +#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +/** + * @} + */ + +/** @defgroup DAC_trigger_selection DAC trigger selection + * @{ + */ +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T9_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T9_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer DAC output buffer + * @{ + */ +#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) + +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection DAC Channel selection + * @{ + */ +#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement DAC data alignement + * @{ + */ +#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) +#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) +#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) +/** + * @} + */ + +/** @defgroup DAC_data DAC data + * @{ + */ +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** @defgroup DAC_flags_definition DAC flags definition + * @{ + */ +#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) + +/** + * @} + */ + +/** @defgroup DAC_IT_definition DAC IT definition + * @{ + */ +#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @brief Reset DAC handle state + * @param __HANDLE__: specifies the DAC handle. + * @retval None + */ +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) + +/** @brief Enable the DAC channel + * @param __HANDLE__: specifies the DAC handle. + * @param __DAC_Channel__: specifies the DAC channel + * @retval None + */ +#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ +((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) + +/** @brief Disable the DAC channel + * @param __HANDLE__: specifies the DAC handle + * @param __DAC_Channel__: specifies the DAC channel. + * @retval None + */ +#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ +((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) + +/** @brief Set DHR12R1 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) + +/** @brief Set DHR12R2 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) + +/** @brief Set DHR12RD alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) + +/** @brief Enable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) + +/** @brief Disable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) + +/** @brief Get the selected DAC's flag status. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the FLAG. + * @retval None + */ +#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the DAC's flag. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the FLAG. + * @retval None + */ +#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) + +/** + * @} + */ + + +/* Include DAC HAL Extension module */ +#include "stm32l1xx_hal_dac_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral State functions ***************************************************/ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); + +void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); +void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32L1xx_HAL_DAC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h new file mode 100644 index 000000000..9c3032ee8 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dac_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of DAC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_DAC_EX_H +#define __STM32L1xx_HAL_DAC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DACEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Constants DACEx Exported Constants + * @{ + */ + +/** @defgroup DACEx_wave_generation DACEx wave generation + * @{ + */ +#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000) +#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0) +#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) + +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \ + ((WAVE) == DAC_WAVEGENERATION_NOISE) || \ + ((WAVE) == DAC_WAVEGENERATION_TRIANGLE)) +/** + * @} + */ + +/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude + * @{ + */ +#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) +/** + * @} + */ + +/** @defgroup DACEx_wave_generation DACEx wave generation + * @{ + */ +#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) +#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \ + ((WAVE) == DAC_WAVE_TRIANGLE)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group1 + * @{ + */ +/* Extension features functions ***********************************************/ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); + +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); + +/** + * @} + */ + +/** + * @} + */ +/** @addtogroup DACEx_Private_Functions + * @{ + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32L1xx_HAL_DAC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h new file mode 100644 index 000000000..a8ad77943 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h @@ -0,0 +1,195 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_def.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_DEF +#define __STM32L1xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ +#ifndef NULL + #define NULL (void *) 0 +#endif + +#define HAL_MAX_DELAY 0xFFFFFFFF + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ + (__DMA_HANDLE_).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC HAL_StatusTypeDef + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc HAL_StatusTypeDef + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32L1xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h new file mode 100644 index 000000000..366d973a0 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h @@ -0,0 +1,444 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dma.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_DMA_H +#define __STM32L1xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ + +} DMA_InitTypeDef; + +/** + * @brief DMA Configuration enumeration values definition + */ +typedef enum +{ + DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ + DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ + +} DMA_ControlTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ + HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ + HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ + +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ + +}HAL_DMA_LevelCompleteTypeDef; + + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + +} DMA_HandleTypeDef; +/** + * @} + */ + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA_Error_Code + * @{ + */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +/** + * @} + */ + + +/** @defgroup DMA_Data_transfer_direction DMA_Data_transfer_direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +/** + * @} + */ + +/** @defgroup DMA_Data_buffer_size DMA_Data_buffer_size + * @{ + */ +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA_Peripheral_incremented_mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA_Memory_incremented_mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA_Peripheral_data_size + * @{ + */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) +/** + * @} + */ + + +/** @defgroup DMA_Memory_data_size DMA_Memory_data_size + * @{ + */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) +/** + * @} + */ + +/** @defgroup DMA_mode DMA_mode + * @{ + */ +#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA_Priority_level + * @{ + */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA_interrupt_enable_definitions + * @{ + */ + +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) + +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA_flag_definitions + * @{ + */ + +#define DMA_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA_FLAG_TE7 ((uint32_t)0x08000000) + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__: DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None. + */ +#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None. + */ +#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) + +/** + * @brief Disables the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) + +/** + * @brief Checks whether the specified DMA Channel interrupt has occurred or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @} + */ + + +/* Include DMA HAL Extension module */ +#include "stm32l1xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); + +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h new file mode 100644 index 000000000..c1feb45bc --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h @@ -0,0 +1,248 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dma_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_DMA_EX_H +#define __STM32L1xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros + * @{ + */ + +/* Interrupt & Flag management */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ + +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +#else +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_DMA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h new file mode 100644 index 000000000..5bbe8c878 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h @@ -0,0 +1,385 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_FLASH_H +#define __STM32L1xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Error structure definition + */ +typedef enum +{ + FLASH_ERROR_SIZE = 0x01, + FLASH_ERROR_OPTV = 0x02, + FLASH_ERROR_OPTVUSR = 0x04, + FLASH_ERROR_PGA = 0x08, + FLASH_ERROR_WRP = 0x10, + FLASH_ERROR_RD = 0x20, + FLASH_ERROR_OPERATION = 0x40 +}FLASH_ErrorTypeDef; + + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0, + FLASH_PROC_PAGEERASE, + FLASH_PROC_PROGRAM +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ + + __IO uint32_t NbPagesToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ + + __IO uint32_t Page; /*Internal variable to define the current sector which is erasing*/ + + __IO uint32_t Address; /*Internal variable to save address selected for program*/ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/** @addtogroup FLASH_Internal_Variables + * @{ + */ + +/** + * @brief Variable used for Program/Erase sectors under interruption. + * Put as extern as used also in flash_ex.c. + */ +extern FLASH_ProcessTypeDef ProcFlash; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000) /* 50 s */ + +#define FLASH_PAGE_SIZE ((uint32_t)256) + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */ + +#define IS_TYPEPROGRAMFLASH(_VALUE_) (((_VALUE_) == TYPEPROGRAM_WORD)) + +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */ + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts FLASH Interrupts + * @{ + */ + +#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */ +#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_Flags FLASH Flags + * @{ + */ + +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ +#define FLASH_FLAG_ENDHV FLASH_SR_ENDHV /*!< FLASH End of High Voltage flag */ +#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */ + +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ + +#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */ +#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 + to unlock the RUN_PD bit in FLASH_ACR */ + +#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */ +#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2 + to unlock the write access to the FLASH_PECR register and + data EEPROM */ + +#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */ +#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2 + to unlock the program memory */ + +#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */ +#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to + unlock the write access to the option byte block */ +/** + * @} + */ + + + +#if defined ( __ICCARM__ ) +#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk +#endif + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) ((FLASH->PECR) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) ((FLASH->PECR) &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_ENDHV : FLASH End of High Voltage flag + * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH Size error flag + * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error error flag + * @arg FLASH_FLAG_OPTVERRUSR : FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_ENDHV : FLASH End of High Voltage flag + * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH Size error flag + * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error error flag + * @arg FLASH_FLAG_OPTVERRUSR : FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32l1xx_hal_flash_ex.h" +#include "stm32l1xx_hal_flash_ramfunc.h" + +/* Exported functions ------------------------------------------------------- */ + +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ + +/** + * @brief FLASH memory functions that can be executed from FLASH. + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); + +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ + +/* FLASH Memory Programming functions *****************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); + +/* Option Bytes Programming functions *****************************************/ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral State methods **************************************************/ +FLASH_ErrorTypeDef HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Internal_Functions + * @{ + */ + +/** + * @brief Function used internally by HAL FLASH driver. + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h new file mode 100644 index 000000000..50b5fc7f3 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h @@ -0,0 +1,975 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_FLASH_EX_H +#define __STM32L1xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Page Erase only. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased + This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ + + uint32_t NbPages; /*!< NbPages: Number of pages to be erased. + This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes PROGRAM structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ +#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Advanced Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . + This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ + + uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */ + +#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ +#endif /* STM32L151xC || STM32L152xC || STM32L162xC */ +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ +} FLASH_AdvOBProgramInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase + * @{ + */ +#define TYPEERASE_PAGES ((uint32_t)0x00) /*!= 256KB*/ +#define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */ +#define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */ +#define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */ +#define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */ +#define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */ +#define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */ +#define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */ +#define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */ +#define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */ +#define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */ +#define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */ +#define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */ +#define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */ +#define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */ +#define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */ +#define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */ +#define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */ +#define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */ +#define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */ +#define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */ +#define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */ +#define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */ +#define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */ +#define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */ +#define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */ +#define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */ +#define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */ +#define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */ +#define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */ +#define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */ +#define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */ +#define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */ + +#define OB_WRP3_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ + +#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4 + * @{ + */ + +/* Pages for Cat5 devices*/ +#define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/ +#define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/ +#define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/ +#define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/ +#define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/ +#define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/ +#define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/ +#define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/ +#define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/ +#define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/ +#define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/ +#define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/ +#define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/ +#define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/ +#define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/ +#define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/ +#define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/ +#define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/ +#define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/ +#define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/ +#define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/ +#define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/ +#define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/ +#define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/ +#define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/ +#define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/ +#define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/ +#define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/ +#define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/ +#define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/ +#define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/ +#define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000) /* Write protection of Sector127*/ + +#define OB_WRP4_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ + +/** + * @} + */ + +#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL0 ((uint8_t)0xAA) +#define OB_RDP_LEVEL1 ((uint8_t)0xBB) +/*#define OB_RDP_LEVEL2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ + +#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL0)||\ + ((__LEVEL__) == OB_RDP_LEVEL1))/*||\ + ((__LEVEL__) == OB_RDP_LEVEL2))*/ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level + * @{ + */ + +#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD + power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ +#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ +#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ +#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ +#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ + +#define IS_OB_BOR_LEVEL(__LEVEL__) ( ((__LEVEL__) == OB_BOR_OFF) || \ + ((__LEVEL__) == OB_BOR_LEVEL1) || \ + ((__LEVEL__) == OB_BOR_LEVEL2) || \ + ((__LEVEL__) == OB_BOR_LEVEL3) || \ + ((__LEVEL__) == OB_BOR_LEVEL4) || \ + ((__LEVEL__) == OB_BOR_LEVEL5)) + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */ + +#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP + * @{ + */ + +#define OB_STOP_NORST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY + * @{ + */ + +#define OB_STDBY_NORST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) + +/** + * @} + */ + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + +/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type + * @{ + */ + +#define OBEX_PCROP ((uint32_t)0x01) /*!= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END)) + +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || \ + defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined (STM32L151xCA) || defined (STM32L152xCA) || defined (STM32L162xCA) + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) + +#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) +#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) +#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) + +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L152xCA || STM32L162xCA */ + +#define IS_NBPAGES(_PAGES_) (((_PAGES_) >= 1) && ((_PAGES_) <= FLASH_NBPAGES_MAX)) + +/** + * @} + */ + +/** @defgroup FLASHEx_Flags FLASHEx Flags + * @{ + */ + +/* Cat2 & Cat3*/ +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */ + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +/* Cat3, Cat4 & Cat5*/ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */ + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/* Cat1*/ +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined (STM32L100xBA) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR) + +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA */ + +/* RDERR only for STM32L151xBA & STM32L152xBA (Cat2)*/ +#if defined (STM32L151xBA) || defined (STM32L152xBA) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_RDERR) + +#endif /* STM32L151xBA || STM32L152xBA */ + +/* FLASH_FLAG_OPTVERRUSR & RDERR only for STM32L151xC, STM32L152xC & STM32L152xBA (Cat3) */ +#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC */ + +/* FLASH_FLAG_OPTVERRUSR only for STM32L100xC (Cat3) */ +#if defined (STM32L100xC) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERRUSR) + +#endif /* STM32L100xC */ + +/* Cat4 & Cat5 */ +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERRUSR) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT + * @{ + */ + +#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 + or Bank 1, depending on the activation of the bank */ +#define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ +#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) + +/** + * @} + */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__: FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1: FLASH One Latency cycle + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \ + if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \ + MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \ + } while(0) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1: FLASH One Latency cycle + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + + /** + * @brief Enable the FLASH 64-bit access. + * @note Read access 64 bit is used. + * @note This bit cannot be written at the same time as the LATENCY and + * PRFTEN bits. + * @retval none + */ +#define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64)) + + /** + * @brief Disable the FLASH 64-bit access. + * @note Read access 32 bit is used + * @note To reset this bit, the LATENCY should be zero wait state and the + * prefetch off. + * @retval none + */ +#define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64)) + + /** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \ + SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \ + } while(0) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH power down during Sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @brief Disable the FLASH power down during Sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @brief Macro to enable or disable the Flash Run power down mode. + * @note Writing this bit to 0 this bit, automatically the keys are + * loss and a new unlock sequence is necessary to re-write it to 1. + */ + +#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ + FLASH->PDKEYR = FLASH_PDKEY2; \ + SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ + } while (0) + +#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ + FLASH->PDKEYR = FLASH_PDKEY2; \ + CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ + } while (0) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ + +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); + +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address); +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); +void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); +void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h new file mode 100644 index 000000000..a4b2f3242 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h @@ -0,0 +1,130 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash_ramfunc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of FLASH RAMFUNC driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_FLASH_RAMFUNC_H +#define __STM32L1xx_FLASH_RAMFUNC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHRamfunc + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup FLASHRamfunc_Exported_Functions + * @{ + */ + +/* + * @brief FLASH memory functions that should be executed from internal SRAM. + * These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c" + * file. + */ + +/** @addtogroup FLASHRamfunc_Exported_Functions_Group1 + * @{ + */ + +__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); +__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); + +/** + * @} + */ + +/** @addtogroup FLASHRamfunc_Exported_Functions_Group2 + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); +__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); + +/** + * @} + */ + +/** @addtogroup FLASHRamfunc_Exported_Functions_Group3 + * @{ + */ + +__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address); +__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_FLASH_RAMFUNC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h new file mode 100644 index 000000000..fab2e3fd0 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h @@ -0,0 +1,331 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_gpio.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_GPIO_H +#define __STM32L1xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +/** + * @} + */ + + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_VERY_LOW ((uint32_t)0x00000000) /*!< Very Low speed */ +#define GPIO_SPEED_LOW ((uint32_t)0x00000001) /*!< Low speed */ +#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000002) /*!< Medium speed */ +#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ + +/** + * @} + */ + + + /** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Macros + * @{ + */ + +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) + +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_VERY_LOW) || ((SPEED) == GPIO_SPEED_LOW) || \ + ((SPEED) == GPIO_SPEED_MEDIUM) || ((SPEED) == GPIO_SPEED_HIGH)) + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +/* Include GPIO HAL Extension module */ +#include "stm32l1xx_hal_gpio_ex.h" +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/* Initialization and de-initialization functions *******************************/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * + * @{ + */ + +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/* IO operation functions *******************************************************/ +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief Initialization and Configuration functions + * + * @{ + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h new file mode 100644 index 000000000..ba82ea56c --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h @@ -0,0 +1,260 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_gpio_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_GPIO_EX_H +#define __STM32L1xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_OUT Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) ||\ + defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) + +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ + +#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE */ + + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#if defined (STM32L151xD) || defined (STM32L151xE) ||\ + defined (STM32L152xD) || defined (STM32L152xE) ||\ + defined (STM32L162xD) || defined (STM32L162xE) + +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ + +#endif /* STM32L151xD || STM32L151xE || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE */ + + +/** + * @brief AF 9 selection + */ + +/** + * @brief AF 10 selection + */ + +/** + * @brief AF 11 selection + */ +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) + +#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ + +#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE */ + +/** + * @brief AF 12 selection + */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +/** + * @brief AF 13 selection + */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros + * @{ + */ + + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif + +#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) +#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) +#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif + + + +/** + * @} + */ + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h new file mode 100644 index 000000000..cabf29d17 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h @@ -0,0 +1,538 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_i2c.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_I2C_H +#define __STM32L1xx_HAL_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +}I2C_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ + HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */ + HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */ + HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */ + HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */ + +}HAL_I2C_StateTypeDef; + +/** + * @brief HAL I2C Error Code structure definition + */ +typedef enum +{ + HAL_I2C_ERROR_NONE = 0x00, /*!< No error */ + HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */ + HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */ + HAL_I2C_ERROR_AF = 0x04, /*!< AF error */ + HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */ + HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */ + HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */ + +}HAL_I2C_ErrorTypeDef; + +/** + * @brief I2C handle Structure definition + */ +typedef struct +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */ + +}I2C_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C_duty_cycle_in_fast_mode + * @{ + */ +#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000) +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY + +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C_addressing_mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000) +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000)) + +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C_dual_addressing_mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000) +#define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLED)) +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C_general_call_addressing_mode + * @{ + */ +#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000) +#define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \ + ((CALL) == I2C_GENERALCALL_ENABLED)) +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C_nostretch_mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLED)) +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C_Memory_Address_Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) +#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C_Interrupt_configuration_definition + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C_Flag_definition + * @{ + */ +#define I2C_FLAG_OVR ((uint32_t)(1 << 16 | I2C_SR1_OVR)) +#define I2C_FLAG_AF ((uint32_t)(1 << 16 | I2C_SR1_AF)) +#define I2C_FLAG_ARLO ((uint32_t)(1 << 16 | I2C_SR1_ARLO)) +#define I2C_FLAG_BERR ((uint32_t)(1 << 16 | I2C_SR1_BERR)) +#define I2C_FLAG_TXE ((uint32_t)(1 << 16 | I2C_SR1_TXE)) +#define I2C_FLAG_RXNE ((uint32_t)(1 << 16 | I2C_SR1_RXNE)) +#define I2C_FLAG_STOPF ((uint32_t)(1 << 16 | I2C_SR1_STOPF)) +#define I2C_FLAG_ADD10 ((uint32_t)(1 << 16 | I2C_SR1_ADD10)) +#define I2C_FLAG_BTF ((uint32_t)(1 << 16 | I2C_SR1_BTF)) +#define I2C_FLAG_ADDR ((uint32_t)(1 << 16 | I2C_SR1_ADDR)) +#define I2C_FLAG_SB ((uint32_t)(1 << 16 | I2C_SR1_SB)) +#define I2C_FLAG_DUALF ((uint32_t)(2 << 16 | I2C_SR2_DUALF)) +#define I2C_FLAG_GENCALL ((uint32_t)(2 << 16 | I2C_SR2_GENCALL)) +#define I2C_FLAG_TRA ((uint32_t)(2 << 16 | I2C_SR2_TRA)) +#define I2C_FLAG_BUSY ((uint32_t)(2 << 16 | I2C_SR2_BUSY)) +#define I2C_FLAG_MSL ((uint32_t)(2 << 16 | I2C_SR2_MSL)) + + +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF) + +/** + * @} + */ + +/** @defgroup I2C_Clock_Speed_definition I2C_Clock_Speed_definition + * @{ + */ +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** @defgroup I2C_Own_Address1_definition I2C_Own_Address1_definition + * @{ + */ +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0) +/** + * @} + */ + +/** @defgroup I2C_Own_Address2_definition I2C_Own_Address2_definition + * @{ + */ +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ + +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __INTERRUPT__: specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ + ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ + +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\ + (__HANDLE__)->Instance->SR2;}while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\ + SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);}while(0) + +/** @brief Enable the I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** @brief Disable the I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1))) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup I2C_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + + +/* I/O operation functions *****************************************************/ +/** @addtogroup I2C_Exported_Functions_Group2 + * @{ + */ + +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + + +/* Peripheral Control and State functions **************************************/ +/** @addtogroup I2C_Exported_Functions_Group3 + * @{ + */ + +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** + * @} + */ + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h new file mode 100644 index 000000000..63704acbb --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h @@ -0,0 +1,454 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_i2s.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_I2S_H +#define __STM32L1xx_HAL_I2S_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L100xC) || \ + defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \ + defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L151xE) || \ + defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ + +}I2S_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S pause state: used in case of DMA */ + HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ +}HAL_I2S_StateTypeDef; + +/** + * @brief HAL I2S Error Code structure definition + */ +typedef enum +{ + HAL_I2S_ERROR_NONE = 0x00, /*!< No error */ + HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */ + HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */ + HAL_I2S_ERROR_FRE = 0x04, /*!< I2S Frame format error */ + HAL_I2S_ERROR_DMA = 0x08 /*!< DMA transfer error */ +}HAL_I2S_ErrorTypeDef; + +/** + * @brief I2S handle Structure definition + */ +typedef struct +{ + SPI_TypeDef *Instance; /* I2S registers base address */ + + I2S_InitTypeDef Init; /* I2S communication parameters */ + + uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /* I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /* I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /* I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received. + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + + DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /* I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ + + __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */ + +}I2S_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) +#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) +#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) +#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) + +#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ + ((MODE) == I2S_MODE_SLAVE_RX) || \ + ((MODE) == I2S_MODE_MASTER_TX) || \ + ((MODE) == I2S_MODE_MASTER_RX)) +/** + * @} + */ + +/** @defgroup I2S_Standard I2S Standard + * @{ + */ +#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) +#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0) +#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ + SPI_I2SCFGR_I2SSTD_1)) +#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ + SPI_I2SCFGR_I2SSTD_1 |\ + SPI_I2SCFGR_PCMSYNC)) + +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ + ((STANDARD) == I2S_STANDARD_MSB) || \ + ((STANDARD) == I2S_STANDARD_LSB) || \ + ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ + ((STANDARD) == I2S_STANDARD_PCM_LONG)) +/** @defgroup I2S_Legacy I2S Legacy + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2S_Data_Format I2S Data Format + * @{ + */ +#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) +#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN) +#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) +#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) + +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ + ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((FORMAT) == I2S_DATAFORMAT_24B) || \ + ((FORMAT) == I2S_DATAFORMAT_32B)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output I2S MCLK Output + * @{ + */ +#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) +#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) + +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ + ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIOFREQ_192K ((uint32_t)192000) +#define I2S_AUDIOFREQ_96K ((uint32_t)96000) +#define I2S_AUDIOFREQ_48K ((uint32_t)48000) +#define I2S_AUDIOFREQ_44K ((uint32_t)44100) +#define I2S_AUDIOFREQ_32K ((uint32_t)32000) +#define I2S_AUDIOFREQ_22K ((uint32_t)22050) +#define I2S_AUDIOFREQ_16K ((uint32_t)16000) +#define I2S_AUDIOFREQ_11K ((uint32_t)11025) +#define I2S_AUDIOFREQ_8K ((uint32_t)8000) +#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ + ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ + ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity + * @{ + */ +#define I2S_CPOL_LOW ((uint32_t)0x00000000) +#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) + +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ + ((CPOL) == I2S_CPOL_HIGH)) +/** + * @} + */ + +/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition + * @{ + */ +#define I2S_IT_TXE SPI_CR2_TXEIE +#define I2S_IT_RXNE SPI_CR2_RXNEIE +#define I2S_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup I2S_Flag_definition I2S Flag definition + * @{ + */ +#define I2S_FLAG_TXE SPI_SR_TXE +#define I2S_FLAG_RXNE SPI_SR_RXNE + +#define I2S_FLAG_UDR SPI_SR_UDR +#define I2S_FLAG_OVR SPI_SR_OVR +#define I2S_FLAG_FRE SPI_SR_FRE + +#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE +#define I2S_FLAG_BSY SPI_SR_BSY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_macros I2S Exported Macros + * @{ + */ + +/** @brief Reset I2S handle state + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) + +/** @brief Enable or disable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) +#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Enable or disable the specified I2S interrupts. + * @param __HANDLE__: specifies the I2S Handle. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) +#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Checks if the specified I2S interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. + * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2S flag is set or not. + * @param __HANDLE__: specifies the I2S Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXNE: Receive buffer not empty flag + * @arg I2S_FLAG_TXE: Transmit buffer empty flag + * @arg I2S_FLAG_UDR: Underrun flag + * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_FRE: Frame error flag + * @arg I2S_FLAG_CHSIDE: Channel Side flag + * @arg I2S_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the I2S OVR pending flag. + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\ + tmpreg = (__HANDLE__)->Instance->SR;\ + }while(0) +/** @brief Clears the I2S UDR pending flag. + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); + + /* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); + +/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ +void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); +HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32L100xC || + STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\ + STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L151xE ||\\ + STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_I2S_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h new file mode 100644 index 000000000..ca1264730 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h @@ -0,0 +1,535 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_irda.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains all the functions prototypes for the IRDA + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_IRDA_H +#define __STM32L1xx_HAL_IRDA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup IRDA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Types IRDA Exported Types + * @{ + */ + +/** + * @brief IRDA Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref IRDA_Word_Length */ + + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref IRDA_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref IRDA_Transfer_Mode */ + + uint8_t Prescaler; /*!< Specifies the Prescaler */ + + uint32_t IrDAMode; /*!< Specifies the IrDA mode + This parameter can be a value of @ref IRDA_Low_Power */ +}IRDA_InitTypeDef; + +/** + * @brief HAL IRDA State structures definition + */ +typedef enum +{ + HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ +}HAL_IRDA_StateTypeDef; + +/** + * @brief HAL IRDA Error Code structure definition + */ +typedef enum +{ + HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */ + HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */ + HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */ + HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */ + HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */ +}HAL_IRDA_ErrorTypeDef; + +/** + * @brief IRDA handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /* USART registers base address */ + + IRDA_InitTypeDef Init; /* IRDA communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */ + + uint16_t TxXferSize; /* IRDA Tx Transfer size */ + + uint16_t TxXferCount; /* IRDA Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */ + + uint16_t RxXferSize; /* IRDA Rx Transfer size */ + + uint16_t RxXferCount; /* IRDA Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */ + + __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */ + +}IRDA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Constants IRDA Exported constants + * @{ + */ + +/** @defgroup IRDA_Word_Length IRDA Word Length + * @{ + */ +#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) +#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ + ((LENGTH) == IRDA_WORDLENGTH_9B)) +/** + * @} + */ + + +/** @defgroup IRDA_Parity IRDA Parity + * @{ + */ +#define IRDA_PARITY_NONE ((uint32_t)0x00000000) +#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ + ((PARITY) == IRDA_PARITY_EVEN) || \ + ((PARITY) == IRDA_PARITY_ODD)) +/** + * @} + */ + + +/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode + * @{ + */ +#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) +#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) +#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000)) +/** + * @} + */ + +/** @defgroup IRDA_Low_Power IRDA Low Power + * @{ + */ +#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) +#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) +#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ + ((MODE) == IRDA_POWERMODE_NORMAL)) +/** + * @} + */ + +/** @defgroup IRDA_Flags IRDA Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ +#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC) +#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE) +#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE) +#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask in the XX register + * - Y : Interrupt source register (4 bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * + * @{ + */ + +#define IRDA_IT_PE ((uint32_t)0x10000100) +#define IRDA_IT_TXE ((uint32_t)0x10000080) +#define IRDA_IT_TC ((uint32_t)0x10000040) +#define IRDA_IT_RXNE ((uint32_t)0x10000020) +#define IRDA_IT_IDLE ((uint32_t)0x10000010) + +#define IRDA_IT_LBD ((uint32_t)0x20000040) + +#define IRDA_IT_CTS ((uint32_t)0x30000400) +#define IRDA_IT_ERR ((uint32_t)0x30000001) + +/** + * @} + */ + +/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask + * @{ + */ +#define IRDA_IT_MASK ((uint32_t)0x0000FFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Macros IRDA Exported Macros + * @{ + */ + +/** @brief Reset IRDA handle state + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) + +/** @brief Flushs the IRDA DR register + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + */ +#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified IRDA flag is set or not. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IRDA_FLAG_TXE: Transmit data register empty flag + * @arg IRDA_FLAG_TC: Transmission Complete flag + * @arg IRDA_FLAG_RXNE: Receive data register not empty flag + * @arg IRDA_FLAG_IDLE: Idle Line detection flag + * @arg IRDA_FLAG_ORE: OverRun Error flag + * @arg IRDA_FLAG_NE: Noise Error flag + * @arg IRDA_FLAG_FE: Framing Error flag + * @arg IRDA_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified IRDA pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg IRDA_FLAG_TC: Transmission Complete flag. + * @arg IRDA_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clear the IRDA PE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the IRDA FE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the IRDA NE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the IRDA ORE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the IRDA IDLE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enables the specified IRDA interrupt. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. + * This parameter can be one of the following values: + * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt + * @arg IRDA_IT_TC: Transmission complete interrupt + * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt + * @arg IRDA_IT_IDLE: Idle line detection interrupt + * @arg IRDA_IT_PE: Parity Error interrupt + * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK))) + +/** @brief Disables the specified IRDA interrupt. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. + * This parameter can be one of the following values: + * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt + * @arg IRDA_IT_TC: Transmission complete interrupt + * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt + * @arg IRDA_IT_IDLE: Idle line detection interrupt + * @arg IRDA_IT_PE: Parity Error interrupt + * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK))) + +/** @brief Checks whether the specified IRDA interrupt has occurred or not. + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __IT__: specifies the IRDA interrupt source to check. + * This parameter can be one of the following values: + * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt + * @arg IRDA_IT_TC: Transmission complete interrupt + * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt + * @arg IRDA_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ERR: Error interrupt + * @arg IRDA_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK)) + +/** @brief Enable UART/USART associated to IRDA Handle + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) + +/** @brief Disable UART/USART associated to IRDA Handle + * @param __HANDLE__: specifies the IRDA Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup IRDA_Private_Macros IRDA Private Macros + * @{ + */ + +#define IRDA_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) +#define IRDA_DIVMANT(__PCLK__, __BAUD__) (IRDA_DIV((__PCLK__), (__BAUD__))/100) +#define IRDA_DIVFRAQ(__PCLK__, __BAUD__) (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) +#define IRDA_BRR(__PCLK__, __BAUD__) ((IRDA_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(IRDA_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) + +/** @brief Ensure that IRDA Baud rate is less or equal to maximum value + * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * @retval True or False + */ +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_IRDA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h new file mode 100644 index 000000000..6c7842d73 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_iwdg.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of IWDG HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_IWDG_H +#define __STM32L1xx_HAL_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Types IWDG Exported Types + * @{ + */ + +/** + * @brief IWDG HAL State Structure definition + */ +typedef enum +{ + HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ + HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ + HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ + HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ + HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ + +}HAL_IWDG_StateTypeDef; + +/** + * @brief IWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Select the prescaler of the IWDG. + This parameter can be a value of @ref IWDG_Prescaler */ + + uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + +}IWDG_InitTypeDef; + +/** + * @brief IWDG Handle Structure definition + */ +typedef struct +{ + IWDG_TypeDef *Instance; /*!< Register base address */ + + IWDG_InitTypeDef Init; /*!< IWDG required parameters */ + + HAL_LockTypeDef Lock; /*!< IWDG Locking object */ + + __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ + +}IWDG_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_Registers_BitMask IWDG_Registers_BitMask + * @brief IWDG registers bit mask + * @{ + */ +/* --- KR Register ---*/ +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ +#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ +#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ +#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ + +#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \ + ((__KR__) == KR_KEY_ENABLE))|| \ + ((__KR__) == KR_KEY_EWA)) || \ + ((__KR__) == KR_KEY_DWA)) +/** + * @} + */ + +/** @defgroup IWDG_Flag_definition IWDG_Flag_definition + * @{ + */ +#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */ +#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */ + +/** + * @} + */ + +/** @defgroup IWDG_Prescaler IWDG_Prescaler + * @{ + */ +#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ + +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)) + +/** + * @} + */ + +/** @defgroup IWDG_Reload_Value IWDG_Reload_Value + * @{ + */ +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @brief Reset IWDG handle state + * @param __HANDLE__: IWDG handle. + * @retval None + */ +#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) + +/** + * @brief Enables the IWDG peripheral. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE) + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD) + +/** + * @brief Enables write access to IWDG_PR and IWDG_RLR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA) + +/** + * @brief Disables write access to IWDG_PR and IWDG_RLR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA) + +/** + * @brief Gets the selected IWDG's flag status. + * @param __HANDLE__: IWDG handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag + * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +/** @addtogroup IWDG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); + +/** + * @} + */ + +/** @addtogroup IWDG_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_IWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h new file mode 100644 index 000000000..e65ec99ce --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h @@ -0,0 +1,763 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_lcd.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of LCD Controller HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_LCD_H +#define __STM32L1xx_HAL_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup LCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup LCD_Exported_Types LCD Exported Types + * @{ + */ + +/** + * @brief LCD Init structure definition + */ + +typedef struct +{ + uint32_t Prescaler; /*!< Configures the LCD Prescaler. + This parameter can be one value of @ref LCD_Prescaler */ + uint32_t Divider; /*!< Configures the LCD Divider. + This parameter can be one value of @ref LCD_Divider */ + uint32_t Duty; /*!< Configures the LCD Duty. + This parameter can be one value of @ref LCD_Duty */ + uint32_t Bias; /*!< Configures the LCD Bias. + This parameter can be one value of @ref LCD_Bias */ + uint32_t VoltageSource; /*!< Selects the LCD Voltage source. + This parameter can be one value of @ref LCD_Voltage_Source */ + uint32_t Contrast; /*!< Configures the LCD Contrast. + This parameter can be one value of @ref LCD_Contrast */ + uint32_t DeadTime; /*!< Configures the LCD Dead Time. + This parameter can be one value of @ref LCD_DeadTime */ + uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration. + This parameter can be one value of @ref LCD_PulseOnDuration */ + uint32_t BlinkMode; /*!< Configures the LCD Blink Mode. + This parameter can be one value of @ref LCD_BlinkMode */ + uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency. + This parameter can be one value of @ref LCD_BlinkFrequency */ + uint32_t MuxSegment; /*!< Enable or disable mux segment. + This parameter can be set to ENABLE or DISABLE. */ +}LCD_InitTypeDef; + +/** + * @brief HAL LCD State structures definition + */ +typedef enum +{ + HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ + HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_LCD_STATE_ERROR = 0x04 /*!< Error */ +}HAL_LCD_StateTypeDef; + +/** + * @brief HAL LCD Error Code structure definition + */ +typedef enum +{ + HAL_LCD_ERROR_NONE = 0x00, /*!< No error */ + HAL_LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag timeout error */ + HAL_LCD_ERROR_UDR = 0x02, /*!< Update display request flag timeout error */ + HAL_LCD_ERROR_UDD = 0x04, /*!< Update display done flag timeout error */ + HAL_LCD_ERROR_ENS = 0x08, /*!< LCD enabled status flag timeout error */ + HAL_LCD_ERROR_RDY = 0x10 /*!< LCD Booster ready timeout error */ +}HAL_LCD_ErrorTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct +{ + LCD_TypeDef *Instance; /* LCD registers base address */ + + LCD_InitTypeDef Init; /* LCD communication parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + __IO HAL_LCD_StateTypeDef State; /* LCD communication state */ + + __IO HAL_LCD_ErrorTypeDef ErrorCode; /* LCD Error code */ + +}LCD_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup LCD_Exported_Constants LCD Exported Constants + * @{ + */ + +/** @defgroup LCD_Prescaler LCD Prescaler + * @{ + */ + +#define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */ +#define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */ +#define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */ +#define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */ +#define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */ +#define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */ +#define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */ +#define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */ +#define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */ +#define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */ +#define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */ +#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */ +#define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ +#define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ +#define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ +#define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */ + +#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \ + ((__PRESCALER__) == LCD_PRESCALER_2) || \ + ((__PRESCALER__) == LCD_PRESCALER_4) || \ + ((__PRESCALER__) == LCD_PRESCALER_8) || \ + ((__PRESCALER__) == LCD_PRESCALER_16) || \ + ((__PRESCALER__) == LCD_PRESCALER_32) || \ + ((__PRESCALER__) == LCD_PRESCALER_64) || \ + ((__PRESCALER__) == LCD_PRESCALER_128) || \ + ((__PRESCALER__) == LCD_PRESCALER_256) || \ + ((__PRESCALER__) == LCD_PRESCALER_512) || \ + ((__PRESCALER__) == LCD_PRESCALER_1024) || \ + ((__PRESCALER__) == LCD_PRESCALER_2048) || \ + ((__PRESCALER__) == LCD_PRESCALER_4096) || \ + ((__PRESCALER__) == LCD_PRESCALER_8192) || \ + ((__PRESCALER__) == LCD_PRESCALER_16384) || \ + ((__PRESCALER__) == LCD_PRESCALER_32768)) + +/** + * @} + */ + +/** @defgroup LCD_Divider LCD Divider + * @{ + */ + +#define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */ +#define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */ +#define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */ +#define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */ +#define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */ +#define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */ +#define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */ +#define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */ +#define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */ +#define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */ +#define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */ +#define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */ +#define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ +#define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ +#define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ +#define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */ + +#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \ + ((__DIVIDER__) == LCD_DIVIDER_17) || \ + ((__DIVIDER__) == LCD_DIVIDER_18) || \ + ((__DIVIDER__) == LCD_DIVIDER_19) || \ + ((__DIVIDER__) == LCD_DIVIDER_20) || \ + ((__DIVIDER__) == LCD_DIVIDER_21) || \ + ((__DIVIDER__) == LCD_DIVIDER_22) || \ + ((__DIVIDER__) == LCD_DIVIDER_23) || \ + ((__DIVIDER__) == LCD_DIVIDER_24) || \ + ((__DIVIDER__) == LCD_DIVIDER_25) || \ + ((__DIVIDER__) == LCD_DIVIDER_26) || \ + ((__DIVIDER__) == LCD_DIVIDER_27) || \ + ((__DIVIDER__) == LCD_DIVIDER_28) || \ + ((__DIVIDER__) == LCD_DIVIDER_29) || \ + ((__DIVIDER__) == LCD_DIVIDER_30) || \ + ((__DIVIDER__) == LCD_DIVIDER_31)) + +/** + * @} + */ + + +/** @defgroup LCD_Duty LCD Duty + * @{ + */ + +#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */ +#define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */ +#define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */ +#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */ +#define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */ + +#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \ + ((__DUTY__) == LCD_DUTY_1_2) || \ + ((__DUTY__) == LCD_DUTY_1_3) || \ + ((__DUTY__) == LCD_DUTY_1_4) || \ + ((__DUTY__) == LCD_DUTY_1_8)) + +/** + * @} + */ + + +/** @defgroup LCD_Bias LCD Bias + * @{ + */ + +#define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */ +#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ +#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ + +#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \ + ((__BIAS__) == LCD_BIAS_1_2) || \ + ((__BIAS__) == LCD_BIAS_1_3)) +/** + * @} + */ + +/** @defgroup LCD_Voltage_Source LCD Voltage Source + * @{ + */ + +#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */ +#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */ + +#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \ + ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL)) + +/** + * @} + */ + +/** @defgroup LCD_Interrupts LCD Interrupts + * @{ + */ +#define LCD_IT_SOF LCD_FCR_SOFIE +#define LCD_IT_UDD LCD_FCR_UDDIE + +/** + * @} + */ + +/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration + * @{ + */ + +#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ +#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */ +#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */ +#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */ +#define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */ +#define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */ +#define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */ +#define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */ + +#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \ + ((__DURATION__) == LCD_PULSEONDURATION_1) || \ + ((__DURATION__) == LCD_PULSEONDURATION_2) || \ + ((__DURATION__) == LCD_PULSEONDURATION_3) || \ + ((__DURATION__) == LCD_PULSEONDURATION_4) || \ + ((__DURATION__) == LCD_PULSEONDURATION_5) || \ + ((__DURATION__) == LCD_PULSEONDURATION_6) || \ + ((__DURATION__) == LCD_PULSEONDURATION_7)) +/** + * @} + */ + + +/** @defgroup LCD_DeadTime LCD Dead Time + * @{ + */ + +#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */ +#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */ +#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */ +#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */ +#define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */ +#define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */ +#define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */ +#define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */ + +#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \ + ((__TIME__) == LCD_DEADTIME_1) || \ + ((__TIME__) == LCD_DEADTIME_2) || \ + ((__TIME__) == LCD_DEADTIME_3) || \ + ((__TIME__) == LCD_DEADTIME_4) || \ + ((__TIME__) == LCD_DEADTIME_5) || \ + ((__TIME__) == LCD_DEADTIME_6) || \ + ((__TIME__) == LCD_DEADTIME_7)) +/** + * @} + */ + +/** @defgroup LCD_BlinkMode LCD Blink Mode + * @{ + */ + +#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */ +#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ +#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to + 8 pixels according to the programmed duty) */ +#define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */ + +#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \ + ((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \ + ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \ + ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM)) +/** + * @} + */ + +/** @defgroup LCD_BlinkFrequency LCD Blink Frequency + * @{ + */ + +#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ +#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */ +#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */ +#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */ +#define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */ +#define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */ +#define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */ +#define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */ + +#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024)) +/** + * @} + */ + +/** @defgroup LCD_Contrast LCD Contrast + * @{ + */ + +#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ +#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */ +#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */ +#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */ +#define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */ +#define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V */ +#define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V */ +#define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.51V */ + +#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_7)) +/** + * @} + */ + +/** @defgroup LCD_MuxSegment LCD Mux Segment + * @{ + */ + +#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */ +#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */ + +#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \ + ((__VALUE__) == LCD_MUXSEGMENT_DISABLE)) +/** + * @} + */ + +/** @defgroup LCD_Flag LCD Flag + * @{ + */ + +#define LCD_FLAG_ENS LCD_SR_ENS +#define LCD_FLAG_SOF LCD_SR_SOF +#define LCD_FLAG_UDR LCD_SR_UDR +#define LCD_FLAG_UDD LCD_SR_UDD +#define LCD_FLAG_RDY LCD_SR_RDY +#define LCD_FLAG_FCRSF LCD_SR_FCRSR + +/** + * @} + */ + +/** @defgroup LCD_RAMRegister LCD RAMRegister + * @{ + */ + +#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */ +#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */ +#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */ +#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */ +#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */ +#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */ +#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */ +#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */ +#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */ +#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */ +#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */ +#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */ +#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */ +#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */ +#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ +#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ + +#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \ + ((__REGISTER__) == LCD_RAM_REGISTER1) || \ + ((__REGISTER__) == LCD_RAM_REGISTER2) || \ + ((__REGISTER__) == LCD_RAM_REGISTER3) || \ + ((__REGISTER__) == LCD_RAM_REGISTER4) || \ + ((__REGISTER__) == LCD_RAM_REGISTER5) || \ + ((__REGISTER__) == LCD_RAM_REGISTER6) || \ + ((__REGISTER__) == LCD_RAM_REGISTER7) || \ + ((__REGISTER__) == LCD_RAM_REGISTER8) || \ + ((__REGISTER__) == LCD_RAM_REGISTER9) || \ + ((__REGISTER__) == LCD_RAM_REGISTER10) || \ + ((__REGISTER__) == LCD_RAM_REGISTER11) || \ + ((__REGISTER__) == LCD_RAM_REGISTER12) || \ + ((__REGISTER__) == LCD_RAM_REGISTER13) || \ + ((__REGISTER__) == LCD_RAM_REGISTER14) || \ + ((__REGISTER__) == LCD_RAM_REGISTER15)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup LCD_Exported_Macros LCD Exported Macros + * @{ + */ + +/** @brief Reset LCD handle state + * @param __HANDLE__: specifies the LCD Handle. + * @retval None + */ +#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET) + +/** @brief macros to enables or disables the LCD + * @param __HANDLE__: specifies the LCD Handle. + * @retval None + */ +#define __HAL_LCD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) +#define __HAL_LCD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) + +/** @brief Macros to enable or disable the low resistance divider. Displays with high + * internal resistance may need a longer drive time to achieve + * satisfactory contrast. This function is useful in this case if some + * additional power consumption can be tolerated. + * @param __HANDLE__: specifies the LCD Handle. + * @note When this mode is enabled, the PulseOn Duration (PON) have to be + * programmed to 1/CK_PS (LCD_PULSEONDURATION_1). + * @retval None + */ +#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) + +#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) + +/** + * @brief Macro to configure the LCD pulses on duration. + * @param __HANDLE__: specifies the LCD Handle. + * @param __DURATION__: specifies the LCD pulse on duration in terms of + * CK_PS (prescaled LCD clock period) pulses. + * This parameter can be one of the following values: + * @arg LCD_PULSEONDURATION_0: 0 pulse + * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS + * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS + * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS + * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS + * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS + * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS + * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS + * @retval None + */ +#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__) \ + do{ \ + MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) + +/** + * @brief Macro to configure the LCD dead time. + * @param __HANDLE__: specifies the LCD Handle. + * @param __DEADTIME__: specifies the LCD dead time. + * This parameter can be one of the following values: + * @arg LCD_DEADTIME_0: No dead Time + * @arg LCD_DEADTIME_1: One Phase between different couple of Frame + * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame + * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame + * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame + * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame + * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame + * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame + * @retval None + */ +#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__) \ + do{ \ + MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) + +/** + * @brief Macro to configure the LCD Contrast. + * @param __HANDLE__: specifies the LCD Handle. + * @param __CONTRAST__: specifies the LCD Contrast. + * This parameter can be one of the following values: + * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V + * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V + * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V + * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V + * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V + * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V + * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V + * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V + * @retval None + */ +#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__) \ + do{ \ + MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \ + LCD_WaitForSynchro(__HANDLE__); \ + } while(0) + +/** + * @brief Macro to configure the LCD Blink mode and Blink frequency. + * @param __HANDLE__: specifies the LCD Handle. + * @param __BLINKMODE__: specifies the LCD blink mode. + * This parameter can be one of the following values: + * @arg LCD_BLINKMODE_OFF: Blink disabled + * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel) + * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 + * pixels according to the programmed duty) + * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM + * (all pixels) + * @param __BLINKFREQUENCY__: specifies the LCD blink frequency. + * @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8 + * @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16 + * @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32 + * @arg LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64 + * @arg LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128 + * @arg LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256 + * @arg LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512 + * @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024 + * @retval None + */ +#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__) \ + do{ \ + MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) + +/** @brief Enables or disables the specified LCD interrupt. + * @param __HANDLE__: specifies the LCD Handle. + * @param __INTERRUPT__: specifies the LCD interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt + * @retval None + */ +#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) +#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) + +/** @brief Checks whether the specified LCD interrupt is enabled or not. + * @param __HANDLE__: specifies the LCD Handle. + * @param __IT__: specifies the LCD interrupt source to check. + * This parameter can be one of the following values: + * @arg LCD_IT_SOF: Start of Frame Interrupt + * @arg LCD_IT_UDD: Update Display Done Interrupt. + * @note If the device is in STOP mode (PCLK not provided) UDD will not + * generate an interrupt even if UDDIE = 1. + * If the display is not enabled the UDD interrupt will never occur. + * @retval The state of __IT__ (TRUE or FALSE). + */ +#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__)) + +/** @brief Checks whether the specified LCD flag is set or not. + * @param __HANDLE__: specifies the LCD Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. + * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR + * goes from 0 to 1. On deactivation it reflects the real status of + * LCD so it becomes 0 at the end of the last displayed frame. + * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at + * the beginning of a new frame, at the same time as the display data is + * updated. + * @arg LCD_FLAG_UDR: Update Display Request flag. + * @arg LCD_FLAG_UDD: Update Display Done flag. + * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status + * of the step-up converter. + * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. + * This flag is set by hardware each time the LCD_FCR register is updated + * in the LCDCLK domain. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified LCD pending flag. + * @param __HANDLE__: specifies the LCD Handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LCD_FLAG_SOF: Start of Frame Interrupt + * @arg LCD_FLAG_UDD: Update Display Done Interrupt + * @retval None + */ +#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLR = (__FLAG__)) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ + +/** @addtogroup LCD_Exported_Functions + * @{ + */ + +/** @addtogroup LCD_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization methods **********************************/ +HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd); +HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd); +void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd); +void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd); + +/** + * @} + */ + +/** @addtogroup LCD_Exported_Functions_Group2 + * @{ + */ + +/* IO operation methods *******************************************************/ +HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data); +HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd); +HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd); + +/** + * @} + */ + +/** @addtogroup LCD_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral State methods **************************************************/ +HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd); +uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup LCD_Private_Functions + * @{ + */ + +/* Private functions ---------------------------------------------------------*/ +HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_LCD_H */ + +/******************* (C) COPYRIGHT 2014 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h new file mode 100644 index 000000000..1401fc2e3 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_nor.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of NOR HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_NOR_H +#define __STM32L1xx_HAL_NOR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_ll_fsmc.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup NOR + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup NOR_Exported_typedef NOR Exported typedef + * @{ + */ + +/** + * @brief HAL SRAM State structures definition + */ +typedef enum +{ + HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ + HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ + HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ + HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ + HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ + +}HAL_NOR_StateTypeDef; + +/** + * @brief FSMC NOR Status typedef + */ +typedef enum +{ + NOR_SUCCESS = 0, + NOR_ONGOING, + NOR_ERROR, + NOR_TIMEOUT + +}NOR_StatusTypedef; + +/** + * @brief FSMC NOR ID typedef + */ +typedef struct +{ + uint16_t ManufacturerCode; /*!< Defines the device's manufacturer code used to identify the memory */ + + uint16_t DeviceCode1; + + uint16_t DeviceCode2; + + uint16_t DeviceCode3; /*!< Defines the devices' codes used to identify the memory. + These codes can be accessed by performing read operations with specific + control signals and addresses set.They can also be accessed by issuing + an Auto Select command */ + +}NOR_IDTypeDef; + + +/** + * @brief FSMC NOR CFI typedef + */ +typedef struct +{ + /*!< Defines the information stored in the memory's Common flash interface + which contains a description of various electrical and timing parameters, + density information and functions supported by the memory */ + + uint16_t CFI1; + + uint16_t CFI2; + + uint16_t CFI3; + + uint16_t CFI4; + +}NOR_CFITypeDef; + +/** + * @brief NOR handle Structure definition + */ +typedef struct +{ + FSMC_NORSRAM_TYPEDEF *Instance; /*!< Register base address */ + + FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended; /*!< Extended mode register base address */ + + FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< NOR locking object */ + + __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + +}NOR_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup NOR_Exported_Constants NOR Exported Constants + * @{ + */ + +/* NOR device IDs addresses */ +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) + +/* NOR CFI IDs addresses */ +#define CFI1_ADDRESS ((uint16_t)0x10) +#define CFI2_ADDRESS ((uint16_t)0x11) +#define CFI3_ADDRESS ((uint16_t)0x12) +#define CFI4_ADDRESS ((uint16_t)0x13) + +/* NOR operation wait timeout */ +#define NOR_TMEOUT ((uint16_t)0xFFFF) + +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x0) +#define NOR_MEMORY_16B ((uint8_t)0x1) + +/* NOR memory device read/write start address */ +#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) +#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) +#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) +#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup NOR_Exported_macro NOR Exported macro + * @{ + */ + +/** @brief Reset NOR handle state + * @param __HANDLE__: NOR handle + * @retval None + */ +#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) + + +/** + * @brief NOR memory address shifting. + * @param __NOR_ADDRESS: NOR base address + * @param __NOR_MEMORY_WIDTH_: NOR memory width + * @param __ADDRESS__: NOR memory address + * @retval NOR shifted address value + */ +#define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) + +/** + * @brief NOR memory write data to specified address. + * @param __ADDRESS__: NOR memory address + * @param __DATA__: Data to write + * @retval None + */ +#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup NOR_Exported_Functions + * @{ + */ + +/** @addtogroup NOR_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); +void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); +void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); +void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); + +/** + * @} + */ + +/** @addtogroup NOR_Exported_Functions_Group2 + * @{ + */ + +/* I/O operation functions *****************************************************/ +HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); +HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); +HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); +HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); + +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); + +HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); +HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); +HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); + +/** + * @} + */ + +/** @addtogroup NOR_Exported_Functions_Group3 + * @{ + */ + +/* NOR Control functions *******************************************************/ +HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); +HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); + +/** + * @} + */ + +/** @addtogroup NOR_Exported_Functions_Group4 + * @{ + */ + +/* NOR State functions **********************************************************/ +HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); +NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_NOR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h new file mode 100644 index 000000000..dc6726f76 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_opamp.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of OPAMP HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_OPAMP_H +#define __STM32L1xx_HAL_OPAMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup OPAMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup OPAMP_Exported_Types OPAMP Exported Types + * @{ + */ +/** + * @brief OPAMP Init structure definition + */ + +typedef struct +{ + uint32_t PowerSupplyRange; /*!< Specifies the power supply range: above or under 2.4V. + This parameter must be a value of @ref OPAMP_PowerSupplyRange + Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */ + + uint32_t UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref OPAMP_UserTrimming + UserTrimming is either factory or user trimming. + Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */ + + uint32_t Mode; /*!< Specifies the OPAMP mode + This parameter must be a value of @ref OPAMP_Mode + mode is either Standalone or Follower */ + + uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone mode + - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE + This parameter must be a value of @ref OPAMP_InvertingInput + InvertingInput is either VM0 or VM1 + - In Follower mode: i.e when mode is OPAMP_FOLLOWER_MODE + This parameter is Not Applicable */ + + uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: + This parameter must be a value of @ref OPAMP_NonInvertingInput + NonInvertingInput is either VP0, VP1 or VP2 */ + + uint32_t PowerMode; /*!< Specifies the power mode Normal or Low-Power. + This parameter must be a value of @ref OPAMP_PowerMode */ + + uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ + + uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ + + uint32_t TrimmingValuePLowPower; /*!< Specifies the offset trimming value (PMOS) + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ + + uint32_t TrimmingValueNLowPower; /*!< Specifies the offset trimming value (NMOS) + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ + +}OPAMP_InitTypeDef; + +/** + * @brief HAL State structures definition + */ + +typedef enum +{ + HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPMAP is not yet Initialized */ + + HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */ + HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */ + + HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */ + HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005, /*!< OPAMP is locked + only system reset allows reconfiguring the opamp. */ + +}HAL_OPAMP_StateTypeDef; + +/** + * @brief OPAMP Handle Structure definition + */ +typedef struct +{ + OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */ + OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */ + HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */ + +} OPAMP_HandleTypeDef; + +/** + * @brief OPAMP_TrimmingValueTypeDef @brief definition + */ + +typedef uint32_t OPAMP_TrimmingValueTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants + * @{ + */ + +/** + * OTR register Mask + */ +#define OPAMP_TRIM_VALUE_MASK OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW + +/** + * CSR register Mask + */ +#define OPAMP_CSR_INSTANCE_OFFSET ((uint32_t) 8) /* Offset of each OPAMP instance into register CSR */ +#define OPAMP_OTR_INSTANCE_OFFSET ((uint32_t) 10) /* Offset of each OPAMP instance into register OTR */ + + +/** @defgroup OPAMP_Mode OPAMP Mode + * @{ + */ +#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< OPAMP standalone mode */ +#define OPAMP_FOLLOWER_MODE ((uint32_t)0x00000001) /*!< OPAMP follower mode */ + +#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \ + ((INPUT) == OPAMP_FOLLOWER_MODE)) +/** + * @} + */ + +/** @defgroup OPAMP_NonInvertingInput OPAMP NonInvertingInput + * @{ + */ +#define OPAMP_NONINVERTINGINPUT_VP0 ((uint32_t)0x00000000) /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */ +#define OPAMP_NONINVERTINGINPUT_DAC_CH1 ((uint32_t)0x00000001) /*!< Comparator non-inverting input connected internally to DAC channel 1 */ +#define OPAMP_NONINVERTINGINPUT_DAC_CH2 ((uint32_t)0x00000002) /*!< Comparator non-inverting input connected internally to DAC channel 2. Available on OPAMP2 only. */ + +#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_VP0) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) || \ + ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2) ) +/** + * @} + */ + +/** @defgroup OPAMP_InvertingInput OPAMP InvertingInput + * @{ + */ +#define OPAMP_INVERTINGINPUT_VM0 ((uint32_t)0x00000000) /*!< Comparator inverting input connected to dedicated IO pin low-leakage */ +#define OPAMP_INVERTINGINPUT_VM1 ((uint32_t)0x00000001) /*!< Comparator inverting input connected to alternative IO pin available on some device packages */ + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_INVERTINGINPUT_VM1 /*!< Alternate name for comparator inverting input connected to alternative IO pin available on some device packages */ + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_VM0 /* For compatibility with other STM32 devices */ +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_VM1 /* For compatibility with other STM32 devices */ + +#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_VM0) || \ + ((INPUT) == OPAMP_INVERTINGINPUT_VM1) ) +/** + * @} + */ + +/** @defgroup OPAMP_PowerMode OPAMP PowerMode + * @{ + */ +#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000) +#define OPAMP_POWERMODE_LOWPOWER ((uint32_t)0x00000001) + +#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \ + ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) ) +/** + * @} + */ + +/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange + * @{ + */ +#define OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000) /*!< Power supply range low (VDDA lower than 2.4V) */ +#define OPAMP_POWERSUPPLY_HIGH OPAMP_CSR_AOP_RANGE /*!< Power supply range high (VDDA higher than 2.4V) */ + +#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \ + ((RANGE) == OPAMP_POWERSUPPLY_HIGH) ) +/** + * @} + */ + +/** @defgroup OPAMP_UserTrimming OPAMP UserTrimming + * @{ + */ +#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ +#define OPAMP_TRIMMING_USER OPAMP_OTR_OT_USER /*!< User trimming */ + +#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \ + ((TRIMMING) == OPAMP_TRIMMING_USER)) +/** + * @} + */ + +/** @defgroup OPAMP_FactoryTrimming OPAMP FactoryTrimming + * @{ + */ +#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy value if trimming value could not be retrieved */ + +#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000000) /*!< Offset trimming P */ +#define OPAMP_FACTORYTRIMMING_N POSITION_VAL(OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH) /*!< Offset trimming N */ + +#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \ + ((TRIMMING) == OPAMP_FACTORYTRIMMING_P) ) +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup OPAMP_Private_Constants OPAMP Private Constants + * @{ + */ + +/* Offset trimming time: during calibration, minimum time needed between two */ +/* steps to have 1 mV accuracy. */ +/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/ +/* Unit: ms. */ +#define OPAMP_TRIMMING_DELAY ((uint32_t) 1) + +/** + * @} + */ + + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup OPAMP_Private_Macro OPAMP Private Macro + * @{ + */ + +/** @brief Reset OPAMP handle state + * @param __HANDLE__: OPAMP handle. + * @retval None + */ +#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET) + +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup OPAMP_Private_Macro OPAMP Private Macro + * @{ + */ + +/** + * @brief Select the OPAMP bit OPAxPD (power-down) corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_OPAXPD(__HANDLE__) \ + (OPAMP_CSR_OPA1PD << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bit S3SELx (switch 3) corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_S3SELX(__HANDLE__) \ + (OPAMP_CSR_S3SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bit S4SELx (switch 4) corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_S4SELX(__HANDLE__) \ + (OPAMP_CSR_S4SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bit S5SELx (switch 5) corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_S5SELX(__HANDLE__) \ + (OPAMP_CSR_S5SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bit S3SELx (switch 6) corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_S6SELX(__HANDLE__) \ + (OPAMP_CSR_S6SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bit OPAxCAL_L (offset calibration for differential + * pair P) corresponding to the selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_OPAXCAL_L(__HANDLE__) \ + (OPAMP_CSR_OPA1CAL_L << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bit OPAxCAL_H (offset calibration for differential + * pair N) corresponding to the selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_OPAXCAL_H(__HANDLE__) \ + (OPAMP_CSR_OPA1CAL_H << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bit OPAxLPM (low power mode) corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_OPAXLPM(__HANDLE__) \ + (OPAMP_CSR_OPA1LPM << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) + +/** + * @brief Select the OPAMP bits of all switches corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_ALL_SWITCHES(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance != OPAMP2) \ + )? \ + ( \ + ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ + | \ + (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) \ + ) \ + : \ + ( \ + ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ + | \ + (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) \ + | \ + (OPAMP_CSR_S7SEL2) \ + ) \ + ) + +/** + * @brief Select the OPAMP bit ANAWSELx (switch SanA) corresponding to the + * selected OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_ANAWSELX(__HANDLE__) \ + (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) + +/** + * @brief Select the OPAMP bit OPAxCALOUT in function of the selected + * OPAMP instance. + * @param __HANDLE__: OPAMP handle + * @retval None + */ +#define __OPAMP_CSR_OPAXCALOUT(__HANDLE__) \ + (OPAMP_CSR_OPA1CALOUT << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) + +/** + * @brief Select the OPAMP trimming bits position value (position of LSB) + * in register OPAMP_OTR or register OPAMP_LPOTR in function of the selected + * OPAMP instance and the transistors differential pair high (PMOS) or + * low (NMOS). + * @param __HANDLE__: OPAMP handle + * @param __TRIM_HIGH_LOW__: transistors differential pair high or low. + * Must be a value of @ref OPAMP_FactoryTrimming. + * @retval None + */ +#define __OPAMP_OFFSET_TRIM_BITSPOSITION(__HANDLE__, __TRIM_HIGH_LOW__) \ + ((__OPAMP_INSTANCE_DECIMAL__((__HANDLE__)) * OPAMP_OTR_INSTANCE_OFFSET) + (__TRIM_HIGH_LOW__)) + +/** + * @brief Shift the OPAMP trimming bits to register OPAMP_OTR or register + * OPAMP_LPOTR in function of the selected OPAMP instance and the transistors + * differential pair high (PMOS) or low (NMOS). + * @param __HANDLE__: OPAMP handle + * @param __TRIM_HIGH_LOW__: transistors differential pair high or low. + * Must be a value of @ref OPAMP_FactoryTrimming. + * @param __TRIMMING_VALUE__: Trimming value + * @retval None + */ +#define __OPAMP_OFFSET_TRIM_SET(__HANDLE__, __TRIM_HIGH_LOW__, __TRIMMING_VALUE__) \ + ((__TRIMMING_VALUE__) << (__OPAMP_OFFSET_TRIM_BITSPOSITION((__HANDLE__), (__TRIM_HIGH_LOW__)))) + +/** + * @brief Check that trimming value is within correct range + * @param TRIMMINGVALUE: OPAMP trimming value + * @retval None + */ +#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1E) + +/** + * @} + */ + + +/* Include OPAMP HAL Extension module */ +#include "stm32l1xx_hal_opamp_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup OPAMP_Exported_Functions + * @{ + */ + +/** @addtogroup OPAMP_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp); +void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp); +void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp); +/** + * @} + */ + +/** @addtogroup OPAMP_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions *****************************************************/ +HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); +OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); +/** + * @} + */ + +/** @addtogroup OPAMP_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); +/** + * @} + */ + +/** @addtogroup OPAMP_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); +/** + * @} + */ + +/** + * @} + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_OPAMP_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h new file mode 100644 index 000000000..d3a34ca17 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h @@ -0,0 +1,225 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_opamp_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of OPAMP HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_OPAMP_EX_H +#define __STM32L1xx_HAL_OPAMP_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup OPAMPEx + * @{ + */ + + + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants ---------------------------------------------------------*/ +/** @defgroup OPAMPEx_Exported_Constants OPAMPEx Exported Constants + * @{ + */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#define OPAMP_CSR_OPAXPD_ALL \ + (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD | OPAMP_CSR_OPA3PD) + +#define OPAMP_CSR_OPAXCAL_L_ALL \ + (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA3CAL_L) + +#define OPAMP_CSR_OPAXCAL_H_ALL \ + (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H | OPAMP_CSR_OPA3CAL_H) + +#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS \ + (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \ + OPAMP_CSR_ANAWSEL1 | \ + OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \ + OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2 | \ + OPAMP_CSR_S3SEL3 | OPAMP_CSR_S4SEL3 | OPAMP_CSR_S5SEL3 | OPAMP_CSR_S6SEL3 | \ + OPAMP_CSR_ANAWSEL3 ) +#else +#define OPAMP_CSR_OPAXPD_ALL \ + (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD) + +#define OPAMP_CSR_OPAXCAL_L_ALL \ + (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L) + +#define OPAMP_CSR_OPAXCAL_H_ALL \ + (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H) + +#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS \ + (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \ + OPAMP_CSR_ANAWSEL1 | \ + OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \ + OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2 ) +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup OPAMPEx_Exported_Macro OPAMPEx Exported Macro + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +/** + * @brief Enable internal analog switch SW1 to connect OPAMP3 ouput to ADC + * switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting input + * (OPAMP3 available on STM32L1 devices Cat.4 only). + * @retval None + */ +#define __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() __HAL_RI_SWITCH_COMP1_SW1_CLOSE() + +/** + * @brief Disable internal analog switch SW1 to disconnect OPAMP3 ouput from + * ADC switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting + * input. + * @retval None + */ +#define __HAL_OPAMP_OPAMP3OUT_DISCONNECT_ADC_COMP1() __HAL_RI_SWITCH_COMP1_SW1_OPEN() +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup OPAMPEx_Private_Macro OPAMPEx Private Macro + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +/** + * @brief Get the OPAMP instance in decimal number for further + * processing needs by HAL OPAMP driver functions. + * @param __HANDLE__: OPAMP handle + * @retval "0" for OPAMP1, "1" for OPAMP2, "2" for OPAMP3 + */ +#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance == OPAMP1) \ + )? \ + ((uint32_t)0) \ + : \ + ( ( ((__HANDLE__)->Instance == OPAMP2) \ + )? \ + ((uint32_t)1) \ + : \ + ((uint32_t)2) \ + ) \ + ) +#else +/** + * @brief Get the OPAMP instance in decimal number for further + * processing needs by HAL OPAMP driver functions. + * @param __HANDLE__: OPAMP handle + * @retval "0" for OPAMP1, "1" for OPAMP2 + */ +#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance == OPAMP1) \ + )? \ + ((uint32_t)0) \ + : \ + ((uint32_t)1) \ + ) +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup OPAMPEx_Exported_Functions + * @{ + */ + +/* I/O operation functions *****************************************************/ +/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended IO operation functions + * @{ + */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3); +#else +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +/** + * @} + */ +/* Peripheral Control functions ************************************************/ +/** @addtogroup OPAMPEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_OPAMP_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h new file mode 100644 index 000000000..5d373423f --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h @@ -0,0 +1,833 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pcd.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_PCD_H +#define __STM32L1xx_HAL_PCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + + /** + * @brief PCD State structures definition + */ +typedef enum +{ + PCD_READY = 0x00, + PCD_ERROR = 0x01, + PCD_BUSY = 0x02, + PCD_TIMEOUT = 0x03 +} PCD_StateTypeDef; + +typedef enum +{ + /* double buffered endpoint direction */ + PCD_EP_DBUF_OUT, + PCD_EP_DBUF_IN, + PCD_EP_DBUF_ERR, +}PCD_EP_DBUF_DIR; + +/* endpoint buffer number */ +typedef enum +{ + PCD_EP_NOBUF, + PCD_EP_BUF0, + PCD_EP_BUF1 +}PCD_EP_BUF_NUM; + +/** + * @brief PCD Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref USB_EP0_MPS */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ + + uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + +}PCD_InitTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type */ + + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + +}PCD_EPTypeDef; + +typedef USB_TypeDef PCD_TypeDef; + +/** + * @brief PCD Handle Structure definition + */ +typedef struct +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + void *pData; /*!< Pointer to upper stack Handler */ + +} PCD_HandleTypeDef; + +/** + * @} + */ + +#include "stm32l1xx_hal_pcd_ex.h" +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup USB_Exti_Line_Wakeup USB_Exti_Line_Wakeup + * @{ + */ + +#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +/** + * @} + */ + + +/** @defgroup USB_Core_Speed USB Core Speed + * @{ + */ +#define PCD_SPEED_HIGH 0 /* Not Supported */ +#define PCD_SPEED_FULL 2 +/** + * @} + */ + + /** @defgroup USB_Core_PHY USB Core PHY + * @{ + */ +#define PCD_PHY_EMBEDDED 2 +/** + * @} + */ + +/** @defgroup USB_EP0_MPS USB EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0 +#define DEP0CTL_MPS_32 1 +#define DEP0CTL_MPS_16 2 +#define DEP0CTL_MPS_8 3 + +#define PCD_EP0MPS_64 DEP0CTL_MPS_64 +#define PCD_EP0MPS_32 DEP0CTL_MPS_32 +#define PCD_EP0MPS_16 DEP0CTL_MPS_16 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +/** + * @} + */ + +/** @defgroup USB_EP_Type USB EP Type + * @{ + */ +#define PCD_EP_TYPE_CTRL 0 +#define PCD_EP_TYPE_ISOC 1 +#define PCD_EP_TYPE_BULK 2 +#define PCD_EP_TYPE_INTR 3 +/** + * @} + */ + +/** @defgroup USB_ENDP_Type USB_ENDP_Type + * @{ + */ + +#define PCD_ENDP0 ((uint8_t)0) +#define PCD_ENDP1 ((uint8_t)1) +#define PCD_ENDP2 ((uint8_t)2) +#define PCD_ENDP3 ((uint8_t)3) +#define PCD_ENDP4 ((uint8_t)4) +#define PCD_ENDP5 ((uint8_t)5) +#define PCD_ENDP6 ((uint8_t)6) +#define PCD_ENDP7 ((uint8_t)7) + +/* Endpoint Kind */ +#define PCD_SNG_BUF 0 +#define PCD_DBL_BUF 1 + +#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) + +#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP +#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP) +#define __HAL_USB_EXTI_GET_FLAG() EXTI->PR & (USB_EXTI_LINE_WAKEUP) +#define __HAL_USB_EXTI_CLEAR_FLAG() EXTI->PR = USB_EXTI_LINE_WAKEUP + +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\ + EXTI->RTSR |= USB_EXTI_LINE_WAKEUP + + +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (USB_EXTI_LINE_WAKEUP);\ + EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP) + + +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP);\ + EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\ + EXTI->RTSR |= USB_EXTI_LINE_WAKEUP;\ + EXTI->FTSR |= USB_EXTI_LINE_WAKEUP + +/** + * @} + */ + +/* Internal macros -----------------------------------------------------------*/ + +/** @defgroup PCD_Private_Macros PCD Private Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) + + + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wType: Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) + + +/** + * @brief free buffer used from the application realizing it to the line + toggles bit SW_BUF in the double buffered endpoint register + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param bDir: Direction + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ +{\ + if ((bDir) == PCD_EP_DBUF_OUT)\ + { /* OUT double buffered endpoint */\ + PCD_TX_DTOG((USBx), (bEpNum));\ + }\ + else if ((bDir) == PCD_EP_DBUF_IN)\ + { /* IN double buffered endpoint */\ + PCD_RX_DTOG((USBx), (bEpNum));\ + }\ +} + +/** + * @brief gets direction of the double buffered endpoint + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval EP_DBUF_OUT, EP_DBUF_IN, + * EP_DBUF_ERR if the endpoint counter not yet programmed. + */ +#define PCD_GET_DB_DIR(USBx, bEpNum)\ +{\ + if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ + return(PCD_EP_DBUF_OUT);\ + else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ + return(PCD_EP_DBUF_IN);\ + else\ + return(PCD_EP_DBUF_ERR);\ +} + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wState: new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wState))!= 0) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & (wState))!= 0) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + } /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wState: new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & (wState))!= 0) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & (wState))!= 0) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + } /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wStaterx: new state. + * @param wStatetx: new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ + register uint32_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ + /* toggle first bit ? */ \ + if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ + } /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) + +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) + +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ + == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ + == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) +#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ + { \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ + { \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } + +/** + * @brief Sets address in an endpoint register. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param bAddr: Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ + USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) + +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400))) + +#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ + uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ + } + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wAddr: address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param dwReg: Register + * @param wCount: Counter. + * @param wNBlocks: no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 5;\ + if(((wCount) & 0x1f) == 0)\ + { \ + (wNBlocks)--;\ + } \ + *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ + }/* PCD_CALC_BLK32 */ + +#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ + (wNBlocks) = (wCount) >> 1;\ + if(((wCount) & 0x1) != 0)\ + { \ + (wNBlocks)++;\ + } \ + *pdwReg = (uint16_t)((wNBlocks) << 10);\ + }/* PCD_CALC_BLK2 */ + +#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ + uint16_t wNBlocks;\ + if((wCount) > 62) \ + { \ + PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ + } \ + else \ + { \ + PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \ + } \ + }/* PCD_SET_EP_CNT_RX_REG */ + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ + uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ + } +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wCount: Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) + + +/** + * @brief gets counter of the tx buffer. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ + } /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @param bDir: endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + /* OUT endpoint */ \ + {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ + else if((bDir) == PCD_EP_DBUF_IN)\ + /* IN endpoint */ \ + *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ + if((bDir) == PCD_EP_DBUF_OUT)\ + {/* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \ + } \ + else if((bDir) == PCD_EP_DBUF_IN)\ + {/* IN endpoint */ \ + *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ + } /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + } /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx: USB peripheral instance register address. + * @param bEpNum: Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PCD_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ + + +/** @addtogroup PCD_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + + +/* Peripheral State functions **************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_PCD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h new file mode 100644 index 000000000..092fca04a --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h @@ -0,0 +1,89 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pcd.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_PCD_EX_H +#define __STM32L1xx_HAL_PCD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Internal macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions + * @{ + */ +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_PCD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h new file mode 100644 index 000000000..5732776b8 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_PWR_H +#define __STM32L1xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00 +#define PWR_CSR_OFFSET 0x04 +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of LPSDSR bit */ +#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) +#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) + +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) +#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) + +/* Alias word address of LPRUN bit */ +#define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) +#define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) +#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) + +/* Alias word address of FWU bit */ +#define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) +#define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) + +/* Alias word address of ULP bit */ +#define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) +#define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ + +/* --- CSR Register ---*/ +/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ +#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) +/** + * @} + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage + (Compare internally to VREFINT) */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ + +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS + +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#define PWR_FLAG_VOS PWR_CSR_VOSF +#define PWR_FLAG_REGLP PWR_CSR_REGLPF + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__: specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, + * System frequency up to 32 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, + * System frequency up to 16 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, + * System frequency up to 4.2 MHz + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm B), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. + * This bit indicates the state of the internal voltage reference, VREFINT. + * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for + * the internal regulator to be ready after the voltage range is changed. + * The VOSF bit indicates that the regulator has reached the voltage level + * defined with bits VOS of PWR_CR register. + * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run + * mode, this bit stays at 1 until the regulator is ready in main mode. + * A polling on this bit is recommended to wait for the regulator main mode. + * This bit is reset by hardware when the regulator is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2) + +#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief PVD EXTI line configuration: clear falling edge trigger and set rising edge. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \ + EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32l1xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h new file mode 100644 index 000000000..cfd35938c --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h @@ -0,0 +1,135 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_PWR_EX_H +#define __STM32L1xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + + +/** @defgroup PWR_WakeUp_Pins PWREx Wakeup Pins + * @{ + */ + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) + +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 +#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) +#else +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ + +/* Peripheral Control methods ************************************************/ +void HAL_PWREx_EnableFastWakeUp(void); +void HAL_PWREx_DisableFastWakeUp(void); +void HAL_PWREx_EnableUltraLowPower(void); +void HAL_PWREx_DisableUltraLowPower(void); +void HAL_PWREx_EnableLowPowerRunMode(void); +void HAL_PWREx_DisableLowPowerRunMode(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h new file mode 100644 index 000000000..b093b03fd --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h @@ -0,0 +1,1227 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_RCC_H +#define __STM32L1xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + + uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Division_Factor*/ +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t MSIState; /*!< The new state of the MSI. + This parameter can be a value of @ref RCC_MSI_Config */ + + uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t MSIClockRange; /*!< The MSI frequency range. + This parameter can be a value of @ref RCC_MSI_Clock_Range */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ +#define DBP_TIMEOUT_VALUE ((uint32_t)100) +#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x08 +#define RCC_CIR_OFFSET 0x0C +#define RCC_CSR_OFFSET 0x34 +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION) +#define CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4))) +/* Alias word address of MSION bit */ +#define MSION_BITNUMBER POSITION_VAL(RCC_CR_MSION) +#define CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4))) +/* Alias word address of HSEON bit */ +#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON) +#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4))) +/* Alias word address of CSSON bit */ +#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON) +#define CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4))) +/* Alias word address of PLLON bit */ +#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON) +#define CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION) +#define CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4))) + +/* Alias word address of LSEON bit */ +#define LSEON_BITNUMBER POSITION_VAL(RCC_CSR_LSEON) +#define CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4))) + +/* Alias word address of LSEON bit */ +#define LSEBYP_BITNUMBER POSITION_VAL(RCC_CSR_LSEBYP) +#define CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4))) + +/* Alias word address of RTCEN bit */ +#define RTCEN_BITNUMBER POSITION_VAL(RCC_CSR_RTCEN) +#define CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4))) + +/* Alias word address of RTCRST bit */ +#define RTCRST_BITNUMBER POSITION_VAL(RCC_CSR_RTCRST) +#define CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4))) + +/* CR register byte 2 (Bits[23:16]) base address */ +#define CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type RCC Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) +#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) + +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) +/** + * @} + */ + +/** @defgroup RCC_HSE_Config RCC HSE Config + * @{ + */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00000001) +#define RCC_HSE_BYPASS ((uint32_t)0x00000005) + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config RCC LSE Config + * @{ + */ +#define RCC_LSE_OFF ((uint32_t)0x00000000) +#define RCC_LSE_ON ((uint32_t)0x00000001) +#define RCC_LSE_BYPASS ((uint32_t)0x00000005) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config RCC HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint32_t)0x00000000) +#define RCC_HSI_ON ((uint32_t)0x00000001) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ + +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) +/** + * @} + */ + +/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range + * @{ + */ + +#define RCC_MSIRANGE_0 ((uint32_t)RCC_ICSCR_MSIRANGE_0) /*!< MSI = 65.536 KHz */ +#define RCC_MSIRANGE_1 ((uint32_t)RCC_ICSCR_MSIRANGE_1) /*!< MSI = 131.072 KHz */ +#define RCC_MSIRANGE_2 ((uint32_t)RCC_ICSCR_MSIRANGE_2) /*!< MSI = 262.144 KHz */ +#define RCC_MSIRANGE_3 ((uint32_t)RCC_ICSCR_MSIRANGE_3) /*!< MSI = 524.288 KHz */ +#define RCC_MSIRANGE_4 ((uint32_t)RCC_ICSCR_MSIRANGE_4) /*!< MSI = 1.048 MHz */ +#define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /*!< MSI = 2.097 MHz */ +#define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /*!< MSI = 4.194 MHz */ + +#define IS_RCC_MSIRANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ + ((__RANGE__) == RCC_MSIRANGE_1) || \ + ((__RANGE__) == RCC_MSIRANGE_2) || \ + ((__RANGE__) == RCC_MSIRANGE_3) || \ + ((__RANGE__) == RCC_MSIRANGE_4) || \ + ((__RANGE__) == RCC_MSIRANGE_5) || \ + ((__RANGE__) == RCC_MSIRANGE_6)) +/** + * @} + */ + +/** @defgroup RCC_LSI_Config RCC LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint32_t)0x00000000) +#define RCC_LSI_ON ((uint32_t)0x00000001) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +/** + * @} + */ + + +/** @defgroup RCC_MSI_Config RCC MSI Config + * @{ + */ +#define RCC_MSI_OFF ((uint32_t)0x00000000) +#define RCC_MSI_ON ((uint32_t)0x00000001) + +#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) + +#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_PLL_Config RCC PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint32_t)0x00000000) +#define RCC_PLL_OFF ((uint32_t)0x00000001) +#define RCC_PLL_ON ((uint32_t)0x00000002) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor + * @{ + */ + +#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 +#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 +#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 + +#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ + ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor + * @{ + */ + +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 +#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 +#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 +#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 + +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ + ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ + ((__MUL__) == RCC_PLL_MUL48)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type RCC System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) + +#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source RCC System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_MSI ((uint32_t)RCC_CFGR_SW_MSI) +#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) +#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) +#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1) +#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2) +#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4) +#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8) +#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16) +#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64) +#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128) +#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256) +#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 ((uint32_t)RCC_CFGR_PPRE1_DIV1) +#define RCC_HCLK_DIV2 ((uint32_t)RCC_CFGR_PPRE1_DIV2) +#define RCC_HCLK_DIV4 ((uint32_t)RCC_CFGR_PPRE1_DIV4) +#define RCC_HCLK_DIV8 ((uint32_t)RCC_CFGR_PPRE1_DIV8) +#define RCC_HCLK_DIV16 ((uint32_t)RCC_CFGR_PPRE1_DIV16) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +/** + * @} + */ + +/** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_CSR_RTCSEL_LSE) +#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_CSR_RTCSEL_LSI) +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)RCC_CSR_RTCSEL_HSE) +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)(RCC_CR_RTCPRE_0 | RCC_CSR_RTCSEL_HSE)) +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)(RCC_CR_RTCPRE_1 | RCC_CSR_RTCSEL_HSE)) +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)(RCC_CR_RTCPRE | RCC_CSR_RTCSEL_HSE)) +/** + * @} + */ + +/** @defgroup RCC_MCO_Index RCC MCO Index + * @{ + */ +#define RCC_MCO1 ((uint32_t)0x00000000) +#define RCC_MCO RCC_MCO1 + +#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO)) +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1) +#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4) +#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8) +#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16) + +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) +#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) +#define RCC_MCO1SOURCE_MSI ((uint32_t)RCC_CFGR_MCO_MSI) +#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) +#define RCC_MCO1SOURCE_LSE ((uint32_t)RCC_CFGR_MCO_LSE) +#define RCC_MCO1SOURCE_LSI ((uint32_t)RCC_CFGR_MCO_LSI) +#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) +#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt RCC Interrupt + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) +#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) +#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSS) +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) +/** + * @} + */ + +/** @defgroup RCC_Flag RCC Flag + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - XX : Register index + * - 01: CR register + * - 11: CSR register + * @{ + */ +#define CR_REG_INDEX ((uint8_t)1) +#define CSR_REG_INDEX ((uint8_t)3) + +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) +#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) +#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) +#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) +#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_RMVF))) +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) + +#define RCC_FLAG_MASK ((uint8_t)0x1F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) +#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) +#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) +#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) +#define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN)) + +#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) +#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) +#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) + +#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) +#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) + +#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) +#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) +#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN)) +#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) +#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) +#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) +#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) +#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) +#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) +#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) +#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) +#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) +#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) +#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) +#define __COMP_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_COMPEN)) + +#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN)) + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) +#define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN)) +#define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN)) +#define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN)) +#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) +#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) +#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) + +#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) + +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) +#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) +#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) + +#define __CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) +#define __FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST)) +#define __DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) + +#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) +#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) + +#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST)) +#define __FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST)) +#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST)) + +/** @brief Force or release APB1 peripheral reset. + */ +#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) +#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST)) + +#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST)) + +/** @brief Force or release APB2 peripheral reset. + */ +#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) +#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) + +#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) + +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN)) +#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN)) +#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN)) +#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN)) +#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN)) + +#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN)) +#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN)) +#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN)) + +#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN)) +#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN)) +#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN)) +#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN)) +#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN)) + +#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN)) +#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN)) +#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN)) +#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) +#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN)) + +#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN)) +#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) +#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN)) + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) +#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) + +#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) +#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) + +/** + * @} + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE) + +/** @brief Macros to enable or disable the External High Speed oscillator (HSE). + * @param __HSE_STATE__: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__HSE_STATE__)) + +/** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). + * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note MSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the MSI. + * @note After enabling the MSI, the application software should wait on MSIRDY + * flag to be set indicating that MSI clock is stable and can be used as + * system clock source. + * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator + * clock cycles. + */ +#define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) CR_MSION_BB = ENABLE) +#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) CR_MSION_BB = DISABLE) + +/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM))) + +/** @brief macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal MSI RC. + * @param _MSICALIBRATIONVALUE_: specifies the calibration trimming value. + * (default is RCC_MSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM))) + +/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. + * @note After restart from Reset or wakeup from STANDBY, the MSI clock is + * around 2.097 MHz. The MSI clock does not change after wake-up from + * STOP mode. + * @note The MSI clock range can be modified on the fly. + * @param _MSIRANGEVALUE_: specifies the MSI Clock range. + * This parameter must be one of the following values: + * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz + * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz + * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz + * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz + * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz + * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) + * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz + */ +#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) + + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE) +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE). + */ +#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \ + do{ \ + if ((__LSE_STATE__) == RCC_LSE_OFF) \ + { \ + *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \ + *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \ + } \ + else if ((__LSE_STATE__) == RCC_LSE_ON) \ + { \ + *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \ + *(__IO uint32_t *) CSR_LSEON_BB = ENABLE; \ + } \ + else \ + { \ + *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \ + *(__IO uint32_t *) CSR_LSEBYP_BB = ENABLE; \ + } \ + }while(0) + +/** @brief Macros to enable or disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = ENABLE) +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = DISABLE) + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) CSR_RTCRST_BB = ENABLE) +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) CSR_RTCRST_BB = DISABLE) + + +/** @brief Macro to configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). + * + * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \ + if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \ + { \ + MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \ + } \ + } while (0) + +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \ + __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ + RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ + } while (0) + +/** @brief macros to get the RTC clock source. + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE) +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE) + +/** @brief macros to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 + * @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4 + * @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6 + * @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8 + * @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 + * @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 + * @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24 + * @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32 + * @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48 + * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in + * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is + * in Range 3. + * + * @param __PLLDIV__: specifies the division factor for PLL VCO input clock + * This parameter can be one of the following values: + * @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2 + * @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3 + * @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4 + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg RCC_CFGR_SWS_MSI: MSI used as system clock + * @arg RCC_CFGR_SWS_HSI: HSI used as system clock + * @arg RCC_CFGR_SWS_HSE: HSE used as system clock + * @arg RCC_CFGR_SWS_PLL: PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** @brief macros to manage the specified RCC Flags and interrupts. + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts.). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_MSIRDY: MSI ready interrupt. + * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) + * @arg RCC_IT_CSS: Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_MSIRDY: MSI ready interrupt. + * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*) + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @note (*) This bit is available in high and medium+ density devices only. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) + + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC)) + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32l1xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CCSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h new file mode 100644 index 000000000..94d9d7c06 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h @@ -0,0 +1,573 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_RCC_EX_H +#define __STM32L1xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< specifies the RTC clock source. + This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + + uint32_t LCDClockSelection; /*!< specifies the LCD clock source. + This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +} RCC_PeriphCLKInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001) + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + +#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + +#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) + +#else /* Not LCD LINE */ + +#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +/* Alias word address of LSECSSON bit */ +#define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON) +#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4))) + +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined (STM32L151xB) || defined (STM32L152xB) || \ + defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) +#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) +#define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN)) + +#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) +#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +#define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_AESEN)) +#define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define __FSMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FSMCEN)) +#define __FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + +#define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN)) +#define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + +/** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN)) +#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) +#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) +#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) + +#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) + +#define __OPAMP_CLK_ENABLE() __COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __OPAMP_CLK_DISABLE() __COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +/** @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN)) +#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases AHB peripheral reset. + * @{ + */ +#if defined (STM32L151xB) || defined (STM32L152xB) || \ + defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) +#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) +#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) + +#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) +#define __DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +#define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) +#define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define __FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) +#define __FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + +#define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) +#define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + +/** @brief Forces or releases APB1 peripheral reset. + */ +#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) + +#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) + +#define __OPAMP_FORCE_RESET() __COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __OPAMP_RELEASE_RESET() __COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +/** @brief Forces or releases APB2 peripheral reset. + */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable + * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined (STM32L151xB) || defined (STM32L152xB) || \ + defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) +#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) +#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) + +#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) +#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) +#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) +#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) +#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + +#define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) +#define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + +/** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) + +#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + + +/** @brief Macro to configures LCD clock (LCDCLK). + * @note LCD and RTC use the same configuration + * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the + * LCD clock source. + * + * @param __LCD_CLKSOURCE__: specifies the LCD clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock + */ +#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) + +/** @brief macros to get the LCD clock source. + */ +#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); + +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h new file mode 100644 index 000000000..2d0d7a23f --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h @@ -0,0 +1,641 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rtc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_RTC_H +#define __STM32L1xx_HAL_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + +}HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ + + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ +}RTC_InitTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + +}RTC_DateTypeDef; + +/** + * @brief Time Handle Structure definition + */ +typedef struct +{ + RTC_TypeDef *Instance; /*!< Register base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +}RTC_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Timeout_Value Default Timeout Value + * @{ + */ +#define RTC_TIMEOUT_VALUE 1000 +/** + * @} + */ + +/** @defgroup RTC_Hour_Formats Hour Formats + * @{ + */ +#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) +#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) + +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ + ((FORMAT) == RTC_HOURFORMAT_24)) +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions Outpout Polarity + * @{ + */ +#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) + +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((POL) == RTC_OUTPUT_POLARITY_LOW)) +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT Alarm Output Type + * @{ + */ +#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000) + +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) + +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions Time Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions AM PM Definitions + * @{ + */ +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) + +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions DayLightSaving + * @{ + */ +#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) +#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) +#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) + +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) +/** + * @} + */ + +/** @defgroup RTC_StoreOperation_Definitions StoreOperation + * @{ + */ +#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) + +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ + ((OPERATION) == RTC_STOREOPERATION_SET)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format + * @{ + */ +#define FORMAT_BIN ((uint32_t)0x000000000) +#define FORMAT_BCD ((uint32_t)0x000000001) + +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD)) +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions Year Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions Month Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) + +#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) +#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) + +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Definitions Alarm Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions AlarmDateWeekDay Definitions + * @{ + */ +#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions Alarm Mask Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) + +#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions Alarms Definitions + * @{ + */ +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE + +#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__: RTC handle. + * @retval None + */ +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->WPR = 0xCA; \ + (__HANDLE__)->Instance->WPR = 0x53; \ + } while(0) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->WPR = 0xFF; \ + } while(0) + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) + +/** + * @brief Disable the RTC ALARMA peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) + +/** + * @brief Enable the RTC ALARMB peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) + +/** + * @brief Disable the RTC ALARMB peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Alarm's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @arg RTC_FLAG_ALRBF + * @arg RTC_FLAG_ALRAWF + * @arg RTC_FLAG_ALRBWF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Alarm's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @arg RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + + +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ + +/** + * @brief Enable the RTC Exti line. + * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +/** + * @brief Disable the RTC Exti line. + * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) + +/** + * @brief Clear the RTC Exti flags. + * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_EXTI_LINE_ALARM_EVENT + * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT + * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @retval None + */ +#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) + +/* alias define maintained for legacy */ +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG + +/** + * @} + */ + +/* Include RTC HAL Extension module */ +#include "stm32l1xx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_Exported_Functions + * @{ + */ + + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup RTC_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* RTC Time and Date functions ************************************************/ +/** @addtogroup RTC_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +/** + * @} + */ + +/* RTC Alarm functions ********************************************************/ +/** @addtogroup RTC_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup RTC_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); +/** + * @} + */ + +/* Peripheral State functions *************************************************/ +/** @addtogroup RTC_Exported_Functions_Group5 + * @{ + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ +/* Private functions **********************************************************/ +/** @addtogroup RTC_Internal_Functions + * @{ + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); +uint8_t RTC_ByteToBcd2(uint8_t Value); +uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_RTC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h new file mode 100644 index 000000000..1b93cc6ec --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h @@ -0,0 +1,973 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rtc_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of RTC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_RTC_EX_H +#define __STM32L1xx_HAL_RTC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ + +/** + * @brief RTC Tamper structure definition + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t Filter; /*!< Specifies the RTC Filter Tamper. + This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ + + uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. + This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ + + uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . + This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ + + uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . + This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +}RTC_TamperTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. + This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + + uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit + in CR register to store the operation. + This parameter can be a value of @ref RTC_StoreOperation_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. + This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint32_t Alarm; /*!< Specifies the alarm . + This parameter can be a value of @ref RTC_Alarms_Definitions */ +}RTC_AlarmTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +/** @defgroup RTC_Masks_Definitions Masks Definitions + * @{ + */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \ + RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \ + RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \ + RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ + RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \ + RTC_FLAG_RECALPF)) +#else +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \ + RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \ + RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \ + RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ + RTC_FLAG_TAMP1F | \ + RTC_FLAG_RECALPF)) + +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup RTC_Synchronous_Predivider Synchronous Predivider + * @{ + */ +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) +#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x1FFF) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_WUT ((uint32_t)0x00004000) +#define RTC_IT_ALRB ((uint32_t)0x00002000) +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define RTC_IT_TAMP2 ((uint32_t)0x00040000) +#define RTC_IT_TAMP3 ((uint32_t)0x00080000) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions Flags Definitions + * @{ + */ +#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) +#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TSF ((uint32_t)0x00000800) +#define RTC_FLAG_WUTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSF ((uint32_t)0x00000020) +#define RTC_FLAG_INITS ((uint32_t)0x00000010) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define RTC_FLAG_SHPF ((uint32_t)0x00000008) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup RTCEx_Output_selection_Definitions Output selection Definitions + * @{ + */ +#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) +#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) +#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) +#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP)) +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions + * @{ + */ +#if RTC_BKP_NUMBER > 0 +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#endif /* RTC_BKP_NUMBER > 0 */ + +#if RTC_BKP_NUMBER > 5 +#define RTC_BKP_DR5 ((uint32_t)0x00000005) +#define RTC_BKP_DR6 ((uint32_t)0x00000006) +#define RTC_BKP_DR7 ((uint32_t)0x00000007) +#define RTC_BKP_DR8 ((uint32_t)0x00000008) +#define RTC_BKP_DR9 ((uint32_t)0x00000009) +#define RTC_BKP_DR10 ((uint32_t)0x0000000A) +#define RTC_BKP_DR11 ((uint32_t)0x0000000B) +#define RTC_BKP_DR12 ((uint32_t)0x0000000C) +#define RTC_BKP_DR13 ((uint32_t)0x0000000D) +#define RTC_BKP_DR14 ((uint32_t)0x0000000E) +#define RTC_BKP_DR15 ((uint32_t)0x0000000F) +#define RTC_BKP_DR16 ((uint32_t)0x00000010) +#define RTC_BKP_DR17 ((uint32_t)0x00000011) +#define RTC_BKP_DR18 ((uint32_t)0x00000012) +#define RTC_BKP_DR19 ((uint32_t)0x00000013) +#endif /* RTC_BKP_NUMBER > 5 */ + +#if RTC_BKP_NUMBER > 20 +#define RTC_BKP_DR20 ((uint32_t)0x00000014) +#define RTC_BKP_DR21 ((uint32_t)0x00000015) +#define RTC_BKP_DR22 ((uint32_t)0x00000016) +#define RTC_BKP_DR23 ((uint32_t)0x00000017) +#define RTC_BKP_DR24 ((uint32_t)0x00000018) +#define RTC_BKP_DR25 ((uint32_t)0x00000019) +#define RTC_BKP_DR26 ((uint32_t)0x0000001A) +#define RTC_BKP_DR27 ((uint32_t)0x0000001B) +#define RTC_BKP_DR28 ((uint32_t)0x0000001C) +#define RTC_BKP_DR29 ((uint32_t)0x0000001D) +#define RTC_BKP_DR30 ((uint32_t)0x0000001E) +#define RTC_BKP_DR31 ((uint32_t)0x0000001F) +#endif /* RTC_BKP_NUMBER > 20 */ + +#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) +/** + * @} + */ + +/** @defgroup RTCEx_Time_Stamp_Edges_Definitions Time Stamp Edges Definitions + * @{ + */ +#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) + +#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ + ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions + * @{ + */ +#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E +#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define IS_TAMPER(TAMPER) (((~(RTC_TAMPER_1|RTC_TAMPER_2|RTC_TAMPER_3) & (TAMPER)) == (uint32_t)RESET) && ((TAMPER) != (uint32_t)RESET)) +#else +#define IS_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions + * @{ + */ +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE +#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) +#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) +#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** @defgroup RTCEx_Tamper_Filter_Definitions Tamper Filter Definitions + * @{ + */ +#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active level. */ + +#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ + ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions Tamper Sampling Frequencies + * @{ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ + +#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions Tamper Pin Precharge Duration + * @{ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ + +#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions TimeStampOnTamperDetection Definitions + * @{ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ + +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_Up_Definitions Tamper Pull-Up Definitions + * @{ + */ +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ + +#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) +/** + * @} + */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions Wakeup Timer Definitions + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) + +#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @defgroup RTCEx_Digital_Calibration_Definitions Digital Calibration Definitions + * @{ + */ +#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000) +#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080) + +#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \ + ((SIGN) == RTC_CALIBSIGN_NEGATIVE)) + +#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_Calib_Period_Definitions Smooth Calib Period Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 32s, else 2exp20 RTCCLK seconds */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 16s, else 2exp19 RTCCLK seconds */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 8s, else 2exp18 RTCCLK seconds */ + +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_Calib_Plus_Pulses_Definitions Smooth Calib Plus Pulses Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ + +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_Calib_Minus_Pulses_Definitions Smooth Calib Minus Pulses Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +/** + * @} + */ + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) +#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) + +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ + ((SEL) == RTC_SHIFTADD1S_SET)) +/** + * @} + */ + +/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value Substract Fraction Of Second Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +/** + * @} + */ + +/** @defgroup RTCEx_Calib_Output_Selection_Definitions Calib Output Selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) +#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) + +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ + ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) +/** + * @} + */ + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** @defgroup RTC_Alarm_Sub_Seconds_Value Alarm Sub Seconds Value + * @{ + */ +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions Alarm Sub Seconds Masks Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match + to activate alarm. */ + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) +/** + * @} + */ +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) + +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) + +/** + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) + +/** + * @brief Enable the Coarse calibration process. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE)) + +/** + * @brief Disable the Coarse calibration process. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE)) + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TAMP1 + * @arg RTC_IT_TAMP2 + * @arg RTC_IT_TAMP3 + * @retval None + */ +#else +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TAMP1 + * @retval None + */ +#endif +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC TimeStamp's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @arg RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC WakeUpTimer's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @arg RTC_FLAG_WUTWF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Get the selected RTC shift operation's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_SHPF + * @retval None + */ +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Clear the RTC Time Stamp's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Clear the RTC Wake Up timer's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + +/* RTC TimeStamp and Tamper functions *****************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); + +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); + +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +/** + * @} + */ + +/* RTC Wake-up functions ******************************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group5 + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/* Extension Control functions ************************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group7 + * @{ + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); + +HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value); +HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); +#else +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Extension RTC features functions *******************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group8 + * @{ + */ +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_RTC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h new file mode 100644 index 000000000..b3aec3dfe --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h @@ -0,0 +1,705 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_sd.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of SD HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_SD_H +#define __STM32L1xx_HAL_SD_H + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_ll_sdmmc.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SD_Exported_Types SD Exported Types + * @{ + */ + +#define SD_InitTypeDef SDIO_InitTypeDef +#define SD_TypeDef SDIO_TypeDef + +/** + * @brief SDIO Handle Structure definition + */ +typedef struct +{ + SD_TypeDef *Instance; /*!< SDIO register base address */ + + SD_InitTypeDef Init; /*!< SD required parameters */ + + HAL_LockTypeDef Lock; /*!< SD locking object */ + + uint32_t CardType; /*!< SD card type */ + + uint32_t RCA; /*!< SD relative card address */ + + uint32_t CSD[4]; /*!< SD card specific data table */ + + uint32_t CID[4]; /*!< SD card identification number table */ + + __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */ + + __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */ + + __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */ + + __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */ + + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ + + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ + +}SD_HandleTypeDef; + +/** + * @brief Card Specific Data: CSD Register + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ + +}HAL_SD_CSDTypedef; + +/** + * @brief Card Identification Data: CID Register + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_SD_CIDTypedef; + +/** + * @brief SD Card Status returned by ACMD13 + */ +typedef struct +{ + __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */ + __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */ + __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */ + __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */ + __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */ + __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */ + __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */ + __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */ + __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */ + __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */ + +}HAL_SD_CardStatusTypedef; + +/** + * @brief SD Card information structure + */ +typedef struct +{ + HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */ + HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */ + uint64_t CardCapacity; /*!< Card capacity */ + uint32_t CardBlockSize; /*!< Card block size */ + uint16_t RCA; /*!< SD relative card address */ + uint8_t CardType; /*!< SD card type */ + +}HAL_SD_CardInfoTypedef; + +/** + * @brief SD Error status enumeration Structure definition + */ +typedef enum +{ +/** + * @brief SD specific error defines + */ + SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ + SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */ + SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ + SD_DATA_TIMEOUT = (4), /*!< Data timeout */ + SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */ + SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */ + SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */ + SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */ + SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ + SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ + SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */ + SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */ + SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ + SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ + SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ + SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ + SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ + SD_CC_ERROR = (18), /*!< Internal card controller error */ + SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */ + SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ + SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ + SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ + SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */ + SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ + SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ + SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ + SD_INVALID_VOLTRANGE = (27), + SD_ADDR_OUT_OF_RANGE = (28), + SD_SWITCH_ERROR = (29), + SD_SDIO_DISABLED = (30), + SD_SDIO_FUNCTION_BUSY = (31), + SD_SDIO_FUNCTION_FAILED = (32), + SD_SDIO_UNKNOWN_FUNCTION = (33), + +/** + * @brief Standard error defines + */ + SD_INTERNAL_ERROR = (34), + SD_NOT_CONFIGURED = (35), + SD_REQUEST_PENDING = (36), + SD_REQUEST_NOT_APPLICABLE = (37), + SD_INVALID_PARAMETER = (38), + SD_UNSUPPORTED_FEATURE = (39), + SD_UNSUPPORTED_HW = (40), + SD_ERROR = (41), + SD_OK = (0) + +}HAL_SD_ErrorTypedef; + +/** + * @brief SD Transfer state enumeration structure + */ +typedef enum +{ + SD_TRANSFER_OK = 0, /*!< Transfer success */ + SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */ + SD_TRANSFER_ERROR = 2 /*!< Transfer failed */ + +}HAL_SD_TransferStateTypedef; + +/** + * @brief SD Card State enumeration structure + */ +typedef enum +{ + SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */ + SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */ + SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */ + SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */ + SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */ + SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */ + SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */ + SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */ + SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */ + +}HAL_SD_CardStateTypedef; + +/** + * @brief SD Operation enumeration structure + */ +typedef enum +{ + SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */ + SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */ + SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */ + SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */ + +}HAL_SD_OperationTypedef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SD_Exported_Constants SD Exported Constants + * @{ + */ + +/** + * @brief SD Commands Index + */ +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ +#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ +#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ +#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ +#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ +#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) +#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ +#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ +#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ +#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ +#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ +#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ +#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ +#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ +#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ +#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define SD_CMD_NO_CMD ((uint8_t)64) + +/** + * @brief Following commands are SD Card Specific commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SD_CMD_APP_CMD should be sent before sending these commands. + */ +#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */ +#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */ +#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */ +#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */ +#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */ + +/** + * @brief Supported SD Memory Cards + */ +#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SD_Exported_macros SD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the SD device. + * @retval None + */ +#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE() + +/** + * @brief Disable the SD device. + * @retval None + */ +#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE() + +/** + * @brief Enable the SDIO DMA transfer. + * @retval None + */ +#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE() + +/** + * @brief Disable the SDIO DMA transfer. + * @retval None + */ +#define __HAL_SD_SDIO_DMA_DISABLE() __SDIO_DMA_DISABLE() + +/** + * @brief Enable the SD device interrupt. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SD device interrupt. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SD flag is set or not. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SD FLAG (SET or RESET). + */ +#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SD's pending flags. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SD interrupt has occurred or not. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SD IT (SET or RESET). + */ +#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__) + +/** + * @brief Clear the SD's interrupt pending bits. + * @param __HANDLE__ : SD Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SD_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions **********************************/ +/** @addtogroup SD_Exported_Functions_Group1 + * @{ + */ +HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo); +HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); +void HAL_SD_MspInit(SD_HandleTypeDef *hsd); +void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup SD_Exported_Functions_Group2 + * @{ + */ +/* Blocking mode: Polling */ +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr); + +/* Non-Blocking mode: Interrupt */ +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); + +/* Callback in non blocking modes (DMA) */ +void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma); +void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma); +void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd); + +/* Non-Blocking mode: DMA */ +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); +HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); +HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup SD_Exported_Functions_Group3 + * @{ + */ +HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo); +HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode); +HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd); +HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd); +/** + * @} + */ + +/* Peripheral State functions **************************************************/ +/** @addtogroup SD_Exported_Functions_Group4 + * @{ + */ +HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus); +HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#endif /* __STM32L1xx_HAL_SD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h new file mode 100644 index 000000000..f24169fbe --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h @@ -0,0 +1,587 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_smartcard.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains all the functions prototypes for the SMARTCARD + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_SMARTCARD_H +#define __STM32L1xx_HAL_SMARTCARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types + * @{ + */ + + +/** + * @brief SMARTCARD Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (hsc->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref SMARTCARD_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref SMARTCARD_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref SMARTCARD_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits).*/ + + uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref SMARTCARD_Mode */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SMARTCARD_Clock_Phase */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref SMARTCARD_Last_Bit */ + + uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler + This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ + + uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time + This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ + + uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state + This parameter can be a value of @ref SMARTCARD_NACK_State */ +}SMARTCARD_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ + HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ +}HAL_SMARTCARD_StateTypeDef; + +/** + * @brief HAL SMARTCARD Error Code structure definition + */ +typedef enum +{ + HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ + HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ + HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ + HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ + HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */ +}HAL_SMARTCARD_ErrorTypeDef; + +/** + * @brief SMARTCARD handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /* USART registers base address */ + + SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */ + + uint16_t TxXferSize; /* SmartCard Tx Transfer size */ + + uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */ + + uint16_t RxXferSize; /* SmartCard Rx Transfer size */ + + uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */ + + __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SmartCard Error code */ +}SMARTCARD_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants + * @{ + */ + +/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length + * @{ + */ +#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000) +#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) +/** + * @} + */ + +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits + * @{ + */ +#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000) +#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) +#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) +#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \ + ((STOPBITS) == SMARTCARD_STOPBITS_1_5)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Parity SMARTCARD Parity + * @{ + */ +#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000) +#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ + ((PARITY) == SMARTCARD_PARITY_ODD)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Mode SMARTCARD Mode + * @{ + */ +#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) +#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) +#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity + * @{ + */ +#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) +#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) +#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase + * @{ + */ +#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) +#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) +#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit + * @{ + */ +#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) +#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ + ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) +/** + * @} + */ + +/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State + * @{ + */ +#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK) +#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000) +#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \ + ((NACK) == SMARTCARD_NACK_DISABLED)) +/** + * @} + */ + +/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests + * @{ + */ + +#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) +#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) + +/** + * @} + */ + +/** @defgroup SMARTCARD_Flags SMARTCARD Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ + +#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC) +#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE) +#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE) +#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask in the XX register + * - Y : Interrupt source register (4 bits) + * - 01: CR1 register + * - 10: CR3 register + + * + * @{ + */ +#define SMARTCARD_IT_PE ((uint32_t)0x10000100) +#define SMARTCARD_IT_TXE ((uint32_t)0x10000080) +#define SMARTCARD_IT_TC ((uint32_t)0x10000040) +#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020) +#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010) +#define SMARTCARD_IT_ERR ((uint32_t)0x20000001) + +/** + * @} + */ + +/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask + * @{ + */ +#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros + * @{ + */ + + +/** @brief Reset SMARTCARD handle state + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) + +/** @brief Flushs the Smartcard DR register + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + */ +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified Smartcard flag is set or not. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag + * @arg SMARTCARD_FLAG_TC: Transmission Complete flag + * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag + * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag + * @arg SMARTCARD_FLAG_ORE: OverRun Error flag + * @arg SMARTCARD_FLAG_NE: Noise Error flag + * @arg SMARTCARD_FLAG_FE: Framing Error flag + * @arg SMARTCARD_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified Smartcard pending flags. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg SMARTCARD_FLAG_TC: Transmission Complete flag. + * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun + * error) flags are cleared by software sequence: a read operation to + * USART_SR register followed by a read operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clear the SMARTCARD PE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the SMARTCARD FE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the SMARTCARD NE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the SMARTCARD ORE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the SMARTCARD IDLE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enables the specified SmartCard interrupt. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * This parameter can be one of the following values: + * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt + * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt + * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + */ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK))) + +/** @brief Disables the specified SmartCard interrupts. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. + * This parameter can be one of the following values: + * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt + * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt + * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + */ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK))) + +/** @brief Checks whether the specified SmartCard interrupt has occurred or not. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @param __IT__: specifies the SMARTCARD interrupt source to check. + * This parameter can be one of the following values: + * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt + * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt + * @arg SMARTCARD_IT_ERR: Error interrupt + * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) + +/** @brief Enable the USART associated to the SMARTCARD Handle + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) + +/** @brief Disable the USART associated to the SMARTCARD Handle + * @param __HANDLE__: specifies the SMARTCARD Handle. + * This parameter can be USARTx with x: 1, 2 or 3. + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) + + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + +/** @brief Macros to enable or disable the SmartCard DMA request. + * @param __HANDLE__: specifies the SmartCard Handle. + * @param __REQUEST__: specifies the SmartCard DMA request. + * This parameter can be one of the following values: + * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request + * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request + */ +#define SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) +#define SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) + +#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) +#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100) +#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) +#define SMARTCARD_BRR(__PCLK__, __BAUD__) ((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) + +/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the + * maximum clock on L1 (i.e. 32 MHz) divided by the oversampling used + * on the SMARTCARD (i.e. 16). No overSampling by 16 on Smartcard. + * @param __BAUDRATE__: Baud rate set by the configuration function. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions + * @{ + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc); + +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc); + +/** + * @} + */ + +/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions functions *****************************/ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_SMARTCARD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h new file mode 100644 index 000000000..419e3055a --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h @@ -0,0 +1,556 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_spi.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_SPI_H +#define __STM32L1xx_HAL_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint32_t Direction; /*!< Specifies the SPI Directional mode state. + This parameter can be a value of @ref SPI_Direction_mode */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + +}SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ + HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ + +}HAL_SPI_StateTypeDef; + +/** + * @brief HAL SPI Error Code structure definition + */ +typedef enum +{ + HAL_SPI_ERROR_NONE = 0x00, /*!< No error */ + HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */ + HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */ + HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */ + HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */ + HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */ + HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */ + +}HAL_SPI_ErrorTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /* SPI registers base address */ + + SPI_InitTypeDef Init; /* SPI communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /* SPI Tx transfer size */ + + uint16_t TxXferCount; /* SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /* SPI Rx transfer size */ + + uint16_t RxXferCount; /* SPI Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */ + + void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */ + + HAL_LockTypeDef Lock; /* SPI locking object */ + + __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ + + __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */ + +}SPI_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_mode SPI mode + * @{ + */ +#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) + +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) +/** + * @} + */ + +/** @defgroup SPI_Direction_mode SPI Direction mode + * @{ + */ +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE + +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((MODE) == SPI_DIRECTION_1LINE)) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_1LINE)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +/** + * @} + */ + +/** @defgroup SPI_data_size SPI data size + * @{ + */ +#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN + +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) +/** + * @} + */ + +/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flag_definition SPI Flag definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE +#define SPI_FLAG_TXE SPI_SR_TXE +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_FLAG_OVR SPI_SR_OVR +#define SPI_FLAG_BSY SPI_SR_BSY +#define SPI_FLAG_FRE SPI_SR_FRE + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + +/** @brief Enable or disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check if the specified SPI interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE);}while(0) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ + (__HANDLE__)->Instance->SR;}while(0) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR) + +/** @brief Enables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) +/** + * @} + */ + + +/* Private macro ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Sets the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Sets the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Resets the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) +/** + * @} + */ + +/* Include SPI HAL Extension module */ +#include "stm32l1xx_hal_spi_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + + +/* Peripheral State and Control functions **************************************/ +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi_ex.h new file mode 100644 index 000000000..6cb3a398e --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi_ex.h @@ -0,0 +1,106 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_spi_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_SPI_EX_H +#define __STM32L1xx_HAL_SPI_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** @defgroup SPI_TI_mode SPI TI mode + * @{ + */ +#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) +#define SPI_TIMODE_ENABLED SPI_CR2_FRF + +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ + ((MODE) == SPI_TIMODE_ENABLED)) +#else +/** @defgroup SPI_TI_mode SPI TI mode disable + * @brief SPI TI Mode not supported for Category 1 and 2 + * @{ + */ +#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) + +#define IS_SPI_TIMODE(MODE) ((MODE) == SPI_TIMODE_DISABLED) + +#endif +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h new file mode 100644 index 000000000..9b25f1328 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h @@ -0,0 +1,202 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_sram.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of SRAM HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_SRAM_H +#define __STM32L1xx_HAL_SRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_ll_fsmc.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SRAM + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_typedef SRAM Exported typedef + * @{ + */ + +/** + * @brief HAL SRAM State structures definition + */ +typedef enum +{ + HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ + +}HAL_SRAM_StateTypeDef; + +/** + * @brief SRAM handle Structure definition + */ +typedef struct +{ + FSMC_NORSRAM_TYPEDEF *Instance; /*!< Register base address */ + + FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended; /*!< Extended mode register base address */ + + FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< SRAM locking object */ + + __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ + + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ + +}SRAM_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_macro SRAM Exported macro + * @{ + */ + +/** @brief Reset SRAM handle state + * @param __HANDLE__: SRAM handle + * @retval None + */ +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SRAM_Exported_Functions + * @{ + */ + +/** @addtogroup SRAM_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); + +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group2 + * @{ + */ + +/* I/O operation functions *****************************************************/ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group3 + * @{ + */ + +/* SRAM Control functions ******************************************************/ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group4 + * @{ + */ + +/* SRAM State functions *********************************************************/ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_SRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h new file mode 100644 index 000000000..59f5adba0 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h @@ -0,0 +1,1508 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_tim.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_TIM_H +#define __STM32L1xx_HAL_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" +#include "stm32l1xx_hal_dma.h" +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClockConfigTypeDef; + +/** + * @brief Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter can be a value of @ref TIM_ClearInput_Prescaler */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct { + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +}TIM_SlaveConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ +}HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ +}HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +typedef struct +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ +}TIM_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM_Counter_Mode + * @{ + */ +#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ + ((MODE) == TIM_COUNTERMODE_DOWN) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM_ClockDivision + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) +#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) + +#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes + * @{ + */ +#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) +#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) + +#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ + ((MODE) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ + ((MODE) == TIM_OCMODE_ACTIVE) || \ + ((MODE) == TIM_OCMODE_INACTIVE) || \ + ((MODE) == TIM_OCMODE_TOGGLE) || \ + ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) + +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTSTATE_ENABLE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State + * @{ + */ +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) + +#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ + ((STATE) == TIM_OCFAST_ENABLE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCPOLARITY_LOW)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State + * @{ + */ +#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) +#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ + ((STATE) == TIM_OCIDLESTATE_RESET)) +/** + * @} + */ + +/** @defgroup TIM_Channel TIM_Channel + * @{ + */ +#define TIM_CHANNEL_1 ((uint32_t)0x0000) +#define TIM_CHANNEL_2 ((uint32_t)0x0004) +#define TIM_CHANNEL_3 ((uint32_t)0x0008) +#define TIM_CHANNEL_4 ((uint32_t)0x000C) +#define TIM_CHANNEL_ALL ((uint32_t)0x0018) + +#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_ALL)) + +#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ + ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode + * @{ + */ +#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) +#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ + ((MODE) == TIM_OPMODE_REPETITIVE)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) +#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ + ((MODE) == TIM_ENCODERMODE_TI2) || \ + ((MODE) == TIM_ENCODERMODE_TI12)) +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition + * @{ + */ +#define TIM_IT_UPDATE (TIM_DIER_UIE) +#define TIM_IT_CC1 (TIM_DIER_CC1IE) +#define TIM_IT_CC2 (TIM_DIER_CC2IE) +#define TIM_IT_CC3 (TIM_DIER_CC3IE) +#define TIM_IT_CC4 (TIM_DIER_CC4IE) +#define TIM_IT_TRIGGER (TIM_DIER_TIE) + +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM_DMA_sources + * @{ + */ +#define TIM_DMA_UPDATE (TIM_DIER_UDE) +#define TIM_DMA_CC1 (TIM_DIER_CC1DE) +#define TIM_DMA_CC2 (TIM_DIER_CC2DE) +#define TIM_DMA_CC3 (TIM_DIER_CC3DE) +#define TIM_DMA_CC4 (TIM_DIER_CC4DE) +#define TIM_DMA_TRIGGER (TIM_DIER_TDE) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM_Event_Source + * @{ + */ +#define TIM_EventSource_Update TIM_EGR_UG +#define TIM_EventSource_CC1 TIM_EGR_CC1G +#define TIM_EventSource_CC2 TIM_EGR_CC2G +#define TIM_EventSource_CC3 TIM_EGR_CC3G +#define TIM_EventSource_CC4 TIM_EGR_CC4G +#define TIM_EventSource_Trigger TIM_EGR_TG + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM_Flag_definition + * @{ + */ +#define TIM_FLAG_UPDATE (TIM_SR_UIF) +#define TIM_FLAG_CC1 (TIM_SR_CC1IF) +#define TIM_FLAG_CC2 (TIM_SR_CC2IF) +#define TIM_FLAG_CC3 (TIM_SR_CC3IF) +#define TIM_FLAG_CC4 (TIM_SR_CC4IF) +#define TIM_FLAG_TRIGGER (TIM_SR_TIF) +#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) +#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) +#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) +#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) + +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM_Clock_Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) + +#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ + +#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ + +#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Filter TIM_Clock_Filter + * @{ + */ +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) +#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) +#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) + +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ + + +#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ + +#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter + * @{ + */ +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ +#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) +#define TIM_OSSR_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ + ((STATE) == TIM_OSSR_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ +#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) +#define TIM_OSSI_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ + ((STATE) == TIM_OSSI_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level TIM_Lock_level + * @{ + */ +#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) +#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) +#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) +#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM_LOCKLEVEL_1) || \ + ((LEVEL) == TIM_LOCKLEVEL_2) || \ + ((LEVEL) == TIM_LOCKLEVEL_3)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset + * @{ + */ +#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) +#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection + * @{ + */ +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ + ((SOURCE) == TIM_TRGO_ENABLE) || \ + ((SOURCE) == TIM_TRGO_UPDATE) || \ + ((SOURCE) == TIM_TRGO_OC1) || \ + ((SOURCE) == TIM_TRGO_OC1REF) || \ + ((SOURCE) == TIM_TRGO_OC2REF) || \ + ((SOURCE) == TIM_TRGO_OC3REF) || \ + ((SOURCE) == TIM_TRGO_OC4REF)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM_Slave_Mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) +#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) +#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) +#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ + ((MODE) == TIM_SLAVEMODE_GATED) || \ + ((MODE) == TIM_SLAVEMODE_RESET) || \ + ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) +#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection + * @{ + */ +#define TIM_TS_ITR0 ((uint32_t)0x0000) +#define TIM_TS_ITR1 ((uint32_t)0x0010) +#define TIM_TS_ITR2 ((uint32_t)0x0020) +#define TIM_TS_ITR3 ((uint32_t)0x0030) +#define TIM_TS_TI1F_ED ((uint32_t)0x0040) +#define TIM_TS_TI1FP1 ((uint32_t)0x0050) +#define TIM_TS_TI2FP2 ((uint32_t)0x0060) +#define TIM_TS_ETRF ((uint32_t)0x0070) +#define TIM_TS_NONE ((uint32_t)0xFFFF) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_NONE)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ + +#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ + +#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter + * @{ + */ +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM_TI1_Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) + +#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ + ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address + * @{ + */ +#define TIM_DMABase_CR1 (0x00000000) +#define TIM_DMABase_CR2 (0x00000001) +#define TIM_DMABase_SMCR (0x00000002) +#define TIM_DMABase_DIER (0x00000003) +#define TIM_DMABase_SR (0x00000004) +#define TIM_DMABase_EGR (0x00000005) +#define TIM_DMABase_CCMR1 (0x00000006) +#define TIM_DMABase_CCMR2 (0x00000007) +#define TIM_DMABase_CCER (0x00000008) +#define TIM_DMABase_CNT (0x00000009) +#define TIM_DMABase_PSC (0x0000000A) +#define TIM_DMABase_ARR (0x0000000B) +#define TIM_DMABase_CCR1 (0x0000000D) +#define TIM_DMABase_CCR2 (0x0000000E) +#define TIM_DMABase_CCR3 (0x0000000F) +#define TIM_DMABase_CCR4 (0x00000010) +#define TIM_DMABase_DCR (0x00000012) +#define TIM_DMABase_OR (0x00000013) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length + * @{ + */ +#define TIM_DMABurstLength_1Transfer (0x00000000) +#define TIM_DMABurstLength_2Transfers (0x00000100) +#define TIM_DMABurstLength_3Transfers (0x00000200) +#define TIM_DMABurstLength_4Transfers (0x00000300) +#define TIM_DMABurstLength_5Transfers (0x00000400) +#define TIM_DMABurstLength_6Transfers (0x00000500) +#define TIM_DMABurstLength_7Transfers (0x00000600) +#define TIM_DMABurstLength_8Transfers (0x00000700) +#define TIM_DMABurstLength_9Transfers (0x00000800) +#define TIM_DMABurstLength_10Transfers (0x00000900) +#define TIM_DMABurstLength_11Transfers (0x00000A00) +#define TIM_DMABurstLength_12Transfers (0x00000B00) +#define TIM_DMABurstLength_13Transfers (0x00000C00) +#define TIM_DMABurstLength_14Transfers (0x00000D00) +#define TIM_DMABurstLength_15Transfers (0x00000E00) +#define TIM_DMABurstLength_16Transfers (0x00000F00) +#define TIM_DMABurstLength_17Transfers (0x00001000) +#define TIM_DMABurstLength_18Transfers (0x00001100) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value + * @{ + */ +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup DMA_Handle_index DMA_Handle_index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State Channel_CC_State + * @{ + */ +#define TIM_CCx_ENABLE ((uint32_t)0x0001) +#define TIM_CCx_DISABLE ((uint32_t)0x0000) +/** + * @} + */ + +/** + * @} + */ + +/* Private Constants -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM_Private_Constants + * @{ + */ + +/* The counter of a timer instance is disabled only if all the CCx + channels have been disabled */ +#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +/** + * @} + */ + + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } while(0) + +/** + * @brief Enable the specified TIM interrupt. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__: TIM handle + * @param __DMA__: specifies the DMA Channel to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** + * @brief Disable the specified TIM interrupt. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__: TIM handle + * @param __DMA__: specifies the DMA Channel to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** + * @brief Get the TIM Channel pending flags. + * @param __HANDLE__: TIM handle + * @param __FLAG__: Get the specified flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the TIM Channel pending flags. + * @param __HANDLE__: TIM handle + * @param __FLAG__: specifies the flag to clear. + * @retval None + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Checks whether the specified TIM interrupt has occurred or not. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** @brief TIM counter direction + * @param __HANDLE__: TIM handle + */ +#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** @brief Set TIM prescaler + * @param __HANDLE__: TIM handle + * @param __PRESC__: specifies the prescaler value. + * @retval None + */ +#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** @brief Set TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @param __ICPSC__: specifies the prescaler value. + * @retval None + */ +#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + +/** @brief Reset TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @retval None + */ +#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + +/** + * @brief Sets the TIM Capture Compare Register value on runtime without + * calling another time ConfigChannel function. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__: specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) + +/** + * @brief Gets the TIM Capture Compare Register value on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval None + */ +#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) + +/** + * @brief Sets the TIM Counter Register value on runtime. + * @param __HANDLE__: TIM handle. + * @param __COUNTER__: specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Gets the TIM Counter Register value on runtime. + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetCounter(__HANDLE__) \ + ((__HANDLE__)->Instance->CNT) + +/** + * @brief Sets the TIM Autoreload Register value on runtime without calling + * another time any Init function. + * @param __HANDLE__: TIM handle. + * @param __AUTORELOAD__: specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Gets the TIM Autoreload Register value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetAutoreload(__HANDLE__) \ + ((__HANDLE__)->Instance->ARR) + +/** + * @brief Sets the TIM Clock Division value on runtime without calling + * another time any Init function. + * @param __HANDLE__: TIM handle. + * @param __CKD__: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1 + * @arg TIM_CLOCKDIVISION_DIV2 + * @arg TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Gets the TIM Clock Division value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetClockDivision(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Sets the TIM Input Capture prescaler on runtime without calling + * another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ + __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Gets the TIM Input Capture prescaler on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval None + */ +#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + +/** + * @} + */ + +/* Include TIM HAL Extension module */ +#include "stm32l1xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 + * @{ + */ +/* Timer PWM functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions ***********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions ***************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 + * @{ + */ +/* Timer Encoder functions *****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 + * @{ + */ +/* Interrupt Handler functions **********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group9 + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group10 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h~RF15e1dc3.TMP b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h~RF15e1dc3.TMP new file mode 100644 index 000000000..9d22464be --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h~RF15e1dc3.TMP @@ -0,0 +1,1508 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_tim.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_TIM_H +#define __STM32L1xx_HAL_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClockConfigTypeDef; + +/** + * @brief Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter can be a value of @ref TIM_ClearInput_Prescaler */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +}TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct { + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +}TIM_SlaveConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ +}HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ +}HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +typedef struct +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ +}TIM_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM_Counter_Mode + * @{ + */ +#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ + ((MODE) == TIM_COUNTERMODE_DOWN) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM_ClockDivision + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) +#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) + +#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes + * @{ + */ +#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) +#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) +#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) + +#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ + ((MODE) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ + ((MODE) == TIM_OCMODE_ACTIVE) || \ + ((MODE) == TIM_OCMODE_INACTIVE) || \ + ((MODE) == TIM_OCMODE_TOGGLE) || \ + ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) + +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTSTATE_ENABLE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State + * @{ + */ +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) + +#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ + ((STATE) == TIM_OCFAST_ENABLE)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCPOLARITY_LOW)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State + * @{ + */ +#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) +#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ + ((STATE) == TIM_OCIDLESTATE_RESET)) +/** + * @} + */ + +/** @defgroup TIM_Channel TIM_Channel + * @{ + */ +#define TIM_CHANNEL_1 ((uint32_t)0x0000) +#define TIM_CHANNEL_2 ((uint32_t)0x0004) +#define TIM_CHANNEL_3 ((uint32_t)0x0008) +#define TIM_CHANNEL_4 ((uint32_t)0x000C) +#define TIM_CHANNEL_ALL ((uint32_t)0x0018) + +#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_ALL)) + +#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ + ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode + * @{ + */ +#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) +#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ + ((MODE) == TIM_OPMODE_REPETITIVE)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) +#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ + ((MODE) == TIM_ENCODERMODE_TI2) || \ + ((MODE) == TIM_ENCODERMODE_TI12)) +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition + * @{ + */ +#define TIM_IT_UPDATE (TIM_DIER_UIE) +#define TIM_IT_CC1 (TIM_DIER_CC1IE) +#define TIM_IT_CC2 (TIM_DIER_CC2IE) +#define TIM_IT_CC3 (TIM_DIER_CC3IE) +#define TIM_IT_CC4 (TIM_DIER_CC4IE) +#define TIM_IT_TRIGGER (TIM_DIER_TIE) + +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM_DMA_sources + * @{ + */ +#define TIM_DMA_UPDATE (TIM_DIER_UDE) +#define TIM_DMA_CC1 (TIM_DIER_CC1DE) +#define TIM_DMA_CC2 (TIM_DIER_CC2DE) +#define TIM_DMA_CC3 (TIM_DIER_CC3DE) +#define TIM_DMA_CC4 (TIM_DIER_CC4DE) +#define TIM_DMA_TRIGGER (TIM_DIER_TDE) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM_Event_Source + * @{ + */ +#define TIM_EventSource_Update TIM_EGR_UG +#define TIM_EventSource_CC1 TIM_EGR_CC1G +#define TIM_EventSource_CC2 TIM_EGR_CC2G +#define TIM_EventSource_CC3 TIM_EGR_CC3G +#define TIM_EventSource_CC4 TIM_EGR_CC4G +#define TIM_EventSource_Trigger TIM_EGR_TG + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM_Flag_definition + * @{ + */ +#define TIM_FLAG_UPDATE (TIM_SR_UIF) +#define TIM_FLAG_CC1 (TIM_SR_CC1IF) +#define TIM_FLAG_CC2 (TIM_SR_CC2IF) +#define TIM_FLAG_CC3 (TIM_SR_CC3IF) +#define TIM_FLAG_CC4 (TIM_SR_CC4IF) +#define TIM_FLAG_TRIGGER (TIM_SR_TIF) +#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) +#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) +#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) +#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) + +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM_Clock_Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) + +#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ + +#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ + +#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Filter TIM_Clock_Filter + * @{ + */ +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) +#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) +#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) + +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ + + +#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ + +#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter + * @{ + */ +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ +#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) +#define TIM_OSSR_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ + ((STATE) == TIM_OSSR_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ +#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) +#define TIM_OSSI_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ + ((STATE) == TIM_OSSI_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level TIM_Lock_level + * @{ + */ +#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) +#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) +#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) +#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM_LOCKLEVEL_1) || \ + ((LEVEL) == TIM_LOCKLEVEL_2) || \ + ((LEVEL) == TIM_LOCKLEVEL_3)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset + * @{ + */ +#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) +#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection + * @{ + */ +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ + ((SOURCE) == TIM_TRGO_ENABLE) || \ + ((SOURCE) == TIM_TRGO_UPDATE) || \ + ((SOURCE) == TIM_TRGO_OC1) || \ + ((SOURCE) == TIM_TRGO_OC1REF) || \ + ((SOURCE) == TIM_TRGO_OC2REF) || \ + ((SOURCE) == TIM_TRGO_OC3REF) || \ + ((SOURCE) == TIM_TRGO_OC4REF)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM_Slave_Mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) +#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) +#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) +#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ + ((MODE) == TIM_SLAVEMODE_GATED) || \ + ((MODE) == TIM_SLAVEMODE_RESET) || \ + ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) +#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection + * @{ + */ +#define TIM_TS_ITR0 ((uint32_t)0x0000) +#define TIM_TS_ITR1 ((uint32_t)0x0010) +#define TIM_TS_ITR2 ((uint32_t)0x0020) +#define TIM_TS_ITR3 ((uint32_t)0x0030) +#define TIM_TS_TI1F_ED ((uint32_t)0x0040) +#define TIM_TS_TI1FP1 ((uint32_t)0x0050) +#define TIM_TS_TI2FP2 ((uint32_t)0x0060) +#define TIM_TS_ETRF ((uint32_t)0x0070) +#define TIM_TS_NONE ((uint32_t)0xFFFF) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_NONE)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ + +#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ + +#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter + * @{ + */ +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM_TI1_Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) + +#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ + ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address + * @{ + */ +#define TIM_DMABase_CR1 (0x00000000) +#define TIM_DMABase_CR2 (0x00000001) +#define TIM_DMABase_SMCR (0x00000002) +#define TIM_DMABase_DIER (0x00000003) +#define TIM_DMABase_SR (0x00000004) +#define TIM_DMABase_EGR (0x00000005) +#define TIM_DMABase_CCMR1 (0x00000006) +#define TIM_DMABase_CCMR2 (0x00000007) +#define TIM_DMABase_CCER (0x00000008) +#define TIM_DMABase_CNT (0x00000009) +#define TIM_DMABase_PSC (0x0000000A) +#define TIM_DMABase_ARR (0x0000000B) +#define TIM_DMABase_CCR1 (0x0000000D) +#define TIM_DMABase_CCR2 (0x0000000E) +#define TIM_DMABase_CCR3 (0x0000000F) +#define TIM_DMABase_CCR4 (0x00000010) +#define TIM_DMABase_DCR (0x00000012) +#define TIM_DMABase_OR (0x00000013) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length + * @{ + */ +#define TIM_DMABurstLength_1Transfer (0x00000000) +#define TIM_DMABurstLength_2Transfers (0x00000100) +#define TIM_DMABurstLength_3Transfers (0x00000200) +#define TIM_DMABurstLength_4Transfers (0x00000300) +#define TIM_DMABurstLength_5Transfers (0x00000400) +#define TIM_DMABurstLength_6Transfers (0x00000500) +#define TIM_DMABurstLength_7Transfers (0x00000600) +#define TIM_DMABurstLength_8Transfers (0x00000700) +#define TIM_DMABurstLength_9Transfers (0x00000800) +#define TIM_DMABurstLength_10Transfers (0x00000900) +#define TIM_DMABurstLength_11Transfers (0x00000A00) +#define TIM_DMABurstLength_12Transfers (0x00000B00) +#define TIM_DMABurstLength_13Transfers (0x00000C00) +#define TIM_DMABurstLength_14Transfers (0x00000D00) +#define TIM_DMABurstLength_15Transfers (0x00000E00) +#define TIM_DMABurstLength_16Transfers (0x00000F00) +#define TIM_DMABurstLength_17Transfers (0x00001000) +#define TIM_DMABurstLength_18Transfers (0x00001100) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value + * @{ + */ +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup DMA_Handle_index DMA_Handle_index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State Channel_CC_State + * @{ + */ +#define TIM_CCx_ENABLE ((uint32_t)0x0001) +#define TIM_CCx_DISABLE ((uint32_t)0x0000) +/** + * @} + */ + +/** + * @} + */ + +/* Private Constants -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM_Private_Constants + * @{ + */ + +/* The counter of a timer instance is disabled only if all the CCx + channels have been disabled */ +#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +/** + * @} + */ + + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__: TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } while(0) + +/** + * @brief Enable the specified TIM interrupt. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__: TIM handle + * @param __DMA__: specifies the DMA Channel to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** + * @brief Disable the specified TIM interrupt. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__: TIM handle + * @param __DMA__: specifies the DMA Channel to be enabled or disabled. + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** + * @brief Get the TIM Channel pending flags. + * @param __HANDLE__: TIM handle + * @param __FLAG__: Get the specified flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the TIM Channel pending flags. + * @param __HANDLE__: TIM handle + * @param __FLAG__: specifies the flag to clear. + * @retval None + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Checks whether the specified TIM interrupt has occurred or not. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** @brief TIM counter direction + * @param __HANDLE__: TIM handle + */ +#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** @brief Set TIM prescaler + * @param __HANDLE__: TIM handle + * @param __PRESC__: specifies the prescaler value. + * @retval None + */ +#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** @brief Set TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @param __ICPSC__: specifies the prescaler value. + * @retval None + */ +#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + +/** @brief Reset TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @retval None + */ +#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + +/** + * @brief Sets the TIM Capture Compare Register value on runtime without + * calling another time ConfigChannel function. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__: specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) + +/** + * @brief Gets the TIM Capture Compare Register value on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval None + */ +#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) + +/** + * @brief Sets the TIM Counter Register value on runtime. + * @param __HANDLE__: TIM handle. + * @param __COUNTER__: specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Gets the TIM Counter Register value on runtime. + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetCounter(__HANDLE__) \ + ((__HANDLE__)->Instance->CNT) + +/** + * @brief Sets the TIM Autoreload Register value on runtime without calling + * another time any Init function. + * @param __HANDLE__: TIM handle. + * @param __AUTORELOAD__: specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Gets the TIM Autoreload Register value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetAutoreload(__HANDLE__) \ + ((__HANDLE__)->Instance->ARR) + +/** + * @brief Sets the TIM Clock Division value on runtime without calling + * another time any Init function. + * @param __HANDLE__: TIM handle. + * @param __CKD__: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1 + * @arg TIM_CLOCKDIVISION_DIV2 + * @arg TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Gets the TIM Clock Division value on runtime + * @param __HANDLE__: TIM handle. + * @retval None + */ +#define __HAL_TIM_GetClockDivision(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Sets the TIM Input Capture prescaler on runtime without calling + * another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ + __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Gets the TIM Input Capture prescaler on runtime + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__ : TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval None + */ +#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + +/** + * @} + */ + +/* Include TIM HAL Extension module */ +#include "stm32l1xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 + * @{ + */ +/* Timer PWM functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions ***********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions ***************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 + * @{ + */ +/* Timer Encoder functions *****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); + /* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 + * @{ + */ +/* Interrupt Handler functions **********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group9 + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group10 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h new file mode 100644 index 000000000..437f12be6 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_tim_ex.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of TIM HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_TIM_EX_H +#define __STM32L1xx_HAL_TIM_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIMEx Exported Types + * @{ + */ + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct { + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode */ +}TIM_MasterConfigTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIMEx_Exported_Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIMEx_Remap + * @{ + */ + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /* !< TIM2 ITR1 input is connected to TIM10 OC */ +#define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /* !< TIM2 ITR1 input is connected to TIM5 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /* !< TIM3 ITR2 input is connected to TIM11 OC */ +#define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /* !< TIM3 ITR2 input is connected to TIM5 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /* !< TIM9 ITR1 input is connected to TIM3 TGO */ +#define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /* !< TIM9 ITR1 input is connected to touch sensing I/O */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ +#define TIM_TIM9_GPIO (0x00000000) /* !< TIM9 Channel1 is connected to GPIO */ +#define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /* !< TIM9 Channel1 is connected to LSE internal clock */ +#define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /* !< TIM9 Channel1 is connected to GPIO */ +#define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /* !< TIM9 Channel1 is connected to GPIO */ + + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define TIM_TIM10_TI1RMP (0x00000000) /* !< TIM10 Channel 1 depends on TI1_RMP */ +#define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /* !< TIM10 Channel 1 is connected to RI */ +#define TIM_TIM10_ETR_LSE (0x00000000) /* !< TIM10 ETR input is connected to LSE clock */ +#define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /* !< TIM10 ETR input is connected to TIM9 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ +#define TIM_TIM10_GPIO (0x00000000) /* !< TIM10 Channel1 is connected to GPIO */ +#define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /* !< TIM10 Channel1 is connected to LSI internal clock */ +#define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /* !< TIM10 Channel1 is connected to LSE internal clock */ +#define TIM_TIM10_RTC TIM_OR_TI1RMP /* !< TIM10 Channel1 is connected to RTC wakeup interrupt */ + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define TIM_TIM11_TI1RMP (0x00000000) /* !< TIM11 Channel 1 depends on TI1_RMP */ +#define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /* !< TIM11 Channel 1 is connected to RI */ +#define TIM_TIM11_ETR_LSE (0x00000000) /* !< TIM11 ETR input is connected to LSE clock */ +#define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /* !< TIM11 ETR input is connected to TIM9 TGO */ +#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ +#define TIM_TIM11_GPIO (0x00000000) /* !< TIM11 Channel1 is connected to GPIO */ +#define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /* !< TIM11 Channel1 is connected to MSI internal clock */ +#define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /* !< TIM11 Channel1 is connected to HSE_RTC clock */ +#define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /* !< TIM11 Channel1 is connected to GPIO */ + + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \ + (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \ + (((INSTANCE) == TIM9) && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2))) || \ + (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \ + (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \ + ) +#else /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \ + (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1))) \ + ) +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 + * @{ + */ + +/** + * @} + */ + +/* Extension Callback *********************************************************/ + +/** @addtogroup TIMEx_Exported_Functions_Group3 + * @{ + */ + +/** + * @} + */ +/* Extension Peripheral State functions **************************************/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h new file mode 100644 index 000000000..0329bd7d9 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h @@ -0,0 +1,624 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_uart.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains all the functions prototypes for the UART + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_UART_H +#define __STM32L1xx_HAL_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). + This parameter can be a value of @ref UART_Over_Sampling */ +}UART_InitTypeDef; + +/** + * @brief HAL UART State structures definition + */ +typedef enum +{ + HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_UART_STATE_ERROR = 0x04 /*!< Error */ +}HAL_UART_StateTypeDef; + +/** + * @brief HAL UART Error Code structure definition + */ +typedef enum +{ + HAL_UART_ERROR_NONE = 0x00, /*!< No error */ + HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ + HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ + HAL_UART_ERROR_FE = 0x04, /*!< frame error */ + HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */ +}HAL_UART_ErrorTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /* UART registers base address */ + + UART_InitTypeDef Init; /* UART communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /* UART Tx Transfer size */ + + uint16_t TxXferCount; /* UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /* UART Rx Transfer size */ + + uint16_t RxXferCount; /* UART Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + __IO HAL_UART_StateTypeDef State; /* UART communication state */ + + __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */ + +}UART_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported constants + * @{ + */ + +/** @defgroup UART_Word_Length UART Word Length + * @{ + */ +#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 ((uint32_t)0x00000000) +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE ((uint32_t)0x00000000) +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) +/** + * @} + */ + + /** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE ((uint32_t)0x00000000) +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +/** + * @} + */ + +/** @defgroup UART_WakeUp_functions UART Wakeup Functions + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +/** + * @} + */ + +/** @defgroup UART_Flags UART FLags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ +#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define UART_FLAG_TC ((uint32_t)USART_SR_TC) +#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define UART_FLAG_NE ((uint32_t)USART_SR_NE) +#define UART_FLAG_FE ((uint32_t)USART_SR_FE) +#define UART_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupt Definitions + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask in the XX register + * - Y : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * + * @{ + */ +#define UART_IT_PE ((uint32_t)0x10000100) +#define UART_IT_TXE ((uint32_t)0x10000080) +#define UART_IT_TC ((uint32_t)0x10000040) +#define UART_IT_RXNE ((uint32_t)0x10000020) +#define UART_IT_IDLE ((uint32_t)0x10000010) + +#define UART_IT_LBD ((uint32_t)0x20000040) +#define UART_IT_CTS ((uint32_t)0x30000400) + +#define UART_IT_ERR ((uint32_t)0x30000001) + +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART interruptions flag mask + * @{ + */ +#define UART_IT_MASK ((uint32_t)0x0000FFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + + +/** @brief Reset UART handle state + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) + +/** @brief Flushs the UART DR register + * @param __HANDLE__: specifies the UART Handle. + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified UART flag is set or not. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg UART_FLAG_LBD: LIN Break detection flag + * @arg UART_FLAG_TXE: Transmit data register empty flag + * @arg UART_FLAG_TC: Transmission Complete flag + * @arg UART_FLAG_RXNE: Receive data register not empty flag + * @arg UART_FLAG_IDLE: Idle Line detection flag + * @arg UART_FLAG_ORE: OverRun Error flag + * @arg UART_FLAG_NE: Noise Error flag + * @arg UART_FLAG_FE: Framing Error flag + * @arg UART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified UART pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg UART_FLAG_LBD: LIN Break detection flag. + * @arg UART_FLAG_TC: Transmission Complete flag. + * @arg UART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enables or disables the specified UART interrupt. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __INTERRUPT__: specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Checks whether the specified UART interrupt has occurred or not. + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @param __IT__: specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ERR: Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + +/** @brief macros to enables or disables the UART's one bit sampling method + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) +#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) + +/** @brief Enable UART + * @param __HANDLE__: specifies the UART Handle. + * The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART + * The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or + * UART peripheral (availability depending on device for UARTy). + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_))) +#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100) +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F)) + +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_))) +#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100) +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F)) + +/** @brief Check UART Baud rate + * @param __BAUDRATE__: Baudrate specified by the user + * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h new file mode 100644 index 000000000..115298864 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_usart.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_USART_H +#define __STM32L1xx_HAL_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +}USART_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04 /*!< Error */ +}HAL_USART_StateTypeDef; + +/** + * @brief HAL USART Error Code structure definition + */ +typedef enum +{ + HAL_USART_ERROR_NONE = 0x00, /*!< No error */ + HAL_USART_ERROR_PE = 0x01, /*!< Parity error */ + HAL_USART_ERROR_NE = 0x02, /*!< Noise error */ + HAL_USART_ERROR_FE = 0x04, /*!< frame error */ + HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */ +}HAL_USART_ErrorTypeDef; + +/** + * @brief USART handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /* USART registers base address */ + + USART_InitTypeDef Init; /* Usart communication parameters */ + + uint8_t *pTxBuffPtr; /* Pointer to Usart Tx transfer Buffer */ + + uint16_t TxXferSize; /* Usart Tx Transfer size */ + + __IO uint16_t TxXferCount; /* Usart Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /* Pointer to Usart Rx transfer Buffer */ + + uint16_t RxXferSize; /* Usart Rx Transfer size */ + + __IO uint16_t RxXferCount; /* Usart Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /* Usart Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* Usart Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + __IO HAL_USART_StateTypeDef State; /* Usart communication state */ + + __IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */ + +}USART_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported constants + * @{ + */ + +/** @defgroup USART_Word_Length USART Word Length + * @{ + */ +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ + ((LENGTH) == USART_WORDLENGTH_9B)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_1 ((uint32_t)0x00000000) +#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) +#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ + ((STOPBITS) == USART_STOPBITS_0_5) || \ + ((STOPBITS) == USART_STOPBITS_1_5) || \ + ((STOPBITS) == USART_STOPBITS_2)) +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE ((uint32_t)0x00000000) +#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ + ((PARITY) == USART_PARITY_EVEN) || \ + ((PARITY) == USART_PARITY_ODD)) +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX ((uint32_t)USART_CR1_RE) +#define USART_MODE_TX ((uint32_t)USART_CR1_TE) +#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) +#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLED ((uint32_t)0x00000000) +#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \ + ((CLOCK) == USART_CLOCK_ENABLED)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW ((uint32_t)0x00000000) +#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) +#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE ((uint32_t)0x00000000) +#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) +#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) +#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ + ((LASTBIT) == USART_LASTBIT_ENABLE)) +/** + * @} + */ + +/** @defgroup USART_NACK_State USART NACK State + * @{ + */ +#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK) +#define USARTNACK_DISABLED ((uint32_t)0x00000000) +#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \ + ((NACK) == USARTNACK_DISABLED)) +/** + * @} + */ + +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ + +#define USART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define USART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define USART_FLAG_TC ((uint32_t)USART_SR_TC) +#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define USART_FLAG_NE ((uint32_t)USART_SR_NE) +#define USART_FLAG_FE ((uint32_t)USART_SR_FE) +#define USART_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition USART Interrupts Definition + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask in the XX register + * - Y : Interrupt source register (4bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * + * @{ + */ +#define USART_IT_PE ((uint32_t)0x10000100) +#define USART_IT_TXE ((uint32_t)0x10000080) +#define USART_IT_TC ((uint32_t)0x10000040) +#define USART_IT_RXNE ((uint32_t)0x10000020) +#define USART_IT_IDLE ((uint32_t)0x10000010) + +#define USART_IT_LBD ((uint32_t)0x20000040) +#define USART_IT_CTS ((uint32_t)0x30000400) + +#define USART_IT_ERR ((uint32_t)0x30000001) + + +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask USART interruptions flag mask + * @{ + */ +#define USART_IT_MASK ((uint32_t)0x0000FFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + + +/** @brief Reset USART handle state + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) + +/** @brief Checks whether the specified USART flag is set or not. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ + +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified USART pending flags. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ + (__HANDLE__)->Instance->DR;}while(0) +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the USART ORE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enables or disables the specified Usart interrupts. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __INTERRUPT__: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ + (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) + + + +/** @brief Checks whether the specified Usart interrupt has occurred or not. + * @param __HANDLE__: specifies the USART Handle. + * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. + * @param __IT__: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ERR: Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) + +/** @brief Enable USART + * @param __HANDLE__: specifies the USART Handle. + * The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral + * @retval None + */ +#define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) + +/** @brief Disable USART + * @param __HANDLE__: specifies the USART Handle. + * The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) + + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +#define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) +#define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100) +#define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) +#define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) + +/** @brief Check USART Baud rate + * @param __BAUDRATE__: Baudrate specified by the user + * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval Test result (TRUE or FALSE) + */ +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); +void HAL_USART_MspInit(USART_HandleTypeDef *husart); +void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ + +/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_USART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h new file mode 100644 index 000000000..44d1f0970 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_wwdg.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of WWDG HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_WWDG_H +#define __STM32L1xx_HAL_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Types WWDG Exported Types + * @{ + */ + +/** + * @brief WWDG HAL State Structure definition + */ +typedef enum +{ + HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ + HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ + HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ + HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ + HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ +}HAL_WWDG_StateTypeDef; + +/** + * @brief WWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + This parameter can be a value of @ref WWDG_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. + This parameter must be a number lower than Max_Data = 0x80 */ + + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + +}WWDG_InitTypeDef; + +/** + * @brief WWDG handle Structure definition + */ +typedef struct +{ + WWDG_TypeDef *Instance; /*!< Register base address */ + + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ + + HAL_LockTypeDef Lock; /*!< WWDG locking object */ + + __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */ + +}WWDG_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants WWDG Exported Constants + * @{ + */ + +/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress AliasRegion + * @brief WWDG registers bit address in the alias region + * @{ + */ + +/* --- CFR Register ---*/ +/* Alias word address of EWI bit */ +#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04) + +/** + * @} + */ + +/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition + * @{ + */ +#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI) + +/** + * @} + */ + +/** @defgroup WWDG_Flag_definition WWDG Flag definition + * @brief WWDG Flag definition + * @{ + */ +#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */ + +/** + * @} + */ + +/** @defgroup WWDG_Prescaler WWDG Prescaler + * @{ + */ +#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */ + +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8)) + +/** + * @} + */ + +/** @defgroup WWDG_Window WWDG Window + * @{ + */ +#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Counter WWDG Counter + * @{ + */ +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Macros WWDG Exported Macros + * @{ + */ + +/** @brief Reset WWDG handle state + * @param __HANDLE__: WWDG handle + * @retval None + */ +#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) + +/** + * @brief Enables the WWDG peripheral. + * @param __HANDLE__: WWDG handle + * @retval None + */ +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) + +/** + * @brief Gets the selected WWDG's flag status. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the WWDG's pending flags. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval None + */ +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** + * @brief Enables the WWDG early wakeup interrupt. + * @param __INTERRUPT__: specifies the interrupt to enable. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early wakeup interrupt + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @retval None + */ +#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__)) + +/** @brief Clear the WWDG's interrupt pending bits + * bits to clear the selected interrupt pending bits. + * @param __HANDLE__: WWDG handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + */ +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +/** @addtogroup WWDG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); +HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); +HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_WWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h new file mode 100644 index 000000000..4ac76030f --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h @@ -0,0 +1,567 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_fsmc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of FSMC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_FSMC_H +#define __STM32L1xx_LL_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FSMC_LL + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_Bank1_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_Bank1E_TypeDef + +#define FSMC_NORSRAM_DEVICE FSMC_Bank1 +#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E + +/** + * @brief FSMC_NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + +}FSMC_NORSRAM_InitTypeDef; + + +/** + * @brief FSMC_NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ + +}FSMC_NORSRAM_TimingTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank + * @{ + */ +#define FSMC_BANK1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_BANK1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_BANK1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_BANK1_NORSRAM4 ((uint32_t)0x00000006) + +/* To keep compatibility with previous families */ +#define FSMC_NORSRAM_BANK1 FSMC_BANK1_NORSRAM1 +#define FSMC_NORSRAM_BANK2 FSMC_BANK1_NORSRAM2 +#define FSMC_NORSRAM_BANK3 FSMC_BANK1_NORSRAM3 +#define FSMC_NORSRAM_BANK4 FSMC_BANK1_NORSRAM4 + +#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \ + ((__BANK__) == FSMC_BANK1_NORSRAM2) || \ + ((__BANK__) == FSMC_BANK1_NORSRAM3) || \ + ((__BANK__) == FSMC_BANK1_NORSRAM4)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing + * @{ + */ + +#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) +#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) + +#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type FSMC Memory Type + * @{ + */ + +#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) +#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) +#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) + + +#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width + * @{ + */ + +#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) + +#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access + * @{ + */ + +#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) +#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode + * @{ + */ + +#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) +#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) + +#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) +/** + * @} + */ + + +/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity + * @{ + */ + +#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) +#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) + +#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode + * @{ + */ + +#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) +#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) + +#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing FSMC Wait Timing + * @{ + */ + +#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) +#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) + +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation FSMC Write Operation + * @{ + */ + +#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) +#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) + +#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal FSMC Wait Signal + * @{ + */ + +#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) +#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) + +#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) + +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode FSMC Extended Mode + * @{ + */ + +#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) +#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) + +#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait + * @{ + */ + +#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) +#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) + +#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst FSMC Write Burst + * @{ + */ + +#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) +#define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) + +#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division FSMC CLK Division + * @{ + */ + +#define FSMC_CLK_DIV2 ((uint32_t)0x00000002) +#define FSMC_CLK_DIV3 ((uint32_t)0x00000003) +#define FSMC_CLK_DIV4 ((uint32_t)0x00000004) +#define FSMC_CLK_DIV5 ((uint32_t)0x00000005) +#define FSMC_CLK_DIV6 ((uint32_t)0x00000006) +#define FSMC_CLK_DIV7 ((uint32_t)0x00000007) +#define FSMC_CLK_DIV8 ((uint32_t)0x00000008) +#define FSMC_CLK_DIV9 ((uint32_t)0x00000009) +#define FSMC_CLK_DIV10 ((uint32_t)0x0000000A) +#define FSMC_CLK_DIV11 ((uint32_t)0x0000000B) +#define FSMC_CLK_DIV12 ((uint32_t)0x0000000C) +#define FSMC_CLK_DIV13 ((uint32_t)0x0000000D) +#define FSMC_CLK_DIV14 ((uint32_t)0x0000000E) +#define FSMC_CLK_DIV15 ((uint32_t)0x0000000F) +#define FSMC_CLK_DIV16 ((uint32_t)0x00000010) +#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency FSMC Data Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode FSMC Access Mode + * @{ + */ + +#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) +#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) +#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) +#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) + +#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ + ((__MODE__) == FSMC_ACCESS_MODE_B) || \ + ((__MODE__) == FSMC_ACCESS_MODE_C) || \ + ((__MODE__) == FSMC_ACCESS_MODE_D)) +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance + * @{ + */ + +#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) + +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance + * @{ + */ + +#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__: FSMC_NORSRAM Instance + * @param __BANK__: FSMC_NORSRAM Bank + * @retval none + */ +#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__: FSMC_NORSRAM Instance + * @param __BANK__: FSMC_NORSRAM Bank + * @retval none + */ +#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup FSMC_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_FSMC_NORSRAM_Group1 + * @{ + */ + +/* FSMC_NORSRAM Controller functions ******************************************/ +/* Initialization/de-initialization functions */ +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank); + +/** + * @} + */ + +/** @addtogroup HAL_FSMC_NORSRAM_Group2 + * @{ + */ + +/* FSMC_NORSRAM Control functions */ +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_FSMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h new file mode 100644 index 000000000..af0aa6cdb --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h @@ -0,0 +1,907 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_sdmmc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Header file of low layer SDMMC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_SD_H +#define __STM32L1xx_LL_SD_H + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDMMC_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types + * @{ + */ + +/** + * @brief SDMMC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ + + uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ + + uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ + + uint32_t BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ + + uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ + + uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + +}SDIO_InitTypeDef; + + +/** + * @brief SDIO Command Control structure + */ +typedef struct +{ + uint32_t Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register. */ + + uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and + Max_Data = 64 */ + + uint32_t Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDMMC_LL_Response_Type */ + + uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ + + uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_CPSM_State */ +}SDIO_CmdInitTypeDef; + + +/** + * @brief SDIO Data Control structure + */ +typedef struct +{ + uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ + + uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ + + uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ + + uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_DPSM_State */ +}SDIO_DataInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants + * @{ + */ + +/** @defgroup SDMMC_LL_Clock_Edge Clock Edge + * @{ + */ +#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) +#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE + +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ + ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass + * @{ + */ +#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) +#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS + +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ + ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving + * @{ + */ +#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) +#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV + +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ + ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Bus_Wide Bus Width + * @{ + */ +#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) +#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 +#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 + +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ + ((WIDE) == SDIO_BUS_WIDE_4B) || \ + ((WIDE) == SDIO_BUS_WIDE_8B)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control + * @{ + */ +#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) +#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN + +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ + ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Division Clock Division + * @{ + */ +#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Command_Index Command Index + * @{ + */ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Response_Type Response Type + * @{ + */ +#define SDIO_RESPONSE_NO ((uint32_t)0x00000000) +#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 +#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ + ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ + ((RESPONSE) == SDIO_RESPONSE_LONG)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt + * @{ + */ +#define SDIO_WAIT_NO ((uint32_t)0x00000000) +#define SDIO_WAIT_IT SDIO_CMD_WAITINT +#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND + +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ + ((WAIT) == SDIO_WAIT_IT) || \ + ((WAIT) == SDIO_WAIT_PEND)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_CPSM_State CPSM State + * @{ + */ +#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) +#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN + +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ + ((CPSM) == SDIO_CPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Response_Registers Response Register + * @{ + */ +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) + +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ + ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || \ + ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Data_Length Data Lenght + * @{ + */ +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size + * @{ + */ +#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) +#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 +#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 +#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030) +#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 +#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050) +#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060) +#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070) +#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 +#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090) +#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0) +#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0) +#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0) +#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0) +#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0) + +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction + * @{ + */ +#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) +#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ + ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Transfer_Type Transfer Type + * @{ + */ +#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) +#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDIO_TRANSFER_MODE_STREAM)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_DPSM_State DPSM State + * @{ + */ +#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) +#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN + +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ + ((DPSM) == SDIO_DPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode + * @{ + */ +#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000) +#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001) + +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ + ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources + * @{ + */ +#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL +#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL +#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT +#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT +#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR +#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR +#define SDIO_IT_CMDREND SDIO_STA_CMDREND +#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT +#define SDIO_IT_DATAEND SDIO_STA_DATAEND +#define SDIO_IT_STBITERR SDIO_STA_STBITERR +#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND +#define SDIO_IT_CMDACT SDIO_STA_CMDACT +#define SDIO_IT_TXACT SDIO_STA_TXACT +#define SDIO_IT_RXACT SDIO_STA_RXACT +#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE +#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF +#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF +#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF +#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE +#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE +#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL +#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL +#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT +#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND + +/** + * @} + */ + +/** @defgroup SDMMC_LL_Flags Flags + * @{ + */ +#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL +#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL +#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT +#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT +#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR +#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR +#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND +#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT +#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND +#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR +#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND +#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT +#define SDIO_FLAG_TXACT SDIO_STA_TXACT +#define SDIO_FLAG_RXACT SDIO_STA_RXACT +#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE +#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF +#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF +#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF +#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE +#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE +#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL +#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL +#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT +#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros + * @{ + */ + +/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions + * @brief SDMMC_LL registers bit address in the alias region + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region -------------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BITNUMBER 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BITNUMBER 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BITNUMBER 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BITNUMBER 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BITNUMBER 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BITNUMBER 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BITNUMBER 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BITNUMBER 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BITNUMBER 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BITNUMBER 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4)) + +/* ---------------------- SDIO registers bit mask --------------------------- */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ + SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ + SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) + +/* --- DCTRL Register ---*/ +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ + SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ + SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ + SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/* SDIO Intialization Frequency (400KHz max) */ +#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) + +/* SDIO Data Transfer Frequency */ +#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4) + +/** + * @} + */ + +/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the SDIO device. + * @retval None + */ +#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) + +/** + * @brief Disable the SDIO device. + * @retval None + */ +#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) + +/** + * @brief Enable the SDIO DMA transfer. + * @retval None + */ +#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) + +/** + * @brief Disable the SDIO DMA transfer. + * @retval None + */ +#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) + +/** + * @brief Enable the SDIO device interrupt. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) + +/** + * @brief Disable the SDIO device interrupt. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) + + +/** + * @brief Clears the SDIO pending flags. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @retval None + */ +#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) + +/** + * @brief Disable Start the SD I/O Read Wait operations. + * @retval None + */ +#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @retval None + */ +#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) + +/** + * @brief Disable Stop the SD I/O Read Wait operations. + * @retval None + */ +#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) + +/** + * @brief Enable the SD I/O Mode Operation. + * @retval None + */ +#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) + +/** + * @brief Disable the SD I/O Mode Operation. + * @retval None + */ +#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) + +/** + * @brief Enable the SD I/O Suspend command sending. + * @retval None + */ +#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) + +/** + * @brief Disable the SD I/O Suspend command sending. + * @retval None + */ +#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) + +/** + * @brief Enable the command completion signal. + * @retval None + */ +#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) + +/** + * @brief Disable the command completion signal. + * @retval None + */ +#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) + +/** + * @brief Enable the CE-ATA interrupt. + * @retval None + */ +#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0) + +/** + * @brief Disable the CE-ATA interrupt. + * @retval None + */ +#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1) + +/** + * @brief Enable send CE-ATA command (CMD61). + * @retval None + */ +#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) + +/** + * @brief Disable send CE-ATA command (CMD61). + * @retval None + */ +#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDMMC_LL_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup HAL_SDMMC_LL_Group1 + * @{ + */ +HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group2 + * @{ + */ +/* Blocking mode: Polling */ +uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); +HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group3 + * @{ + */ +HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); +HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); + +/* Command path state machine (CPSM) management functions */ +HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); + +/* Data path state machine (DPSM) management functions */ +HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); +uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); + +/* SDIO IO Cards mode management functions */ +HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#endif /* __STM32L1xx_LL_SD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Release_Notes.html b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Release_Notes.html new file mode 100644 index 000000000..57f318105 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Release_Notes.html @@ -0,0 +1,972 @@ + + + + + + + + + + + + + +Release Notes for STM32F4xx HAL Drivers + + + + + + + + + + +
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Release Notes for STM32L1xx HAL Drivers

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Copyright + 2014 STMicroelectronics

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Update History

+ +

V1.0.0 / 05-September-2014

+ +

Main Changes

+ + + + + + +
    +
  • First official release

License

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+Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met:
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  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions +in binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
    +     +
+        from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +
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For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

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+ +
+ + \ No newline at end of file diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c new file mode 100644 index 000000000..02673c07e --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c @@ -0,0 +1,454 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Defines HAL Private Defines + * @{ + */ + +/** + * @brief STM32L1xx HAL Driver version number V1.0.0 + */ +#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32L1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\ + |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32L1xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ + +static __IO uint32_t uwTick; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak + to make override possible in case of other implementations in user file. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Flash prefetch, + * Configures time base source, NVIC and Low level hardware + * @note This function is called at the beginning of program after reset and before + * the clock configuration + * @note The time base configuration is based on MSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __APB1_FORCE_RESET(); + __APB1_RELEASE_RESET(); + + __APB2_FORCE_RESET(); + __APB2_RELEASE_RESET(); + + __AHB_FORCE_RESET(); + __AHB_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /*Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick++; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(__IO uint32_t Delay) +{ + uint32_t tickstart = 0; + tickstart = HAL_GetTick(); + while((HAL_GetTick() - tickstart) < Delay) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32L1xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c new file mode 100644 index 000000000..5f62045cd --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c @@ -0,0 +1,1759 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_adc.c + * @author MCD Application conversion + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization and de-initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of regular + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Analog Watchdog configuration + * ++ Channels configuration on regular group + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * Other functions (extended functions) are available in file + * "stm32l1xx_hal_adc_ex.c". + * + @verbatim + ============================================================================== + ##### ADC specific features ##### + ============================================================================== + [..] + (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution + + (#) Interrupt generation at the end of regular conversion, end of injected + conversion, and in case of analog watchdog or overrun events. + + (#) Single and continuous conversion modes. + + (#) Scan mode for automatic conversion of channel 0 to channel 'n'. + + (#) Data alignment with in-built data coherency. + + (#) Channel-wise programmable sampling time. + + (#) ADC conversion Regular or Injected groups. + + (#) External trigger (timer or EXTI) with configurable polarity for both + regular and injected groups. + + (#) DMA request generation for transfer of conversions data of regular group. + + (#) ADC calibration + + (#) ADC offset on injected channels + + (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + + (#) ADC input range: from Vref– (connected to Vssa) to Vref+ (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Enable the ADC interface + As prerequisite, ADC clock must be configured at RCC top level. + Two clocks settings are mandatory: + - ADC clock (core clock): + Example: + Into HAL_ADC_MspInit() (recommended code location): + __ADC1_CLK_ENABLE(); + + - ADC clock (conversions clock): + Only one possible clock source: derived from HSI RC 16MHz oscillator + (HSI). + Example: + Into HAL_ADC_MspInit() or with main setting of RCC: + RCC_OscInitTypeDef RCC_OscInitStructure; + HAL_RCC_GetOscConfig(&RCC_OscInitStructure); + RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); + RCC_OscInitStructure.HSIState = RCC_HSI_ON; + RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStructure.PLL.PLLSource = ... + RCC_OscInitStructure.PLL... + HAL_RCC_OscConfig(&RCC_OscInitStructure); + + Note: ADC is connected directly to HSI RC 16MHz oscillator. + Therefore, RCC PLL setting has no impact on ADC. + PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or + enabled with HSI16 as clock source + (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device + main clock source SYSCLK. + The only mandatory setting is ".HSIState = RCC_HSI_ON" + + Note: ADC clock prescaler is configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + __GPIOx_CLK_ENABLE(); + (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); + + (#) Configure the ADC parameters (conversion resolution, data alignment, + continuous mode, ...) using the HAL_ADC_Init() function. + + (#) Activate the ADC peripheral using one of the start functions: + HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(). + + *** Channels configuration to regular group *** + ================================================ + [..] + (+) To configure the ADC regular group features, use + HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. + (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. + + *** DMA for regular group configuration *** + =========================================== + [..] + (+) To enable the DMA mode for regular group, use the + HAL_ADC_Start_DMA() function. + (+) To enable the generation of DMA requests continuously at the end of + the last DMA transfer, use the HAL_ADC_Init() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + + /* Fixed timeout values for ADC calibration, enable settling time. */ + /* Values defined to be higher than worst cases: low clocks freq, */ + /* maximum prescaler. */ + /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ + /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ + /* Unit: ms */ + #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) + #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) + + /* Delay for ADC stabilization time. */ + /* Maximum delay is 3.5us (refer to device datasheet, parameter tSTAB). */ + /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */ + /* have the minimum number of CPU cycles to fulfill this delay. */ + #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)112) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC +@endverbatim + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * (clock source APB2). + * See commented example code below that can be copied and uncommented + * into HAL_ADC_MspInit(). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + uint32_t tmp_cr1 = 0; + uint32_t tmp_cr2 = 0; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait)); + assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff)); + assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + + if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); + } + + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + } + + + /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ + /* at RCC top level. */ + /* Refer to header of this file for more details on clock enabling */ + /* procedure. */ + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + { + /* Enable SYSCFG clock to control the routing Interface (RI) */ + __SYSCFG_CLK_ENABLE(); + + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (tmpHALStatus != HAL_ERROR) + { + /* Initialize the ADC state */ + hadc->State = HAL_ADC_STATE_BUSY; + + /* Set ADC parameters */ + + /* Configuration of common ADC clock: clock source HSI with selectable */ + /* prescaler */ + MODIFY_REG(ADC->CCR , + ADC_CCR_ADCPRE , + hadc->Init.ClockPrescaler ); + + /* Configuration of ADC: */ + /* - external trigger polarity */ + /* - End of conversion selection */ + /* - DMA continuous request */ + /* - Channels bank (Banks availability depends on devices categories) */ + /* - continuous conversion mode */ + tmp_cr2 |= (hadc->Init.DataAlign | + hadc->Init.EOCSelection | + __ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) | + hadc->Init.ChannelsBank | + __ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) ); + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmp_cr2 |= ( hadc->Init.ExternalTrigConv | + hadc->Init.ExternalTrigConvEdge ); + } + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - delay selection (LowPowerAutoWait mode) */ + /* - resolution */ + /* - auto power off (LowPowerAutoPowerOff mode) */ + /* - scan mode */ + /* - discontinuous mode disable/enable */ + /* - discontinuous mode number of conversions */ + if ((__HAL_ADC_IS_ENABLED(hadc) == RESET)) + { + tmp_cr2 |= hadc->Init.LowPowerAutoWait; + + tmp_cr1 |= (hadc->Init.Resolution | + hadc->Init.LowPowerAutoPowerOff | + __ADC_CR1_SCAN(hadc->Init.ScanConvMode) ); + + /* Enable discontinuous mode only if continuous mode is disabled */ + if ((hadc->Init.DiscontinuousConvMode == ENABLE) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* Enable discontinuous mode of regular group */ + /* Set the number of channels to be converted in discontinuous mode */ + tmp_cr1 |= ((ADC_CR1_DISCEN) | + __ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)); + } + + /* Update ADC configuration register CR1 with previous settings */ + MODIFY_REG(hadc->Instance->CR1, + ADC_CR1_RES | + ADC_CR1_PDI | + ADC_CR1_PDD | + ADC_CR1_DISCNUM | + ADC_CR1_DISCEN | + ADC_CR1_SCAN , + tmp_cr1 ); + } + + /* Update ADC configuration register CR2 with previous settings */ + MODIFY_REG(hadc->Instance->CR2 , + __ADC_CR2_MASK_ADCINIT() , + tmp_cr2 ); + + /* Configuration of regular group sequencer: */ + /* - if scan mode is disabled, regular channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "NbrOfConversion" is discarded. */ + /* Note: Scan mode is present by hardware on this device and, if */ + /* disabled, discards automatically nb of conversions. Anyway, nb of */ + /* conversions is forced to 0x00 for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion" */ + if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + MODIFY_REG(hadc->Instance->SQR1 , + ADC_SQR1_L , + __ADC_SQR1_L(hadc->Init.NbrOfConversion) ); + } + else + { + MODIFY_REG(hadc->Instance->SQR1, + ADC_SQR1_L , + 0x00000000 ); + } + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core IP clocking. */ + /* Check through register CR2 (excluding execution control bits ADON, */ + /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */ + if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON | + ADC_CR2_SWSTART | ADC_CR2_JSWSTART | + ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL )) + == tmp_cr2) + { + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Initialize the ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + tmpHALStatus = HAL_ERROR; + } + + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Deinitialize the ADC peripheral registers to its default reset values. + * @note To not impact other ADCs, reset of common ADC registers have been + * left commented below. + * If needed, the example code can be copied and uncommented into + * function HAL_ADC_MspDeInit(). + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY; + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmpHALStatus = ADC_ConversionStop_Disable(hadc); + + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (tmpHALStatus != HAL_ERROR) + { + /* ========== Reset ADC registers ========== */ + /* Reset register SR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | + ADC_FLAG_JSTRT | ADC_FLAG_STRT)); + + /* Reset register CR1 */ + CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | + ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD | + ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | + ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | + ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | + ADC_CR1_AWDCH )); + + /* Reset register CR2 */ + __ADC_CR2_CLEAR(hadc); + + /* Reset register SMPR0 */ + __ADC_SMPR0_CLEAR(hadc); + + /* Reset register SMPR1 */ + CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | + ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | + ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | + ADC_SMPR1_SMP20 )); + + /* Reset register SMPR2 */ + CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | + ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | + ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | + ADC_SMPR2_SMP10 )); + + /* Reset register SMPR3 */ + CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | + ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | + ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 | + ADC_SMPR3_SMP0 )); + + /* Reset register JOFR1 */ + CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); + /* Reset register JOFR2 */ + CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); + /* Reset register JOFR3 */ + CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); + /* Reset register JOFR4 */ + CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); + + /* Reset register HTR */ + CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); + /* Reset register LTR */ + CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); + + /* Reset register SQR1 */ + CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX)); + + /* Reset register SQR2 */ + CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | + ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 )); + + /* Reset register SQR3 */ + CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | + ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 )); + + /* Reset register SQR4 */ + CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | + ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 )); + + /* Reset register SQR5 */ + CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | + ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )); + + + /* Reset register JSQR */ + CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | + ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | + ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); + + /* Reset register JSQR */ + CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | + ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | + ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable*/ + + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ + /* bits in access mode read only, no direct reset applicable*/ + + /* Reset register CCR */ + CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE); + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripheral: ADC state is */ + /* forced to a similar state after device power-on. */ + /* If needed, copy-paste and uncomment the following reset code into */ + /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ + /* */ + /* __ADC1_FORCE_RESET() */ + /* __ADC1_RELEASE_RESET() */ + + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Initializes the ADC MSP. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the ADC MSP. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of regular group. + * Interruptions enabled in this function: None. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmpHALStatus = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* State machine update: Check if an injected conversion is ongoing */ + if(hadc->State == HAL_ADC_STATE_BUSY_INJ) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + } + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Start conversion of regular group if software start has been selected. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) + { + /* Start ADC conversion on regular group */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing interruption of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmpHALStatus = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @param hadc: ADC handle + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait until End of Conversion flag is raised */ + while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update ADC state machine to timeout */ + hadc->State = HAL_ADC_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + + /* Clear end of conversion flag of regular group if low power feature "Auto */ + /* Wait" is disabled, to not interfere with this feature until data */ + /* register is read using function HAL_ADC_GetValue(). */ + if (hadc->Init.LowPowerAutoWait == DISABLE) + { + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + } + + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Update ADC state machine */ + if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) + { + /* Check if a conversion is ready on injected group */ + if(hadc->State == HAL_ADC_STATE_EOC_INJ) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_REG; + } + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Poll for conversion event. + * @param hadc: ADC handle + * @param EventType: the ADC event type. + * This parameter can be one of the following values: + * @arg AWD_EVENT: ADC Analog watchdog event. + * @arg OVR_EVENT: ADC Overrun event + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update ADC state machine to timeout */ + hadc->State = HAL_ADC_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + + switch(EventType) + { + /* Analog watchdog (level out of window) event */ + case AWD_EVENT: + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_AWD; + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + break; + + /* Overrun event */ + default: /* Case OVR_EVENT */ + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to overrun */ + hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + + /* Clear ADC Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + break; + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Enables ADC, starts conversion of regular group with interruption. + * Interruptions enabled in this function: EOC (end of conversion), + * overrun. + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmpHALStatus = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* State machine update: Check if an injected conversion is ongoing */ + if(hadc->State == HAL_ADC_STATE_BUSY_INJ) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + } + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable end of conversion interrupt for regular group */ + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Start conversion of regular group if software start has been selected. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) + { + /* Start ADC conversion on regular group */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); + } + + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hadc: ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmpHALStatus = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Disable ADC end of conversion interrupt for regular group */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Enables ADC, starts conversion of regular group and transfers result + * through DMA. + * Interruptions enabled in this function: + * overrun, DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @param pData: The destination Buffer address. + * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @retval None + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmpHALStatus = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* State machine update: Check if an injected conversion is ongoing */ + if(hadc->State == HAL_ADC_STATE_BUSY_INJ) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + } + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + hadc->Instance->CR2 |= ADC_CR2_DMA; + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Start conversion of regular group if software start has been selected. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Note: Alternate trigger for single conversion could be to force an */ + /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ + if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) + { + /* Start ADC conversion on regular group */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @note: ADC peripheral disable is forcing interruption of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmpHALStatus = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Disable ADC DMA mode */ + hadc->Instance->CR2 &= ~ADC_CR2_DMA; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Get ADC regular group conversion result. + * @param hadc: ADC handle + * @retval Converted value + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief DMA transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Update ADC state machine */ + if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) + { + /* Check if a conversion is ready on injected group */ + if(hadc->State == HAL_ADC_STATE_EOC_INJ) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_REG; + } + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Half conversion callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + + /* Error callback */ + HAL_ADC_ErrorCallback(hadc); +} + +/** + * @brief Handles ADC interrupt request + * @param hadc: ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + + + /* ========== Check End of Conversion flag for regular group ========== */ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) + { + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Update ADC state machine */ + if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) + { + /* Check if a conversion is ready on injected group */ + if(hadc->State == HAL_ADC_STATE_EOC_INJ) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_REG; + } + } + } + + /* Disable interruption if no further conversion upcoming regular */ + /* external trigger or by continuous mode */ + if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* Disable ADC end of single conversion interrupt */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used by */ + /* overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + } + } + + /* ========== Check End of Conversion flag for injected group ========== */ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) + { + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Update ADC state machine */ + if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) + { + + if(hadc->State == HAL_ADC_STATE_EOC_REG) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_INJ; + } + } + } + + /* Disable interruption if no further conversion upcoming injected */ + /* external trigger or by automatic injected conversion with regular */ + /* group having no further conversion upcoming (same conditions as */ + /* regular group interruption disabling above). */ + if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) || + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + { + /* Disable ADC end of single conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + } + + /* Conversion complete callback */ + HAL_ADCEx_InjectedConvCpltCallback(hadc); + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); + } + } + + /* ========== Check Analog watchdog flags ========== */ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_AWD; + + /* Clear the ADCx's Analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD); + + /* Level out of window callback */ + HAL_ADC_LevelOutOfWindowCallback(hadc); + } + } + + /* ========== Check Overrun flag ========== */ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR)) + { + /* Change ADC state to error state */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to overrun */ + hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + + /* Error callback */ + HAL_ADC_ErrorCallback(hadc); + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + } + +} + +/** + * @brief Conversion complete callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog callback in non blocking mode. + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non blocking mode + * (ADC conversion with interruption or transfer by DMA) + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the regular + * group. + * @note In case of usage of internal measurement channels: + * Vbat/VrefInt/TempSensor. + * These internal paths can be be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into regular group, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_ChannelConfTypeDef". + * @param hadc: ADC handle + * @param sConfig: Structure of ADC channel for regular group. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + + + /* Regular sequence configuration */ + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7) + { + MODIFY_REG(hadc->Instance->SQR5, + __ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), + __ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13) + { + MODIFY_REG(hadc->Instance->SQR4, + __ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), + __ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 13 to 18 */ + else if (sConfig->Rank < 19) + { + MODIFY_REG(hadc->Instance->SQR3, + __ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), + __ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 19 to 24 */ + else if (sConfig->Rank < 25) + { + MODIFY_REG(hadc->Instance->SQR2, + __ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), + __ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); + } + /* For Rank 25 to 28 */ + else + { + MODIFY_REG(hadc->Instance->SQR1, + __ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), + __ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); + } + + + /* Channel sampling time configuration */ + /* For channels 0 to 9 */ + if (sConfig->Channel < ADC_CHANNEL_10) + { + MODIFY_REG(hadc->Instance->SMPR3, + __ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), + __ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); + } + /* For channels 10 to 19 */ + else if (sConfig->Channel < ADC_CHANNEL_20) + { + MODIFY_REG(hadc->Instance->SMPR2, + __ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), + __ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); + } + /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ + /* For channels 20 to 29 for devices Cat4, Cat.5 */ + else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX) + { + MODIFY_REG(hadc->Instance->SMPR1, + __ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), + __ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); + } + /* For channels 30 to 31 for devices Cat4, Cat.5 */ + else + { + __ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); + } + + /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ + /* and VREFINT measurement path. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || + (sConfig->Channel == ADC_CHANNEL_VREFINT) ) + { + SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Configures the analog watchdog. + * @param hadc: ADC handle + * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); + + if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) + { + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Analog watchdog configuration */ + + /* Configure ADC Analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) + { + /* Enable the ADC Analog watchdog interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); + } + else + { + /* Disable the ADC Analog watchdog interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); + } + + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: regular and/or injected groups, */ + /* one or all channels. */ + /* - Set the Analog watchdog channel (is not used if watchdog */ + /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ + hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL | + ADC_CR1_JAWDEN | + ADC_CR1_AWDEN | + ADC_CR1_AWDCH ); + + hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode | + AnalogWDGConfig->Channel ); + + /* Set the high threshold */ + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; + + /* Set the low threshold */ + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @} + */ + + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief return the ADC state + * @param hadc: ADC handle + * @retval HAL state + */ +HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +{ + /* Return ADC state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code + * @param hadc: ADC handle + * @retval ADC Error Code + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +{ + uint32_t wait_loop_index = 0; + uint32_t tickstart = 0; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (__HAL_ADC_IS_ENABLED(hadc) == RESET) + { + /* Enable the Peripheral */ + __ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time. */ + /* Delay fixed to worst case: maximum CPU frequency */ + while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES) + { + wait_loop_index++; + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for ADC effectively enabled */ + while(__HAL_ADC_IS_ENABLED(hadc) == RESET) + { + if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Stop ADC conversion and disable the selected ADC + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped to disable the ADC. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0; + + /* Verification if ADC is not already disabled: */ + if (__HAL_ADC_IS_ENABLED(hadc) != RESET) + { + /* Disable the ADC peripheral */ + __ADC_DISABLE(hadc); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for ADC effectively disabled */ + while(__HAL_ADC_IS_ENABLED(hadc) != RESET) + { + if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + + return HAL_ERROR; + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c new file mode 100644 index 000000000..58970b543 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c @@ -0,0 +1,849 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_adc_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization and de-initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of regular + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Analog Watchdog configuration + * ++ Channels configuration on regular group + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * Other functions (generic functions) are available in file + * "stm32l1xx_hal_adc.c". + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Activate the ADC peripheral using one of the start functions: + HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(). + + *** Channels configuration to injected group *** + ================================================ + [..] + (+) To configure the ADC Injected channels group features, use + HAL_ADCEx_InjectedConfigChannel() functions. + (+) To activate the continuous mode, use the HAL_ADC_Init() function. + (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() + function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Constants ADCEx Private Constants + * @{ + */ + + /* ADC conversion cycles (unit: ADC clock cycles) */ + /* (selected sampling time + conversion time of 12 ADC clock cycles, with */ + /* resolution 12 bits) */ + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5 ((uint32_t) 16) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES ((uint32_t) 21) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES ((uint32_t) 28) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES ((uint32_t) 36) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES ((uint32_t) 60) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES ((uint32_t)108) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES ((uint32_t)204) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES ((uint32_t)396) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of injected group. + (+) Stop conversion of injected group. + (+) Poll for conversion complete on injected group. + (+) Get result of injected channel conversion. + (+) Start conversion of injected group and enable interruptions. + (+) Stop conversion of injected group and disable interruptions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of injected group. + * Interruptions enabled in this function: None. + * @param hadc: ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmpHALStatus = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Check if a regular conversion is ongoing */ + if(hadc->State == HAL_ADC_STATE_BUSY_REG) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_INJ; + } + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Start conversion of injected group if software start has been selected */ + /* and if automatic injected conversion is disabled. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* If automatic injected conversion is enabled, conversion will start */ + /* after next regular group conversion. */ + if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Enable ADC software conversion for injected channels */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled with this function and if regular conversion + * is on going, function HAL_ADC_Stop must be used preliminarily. + * @note In case of auto-injection mode, HAL_ADC_Stop must be used. + * @param hadc: ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if((hadc->State != HAL_ADC_STATE_BUSY_REG) && + (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmpHALStatus = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Wait for injected group conversion to be completed. + * @param hadc: ADC handle + * @param Timeout: Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Variables for polling in case of scan mode enabled and polling for each */ + /* conversion. */ + /* Note: Variable "conversion_timeout_cpu_cycles" set to offset 28 CPU */ + /* cycles to compensate number of CPU cycles for processing of variable */ + /* "conversion_timeout_cpu_cycles_max" */ + uint32_t conversion_timeout_cpu_cycles = 28; + uint32_t conversion_timeout_cpu_cycles_max = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Polling for end of conversion: differentiation if single/sequence */ + /* conversion. */ + /* For injected group, flag JEOC is set only at the end of the sequence, */ + /* not for each conversion within the sequence. */ + /* If setting "EOCSelection" is set to poll for each single conversion, */ + /* management of polling depends on setting of injected group sequencer: */ + /* - If single conversion for injected group (scan mode disabled or */ + /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ + /* conversion completion. */ + /* - If sequence conversion for injected group (scan mode enabled and */ + /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ + /* sequence. */ + /* To poll for each conversion, the maximum conversion time is computed */ + /* from ADC conversion time (selected sampling time + conversion time of */ + /* 12 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ + /* settings, conversion time range can vary from 8 to several thousands */ + /* of CPU cycles). */ + + /* Note: On STM32L1, setting "EOCSelection" is related to regular group */ + /* only, by hardware. For compatibility with other STM32 devices, */ + /* this setting is related also to injected group by software. */ + if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) || + (hadc->Init.EOCSelection != EOC_SINGLE_CONV) ) + { + /* Wait until End of Conversion flag is raised */ + while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update ADC state machine to timeout */ + hadc->State = HAL_ADC_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + } + else + { + /* Computation of CPU cycles corresponding to ADC conversion cycles. */ + /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ + /* channels. */ + conversion_timeout_cpu_cycles_max = __ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc); + conversion_timeout_cpu_cycles_max *= __ADC_CONVCYCLES_MAX_RANGE(hadc); + + /* Poll with maximum conversion time */ + while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update ADC state machine to timeout */ + hadc->State = HAL_ADC_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + conversion_timeout_cpu_cycles ++; + } + } + + /* Clear end of conversion flag of injected group if low power feature */ + /* "Auto Wait" is disabled, to not interfere with this feature until data */ + /* register is read using function HAL_ADCEx_InjectedGetValue(). */ + if (hadc->Init.LowPowerAutoWait == DISABLE) + { + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); + } + + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Update ADC state machine */ + if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) + { + + if(hadc->State == HAL_ADC_STATE_EOC_REG) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC_INJ; + } + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Enables ADC, starts conversion of injected group with interruption. + * Interruptions enabled in this function: JEOC (end of conversion). + * Each of these interruptions has its dedicated callback function. + * @param hadc: ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmpHALStatus = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Check if a regular conversion is ongoing */ + if(hadc->State == HAL_ADC_STATE_BUSY_REG) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; + } + else + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_INJ; + } + + /* Set ADC error code to none */ + __HAL_ADC_CLEAR_ERRORCODE(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Enable end of conversion interrupt for injected channels */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + + /* Start conversion of injected group if software start has been selected */ + /* and if automatic injected conversion is disabled. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* If automatic injected conversion is enabled, conversion will start */ + /* after next regular group conversion. */ + if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Enable ADC software conversion for injected channels */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled with this function and if regular conversion + * is on going, function HAL_ADC_Stop must be used preliminarily. + * @param hadc: ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if((hadc->State != HAL_ADC_STATE_BUSY_REG) && + (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + tmpHALStatus = ADC_ConversionStop_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @brief Get ADC injected group conversion result. + * @param hadc: ADC handle + * @param InjectedRank: the converted ADC injected rank. + * This parameter can be one of the following values: + * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected + * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected + * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected + * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected + * @retval None + */ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +{ + uint32_t tmp_jdr = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + + /* Clear injected group conversion flag to have similar behaviour as */ + /* regular group: reading data register also clears end of conversion flag. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Get ADC converted value */ + switch(InjectedRank) + { + case ADC_INJECTED_RANK_4: + tmp_jdr = hadc->Instance->JDR4; + break; + case ADC_INJECTED_RANK_3: + tmp_jdr = hadc->Instance->JDR3; + break; + case ADC_INJECTED_RANK_2: + tmp_jdr = hadc->Instance->JDR2; + break; + case ADC_INJECTED_RANK_1: + default: + tmp_jdr = hadc->Instance->JDR1; + break; + } + + /* Return ADC converted value */ + return tmp_jdr; +} + +/** + * @brief Injected conversion complete callback in non blocking mode + * @param hadc: ADC handle + * @retval None + */ +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on injected group + +@endverbatim + * @{ + */ + +/** + * @brief Configures the ADC injected group and the selected channel to be + * linked to the injected group. + * @note Possibility to update parameters on the fly: + * This function initializes injected group, following calls to this + * function can be used to reconfigure some parameters of structure + * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. + * The setting of these parameters is conditioned to ADC state: + * this function must be called when ADC is not under conversion. + * @param hadc: ADC handle + * @param sConfigInjected: Structure of ADC injected group and ADC channel for + * injected group. + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +{ + HAL_StatusTypeDef tmpHALStatus = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); + + if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + } + + if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START) + { + assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Configuration of injected group sequencer: */ + /* - if scan mode is disabled, injected channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "InjectedNbrOfConversion" is discarded. */ + /* Note: Scan mode is present by hardware on this device and, if */ + /* disabled, discards automatically nb of conversions. Anyway, nb of */ + /* conversions is forced to 0x00 for alignment over all STM32 devices. */ + /* - if scan mode is enabled, injected channels sequence length is set to */ + /* parameter ""InjectedNbrOfConversion". */ + if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) + { + if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) + { + /* Clear the old SQx bits for all injected ranks */ + MODIFY_REG(hadc->Instance->JSQR , + ADC_JSQR_JL | + ADC_JSQR_JSQ4 | + ADC_JSQR_JSQ3 | + ADC_JSQR_JSQ2 | + ADC_JSQR_JSQ1 , + __ADC_JSQR_RK(sConfigInjected->InjectedChannel, + ADC_INJECTED_RANK_1, + 0x01) ); + } + /* If another injected rank than rank1 was intended to be set, and could */ + /* not due to ScanConvMode disabled, error is reported. */ + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + } + else + { + /* Since injected channels rank conv. order depends on total number of */ + /* injected conversions, selected rank must be below or equal to total */ + /* number of injected conversions to be updated. */ + if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) + { + /* Clear the old SQx bits for the selected rank */ + /* Set the SQx bits for the selected rank */ + MODIFY_REG(hadc->Instance->JSQR , + + ADC_JSQR_JL | + __ADC_JSQR_RK(ADC_JSQR_JSQ1, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) , + + __ADC_JSQR_JL(sConfigInjected->InjectedNbrOfConversion) | + __ADC_JSQR_RK(sConfigInjected->InjectedChannel, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) ); + } + else + { + /* Clear the old SQx bits for the selected rank */ + MODIFY_REG(hadc->Instance->JSQR , + + ADC_JSQR_JL | + __ADC_JSQR_RK(ADC_JSQR_JSQ1, + sConfigInjected->InjectedRank, + sConfigInjected->InjectedNbrOfConversion) , + + 0x00000000 ); + } + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + MODIFY_REG(hadc->Instance->CR2 , + ADC_CR2_JEXTEN | + ADC_CR2_JEXTSEL , + sConfigInjected->ExternalTrigInjecConv | + sConfigInjected->ExternalTrigInjecConvEdge ); + } + else + { + MODIFY_REG(hadc->Instance->CR2, + ADC_CR2_JEXTEN | + ADC_CR2_JEXTSEL , + 0x00000000 ); + } + + /* Configuration of injected group */ + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Automatic injected conversion */ + /* - Injected discontinuous mode */ + if ((__HAL_ADC_IS_ENABLED(hadc) == RESET)) + { + hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO | + ADC_CR1_JDISCEN ); + + /* Automatic injected conversion can be enabled if injected group */ + /* external triggers are disabled. */ + if (sConfigInjected->AutoInjectedConv == ENABLE) + { + if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) + { + SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + } + + /* Injected discontinuous can be enabled only if auto-injected mode is */ + /* disabled. */ + if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) + { + if (sConfigInjected->AutoInjectedConv == DISABLE) + { + SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); + } + else + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + tmpHALStatus = HAL_ERROR; + } + } + } + + /* InjectedChannel sampling time configuration */ + /* For InjectedChannels 0 to 9 */ + if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10) + { + MODIFY_REG(hadc->Instance->SMPR3, + __ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel), + __ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + } + /* For InjectedChannels 10 to 19 */ + else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20) + { + MODIFY_REG(hadc->Instance->SMPR2, + __ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel), + __ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + } + /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ + /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */ + else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX) + { + MODIFY_REG(hadc->Instance->SMPR1, + __ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel), + __ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); + } + /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */ + else + { + __ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + } + + + /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ + switch(sConfigInjected->InjectedRank) + { + case 1: + /* Set injected channel 1 offset */ + MODIFY_REG(hadc->Instance->JOFR1, + ADC_JOFR1_JOFFSET1, + sConfigInjected->InjectedOffset); + break; + case 2: + /* Set injected channel 2 offset */ + MODIFY_REG(hadc->Instance->JOFR2, + ADC_JOFR2_JOFFSET2, + sConfigInjected->InjectedOffset); + break; + case 3: + /* Set injected channel 3 offset */ + MODIFY_REG(hadc->Instance->JOFR3, + ADC_JOFR3_JOFFSET3, + sConfigInjected->InjectedOffset); + break; + case 4: + default: + MODIFY_REG(hadc->Instance->JOFR4, + ADC_JOFR4_JOFFSET4, + sConfigInjected->InjectedOffset); + break; + } + + /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ + /* and VREFINT measurement path. */ + if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || + (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) + { + SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmpHALStatus; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c new file mode 100644 index 000000000..3847a72e0 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c @@ -0,0 +1,810 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_comp.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief COMP HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the COMP peripheral: + * + Initialization and de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim +================================================================================ + ##### COMP Peripheral features ##### +================================================================================ + + [..] + The STM32L1xx device family integrates 2 analog comparators COMP1 and + COMP2: + (#) The non inverting input and inverting input can be set to GPIO pins. + Refer to "table1. COMP Inputs" below. + HAL COMP driver configures the Routing Interface (RI) to connect the + selected I/O pins to comparator input. + Caution: Comparator COMP1 and ADC cannot be used at the same time as + ADC since they share the ADC switch matrix: COMP1 non-inverting + input is routed through ADC switch matrix. Except if ADC is intented + to measure voltage on COMP1 non-inverting input: it can be performed + on ADC channel VCOMP. + + (#) The COMP output is available using HAL_COMP_GetOutputLevel(). + + (#) The COMP output can be redirected to embedded timers (TIM2, TIM3, + TIM4, TIM10). + COMP output cannot be redirected to any I/O pin. + Refer to "table 2. COMP Outputs redirection to embedded timers" below. + + (#) The comparators COMP1 and COMP2 can be combined in window mode. + In this mode, COMP2 non inverting input is used as common + non-inverting input. + + (#) The 2 comparators have interrupt capability with wake-up + from Sleep and Stop modes (through the EXTI controller): + (++) COMP1 is internally connected to EXTI Line 21 + (++) COMP2 is internally connected to EXTI Line 22 + + From the corresponding IRQ handler, the right interrupt source can be + retrieved with macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: + (++) COMP_EXTI_LINE_COMP1_EVENT + (++) COMP_EXTI_LINE_COMP2_EVENT + + (#) The comparators also offer the possibility to ouput the voltage + reference (VrefInt), used on inverting inputs, on I/O pin through + a buffer. To use it, refer to macro "__HAL_VREFINT_OUT_ENABLE()". + + +[..] Table 1. COMP Inputs for the STM32L1xx devices + +----------------------------------------------------------------------+ + | | | COMP1 | COMP2 | + |-----------------|--------------------------------|---------|---------| + | | 1/4 VREFINT | -- | OK | + | | 1/2 VREFINT | -- | OK | + | | 3/4 VREFINT | -- | OK | + | Inverting | VREFINT | OK | OK | + | input | DAC Ch1 OUT (PA4) | -- | OK | + | | DAC Ch2 OUT (PA5) | -- | OK | + | | IO: PB3 | -- | OK | + |-----------------|--------------------------------|---------|---------| + | | IO: | | | + | | PB4, 5, 6*, 7* | --- | OK | + | Non-inverting | PA0*, 1*, 2*, 3*, 4, 5, 6, 7 | OK | --- | + | input | PB0, 1, 12, 13, 14, 15 | OK | --- | + | | PC0, 1, 2, 3, 4, 5 | OK | --- | + | | PE7, 8, 9, 10 | OK | --- | + | | PF6, 7, 8, 9, 10 | OK | --- | + | | OPAMP1 output | OK | --- | + | | OPAMP2 output | OK | --- | + | | OPAMP3 output** | OK | --- | + +----------------------------------------------------------------------+ + *: Available on devices category Cat.3, Cat.4, Cat.5 only. + **: Available on devices category Cat.4 only. + + [..] Table 2. COMP Outputs redirection to embedded timers + +-----------------------------------+ + | COMP1 | COMP2 | + |-----------------|-----------------| + | | TIM2 IC4 | + | | TIM2 OCREF CLR | + | (no redirection | TIM3 IC4 | + | to timers) | TIM3 OCREF CLR | + | | TIM4 IC4 | + | | TIM4 OCREF CLR | + | | TIM10 IC1 | + +-----------------------------------+ + + + ##### How to use this driver ##### +================================================================================ + [..] + This driver provides functions to configure and program the Comparators of all STM32L1xx devices. + + To use the comparator, perform the following steps: + + (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(). + (++) Configure the comparator input I/O pin using HAL_GPIO_Init(): + - For all inputs: I/O pin in analog mode (Schmitt trigger disabled) + - Possible alternate configuration, for non-inverting inputs of comparator 2: I/O pin in floating mode (Schmitt trigger enabled). + It is recommended to use analog configuration to avoid any overconsumption around VDD/2. + (++) Enable COMP Peripheral clock using macro __COMP_CLK_ENABLE() + (++) If required enable the COMP interrupt (EXTI line Interrupt): enable + the comparator interrupt vector using HAL_NVIC_EnableIRQ(COMP_IRQn) + and HAL_NVIC_SetPriority(COMP_IRQn, xxx, xxx) functions. + + (#) Configure the comparator using HAL_COMP_Init() function: + (++) Select the inverting input (COMP2 only) + (++) Select the non-inverting input + (++) Select the output redirection to timers (COMP2 only) + (++) Select the speed mode (COMP2 only) + (++) Select the window mode (related to COMP1 and COMP2, but selected + by COMP2 only) + (++) Select the pull-up/down resistors on non-inverting input (COMP1 only) + + (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() + function + + (#) If needed, use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback() + functions to manage comparator actions (output level or events) + + (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT() + function + + (#) De-initialize the comparator using HAL_COMP_DeInit() function + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup COMP COMP + * @brief COMP HAL module driver + * @{ + */ + +#ifdef HAL_COMP_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup COMP_Private_Constants COMP Private Constants + * @{ + */ + /* Delay for COMP startup time. */ + /* Maximum delay is 10us for comparator 1 and 25us for comparator 2 in slow */ + /* mode (refer to device datasheet, parameter tSTART). */ + /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */ + /* have the minimum number of CPU cycles to fulfill this delay. */ + /* - Comparator 1: delay minimum of 320 CPU cyles. Wait loop takes 3 CPU */ + /* cycles per iteration, therefore total wait iterations */ + /* number must be initialized at 106 iterations. */ + /* - Comparator 2: delay minimum of 800 CPU cyles. Wait loop takes 3 CPU */ + /* cycles per iteration, therefore total wait iterations */ + /* number must be initialized at 266 iterations. */ +#define COMP1_START_DELAY_CPU_CYCLES ((uint32_t)106) +#define COMP2_START_DELAY_CPU_CYCLES ((uint32_t)266) + + /* Comparator status "locked": to update COMP handle state (software lock */ + /* only on COMP of STM32L1xx devices) by bitfield: */ + /* states HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_BUSY_LOCKED. */ +#define COMP_STATE_BIT_LOCK ((uint32_t) 0x00000010) + +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Functions COMP Exported Functions + * @{ + */ + +/** @defgroup COMP_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions to initialize and de-initialize comparators + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the COMP according to the specified + * parameters in the COMP_InitTypeDef and create the associated handle. + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if (hcomp->Instance == COMP1) + { + assert_param(IS_COMP_NONINVERTINGINPUTPULL(hcomp->Init.NonInvertingInputPull)); + } + else /* if (hcomp->Instance == COMP2) */ + { + assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput)); + assert_param(IS_COMP_OUTPUT(hcomp->Init.Output)); + assert_param(IS_COMP_MODE(hcomp->Init.Mode)); + assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); + } + + /* In window mode, non-inverting inputs of the 2 comparators are */ + /* connected together and are using inputs of COMP2 only. If COMP1 is */ + /* selected, this parameter is discarded. */ + if ((hcomp->Init.WindowMode == COMP_WINDOWMODE_DISABLED) || + (hcomp->Instance == COMP2) ) + { + assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput)); + } + + + /* Enable SYSCFG clock and the low level hardware to access comparators */ + if(hcomp->State == HAL_COMP_STATE_RESET) + { + /* Enable SYSCFG clock to control the routing Interface (RI) */ + __SYSCFG_CLK_ENABLE(); + + /* Init the low level hardware */ + HAL_COMP_MspInit(hcomp); + } + + /* Configuration of comparator: */ + /* - Output selection */ + /* - Inverting input selection */ + /* - Window mode */ + /* - Mode fast/slow speed */ + /* - Inverting input pull-up/down resistors */ + + /* Configuration depending on comparator instance */ + if (hcomp->Instance == COMP1) + { + MODIFY_REG(COMP->CSR, COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU, + hcomp->Init.NonInvertingInputPull ); + } + else /* if (hcomp->Instance == COMP2) */ + { + /* Note: If comparator 2 is not enabled, inverting input (parameter */ + /* "hcomp->Init.InvertingInput") is configured into function */ + /* "HAL_COMP_Start()" since inverting input selection also */ + /* enables the comparator 2. */ + /* If comparator 2 is already enabled, inverting input is */ + /* reconfigured on the fly. */ + if (__COMP_IS_ENABLED(hcomp) == RESET) + { + MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL | + COMP_CSR_WNDWE | + COMP_CSR_SPEED , + hcomp->Init.Output | + hcomp->Init.WindowMode | + hcomp->Init.Mode ); + } + else + { + MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL | + COMP_CSR_INSEL | + COMP_CSR_WNDWE | + COMP_CSR_SPEED , + hcomp->Init.Output | + hcomp->Init.InvertingInput | + hcomp->Init.WindowMode | + hcomp->Init.Mode ); + } + } + + /* Configure Routing Interface (RI) switches for comparator non-inverting */ + /* input. */ + /* Except in 2 cases: */ + /* - if non-inverting input has no selection: it can be the case for */ + /* COMP1 in window mode. */ + /* - particular case for PC3: if switch COMP1_SW1 is closed */ + /* (by macro "__HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1()" or */ + /* "__HAL_RI_SWITCH_COMP1_SW1_CLOSE()"), connection between pin PC3 */ + /* (or OPAMP3, if available) and COMP1 is done directly, without going */ + /* through ADC switch matrix. */ + if (__COMP_ROUTING_INTERFACE_TOBECONFIGURED(hcomp)) + { + if (hcomp->Instance == COMP1) + { + /* Enable the switch control mode */ + __HAL_RI_SWITCHCONTROLMODE_ENABLE(); + + /* Close the analog switch of ADC switch matrix to COMP1 (ADC */ + /* channel 26: Vcomp) */ + __HAL_RI_IOSWITCH_CLOSE(RI_IOSWITCH_VCOMP); + } + + /* Close the I/O analog switch corresponding to comparator */ + /* non-inverting input selected. */ + __HAL_RI_IOSWITCH_CLOSE(hcomp->Init.NonInvertingInput); + } + + + /* Initialize the COMP state*/ + if(hcomp->State == HAL_COMP_STATE_RESET) + { + hcomp->State = HAL_COMP_STATE_READY; + } + } + + return status; +} + + +/** + * @brief DeInitializes the COMP peripheral + * @note Deinitialization can't be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Reset configuration depending on comparator instance */ + if (hcomp->Instance == COMP1) + { + CLEAR_BIT(COMP->CSR , COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU); + } + else /* if (hcomp->Instance == COMP2) */ + { + CLEAR_BIT(COMP->CSR , COMP_CSR_OUTSEL | + COMP_CSR_WNDWE | + COMP_CSR_INSEL | + COMP_CSR_SPEED ); + } + + + /* Restore default state of Routing Interface (RI) switches for */ + /* comparator non-inverting input. */ + if (hcomp->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) + { + /* Open the I/O analog switch corresponding to comparator */ + /* non-inverting input selected. */ + __HAL_RI_IOSWITCH_OPEN(hcomp->Init.NonInvertingInput); + } + if (hcomp->Instance == COMP1) + { + /* Open the analog switch of ADC switch matrix to COMP1 (ADC */ + /* channel 26: Vcomp) */ + __HAL_RI_IOSWITCH_OPEN(RI_IOSWITCH_VCOMP); + + /* Disable the switch control mode */ + __HAL_RI_SWITCHCONTROLMODE_DISABLE(); + } + + + /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ + HAL_COMP_MspDeInit(hcomp); + + hcomp->State = HAL_COMP_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcomp); + } + + return status; +} + +/** + * @brief Initializes the COMP MSP. + * @param hcomp: COMP handle + * @retval None + */ +__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_COMP_MspInit could be implenetd in the user file + */ +} + +/** + * @brief DeInitializes COMP MSP. + * @param hcomp: COMP handle + * @retval None + */ +__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_COMP_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the COMP + start and stop actions with or without interruption on ExtI line. + +@endverbatim + * @{ + */ + +/** + * @brief Start the comparator + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t wait_loop_cycles = 0; + __IO uint32_t wait_loop_index = 0; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if(hcomp->State == HAL_COMP_STATE_READY) + { + + /* Note: For comparator 2, inverting input (parameter */ + /* "hcomp->Init.InvertingInput") is configured into this */ + /* function instead of function "HAL_COMP_Init()" since */ + /* inverting input selection also enables the comparator 2. */ + __HAL_COMP_ENABLE(hcomp); + + /* Set delay for COMP startup time */ + if (hcomp->Instance == COMP1) + { + wait_loop_cycles = COMP1_START_DELAY_CPU_CYCLES; + } + else /* if (hcomp->Instance == COMP2) */ + { + wait_loop_cycles = COMP2_START_DELAY_CPU_CYCLES; + } + + /* Delay for COMP startup time. */ + /* Delay fixed to worst case: maximum CPU frequency */ + while(wait_loop_index < wait_loop_cycles) + { + wait_loop_index++; + } + + /* Update COMP state */ + hcomp->State = HAL_COMP_STATE_BUSY; + + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Stop the comparator + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if(hcomp->State == HAL_COMP_STATE_BUSY) + { + /* Disable the selected comparator */ + __HAL_COMP_DISABLE(hcomp); + + /* Update COMP state */ + hcomp->State = HAL_COMP_STATE_READY; + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Enables the interrupt and starts the comparator + * @param hcomp: COMP handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t extiline = 0; + + status = HAL_COMP_Start(hcomp); + if(status == HAL_OK) + { + /* Check the parameter */ + assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); + + /* Get the Exti Line output configuration */ + extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + + /* Configure the rising edge */ + /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_RISING or */ + /* COMP_TRIGGERMODE_IT_RISING_FALLING. */ + if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET) + { + __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline); + } + else + { + __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline); + } + + /* Configure the falling edge */ + /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_FALLING or */ + /* COMP_TRIGGERMODE_IT_RISING_FALLING. */ + if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET) + { + __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline); + } + else + { + __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline); + } + + /* Enable Exti interrupt mode */ + __HAL_COMP_EXTI_ENABLE_IT(extiline); + /* Clear COMP Exti pending bit */ + __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + } + + return status; +} + +/** + * @brief Disable the interrupt and Stop the comparator + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the Exti Line interrupt mode */ + __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance)); + + status = HAL_COMP_Stop(hcomp); + + return status; +} + +/** + * @brief Comparator IRQ Handler + * @param hcomp: COMP handle + * @retval HAL status + */ +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) +{ + uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + + /* Check COMP Exti flag */ + if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET) + { + /* Clear COMP Exti pending bit */ + __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + + /* COMP trigger user callback */ + HAL_COMP_TriggerCallback(hcomp); + } +} + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the COMP + management functions: Lock status, comparator output level check, IRQ + callback (in case of usage of comparator with interruption on ExtI line). + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected comparator configuration. + * Caution: On STM32L1, HAL COMP lock is software lock only (not + * hardware lock as on some other STM32 devices) + * @param hcomp: COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Set lock flag */ + hcomp->State |= COMP_STATE_BIT_LOCK; + } + + return status; +} + +/** + * @brief Return the output level (high or low) of the selected comparator. + * The output level depends on the selected polarity. + * - Comparator output is low when the non-inverting input is at a lower + * voltage than the inverting input + * - Comparator output is high when the non-inverting input is at a higher + * voltage than the inverting input + * @param hcomp: COMP handle + * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH. + * + */ +uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +{ + uint32_t level = 0; + + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Read output level of the selected comparator */ + if(READ_BIT(COMP->CSR, __COMP_CSR_CMPXOUT(hcomp)) == RESET) + { + level = COMP_OUTPUTLEVEL_LOW; + } + else + { + level = COMP_OUTPUTLEVEL_HIGH; + } + + return(level); +} + +/** + * @brief Comparator callback. + * @param hcomp: COMP handle + * @retval None + */ +__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_TriggerCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the COMP state + * @param hcomp : COMP handle + * @retval HAL state + */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +{ + /* Check the COMP handle allocation */ + if(hcomp == NULL) + { + return HAL_COMP_STATE_RESET; + } + + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return hcomp->State; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_COMP_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c new file mode 100644 index 000000000..4aaa44978 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cortex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief CORTEX HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using Cortex HAL driver *** + =========================================================== + [..] + This section provide functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M3 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ========================================================================================================================== + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using Cortex HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for 1 msec interrupts. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32l1xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provide the Cortex HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c new file mode 100644 index 000000000..24fe2efd9 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c @@ -0,0 +1,339 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_crc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The CRC HAL driver can be used as follows: + + (#) Enable CRC AHB clock using __CRC_CLK_ENABLE(); + + (#) Use HAL_CRC_Accumulate() function to compute the CRC value of + a 32-bit data buffer using combination of the previous CRC value + and the new one. + + (#) Use HAL_CRC_Calculate() function to compute the CRC Value of + a new 32-bit data buffer. This function resets the CRC computation + unit before starting the computation to avoid getting wrong CRC values. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP + (+) DeInitialize CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CRC according to the specified + * parameters in the CRC_InitTypeDef and creates the associated handle. + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if(hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if(hcrc->State == HAL_CRC_STATE_RESET) + { + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the CRC peripheral. + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if(hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CRC MSP. + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Compute the 32-bit CRC value of 32-bit data buffer, + using combination of the previous CRC value and the new one. + (+) Compute the 32-bit CRC value of 32-bit data buffer, + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Computes the 32-bit CRC of 32-bit data buffer using combination + * of the previous CRC value and the new one. + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed (defined in word, 4 bytes) + * @retval 32-bit CRC + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + /* Process Locked */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Enter Data to the CRC calculator */ + for(index = 0; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @brief Computes the 32-bit CRC of 32-bit data buffer independently + * of the previous CRC value. + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC + * @param pBuffer: Pointer to the buffer containing the data to be computed + * @param BufferLength: Length of the buffer to be computed (defined in word, 4 bytes) + * @retval 32-bit CRC + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + /* Process Locked */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Enter Data to the CRC calculator */ + for(index = 0; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +{ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c new file mode 100644 index 000000000..b7dedd2df --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c @@ -0,0 +1,2111 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cryp.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief CRYP HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Cryptography (CRYP) peripheral: + * + Initialization and de-initialization functions + * + Processing functions by algorithm using polling mode + * + Processing functions by algorithm using interrupt mode + * + Processing functions by algorithm using DMA mode + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The CRYP HAL driver can be used as follows: + + (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): + (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE() + (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT()) + (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() + (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA()) + (+) Enable the DMA2 interface clock using + (++) __DMA2_CLK_ENABLE() + (+) Configure and enable two DMA Channels one for managing data transfer from + memory to peripheral (input channel) and another channel for managing data + transfer from peripheral to memory (output channel) + (+) Associate the initialized DMA handle to the CRYP DMA handle + using __HAL_LINKDMA() + (+) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream. + (++) HAL_NVIC_SetPriority() + (++) HAL_NVIC_EnableIRQ() + + (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly: + (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit + (##) The encryption/decryption key. + (##) The initialization vector (counter). It is not used ECB mode. + + (#)Three processing (encryption/decryption) functions are available: + (##) Polling mode: encryption and decryption APIs are blocking functions + i.e. they process the data and wait till the processing is finished + e.g. HAL_CRYP_AESCBC_Encrypt() + (##) Interrupt mode: encryption and decryption APIs are not blocking functions + i.e. they process the data under interrupt + e.g. HAL_CRYP_AESCBC_Encrypt_IT() + (##) DMA mode: encryption and decryption APIs are not blocking functions + i.e. the data transfer is ensured by DMA + e.g. HAL_CRYP_AESCBC_Encrypt_DMA() + + (#)When the processing function is called for the first time after HAL_CRYP_Init() + the CRYP peripheral is initialized and processes the buffer in input. + At second call, the processing function performs an append of the already + processed buffer. + When a new data block is to be processed, call HAL_CRYP_Init() then the + processing function. + + (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +#ifdef HAL_CRYP_MODULE_ENABLED + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup CRYP CRYP + * @brief CRYP HAL module driver. + * @{ + */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Defines CRYP Private Defines + * @{ + */ + +#define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions CRYP Private Functions + * @{ + */ + +static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp); +static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector); +static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key); +static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout); +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAError(DMA_HandleTypeDef *hdma); +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Functions CRYP Exported Functions + * @{ + */ + +/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRYP according to the specified parameters + in the CRYP_InitTypeDef and creates the associated handle + (+) DeInitialize the CRYP peripheral + (+) Initialize the CRYP MSP + (+) DeInitialize CRYP MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CRYP according to the specified + * parameters in the CRYP_InitTypeDef and creates the associated handle. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if(hcryp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); + + if(hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Init the low level hardware */ + HAL_CRYP_MspInit(hcryp); + } + + /* Check if AES already enabled */ + if (HAL_IS_BIT_CLR(AES->CR, AES_CR_EN)) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Set the data type*/ + MODIFY_REG(AES->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + + /* Reset CrypInCount and CrypOutCount */ + hcryp->CrypInCount = 0; + hcryp->CrypOutCount = 0; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Set the default CRYP phase */ + hcryp->Phase = HAL_CRYP_PHASE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */ + /* enabled is forbidden to avoid unpredictable AES behavior.*/ + + /* Return function status */ + return HAL_ERROR; + } + +} + +/** + * @brief DeInitializes the CRYP peripheral. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if(hcryp == NULL) + { + return HAL_ERROR; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Set the default CRYP phase */ + hcryp->Phase = HAL_CRYP_PHASE_READY; + + /* Reset CrypInCount and CrypOutCount */ + hcryp->CrypInCount = 0; + hcryp->CrypOutCount = 0; + + /* Disable the CRYP Peripheral Clock */ + __HAL_CRYP_DISABLE(); + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_CRYP_MspDeInit(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRYP MSP. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file */ +} + +/** + * @brief DeInitializes CRYP MSP. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file */ +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions + * @brief processing functions. + * +@verbatim + ============================================================================== + ##### AES processing functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Encrypt plaintext using AES algorithm in different chaining modes + (+) Decrypt cyphertext using AES algorithm in different chaining modes + [..] Three processing functions are available: + (+) Polling mode + (+) Interrupt mode + (+) DMA mode + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CRYP peripheral in AES ECB encryption mode + * then encrypt pPlainData. The cypher data are available in pCypherData + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) +{ + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Check that data aligned on u32 and Size multiple of 16*/ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Write Plain Data and Get Cypher Data */ + if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CBC encryption mode + * then encrypt pPlainData. The cypher data are available in pCypherData + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) +{ + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Write Plain Data and Get Cypher Data */ + if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CTR encryption mode + * then encrypt pPlainData. The cypher data are available in pCypherData + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) +{ + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CTR mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Write Plain Data and Get Cypher Data */ + if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES ECB decryption mode + * then decrypted pCypherData. The cypher data are available in pPlainData + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) +{ + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Write Cypher Data and Get Plain Data */ + if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES ECB decryption mode + * then decrypted pCypherData. The cypher data are available in pPlainData + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) +{ + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Write Cypher Data and Get Plain Data */ + if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CTR decryption mode + * then decrypted pCypherData. The cypher data are available in pPlainData + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) +{ + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if initialization phase has already been performed */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY)) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CTR decryption mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Write Cypher Data and Get Plain Data */ + if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Get the buffer addresses and sizes */ + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pPlainData; + hcryp->pCrypOutBuffPtr = pCypherData; + hcryp->CrypOutCount = Size; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(AES_IT_CC); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Get the last input data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Get the buffer addresses and sizes */ + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pPlainData; + hcryp->pCrypOutBuffPtr = pCypherData; + hcryp->CrypOutCount = Size; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(AES_IT_CC); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Get the last input data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Get the buffer addresses and sizes */ + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pPlainData; + hcryp->pCrypOutBuffPtr = pCypherData; + hcryp->CrypOutCount = Size; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CTR mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(AES_IT_CC); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Get the last input data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Get the buffer addresses and sizes */ + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pCypherData; + hcryp->pCrypOutBuffPtr = pPlainData; + hcryp->CrypOutCount = Size; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(AES_IT_CC); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Get the last input data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Get the buffer addresses and sizes */ + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pCypherData; + hcryp->pCrypOutBuffPtr = pPlainData; + hcryp->CrypOutCount = Size; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(AES_IT_CC); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Get the last input data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + /* Get the buffer addresses and sizes */ + hcryp->CrypInCount = Size; + hcryp->pCrypInBuffPtr = pCypherData; + hcryp->pCrypOutBuffPtr = pPlainData; + hcryp->CrypOutCount = Size; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CTR decryption mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(AES_IT_CC); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); + + /* Get the last input data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + inputaddr = (uint32_t)pPlainData; + outputaddr = (uint32_t)pCypherData; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Set the CRYP peripheral in AES ECB mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + inputaddr = (uint32_t)pPlainData; + outputaddr = (uint32_t)pCypherData; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Set the CRYP peripheral in AES CBC mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + inputaddr = (uint32_t)pPlainData; + outputaddr = (uint32_t)pCypherData; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Set the CRYP peripheral in AES CTR mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + inputaddr = (uint32_t)pCypherData; + outputaddr = (uint32_t)pPlainData; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + inputaddr = (uint32_t)pCypherData; + outputaddr = (uint32_t)pPlainData; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) + * @param Size: Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcryp); + + inputaddr = (uint32_t)pCypherData; + outputaddr = (uint32_t)pPlainData; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Set the CRYP peripheral in AES CTR mode */ + __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions + * @brief DMA callback functions. + * +@verbatim + ============================================================================== + ##### DMA callback functions ##### + ============================================================================== + [..] This section provides DMA callback functions: + (+) DMA Input data transfer complete + (+) DMA Output data transfer complete + (+) DMA error + +@endverbatim + * @{ + */ + +/** + * @brief CRYP error callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ + __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief Input transfer completed callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Output transfer completed callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler + * @brief CRYP IRQ handler. + * +@verbatim + ============================================================================== + ##### CRYP IRQ handler management ##### + ============================================================================== +[..] This section provides CRYP IRQ handler function. + +@endverbatim + * @{ + */ + +/** + * @brief This function handles CRYP interrupt request. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) +{ + /* Check if error occurred*/ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_ERR) != RESET) + { + if (__HAL_CRYP_GET_FLAG(AES_FLAG_RDERR) != RESET) + { + __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_RDERR); + } + + if (__HAL_CRYP_GET_FLAG(AES_FLAG_WRERR) != RESET) + { + __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_WRERR); + } + + if (__HAL_CRYP_GET_FLAG(AES_FLAG_CCF) != RESET) + { + __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + } + + hcryp->State= HAL_CRYP_STATE_ERROR; + /* Disable Computation Complete Interrupt */ + __HAL_CRYP_DISABLE_IT(AES_IT_CC); + __HAL_CRYP_DISABLE_IT(AES_IT_ERR); + + HAL_CRYP_ErrorCallback(hcryp); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return; + } + + /* Check if computation complete interrupt was enabled*/ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_CC) != RESET) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + + CRYP_EncryptDecrypt_IT(hcryp); + } +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CRYP state. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL state + */ +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) +{ + return hcryp->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRYP_Private_Functions + * @{ + */ + +/** + * @brief IT function called under interruption context to continue encryption or decryption + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Get the last Output data adress */ + outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + + /* Read the Output block from the Output Register */ + *(uint32_t*)(outputaddr) = AES->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = AES->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = AES->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = AES->DOUTR; + + hcryp->pCrypOutBuffPtr += 16; + hcryp->CrypOutCount -= 16; + + /* Check if all input text is encrypted or decrypted */ + if(hcryp->CrypOutCount == 0) + { + /* Disable Computation Complete Interrupt */ + __HAL_CRYP_DISABLE_IT(AES_IT_CC); + __HAL_CRYP_DISABLE_IT(AES_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + } + else /* Process the rest of input text */ + { + /* Get the last Intput data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + } + return HAL_OK; +} +/** + * @brief DMA CRYP Input Data process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable the DMA transfer for input request */ + CLEAR_BIT(AES->CR, AES_CR_DMAINEN); + + /* Call input data transfer complete callback */ + HAL_CRYP_InCpltCallback(hcryp); +} + +/** + * @brief DMA CRYP Output Data process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit + in the DMACR register */ + CLEAR_BIT(AES->CR, AES_CR_DMAOUTEN); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(); + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Call output data transfer complete callback */ + HAL_CRYP_OutCpltCallback(hcryp); +} + +/** + * @brief DMA CRYP communication error callback. + * @param hdma: DMA handle + * @retval None + */ +static void CRYP_DMAError(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + hcryp->State= HAL_CRYP_STATE_ERROR; + HAL_CRYP_ErrorCallback(hcryp); +} + +/** + * @brief Writes the Key in Key registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Key: Pointer to Key buffer + * @note Key must be written as little endian. + * If Key pointer points at address n, + * n[15:0] contains key[96:127], + * (n+4)[15:0] contains key[64:95], + * (n+8)[15:0] contains key[32:63] and + * (n+12)[15:0] contains key[0:31] + * @retval None + */ +static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key) +{ + uint32_t keyaddr = (uint32_t)Key; + + AES->KEYR3 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES->KEYR2 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES->KEYR1 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES->KEYR0 = __REV(*(uint32_t*)(keyaddr)); +} + +/** + * @brief Writes the InitVector/InitCounter in IV registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param InitVector: Pointer to InitVector/InitCounter buffer + * @note Init Vector must be written as little endian. + * If Init Vector pointer points at address n, + * n[15:0] contains Vector[96:127], + * (n+4)[15:0] contains Vector[64:95], + * (n+8)[15:0] contains Vector[32:63] and + * (n+12)[15:0] contains Vector[0:31] + * @retval None + */ +static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) +{ + uint32_t ivaddr = (uint32_t)InitVector; + + AES->IVR3 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + AES->IVR2 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + AES->IVR1 = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4; + AES->IVR0 = __REV(*(uint32_t*)(ivaddr)); +} + +/** + * @brief Process Data: Writes Input data in polling mode and reads the output data + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input: Pointer to the Input buffer + * @param Ilength: Length of the Input buffer, must be a multiple of 16. + * @param Output: Pointer to the returned buffer + * @param Timeout: Specify Timeout value + * @retval None + */ +static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + uint32_t index = 0; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + for(index=0; (index < Ilength); index += 16) + { + /* Write the Input block in the Data Input register */ + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + AES->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(AES->SR, AES_SR_CCF)) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Change state */ + hcryp->State = HAL_CRYP_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + return HAL_TIMEOUT; + } + } + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); + + /* Read the Output block from the Data Output Register */ + *(uint32_t*)(outputaddr) = AES->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = AES->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = AES->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = AES->DOUTR; + outputaddr+=4; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the DMA configuration and start the DMA transfer + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param inputaddr: address of the Input buffer + * @param Size: Size of the Input buffer, must be a multiple of 16. + * @param outputaddr: address of the Output buffer + * @retval None + */ +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) +{ + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + /* Set the DMA error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; + /* Set the DMA error callback */ + hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; + + /* Enable the DMA In DMA Stream */ + HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&AES->DINR, Size/4); + + /* Enable the DMA Out DMA Stream */ + HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&AES->DOUTR, outputaddr, Size/4); + + /* Enable In and Out DMA requests */ + SET_BIT(AES->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(); +} + +/** + * @} + */ + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CRYP_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c new file mode 100644 index 000000000..66db6dbb6 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cryp_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief CRYPEx HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Cryptography (CRYP) extension peripheral: + * + Computation completed callback. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +#ifdef HAL_CRYP_MODULE_ENABLED + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup CRYPEx CRYPEx + * @brief CRYP HAL Extended module driver. + * @{ + */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions + * @{ + */ + + +/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions. + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides callback functions: + (+) Computation completed. + +@endverbatim + * @{ + */ + +/** + * @brief Computation completed callbacks. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_ComputationCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CRYP_MODULE_ENABLED */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c new file mode 100644 index 000000000..5746fec58 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c @@ -0,0 +1,963 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dac.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Digital to Analog Converter (DAC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * + @verbatim + ============================================================================== + ##### DAC Peripheral features ##### + ============================================================================== + [..] + *** DAC Channels *** + ==================== + [..] + The device integrates two 12-bit Digital Analog Converters that can + be used independently or simultaneously (dual mode): + (#) DAC channel1 with DAC_OUT1 (PA4) as output + (#) DAC channel2 with DAC_OUT2 (PA5) as output + + *** DAC Triggers *** + ==================== + [..] + Digital to Analog conversion can be non-triggered using DAC_Trigger_None + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] + Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. + The used pin (GPIOx_Pin9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7, TIM9 + (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) + + (#) Software using DAC_Trigger_Software + + *** DAC Buffer mode feature *** + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable, the output buffer use + sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + [..] + (@) Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + *** DAC wave generation feature *** + =================================== + [..] + Both DAC channels can be used to generate + (#) Noise wave + (#) Triangle wave + + *** DAC data format *** + ======================= + [..] + The DAC data format can be: + (#) 8-bit right alignment using DAC_ALIGN_8B_R + (#) 12-bit left alignment using DAC_ALIGN_12B_L + (#) 12-bit right alignment using DAC_ALIGN_12B_R + + *** DAC data value to voltage correspondence *** + ================================================ + [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + DAC_OUTx = VREF+ * DOR / 4095 + with DOR is the Data Output Register + VEF+ is the input voltage reference (refer to the device datasheet) + e.g. To set DAC_OUT1 to 0.7V, use + Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA1 request can be generated when an external trigger (but not + a software trigger) occurs if DMA1 requests are enabled using + HAL_DAC_Start_DMA() + [..] + DMA1 requests are mapped as following: + (#) DAC channel1 : mapped on DMA1 channel2 which must be + already configured + (#) DAC channel2 : mapped on DMA1 channel3 which must be + already configured + + -@- For Dual mode and specific signal (Triangle and noise) generation please + refer to Extension Features Driver description + + + ##### How to use this driver ##### + ============================================================================== + [..] + (+) DAC APB clock must be enabled to get write access to DAC + registers using HAL_DAC_Init() + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. + (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() + (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function. + (+) Stop the DAC peripheral using HAL_DAC_Stop() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DAC_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2 + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. + HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DAC_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DAC_DMAUnderrunCallbackCh2 + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() + + *** DAC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DAC HAL driver. + + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral + (+) __HAL_DAC_DISABLE : Disable the DAC peripheral + (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags + (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status + + [..] + (@) You can refer to the DAC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup DAC DAC + * @brief DAC driver modules + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Functions DAC Exported Functions + * @{ + */ + +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) +{ + /* Check DAC handle */ + if(hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + if(hdac->State == HAL_DAC_STATE_RESET) + { + /* Init the low level hardware */ + HAL_DAC_MspInit(hdac); + } + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) +{ + /* Check DAC handle */ + if(hdac == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_DAC_MspDeInit(hdac); + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DAC MSP. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the DAC MSP. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + if(Channel == DAC_CHANNEL_1) + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + } + else + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN2; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + { + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); + } + } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param pData: The destination peripheral Buffer address. + * @param Length: The length of data to be transferred from memory to DAC peripheral + * @param Alignment: Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + if(Channel == DAC_CHANNEL_1) + { + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Case of use of channel 1 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + } + else + { + /* Set the DMA transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; + + /* Set the DMA half transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; + + /* Set the DMA error callback for channel2 */ + hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; + + /* Enable the selected DAC channel2 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Case of use of channel 2 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + } + + /* Enable the DMA Stream */ + if(Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } + else + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + } + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); + + /* Disable the Peripharal */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA Channel */ + /* Channel1 is used */ + if(Channel == DAC_CHANNEL_1) + { + status = HAL_DMA_Abort(hdac->DMA_Handle1); + } + else /* Channel2 is used for */ + { + status = HAL_DMA_Abort(hdac->DMA_Handle2); + } + + /* Check if DMA Channel effectively disabled */ + if(status != HAL_OK) + { + /* Update ADC state machine to error */ + hdac->State = HAL_DAC_STATE_ERROR; + } + else + { + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + if(Channel == DAC_CHANNEL_1) + { + return hdac->Instance->DOR1; + } + else + { + return hdac->Instance->DOR2; + } +} + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Check underrun flag of DAC channel 1 */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to chanel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + + /* Error callback */ + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + } + + /* Check underrun flag of DAC channel 2 */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel2 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + + /* Error callback */ + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); + } +} + +/** + * @brief Conversion complete callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels. + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig: DAC configuration structure. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); + /* Configure for the selected DAC channel: buffer output, trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; + /* Disable wave generation */ + DAC->CR &= ~(DAC_CR_WAVE1 << Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment: Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + if(Channel == DAC_CHANNEL_1) + { + tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment); + } + else + { + tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment); + } + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DAC state. + (+) Check the DAC Errors. + +@endverbatim + * @{ + */ + +/** + * @brief return the DAC state + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL state + */ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) +{ + /* Return DAC state */ + return hdac->State; +} + + +/** + * @brief Return the DAC error code + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval DAC Error Code + */ +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +{ + return hdac->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DAC_ConvCpltCallbackCh1(hdac); + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DAC_ErrorCallbackCh1(hdac); + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c new file mode 100644 index 000000000..39f6b0134 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dac_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of DAC extension peripheral: + * + Extended features functions + * + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : + Use HAL_DACEx_DualGetValue() to get digital data to be converted and use + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. + (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup DACEx DACEx + * @brief DAC driver modules + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Functions DACEx Exported Functions + * @{ + */ + +/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + (+) Get result of dual mode conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) +{ + uint32_t tmp = 0; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16; + + /* Returns the DAC channel data output register value */ + return tmp; +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * DAC_CHANNEL_1 / DAC_CHANNEL_2 + * @param Amplitude: Select max triangle amplitude. + * This parameter can be one of the following values: + * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 + * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 + * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 + * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 + * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 + * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 + * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 + * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 + * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 + * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 + * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the selected wave generation for the selected DAC channel */ + hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * DAC_CHANNEL_1 / DAC_CHANNEL_2 + * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: + * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the selected wave generation for the selected DAC channel */ + hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the specified data holding register value for dual DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Alignment: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_8B_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)hdac->Instance; + tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Conversion complete callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DACEx_Private_Functions DACEx Private Functions + * @{ + */ +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DACEx_ConvCpltCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DACEx_ErrorCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c new file mode 100644 index 000000000..f71b6c78c --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c @@ -0,0 +1,707 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dma.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Channel Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants +* @{ +*/ +#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions +* @{ +*/ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral handle */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + return HAL_ERROR; + } + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0; + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Group2 I/O operation functions + * @brief I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Process locked */ + __HAL_LOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + + return HAL_OK; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Process locked */ + __HAL_LOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); + + /* Enable the Half transfer complete interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + + /* Enable the transfer Error interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * + * @note After disabling a DMA Channel, a check for wait until the DMA Channel is + * effectively disabled is added. If a Channel is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Channel will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + uint32_t tickstart = 0x00; + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Check if the DMA Channel is effectively disabled */ + while((hdma->Instance->CCR & DMA_CCR_EN) != 0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel: Specifies the DMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0x00; + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + } + else + { + /* Half Transfer Complete flag */ + temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + { + if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) + { + /* Clear the transfer error flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + } + + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY_HALF; + /* Process unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Transfer Error Interrupt management ***************************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); + + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + + /* Half Transfer Complete Interrupt management ******************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_READY_HALF; + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Transfer Complete Interrupt management ***********************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable the transfer complete interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } +} +} + +/** + * @} + */ + +/** @defgroup DMA_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions +* @{ +*/ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @} + */ + + +#endif /* HAL_DMA_MODULE_ENABLED */ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c new file mode 100644 index 000000000..4e77a1384 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c @@ -0,0 +1,490 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + FLASH Interface configuration + * + FLASH Memory Programming + * + Interrupts and flags management + * + * @verbatim + + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the Flash + memory of all STM32L1xx devices. + + (#) FLASH Memory Programming functions: this group includes all + needed functions to erase and program the main memory: + (++) Lock and Unlock the Flash interface. + (++) Erase function: Erase Page. + (++) Program functions: Fast Word and Half Page(should be + executed from internal SRAM). + + (#) DATA EEPROM Programming functions: this group includes all + needed functions to erase and program the DATA EEPROM memory: + (++) Lock and Unlock the DATA EEPROM interface. + (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase + Double Word (should be executed from internal SRAM). + (++) Program functions: Fast Program Byte, Fast Program Half-Word, + FastProgramWord, Program Byte, Program Half-Word, + Program Word and Program Double-Word (should be executed + from internal SRAM). + + (#) FLASH Option Bytes Programming functions: this group includes + all needed functions to: + (++) Lock and Unlock the Flash Option bytes. + (++) Set/Reset the write protection. + (++) Set the Read protection Level. + (++) Set the BOR level. + (++) Program the user option Bytes. + (++) Launch the Option Bytes loader. + (++) Get the Write protection. + (++) Get the read protection status. + (++) Get the BOR level. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Wait for last FLASH operation according to its status + (++) Get error flag status by calling HAL_GetErrorCode() + + (#) FLASH Interface configuration functions: this group includes + the management of following features: + (++) Enable/Disable the RUN PowerDown mode. + (++) Enable/Disable the SLEEP PowerDown mode. + + (#) FLASH Peripheral State methods: this group includes + the management of following features: + (++) Wait for the FLASH operation + (++) Get the specific FLASH error flag + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the 64 bit Read Access. + (+) Enable/Disable the Flash power-down + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + + [..] The FLASH Memory Programming functions, includes the following functions: + (+) HAL_FLASH_Unlock(void); + (+) HAL_FLASH_Lock(void); + (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page or program data. + (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + + [..] The FLASH_Option Bytes Programming_functions, includes the following functions: + (+) HAL_FLASH_OB_Unlock(void); + (+) HAL_FLASH_OB_Lock(void); + (+) HAL_FLASH_OB_Launch(void); + (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); + (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control + register access. + (#) Call the following functions to program the desired option bytes. + (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); + (#) Once all needed option bytes to be programmed are correctly written, call the + HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended + to protect the option Bytes against possible unwanted operations). + + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Internal_Variables FLASH Internal Variables + * @{ + */ + +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef ProcFlash; + + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Functions FLASH Exported functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ +/** + * @brief Program word at a specified address + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Check the parameters */ + assert_param(IS_TYPEPROGRAMFLASH(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Program word (32-bit) at a specified address.*/ + *(__IO uint32_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + + return status; +} + +/** + * @brief Program word at a specified address with interrupt enabled. + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Check the parameters */ + assert_param(IS_TYPEPROGRAMFLASH(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); + + ProcFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + ProcFlash.Address = Address; + + if(TypeProgram == TYPEPROGRAM_WORD) + { + /*Program word (32-bit) at a specified address.*/ + *(__IO uint32_t *)Address = Data; + } + + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + + return status; +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Pages Erase: Sector which has been erased + * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Pagess Erase: Sector number which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET) + { + /* Unlocking FLASH_PECR register access*/ + if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + { + FLASH->PEKEYR = FLASH_PEKEY1; + FLASH->PEKEYR = FLASH_PEKEY2; + } + + /* Unlocking the program memory access */ + FLASH->PRGKEYR = FLASH_PRGKEY1; + FLASH->PRGKEYR = FLASH_PRGKEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the PRGLOCK Bit to lock the program memory access */ + SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET) + { + /* Unlocking FLASH_PECR register access*/ + if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + { + /* Unlocking FLASH_PECR register access*/ + FLASH->PEKEYR = FLASH_PEKEY1; + FLASH->PEKEYR = FLASH_PEKEY2; + } + + /* Unlocking the option bytes block access */ + FLASH->OPTKEYR = FLASH_OPTKEY1; + FLASH->OPTKEYR = FLASH_OPTKEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the option bytes block access */ + SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to lauch the option byte loading */ + SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be: + * @arg FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg FLASH_ERROR_SIZE: FLASH Size error flag + * @arg FLASH_ERROR_OPTV: Option validity error flag + * @arg FLASH_ERROR_OPTVUSR: Option UserValidity Error flag (available only Cat.3, Cat.4 and Cat.5 devices) + * @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) + */ +FLASH_ErrorTypeDef HAL_FLASH_GetError(void) +{ + return ProcFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c new file mode 100644 index 000000000..3f46d15fa --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c @@ -0,0 +1,1952 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + FLASH Interface configuration + * + FLASH Memory Erasing + * + DATA EEPROM Programming/Erasing + * + Option Bytes Programming + * + Interrupts management + * + * @verbatim + ============================================================================== + ##### Flash peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other products, the FLASH interface for STM32L1xx + devices contains the following additional features + (+) Erase functions + (+) DATA_EEPROM memory management + (+) BOOT option bit configuration + (+) PCROP protection for all sectors + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32L1xx. It includes: + (+) Full DATA_EEPROM erase and program management + (+) Boot activation + (+) PCROP protection configuration and control for all pages + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void FLASH_SetErrorCode(void); +static void FLASH_ErasePage(uint32_t PageAddress); + +static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState); +static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState); +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState); +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState); +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState); +#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ +static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR); +static uint8_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); +static uint8_t FLASH_OB_GetBOR(void); +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState); +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT); +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data); + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASH Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) HAL_FLASHEx_Erase: return only when erase has been done + (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback is called with parameter + 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + +/** + * @brief Erase the specified FLASH memory Pages + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError: pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFF means that all the sectors have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t index = 0; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFF; + + /* Check the parameters */ + assert_param(IS_NBPAGES(pEraseInit->NbPages)); + assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + + /* Erase by sector by sector to be done*/ + for(index = pEraseInit->PageAddress; index < ((pEraseInit->NbPages * FLASH_PAGE_SIZE)+ pEraseInit->PageAddress); index += FLASH_PAGE_SIZE) + { + FLASH_ErasePage(index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the ERASE Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *PageError = index; + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + + return status; +} + +/** + * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); + + /* Check the parameters */ + assert_param(IS_NBPAGES(pEraseInit->NbPages)); + assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + + ProcFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + ProcFlash.NbPagesToErase = pEraseInit->NbPages; + ProcFlash.Page = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_ErasePage(pEraseInit->PageAddress); + + return status; +} + +/** + * @} + */ + + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control + register access. + (#) Call following function to program the desired option bytes. + (++) HAL_FLASHEx_OBProgram: + - To Enable/Disable the desired sector write protection. + - To set the desired read Protection Level. + - To configure the user option Bytes: IWDG, STOP and the Standby. + - To Set the BOR level. + (#) Once all needed option bytes to be programmed are correctly written, call the + HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended + to protect the option Bytes against possible unwanted operations). + + [..] Proprietary code Read Out Protection (PcROP): + (#) The PcROP sector is selected by using the same option bytes as the Write + protection (nWRPi bits). As a result, these 2 options are exclusive each other. + (#) In order to activate the PcROP (change the function of the nWRPi option bits), + the SPRMOD option bit must be activated. + (#) The active value of nWRPi bits is inverted when PCROP mode is active, this + means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" + is read/write protected. + (#) To activate PCROP mode for Flash sector(s), you need to call the following function: + (++) HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected + (++) HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection + (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices. + +@endverbatim + * @{ + */ + +/** + * @brief Program option bytes + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /*Write protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected Sector*/ + status = FLASH_OB_WRPConfig(pOBInit, ENABLE); + } + else + { + /* Disable of Write protection on the selected Sector*/ + status = FLASH_OB_WRPConfig(pOBInit, DISABLE); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + return status; + } + } + + /* Read protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDPConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + return status; + } + } + + /* USER configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NORST, + pOBInit->USERConfig & OB_STDBY_NORST); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + return status; + } + } + + /* BOR Level configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BORConfig(pOBInit->BORLevel); + } + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + + /*Get WRP1*/ + pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1); + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + /*Get WRP2*/ + pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2); + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + /*Get WRP3*/ + pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3); + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + /*Get WRP4*/ + pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4); + +#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + +} + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +/** + * @brief Program option bytes + * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. + * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OBEX(pAdvOBInit->OptionType)); + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + + /* Cat2 & Cat3 devices only */ + /*Program PCROP option byte*/ + if ((pAdvOBInit->OptionType & OBEX_PCROP) == OBEX_PCROP) + { + /* Check the parameters */ + assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); + if (pAdvOBInit->PCROPState == PCROPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE); + if (status != HAL_OK) + { + return status; + } + } + else + { + /*Disable of Write protection on the selected Sector*/ + status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE); + if (status != HAL_OK) + { + return status; + } + } + } + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + /* Cat4 & Cat5 devices only */ + /*Program BOOT config option byte*/ + if ((pAdvOBInit->OptionType & OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG) + { + status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); + } + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + return status; +} + +/** + * @brief Get the OBEX byte configuration + * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. + * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + + pAdvOBInit->OptionType = OBEX_PCROP; + + /*Get PCROP state */ + pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD); + + /*Get PCROP protected sector from 0 to 31 */ + pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1; + + #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + + /*Get PCROP protected sector from 32 to 63 */ + pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2; + + #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + pAdvOBInit->OptionType = OBEX_BOOTCONFIG; + + /*Get Boot config OB*/ + pAdvOBInit->BootConfig = (FLASH->OBR & 0x80000000) >> 24; + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +} + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + +/** + * @brief Select the Protection Mode (SPRMOD). + * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices + * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t tmp1 = 0; + uint32_t tmp2 = 0; + uint8_t optiontmp = 0; + uint16_t optiontmp2 = 0; + + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Mask RDP Byte */ + optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); + + /* Update Option Byte */ + optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); + + /* calculate the option byte to write */ + tmp1 = (uint16_t)(~(optiontmp2 )); + tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); + + if(status == HAL_OK) + { + /* program PCRop */ + OB->RDP = tmp2; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Return the Read protection operation Status */ + return status; +} + +/** + * @brief Deselect the Protection Mode (SPRMOD). + * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices + * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t tmp1 = 0; + uint32_t tmp2 = 0; + uint8_t optiontmp = 0; + uint16_t optiontmp2 = 0; + + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Mask RDP Byte */ + optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); + + /* Update Option Byte */ + optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); + + /* calculate the option byte to write */ + tmp1 = (uint16_t)(~(optiontmp2 )); + tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); + + if(status == HAL_OK) + { + /* program PCRop */ + OB->RDP = tmp2; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Return the Read protection operation Status */ + return status; +} + +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions + * @brief DATA EEPROM Programming functions + * +@verbatim + =============================================================================== + ##### DATA EEPROM Programming functions ##### + =============================================================================== + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access + and Flash program erase control register access. + (#) Call the desired function to erase or program data. + (#) Call the HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access + and Flash program erase control register access(recommended + to protect the DATA_EEPROM against possible unwanted operation). + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the data memory and FLASH_PECR register access. + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void) +{ + if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + { + /* Unlocking the Data memory and FLASH_PECR register access*/ + FLASH->PEKEYR = FLASH_PEKEY1; + FLASH->PEKEYR = FLASH_PEKEY2; + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Locks the Data memory and FLASH_PECR register access. + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) +{ + /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ + SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK); + + return HAL_OK; +} + +/** + * @brief Erase a word in data memory. + * @param Address: specifies the address to be erased. + * @param TypeErase: Indicate the way to erase at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @note To correctly run this function, the DATA_EEPROM_Unlock() function + * must be called before. + * Call the DATA_EEPROM_Lock() to the data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TYPEPROGRAMDATA(TypeErase)); + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeErase == TYPEERASEDATA_WORD) + { + /* Write 00000000h to valid address in the data memory */ + *(__IO uint32_t *) Address = 0x00000000; + } + + if(TypeErase == TYPEERASEDATA_HALFWORD) + { + /* Write 0000h to valid address in the data memory */ + *(__IO uint16_t *) Address = (uint16_t)0x0000; + } + + if(TypeErase == TYPEERASEDATA_BYTE) + { + /* Write 00h to valid address in the data memory */ + *(__IO uint8_t *) Address = (uint8_t)0x00; + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program word at a specified address + * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function + * must be called before. + * Call the HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @note The function HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before + * this function to configure the Fixed Time Programming. + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASHEx_Type_Program_Data + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ + +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Check the parameters */ + assert_param(IS_TYPEPROGRAMDATA(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeProgram == TYPEPROGRAMDATA_FASTBYTE) + { + /*Program word (8-bit) at a specified address.*/ + FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data); + } + + if(TypeProgram == TYPEPROGRAMDATA_FASTHALFWORD) + { + /*Program word (16-bit) at a specified address.*/ + FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data); + } + + if(TypeProgram == TYPEPROGRAMDATA_FASTWORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data); + } + + if(TypeProgram == TYPEPROGRAMDATA_WORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data); + } + + if(TypeProgram == TYPEPROGRAMDATA_HALFWORD) + { + /*Program word (16-bit) at a specified address.*/ + FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data); + } + + if(TypeProgram == TYPEPROGRAMDATA_BYTE) + { + /*Program word (8-bit) at a specified address.*/ + FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + + return status; +} + +/** + * @brief Enable DATA EEPROM fixed Time programming (2*Tprog). + * @retval None + */ +void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void) +{ + SET_BIT(FLASH->PECR, FLASH_PECR_FTDW); +} + +/** + * @brief Disables DATA EEPROM fixed Time programming (2*Tprog). + * @retval None + */ +void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) +{ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Private_Functions FLASHEx Private functions + * @{ + */ + +/* +============================================================================== + ##### FLASH STATIC functions ##### +============================================================================== +*/ + +/* +============================================================================== + FLASH +============================================================================== +*/ + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + { + ProcFlash.ErrorCode = FLASH_ERROR_WRP; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + { + ProcFlash.ErrorCode |= FLASH_ERROR_PGA; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) + { + ProcFlash.ErrorCode |= FLASH_ERROR_SIZE; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) + { + ProcFlash.ErrorCode |= FLASH_ERROR_OPTV; + } + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + ProcFlash.ErrorCode |= FLASH_ERROR_RD; + } +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) + { + ProcFlash.ErrorCode |= FLASH_ERROR_OPTVUSR; + } +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +} + +/** + * @brief Erases a specified page in program memory. + * @param PageAddress: The page address in program memory to be erased. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of 256 bytes). + * @retval None + */ +static void FLASH_ErasePage(uint32_t PageAddress) +{ + /* Set the ERASE bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + /* Set PROG bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /* Write 00000000h to the first word of the program page to erase */ + *(__IO uint32_t *)PageAddress = 0x00000000; +} + + +/* +============================================================================== + OPTIONS BYTES +============================================================================== +*/ +/** + * @brief Enables or disables the read out protection. + * @note To correctly run this function, the HAL_FLASH_OB_Unlock() function + * must be called before. + * @param OB_RDP: specifies the read protection level. + * This parameter can be: + * @arg OB_RDP_LEVEL0: No protection + * @arg OB_RDP_LEVEL1: Read protection of the memory + * @arg OB_RDP_LEVEL2: Chip protection + * + * !!!Warning!!! When enabling OB_RDP_LEVEL2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp1 = 0, tmp2 = 0, sprmod = 0; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + + /* According to errata sheet, DocID022054 Rev 5, par2.1.5 + Before setting Level0 in the RDP register, check that the current level is not equal to Level0. + If the current level is not equal to Level0, Level0 can be activated. + If the current level is Level0 then the RDP register must not be written again with Level0. */ + tmp1 = (uint32_t)(OB->RDP & 0x000000FF); + + if ((tmp1 == OB_RDP_LEVEL0) && (OB_RDP == OB_RDP_LEVEL0)) + { + /*current level is Level0 then the RDP register must not be written again with Level0. */ + status = HAL_ERROR; + } + else + { + /* Mask SPRMOD bit */ + sprmod = (uint32_t)(OB->RDP & 0x00000100); + + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* calculate the option byte to write */ + tmp1 = (~((uint32_t)(OB_RDP | sprmod))); + tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)(OB_RDP | sprmod))); + + if(status == HAL_OK) + { + /* program read protection level */ + OB->RDP = tmp2; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + + /* Return the Read protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH brownout reset threshold level Option Byte. + * @param OB_BOR: Selects the brownout reset threshold level. + * This parameter can be one of the following values: + * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD + * power supply reaches the PDR(Power Down Reset) threshold (1.5V) + * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply + * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply + * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply + * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply + * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0, tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(OB_BOR)); + + /* Get the User Option byte register */ + tmp1 = (FLASH->OBR & (FLASH_OBR_USER)) >> 16; + + /* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/ + tmp = (uint32_t)~((OB_BOR | tmp1)) << 16; + tmp |= (OB_BOR | tmp1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Write the BOR Option Byte */ + OB->USER = tmp; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @retval The FLASH User Option Bytes. + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> POSITION_VAL(FLASH_OBR_USER)); +} + +/** + * @brief Checks whether the FLASH Read out Protection Status is set or not. + * @retval FLASH ReadOut Protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + return (uint8_t)(FLASH->OBR & FLASH_OBR_RDPRT); +} + +/** + * @brief Returns the FLASH BOR level. + * @retval The FLASH User Option Bytes. + */ +static uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the BOR level */ + return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> POSITION_VAL(FLASH_OBR_BOR_LEV)); +} + +/** + * @brief Write protects the desired pages of the first 64KB of the Flash. + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * contains WRP parameters. + * @param NewState: new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval HAL_StatusTypeDef + */ +static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* WRP for sector between 0 to 31 */ + if (pOBInit->WRPSector0To31 != 0) + { + FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState); + } + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + /* Pages for Cat3, Cat4 & Cat5 devices*/ + /* WRP for sector between 32 to 63 */ + if (pOBInit->WRPSector32To63 != 0) + { + FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState); + } + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + /* Pages for devices with FLASH >= 256KB*/ + /* WRP for sector between 64 to 95 */ + if (pOBInit->WRPSector64To95 != 0) + { + FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState); + } + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + + /* Pages for Cat5 devices*/ + /* WRP for sector between 96 to 127 */ + if (pOBInit->WRPSector96To127 != 0) + { + FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState); + } + +#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + + /* Return the write protection operation Status */ + return status; +} + +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) +/** + * @brief Enables the read/write protection (PCROP) of the desired + * sectors. + * @note This function can be used only for Cat2 & Cat3 devices + * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains PCROP parameters. + * @param NewState: new state of the specified FLASH Pages read/Write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState) +{ + HAL_StatusTypeDef status = HAL_OK; + FunctionalState pcropstate = DISABLE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Invert state to use same function of WRP */ + if (NewState == DISABLE) + { + pcropstate = ENABLE; + } + + if(status == HAL_OK) + { + /* Pages for Cat2 devices*/ + /* PCROP for sector between 0 to 31 */ + if (pAdvOBInit->PCROPSector0To31 != 0) + { + FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate); + } + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + + /* Pages for Cat3 devices*/ + /* WRP for sector between 32 to 63 */ + if (pAdvOBInit->PCROPSector32To63 != 0) + { + FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate); + } + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + + /* Return the write protection operation Status */ + return status; +} +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +/** + * @brief Write protects the desired pages of the first 128KB of the Flash. + * @param WRP1OrPCROP1: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg value between OB_WRP1/PCROP1_PAGES0TO15 and OB_WRP1/PCROP1_PAGES496TO511 + * @arg OB_WRP1/PCROP1_ALLPAGES + * @param NewState: new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState) +{ + uint32_t wrp01data = 0, wrp23data = 0; + + uint32_t tmp1 = 0, tmp2 = 0; + + if (NewState != DISABLE) + { + wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01)); + wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 | OB->WRP23))); + tmp1 = (uint32_t)(~(wrp01data) << 16)|(wrp01data); + OB->WRP01 = tmp1; + + tmp2 = (uint32_t)(~(wrp23data) << 16)|(wrp23data); + OB->WRP23 = tmp2; + } + else + { + wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01)); + wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 & OB->WRP23))); + + tmp1 = (uint32_t)((~wrp01data) << 16)|(wrp01data); + OB->WRP01 = tmp1; + + tmp2 = (uint32_t)((~wrp23data) << 16)|(wrp23data); + OB->WRP23 = tmp2; + } +} + +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Enable Write protects the desired pages of the second 128KB of the Flash. + * @note This function can be used only for Cat3, Cat4 & Cat5 devices. + * @param WRP2OrPCROP2: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg value between OB_WRP2/PCROP2_PAGES512TO527 and OB_WRP2/PCROP2_PAGES1008TO1023 + * @arg OB_WRP2/PCROP2_ALLPAGES + * @param NewState: new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState) +{ + uint32_t wrp45data = 0, wrp67data = 0; + + uint32_t tmp1 = 0, tmp2 = 0; + + if (NewState != DISABLE) + { + wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45)); + wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 | OB->WRP67))); + tmp1 = (uint32_t)(~(wrp45data) << 16)|(wrp45data); + OB->WRP45 = tmp1; + + tmp2 = (uint32_t)(~(wrp67data) << 16)|(wrp67data); + OB->WRP67 = tmp2; + } + else + { + wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45)); + wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 & OB->WRP67))); + + tmp1 = (uint32_t)((~wrp45data) << 16)|(wrp45data); + OB->WRP45 = tmp1; + + tmp2 = (uint32_t)((~wrp67data) << 16)|(wrp67data); + OB->WRP67 = tmp2; + } +} +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Enable Write protects the desired pages of the third 128KB of the Flash. + * @note This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD & Cat5 devices. + * @param WRP3: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg value between WRP3_PAGES1024TO1039 and OB_WRP3_PAGES1520TO1535 + * @arg OB_WRP3_ALLPAGES + * @param NewState: new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState) +{ + uint32_t wrp89data = 0, wrp1011data = 0; + + uint32_t tmp1 = 0, tmp2 = 0; + + if (NewState != DISABLE) + { + wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89)); + wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16 | OB->WRP1011))); + tmp1 = (uint32_t)(~(wrp89data) << 16)|(wrp89data); + OB->WRP89 = tmp1; + + tmp2 = (uint32_t)(~(wrp1011data) << 16)|(wrp1011data); + OB->WRP1011 = tmp2; + } + else + { + wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89)); + wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16 & OB->WRP1011))); + + tmp1 = (uint32_t)((~wrp89data) << 16)|(wrp89data); + OB->WRP89 = tmp1; + + tmp2 = (uint32_t)((~wrp1011data) << 16)|(wrp1011data); + OB->WRP1011 = tmp2; + } +} +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Enable Write protects the desired pages of the Fourth 128KB of the Flash. + * @note This function can be used only for Cat5 devices. + * @param WRP4: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg value between OB_WRP4_PAGES1536TO1551 and OB_WRP4_PAGES2032TO2047 + * @arg OB_WRP4_ALLPAGES + * @param NewState: new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState) +{ + uint32_t wrp1213data = 0, wrp1415data = 0; + + uint32_t tmp1 = 0, tmp2 = 0; + + if (NewState != DISABLE) + { + wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213)); + wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16 | OB->WRP1415))); + tmp1 = (uint32_t)(~(wrp1213data) << 16)|(wrp1213data); + OB->WRP1213 = tmp1; + + tmp2 = (uint32_t)(~(wrp1415data) << 16)|(wrp1415data); + OB->WRP1415 = tmp2; + } + else + { + wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213)); + wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16 & OB->WRP1415))); + + tmp1 = (uint32_t)((~wrp1213data) << 16)|(wrp1213data); + OB->WRP1213 = tmp1; + + tmp2 = (uint32_t)((~wrp1415data) << 16)|(wrp1415data); + OB->WRP1415 = tmp2; + } +} +#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param OB_IWDG: Selects the WDG mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software WDG selected + * @arg OB_IWDG_HW: Hardware WDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NORST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NORST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0, tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Get the User Option byte register */ + tmp1 = (FLASH->OBR & FLASH_OBR_BOR_LEV) >> 16; + + /* Calculate the user option byte to write */ + tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16); + tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Write the User Option Byte */ + OB->USER = tmp; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Return the Option Byte program Status */ + return status; +} + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Configures to boot from Bank1 or Bank2. + * @param OB_BOOT: select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * For more information, please refer to AN2606 from www.st.com. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0, tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_OB_BOOT_BANK(OB_BOOT)); + + /* Get the User Option byte register and BOR Level*/ + tmp1 = (FLASH->OBR & (FLASH_OBR_nRST_STDBY | FLASH_OBR_nRST_STOP | FLASH_OBR_IWDG_SW | FLASH_OBR_BOR_LEV)) >> 16; + + /* Calculate the option byte to write */ + tmp = (uint32_t)~(OB_BOOT | tmp1) << 16; + tmp |= (OB_BOOT | tmp1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Write the BOOT Option Byte */ + OB->USER = tmp; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* Return the Option Byte program Status */ + return status; +} + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/* +============================================================================== + DATA +============================================================================== +*/ + +/** + * @brief Write a Byte at a specified address in data memory. + * @param Address: specifies the address to be written. + * @param Data: specifies the data to be written. + * @note This function assumes that the is data word is already erased. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + uint32_t tmp = 0, tmpaddr = 0; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clear the FTDW bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); + +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + /* Possible only on Cat1 devices */ + if(Data != (uint8_t)0x00) + { + /* If the previous operation is completed, proceed to write the new Data */ + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + else + { + tmpaddr = Address & 0xFFFFFFFC; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + } +#else /*!Cat1*/ + /* If the previous operation is completed, proceed to write the new Data */ + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Writes a half word at a specified address in data memory. + * @param Address: specifies the address to be written. + * @param Data: specifies the data to be written. + * @note This function assumes that the is data word is already erased. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + uint32_t tmp = 0, tmpaddr = 0; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clear the FTDW bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); + +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + /* Possible only on Cat1 devices */ + if(Data != (uint16_t)0x0000) + { + /* If the previous operation is completed, proceed to write the new data */ + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + else + { + if((Address & 0x3) != 0x3) + { + tmpaddr = Address & 0xFFFFFFFC; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + } + else + { + HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); + HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); + } + } +#else /* !Cat1 */ + /* If the previous operation is completed, proceed to write the new data */ + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Programs a word at a specified address in data memory. + * @param Address: specifies the address to be written. + * @param Data: specifies the data to be written. + * @note This function assumes that the is data word is already erased. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clear the FTDW bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); + + /* If the previous operation is completed, proceed to program the new data */ + *(__IO uint32_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Write a Byte at a specified address in data memory without erase. + * @param Address: specifies the address to be written. + * @param Data: specifies the data to be written. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + uint32_t tmp = 0, tmpaddr = 0; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + if(Data != (uint8_t) 0x00) + { + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + } + else + { + tmpaddr = Address & 0xFFFFFFFC; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + } +#else /* Not Cat1*/ + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Writes a half word at a specified address in data memory without erase. + * @param Address: specifies the address to be written. + * @param Data: specifies the data to be written. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + uint32_t tmp = 0, tmpaddr = 0; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { +#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) + if(Data != (uint16_t)0x0000) + { + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + else + { + if((Address & 0x3) != 0x3) + { + tmpaddr = Address & 0xFFFFFFFC; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); + status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); + } + else + { + HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); + HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); + } + } +#else /* Not Cat1*/ + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Programs a word at a specified address in data memory without erase. + * @param Address: specifies the address to be written. + * @param Data: specifies the data to be written. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint32_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + /* Return the Write Status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @brief Interrupts functions + * +@verbatim + ============================================================================== + ##### Interrupts functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t temp; + + /* If the program operation is completed, disable the PROG Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /* If the erase operation is completed, disable the ERASE Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /*Nb of sector to erased can be decreased*/ + ProcFlash.NbPagesToErase--; + + /* Check if there are still sectors to erase*/ + if(ProcFlash.NbPagesToErase != 0) + { + temp = ProcFlash.Page; + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(temp); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); + + /*Increment sector number*/ + temp = ProcFlash.Page + FLASH_PAGE_SIZE; + ProcFlash.Page = ProcFlash.Page + FLASH_PAGE_SIZE; + FLASH_ErasePage(temp); + } + else + { + /*No more sectors to Erase, user callback can be called.*/ + /*Reset Sector and stop Erase sectors procedure*/ + ProcFlash.Page = temp = 0xFFFFFFFF; + ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(temp); + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + } + else + { + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(ProcFlash.Address); + } + ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + } + + /* Check FLASH operation error flags */ + if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) + { + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /*return the faulty sector*/ + temp = ProcFlash.Page; + ProcFlash.Page = 0xFFFFFFFF; + } + else + { + /*retrun the faulty address*/ + temp = ProcFlash.Address; + } + + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); + + /*Stop the procedure ongoing*/ + ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Disable End of FLASH Operation interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + + /* Disable Error source interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + } + +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Internal_Functions FLASH Internal function + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout: maximum flash operationtimeout + * @retval HAL status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c new file mode 100644 index 000000000..b743f19f1 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c @@ -0,0 +1,545 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash_ramfunc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief FLASH RAMFUNC driver. + * This file provides a Flash firmware functions which should be + * executed from internal SRAM + * + * @verbatim + + *** ARM Compiler *** + -------------------- + [..] RAM functions are defined using the toolchain options. + Functions that are be executed in RAM should reside in a separate + source module. Using the 'Options for File' dialog you can simply change + the 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + Options for Target' dialog. + + *** ICCARM Compiler *** + ----------------------- + [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + + *** GNU Compiler *** + -------------------- + [..] RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". + +@endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHRamfunc FLASHRamfunc + * @brief FLASH functions executed from RAM + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASHRamfunc_Exported_Functions FLASH RAM Exported Functions + * +@verbatim + =============================================================================== + ##### ramfunc functions ##### + =============================================================================== + [..] + This subsection provides a set of functions that should be executed from RAM + transfers. + +@endverbatim + * @{ + */ + +/** @defgroup FLASHRamfunc_Exported_Functions_Group1 FLASH RAM Peripheral features functions + * @{ + */ + +/** + * @brief Enable the power down mode during RUN mode. + * @note This function can be used only when the user code is running from Internal SRAM. + * @retval None + */ +__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) +{ + /* Enable the Power Down in Run mode*/ + __HAL_FLASH_POWER_DOWN_ENABLE(); + + return HAL_OK; +} + + +/** + * @brief Disable the power down mode during RUN mode. + * @note This function can be used only when the user code is running from Internal SRAM. + * @retval None + */ +__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) +{ + /* Disable the Power Down in Run mode*/ + __HAL_FLASH_POWER_DOWN_DISABLE(); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup FLASHRamfunc_Exported_Functions_Group2 FLASH RAM Programming and erasing operation functions + * +@verbatim +@endverbatim + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Erases a specified 2 page in program memory in parallel. + * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. + * To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * @param Page_Address1: The page address in program memory to be erased in + * the first Bank (BANK1). This parameter should be between FLASH_BASE + * and FLASH_BANK1_END. + * @param Page_Address2: The page address in program memory to be erased in + * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE + * and FLASH_BANK2_END. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of 256 bytes). + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. + */ +__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* If the previous operation is completed, proceed to erase the page */ + + /* Set the PARALLBANK bit */ + FLASH->PECR |= FLASH_PECR_PARALLBANK; + + /* Set the ERASE bit */ + FLASH->PECR |= FLASH_PECR_ERASE; + + /* Set PROG bit */ + FLASH->PECR |= FLASH_PECR_PROG; + + /* Write 00000000h to the first word of the first program page to erase */ + *(__IO uint32_t *)Page_Address1 = 0x00000000; + /* Write 00000000h to the first word of the second program page to erase */ + *(__IO uint32_t *)Page_Address2 = 0x00000000; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ + FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); + FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); + FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Programs 2 half page in program memory in parallel. + * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. + * @param Address1: specifies the first address to be written in the first bank + * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE). + * @param pBuffer1: pointer to the buffer containing the data to be written + * to the first half page in the first bank. + * @param Address2: specifies the second address to be written in the second bank + * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE). + * @param pBuffer2: pointer to the buffer containing the data to be written + * to the second half page in the second bank. + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * @note Half page write is possible only from SRAM. + * @note If there are more than 32 words to write, after 32 words another + * Half Page programming operation starts and has to be finished. + * @note A half page is written to the program memory only if the first + * address to load is the start address of a half page (multiple of 128 + * bytes) and the 31 remaining words to load are in the same half page. + * @note During the Program memory half page write all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @note If a PGAERR is set during a Program memory half page write, the + * complete write operation is aborted. Software should then reset the + * FPRG and PROG/DATA bits and restart the write operation from the + * beginning. + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. + */ +__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) +{ + uint32_t count = 0; + + HAL_StatusTypeDef status = HAL_OK; + + /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) + This bit prevents the interruption of multicycle instructions and therefore + will increase the interrupt latency. of Cortex-M3. */ + SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* If the previous operation is completed, proceed to program the new + half page */ + FLASH->PECR |= FLASH_PECR_PARALLBANK; + FLASH->PECR |= FLASH_PECR_FPRG; + FLASH->PECR |= FLASH_PECR_PROG; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + if(status == HAL_OK) + { + /* Write the first half page directly with 32 different words */ + while(count < 32) + { + *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *(pBuffer1++); + count ++; + } + count = 0; + + /* Write the second half page directly with 32 different words */ + while(count < 32) + { + *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *(pBuffer2++); + count ++; + } + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + } + /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ + FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); + FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); + FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); + } + + SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Return the Write Status */ + return status; +} +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief Programs a half page in program memory. + * @param Address: specifies the address to be written. + * @param pBuffer: pointer to the buffer containing the data to be written to + * the half page. + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @note Half page write is possible only from SRAM. + * @note If there are more than 32 words to write, after 32 words another + * Half Page programming operation starts and has to be finished. + * @note A half page is written to the program memory only if the first + * address to load is the start address of a half page (multiple of 128 + * bytes) and the 31 remaining words to load are in the same half page. + * @note During the Program memory half page write all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @note If a PGAERR is set during a Program memory half page write, the + * complete write operation is aborted. Software should then reset the + * FPRG and PROG/DATA bits and restart the write operation from the + * beginning. + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. + */ +__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) +{ + uint32_t count = 0; + + HAL_StatusTypeDef status = HAL_OK; + + /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) + This bit prevents the interruption of multicycle instructions and therefore + will increase the interrupt latency. of Cortex-M3. */ + SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* if the previous operation is completed, proceed to program the new + half page */ + FLASH->PECR |= FLASH_PECR_FPRG; + FLASH->PECR |= FLASH_PECR_PROG; + + /* Write one half page directly with 32 different words */ + while(count < 32) + { + *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *(pBuffer++); + count ++; + } + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* if the write operation is completed, disable the PROG and FPRG bits */ + FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); + FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); + } + + SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Return the Write Status */ + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHRamfunc_Exported_Functions_Group3 FLASH RAM DATA EEPROM functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Erase a double word in data memory. + * @param Address: specifies the address to be erased. + * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function + * must be called before. + * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @note Data memory double word erase is possible only from SRAM. + * @note A double word is erased to the data memory only if the first address + * to load is the start address of a double word (multiple of 8 bytes). + * @note During the Data memory double word erase, all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. + */ + +__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) + This bit prevents the interruption of multicycle instructions and therefore + will increase the interrupt latency. of Cortex-M3. */ + SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* If the previous operation is completed, proceed to erase the next double word */ + /* Set the ERASE bit */ + FLASH->PECR |= FLASH_PECR_ERASE; + + /* Set DATA bit */ + FLASH->PECR |= FLASH_PECR_DATA; + + /* Write 00000000h to the 2 words to erase */ + *(__IO uint32_t *)Address = 0x00000000; + Address += 4; + *(__IO uint32_t *)Address = 0x00000000; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the ERASE and DATA bits */ + FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); + FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); + } + + SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Return the erase status */ + return status; +} + +/** + * @brief Write a double word in data memory without erase. + * @param Address: specifies the address to be written. + * @param Data: specifies the data to be written. + * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function + * must be called before. + * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @note Data memory double word write is possible only from SRAM. + * @note A data memory double word is written to the data memory only if the + * first address to load is the start address of a double word (multiple + * of double word). + * @note During the Data memory double word write, all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. + */ +__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) + This bit prevents the interruption of multicycle instructions and therefore + will increase the interrupt latency. of Cortex-M3. */ + SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* If the previous operation is completed, proceed to program the new data*/ + FLASH->PECR |= FLASH_PECR_FPRG; + FLASH->PECR |= FLASH_PECR_DATA; + + /* Write the 2 words */ + *(__IO uint32_t *)Address = (uint32_t) Data; + Address += 4; + *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); + + /* If the write operation is completed, disable the FPRG and DATA bits */ + FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); + FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); + } + + SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; + + /* Return the Write Status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHRamfunc_Private_Functions FLASH RAM Private Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout: maximum flash operationtimeout + * @retval HAL status + */ +static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00)) + { + Timeout--; + } + + if(Timeout == 0x00 ) + { + return HAL_TIMEOUT; + } + + if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || +#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) + { + return HAL_ERROR; + } + + /* If there is an error flag set */ + return HAL_OK; +} + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c new file mode 100644 index 000000000..1623eaaf5 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c @@ -0,0 +1,540 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_gpio.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral’s alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure + (++) If alternate mode is selected, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#define GPIO_MODE ((uint32_t)0x00000003) +#define EXTI_MODE ((uint32_t)0x10000000) +#define GPIO_MODE_IT ((uint32_t)0x00010000) +#define GPIO_MODE_EVT ((uint32_t)0x00020000) +#define RISING_EDGE ((uint32_t)0x00100000) +#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_NUMBER ((uint32_t)16) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t temp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for (position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if (iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + GPIOx->AFR[position >> 3] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; + + /* In case of Output or Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); + SET_BIT(temp, (GET_GPIO_INDEX(GPIOx)) << (4 * (position & 0x03))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + SET_BIT(temp, iocurrent); + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + SET_BIT(temp, iocurrent); + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + SET_BIT(temp, iocurrent); + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + SET_BIT(temp, iocurrent); + } + EXTI->FTSR = temp; + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for (position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if (iocurrent == ioposition) + { + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floting Mode */ + CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); + + /* Configure the default Alternate Function in current IO */ + CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + + /* Configure the default value for IO Speed */ + CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + + /* Configure the default value IO Output Type */ + CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; + + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2)); + + + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Configure the External Interrupt or event for the current IO */ + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); + + /* Clear EXTI line configuration */ + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_BIT_RESET: to clear the port pin + * @arg GPIO_BIT_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + +/** + * @brief Toggles the specified GPIO pin + * @param GPIOx: where x can be (A..Gdepending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, +* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. +* @note The configuration of the locked GPIO pins can no longer be modified +* until the next reset. +* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices +* @param GPIO_Pin: specifies the port bit to be locked. +* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + SET_BIT(tmp, GPIO_Pin); + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin: Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback + * @param GPIO_Pin: Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c new file mode 100644 index 000000000..8f227dc75 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c @@ -0,0 +1,3635 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_i2c.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Channel + (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx Channel + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_TIMEOUT_FLAG ((uint32_t)35) /* 35 ms */ +#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /* 10 s */ + +#define I2C_MIN_PCLK_FREQ ((uint32_t)2000000) /* 2 MHz*/ +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout); + +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and create the associated handle. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange = 0; + uint32_t pclk1 = 0; + + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if(hi2c->State == HAL_I2C_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + } + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* The minimum allowed frequency is 2 MHz */ + if(pclk1 < I2C_MIN_PCLK_FREQ) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disble the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2C peripheral. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if(hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->State = HAL_I2C_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief I2C MSP Init. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2C MSP DeInit + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(Size > 0) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Write data to DR */ + hi2c->Instance->DR = (*pData++); + Size--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*pData++); + Size--; + } + } + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + if(Size == 1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if(Size == 2) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(Size > 0) + { + if(Size <= 3) + { + /* One byte */ + if(Size == 1) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + /* Two bytes */ + else if(Size == 2) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + } + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(Size > 0) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Write data to DR */ + hi2c->Instance->DR = (*pData++); + Size--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*pData++); + Size--; + } + } + + /* Wait until AF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while(Size > 0) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + { + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + } + + /* Wait until STOP flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + if(hi2c->XferCount == 1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + else if(hi2c->XferCount == 2) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in no-blocking mode with DMA + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Set the I2C DMA transfert complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); + + /* Send Slave Address */ + if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in no-blocking mode with DMA + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Set the I2C DMA transfert complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); + + /* Send Slave Address */ + if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + if(Size == 1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Set the I2C DMA transfert complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* If 7bit addressing mode is selected */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in no-blocking mode with DMA + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Set the I2C DMA transfert complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + while(Size > 0) + { + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Write data to DR */ + hi2c->Instance->DR = (*pData++); + Size--; + + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + { + /* Write data to DR */ + hi2c->Instance->DR = (*pData++); + Size--; + } + } + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + if(Size == 1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + else if(Size == 2) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while(Size > 0) + { + if(Size <= 3) + { + /* One byte */ + if(Size== 1) + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + /* Two bytes */ + else if(Size == 2) + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + /* Wait until BTF flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + } + else + { + /* Wait until RXNE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*pData++) = hi2c->Instance->DR; + Size--; + } + } + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + if(hi2c->XferCount == 1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + else if(hi2c->XferCount == 2) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Set the I2C DMA transfert complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + hi2c->pBuffPtr = pData; + hi2c->XferSize = Size; + hi2c->XferCount = Size; + + /* Set the I2C DMA transfert complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + if(Size == 1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param Trials: Number of trials + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart = 0, I2C_Trials = 1; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET) && \ + (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && \ + (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + }while(I2C_Trials++ < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Master mode selected */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == SET) + { + /* I2C in mode Transmitter -----------------------------------------------*/ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ + (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) + { + I2C_MasterTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ + (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) + { + I2C_MasterReceive_BTF(hi2c); + } + } + } + /* Slave mode selected */ + else + { + /* ADDR set --------------------------------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT)) == SET)) + { + I2C_Slave_ADDR(hi2c); + } + /* STOPF set --------------------------------------------------------------*/ + else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT)) == SET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ + (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ + (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) + { + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == RESET) && \ + (hi2c->XferCount == 0) && \ + (hi2c->State == HAL_I2C_STATE_BUSY_TX)) + { + I2C_Slave_AF(hi2c); + } + else + { + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && \ + (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Disable EVT, BUF and ERR interrupts */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + HAL_I2C_ErrorCallback(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callbacks. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callbacks. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback can be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callbacks. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callbacks. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callbacks. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callbacks. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief I2C error callbacks. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ + __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the I2C state. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->State; +} + +/** + * @brief Return the I2C error code + * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. +* @retval I2C Error Code +*/ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @addtogroup I2C_Private_Functions + * @{ + */ + + +/** + * @brief Handle TXE flag for Master + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + + if(hi2c->XferCount == 0) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + else + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmp = 0; + + tmp = hi2c->XferCount; + if(tmp > 3) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if((tmp == 2) || (tmp == 3)) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount == 3) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if(hi2c->XferCount == 2) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } + else + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->XferCount != 0) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + return HAL_OK; +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + return HAL_OK; +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_SlaveRxCpltCallback(hi2c); + + return HAL_OK; +} + +/** + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_SlaveTxCpltCallback(hi2c); + + return HAL_OK; +} + +/** + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) +{ + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param MemAddSize: Size of internal memory address + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +{ + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* If Memory address size is 8Bit */ + if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Wait until BTF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0; + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MasterTxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Wait until AF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0; + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_SlaveTxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C master receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Disable Last DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0; + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MasterRxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Wait until STOPF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0; + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_SlaveRxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C Memory Write process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Wait until BTF flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0; + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MemTxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C Memory Read process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Disable Last DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0; + + /* Wait until BUSY flag is reset */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + HAL_I2C_ErrorCallback(hi2c); + } + else + { + HAL_I2C_MemRxCpltCallback(hi2c); + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma: DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferCount = 0; + + hi2c->State = HAL_I2C_STATE_READY; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + HAL_I2C_ErrorCallback(hi2c); +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag: specifies the I2C flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag: specifies the I2C flag to check. + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c new file mode 100644 index 000000000..1506745f6 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c @@ -0,0 +1,1384 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_i2s.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2S HAL driver can be used as follow: + + (#) Declare a I2S_HandleTypeDef handle structure. + (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: + (##) Enable the SPIx interface clock. + (##) I2S pins configuration: + (+++) Enable the clock for the I2S GPIOs. + (+++) Configure these I2S pins as alternate function. + (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() + and HAL_I2S_Receive_IT() APIs). + (+++) Configure the I2Sx interrupt priority. + (+++) Enable the NVIC I2S IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() + and HAL_I2S_Receive_DMA() APIs: + (+++) Declare a DMA handle structure for the Tx/Rx Channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Channel. + (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Channel. + + (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity + using HAL_I2S_Init() function. + + -@- The specific I2S interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. + -@- Make sure that either: + (+@) External clock source is configured after setting correctly + the define constant HSE_VALUE in the stm32l1xx_hal_conf.h file. + + (#) Three mode of operations are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() + (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) Pause the DMA Transfer using HAL_I2S_DMAPause() + (+) Resume the DMA Transfer using HAL_I2S_DMAResume() + (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + + *** I2S HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in USART HAL driver. + + (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts + (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts + (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + + [..] + (@) You can refer to the I2S HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S HAL module driver + * @{ + */ + +#ifdef HAL_I2S_MODULE_ENABLED +#if defined(STM32L100xC) || \ + defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \ + defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || \ + defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMAError(DMA_HandleTypeDef *hdma); +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2S_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Sx peripheral in simplex mode: + + (+) User must Implement HAL_I2S_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2S_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Standard + (++) Data Format + (++) MCLK Output + (++) Audio frequency + (++) Polarity + + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx periperal. + @endverbatim + * @{ + */ + +/** + * @brief Initializes the I2S according to the specified parameters + * in the I2S_InitTypeDef and create the associated handle. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0, i2sclk = 0; + + /* Check the I2S handle allocation */ + if(hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_MODE(hi2s->Init.Mode)); + assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); + assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + + if(hi2s->State == HAL_I2S_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); + } + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) + { + i2sodd = (uint32_t)0; + i2sdiv = (uint32_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) *******************/ + if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the source clock value: based on System Clock value */ + i2sclk = HAL_RCC_GetSysClockFreq(); + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); + } + + /* Remove the flatting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint32_t)(tmp & (uint32_t)1); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint32_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint32_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + /* And configure the I2S with the I2S_InitStruct values */ + MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\ + SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\ + (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\ + hi2s->Init.Standard | hi2s->Init.DataFormat |\ + hi2s->Init.CPOL)); + + /* Write to SPIx I2SPR register the computed value */ + hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State= HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2S peripheral + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if(hi2s == NULL) + { + return HAL_ERROR; + } + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* Disable the I2S Peripheral Clock */ + __HAL_I2S_DISABLE(hi2s); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief I2S MSP Init + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2S MSP DeInit + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2S data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2S_Transmit() + (++) HAL_I2S_Receive() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2S_Transmit_IT() + (++) HAL_I2S_Receive_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2S_Transmit_DMA() + (++) HAL_I2S_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2S_TxCpltCallback() + (++) HAL_I2S_RxCpltCallback() + (++) HAL_I2S_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout: Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->pTxBuffPtr = pData; + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + while(hi2s->TxXferCount > 0) + { + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + } + + /* Wait until TXE flag is set, to confirm the end of the transcation */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + /* Wait until Busy flag is reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout: Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate + * in continouse way and as the I2S is not disabled at the end of the I2S transaction. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->pRxBuffPtr = pData; + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Receive data */ + while(hi2s->RxXferCount > 0) + { + /* Wait until RXNE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + hi2s->RxXferCount--; + } + + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pTxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Enable TXE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to the Receive data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation + * between Master and Slave otherwise the I2S interrupt should be optimized. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pRxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + /* Enable TXE and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to the Transmit data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pTxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); + } + else + { + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + } + + /* Set the I2S Tx DMA Half transfert complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; + + /* Set the I2S Tx DMA transfert complete callback */ + hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; + + /* Set the DMA error callback */ + hi2s->hdmatx->XferErrorCallback = I2S_DMAError; + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Tx request is already enabled */ + if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) + { + /* Enable Tx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData: a 16-bit pointer to the Receive data buffer. + * @param Size: number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { + hi2s->pRxBuffPtr = pData; + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); + } + else + { + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + } + + + /* Set the I2S Rx DMA Half transfert complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; + + /* Set the I2S Rx DMA transfert complete callback */ + hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; + + /* Set the DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2S_DMAError; + + /* Check if Master Receiver mode is selected */ + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Check if the I2S Rx request is already enabled */ + if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) + { + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + return HAL_BUSY; + } +} + +/** + * @brief Pauses the audio stream playing from the Media. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Disable the I2S DMA Tx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Disable the I2S DMA Rx request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Resumes the audio stream playing from the Media. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* Enable the I2S DMA Tx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } + else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* Enable the I2S DMA Rx request */ + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* If the I2S peripheral is still not enabled, enable it */ + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Resumes the audio stream playing from the Media. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Disable the I2S Tx/Rx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Abort the I2S DMA Channel tx */ + if(hi2s->hdmatx != NULL) + { + /* Disable the I2S DMA channel */ + __HAL_DMA_DISABLE(hi2s->hdmatx); + HAL_DMA_Abort(hi2s->hdmatx); + } + /* Abort the I2S DMA Channel rx */ + if(hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA channel */ + __HAL_DMA_DISABLE(hi2s->hdmarx); + HAL_DMA_Abort(hi2s->hdmarx); + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief This function handles I2S interrupt request. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2ssr = hi2s->Instance->SR; + + /* I2S in mode Receiver ------------------------------------------------*/ + if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) && + ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) + { + I2S_Receive_IT(hi2s); + return; + } + + /* I2S in mode Tramitter -----------------------------------------------*/ + if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + { + I2S_Transmit_IT(hi2s); + return; + } + + /* I2S interrupt error -------------------------------------------------*/ + if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) + { + /* I2S Overrun error interrupt occured ---------------------------------*/ + if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + + /* I2S Underrun error interrupt occured --------------------------------*/ + if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + + /* I2S Frame format error interrupt occured --------------------------*/ + if((i2ssr & I2S_FLAG_FRE) == I2S_FLAG_FRE) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE); + } + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + /* Call the Error Callback */ + HAL_I2S_ErrorCallback(hi2s); + } +} + +/** + * @brief Tx Transfer Half completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2S error callbacks + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ + __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2S state + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL state + */ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +{ + return hi2s->State; +} + +/** + * @brief Return the I2S error code + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval I2S Error Code + */ +HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +{ + return hi2s->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/** + * @brief DMA I2S transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + + hi2s->TxXferCount = 0; + hi2s->State = HAL_I2S_STATE_READY; + } + HAL_I2S_TxCpltCallback(hi2s); +} + +/** + * @brief DMA I2S transmit process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_I2S_TxHalfCpltCallback(hi2s); +} + +/** + * @brief DMA I2S receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + hi2s->RxXferCount = 0; + hi2s->State = HAL_I2S_STATE_READY; + } + HAL_I2S_RxCpltCallback(hi2s); +} + +/** + * @brief DMA I2S receive process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_I2S_RxHalfCpltCallback(hi2s); +} + +/** + * @brief DMA I2S communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMAError(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Disable Rx and Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + hi2s->TxXferCount = 0; + hi2s->RxXferCount = 0; + + hi2s->State= HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + HAL_I2S_ErrorCallback(hi2s); +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Transmit data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + + if(hi2s->TxXferCount == 0) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + HAL_I2S_TxCpltCallback(hi2s); + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s: I2S handle + * @retval None + */ +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) +{ + /* Receive data */ + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + hi2s->RxXferCount--; + + if(hi2s->RxXferCount == 0) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + HAL_I2S_RxCpltCallback(hi2s); + } +} + + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param Flag: Flag checked + * @param Status: Value of the flag expected + * @param Timeout: Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Set the I2S State ready */ + hi2s->State= HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Set the I2S State ready */ + hi2s->State= HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ +#endif /* STM32L100xC || + STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\ + STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE ||\\ + STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ +#endif /* HAL_I2S_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c new file mode 100644 index 000000000..de6eceb70 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c @@ -0,0 +1,1571 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_irda.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief IRDA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the IrDA SIR ENDEC block (IrDA): + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The IRDA HAL driver can be used as follows: + + (#) Declare a IRDA_HandleTypeDef handle structure. + (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API: + (##) Enable the USARTx interface clock. + (##) IRDA pins configuration: + (+++) Enable the clock for the IRDA GPIOs. + (+++) Configure these IRDA pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() + and HAL_IRDA_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() + and HAL_IRDA_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler + and Mode(Receiver/Transmitter) in the hirda Init structure. + + (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_IRDA_MspInit() API. + + -@@- The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() + (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback + + *** IRDA HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IRDA HAL driver. + + (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral + (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral + (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not + (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag + (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt + (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt + + [..] + (@) You can refer to the IRDA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup IRDA IRDA + * @brief HAL IRDA module driver + * @{ + */ + +#ifdef HAL_IRDA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Constants IRDA Private Constants + * @{ + */ +#define IRDA_TIMEOUT_VALUE 22000 +#define IRDA_DR_MASK_U16_7DATABITS (uint16_t)0x007F +#define IRDA_DR_MASK_U16_8DATABITS (uint16_t)0x00FF +#define IRDA_DR_MASK_U16_9DATABITS (uint16_t)0x01FF + +#define IRDA_DR_MASK_U8_7DATABITS (uint8_t)0x7F +#define IRDA_DR_MASK_U8_8DATABITS (uint8_t)0xFF + + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ +static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in IrDA mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible IRDA frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | IRDA frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may + not be rejected. The receiver set up time should be managed by software. The IrDA physical layer + specification specifies a minimum of 10 ms delay between transmission and + reception (IrDA is a half duplex protocol). + (++) Mode: Receiver/transmitter modes + (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode. + + [..] + The HAL_IRDA_Init() function follows IRDA configuration procedures (details for the procedures + are available in reference manual (RM0038)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and create the associated handle. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if(hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the IRDA instance parameters */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + /* Check the IRDA mode parameter in the IRDA handle */ + assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode)); + + if(hirda->State == HAL_IRDA_STATE_RESET) + { + /* Init the low level hardware */ + HAL_IRDA_MspInit(hirda); + } + + hirda->State = HAL_IRDA_STATE_BUSY; + + /* Disable the IRDA peripheral */ + __HAL_IRDA_DISABLE(hirda); + + /* Set the IRDA communication parameters */ + IRDA_SetConfig(hirda); + + /* In IrDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN)); + CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + + /* Enable the IRDA peripheral */ + __HAL_IRDA_ENABLE(hirda); + + /* Set the prescaler */ + MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); + + /* Configure the IrDA mode */ + MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode); + + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_IREN); + + /* Initialize the IRDA state*/ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->State= HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the IRDA peripheral + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if(hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + hirda->State = HAL_IRDA_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_IRDA_DISABLE(hirda); + + /* DeInit the low level hardware */ + HAL_IRDA_MspDeInit(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->State = HAL_IRDA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief IRDA MSP Init. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ + __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspInit can be implemented in the user file + */ +} + +/** + * @brief IRDA MSP DeInit. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ + __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions + * @brief IRDA Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the IRDA data transfers. + + [..] + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_IRDA_ErrorCallback() user callback will be executed when a communication + error is detected + + (#) Blocking mode APIs are : + (++) HAL_IRDA_Transmit() + (++) HAL_IRDA_Receive() + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_IRDA_Transmit_IT() + (++) HAL_IRDA_Receive_IT() + (++) HAL_IRDA_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_IRDA_Transmit_DMA() + (++) HAL_IRDA_Receive_DMA() + (++) HAL_IRDA_DMAPause() + (++) HAL_IRDA_DMAResume() + (++) HAL_IRDA_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_IRDA_TxHalfCpltCallback() + (++) HAL_IRDA_TxCpltCallback() + (++) HAL_IRDA_RxHalfCpltCallback() + (++) HAL_IRDA_RxCpltCallback() + (++) HAL_IRDA_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hirda->State; + if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + while(hirda->TxXferCount > 0) + { + if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) + { + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pData; + WRITE_REG(hirda->Instance->DR,(*tmp & IRDA_DR_MASK_U16_9DATABITS)); + if(hirda->Init.Parity == IRDA_PARITY_NONE) + { + pData +=2; + } + else + { + pData +=1; + } + } + else + { + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + WRITE_REG(hirda->Instance->DR, (*pData++ & IRDA_DR_MASK_U8_8DATABITS)); + } + hirda->TxXferCount--; + } + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hirda->State; + if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + /* Check the remain data to be received */ + while(hirda->RxXferCount > 0) + { + if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) + { + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pData ; + if(hirda->Init.Parity == IRDA_PARITY_NONE) + { + *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS); + pData +=2; + } + else + { + *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS); + pData +=1; + } + } + else + { + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if(hirda->Init.Parity == IRDA_PARITY_NONE) + { + *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS); + } + else + { + *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS); + } + } + hirda->RxXferCount--; + } + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non-blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + uint32_t tmp = 0; + + tmp = hirda->State; + if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + + /* Enable the IRDA Parity Error Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non-blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + uint32_t tmp = 0; + + tmp = hirda->State; + if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + + /* Enable the IRDA Data Register not empty Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); + + /* Enable the IRDA Parity Error Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non-blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hirda->State; + if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; + + /* Set the IRDA DMA half transfert complete callback */ + hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmatx->XferErrorCallback = IRDA_DMAError; + + /* Enable the IRDA transmit DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hirda->State; + if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; + + /* Set the IRDA DMA half transfert complete callback */ + hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmarx->XferErrorCallback = IRDA_DMAError; + + /* Enable the DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + /* Disable the UART DMA Rx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + /* Disable the UART DMA Tx & Rx requests */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + /* Enable the UART DMA Rx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + /* Enable the UART DMA Tx & Rx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Disable the UART Tx/Rx DMA requests */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA tx channel */ + if(hirda->hdmatx != NULL) + { + HAL_DMA_Abort(hirda->hdmatx); + } + /* Abort the UART DMA rx channel */ + if(hirda->hdmarx != NULL) + { + HAL_DMA_Abort(hirda->hdmarx); + } + + hirda->State = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles IRDA interrupt request. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE); + /* IRDA parity error interrupt occurred -----------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_IRDA_CLEAR_PEFLAG(hirda); + hirda->ErrorCode |= HAL_IRDA_ERROR_PE; + } + + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); + /* IRDA frame error interrupt occurred ------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_IRDA_CLEAR_FEFLAG(hirda); + hirda->ErrorCode |= HAL_IRDA_ERROR_FE; + } + + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); + /* IRDA noise error interrupt occurred ------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_IRDA_CLEAR_NEFLAG(hirda); + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + } + + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); + /* IRDA Over-Run interrupt occurred ---------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_IRDA_CLEAR_OREFLAG(hirda); + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + } + + /* Call the Error call Back in case of Errors */ + if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + { + /* Disable PE and ERR interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + + /* Set the IRDA state ready to be able to start again the process */ + hirda->State = HAL_IRDA_STATE_READY; + HAL_IRDA_ErrorCallback(hirda); + } + + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE); + /* IRDA in mode Receiver --------------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + IRDA_Receive_IT(hirda); + } + + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE); + /* IRDA in mode Transmitter -----------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + IRDA_Transmit_IT(hirda); + } + + tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC); + tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC); + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + IRDA_EndTransmit_IT(hirda); + } + +} + +/** + * @brief Tx Transfer completed callbacks. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ + __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer complete callbacks. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief IRDA error callbacks. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ + __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief IRDA State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of IrDA + communication process and also return Peripheral Errors occurred during communication process + (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state + of the IRDA peripheral. + (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the IRDA state. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL state + */ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +{ + return hirda->State; +} + +/** + * @brief Return the IRDA error code + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval IRDA Error Code + */ +uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +{ + return hirda->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IRDA_Private_Functions IRDA Private Functions + * @brief IRDA Private functions + * @{ + */ +/** + * @brief DMA IRDA transmit process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + hirda->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Wait for IRDA TC Flag */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + hirda->State = HAL_IRDA_STATE_TIMEOUT; + HAL_IRDA_ErrorCallback(hirda); + } + else + { + /* No Timeout */ + /* Check if a receive process is ongoing or not */ + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + HAL_IRDA_TxCpltCallback(hirda); + } + } + /* DMA Circular mode */ + else + { + HAL_IRDA_TxCpltCallback(hirda); + } +} + +/** + * @brief DMA IRDA receive process half complete callback + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_IRDA_TxHalfCpltCallback(hirda); +} + +/** + * @brief DMA IRDA receive process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + hirda->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + } + + HAL_IRDA_RxCpltCallback(hirda); +} + +/** + * @brief DMA IRDA receive process half complete callback + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_IRDA_RxHalfCpltCallback(hirda); +} + +/** + * @brief DMA IRDA communication error callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->RxXferCount = 0; + hirda->TxXferCount = 0; + hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; + hirda->State= HAL_IRDA_STATE_READY; + + HAL_IRDA_ErrorCallback(hirda); +} + +/** + * @brief This function handles IRDA Communication Timeout. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param Flag: specifies the IRDA flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State= HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State= HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Send an amount of data in non-blocking mode. + * Function called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Transmit_IT() + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hirda->State; + if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) + { + if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) + { + tmp = (uint16_t*) hirda->pTxBuffPtr; + WRITE_REG(hirda->Instance->DR, (uint16_t)(*tmp & IRDA_DR_MASK_U16_9DATABITS)); + if(hirda->Init.Parity == IRDA_PARITY_NONE) + { + hirda->pTxBuffPtr += 2; + } + else + { + hirda->pTxBuffPtr += 1; + } + } + else + { + WRITE_REG(hirda->Instance->DR, (uint8_t)(*hirda->pTxBuffPtr++ & IRDA_DR_MASK_U8_8DATABITS)); + } + + if(--hirda->TxXferCount == 0) + { + /* Disable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + /* Disable the IRDA Parity Error Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_TxCpltCallback(hirda); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hirda->State; + if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) + { + if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) + { + tmp = (uint16_t*) hirda->pRxBuffPtr; + if(hirda->Init.Parity == IRDA_PARITY_NONE) + { + *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS); + hirda->pRxBuffPtr += 2; + } + else + { + *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS); + hirda->pRxBuffPtr += 1; + } + } + else + { + if(hirda->Init.Parity == IRDA_PARITY_NONE) + { + *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS); + } + else + { + *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS); + } + } + + if(--hirda->RxXferCount == 0) + { + + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + /* Disable the IRDA Parity Error Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State = HAL_IRDA_STATE_READY; + } + HAL_IRDA_RxCpltCallback(hirda); + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the IRDA peripheral. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) +{ + /* Check the parameters */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); + assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); + assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); + assert_param(IS_IRDA_MODE(hirda->Init.Mode)); + + /*-------------------------- IRDA CR2 Configuration ------------------------*/ + /* Clear STOP[13:12] bits */ + CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the USART Word Length, Parity and mode: + Set the M bits according to hirda->Init.WordLength value + Set PCE and PS bits according to hirda->Init.Parity value + Set TE and RE bits according to hirda->Init.Mode value */ + MODIFY_REG(hirda->Instance->CR1, + ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), + (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Clear CTSE and RTSE bits */ + CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); + + /*-------------------------- USART BRR Configuration -----------------------*/ + if(hirda->Instance == USART1) + { + hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate); + } + else + { + hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate); + } +} +/** + * @} + */ + +#endif /* HAL_IRDA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c new file mode 100644 index 000000000..39f65ba16 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c @@ -0,0 +1,360 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_iwdg.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief IWDG HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the IWDG peripheral: + * + Initialization and Configuration functions + * + IO operation functions + * + Peripheral State functions + * + @verbatim + +================================================================================ + ##### IWDG specific features ##### +================================================================================ + [..] + (+) The IWDG can be started by either software or hardware (configurable + through option byte). + (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and + thus stays active even if the main clock fails. + (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled + (LSI cannot be disabled too), and the counter starts counting down from + the reset value of 0xFFF. When it reaches the end of count value (0x000) + a system reset is generated. + (+) The IWDG counter should be refreshed at regular intervals, otherwise the + watchdog generates an MCU reset when the counter reaches 0. + (+) The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + reset occurs. + + (+) Min-max timeout value @37KHz (LSI): ~108us / ~28.3s + The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx + devices provide the capability to measure the LSI frequency (LSI clock + connected internally to TIM10 CH1 input capture). The measured value + can be used to have an IWDG timeout with an acceptable accuracy. + For more information, please refer to the STM32L1xx Reference manual. + + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Set the IWDG prescaler and reload value + using HAL_IWDG_Init() function. + (+) Use IWDG using HAL_IWDG_Start() function to: + (++) Enable write access to IWDG_PR and IWDG_RLR registers. + (++) Configure the IWDG prescaler and counter reload values. + (++) Reload IWDG counter with value defined in the IWDG_RLR register. + (++) Start the IWDG, when the IWDG is used in software mode (no need + to enable the LSI, it will be enabled by hardware). + (+) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + + *** IWDG HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IWDG HAL driver. + + (+) __HAL_IWDG_START: Enable the IWDG peripheral + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register + (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers + (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers + (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status + (+) __HAL_IWDG_CLEAR_FLAG: Clear the IWDG's pending flags + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup IWDG IWDG + * @brief IWDG HAL module driver. + * @{ + */ + +#ifdef HAL_IWDG_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup IWDG_Private_Defines IWDG Private Defines + * @{ + */ + +#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000 + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions + * @{ + */ + +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters + in the IWDG_InitTypeDef and create the associated handle + (+) Initialize the IWDG MSP + (+) DeInitialize IWDG MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the IWDG according to the specified + * parameters in the IWDG_InitTypeDef and creates the associated handle. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) +{ + /* Check the IWDG handle allocation */ + if(hiwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); + assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); + assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); + + /* Check pending flag, if previous update not done, return error */ + if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) + &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)) + { + return HAL_ERROR; + } + + if(hiwdg->State == HAL_IWDG_STATE_RESET) + { + /* Init the low level hardware */ + HAL_IWDG_MspInit(hiwdg); + } + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_BUSY; + + /* Enable write access to IWDG_PR and IWDG_RLR registers */ + __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg); + + /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ + MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); + MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the IWDG MSP. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval None + */ +__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_IWDG_MspInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start the IWDG. + (+) Refresh the IWDG. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the IWDG. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) +{ + /* Process Locked */ + __HAL_LOCK(hiwdg); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_BUSY; + + /* Start the IWDG peripheral */ + __HAL_IWDG_START(hiwdg); + + /* Reload IWDG counter with value defined in the RLR register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hiwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Refreshes the IWDG. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) +{ + uint32_t tickstart = 0; + + /* Process Locked */ + __HAL_LOCK(hiwdg); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_BUSY; + + tickstart = HAL_GetTick(); + + /* Wait until RVU flag is RESET */ + while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) + { + if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) + { + /* Set IWDG state */ + hiwdg->State = HAL_IWDG_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hiwdg); + + return HAL_TIMEOUT; + } + } + + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hiwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the IWDG state. + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL state + */ +HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) +{ + return hiwdg->State; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_IWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c new file mode 100644 index 000000000..e77f978ee --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c @@ -0,0 +1,610 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_lcd.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief LCD Controller HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the LCD Controller (LCD) peripheral: + * + Initialization/de-initialization methods + * + I/O operation methods + * + Peripheral State methods + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] The LCD HAL driver can be used as follows: + + (#) Declare a LCD_HandleTypeDef handle structure. + + (#) Initialize the LCD low level resources by implement the HAL_LCD_MspInit() API: + (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows: + (+) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and + selected clock source (HSE, LSI or LSE) + + -@- The frequency generator allows you to achieve various LCD frame rates + starting from an LCD input clock frequency (LCDCLK) which can vary + from 32 kHz up to 1 MHz. + (##) LCD pins configuration: + (+) Enable the clock for the LCD GPIOs. + (+) Configure these LCD pins as alternate function no-pull. + (##) Enable the LCD interface clock. + + (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias, + Voltage Source, Dead Time, Pulse On Duration and Contrast in the hlcd Init structure. + + (#) Initialize the LCD registers by calling the HAL_LCD_Init() API. + + -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc) + by calling the custumed HAL_LCD_MspInit() API. + -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared + + (#) Optionally you can update the LCD configuration using these macros: + (+) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros + (+) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro + (+) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro + (+) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro + (+) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro + + (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called + more time to update the different LCD RAM registers before calling + HAL_LCD_UpdateDisplayRequest() API. + + (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory. + + (#) When LCD RAM memory is updated enable the update display request using + the HAL_LCD_UpdateDisplayRequest() API. + + [..] LCD and low power modes: + (#) The LCD remain active during STOP mode. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_LCD_MODULE_ENABLED + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) + +/** @defgroup LCD LCD + * @brief LCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup LCD_Private_Defines LCD Private Defines + * @{ + */ + +#define LCD_TIMEOUT_VALUE 1000 + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LCD_Exported_Functions LCD Exported Functions + * @{ + */ + +/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + +/** + * @brief DeInitializes the LCD peripheral. + * @param hlcd: LCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) +{ + /* Check the LCD handle allocation */ + if(hlcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); + + hlcd->State = HAL_LCD_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_LCD_MspDeInit(hlcd); + + hlcd->ErrorCode = HAL_LCD_ERROR_NONE; + hlcd->State = HAL_LCD_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hlcd); + + return HAL_OK; +} + +/** + * @brief Initializes the LCD peripheral according to the specified parameters + * in the LCD_InitStruct. + * @note This function can be used only when the LCD is disabled. + * @param hlcd: LCD handle + * @retval None + */ +HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) +{ + uint32_t tickstart = 0x00; + uint8_t counter = 0; + + /* Check the LCD handle allocation */ + if(hlcd == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); + assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler)); + assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider)); + assert_param(IS_LCD_DUTY(hlcd->Init.Duty)); + assert_param(IS_LCD_BIAS(hlcd->Init.Bias)); + assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource)); + assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration)); + assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime)); + assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); + assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); + assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); + assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment)); + + if(hlcd->State == HAL_LCD_STATE_RESET) + { + /* Initialize the low level hardware (MSP) */ + HAL_LCD_MspInit(hlcd); + } + + hlcd->State = HAL_LCD_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_LCD_DISABLE(hlcd); + + /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit + in the LCD_SR register */ + for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) + { + hlcd->Instance->RAM[counter] = 0; + } + /* Enable the display request */ + hlcd->Instance->SR |= LCD_SR_UDR; + + /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: + Set PS[3:0] bits according to hlcd->Init.Prescaler value + Set DIV[3:0] bits according to hlcd->Init.Divider value + Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value + Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value + Set DEAD[2:0] bits according to hlcd->Init.DeadTime value + Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value + Set CC[2:0] bits according to hlcd->Init.Contrast value */ + MODIFY_REG(hlcd->Instance->FCR, \ + (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \ + LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \ + (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ + hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast)); + + /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register + This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK + domain. It is cleared by hardware when writing to the LCD_FCR register.*/ + LCD_WaitForSynchro(hlcd); + + /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast: + Set DUTY[2:0] bits according to hlcd->Init.Duty value + Set BIAS[1:0] bits according to hlcd->Init.Bias value + Set VSEL bit according to hlcd->Init.VoltageSource value + Set MUX_SEG bit according to hlcd->Init.MuxSegment value */ + MODIFY_REG(hlcd->Instance->CR, \ + (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \ + (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment)); + + /* Enable the peripheral */ + __HAL_LCD_ENABLE(hlcd); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait Until the LCD is enabled */ + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET) + { + if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + { + hlcd->ErrorCode = HAL_LCD_ERROR_ENS; + return HAL_TIMEOUT; + } + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /*!< Wait Until the LCD Booster is ready */ + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + { + hlcd->ErrorCode = HAL_LCD_ERROR_RDY; + return HAL_TIMEOUT; + } + } + + /* Initialize the LCD state */ + hlcd->ErrorCode = HAL_LCD_ERROR_NONE; + hlcd->State= HAL_LCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief LCD MSP DeInit. + * @param hlcd: LCD handle + * @retval None + */ + __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_LCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief LCD MSP Init. + * @param hlcd: LCD handle + * @retval None + */ + __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_LCD_MspInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LCD_Exported_Functions_Group2 IO operation methods + * @brief LCD RAM functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] Using its double buffer memory the LCD controller ensures the coherency of the + displayed information without having to use interrupts to control LCD_RAM + modification. + The application software can access the first buffer level (LCD_RAM) through + the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API, + it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API. + This UDR flag (update display request) requests the updated information to be + moved into the second buffer level (LCD_DISPLAY). + This operation is done synchronously with the frame (at the beginning of the + next frame), until the update is completed, the LCD_RAM is write protected and + the UDR flag stays high. + Once the update is completed another flag (UDD - Update Display Done) is set and + generates an interrupt if the UDDIE bit in the LCD_FCR register is set. + The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one + even frame. + The update will not occur (UDR = 1 and UDD = 0) until the display is + enabled (LCDEN = 1). + +@endverbatim + * @{ + */ + +/** + * @brief Writes a word in the specific LCD RAM. + * @param hlcd: LCD handle + * @param RAMRegisterIndex: specifies the LCD RAM Register. + * This parameter can be one of the following values: + * @arg LCD_RAM_REGISTER0: LCD RAM Register 0 + * @arg LCD_RAM_REGISTER1: LCD RAM Register 1 + * @arg LCD_RAM_REGISTER2: LCD RAM Register 2 + * @arg LCD_RAM_REGISTER3: LCD RAM Register 3 + * @arg LCD_RAM_REGISTER4: LCD RAM Register 4 + * @arg LCD_RAM_REGISTER5: LCD RAM Register 5 + * @arg LCD_RAM_REGISTER6: LCD RAM Register 6 + * @arg LCD_RAM_REGISTER7: LCD RAM Register 7 + * @arg LCD_RAM_REGISTER8: LCD RAM Register 8 + * @arg LCD_RAM_REGISTER9: LCD RAM Register 9 + * @arg LCD_RAM_REGISTER10: LCD RAM Register 10 + * @arg LCD_RAM_REGISTER11: LCD RAM Register 11 + * @arg LCD_RAM_REGISTER12: LCD RAM Register 12 + * @arg LCD_RAM_REGISTER13: LCD RAM Register 13 + * @arg LCD_RAM_REGISTER14: LCD RAM Register 14 + * @arg LCD_RAM_REGISTER15: LCD RAM Register 15 + * @param RAMRegisterMask: specifies the LCD RAM Register Data Mask. + * @param Data: specifies LCD Data Value to be written. + * @retval None + */ +HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data) +{ + uint32_t tickstart = 0x00; + + if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) + { + /* Check the parameters */ + assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex)); + + if(hlcd->State == HAL_LCD_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hlcd); + hlcd->State = HAL_LCD_STATE_BUSY; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /*!< Wait Until the LCD is ready */ + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) + { + if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + { + hlcd->ErrorCode = HAL_LCD_ERROR_UDR; + + /* Process Unlocked */ + __HAL_UNLOCK(hlcd); + + return HAL_TIMEOUT; + } + } + } + + /* Copy the new Data bytes to LCD RAM register */ + MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Clears the LCD RAM registers. + * @param hlcd: LCD handle + * @retval None + */ +HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) +{ + uint32_t tickstart = 0x00; + uint32_t counter = 0; + + if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) + { + /* Process Locked */ + __HAL_LOCK(hlcd); + + hlcd->State = HAL_LCD_STATE_BUSY; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /*!< Wait Until the LCD is ready */ + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) + { + if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + { + hlcd->ErrorCode = HAL_LCD_ERROR_UDR; + + /* Process Unlocked */ + __HAL_UNLOCK(hlcd); + + return HAL_TIMEOUT; + } + } + /* Clear the LCD_RAM registers */ + for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) + { + hlcd->Instance->RAM[counter] = 0; + } + + /* Update the LCD display */ + HAL_LCD_UpdateDisplayRequest(hlcd); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enables the Update Display Request. + * @param hlcd: LCD handle + * @note Each time software modifies the LCD_RAM it must set the UDR bit to + * transfer the updated data to the second level buffer. + * The UDR bit stays set until the end of the update and during this + * time the LCD_RAM is write protected. + * @note When the display is disabled, the update is performed for all + * LCD_DISPLAY locations. + * When the display is enabled, the update is performed only for locations + * for which commons are active (depending on DUTY). For example if + * DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated. + * @retval None + */ +HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) +{ + uint32_t tickstart = 0x00; + + /* Clear the Update Display Done flag before starting the update display request */ + __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD); + + /* Enable the display request */ + hlcd->Instance->SR |= LCD_SR_UDR; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /*!< Wait Until the LCD display is done */ + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET) + { + if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + { + hlcd->ErrorCode = HAL_LCD_ERROR_UDD; + + /* Process Unlocked */ + __HAL_UNLOCK(hlcd); + + return HAL_TIMEOUT; + } + } + + hlcd->State = HAL_LCD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hlcd); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods + * @brief LCD State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the LCD: + (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State. + (+) HAL_LCD_GetError() API to return the LCD error code. +@endverbatim + * @{ + */ + +/** + * @brief Returns the LCD state. + * @param hlcd: LCD handle + * @retval HAL state + */ +HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd) +{ + return hlcd->State; +} + +/** + * @brief Return the LCD error code + * @param hlcd: LCD handle + * @retval LCD Error Code + */ +uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd) +{ + return hlcd->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LCD_Private_Functions LCD Private Functions + * @{ + */ + +/** + * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain. + * This function must be called after any write operation to LCD_FCR register. + * @retval None + */ +HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) +{ + uint32_t tickstart = 0x00; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Loop until FCRSF flag is set */ + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET) + { + if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + { + hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF; + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */ + +#endif /* HAL_LCD_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c new file mode 100644 index 000000000..75c0a849c --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c @@ -0,0 +1,838 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_nor.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief NOR HAL module driver. + * This file provides a generic firmware to drive NOR memories mounted + * as external device. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control NOR flash memories. It uses the FSMC layer functions to interface + with NOR devices. This driver is used as follows: + + (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() + with control and timing parameters for both normal and extended mode. + + (+) Read NOR flash memory manufacturer code and device IDs using the function + HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef + structure declared by the function caller. + + (+) Access NOR flash memory by read/write data unit operations using the functions + HAL_NOR_Read(), HAL_NOR_Program(). + + (+) Perform NOR flash erase block/chip operations using the functions + HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). + + (+) Read the NOR flash CFI (common flash interface) IDs using the function + HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef + structure declared by the function caller. + + (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ + HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation + + (+) You can monitor the NOR device HAL state by calling the function + HAL_NOR_GetState() + [..] + (@) This driver is a set of generic APIs which handle standard NOR flash operations. + If a NOR flash device contains different operations and/or implementations, + it should be implemented separately. + + *** NOR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in NOR HAL driver. + + (+) __NOR_WRITE : NOR memory write data to specified address + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup NOR NOR + * @brief NOR driver modules + * @{ + */ +#ifdef HAL_NOR_MODULE_ENABLED +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup NOR_Private_Variables NOR Private Variables + * @{ + */ + +static uint32_t uwNORAddress = NOR_MEMORY_ADRESS1; +static uint32_t uwNORMememoryDataWidth = NOR_MEMORY_8B; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup NOR_Exported_Functions NOR Exported Functions + * @{ + */ + +/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### NOR Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the NOR memory + +@endverbatim + * @{ + */ + +/** + * @brief Perform the NOR memory Initialization sequence + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Timing: pointer to NOR control timing structure + * @param ExtTiming: pointer to NOR extended mode timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) +{ + /* Check the NOR handle parameter */ + if(hnor == NULL) + { + return HAL_ERROR; + } + + if(hnor->State == HAL_NOR_STATE_RESET) + { + /* Initialize the low level hardware (MSP) */ + HAL_NOR_MspInit(hnor); + } + + /* Initialize NOR control Interface */ + FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); + + /* Initialize NOR timing Interface */ + FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); + + /* Initialize NOR extended mode timing Interface */ + FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); + + /* Enable the NORSRAM device */ + __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); + + /* Initialize NOR address mapped by FSMC */ + if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM1) + { + uwNORAddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM2) + { + uwNORAddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM3) + { + uwNORAddress = NOR_MEMORY_ADRESS3; + } + else + { + uwNORAddress = NOR_MEMORY_ADRESS4; + } + + /* Initialize NOR Memory Data Width*/ + if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8) + { + uwNORMememoryDataWidth = NOR_MEMORY_8B; + } + else + { + uwNORMememoryDataWidth = NOR_MEMORY_16B; + } + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Perform NOR memory De-Initialization sequence + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) +{ + /* De-Initialize the low level hardware (MSP) */ + HAL_NOR_MspDeInit(hnor); + + /* Configure the NOR registers with their reset values */ + FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief NOR MSP Init + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval None + */ +__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NOR_MspInit could be implemented in the user file + */ +} + +/** + * @brief NOR MSP DeInit + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval None + */ +__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NOR_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief NOR BSP Wait fro Ready/Busy signal + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Timeout: Maximum timeout value + * @retval None + */ +__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NOR_BspWait could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### NOR Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the NOR memory + +@endverbatim + * @{ + */ + +/** + * @brief Read NOR flash IDs + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pNOR_ID : pointer to NOR ID structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Send read ID command */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0090); + + /* Read the NOR IDs */ + pNOR_ID->ManufacturerCode = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, MC_ADDRESS); + pNOR_ID->DeviceCode1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE1_ADDR); + pNOR_ID->DeviceCode2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE2_ADDR); + pNOR_ID->DeviceCode3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE3_ADDR); + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief Returns the NOR memory to Read mode. + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + __NOR_WRITE(uwNORAddress, 0x00F0); + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief Read data from NOR memory + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pAddress: pointer to Device address + * @param pData : pointer to read data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Send read data command */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055); + __NOR_WRITE(*pAddress, 0x00F0); + + /* Read the data */ + *pData = *(__IO uint32_t *)pAddress; + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief Program data to NOR memory + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pAddress: Device address + * @param pData : pointer to the data to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Send program data command */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00A0); + + /* Write the data */ + __NOR_WRITE(pAddress, *pData); + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief Reads a block of data from the FSMC NOR memory. + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param uwAddress: NOR memory internal address to read from. + * @param pData: pointer to the buffer that receives the data read from the + * NOR memory. + * @param uwBufferSize : number of Half word to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Send read data command */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055); + __NOR_WRITE(uwAddress, 0x00F0); + + /* Read buffer */ + while( uwBufferSize > 0) + { + *pData++ = *(__IO uint16_t *)uwAddress; + uwAddress += 2; + uwBufferSize--; + } + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief Writes a half-word buffer to the FSMC NOR memory. This function + * must be used only with S29GL128P NOR memory. + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param uwAddress: NOR memory internal address from which the data + * @param pData: pointer to source data buffer. + * @param uwBufferSize: number of Half words to write. The maximum allowed + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +{ + uint32_t lastloadedaddress = 0; + uint32_t currentaddress = 0; + uint32_t endaddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Initialize variables */ + currentaddress = uwAddress; + endaddress = uwAddress + uwBufferSize - 1; + lastloadedaddress = uwAddress; + + /* Issue unlock command sequence */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + + /* Write Buffer Load Command */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), 0x25); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), (uwBufferSize - 1)); + + /* Load Data into NOR Buffer */ + while(currentaddress <= endaddress) + { + /* Store last loaded address & data value (for polling) */ + lastloadedaddress = currentaddress; + + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, currentaddress), *pData++); + + currentaddress += 1; + } + + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, lastloadedaddress), 0x29); + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; + +} + +/** + * @brief Erase the specified block of the NOR memory + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param BlockAddress : Block to erase address + * @param Address: Device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Send block erase command sequence */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30); + + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; + +} + +/** + * @brief Erase the entire NOR chip. + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Address : Device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Send NOR chip erase command sequence */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0010); + + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief Read NOR flash CFI IDs + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pNOR_CFI : pointer to NOR CFI IDs structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Check the NOR controller state */ + if(hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Send read CFI query command */ + __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0055), 0x0098); + + /* read the NOR CFI information */ + pNOR_CFI->CFI1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI1_ADDRESS); + pNOR_CFI->CFI2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI2_ADDRESS); + pNOR_CFI->CFI3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI3_ADDRESS); + pNOR_CFI->CFI4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI4_ADDRESS); + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup NOR_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### NOR Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the NOR interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically NOR write operation. + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Enable write operation */ + FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief Disables dynamically NOR write operation. + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) +{ + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the SRAM controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Disable write operation */ + FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup NOR_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### NOR State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the NOR controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief return the NOR controller state + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval NOR controller state + */ +HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) +{ + return hnor->State; +} + +/** + * @brief Returns the NOR operation status. + * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Address: Device address + * @param Timeout: NOR progamming Timeout + * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR + * or NOR_TIMEOUT + */ +NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) +{ + NOR_StatusTypedef status = NOR_ONGOING; + uint16_t tmpSR1 = 0, tmpSR2 = 0; + uint32_t tickstart = 0; + + /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ + HAL_NOR_MspWait(hnor, Timeout); + + /* Get the NOR memory operation status -------------------------------------*/ + while(status != NOR_TIMEOUT) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + status = NOR_TIMEOUT; + } + + /* Read NOR status register (DQ6 and DQ5) */ + tmpSR1 = *(__IO uint16_t *)Address; + tmpSR2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return NOR_Success */ + if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) + { + return NOR_SUCCESS; + } + + if((tmpSR1 & 0x0020) == 0x0020) + { + return NOR_ONGOING; + } + + tmpSR1 = *(__IO uint16_t *)Address; + tmpSR2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return NOR_Success */ + if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) + { + return NOR_SUCCESS; + } + + if((tmpSR1 & 0x0020) == 0x0020) + { + return NOR_ERROR; + } + } + + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c new file mode 100644 index 000000000..c159523f3 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c @@ -0,0 +1,1004 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_opamp.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief OPAMP HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the operational amplifiers (OPAMP1 ,... ,OPAMP3) + * peripheral: + * + OPAMP configuration + * + OPAMP calibration + * + * Thanks to + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim +================================================================================ + ##### OPAMP Peripheral Features ##### +================================================================================ + + [..] The device integrates up to 3 operational amplifiers OPAMP1, OPAMP2, + OPAMP3 (OPAMP3 availability depends on device category) + + (#) The OPAMP(s) provides several exclusive running modes. + (+) Standalone mode + (+) Follower mode + + (#) The OPAMP(s) provide(s) calibration capabilities. + (+) Calibration aims at correcting some offset for running mode. + (+) The OPAMP uses either factory calibration settings OR user defined + calibration (trimming) settings (i.e. trimming mode). + (+) The user defined settings can be figured out using self calibration + handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll + (+) HAL_OPAMP_SelfCalibrate: + (++) Runs automatically the calibration in 2 steps: for transistors + differential pair high (PMOS) or low (NMOS) + (++) Enables the user trimming mode + (++) Updates the init structure with trimming values with fresh calibration + results. + The user may store the calibration results for larger + (ex monitoring the trimming as a function of temperature + for instance) + (++) for devices having several OPAMPs, HAL_OPAMPEx_SelfCalibrateAll + runs calibration of all OPAMPs in parallel to save trimming search + wait time. + + (#) Running mode: Standalone mode + (+) Gain is set externally (gain depends on external loads). + (+) Follower mode also possible externally by connecting the inverting input to + the output. + + (#) Running mode: Follower mode + (+) No Inverting Input is connected. + (+) The OPAMP(s) output(s) are internally connected to inverting input + + (#) The OPAMPs inverting input can be selected among the list shown + in table below. + + (#) The OPAMPs non inverting input can be selected among the list shown + in table below. + + [..] Table 1. OPAMPs inverting/non-inverting inputs for STM32L1 devices: + + +--------------------------------------------------------------------------+ + | | HAL param | OPAMP1 | OPAMP2 | OPAMP3(4) | + | | name | | | | + |----------------|------------|--------------|--------------|--------------| + | Inverting | VM0 | PA2 | PA7 | PC2 | + | input (1) | VM1 | VINM pin (2) | VINM pin (2) | VINM pin (2) | + |----------------|------------|--------------|--------------|--------------| + | Non Inverting | VP0 | PA1 | PA6 | PC1 | + | input | DAC_CH1 (3)| DAC_CH1 | DAC_CH1 | --- | + | | DAC_CH2 (3)| --- | DAC_CH2 | DAC_CH2 | + +--------------------------------------------------------------------------+ + (1): NA in follower mode. + (2): OPAMP input OPAMPx_VINM are dedicated OPAMP pins, their availability + depends on device package. + (3): DAC channels 1 and 2 are connected internally to OPAMP. Nevertheless, + I/O pins connected to DAC can still be used as DAC output (pins PA4 + and PA5). + (4): OPAMP3 availability depends on device category. + + + [..] Table 2. OPAMPs outputs for STM32L1 devices: + + +--------------------------------------------------------+ + | | OPAMP1 | OPAMP2 | OPAMP3(4) | + |-----------------|------------|------------|------------| + | Output | PA3 | PB0 | PC3 | + +--------------------------------------------------------+ + (4) : OPAMP3 availability depends on device category + + + ##### How to use this driver ##### +================================================================================ + [..] + + *** Calibration *** + ============================================ + To run the opamp calibration self calibration: + + (#) Start calibration using HAL_OPAMP_SelfCalibrate. + Store the calibration results. + + *** Running mode *** + ============================================ + + To use the opamp, perform the following steps: + + (#) Fill in the HAL_OPAMP_MspInit() to + (+) Enable the OPAMP Peripheral clock using macro "__OPAMP_CLK_ENABLE()" + (++) Configure the opamp input AND output in analog mode using + HAL_GPIO_Init() to map the opamp output to the GPIO pin. + + (#) Configure the opamp using HAL_OPAMP_Init() function: + (+) Select the mode + (+) Select the inverting input + (+) Select the non-inverting input + (+) Select either factory or user defined trimming mode. + (+) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values + (typ. settings returned by HAL_OPAMP_SelfCalibrate function). + + (#) Enable the opamp using HAL_OPAMP_Start() function. + + (#) Disable the opamp using HAL_OPAMP_Stop() function. + + (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. + Caution: On STM32L1, HAL OPAMP lock is software lock only (not + hardware lock as on some other STM32 devices) + + (#) If needed, unlock the opamp using HAL_OPAMPEx_Unlock() function. + + *** Running mode: change of configuration while OPAMP ON *** + ============================================ + To Re-configure OPAMP when OPAMP is ON (change on the fly) + (#) If needed, Fill in the HAL_OPAMP_MspInit() + (+) This is the case for instance if you wish to use new OPAMP I/O + + (#) Configure the opamp using HAL_OPAMP_Init() function: + (+) As in configure case, selects first the parameters you wish to modify. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup OPAMP OPAMP + * @brief OPAMP HAL module driver + * @{ + */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions + * @{ + */ + +/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the OPAMP according to the specified + * parameters in the OPAMP_InitTypeDef and create the associated handle. + * @note If the selected opamp is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @param hopamp: OPAMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp_csr = 0; /* Temporary variable to update register CSR, except bits ANAWSSELx, S7SEL2, OPA_RANGE, OPAxCALOUT */ + + /* Check the OPAMP handle allocation and lock status */ + /* Init not allowed if calibration is ongoing */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) + || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) ) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + /* Set OPAMP parameters */ + assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); + assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput)); + assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); + assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange)); + assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); + + if (hopamp->Init.Mode != OPAMP_FOLLOWER_MODE) + { + assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput)); + } + + if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) + { + if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP)); + assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN)); + } + else + { + assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower)); + assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower)); + } + } + + /* Call MSP init function */ + HAL_OPAMP_MspInit(hopamp); + + + /* Set OPAMP parameters */ + /* - Set internal switches in function of: */ + /* - OPAMP selected mode: standalone or follower. */ + /* - Non-inverting input connection */ + /* - Inverting input connection */ + /* - Set power supply range */ + /* - Set power mode and associated calibration parameters */ + + /* Get OPAMP CSR register into temporary variable */ + tmp_csr = OPAMP->CSR; + + /* Open all switches on non-inverting input, inverting input and output */ + /* feedback. */ + CLEAR_BIT(tmp_csr, __OPAMP_CSR_ALL_SWITCHES(hopamp)); + + /* Set internal switches in function of OPAMP mode selected: standalone */ + /* or follower. */ + /* If follower mode is selected, feedback switch S3 is closed and */ + /* inverting inputs switches are let opened. */ + /* If standalone mode is selected, feedback switch S3 is let opened and */ + /* the selected inverting inputs switch is closed. */ + if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE) + { + /* Follower mode: Close switches S3 and SanB */ + SET_BIT(tmp_csr, __OPAMP_CSR_S3SELX(hopamp)); + } + else + { + /* Set internal switches in function of inverting input selected: */ + /* Close switch to connect comparator inverting input to the selected */ + /* input: dedicated IO pin or alternative IO pin available on some */ + /* device packages. */ + if (hopamp->Init.InvertingInput == OPAMP_INVERTINGINPUT_VM0) + { + /* Close switch to connect comparator non-inverting input to */ + /* dedicated IO pin low-leakage. */ + SET_BIT(tmp_csr, __OPAMP_CSR_S4SELX(hopamp)); + } + else + { + /* Close switch to connect comparator inverting input to alternative */ + /* IO pin available on some device packages. */ + SET_BIT(tmp_csr, __OPAMP_CSR_ANAWSELX(hopamp)); + } + } + + /* Set internal switches in function of non-inverting input selected: */ + /* Close switch to connect comparator non-inverting input to the selected */ + /* input: dedicated IO pin or DAC channel. */ + if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_VP0) + { + /* Close switch to connect comparator non-inverting input to */ + /* dedicated IO pin low-leakage. */ + SET_BIT(tmp_csr, __OPAMP_CSR_S5SELX(hopamp)); + } + else if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_DAC_CH1) + { + + /* Particular case for connection to DAC channel 1: */ + /* OPAMP_NONINVERTINGINPUT_DAC_CH1 available on OPAMP1 and OPAMP2 only */ + /* (OPAMP3 availability depends on device category). */ + if ((hopamp->Instance == OPAMP1) || (hopamp->Instance == OPAMP2)) + { + /* Close switch to connect comparator non-inverting input to */ + /* DAC channel 1. */ + SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); + } + else + { + /* Set HAL status to error if another OPAMP instance as OPAMP1 or */ + /* OPAMP2 is intended to be connected to DAC channel 2. */ + status = HAL_ERROR; + } + } + else /* if (hopamp->Init.NonInvertingInput == */ + /* OPAMP_NONINVERTINGINPUT_DAC_CH2 ) */ + { + /* Particular case for connection to DAC channel 2: */ + /* OPAMP_NONINVERTINGINPUT_DAC_CH2 available on OPAMP2 and OPAMP3 only */ + /* (OPAMP3 availability depends on device category). */ + if (hopamp->Instance == OPAMP2) + { + /* Close switch to connect comparator non-inverting input to */ + /* DAC channel 2. */ + SET_BIT(tmp_csr, OPAMP_CSR_S7SEL2); + } + /* If OPAMP3 is selected (if available) */ + else if (hopamp->Instance != OPAMP1) + { + /* Close switch to connect comparator non-inverting input to */ + /* DAC channel 2. */ + SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); + } + else + { + /* Set HAL status to error if another OPAMP instance as OPAMP2 or */ + /* OPAMP3 (if available) is intended to be connected to DAC channel 2.*/ + status = HAL_ERROR; + } + } + + /* Continue OPAMP configuration if settings of switches are correct */ + if (status != HAL_ERROR) + { + /* Set power mode and associated calibration parameters */ + if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Set normal mode */ + CLEAR_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); + + if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) + { + /* Set calibration mode (factory or user) and values for */ + /* transistors differential pair high (PMOS) and low (NMOS) for */ + /* normal mode. */ + MODIFY_REG(OPAMP->OTR, OPAMP_OTR_OT_USER | + __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | + __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , + hopamp->Init.UserTrimming | + __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueN) | + __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValueP) ); + } + else + { + /* Set calibration mode to factory */ + CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); + } + + } + else + { + /* Set low power mode */ + SET_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); + + if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) + { + /* Set calibration mode to user trimming */ + SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); + + /* Set values for transistors differential pair high (PMOS) and low */ + /* (NMOS) for low power mode. */ + MODIFY_REG(OPAMP->LPOTR, __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | + __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , + __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueNLowPower) | + __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValuePLowPower) ); + } + else + { + /* Set calibration mode to factory trimming */ + CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); + } + + } + + + /* Configure the power supply range */ + MODIFY_REG(tmp_csr, OPAMP_CSR_AOP_RANGE, + hopamp->Init.PowerSupplyRange); + + /* Set OPAMP CSR register from temporary variable */ + /* This allows to apply all changes on one time, in case of update on */ + /* the fly with OPAMP previously set and running: */ + /* - to avoid hazardous transient switches settings (risk of short */ + /* circuit) */ + /* - to avoid interruption of input signal */ + OPAMP->CSR = tmp_csr; + + + /* Update the OPAMP state */ + /* If coming from state reset: Update from state RESET to state READY */ + /* else: remain in state READY or BUSY (no update) */ + if (hopamp->State == HAL_OPAMP_STATE_RESET) + { + hopamp->State = HAL_OPAMP_STATE_READY; + } + } + } + + return status; +} + + +/** + * @brief DeInitializes the OPAMP peripheral + * @note Deinitialization can't be performed if the OPAMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param hopamp: OPAMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + /* DeInit not allowed if calibration is ongoing */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ + || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + { + status = HAL_ERROR; + } + else + { + + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + /* Open all switches on non-inverting input, inverting input and output */ + /* feedback. */ + CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); + + /* DeInit the low level hardware */ + HAL_OPAMP_MspDeInit(hopamp); + + /* Update the OPAMP state*/ + hopamp->State = HAL_OPAMP_STATE_RESET; + } + + /* Process unlocked */ + __HAL_UNLOCK(hopamp); + + return status; +} + + +/** + * @brief Initializes the OPAMP MSP. + * @param hopamp: OPAMP handle + * @retval None + */ +__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* hopamp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the function "HAL_OPAMP_MspInit()" must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes OPAMP MSP. + * @param hopamp: OPAMP handle + * @retval None + */ +__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* hopamp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file. + */ +} + +/** + * @} + */ + + +/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the OPAMP + start, stop and calibration actions. + +@endverbatim + * @{ + */ + +/** + * @brief Start the opamp + * @param hopamp: OPAMP handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + if(hopamp->State == HAL_OPAMP_STATE_READY) + { + /* Enable the selected opamp */ + CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); + + /* Update the OPAMP state */ + /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */ + hopamp->State = HAL_OPAMP_STATE_BUSY; + } + else + { + status = HAL_ERROR; + } + + } + return status; +} + +/** + * @brief Stop the opamp + * @param hopamp: OPAMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + /* Check if OPAMP calibration ongoing */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ + || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + if(hopamp->State == HAL_OPAMP_STATE_BUSY) + { + /* Disable the selected opamp */ + SET_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); + + /* Update the OPAMP state*/ + /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/ + hopamp->State = HAL_OPAMP_STATE_READY; + } + else + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Run the self calibration of one OPAMP + * @note Trimming values (PMOS & NMOS) are updated and user trimming is + * enabled is calibration is succesful. + * @note Calibration is performed in the mode specified in OPAMP init + * structure (mode normal or low-power). To perform calibration for + * both modes, repeat this function twice after OPAMP init structure + * accordingly updated. + * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P + * and N transistors: 10 steps with 1 ms for each step). + * @param hopamp: handle + * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + + uint32_t* opamp_trimmingvalue = 0; + uint32_t opamp_trimmingvaluen = 0; + uint32_t opamp_trimmingvaluep = 0; + + uint32_t trimming_diff_pair = 0; /* Selection of differential transistors pair high or low */ + + __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + uint32_t tmp_opamp_otr_otuser = 0; /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */ + + uint32_t tmp_Opaxcalout_DefaultSate = 0; /* Bit OPAMP_CSR_OPAXCALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ + + uint32_t tmp_OpaxSwitchesContextBackup = 0; + + uint8_t trimming_diff_pair_iteration_count = 0; + uint8_t delta = 0; + + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + { + status = HAL_ERROR; + } + else + { + + /* Check if OPAMP in calibration mode and calibration not yet enable */ + if(hopamp->State == HAL_OPAMP_STATE_READY) + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); + + /* Update OPAMP state */ + hopamp->State = HAL_OPAMP_STATE_CALIBBUSY; + + /* Backup of switches configuration to restore it at the end of the */ + /* calibration. */ + tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); + + /* Open all switches on non-inverting input, inverting input and output */ + /* feedback. */ + CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); + + /* Set calibration mode to user programmed trimming values */ + SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); + + + /* Select trimming settings depending on power mode */ + if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp_otr_otuser = OPAMP_OTR_OT_USER; + tmp_opamp_reg_trimming = &OPAMP->OTR; + } + else + { + tmp_opamp_otr_otuser = 0x00000000; + tmp_opamp_reg_trimming = &OPAMP->LPOTR; + } + + + /* Enable the selected opamp */ + CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); + + /* Perform trimming for both differential transistors pair high and low */ + for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) + { + if (trimming_diff_pair_iteration_count == 0) + { + /* Calibration of transistors differential pair high (NMOS) */ + trimming_diff_pair = OPAMP_FACTORYTRIMMING_N; + opamp_trimmingvalue = &opamp_trimmingvaluen; + + /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ + /* is 00000b. Used to detect the bit toggling during trimming. */ + tmp_Opaxcalout_DefaultSate = RESET; + + /* Enable calibration for N differential pair */ + MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_L(hopamp), + __OPAMP_CSR_OPAXCAL_H(hopamp) ); + } + else /* (trimming_diff_pair_iteration_count == 1) */ + { + /* Calibration of transistors differential pair low (PMOS) */ + trimming_diff_pair = OPAMP_FACTORYTRIMMING_P; + opamp_trimmingvalue = &opamp_trimmingvaluep; + + /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ + /* is 00000b. Used to detect the bit toggling during trimming. */ + tmp_Opaxcalout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp); + + /* Enable calibration for P differential pair */ + MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_H(hopamp), + __OPAMP_CSR_OPAXCAL_L(hopamp) ); + } + + + /* Perform calibration parameter search by dichotomy sweep */ + /* - Delta initial value 16: for 5 dichotomy steps: 16 for the */ + /* initial range, then successive delta sweeps (8, 4, 2, 1). */ + /* can extend the search range to +/- 15 units. */ + /* - Trimming initial value 15: search range will go from 0 to 30 */ + /* (Trimming value 31 is forbidden). */ + *opamp_trimmingvalue = 15; + delta = 16; + + while (delta != 0) + { + /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser); + + /* Offset trimming time: during calibration, minimum time needed */ + /* between two steps to have 1 mV accuracy. */ + HAL_Delay(OPAMP_TRIMMING_DELAY); + + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1; + + /* Set trimming values for next iteration in function of trimming */ + /* result toggle (versus initial state). */ + if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp)) != tmp_Opaxcalout_DefaultSate) + { + /* If calibration output is has toggled, try lower trimming */ + *opamp_trimmingvalue -= delta; + } + else + { + /* If calibration output is has not toggled, try higher trimming */ + *opamp_trimmingvalue += delta; + } + } + + } + + /* Disable calibration for P and N differential pairs */ + /* Disable the selected opamp */ + CLEAR_BIT (OPAMP->CSR, (__OPAMP_CSR_OPAXCAL_H(hopamp) | + __OPAMP_CSR_OPAXCAL_L(hopamp) | + __OPAMP_CSR_OPAXPD(hopamp)) ); + + /* Backup of switches configuration to restore it at the end of the */ + /* calibration. */ + SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); + + /* Self calibration is successful */ + /* Store calibration (user trimming) results in init structure. */ + + /* Set user trimming mode */ + hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER; + + /* Affect calibration parameters depending on mode normal/low power */ + if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp->Init.TrimmingValueN = opamp_trimmingvaluen; + /* Write calibration result P */ + hopamp->Init.TrimmingValueP = opamp_trimmingvaluep; + } + else + { + /* Write calibration result N */ + hopamp->Init.TrimmingValueNLowPower = opamp_trimmingvaluen; + /* Write calibration result P */ + hopamp->Init.TrimmingValuePLowPower = opamp_trimmingvaluep; + } + + /* Update OPAMP state */ + hopamp->State = HAL_OPAMP_STATE_READY; + + } + else + { + /* OPAMP can not be calibrated from this mode */ + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Return the OPAMP factory trimming value + * Caution: On STM32L1 OPAMP, user can retrieve factory trimming if + * OPAMP has never been set to user trimming before. + * Therefore, this fonction must be called when OPAMP init + * parameter "UserTrimming" is set to trimming factory, + * and before OPAMP calibration (function + * "HAL_OPAMP_SelfCalibrate()"). + * Otherwise, factory triming value cannot be retrieved and + * error status is returned. + * @param hopamp : OPAMP handle + * @param trimmingoffset : Trimming offset (P or N) + * This parameter must be a value of @ref OPAMP_FactoryTrimming + * @note Calibration parameter retrieved is corresponding to the mode + * specified in OPAMP init structure (mode normal or low-power). + * To retrieve calibration parameters for both modes, repeat this + * function after OPAMP init structure accordingly updated. + * @retval Trimming value (P or N): range: 0->31 + * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available + * @{ + */ +OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) +{ + OPAMP_TrimmingValueTypeDef trimmingvalue; + __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + + /* Check the OPAMP handle allocation */ + /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) + || (hopamp->State == HAL_OPAMP_STATE_BUSY) + || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) + || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + { + trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY; + } + else + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset)); + assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); + + /* Check the trimming mode */ + if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) + { + /* This fonction must called when OPAMP init parameter "UserTrimming" */ + /* is set to trimming factory, and before OPAMP calibration (function */ + /* "HAL_OPAMP_SelfCalibrate()"). */ + /* Otherwise, factory triming value cannot be retrieved and error */ + /* status is returned. */ + trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY; + } + else + { + /* Select trimming settings depending on power mode */ + if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp_reg_trimming = &OPAMP->OTR; + } + else + { + tmp_opamp_reg_trimming = &OPAMP->LPOTR; + } + + /* Get factory trimming */ + trimmingvalue = ((*tmp_opamp_reg_trimming >> __OPAMP_OFFSET_TRIM_BITSPOSITION(hopamp, trimmingoffset)) & OPAMP_TRIM_VALUE_MASK); + } + } + + return trimmingvalue; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected opamp configuration. + * Caution: On STM32L1, HAL OPAMP lock is software lock only (not + * hardware lock as on some other STM32 devices) + * @param hopamp: OPAMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + /* OPAMP can be locked when enabled and running in normal mode */ + /* It is meaningless otherwise */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ + || (hopamp->State == HAL_OPAMP_STATE_READY) \ + || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ + || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + + { + status = HAL_ERROR; + } + + else + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + /* OPAMP state changed to locked */ + hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED; + } + return status; +} + +/** + * @} + */ + + +/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the OPAMP state + * @param hopamp : OPAMP handle + * @retval HAL state + */ +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef* hopamp) +{ + /* Check the OPAMP handle allocation */ + if(hopamp == NULL) + { + return HAL_OPAMP_STATE_RESET; + } + + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + return hopamp->State; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +#endif /* HAL_OPAMP_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c new file mode 100644 index 000000000..364e222fc --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c @@ -0,0 +1,757 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_opamp_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Extended OPAMP HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (OPAMP) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + @verbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup OPAMPEx OPAMPEx + * @brief OPAMP Extended HAL module driver. + * @{ + */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions + * @{ + */ + +/** @addtogroup OPAMPEx_Exported_Functions_Group1 + * @brief Extended operation functions + * +@verbatim + =============================================================================== + ##### Extended IO operation functions ##### + =============================================================================== + [..] + (+) OPAMP Self calibration. + +@endverbatim + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/* 3 OPAMPS available */ +/* 3 OPAMPS can be calibrated in parallel */ + +/** + * @brief Run the self calibration of the 3 OPAMPs in parallel. + * @note Trimming values (PMOS & NMOS) are updated and user trimming is + * enabled is calibration is succesful. + * @note Calibration is performed in the mode specified in OPAMP init + * structure (mode normal or low-power). To perform calibration for + * both modes, repeat this function twice after OPAMP init structure + * accordingly updated. + * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P + * and N transistors: 10 steps with 1 ms for each step). + * @param hopamp1 handle + * @param hopamp2 handle + * @param hopamp3 handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3) +{ + HAL_StatusTypeDef status = HAL_OK; + + uint32_t* opamp1_trimmingvalue = 0; + uint32_t opamp1_trimmingvaluen = 0; + uint32_t opamp1_trimmingvaluep = 0; + + uint32_t* opamp2_trimmingvalue = 0; + uint32_t opamp2_trimmingvaluen = 0; + uint32_t opamp2_trimmingvaluep = 0; + + uint32_t* opamp3_trimmingvalue = 0; + uint32_t opamp3_trimmingvaluen = 0; + uint32_t opamp3_trimmingvaluep = 0; + + uint32_t trimming_diff_pair = 0; /* Selection of differential transistors pair high or low */ + + __IO uint32_t* tmp_opamp1_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + __IO uint32_t* tmp_opamp2_reg_trimming; + __IO uint32_t* tmp_opamp3_reg_trimming; + uint32_t tmp_opamp1_otr_otuser = 0; /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */ + uint32_t tmp_opamp2_otr_otuser = 0; + uint32_t tmp_opamp3_otr_otuser = 0; + + uint32_t tmp_Opa1calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ + uint32_t tmp_Opa2calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ + uint32_t tmp_Opa3calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA3CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ + + uint32_t tmp_OpaxSwitchesContextBackup = 0; + + uint8_t trimming_diff_pair_iteration_count = 0; + uint8_t delta = 0; + + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || + (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || + (hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) ) + { + status = HAL_ERROR; + } + else + { + + /* Check if OPAMP in calibration mode and calibration not yet enable */ + if((hopamp1->State == HAL_OPAMP_STATE_READY) && + (hopamp2->State == HAL_OPAMP_STATE_READY) && + (hopamp3->State == HAL_OPAMP_STATE_READY) ) + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance)); + assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); + assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); + assert_param(IS_OPAMP_POWERMODE(hopamp3->Init.PowerMode)); + + /* Update OPAMP state */ + hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY; + hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY; + hopamp3->State = HAL_OPAMP_STATE_CALIBBUSY; + + /* Backup of switches configuration to restore it at the end of the */ + /* calibration. */ + tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); + + /* Open all switches on non-inverting input, inverting input and output */ + /* feedback. */ + CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); + + /* Set calibration mode to user programmed trimming values */ + SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); + + /* Select trimming settings depending on power mode */ + if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER; + tmp_opamp1_reg_trimming = &OPAMP->OTR; + } + else + { + tmp_opamp1_otr_otuser = 0x00000000; + tmp_opamp1_reg_trimming = &OPAMP->LPOTR; + } + + if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER; + tmp_opamp2_reg_trimming = &OPAMP->OTR; + } + else + { + tmp_opamp2_otr_otuser = 0x00000000; + tmp_opamp2_reg_trimming = &OPAMP->LPOTR; + } + + if (hopamp3->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp3_otr_otuser = OPAMP_OTR_OT_USER; + tmp_opamp3_reg_trimming = &OPAMP->OTR; + } + else + { + tmp_opamp3_otr_otuser = 0x00000000; + tmp_opamp3_reg_trimming = &OPAMP->LPOTR; + } + + /* Enable the selected opamp */ + CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL); + + /* Perform trimming for both differential transistors pair high and low */ + for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) + { + if (trimming_diff_pair_iteration_count == 0) + { + /* Calibration of transistors differential pair high (NMOS) */ + trimming_diff_pair = OPAMP_FACTORYTRIMMING_N; + opamp1_trimmingvalue = &opamp1_trimmingvaluen; + opamp2_trimmingvalue = &opamp2_trimmingvaluen; + opamp3_trimmingvalue = &opamp3_trimmingvaluen; + + /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ + /* is 00000b. Used to detect the bit toggling during trimming. */ + tmp_Opa1calout_DefaultSate = RESET; + tmp_Opa2calout_DefaultSate = RESET; + tmp_Opa3calout_DefaultSate = RESET; + + /* Enable calibration for N differential pair */ + MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, + OPAMP_CSR_OPAXCAL_H_ALL); + } + else /* (trimming_diff_pair_iteration_count == 1) */ + { + /* Calibration of transistors differential pair low (PMOS) */ + trimming_diff_pair = OPAMP_FACTORYTRIMMING_P; + opamp1_trimmingvalue = &opamp1_trimmingvaluep; + opamp2_trimmingvalue = &opamp2_trimmingvaluep; + opamp3_trimmingvalue = &opamp3_trimmingvaluep; + + /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ + /* is 00000b. Used to detect the bit toggling during trimming. */ + tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1); + tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2); + tmp_Opa3calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp3); + + /* Enable calibration for P differential pair */ + MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, + OPAMP_CSR_OPAXCAL_L_ALL); + } + + + /* Perform calibration parameter search by dichotomy sweep */ + /* - Delta initial value 16: for 5 dichotomy steps: 16 for the */ + /* initial range, then successive delta sweeps (8, 4, 2, 1). */ + /* can extend the search range to +/- 15 units. */ + /* - Trimming initial value 15: search range will go from 0 to 30 */ + /* (Trimming value 31 is forbidden). */ + *opamp1_trimmingvalue = 15; + *opamp2_trimmingvalue = 15; + *opamp3_trimmingvalue = 15; + delta = 16; + + while (delta != 0) + { + /* Set candidate trimming */ + + MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); + + MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); + + MODIFY_REG(*tmp_opamp3_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser); + + + /* Offset trimming time: during calibration, minimum time needed */ + /* between two steps to have 1 mV accuracy. */ + HAL_Delay(OPAMP_TRIMMING_DELAY); + + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1; + + /* Set trimming values for next iteration in function of trimming */ + /* result toggle (versus initial state). */ + /* Trimming values update with dichotomy delta of previous */ + /* iteration. */ + if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) + { + /* If calibration output is has toggled, try lower trimming */ + *opamp1_trimmingvalue -= delta; + } + else + { + /* If calibration output is has not toggled, try higher trimming */ + *opamp1_trimmingvalue += delta; + } + + /* Set trimming values for next iteration in function of trimming */ + /* result toggle (versus initial state). */ + /* Trimming values update with dichotomy delta of previous */ + /* iteration. */ + if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) + { + /* If calibration output is has toggled, try lower trimming */ + *opamp2_trimmingvalue -= delta; + } + else + { + /* If calibration output is has not toggled, try higher trimming */ + *opamp2_trimmingvalue += delta; + } + + /* Set trimming values for next iteration in function of trimming */ + /* result toggle (versus initial state). */ + /* Trimming values update with dichotomy delta of previous */ + /* iteration. */ + if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp3)) != tmp_Opa3calout_DefaultSate) + { + /* If calibration output is has toggled, try lower trimming */ + *opamp3_trimmingvalue -= delta; + } + else + { + /* If calibration output is has not toggled, try higher trimming */ + *opamp3_trimmingvalue += delta; + } + + } + } + + + /* Disable calibration for P and N differential pairs */ + /* Disable the selected opamp */ + CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | + OPAMP_CSR_OPAXCAL_L_ALL | + OPAMP_CSR_OPAXPD_ALL )); + + /* Backup of switches configuration to restore it at the end of the */ + /* calibration. */ + SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); + + /* Self calibration is successful */ + /* Store calibration (user trimming) results in init structure. */ + + /* Set user trimming mode */ + hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; + hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; + hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER; + + /* Affect calibration parameters depending on mode normal/low power */ + if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen; + /* Write calibration result P */ + hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep; + } + else + { + /* Write calibration result N */ + hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen; + /* Write calibration result P */ + hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep; + } + + if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen; + /* Write calibration result P */ + hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep; + } + else + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen; + /* Write calibration result P */ + hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep; + } + + if (hopamp3->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp3->Init.TrimmingValueN = opamp3_trimmingvaluen; + /* Write calibration result P */ + hopamp3->Init.TrimmingValueP = opamp3_trimmingvaluep; + } + else + { + /* Write calibration result N */ + hopamp3->Init.TrimmingValueNLowPower = opamp3_trimmingvaluen; + /* Write calibration result P */ + hopamp3->Init.TrimmingValuePLowPower = opamp3_trimmingvaluep; + } + + /* Update OPAMP state */ + hopamp1->State = HAL_OPAMP_STATE_READY; + hopamp2->State = HAL_OPAMP_STATE_READY; + hopamp3->State = HAL_OPAMP_STATE_READY; + + } + else + { + /* OPAMP can not be calibrated from this mode */ + status = HAL_ERROR; + } + } + + return status; +} + +#else + +/* 2 OPAMPS available */ +/* 2 OPAMPS can be calibrated in parallel */ + +/** + * @brief Run the self calibration of the 2 OPAMPs in parallel. + * @note Trimming values (PMOS & NMOS) are updated and user trimming is + * enabled is calibration is succesful. + * @note Calibration is performed in the mode specified in OPAMP init + * structure (mode normal or low-power). To perform calibration for + * both modes, repeat this function twice after OPAMP init structure + * accordingly updated. + * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P + * and N transistors: 10 steps with 1 ms for each step). + * @param hopamp1 handle + * @param hopamp2 handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2) +{ + HAL_StatusTypeDef status = HAL_OK; + + uint32_t* opamp1_trimmingvalue = 0; + uint32_t opamp1_trimmingvaluen = 0; + uint32_t opamp1_trimmingvaluep = 0; + + uint32_t* opamp2_trimmingvalue = 0; + uint32_t opamp2_trimmingvaluen = 0; + uint32_t opamp2_trimmingvaluep = 0; + + uint32_t trimming_diff_pair = 0; /* Selection of differential transistors pair high or low */ + + __IO uint32_t* tmp_opamp1_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + __IO uint32_t* tmp_opamp2_reg_trimming; + uint32_t tmp_opamp1_otr_otuser = 0; /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */ + uint32_t tmp_opamp2_otr_otuser = 0; + + uint32_t tmp_Opa1calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ + uint32_t tmp_Opa2calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ + + uint32_t tmp_OpaxSwitchesContextBackup = 0; + + uint8_t trimming_diff_pair_iteration_count = 0; + uint8_t delta = 0; + + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || + (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) ) + { + status = HAL_ERROR; + } + else + { + + /* Check if OPAMP in calibration mode and calibration not yet enable */ + if((hopamp1->State == HAL_OPAMP_STATE_READY) && + (hopamp2->State == HAL_OPAMP_STATE_READY) ) + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); + assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); + assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); + + /* Update OPAMP state */ + hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY; + hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY; + + /* Backup of switches configuration to restore it at the end of the */ + /* calibration. */ + tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); + + /* Open all switches on non-inverting input, inverting input and output */ + /* feedback. */ + CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); + + /* Set calibration mode to user programmed trimming values */ + SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); + + /* Select trimming settings depending on power mode */ + if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER; + tmp_opamp1_reg_trimming = &OPAMP->OTR; + } + else + { + tmp_opamp1_otr_otuser = 0x00000000; + tmp_opamp1_reg_trimming = &OPAMP->LPOTR; + } + + if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER; + tmp_opamp2_reg_trimming = &OPAMP->OTR; + } + else + { + tmp_opamp2_otr_otuser = 0x00000000; + tmp_opamp2_reg_trimming = &OPAMP->LPOTR; + } + + /* Enable the selected opamp */ + CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL); + + /* Perform trimming for both differential transistors pair high and low */ + for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) + { + if (trimming_diff_pair_iteration_count == 0) + { + /* Calibration of transistors differential pair high (NMOS) */ + trimming_diff_pair = OPAMP_FACTORYTRIMMING_N; + opamp1_trimmingvalue = &opamp1_trimmingvaluen; + opamp2_trimmingvalue = &opamp2_trimmingvaluen; + + /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ + /* is 00000b. Used to detect the bit toggling during trimming. */ + tmp_Opa1calout_DefaultSate = RESET; + tmp_Opa2calout_DefaultSate = RESET; + + /* Enable calibration for N differential pair */ + MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, + OPAMP_CSR_OPAXCAL_H_ALL); + } + else /* (trimming_diff_pair_iteration_count == 1) */ + { + /* Calibration of transistors differential pair low (PMOS) */ + trimming_diff_pair = OPAMP_FACTORYTRIMMING_P; + opamp1_trimmingvalue = &opamp1_trimmingvaluep; + opamp2_trimmingvalue = &opamp2_trimmingvaluep; + + /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ + /* is 00000b. Used to detect the bit toggling during trimming. */ + tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1); + tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2); + + /* Enable calibration for P differential pair */ + MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, + OPAMP_CSR_OPAXCAL_L_ALL); + } + + + /* Perform calibration parameter search by dichotomy sweep */ + /* - Delta initial value 16: for 5 dichotomy steps: 16 for the */ + /* initial range, then successive delta sweeps (8, 4, 2, 1). */ + /* can extend the search range to +/- 15 units. */ + /* - Trimming initial value 15: search range will go from 0 to 30 */ + /* (Trimming value 31 is forbidden). */ + *opamp1_trimmingvalue = 15; + *opamp2_trimmingvalue = 15; + delta = 16; + + while (delta != 0) + { + /* Set candidate trimming */ + + MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); + + MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , + __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); + + + /* Offset trimming time: during calibration, minimum time needed */ + /* between two steps to have 1 mV accuracy. */ + HAL_Delay(OPAMP_TRIMMING_DELAY); + + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1; + + /* Set trimming values for next iteration in function of trimming */ + /* result toggle (versus initial state). */ + if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) + { + /* If calibration output is has toggled, try lower trimming */ + *opamp1_trimmingvalue -= delta; + } + else + { + /* If calibration output is has not toggled, try higher trimming */ + *opamp1_trimmingvalue += delta; + } + + /* Set trimming values for next iteration in function of trimming */ + /* result toggle (versus initial state). */ + if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) + { + /* If calibration output is has toggled, try lower trimming */ + *opamp2_trimmingvalue -= delta; + } + else + { + /* If calibration output is has not toggled, try higher trimming */ + *opamp2_trimmingvalue += delta; + } + + } + } + + + /* Disable calibration for P and N differential pairs */ + /* Disable the selected opamp */ + CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | + OPAMP_CSR_OPAXCAL_L_ALL | + OPAMP_CSR_OPAXPD_ALL )); + + /* Backup of switches configuration to restore it at the end of the */ + /* calibration. */ + SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); + + /* Self calibration is successful */ + /* Store calibration (user trimming) results in init structure. */ + + /* Set user trimming mode */ + hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; + hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; + + /* Affect calibration parameters depending on mode normal/low power */ + if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen; + /* Write calibration result P */ + hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep; + } + else + { + /* Write calibration result N */ + hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen; + /* Write calibration result P */ + hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep; + } + + if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen; + /* Write calibration result P */ + hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep; + } + else + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen; + /* Write calibration result P */ + hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep; + } + + /* Update OPAMP state */ + hopamp1->State = HAL_OPAMP_STATE_READY; + hopamp2->State = HAL_OPAMP_STATE_READY; + + } + else + { + /* OPAMP can not be calibrated from this mode */ + status = HAL_ERROR; + } + } + + return status; +} + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @defgroup OPAMPEx_Exported_Functions_Group2 Extended Peripheral Control functions + * @brief Extended control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + (+) OPAMP unlock. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the selected opamp configuration. + * This function must be called only when OPAMP is in state "locked". + * @param hopamp: OPAMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) + || (hopamp->State == HAL_OPAMP_STATE_READY) + || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) + || (hopamp->State == HAL_OPAMP_STATE_BUSY)) + + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + /* OPAMP state changed to locked */ + hopamp->State = HAL_OPAMP_STATE_BUSY; + } + return status; +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +#endif /* HAL_OPAMP_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c new file mode 100644 index 000000000..8dc7ffcf8 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c @@ -0,0 +1,1345 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pcd.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __USB_CLK_ENABLE); + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable HCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +#define BTABLE_ADDRESS (0x000) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +/** + * @} + */ + + +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and create the associated handle. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + uint32_t i = 0; + + uint32_t wInterrupt_Mask = 0; + + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + + hpcd->State = PCD_BUSY; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + + /* Init endpoints structures */ + for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1; + hpcd->IN_ep[i].num = i; + /* Control until ep is actvated */ + hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0; + hpcd->IN_ep[i].xfer_buff = 0; + hpcd->IN_ep[i].xfer_len = 0; + } + + for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + { + hpcd->OUT_ep[i].is_in = 0; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0; + hpcd->OUT_ep[i].xfer_buff = 0; + hpcd->OUT_ep[i].xfer_len = 0; + } + + /* Init Device */ + /*CNTR_FRES = 1*/ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /*CNTR_FRES = 0*/ + hpcd->Instance->CNTR = 0; + + /*Clear pending interrupts*/ + hpcd->Instance->ISTR = 0; + + /*Set Btable Adress*/ + hpcd->Instance->BTABLE = BTABLE_ADDRESS; + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + hpcd->USB_Address = 0; + hpcd->State= PCD_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if(hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = PCD_BUSY; + + /* Stop Device */ + HAL_PCD_Stop(hpcd); + + /* DeInit the low level hardware */ + HAL_PCD_MspDeInit(hpcd); + + hpcd->State = PCD_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd: PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implenetd in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd: PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start The USB OTG Device. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + HAL_PCDEx_SetConnectionState (hpcd, 1); + return HAL_OK; +} + +/** + * @brief Stop The USB OTG Device. + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* disable all interrupts and force USB reset */ + hpcd->Instance->CNTR = USB_CNTR_FRES; + + /* clear interrupt status register */ + hpcd->Instance->ISTR = 0; + + /* switch-off device */ + hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief This function handles PCD interrupt request. + * @param hpcd: PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + uint32_t wInterrupt_Mask = 0; + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + PCD_EP_ISR_Handler(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + HAL_PCD_ResetCallback(hpcd); + HAL_PCD_SetAddress(hpcd, 0); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVRM)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVRM); + } + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) + { + hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE); + + /*set wInterrupt_Mask global variable*/ + wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ + | USB_CNTR_ESOFM | USB_CNTR_RESETM; + + /*Set interrupt mask*/ + hpcd->Instance->CNTR = wInterrupt_Mask; + + HAL_PCD_ResumeCallback(hpcd); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) + { + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + { + HAL_PCD_SuspendCallback(hpcd); + } + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + HAL_PCD_SOFCallback(hpcd); + } + + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + } +} + +/** + * @brief Data out stage callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implenetd in the user file + */ +} + +/** + * @brief Data IN stage callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implenetd in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd: ppp handle + * @retval None + */ + __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implenetd in the user file + */ +} + +/** + * @brief USB Start Of Frame callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implenetd in the user file + */ +} + +/** + * @brief USB Reset callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implenetd in the user file + */ +} + + +/** + * @brief Suspend event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implenetd in the user file + */ +} + +/** + * @brief Resume event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implenetd in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implenetd in the user file + */ +} + +/** + * @brief Incomplete ISO IN callbacks + * @param hpcd: PCD handle + * @param epnum: endpoint number + * @retval None + */ + __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implenetd in the user file + */ +} + +/** + * @brief Connection event callbacks + * @param hpcd: PCD handle + * @retval None + */ + __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implenetd in the user file + */ +} + +/** + * @brief Disconnection event callbacks + * @param hpcd: ppp handle + * @retval None + */ + __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ + HAL_PCDEx_SetConnectionState (hpcd, 1); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Disconnect the USB device + * @param hpcd: PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + + /* Disable DP Pull-Down bit*/ + HAL_PCDEx_SetConnectionState (hpcd, 0); + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Set the USB Device address + * @param hpcd: PCD handle + * @param address: new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + + if(address == 0) + { + /* set device address and enable function */ + hpcd->Instance->DADDR = USB_DADDR_EF; + } + else /* USB Address will be applied later */ + { + hpcd->USB_Address = address; + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} +/** + * @brief Open and configure an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @param ep_mps: endpoint max packert size + * @param ep_type: endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + + ep->is_in = (0x80 & ep_addr) != 0; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + __HAL_LOCK(hpcd); + +/* initialize Endpoint */ + switch (ep->type) + { + case PCD_EP_TYPE_CTRL: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL); + break; + case PCD_EP_TYPE_BULK: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK); + break; + case PCD_EP_TYPE_INTR: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT); + break; + case PCD_EP_TYPE_ISOC: + PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); + break; + default: + break; + } + + PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); + + if (ep->doublebuffer == 0) + { + if (ep->is_in) + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + /* Configure NAK status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + else + { + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + } + } + /*Double Buffer*/ + else + { + /*Set the endpoint as double buffered*/ + PCD_SET_EP_DBUF(hpcd->Instance, ep->num); + /*Set buffer address for double buffered mode*/ + PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1); + + if (ep->is_in==0) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + } + } + + __HAL_UNLOCK(hpcd); + return ret; +} + + +/** + * @brief Deactivate an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + + ep->is_in = (0x80 & ep_addr) != 0; + + __HAL_LOCK(hpcd); + + if (ep->doublebuffer == 0) + { + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + } + } + /*Double Buffer*/ + else + { + if (ep->is_in==0) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(hpcd->Instance, ep->num); + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_RX_DTOG(hpcd->Instance, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + } + } + + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @param pBuf: pointer to the reception buffer + * @param len: amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0; + ep->is_in = 0; + ep->num = ep_addr & 0x7F; + + __HAL_LOCK(hpcd); + + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0; + } + + /* configure and validate Rx endpoint */ + if (ep->doublebuffer == 0) + { + /*Set RX buffer count*/ + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len); + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + } + + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval Data Size + */ +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @param pBuf: pointer to the transmission buffer + * @param len: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + uint16_t pmabuffer = 0; + + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0; + ep->is_in = 1; + ep->num = ep_addr & 0x7F; + + __HAL_LOCK(hpcd); + + /*Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len=ep->maxpacket; + ep->xfer_len-=len; + } + else + { + len=ep->xfer_len; + ep->xfer_len =0; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); + PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /*Write the data to the USB endpoint*/ + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) + { + pmabuffer = ep->pmaaddr1; + } + else + { + pmabuffer = ep->pmaaddr0; + } + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in); + } + + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + __HAL_LOCK(hpcd); + + if ((0x80 & ep_addr) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 1; + ep->num = ep_addr & 0x7F; + ep->is_in = ((ep_addr & 0x80) == 0x80); + + if (ep->num == 0) + { + /* This macro sets STALL status for RX & TX*/ + PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + } + else + { + if (ep->is_in) + { + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); + } + else + { + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL); + } + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((0x80 & ep_addr) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + ep->is_stall = 0; + ep->num = ep_addr & 0x7F; + ep->is_in = ((ep_addr & 0x80) == 0x80); + + __HAL_LOCK(hpcd); + + if (ep->is_in) + { + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + } + else + { + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Flush an endpoint + * @param hpcd: PCD handle + * @param ep_addr: endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return HAL_OK; +} + +/** + * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling + * @param hpcd: PCD handle + * @retval status + */ +HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + hpcd->Instance->CNTR |= USB_CNTR_RESUME; + return HAL_OK; +} + +/** + * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling + * @param hpcd: PCD handle + * @retval status + */ +HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + + +/** + * @brief Return the PCD state + * @param hpcd : PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} + + +/** + * @brief Software Device Connection + * @param hpcd: PCD handle + * @param state: Device state + * @retval None + */ + __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCDEx_SetConnectionState could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PCD_Private_Functions + * @{ + */ + + +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd: PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + PCD_EPTypeDef *ep; + uint16_t count=0; + uint8_t EPindex; + __IO uint16_t wIstr; + __IO uint16_t wEPVal = 0; + + /* stay in loop while pending interrupts */ + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (EPindex == 0) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, 0); + + + if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) + { + hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0; + } + + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0) + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ + HAL_PCD_SetupStageCallback(hpcd); + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + ep->xfer_buff+=ep->xfer_count; + } + + /* Process Control Data OUT Packet*/ + HAL_PCD_DataOutStageCallback(hpcd, 0); + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + } + } + else + { + + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); + if ((wEPVal & USB_EP_CTR_RX) != 0) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); + ep = &hpcd->OUT_ep[EPindex]; + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0) + { + count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + { + /*read from endpoint BUF0Addr buffer*/ + count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count+=count; + ep->xfer_buff+=count; + + if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ + HAL_PCD_DataOutStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0) + { + ep = &hpcd->IN_ep[EPindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); + + /* IN double Buffering*/ + if (ep->doublebuffer == 0) + { + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) + { + /*read from endpoint BUF0Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + } + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff+=ep->xfer_count; + + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx = pointer to USB register. + * @param pbUsrBuf: pointer to user memory area. + * @param wPMABufAddr: address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ + uint32_t i, temp1, temp2; + uint16_t *pdwVal; + pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); + for (i = n; i != 0; i--) + { + temp1 = (uint16_t) * pbUsrBuf; + pbUsrBuf++; + temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + *pdwVal++ = temp2; + pdwVal++; + pbUsrBuf++; + } +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx = pointer to USB register. + * @param pbUsrBuf = pointer to user memory area. + * @param wPMABufAddr: address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1;/* /2*/ + uint32_t i; + uint32_t *pdwVal; + pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); + for (i = n; i != 0; i--) + { + *(uint16_t*)pbUsrBuf++ = *pdwVal++; + pbUsrBuf++; + } +} + +/** + * @} + */ + +#endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c new file mode 100644 index 000000000..e920f600f --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c @@ -0,0 +1,147 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pcd_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Extended PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Configururation of the PMA for EP + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCDEx HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/* +@verbatim + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Configure PMA for EP + * @param hpcd : Device instance + * @param ep_addr: endpoint address + * @param ep_kind: endpoint Kind + * USB_SNG_BUF: Single Buffer used + * USB_DBL_BUF: Double Buffer used + * @param pmaadress: EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval : status + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress) + +{ + PCD_EPTypeDef *ep; + + /* initialize ep structure*/ + if ((0x80 & ep_addr) == 0x80) + { + ep = &hpcd->IN_ep[ep_addr & 0x7F]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + { + /*Single Buffer*/ + ep->doublebuffer = 0; + /*Configure te PMA*/ + ep->pmaadress = (uint16_t)pmaadress; + } + else /*USB_DBL_BUF*/ + { + /*Double Buffer Endpoint*/ + ep->doublebuffer = 1; + /*Configure the PMA*/ + ep->pmaaddr0 = pmaadress & 0xFFFF; + ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; + } + + return HAL_OK; +} + + + +/** + * @} + */ + +#endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c new file mode 100644 index 000000000..ac34c1822 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c @@ -0,0 +1,612 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief PWR HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define PVD_MODE_IT ((uint32_t)0x00010000) +#define PVD_MODE_EVT ((uint32_t)0x00020000) +#define PVD_RISING_EDGE ((uint32_t)0x00000001) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @note Before calling this function, the VOS[1:0] bits should be configured + * to "10" and the system frequency has to be configured accordingly. + * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() + * function. + * @note ULP and FWU bits are not reset by this function. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __PWR_FORCE_RESET(); + __PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers ). + * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers). + * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) The PVD can use an external input analog voltage (PVD_IN) which is compared + internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode + when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). + + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There are two or three WakeUp pins: + WakeUp Pin 1 on PA.00. + WakeUp Pin 2 on PC.13. + WakeUp Pin 3 on PE.06. : Only on product with GPIOE available + + [..] + *** Main and Backup Regulators configuration *** + ================================================ + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() + macro which configure VOS bit in PWR_CR register: + (++) When this bit is set (Regulator voltage output Scale 1 mode selected) + the System frequency can go up to 32 MHz. + (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) + the System frequency can go up to 16 MHz. + (++) When this bit is reset (Regulator voltage output Scale 3 mode selected) + the System frequency can go up to 4.2 MHz. + + Refer to the datasheets for more details. + + *** Low Power modes configuration *** + ===================================== + [..] + The device features 5 low-power modes: + (+) Low power run mode: regulator in low power mode, limited clock frequency, + limited number of peripherals running. + (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running. + (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, + limited number of peripherals running, regulator in low power mode. + (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. + (+) Standby mode: VCORE domain powered off + + *** Low power run mode *** + ========================= + [..] + To further reduce the consumption when the system is in Run mode, the regulator can be + configured in low power mode. In this mode, the system frequency should not exceed + MSI frequency range1. + In Low power run mode, all I/O pins keep the same state as in Run mode. + + (+) Entry: + (++) VCORE in range2 + (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1. + (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() + function. + (+) Exit: + (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode() + function. + (++) Increase the system frequency if needed. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Low power sleep mode *** + ============================ + [..] + (+) Entry: + The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. + This reduces power consumption but increases the wake-up time. + + (+) Exit: + (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt + acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device + from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode, + the MCU exits Sleep mode as soon as an event occurs. + + *** Stop mode *** + ================= + [..] + The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral + clock gating. The voltage regulator can be configured either in normal or low-power mode. + In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and + the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. + To get the lowest consumption in Stop mode, the internal Flash memory also enters low + power mode. When the Flash memory is in power-down mode, an additional startup delay is + incurred when waking up from Stop mode. + To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature + sensor can be switched off before entering Stop mode. They can be switched on again by + software after exiting Stop mode using the ULP bit in the PWR_CR register. + In Stop mode, all I/O pins keep the same state as in Run mode. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI ) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (+) Exit: + (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock. + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based on the + Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is + consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are + also switched off. SRAM and register contents are lost except for the RTC registers, RTC + backup registers and Standby circuitry. + + To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature + sensor can be switched off before entering the Standby mode. They can be switched + on again by software after exiting the Standby mode. + function. + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: + (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() + function + (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() + and HAL_RTC_SetTime() functions. + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and + Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT() + or HAL_RTCEx_SetTimeStamp_IT() functions. + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: + (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and + Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer() + function. + + (+) RTC auto-wakeup (AWU) from the Standby mode + (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: + (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function. + (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() + and HAL_RTC_SetTime() functions. + (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to + detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() + or HAL_RTCEx_SetTamper_IT()functions. + (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: + (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup + event, it is necessary to: + (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the + selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using + the COMP functions. + (+++) Configure the comparator to generate the event. + + + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator: Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by using an interrupt or a wakeup event, + * MSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator: Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - WKUP pin 1 (PA0) if enabled. + * - WKUP pin 2 (PC13) if enabled. + * - WKUP pin 3 (PE6) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c new file mode 100644 index 000000000..a8d474f48 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c @@ -0,0 +1,168 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Enables the Fast WakeUp from Ultra Low Power mode. + * @note This bit works in conjunction with ULP bit. + * Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when + * exiting from low power mode. + * @retval None + */ +void HAL_PWREx_EnableFastWakeUp(void) +{ + /* Enable the fast wake up */ + *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Fast WakeUp from Ultra Low Power mode. + * @retval None + */ +void HAL_PWREx_DisableFastWakeUp(void) +{ + /* Disable the fast wake up */ + *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the Ultra Low Power mode + * @retval None + */ +void HAL_PWREx_EnableUltraLowPower(void) +{ + /* Enable the Ultra Low Power mode */ + *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Ultra Low Power mode + * @retval None + */ +void HAL_PWREx_DisableUltraLowPower(void) +{ + /* Disable the Ultra Low Power mode */ + *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enters the Low Power Run mode. + * @note Low power run mode can only be entered when VCORE is in range 2. + * In addition, the dynamic voltage scaling must not be used when Low + * power run mode is selected. Only Stop and Sleep modes with regulator + * configured in Low power mode is allowed when Low power run mode is + * selected. + * @note In Low power run mode, all I/O pins keep the same state as in Run mode. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + /* Enters the Low Power Run mode */ + *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE; + *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE; +} + +/** + * @brief Exits the Low Power Run mode. + * @retval None + */ +void HAL_PWREx_DisableLowPowerRunMode(void) +{ + /* Exits the Low Power Run mode */ + *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE; + *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c new file mode 100644 index 000000000..731a4f872 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c @@ -0,0 +1,1313 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from multispeed internal oscillator clock + (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at MSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + (*) SDIO only for STM32L1xxxD devices + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Defines RCC Private Defines + * @{ + */ + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t aPLLDivisionFactorTable[4] = {1, 2, 3, 4}; +const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== +##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz, + 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. + + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 32 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clockis automatically switched to MSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M3 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE, + HSE or PLL clock (through a configurable prescaler) on PA8 pin. + + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() + macros to configure this clock. + (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 16. You have to use __HAL_RCC_LCD_CONFIG() + macros to configure this clock. + (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly. This clock is derived of the main PLL through PLL Multiplier. + (+@) IWDG clock which is always the LSI clock. + + (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz + and PCLK1 32 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly: + +----------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |------------------------------------------------------| + | | voltage range 1 | voltage range 2 | voltage range 3 | + | | 1.8 V | 1.5 V | 1.2 V | + |---------------|------------------|-----------------|-----------------| + |0WS(1CPU cycle)| 0 < HCLK <= 16 | 0 < HCLK <= 8 | 0 < HCLK <= 2 | + |---------------|------------------|-----------------|-----------------| + |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 | + +----------------------------------------------------------------------+ + (#) The following table gives the different clock source frequencies depending on the product + voltage range: + +------------------------------------------------------------------------------------------+ + | Product voltage | Clock frequency | + | |------------------|-----------------------------|-----------------------| + | range | MSI | HSI | HSE | PLL | + |-----------------|---------|--------|-----------------------------|-----------------------| + | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) | 32 MHz | + | | | | or 24 MHz (crystal) | (PLLVCO max = 96 MHz) | + |-----------------|---------|--------|-----------------------------|-----------------------| + | Range 2 (1.5 V) | 4.2 MHz | 16 MHz | 16 MHz | 16 MHz | + | | | | | (PLLVCO max = 48 MHz) | + |-----------------|---------|--------|-----------------------------|-----------------------| + | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz | + | | | | | (PLLVCO max = 24 MHz) | + +------------------------------------------------------------------------------------------+ + + @endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - MSI ON and used as system clock source + * - HSI, HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +void HAL_RCC_DeInit(void) +{ + /* Set MSION bit */ + SET_BIT(RCC->CR, RCC_CR_MSION); + + /* Switch SYSCLK to MSI*/ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); + + /* Reset HSION, HSEON, CSSON, HSEBYP & PLLON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */ + MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << POSITION_VAL(RCC_ICSCR_MSITRIM)) | RCC_ICSCR_MSIRANGE_5)); + + /* Set HSITRIM bits to the reset value */ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_ICSCR_HSITRIM))); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) + { + return HAL_ERROR; + } + } + else + { + /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ + __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + { + /* Check the parameters */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSIRANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Configures the Internal Multi Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + + /* Check if MSI is used as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)) + { + /* When MSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Multi Speed oscillator (MSI) calibration value. */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + } + } + else + { + /* Check the MSI State */ + if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF) + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Multi Speed oscillator (MSI) calibration value. */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable Power Clock*/ + __PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ + __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency: FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1: FLASH One Latency cycle + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The MSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /* Decreasing the CPU frequency */ + else + { + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + } + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx: specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected + * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected + * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected + * @arg RCC_MCO1SOURCE_MSI: MSI oscillator clock selected + * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected + * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected + * @arg RCC_MCO1SOURCE_LSI: LSI clock selected + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected + * @param RCC_MCODiv: specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCO clock + * @arg RCC_MCODIV_2: division by 2 applied to MCO clock + * @arg RCC_MCODIV_4: division by 4 applied to MCO clock + * @arg RCC_MCODIV_8: division by 8 applied to MCO clock + * @arg RCC_MCODIV_16: division by 16 applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO Clock Enable */ + __MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Pin = MCO1_PIN; + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is MSI, function returns values based on MSI + * Value as defined by the MSI range. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0; + uint32_t sysclockfreq = 0; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + { + pllm = aPLLMulFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; + plld = aPLLDivisionFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> POSITION_VAL(RCC_CFGR_PLLDIV)]; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = HSE_VALUE * (pllm / plld); + } + else + { + /* HSI used as PLL clock source */ + pllvco = HSI_VALUE * (pllm / plld); + } + sysclockfreq = pllvco; + break; + } + case RCC_CFGR_SWS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> POSITION_VAL(RCC_ICSCR_MSIRANGE); + sysclockfreq = (32768 * (1 << (msiclkrange + 1))); + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM)); + + /* Get the MSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION) + { + RCC_OscInitStruct->MSIState = RCC_MSI_ON; + } + else + { + RCC_OscInitStruct->MSIState = RCC_MSI_OFF; + } + + RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM)); + RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE)); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency: Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CCSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CCSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CCSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c new file mode 100644 index 000000000..435d7998b --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Extended RCC HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Private_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + ) + { + /* Enable Power Controller clock */ + __PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + tmpreg = (RCC->CSR & RCC_CSR_RTCSEL); + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if((tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + ) + { + /* Store the content of CSR register before the reset of Backup Domain */ + tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of CSR register */ + RCC->CSR = tmpreg; + } + + /* If LSE is selected as RTC clock source, wait for LSE reactivation */ + if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE) +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + ) + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + return HAL_OK; +} + +/** + * @brief Get the PeriphClkInit according to the internal + * RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t srcclk = 0; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ + + /* Get the RTC/LCD configuration -----------------------------------------------*/ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2) + { + /* Source clock is LSE or LSI*/ + PeriphClkInit->RTCClockSelection = srcclk; + } + else + { + /* Source clock is HSE. Need to get the prescaler value*/ + PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); + } +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ + defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ + defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ + defined(STM32L162xE) + PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ +} + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ + defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + +/** + * @brief Enables the LSE Clock Security System. + * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied + * to the RTC but no hardware action is made to the registers. + * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup + * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104). + * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator + * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with + * RTCSEL), or take any required action to secure the application. + * @note LSE CSS available only for high density and medium+ devices + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the LSE Clock Security System. + * @note Once enabled this bit cannot be disabled, except after an LSE failure detection + * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit. + * Reset by power on reset and RTC software reset (RTCRST bit). + * @note LSE CSS available only for high density and medium+ devices + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE; +} +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c new file mode 100644 index 000000000..7ec1d1eb0 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c @@ -0,0 +1,902 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rtc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) peripheral: + * + Initialization and de-initialization functions + * + RTC Time and Date functions + * + RTC Alarm functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### Backup Domain Operating Condition ##### + ============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC operating even when the main digital supply (VDD) is turned + off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) PC13 to PC15 I/Os (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected to VDD), + the following pins are available: + (#) PC14 and PC15 can be used as either GPIO or LSE pins + (#) PC13 can be used as a GPIO or as the RTC_AF1 pin + + [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT + because VDD is not present), the following pins are available: + (#) PC14 and PC15 can be used as LSE pins only + (#) PC13 can be used as the RTC_AF1 pin + + ##### Backup Domain Reset ##### + ================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. + [..] A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __PWR_CLK_ENABLE() function. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + + + ##### How to use this driver ##### + ================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source + is LSE or LSI. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RTC peripheral + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + /* Check the RTC peripheral state */ + if(hrtc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + + if(hrtc->State == HAL_RTC_STATE_RESET) + { + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; + hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; + } +} + +/** + * @brief DeInitializes the RTC peripheral + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note This function doesn't reset the RTC Backup Data registers. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32l1xx_hal_rtc_ex.c */ + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief Initializes the RTC MSP. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the RTC MSP. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Sets RTC current time. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + (((uint32_t)sTime->TimeFormat) << 16)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(sTime->Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ + ((uint32_t)(sTime->Minutes) << 8) | \ + ((uint32_t)sTime->Seconds) | \ + ((uint32_t)(sTime->TimeFormat) << 16)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Set the RTC_TR register */ + hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Clear the bits to be configured */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* Wait for synchro */ + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + + +/** + * @brief Sets RTC current date. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate: Pointer to date structure + * @param Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if(Format == FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + ((uint32_t)sDate->WeekDay << 13)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + datetmpreg = RTC_Bcd2ToByte(sDate->Month); + assert_param(IS_RTC_MONTH(datetmpreg)); + datetmpreg = RTC_Bcd2ToByte(sDate->Date); + assert_param(IS_RTC_DATE(datetmpreg)); + + datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ + (((uint32_t)sDate->Month) << 8) | \ + ((uint32_t)sDate->Date) | \ + (((uint32_t)sDate->WeekDay) << 13)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Set the RTC_DR register */ + hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* Wait for synchro */ + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY ; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets RTC current date. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate: Pointer to Date structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if(Format == FORMAT_BIN) + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + } + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ + +/** + * @brief Deactive the specified RTC Alarm + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Alarm: Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + if(Alarm == RTC_ALARM_A) + { + /* AlarmA */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + else + { + /* AlarmB */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); + + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles Alarm interrupt request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +{ + if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) + { + /* AlarmA callback */ + HAL_RTC_AlarmAEventCallback(hrtc); + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + } + } + + if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET) + { + /* AlarmB callback */ + HAL_RTCEx_AlarmBEventCallback(hrtc); + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); + } + } + + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Alarm A callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles AlarmA Polling request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Returns the RTC state. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) +{ + return hrtc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Internal_Functions RTC Internal function + * @{ + */ + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +{ + uint32_t tickstart = 0; + + /* Check if the Initialization mode is set */ + if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcdhigh = 0; + + while(Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Converts from 2 digit BCD to Binary. + * @param Value: BCD value to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c new file mode 100644 index 000000000..2a4c484a6 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c @@ -0,0 +1,2482 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rtc_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extension peripheral: + * + RTC Time Stamp functions + * + RTC Tamper functions + * + RTC Wake-up functions + * + Extension Control functions + * + Extension RTC features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access. + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() + function. + + *** TimeStamp configuration *** + =============================== + [..] + (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the + HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with + interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + (+) The TIMESTAMP alternate function can be mapped to RTC_AF1 (PC13). + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, precharge or discharge and Pull-UP using the + HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt + mode using HAL_RTCEx_SetTamper_IT() function. + (+) The TAMPER1 alternate function can be mapped to RTC_AF1 (PC13). + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup RTC_Exported_Functions + * @{ + */ + + +/** @addtogroup RTC_Exported_Functions_Group1 + * @{ + */ + +/** + * @brief DeInitializes the RTC peripheral + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note This function does not reset the RTC Backup Data registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + hrtc->Instance->TR = (uint32_t)0x00000000; + hrtc->Instance->DR = (uint32_t)0x00002101; + /* Reset All CR bits except CR[2:0] */ + hrtc->Instance->CR &= (uint32_t)0x00000007; + + tickstart = HAL_GetTick(); + + /* Wait till WUTWF flag is set and if Time out is reached exit */ + while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Reset all RTC CR register bits */ + hrtc->Instance->CR &= (uint32_t)0x00000000; + hrtc->Instance->WUTR = (uint32_t)0x0000FFFF; + hrtc->Instance->PRER = (uint32_t)0x007F00FF; + hrtc->Instance->CALIBR = (uint32_t)0x00000000; + hrtc->Instance->ALRMAR = (uint32_t)0x00000000; + hrtc->Instance->ALRMBR = (uint32_t)0x00000000; +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + hrtc->Instance->SHIFTR = (uint32_t)0x00000000; + hrtc->Instance->CALR = (uint32_t)0x00000000; + hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; + hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + /* Reset ISR register and exit initialization mode */ + hrtc->Instance->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + hrtc->Instance->TAFCR = 0x00000000; + + /* Wait for synchro */ + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); + + hrtc->State = HAL_RTC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group2 + * @{ + */ + +/** + * @brief Gets RTC current time. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Get subseconds values from the correspondent registers*/ + sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Get the TR register */ + tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if(Format == FORMAT_BIN) + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group3 + * @{ + */ + +/** + * @brief Sets the specified RTC Alarm. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tickstart = 0; + uint32_t tmpreg = 0; + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t subsecondtmpreg = 0; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_ALARM(sAlarm->Alarm)); + assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if(sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + tickstart = HAL_GetTick(); + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); + + tickstart = HAL_GetTick(); + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMBR = (uint32_t)tmpreg; +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Configure the Alarm B Sub Second register */ + hrtc->Instance->ALRMBSSR = subsecondtmpreg; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMB_ENABLE(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets the specified RTC Alarm with Interrupt + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tickstart = 0; + uint32_t tmpreg = 0; +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t subsecondtmpreg = 0; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_ALARM(sAlarm->Alarm)); + assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if(sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + tickstart = HAL_GetTick(); + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + + /* Clear flag alarm B */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + + tickstart = HAL_GetTick(); + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMBR = (uint32_t)tmpreg; +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Configure the Alarm B Sub Second register */ + hrtc->Instance->ALRMBSSR = subsecondtmpreg; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMB_ENABLE(hrtc); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets the RTC Alarm value and masks. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Date structure + * @param Alarm: Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +{ + uint32_t tmpreg = 0; +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + uint32_t subsecondtmpreg = 0; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_ALARM(Alarm)); + + if(Alarm == RTC_ALARM_A) + { + /* AlarmA */ + sAlarm->Alarm = RTC_ALARM_A; + + tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + } + else + { + sAlarm->Alarm = RTC_ALARM_B; + + tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + } + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); + sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); + sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + + if(Format == FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + } + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup RTC_Exported_Functions_Group6 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +{ + uint32_t tickstart = 0; + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + { + /* Clear RSF flag */ + hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTCEx RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/** @defgroup RTCEx_Exported_Functions_Group4 RTC TimeStamp and Tamper functions + * @brief RTC TimeStamp and Tamper functions + * +@verbatim + =============================================================================== + ##### RTC TimeStamp and Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure TimeStamp feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + tmpreg|= TimeStampEdge; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets TimeStamp with Interrupt. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note This API must be called before enabling the TimeStamp feature. + * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + tmpreg |= TimeStampEdge; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + + /* Enable IT timestamp */ + __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); + + /* RTC timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates TimeStamp. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) +{ + uint32_t tmpreg = 0; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets the RTC TimeStamp value. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTimeStamp: Pointer to Time structure + * @param sTimeStampDate: Pointer to Date structure + * @param Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * FORMAT_BIN: Binary data format + * FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + sTimeStamp->SubSeconds = (uint32_t)((hrtc->Instance->TSSSR) & RTC_TSSSR_SS); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Fill the Date structure fields with the read parameters */ + sTimeStampDate->Year = 0; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if(Format == FORMAT_BIN) + { + /* Convert the TimeStamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + + /* Convert the DateTimeStamp structure parameters to Binary format */ + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + } + + /* Clear the TIMESTAMP Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + + return HAL_OK; +} + +/** + * @brief Sets Tamper + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper: Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TAMPER(sTamper->Tamper)); + assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + assert_param(IS_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) + { + /* Configure the RTC_TAFCR register */ + sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE; + } + else + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ + (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ + (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ + (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ + (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE); +#else + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Trigger)); + + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG); + +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + hrtc->Instance->TAFCR |= tmpreg; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets Tamper with interrupt. + * @note By calling this API we force the tamper interrupt for all tampers. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper: Pointer to RTC Tamper. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TAMPER(sTamper->Tamper)); + assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + assert_param(IS_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Configure the tamper trigger */ + if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) + { + sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE; + } + else + { + sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1); + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ + (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ + (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ + (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ + (uint32_t)RTC_TAFCR_TAMPPUDIS); +#else + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger); + + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPIE); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + hrtc->Instance->TAFCR |= tmpreg; + + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates Tamper. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Tamper: Selected tamper pin. + * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + assert_param(IS_TAMPER(Tamper)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the selected Tamper pin */ + hrtc->Instance->TAFCR &= (uint32_t)~Tamper; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles TimeStamp interrupt request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) + { + /* TIMESTAMP callback */ + HAL_RTCEx_TimeStampEventCallback(hrtc); + + /* Clear the TIMESTAMP interrupt pending bit */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + } + } + + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) + { + /* Tamper callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + } + } + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) + { + /* Tamper callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + } + } + + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP3)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) + { + /* Tamper callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + } + } +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Clear the EXTI s Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief TimeStamp callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 1 callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Tamper 2 callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 3 callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @brief This function handles TimeStamp polling request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + { + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) + { + /* Clear the TIMESTAMP OverRun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); + + /* Change TIMESTAMP state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles Tamper1 Polling. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief This function handles Tamper2 Polling. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles Tamper3 Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group5 RTC Wake-up functions + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets wake up timer. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param WakeUpCounter: Wake up counter + * @param WakeUpClock: Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets wake up timer with interrupt + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param WakeUpCounter: Wake up counter + * @param WakeUpClock: Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + + /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + + EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + + /* Configure the Interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates wake up timer counter. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + + tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets wake up timer counter. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Counter value + */ +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + /* Get the counter value */ + return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); +} + +/** + * @brief This function handles Wake Up Timer interrupt request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) + { + /* WAKEUPTIMER callback */ + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); + + /* Clear the WAKEUPTIMER interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + } + } + + /* Clear the EXTI s line Flag for RTC WakeUpTimer */ + __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Wake Up Timer callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles Wake Up Timer Polling. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group7 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extension Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Writes a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Sets the Coarse calibration parameters. + (+) Deactivates the Coarse calibration parameters + (+) Sets the Smooth calibration parameters. + (+) Configures the Synchronization Shift Control Settings. + (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enables the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enables the Bypass Shadow feature. + (+) Disables the Bypass Shadow feature. + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @brief Sets the Coarse calibration parameters. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param CalibSign: Specifies the sign of the coarse calibration value. + * This parameter can be one of the following values : + * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive + * @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative + * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). + * + * @note This Calibration value should be between 0 and 63 when using negative + * sign with a 2-ppm step. + * + * @note This Calibration value should be between 0 and 126 when using positive + * sign with a 4-ppm step. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_SIGN(CalibSign)); + assert_param(IS_RTC_CALIB_VALUE(Value)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Enable the Coarse Calibration */ + __HAL_RTC_COARSE_CALIB_ENABLE(hrtc); + + /* Set the coarse calibration value */ + hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates the Coarse calibration parameters. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Enable the Coarse Calibration */ + __HAL_RTC_COARSE_CALIB_DISABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Sets the Smooth calibration parameters. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * This parameter can be can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s. + * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmouthCalibMinusPulsesValue must be equal to 0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* check if a calibration is pending*/ + if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + { + tickstart = HAL_GetTick(); + + /* check if a calibration is pending*/ + while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the Smooth calibration settings */ + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS: Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed*/ + while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Check if the reference clock detection is disabled */ + if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + + /* Wait for synchro */ + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param CalibOutput : Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +#else +/** + * @brief Configure the Calibration Pinout (RTC_CALIB). + * @param hrtc : RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc) +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +{ +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Clear flags before config */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)CalibOutput; +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + + __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Enables the RTC reference clock detection. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) +/** + * @brief Enables the Bypass Shadow feature. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set the BYPSHAD bit */ + hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disables the Bypass Shadow feature. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Reset the BYPSHAD bit */ + hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group8 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alram B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ + +/** + * @brief Alarm B callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles AlarmB Polling request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c new file mode 100644 index 000000000..c47de33de --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c @@ -0,0 +1,3439 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_sd.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief SD card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (SD) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by + the user in HAL_SD_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDIO memories which uses the HAL + SDIO driver functions to interface with SD and uSD cards devices. + It is used as follows: + + (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API: + (##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE(); + (##) SDIO pins configuration for SD card + (+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE(); + (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() + and HAL_SD_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDIO and DMA interrupt priorities using functions + HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority + (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT() + and __HAL_SD_SDIO_DISABLE_IT() inside the communication process. + (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT() + and __HAL_SD_SDIO_CLEAR_IT() + (#) At this stage, you can perform SD read/write/erase operations after SD card initialization + + + *** SD Card Initialization and configuration *** + ================================================ + [..] + To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + the SD Card and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Apply the SD Card initialization process at 400KHz and check the SD Card + type (Standard Capacity or High Capacity). You can change or adapt this + frequency by adjusting the "ClockDiv" field. + The SD Card frequency (SDIO_CK) is computed as follows: + + SDIO_CK = SDIOCLK / (ClockDiv + 2) + + In initialization mode and according to the SD Card standard, + make sure that the SDIO_CK frequency doesn't exceed 400KHz. + + (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo + structure. This structure provide also ready computed SD Card capacity + and Block size. + + -@- These information are stored in SD handle structure in case of future use. + + (#) Configure the SD Card Data transfer frequency. By Default, the card transfer + frequency is set to 48MHz / (SDIO_TRANSFER_CLK_DIV + 2) = 8MHz. You can change or adapt this frequency by adjusting + the "ClockDiv" field. + The SD Card frequency (SDIO_CK) is computed as follows: + + SDIO_CK = SDIOCLK / (ClockDiv + 2) + + In transfer mode and according to the SD Card standard, make sure that the + SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDIO + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. + + (#) Select the corresponding SD Card according to the address read with the step 2. + + (#) Configure the SD Card in wide bus mode: 4-bits data. + + *** SD Card Read operation *** + ============================== + [..] + (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). + This function support only 512-byte block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + + (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). + This function support only 512-byte block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to call the function HAL_SD_CheckReadOperation(), to insure + that the read transfer is done correctly in both DMA and SD sides. + + *** SD Card Write operation *** + =============================== + [..] + (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). + This function support only 512-byte block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + + (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). + This function support only 512-byte block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure + that the write transfer is done correctly in both DMA and SD sides. + + *** SD card status *** + ====================== + [..] + (+) At any time, you can check the SD Card status and get the SD card state + by using the HAL_SD_GetStatus() function. This function checks first if the + SD card is still connected and then get the internal SD Card transfer state. + (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() + function. + + *** SD HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SD HAL driver. + + (+) __HAL_SD_SDIO_ENABLE : Enable the SD device + (+) __HAL_SD_SDIO_DISABLE : Disable the SD device + (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer + (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer + (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt + (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt + (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not + (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags + + (@) You can refer to the SD HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup SD SD + * @brief SD HAL module driver + * @{ + */ + +#ifdef HAL_SD_MODULE_ENABLED +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup SD_Private_Define SD Private Define + * @{ + */ + +/** + * @brief SDIO Static flags, TimeOut, FIFO Address + */ +#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ + SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ + SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ + SDIO_FLAG_DBCKEND)) + +#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) + +/** + * @brief Mask for errors Card Status R1 (OCR Register) + */ +#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) +#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) +#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) +#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) +#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) +#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) +#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) +#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) +#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) +#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) +#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) +#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) +#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) +#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) +#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) +#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) +#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) +#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) +#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) +#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) + +/** + * @brief Masks for R6 Response + */ +#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) +#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) +#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) + +#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) +#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) +#define SD_STD_CAPACITY ((uint32_t)0x00000000) +#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) + +#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) +#define SD_ALLZERO ((uint32_t)0x00000000) + +#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) +#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) +#define SD_CARD_LOCKED ((uint32_t)0x02000000) + +#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) +#define SD_0TO7BITS ((uint32_t)0x000000FF) +#define SD_8TO15BITS ((uint32_t)0x0000FF00) +#define SD_16TO23BITS ((uint32_t)0x00FF0000) +#define SD_24TO31BITS ((uint32_t)0xFF000000) +#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) + +#define SD_HALFFIFO ((uint32_t)0x00000008) +#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) + +/** + * @brief Command Class Supported + */ +#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) +#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) +#define SD_CCCC_ERASE ((uint32_t)0x00000020) + +/** + * @brief Following commands are SD Card Specific commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ + +static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr); +static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus); +static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD); +static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA); +static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd); +static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma); +static void SD_DMA_RxError(DMA_HandleTypeDef *hdma); +static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma); +static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** @defgroup SD_Exported_Functions SD Exported Functions + * @{ + */ + +/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the SD + card device to be ready for use. + + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SD card according to the specified parameters in the + SD_HandleTypeDef and create the associated handle. + * @param hsd: SD handle + * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information + * @retval HAL SD error state + */ +HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo) +{ + __IO HAL_SD_ErrorTypedef errorstate = SD_OK; + SD_InitTypeDef tmpinit; + + /* Initialize the low level hardware (MSP) */ + HAL_SD_MspInit(hsd); + + /* Default SDIO peripheral configuration for SD card initialization */ + tmpinit.ClockEdge = SDIO_CLOCK_EDGE_RISING; + tmpinit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + tmpinit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + tmpinit.BusWide = SDIO_BUS_WIDE_1B; + tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + tmpinit.ClockDiv = SDIO_INIT_CLK_DIV; + + /* Initialize SDIO peripheral interface with default configuration */ + SDIO_Init(hsd->Instance, tmpinit); + + /* Identify card operating voltage */ + errorstate = SD_PowerON(hsd); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Initialize the present SDIO card(s) and put them in idle state */ + errorstate = SD_Initialize_Cards(hsd); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Read CSD/CID MSD registers */ + errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo); + + if (errorstate == SD_OK) + { + /* Select the Card */ + errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16)); + } + + /* Configure SDIO peripheral interface */ + SDIO_Init(hsd->Instance, hsd->Init); + + return errorstate; +} + +/** + * @brief De-Initializes the SD card. + * @param hsd: SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) +{ + + /* Set SD power state to off */ + SD_PowerOFF(hsd); + + /* De-Initialize the MSP layer */ + HAL_SD_MspDeInit(hsd); + + return HAL_OK; +} + + +/** + * @brief Initializes the SD MSP. + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize SD MSP. + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group2 IO operation functions + * @brief Data transfer functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to SD card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @param hsd: SD handle + * @param pReadBuffer: pointer to the buffer that will contain the received data + * @param ReadAddr: Address from where data is to be read + * @param BlockSize: SD card Data block size + * This parameter should be 512 + * @param NumberOfBlocks: Number of SD blocks to read + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + if (hsd->CardType == HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + ReadAddr /= 512; + } + + /* Set Block Size for Card */ + sdio_cmdinitstructure.Argument = (uint32_t) BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; + sdio_datainitstructure.DataBlockSize = (uint32_t)(9 << 4); + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + if(NumberOfBlocks > 1) + { + /* Send CMD18 READ_MULT_BLOCK with argument data address */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; + } + else + { + /* Send CMD17 READ_SINGLE_BLOCK */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + } + + sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1) + { + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Poll on SDIO flags */ + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) + { + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + { + /* Read data from SDIO Rx FIFO */ + for (count = 0; count < 8; count++) + { + *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); + } + + tempbuff += 8; + } + } + } + else + { + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* In case of single block transfer, no need of stop transfer at all */ + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) + { + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + { + /* Read data from SDIO Rx FIFO */ + for (count = 0; count < 8; count++) + { + *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); + } + + tempbuff += 8; + } + } + } + + /* Send stop transmission command in case of multiblock read */ + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1)) + { + if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\ + (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ + (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + { + /* Send stop transmission command */ + errorstate = HAL_SD_StopTransfer(hsd); + } + } + + /* Get error state */ + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + + errorstate = SD_DATA_TIMEOUT; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + + errorstate = SD_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); + + errorstate = SD_RX_OVERRUN; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + + errorstate = SD_START_BIT_ERR; + + return errorstate; + } + else + { + /* No error flag set */ + } + + count = SD_DATATIMEOUT; + + /* Empty FIFO if there is still any data */ + while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) + { + *tempbuff = SDIO_ReadFIFO(hsd->Instance); + tempbuff++; + count--; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + return errorstate; +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @param hsd: SD handle + * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit + * @param WriteAddr: Address from where data is to be written + * @param BlockSize: SD card Data block size + * This parameter should be 512. + * @param NumberOfBlocks: Number of SD blocks to write + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0; + uint32_t *tempbuff = (uint32_t *)pWriteBuffer; + uint8_t cardstate = 0; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + if (hsd->CardType == HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + WriteAddr /= 512; + } + + /* Set Block Size for Card */ + sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + + if (errorstate != SD_OK) + { + return errorstate; + } + + if(NumberOfBlocks > 1) + { + /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + } + else + { + /* Send CMD24 WRITE_SINGLE_BLOCK */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; + } + + sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + if(NumberOfBlocks > 1) + { + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); + } + else + { + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); + } + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Set total number of bytes to write */ + totalnumberofbytes = NumberOfBlocks * BlockSize; + + /* Configure the SD DPSM (Data Path State Machine) */ + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + /* Write block(s) in polling mode */ + if(NumberOfBlocks > 1) + { + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) + { + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) + { + if ((totalnumberofbytes - bytestransferred) < 32) + { + restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); + + /* Write data to SDIO Tx FIFO */ + for (count = 0; count < restwords; count++) + { + SDIO_WriteFIFO(hsd->Instance, tempbuff); + tempbuff++; + bytestransferred += 4; + } + } + else + { + /* Write data to SDIO Tx FIFO */ + for (count = 0; count < 8; count++) + { + SDIO_WriteFIFO(hsd->Instance, (tempbuff + count)); + } + + tempbuff += 8; + bytestransferred += 32; + } + } + } + } + else + { + /* In case of single data block transfer no need of stop command at all */ + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) + { + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) + { + if ((totalnumberofbytes - bytestransferred) < 32) + { + restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); + + /* Write data to SDIO Tx FIFO */ + for (count = 0; count < restwords; count++) + { + SDIO_WriteFIFO(hsd->Instance, tempbuff); + tempbuff++; + bytestransferred += 4; + } + } + else + { + /* Write data to SDIO Tx FIFO */ + for (count = 0; count < 8; count++) + { + SDIO_WriteFIFO(hsd->Instance, (tempbuff + count)); + } + + tempbuff += 8; + bytestransferred += 32; + } + } + } + } + + /* Send stop transmission command in case of multiblock write */ + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1)) + { + if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ + (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + { + /* Send stop transmission command */ + errorstate = HAL_SD_StopTransfer(hsd); + } + } + + /* Get error state */ + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + + errorstate = SD_DATA_TIMEOUT; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + + errorstate = SD_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR); + + errorstate = SD_TX_UNDERRUN; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + + errorstate = SD_START_BIT_ERR; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* Wait till the card is in programming state */ + errorstate = SD_IsCardProgramming(hsd, &cardstate); + + while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + { + errorstate = SD_IsCardProgramming(hsd, &cardstate); + } + + return errorstate; +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by the function HAL_SD_CheckReadOperation() + * to check the completion of the read process + * @param hsd: SD handle + * @param pReadBuffer: Pointer to the buffer that will contain the received data + * @param ReadAddr: Address from where data is to be read + * @param BlockSize: SD card Data block size + * This paramater should be 512. + * @param NumberOfBlocks: Number of blocks to read. + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + /* Initialize handle flags */ + hsd->SdTransferCplt = 0; + hsd->DmaTransferCplt = 0; + hsd->SdTransferErr = SD_OK; + + /* Initialize SD Read operation */ + if(NumberOfBlocks > 1) + { + hsd->SdOperation = SD_READ_MULTIPLE_BLOCK; + } + else + { + hsd->SdOperation = SD_READ_SINGLE_BLOCK; + } + + /* Enable transfer interrupts */ + __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\ + SDIO_IT_DTIMEOUT |\ + SDIO_IT_DATAEND |\ + SDIO_IT_RXOVERR |\ + SDIO_IT_STBITERR)); + + /* Enable SDIO DMA transfer */ + __HAL_SD_SDIO_DMA_ENABLE(); + + /* Configure DMA user callbacks */ + hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt; + hsd->hdmarx->XferErrorCallback = SD_DMA_RxError; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)); + + if (hsd->CardType == HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + ReadAddr /= 512; + } + + /* Set Block Size for Card */ + sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + /* Check number of blocks command */ + if(NumberOfBlocks > 1) + { + /* Send CMD18 READ_MULT_BLOCK with argument data address */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; + } + else + { + /* Send CMD17 READ_SINGLE_BLOCK */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + } + + sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + if(NumberOfBlocks > 1) + { + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + } + else + { + errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); + } + + /* Update the SD transfer error in SD handle */ + hsd->SdTransferErr = errorstate; + + return errorstate; +} + + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by the function HAL_SD_CheckWriteOperation() + * to check the completion of the write process (by SD current status polling). + * @param hsd: SD handle + * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit + * @param WriteAddr: Address from where data is to be read + * @param BlockSize: the SD card Data block size + * This parameter should be 512. + * @param NumberOfBlocks: Number of blocks to write + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + /* Initialize handle flags */ + hsd->SdTransferCplt = 0; + hsd->DmaTransferCplt = 0; + hsd->SdTransferErr = SD_OK; + + /* Initialize SD Write operation */ + if(NumberOfBlocks > 1) + { + hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK; + } + else + { + hsd->SdOperation = SD_WRITE_SINGLE_BLOCK; + } + + /* Enable transfer interrupts */ + __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\ + SDIO_IT_DTIMEOUT |\ + SDIO_IT_DATAEND |\ + SDIO_IT_TXUNDERR |\ + SDIO_IT_STBITERR)); + + /* Configure DMA user callbacks */ + hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt; + hsd->hdmatx->XferErrorCallback = SD_DMA_TxError; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)); + + /* Enable SDIO DMA transfer */ + __HAL_SD_SDIO_DMA_ENABLE(); + + if (hsd->CardType == HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + WriteAddr /= 512; + } + + /* Set Block Size for Card */ + sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Check number of blocks command */ + if(NumberOfBlocks <= 1) + { + /* Send CMD24 WRITE_SINGLE_BLOCK */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; + } + else + { + /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + } + + sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + if(NumberOfBlocks > 1) + { + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); + } + else + { + errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); + } + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + hsd->SdTransferErr = errorstate; + + return errorstate; +} + +/** + * @brief This function waits until the SD DMA data read transfer is finished. + * This API should be called after HAL_SD_ReadBlocks_DMA() function + * to insure that all data sent by the card is already transferred by the + * DMA controller. + * @param hsd: SD handle + * @param Timeout: Timeout duration + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t timeout = Timeout; + uint32_t tmp1, tmp2; + HAL_SD_ErrorTypedef tmp3; + + /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ + tmp1 = hsd->DmaTransferCplt; + tmp2 = hsd->SdTransferCplt; + tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; + + while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0)) + { + tmp1 = hsd->DmaTransferCplt; + tmp2 = hsd->SdTransferCplt; + tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; + timeout--; + } + + timeout = Timeout; + + /* Wait until the Rx transfer is no longer active */ + while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0)) + { + timeout--; + } + + /* Send stop command in multiblock read */ + if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK) + { + errorstate = HAL_SD_StopTransfer(hsd); + } + + if ((timeout == 0) && (errorstate == SD_OK)) + { + errorstate = SD_DATA_TIMEOUT; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* Return error state */ + if (hsd->SdTransferErr != SD_OK) + { + return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); + } + + return errorstate; +} + +/** + * @brief This function waits until the SD DMA data write transfer is finished. + * This API should be called after HAL_SD_WriteBlocks_DMA() function + * to insure that all data sent by the card is already transferred by the + * DMA controller. + * @param hsd: SD handle + * @param Timeout: Timeout duration + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t timeout = Timeout; + uint32_t tmp1, tmp2; + HAL_SD_ErrorTypedef tmp3; + + /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ + tmp1 = hsd->DmaTransferCplt; + tmp2 = hsd->SdTransferCplt; + tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; + + while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0)) + { + tmp1 = hsd->DmaTransferCplt; + tmp2 = hsd->SdTransferCplt; + tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; + timeout--; + } + + timeout = Timeout; + + /* Wait until the Tx transfer is no longer active */ + while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT)) && (timeout > 0)) + { + timeout--; + } + + /* Send stop command in multiblock write */ + if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK) + { + errorstate = HAL_SD_StopTransfer(hsd); + } + + if ((timeout == 0) && (errorstate == SD_OK)) + { + errorstate = SD_DATA_TIMEOUT; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* Return error state */ + if (hsd->SdTransferErr != SD_OK) + { + return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); + } + + /* Wait until write is complete */ + while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK) + { + } + + return errorstate; +} + +/** + * @brief Erases the specified memory area of the given SD card. + * @param hsd: SD handle + * @param startaddr: Start byte address + * @param endaddr: End byte address + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + + uint32_t delay = 0; + __IO uint32_t maxdelay = 0; + uint8_t cardstate = 0; + + /* Check if the card command class supports erase command */ + if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0) + { + errorstate = SD_REQUEST_NOT_APPLICABLE; + + return errorstate; + } + + /* Get max delay value */ + maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2); + + if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + { + errorstate = SD_LOCK_UNLOCK_FAILED; + + return errorstate; + } + + /* Get start and end block for high capacity cards */ + if (hsd->CardType == HIGH_CAPACITY_SD_CARD) + { + startaddr /= 512; + endaddr /= 512; + } + + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ + (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + { + /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ + sdio_cmdinitstructure.Argument =(uint32_t)startaddr; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ + sdio_cmdinitstructure.Argument = (uint32_t)endaddr; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END); + + if (errorstate != SD_OK) + { + return errorstate; + } + } + + /* Send CMD38 ERASE */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_ERASE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE); + + if (errorstate != SD_OK) + { + return errorstate; + } + + for (; delay < maxdelay; delay++) + { + } + + /* Wait untill the card is in programming state */ + errorstate = SD_IsCardProgramming(hsd, &cardstate); + + delay = SD_DATATIMEOUT; + + while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + { + errorstate = SD_IsCardProgramming(hsd, &cardstate); + delay--; + } + + return errorstate; +} + +/** + * @brief This function handles SD card interrupt request. + * @param hsd: SD handle + * @retval None + */ +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) +{ + /* Check for SDIO interrupt flags */ + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND); + + /* SD transfer is complete */ + hsd->SdTransferCplt = 1; + + /* No transfer error */ + hsd->SdTransferErr = SD_OK; + + HAL_SD_XferCpltCallback(hsd); + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + + hsd->SdTransferErr = SD_DATA_CRC_FAIL; + + HAL_SD_XferErrorCallback(hsd); + + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + + hsd->SdTransferErr = SD_DATA_TIMEOUT; + + HAL_SD_XferErrorCallback(hsd); + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); + + hsd->SdTransferErr = SD_RX_OVERRUN; + + HAL_SD_XferErrorCallback(hsd); + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR); + + hsd->SdTransferErr = SD_TX_UNDERRUN; + + HAL_SD_XferErrorCallback(hsd); + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + + hsd->SdTransferErr = SD_START_BIT_ERR; + + HAL_SD_XferErrorCallback(hsd); + } + else + { + /* No error flag set */ + } + + /* Disable all SDIO peripheral interrupt sources */ + __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\ + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\ + SDIO_IT_RXOVERR | SDIO_IT_STBITERR); +} + + +/** + * @brief SD end of transfer callback. + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SD Transfer Error callback. + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @brief SD Transfer complete Rx callback in non blocking mode. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_DMA_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SD DMA transfer complete Rx error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_DMA_RxErrorCallback could be implemented in the user file + */ +} + +/** + * @brief SD Transfer complete Tx callback in non blocking mode. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_DMA_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SD DMA transfer complete error Tx callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_DMA_TxErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SD card + operations. + +@endverbatim + * @{ + */ + +/** + * @brief Returns information about specific card. + * @param hsd: SD handle + * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that + * contains all SD cardinformation + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t tmp = 0; + + pCardInfo->CardType = (uint8_t)(hsd->CardType); + pCardInfo->RCA = (uint16_t)(hsd->RCA); + + /* Byte 0 */ + tmp = (hsd->CSD[0] & 0xFF000000) >> 24; + pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); + pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); + pCardInfo->SD_csd.Reserved1 = tmp & 0x03; + + /* Byte 1 */ + tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; + pCardInfo->SD_csd.TAAC = (uint8_t)tmp; + + /* Byte 2 */ + tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; + pCardInfo->SD_csd.NSAC = (uint8_t)tmp; + + /* Byte 3 */ + tmp = hsd->CSD[0] & 0x000000FF; + pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp; + + /* Byte 4 */ + tmp = (hsd->CSD[1] & 0xFF000000) >> 24; + pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4); + + /* Byte 5 */ + tmp = (hsd->CSD[1] & 0x00FF0000) >> 16; + pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); + pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F); + + /* Byte 6 */ + tmp = (hsd->CSD[1] & 0x0000FF00) >> 8; + pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); + pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); + pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); + pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4); + pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */ + + if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0)) + { + pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; + + /* Byte 7 */ + tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); + pCardInfo->SD_csd.DeviceSize |= (tmp) << 2; + + /* Byte 8 */ + tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); + pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + + pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + + /* Byte 9 */ + tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); + pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + /* Byte 10 */ + tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); + pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + + pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ; + pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2)); + pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen); + pCardInfo->CardCapacity *= pCardInfo->CardBlockSize; + } + else if (hsd->CardType == HIGH_CAPACITY_SD_CARD) + { + /* Byte 7 */ + tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); + pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; + + /* Byte 8 */ + tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); + + pCardInfo->SD_csd.DeviceSize |= (tmp << 8); + + /* Byte 9 */ + tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); + + pCardInfo->SD_csd.DeviceSize |= (tmp); + + /* Byte 10 */ + tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); + + pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024; + pCardInfo->CardBlockSize = 512; + } + else + { + /* Not supported card type */ + errorstate = SD_ERROR; + } + + pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; + pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + /* Byte 11 */ + tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); + pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; + pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); + + /* Byte 12 */ + tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24); + pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; + pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; + pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; + pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + + /* Byte 13 */ + tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); + pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; + pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; + pCardInfo->SD_csd.Reserved3 = 0; + pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01); + + /* Byte 14 */ + tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); + pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; + pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; + pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; + pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; + pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; + pCardInfo->SD_csd.ECC = (tmp & 0x03); + + /* Byte 15 */ + tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); + pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; + pCardInfo->SD_csd.Reserved4 = 1; + + /* Byte 0 */ + tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24); + pCardInfo->SD_cid.ManufacturerID = tmp; + + /* Byte 1 */ + tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); + pCardInfo->SD_cid.OEM_AppliID = tmp << 8; + + /* Byte 2 */ + tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); + pCardInfo->SD_cid.OEM_AppliID |= tmp; + + /* Byte 3 */ + tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); + pCardInfo->SD_cid.ProdName1 = tmp << 24; + + /* Byte 4 */ + tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24); + pCardInfo->SD_cid.ProdName1 |= tmp << 16; + + /* Byte 5 */ + tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); + pCardInfo->SD_cid.ProdName1 |= tmp << 8; + + /* Byte 6 */ + tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); + pCardInfo->SD_cid.ProdName1 |= tmp; + + /* Byte 7 */ + tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); + pCardInfo->SD_cid.ProdName2 = tmp; + + /* Byte 8 */ + tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24); + pCardInfo->SD_cid.ProdRev = tmp; + + /* Byte 9 */ + tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); + pCardInfo->SD_cid.ProdSN = tmp << 24; + + /* Byte 10 */ + tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); + pCardInfo->SD_cid.ProdSN |= tmp << 16; + + /* Byte 11 */ + tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); + pCardInfo->SD_cid.ProdSN |= tmp << 8; + + /* Byte 12 */ + tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24); + pCardInfo->SD_cid.ProdSN |= tmp; + + /* Byte 13 */ + tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); + pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; + pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; + + /* Byte 14 */ + tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); + pCardInfo->SD_cid.ManufactDate |= tmp; + + /* Byte 15 */ + tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); + pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; + pCardInfo->SD_cid.Reserved2 = 1; + + return errorstate; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hsd: SD handle + * @param WideMode: Specifies the SD card wide bus mode + * This parameter can be one of the following values: + * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC) + * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer + * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + SDIO_InitTypeDef init; + + /* MMC Card does not support this feature */ + if (hsd->CardType == MULTIMEDIA_CARD) + { + errorstate = SD_UNSUPPORTED_FEATURE; + } + else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ + (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + { + if (WideMode == SDIO_BUS_WIDE_8B) + { + errorstate = SD_UNSUPPORTED_FEATURE; + } + else if (WideMode == SDIO_BUS_WIDE_4B) + { + errorstate = SD_WideBus_Enable(hsd); + } + else if (WideMode == SDIO_BUS_WIDE_1B) + { + errorstate = SD_WideBus_Disable(hsd); + } + else + { + /* WideMode is not a valid argument*/ + errorstate = SD_INVALID_PARAMETER; + } + + if (errorstate == SD_OK) + { + /* Configure the SDIO peripheral */ + init.ClockEdge = hsd->Init.ClockEdge; + init.ClockBypass = hsd->Init.ClockBypass; + init.ClockPowerSave = hsd->Init.ClockPowerSave; + init.BusWide = WideMode; + init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + init.ClockDiv = hsd->Init.ClockDiv; + + /* Configure SDIO peripheral interface */ + SDIO_Init(hsd->Instance, init); + } + else + { + /* An error occured while enabling/disabling the wide bus*/ + } + } + else + { + /* Not supported card type */ + errorstate = SD_ERROR; + } + + return errorstate; +} + +/** + * @brief Aborts an ongoing data transfer. + * @param hsd: SD handle + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + + /* Send CMD12 STOP_TRANSMISSION */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION); + + return errorstate; +} + +/** + * @brief Switches the SD card to High Speed mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDIOCK clock between 67 and 75 MHz + * @param hsd: SD handle + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + + uint8_t SD_hs[64] = {0}; + uint32_t SD_scr[2] = {0, 0}; + uint32_t SD_SPEC = 0 ; + uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; + + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, SD_scr); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Test the Version supported by the card*/ + SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000); + + if (SD_SPEC != SD_ALLZERO) + { + /* Set Block Size for Card */ + sdio_cmdinitstructure.Argument = (uint32_t)64; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = 64; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + /* Send CMD6 switch mode */ + sdio_cmdinitstructure.Argument = 0x80FFFF01; + sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH); + + if (errorstate != SD_OK) + { + return errorstate; + } + + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) + { + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + { + for (count = 0; count < 8; count++) + { + *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); + } + + tempbuff += 8; + } + } + + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + + errorstate = SD_DATA_TIMEOUT; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + + errorstate = SD_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); + + errorstate = SD_RX_OVERRUN; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + + errorstate = SD_START_BIT_ERR; + + return errorstate; + } + else + { + /* No error flag set */ + } + + count = SD_DATATIMEOUT; + + while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) + { + *tempbuff = SDIO_ReadFIFO(hsd->Instance); + tempbuff++; + count--; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* Test if the switch mode HS is ok */ + if ((SD_hs[13]& 2) != 2) + { + errorstate = SD_UNSUPPORTED_FEATURE; + } + } + + return errorstate; +} + +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in runtime the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the current SD card's status. + * @param hsd: SD handle + * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * SD Status register) + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t count = 0; + + /* Check SD response */ + if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + { + errorstate = SD_LOCK_UNLOCK_FAILED; + + return errorstate; + } + + /* Set block size for card if it is not equal to current block size for card */ + sdio_cmdinitstructure.Argument = 64; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Send CMD55 */ + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = 64; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STAUS; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Get status data */ + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) + { + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + { + for (count = 0; count < 8; count++) + { + *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance); + } + + pSDstatus += 8; + } + } + + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + + errorstate = SD_DATA_TIMEOUT; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + + errorstate = SD_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); + + errorstate = SD_RX_OVERRUN; + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + + errorstate = SD_START_BIT_ERR; + + return errorstate; + } + else + { + /* No error flag set */ + } + + count = SD_DATATIMEOUT; + while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) + { + *pSDstatus = SDIO_ReadFIFO(hsd->Instance); + pSDstatus++; + count--; + } + + /* Clear all the static status flags*/ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + return errorstate; +} + +/** + * @brief Gets the current sd card data status. + * @param hsd: SD handle + * @retval Data Transfer state + */ +HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER; + + /* Get SD card state */ + cardstate = SD_GetState(hsd); + + /* Find SD status according to card state*/ + if (cardstate == SD_CARD_TRANSFER) + { + return SD_TRANSFER_OK; + } + else if(cardstate == SD_CARD_ERROR) + { + return SD_TRANSFER_ERROR; + } + else + { + return SD_TRANSFER_BUSY; + } +} + +/** + * @brief Gets the SD card status. + * @param hsd: SD handle + * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that + * will contain the SD card status information + * @retval SD Card error state + */ +HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t tmp = 0; + uint32_t sd_status[16]; + + errorstate = HAL_SD_SendSDStatus(hsd, sd_status); + + if (errorstate != SD_OK) + { + return errorstate; + } + + /* Byte 0 */ + tmp = (sd_status[0] & 0xC0) >> 6; + pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp; + + /* Byte 0 */ + tmp = (sd_status[0] & 0x20) >> 5; + pCardStatus->SECURED_MODE = (uint8_t)tmp; + + /* Byte 2 */ + tmp = (sd_status[2] & 0xFF); + pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8); + + /* Byte 3 */ + tmp = (sd_status[3] & 0xFF); + pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp; + + /* Byte 4 */ + tmp = (sd_status[4] & 0xFF); + pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24); + + /* Byte 5 */ + tmp = (sd_status[5] & 0xFF); + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16); + + /* Byte 6 */ + tmp = (sd_status[6] & 0xFF); + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8); + + /* Byte 7 */ + tmp = (sd_status[7] & 0xFF); + pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp; + + /* Byte 8 */ + tmp = (sd_status[8] & 0xFF); + pCardStatus->SPEED_CLASS = (uint8_t)tmp; + + /* Byte 9 */ + tmp = (sd_status[9] & 0xFF); + pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; + + /* Byte 10 */ + tmp = (sd_status[10] & 0xF0) >> 4; + pCardStatus->AU_SIZE = (uint8_t)tmp; + + /* Byte 11 */ + tmp = (sd_status[11] & 0xFF); + pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8); + + /* Byte 12 */ + tmp = (sd_status[12] & 0xFF); + pCardStatus->ERASE_SIZE |= (uint8_t)tmp; + + /* Byte 13 */ + tmp = (sd_status[13] & 0xFC) >> 2; + pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; + + /* Byte 13 */ + tmp = (sd_status[13] & 0x3); + pCardStatus->ERASE_OFFSET = (uint8_t)tmp; + + return errorstate; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief SD DMA transfer complete Rx callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* DMA transfer is complete */ + hsd->DmaTransferCplt = 1; + + /* Wait until SD transfer is complete */ + while(hsd->SdTransferCplt == 0) + { + } + + /* Transfer complete user callback */ + HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); +} + +/** + * @brief SD DMA transfer Error Rx callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Transfer complete user callback */ + HAL_SD_DMA_RxErrorCallback(hsd->hdmarx); +} + +/** + * @brief SD DMA transfer complete Tx callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* DMA transfer is complete */ + hsd->DmaTransferCplt = 1; + + /* Wait until SD transfer is complete */ + while(hsd->SdTransferCplt == 0) + { + } + + /* Transfer complete user callback */ + HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); +} + +/** + * @brief SD DMA transfer Error Tx callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SD_DMA_TxError(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Transfer complete user callback */ + HAL_SD_DMA_TxErrorCallback(hsd->hdmatx); +} + +/** + * @brief Returns the SD current state. + * @param hsd: SD handle + * @retval SD card current state + */ +static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd) +{ + uint32_t resp1 = 0; + + if (SD_SendStatus(hsd, &resp1) != SD_OK) + { + return SD_CARD_ERROR; + } + else + { + return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); + } +} + +/** + * @brief Initializes all cards or single card as the case may be Card(s) come + * into standby state. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint16_t sd_rca = 1; + + if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */ + { + errorstate = SD_REQUEST_NOT_APPLICABLE; + + return errorstate; + } + + if(hsd->CardType != SECURE_DIGITAL_IO_CARD) + { + /* Send CMD2 ALL_SEND_CID */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp2Error(hsd); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Get Card identification number data */ + hsd->CID[0] = SDIO_GetResponse(SDIO_RESP1); + hsd->CID[1] = SDIO_GetResponse(SDIO_RESP2); + hsd->CID[2] = SDIO_GetResponse(SDIO_RESP3); + hsd->CID[3] = SDIO_GetResponse(SDIO_RESP4); + } + + if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ + (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + { + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca); + + if(errorstate != SD_OK) + { + return errorstate; + } + } + + if (hsd->CardType != SECURE_DIGITAL_IO_CARD) + { + /* Get the SD card RCA */ + hsd->RCA = sd_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp2Error(hsd); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Get Card Specific Data */ + hsd->CSD[0] = SDIO_GetResponse(SDIO_RESP1); + hsd->CSD[1] = SDIO_GetResponse(SDIO_RESP2); + hsd->CSD[2] = SDIO_GetResponse(SDIO_RESP3); + hsd->CSD[3] = SDIO_GetResponse(SDIO_RESP4); + } + + /* All cards are initialized */ + return errorstate; +} + +/** + * @brief Selects od Deselects the corresponding card. + * @param hsd: SD handle + * @param addr: Address of the card to be selected + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + + /* Send CMD7 SDIO_SEL_DESEL_CARD */ + sdio_cmdinitstructure.Argument = (uint32_t)addr; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD); + + return errorstate; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores SD information that will be needed in future + * in the SD handle. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + __IO HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t response = 0, count = 0, validvoltage = 0; + uint32_t sdtype = SD_STD_CAPACITY; + + /* Power ON Sequence -------------------------------------------------------*/ + /* Disable SDIO Clock */ + __HAL_SD_SDIO_DISABLE(); + + /* Set Power State to ON */ + SDIO_PowerState_ON(hsd->Instance); + + /* Enable SDIO Clock */ + __HAL_SD_SDIO_ENABLE(); + + /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/ + /* No CMD response required */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_NO; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdError(hsd); + + if(errorstate != SD_OK) + { + /* CMD Response TimeOut (wait for CMDSENT flag) */ + return errorstate; + } + + /* CMD8: SEND_IF_COND ------------------------------------------------------*/ + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + sdio_cmdinitstructure.Argument = SD_CHECK_PATTERN; + sdio_cmdinitstructure.CmdIndex = SD_SDIO_SEND_IF_COND; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp7Error(hsd); + + if (errorstate == SD_OK) + { + /* SD Card 2.0 */ + hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; + sdtype = SD_HIGH_CAPACITY; + } + + /* Send CMD55 */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + + /* If errorstate is Command TimeOut, it is a MMC card */ + /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + if(errorstate == SD_OK) + { + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) + { + + /* SEND CMD55 APP_CMD with RCA as 0 */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Send CMD41 */ + sdio_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp3Error(hsd); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Get command response */ + response = SDIO_GetResponse(SDIO_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31) == 1) ? 1 : 0); + + count++; + } + + if(count >= SD_MAX_VOLT_TRIAL) + { + errorstate = SD_INVALID_VOLTRANGE; + + return errorstate; + } + + if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->CardType = HIGH_CAPACITY_SD_CARD; + } + + } /* else MMC Card */ + + return errorstate; +} + +/** + * @brief Turns the SDIO output signals off. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + + /* Set Power State to OFF */ + SDIO_PowerState_OFF(hsd->Instance); + + return errorstate; +} + +/** + * @brief Returns the current card's status. + * @param hsd: SD handle + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + + if(pCardStatus == NULL) + { + errorstate = SD_INVALID_PARAMETER; + + return errorstate; + } + + /* Send Status command */ + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Get SD card status */ + *pCardStatus = SDIO_GetResponse(SDIO_RESP1); + + return errorstate; +} + +/** + * @brief Checks for error conditions for CMD0. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t timeout, tmp; + + timeout = SDIO_CMD0TIMEOUT; + + tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT); + + while((timeout > 0) && (!tmp)) + { + tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT); + timeout--; + } + + if(timeout == 0) + { + errorstate = SD_CMD_RSP_TIMEOUT; + return errorstate; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + return errorstate; +} + +/** + * @brief Checks for error conditions for R7 response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) +{ + HAL_SD_ErrorTypedef errorstate = SD_ERROR; + uint32_t timeout = SDIO_CMD0TIMEOUT, tmp; + + tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); + + while((!tmp) && (timeout > 0)) + { + tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); + timeout--; + } + + tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + + if((timeout == 0) || tmp) + { + /* Card is not V2.0 compliant or card does not support the set voltage range */ + errorstate = SD_CMD_RSP_TIMEOUT; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + + return errorstate; + } + + if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND)) + { + /* Card is SD V2.0 compliant */ + errorstate = SD_OK; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND); + + return errorstate; + } + + return errorstate; +} + +/** + * @brief Checks for error conditions for R1 response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t response_r1; + + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) + { + } + + if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) + { + errorstate = SD_CMD_RSP_TIMEOUT; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + + return errorstate; + } + else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) + { + errorstate = SD_CMD_CRC_FAIL; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) + { + errorstate = SD_ILLEGAL_CMD; + + return errorstate; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* We have received response, retrieve it for analysis */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + { + return errorstate; + } + + if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) + { + return(SD_ADDR_OUT_OF_RANGE); + } + + if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) + { + return(SD_ADDR_MISALIGNED); + } + + if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) + { + return(SD_BLOCK_LEN_ERR); + } + + if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) + { + return(SD_ERASE_SEQ_ERR); + } + + if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) + { + return(SD_BAD_ERASE_PARAM); + } + + if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) + { + return(SD_WRITE_PROT_VIOLATION); + } + + if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) + { + return(SD_LOCK_UNLOCK_FAILED); + } + + if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) + { + return(SD_CARD_ECC_FAILED); + } + + if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) + { + return(SD_CC_ERROR); + } + + if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) + { + return(SD_STREAM_READ_UNDERRUN); + } + + if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) + { + return(SD_STREAM_WRITE_OVERRUN); + } + + if((response_r1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) + { + return(SD_CID_CSD_OVERWRITE); + } + + if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) + { + return(SD_WP_ERASE_SKIP); + } + + if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) + { + return(SD_CARD_ECC_DISABLED); + } + + if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) + { + return(SD_ERASE_RESET); + } + + if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) + { + return(SD_AKE_SEQ_ERROR); + } + + return errorstate; +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + + while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) + { + } + + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) + { + errorstate = SD_CMD_RSP_TIMEOUT; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + + return errorstate; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + return errorstate; +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + + while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) + { + } + + if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) + { + errorstate = SD_CMD_RSP_TIMEOUT; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + + return errorstate; + } + else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) + { + errorstate = SD_CMD_CRC_FAIL; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + return errorstate; +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA) +{ + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t response_r1; + + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) + { + } + + if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) + { + errorstate = SD_CMD_RSP_TIMEOUT; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + + return errorstate; + } + else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) + { + errorstate = SD_CMD_CRC_FAIL; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) + { + errorstate = SD_ILLEGAL_CMD; + + return errorstate; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* We have received response, retrieve it. */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO) + { + *pRCA = (uint16_t) (response_r1 >> 16); + + return errorstate; + } + + if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + return errorstate; +} + +/** + * @brief Enables the SDIO wide bus mode. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + + uint32_t scr[2] = {0, 0}; + + if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + { + errorstate = SD_LOCK_UNLOCK_FAILED; + + return errorstate; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* If requested card supports wide bus operation */ + if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA.*/ + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + sdio_cmdinitstructure.Argument = 2; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); + + if(errorstate != SD_OK) + { + return errorstate; + } + + return errorstate; + } + else + { + errorstate = SD_REQUEST_NOT_APPLICABLE; + + return errorstate; + } +} + +/** + * @brief Disables the SDIO wide bus mode. + * @param hsd: SD handle + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + + uint32_t scr[2] = {0, 0}; + + if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + { + errorstate = SD_LOCK_UNLOCK_FAILED; + + return errorstate; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* If requested card supports 1 bit mode operation */ + if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA */ + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); + + if(errorstate != SD_OK) + { + return errorstate; + } + + return errorstate; + } + else + { + errorstate = SD_REQUEST_NOT_APPLICABLE; + + return errorstate; + } +} + + +/** + * @brief Finds the SD card SCR register value. + * @param hsd: SD handle + * @param pSCR: pointer to the buffer that will contain the SCR value + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + SDIO_DataInitTypeDef sdio_datainitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t index = 0; + uint32_t tempscr[2] = {0, 0}; + + /* Set Block Size To 8 Bytes */ + /* Send CMD55 APP_CMD with argument as card's RCA */ + sdio_cmdinitstructure.Argument = (uint32_t)8; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + + if(errorstate != SD_OK) + { + return errorstate; + } + + /* Send CMD55 APP_CMD with argument as card's RCA */ + sdio_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); + + if(errorstate != SD_OK) + { + return errorstate; + } + sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; + sdio_datainitstructure.DataLength = 8; + sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; + sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; + SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + sdio_cmdinitstructure.Argument = 0; + sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + /* Check for error conditions */ + errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR); + + if(errorstate != SD_OK) + { + return errorstate; + } + + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) + { + if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) + { + *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance); + index++; + } + } + + if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + + errorstate = SD_DATA_TIMEOUT; + + return errorstate; + } + else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); + + errorstate = SD_DATA_CRC_FAIL; + + return errorstate; + } + else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); + + errorstate = SD_RX_OVERRUN; + + return errorstate; + } + else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) + { + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + + errorstate = SD_START_BIT_ERR; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\ + ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); + + *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\ + ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); + + return errorstate; +} + +/** + * @brief Checks if the SD card is in programming state. + * @param hsd: SD handle + * @param pStatus: pointer to the variable that will contain the SD card state + * @retval SD Card error state + */ +static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus) +{ + SDIO_CmdInitTypeDef sdio_cmdinitstructure; + HAL_SD_ErrorTypedef errorstate = SD_OK; + __IO uint32_t responseR1 = 0; + + sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); + sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; + sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; + sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; + sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + + while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) + { + } + + if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) + { + errorstate = SD_CMD_RSP_TIMEOUT; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + + return errorstate; + } + else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) + { + errorstate = SD_CMD_CRC_FAIL; + + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Check response received is of desired command */ + if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS) + { + errorstate = SD_ILLEGAL_CMD; + + return errorstate; + } + + /* Clear all the static flags */ + __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + + /* We have received response, retrieve it for analysis */ + responseR1 = SDIO_GetResponse(SDIO_RESP1); + + /* Find out card status */ + *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F); + + if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + { + return errorstate; + } + + if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) + { + return(SD_ADDR_OUT_OF_RANGE); + } + + if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) + { + return(SD_ADDR_MISALIGNED); + } + + if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) + { + return(SD_BLOCK_LEN_ERR); + } + + if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) + { + return(SD_ERASE_SEQ_ERR); + } + + if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) + { + return(SD_BAD_ERASE_PARAM); + } + + if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) + { + return(SD_WRITE_PROT_VIOLATION); + } + + if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) + { + return(SD_LOCK_UNLOCK_FAILED); + } + + if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) + { + return(SD_CARD_ECC_FAILED); + } + + if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) + { + return(SD_CC_ERROR); + } + + if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) + { + return(SD_STREAM_READ_UNDERRUN); + } + + if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) + { + return(SD_STREAM_WRITE_OVERRUN); + } + + if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) + { + return(SD_CID_CSD_OVERWRITE); + } + + if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) + { + return(SD_WP_ERASE_SKIP); + } + + if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) + { + return(SD_CARD_ECC_DISABLED); + } + + if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) + { + return(SD_ERASE_RESET); + } + + if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) + { + return(SD_AKE_SEQ_ERROR); + } + + return errorstate; +} + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c new file mode 100644 index 000000000..198e68699 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c @@ -0,0 +1,1411 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_smartcard.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief SMARTCARD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the SMARTCARD peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMARTCARD HAL driver can be used as follows: + + (#) Declare a SMARTCARD_HandleTypeDef handle structure. + (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: + (##) Enable the USARTx interface clock. + (##) SMARTCARD pins configuration: + (+++) Enable the clock for the SMARTCARD GPIOs. + (+++) Configure these SMARTCARD pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() + and HAL_SMARTCARD_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() + and HAL_SMARTCARD_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. + + (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SMARTCARD_MspInit(&hsc) API. + + -@@- The specific SMARTCARD interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback + + *** SMARTCARD HAL driver macros list *** + ======================================== + [..] + Below the list of most used macros in SMARTCARD HAL driver. + + (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not + (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag + (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt + + [..] + (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup SMARTCARD SMARTCARD + * @brief HAL SMARTCARD module driver + * @{ + */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants + * @{ + */ +#define SMARTCARD_TIMEOUT_VALUE 22000 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ +static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc); +static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc); +static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc); +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions + * @{ + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in Smartcard mode. + [..] + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + [..] + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + [..] + (+) For the Smartcard mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length => Should be 9 bits (8 bits + parity) + (++) Stop Bit + (++) Parity: => Should be enabled + +-------------------------------------------------------------+ + | M bit | PCE bit | SMARTCARD frame | + |---------------------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + (++) Prescaler + (++) GuardTime + (++) NACKState: The Smartcard NACK state + + (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card: + (++) Word Length = 9 Bits + (++) 1.5 Stop Bit + (++) Even parity + (++) BaudRate = 12096 baud + (++) Tx and Rx enabled + [..] + Please refer to the ISO 7816-3 specification for more details. + + -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. + [..] + The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration + procedure (details for the procedure are available in reference manual (RM0038)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SmartCard mode according to the specified + * parameters in the SMARTCARD_HandleTypeDef and create the associated handle. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) +{ + /* Check the SMARTCARD handle allocation */ + if(hsc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); + assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState)); + + if(hsc->State == HAL_SMARTCARD_STATE_RESET) + { + /* Init the low level hardware */ + HAL_SMARTCARD_MspInit(hsc); + } + + hsc->State = HAL_SMARTCARD_STATE_BUSY; + + /* Set the Prescaler */ + MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler); + + /* Set the Guard Time */ + MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8)); + + /* Set the Smartcard Communication parameters */ + SMARTCARD_SetConfig(hsc); + + /* In SmartCard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN); + CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + + /* Enable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); + + /* Enable the SMARTCARD Framing Error Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); + + /* Enable the Peripharal */ + __HAL_SMARTCARD_ENABLE(hsc); + + /* Configure the Smartcard NACK state */ + MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState); + + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN); + + /* Initialize the SMARTCARD state*/ + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsc->State= HAL_SMARTCARD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SMARTCARD peripheral + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) +{ + /* Check the SMARTCARD handle allocation */ + if(hsc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); + + hsc->State = HAL_SMARTCARD_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_SMARTCARD_DISABLE(hsc); + + /* DeInit the low level hardware */ + HAL_SMARTCARD_MspDeInit(hsc); + + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsc->State = HAL_SMARTCARD_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsc); + + return HAL_OK; +} + +/** + * @brief SMARTCARD MSP Init. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ + __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspInit can be implemented in the user file + */ +} + +/** + * @brief SMARTCARD MSP DeInit. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ + __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. + + [..] + Smartcard is a single wire half duplex communication protocol. + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. The USART should be configured as: + - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + will be executed respectivelly at the end of the Transmit or Receive process + The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication + error is detected + + (#) Blocking mode APIs are : + (++) HAL_SMARTCARD_Transmit() + (++) HAL_SMARTCARD_Receive() + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_SMARTCARD_Transmit_IT() + (++) HAL_SMARTCARD_Receive_IT() + (++) HAL_SMARTCARD_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_SMARTCARD_Transmit_DMA() + (++) HAL_SMARTCARD_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_SMARTCARD_TxCpltCallback() + (++) HAL_SMARTCARD_RxCpltCallback() + (++) HAL_SMARTCARD_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsc); + + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + + hsc->TxXferSize = Size; + hsc->TxXferCount = Size; + while(hsc->TxXferCount > 0) + { + if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) + { + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pData; + WRITE_REG(hsc->Instance->DR, (*tmp & (uint16_t)0x01FF)); + if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) + { + pData +=2; + } + else + { + pData +=1; + } + } + else + { + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF)); + } + hsc->TxXferCount--; + } + + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsc); + + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + + hsc->RxXferSize = Size; + hsc->RxXferCount = Size; + /* Check the remain data to be received */ + while(hsc->RxXferCount > 0) + { + if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) + { + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pData; + if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) + { + *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF); + pData +=2; + } + else + { + *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF); + pData +=1; + } + } + else + { + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) + { + *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F); + } + } + hsc->RxXferCount--; + } + + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non-blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +{ + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsc); + + hsc->pTxBuffPtr = pData; + hsc->TxXferSize = Size; + hsc->TxXferCount = Size; + + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + + /* Enable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + /* Enable the SMARTCARD Transmit data register empty Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non-blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +{ + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsc); + + hsc->pRxBuffPtr = pData; + hsc->RxXferSize = Size; + hsc->RxXferCount = Size; + + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + + /* Enable the SMARTCARD Data Register not empty Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); + + /* Enable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non-blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsc); + + hsc->pTxBuffPtr = pData; + hsc->TxXferSize = Size; + hsc->TxXferCount = Size; + + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + + /* Set the SMARTCARD DMA transfer complete callback */ + hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; + + /* Set the DMA error callback */ + hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError; + + /* Enable the SMARTCARD transmit DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD CR3 register */ + SET_BIT(hsc->Instance->CR3,USART_CR3_DMAT); + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsc); + + hsc->pRxBuffPtr = pData; + hsc->RxXferSize = Size; + + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + + /* Set the SMARTCARD DMA transfer complete callback */ + hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; + + /* Set the DMA error callback */ + hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError; + + /* Enable the DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the SMARTCARD CR3 register */ + SET_BIT(hsc->Instance->CR3,USART_CR3_DMAR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles SMARTCARD interrupt request. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE); + /* SMARTCARD parity error interrupt occurred -----------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_SMARTCARD_CLEAR_PEFLAG(hsc); + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; + } + + tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); + /* SMARTCARD frame error interrupt occurred ------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_SMARTCARD_CLEAR_FEFLAG(hsc); + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; + } + + tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); + /* SMARTCARD noise error interrupt occurred ------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_SMARTCARD_CLEAR_NEFLAG(hsc); + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + } + + tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); + /* SMARTCARD Over-Run interrupt occurred ---------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + } + + tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE); + /* SMARTCARD in mode Receiver --------------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + SMARTCARD_Receive_IT(hsc); + } + + tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE); + /* SMARTCARD in mode Transmitter -----------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + SMARTCARD_Transmit_IT(hsc); + } + + tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC); + tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC); + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + SMARTCARD_EndTransmit_IT(hsc); + } + + /* Call the Error call Back in case of Errors */ + if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + { + /* Set the SMARTCARD state ready to be able to start again the process */ + hsc->State= HAL_SMARTCARD_STATE_READY; + HAL_SMARTCARD_ErrorCallback(hsc); + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ + __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SMARTCARD error callbacks. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ + __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_ErrorCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of SmartCard + communication process and also return Peripheral Errors occurred during communication process + (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state + of the SMARTCARD peripheral. + (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SMARTCARD state. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL state + */ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) +{ + return hsc->State; +} + +/** + * @brief Return the SMARTCARD error code + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD Error Code + */ +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) +{ + return hsc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @brief SMARTCARD Private functions + * @{ + */ +/** + * @brief DMA SMARTCARD transmit process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD CR3 register */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); + + /* Wait for SMARTCARD TC Flag */ + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + hsc->State = HAL_SMARTCARD_STATE_TIMEOUT; + HAL_SMARTCARD_ErrorCallback(hsc); + } + else + { + /* No Timeout */ + /* Check if a non-blocking receive process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } + HAL_SMARTCARD_TxCpltCallback(hsc); + } +} + +/** + * @brief DMA SMARTCARD receive process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_RxCpltCallback(hsc); +} + +/** + * @brief DMA SMARTCARD communication error callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->RxXferCount = 0; + hsc->TxXferCount = 0; + hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + hsc->State= HAL_SMARTCARD_STATE_READY; + + HAL_SMARTCARD_ErrorCallback(hsc); +} + +/** + * @brief This function handles SMARTCARD Communication Timeout. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param Flag: specifies the SMARTCARD flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE and RXNE interrupts for the interrupt process */ + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); + + hsc->State= HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE and RXNE interrupts for the interrupt process */ + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); + + hsc->State= HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Send an amount of data in non-blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + { + if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) + { + tmp = (uint16_t*) hsc->pTxBuffPtr; + WRITE_REG(hsc->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); + if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) + { + hsc->pTxBuffPtr += 2; + } + else + { + hsc->pTxBuffPtr += 1; + } + } + else + { + WRITE_REG(hsc->Instance->DR, (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF)); + } + + if(--hsc->TxXferCount == 0) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + /* Disable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); + + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_TxCpltCallback(hsmartcard); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) +{ + uint16_t* tmp = 0; + uint32_t tmp1 = 0; + + tmp1 = hsc->State; + if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + { + if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) + { + tmp = (uint16_t*) hsc->pRxBuffPtr; + if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) + { + *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF); + hsc->pRxBuffPtr += 2; + } + else + { + *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF); + hsc->pRxBuffPtr += 1; + } + } + else + { + if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) + { + *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); + } + else + { + *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F); + } + } + + if(--hsc->RxXferCount == 0) + { + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); + + /* Disable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); + + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); + + /* Check if a non-blocking transmit process is ongoing or not */ + if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + hsc->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_RxCpltCallback(hsc); + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the SMARTCARD peripheral. + * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) +{ + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); + assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity)); + assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase)); + assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); + assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate)); + assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)); + assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)); + assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity)); + assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode)); + assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState)); + + /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the + receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */ + CLEAR_BIT(hsc->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /*-------------------------- SMARTCARD CR2 Configuration ------------------------*/ + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/ + /* Set CPOL bit according to hsc->Init.CLKPolarity value */ + /* Set CPHA bit according to hsc->Init.CLKPhase value */ + /* Set LBCL bit according to hsc->Init.CLKLastBit value */ + MODIFY_REG(hsc->Instance->CR2, + ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)), + ((uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | hsc->Init.CLKPhase| hsc->Init.CLKLastBit)) ); + + /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */ + MODIFY_REG(hsc->Instance->CR2, USART_CR2_STOP,(uint32_t)(hsc->Init.StopBits)); + + /*-------------------------- SMARTCARD CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits */ + /* Configure the SMARTCARD Word Length, Parity and mode: + Set the M bits according to hsc->Init.WordLength value + Set PCE and PS bits according to hsc->Init.Parity value + Set TE and RE bits according to hsc->Init.Mode value */ + MODIFY_REG(hsc->Instance->CR1, + ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), + ((uint32_t)(hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode)) ); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Clear CTSE and RTSE bits */ + CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); + + /*-------------------------- USART BRR Configuration -----------------------*/ + if(hsc->Instance == USART1) + { + hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate); + } + else + { + hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate); + } +} + +/** + * @} + */ + +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c new file mode 100644 index 000000000..d481bb749 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c @@ -0,0 +1,2258 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_spi.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Channel + (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ + +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_TIMEOUT_VALUE 10 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ + +static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi); +static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi); +static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma); +static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ + + +__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + return HAL_ERROR; +} + +/** + * @brief DeInitializes the SPI peripheral + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief SPI MSP Init + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + { + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspInit could be implenetd in the user file + */ +} + +/** + * @brief SPI MSP DeInit + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode APIs are : + (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_TransmitReceive() in full duplex mode + + (#) Non Blocking mode API's with Interrupt are : + (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_TransmitReceive_IT()in full duplex mode + (++) HAL_SPI_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode + (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_SPI_TxCpltCallback() + (++) HAL_SPI_RxCpltCallback() + (++) HAL_SPI_TxRxCpltCallback() + (++) HAL_SPI_TxHalfCpltCallback() + (++) HAL_SPI_RxHalfCpltCallback() + (++) HAL_SPI_TxRxHalfCpltCallback() + (++) HAL_SPI_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Configure communication direction : 1Line */ + SPI_1LINE_TX(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Transmit data in 16 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Receive data in 16 Bit mode */ + else + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set to read data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Receive last data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive last data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* Wait until RXNE flag is set: CRC Received */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + + /* Read CRC to Flush RXNE flag */ + tmpreg = hspi->Instance->DR; + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Receive the last byte */ + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + } + } + + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); + }else + { + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->RxISR = &SPI_RxISR; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size ; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->RxISR = &SPI_2LinesRxISR; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = (uint8_t*)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->pRxBuffPtr = (uint8_t*)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + } + else + { + hspi->hdmatx->XferErrorCallback = NULL; + } + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Channel */ + if(hspi->hdmatx != NULL) + { + HAL_DMA_Abort(hspi->hdmatx); + } + /* Abort the SPI DMA rx Channel */ + if(hspi->hdmarx != NULL) + { + HAL_DMA_Abort(hspi->hdmarx); + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Tramitter ---------------------------------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) + { + /* SPI CRC error interrupt occurred ---------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + /* SPI Mode Fault error interrupt occurred --------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Overrun error interrupt occurred -----------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + { + if(hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + } + + /* SPI Frame error interrupt occurred -------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + /* Call the Error call Back in case of Errors */ + if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) + { + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief SPI error callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* NOTE : - This function Should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback() could be implenetd in the user file. + - The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI state + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + return hspi->State; +} + +/** + * @brief Return the SPI error code + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI Error Code + */ +HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + + +/** @addtogroup SPI_Private_Functions + * @{ + */ + + + /** + * @brief Interrupt Handler to close Tx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval void + */ +static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi) +{ + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE )); + + /* Disable ERR interrupt if Receive process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) + { + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Tx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to transmit amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval void + */ +static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + } + /* Transmit data in 16 Bit mode */ + else + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + } + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* calculate and transfer CRC on Tx line */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + SPI_TxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to close Rx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval void + */ +static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC to reset RXNE flag */ + tmpreg = hspi->Instance->DR; + + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + } + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); + + /* if Transmit process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Rx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to receive amount of data in 2Lines mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval void + */ +static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + if(hspi->RxXferCount==0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to receive amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval void + */ +static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + { + /* Set CRC Next to calculate CRC on Rx side */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + if(hspi->RxXferCount == 0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief DMA SPI transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal Mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + hspi->TxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC */ + tmpreg = hspi->Instance->DR; + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + /* Check if CRC is done on going (RXNE flag set) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) + { + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI half transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_RxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI Half transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxRxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + hspi->State= HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief This function handles SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: Flag status to check: RESET or set + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi_ex.c new file mode 100644 index 000000000..642c2c532 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi_ex.c @@ -0,0 +1,153 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_spi_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief Extended SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities SPI extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); + + /* Configure : NSS management */ + hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; + +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c new file mode 100644 index 000000000..ce10a4a43 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c @@ -0,0 +1,681 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_sram.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief SRAM HAL module driver. + * This file provides a generic firmware to drive SRAM memories + * mounted as external device. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SRAM memories. It uses the FSMC layer functions to interface + with SRAM devices. + The following sequence should be followed to configure the FSMC to interface + with SRAM/PSRAM memories: + + (#) Declare a SRAM_HandleTypeDef handle structure, for example: + SRAM_HandleTypeDef hsram; and: + + (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SRAM device + + (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined + base register instance for NOR or SRAM extended mode + + (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended + mode timings; for example: + FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() + (##) Control register configuration using the FSMC NORSRAM interface function + FSMC_NORSRAM_Init() + (##) Timing register configuration using the FSMC NORSRAM interface function + FSMC_NORSRAM_Timing_Init() + (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function + FSMC_NORSRAM_Extended_Timing_Init() + (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE() + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access + (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ + HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation + + (#) You can continuously monitor the SRAM device HAL state by calling the function + HAL_SRAM_GetState() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup SRAM SRAM + * @brief SRAM driver modules + * @{ + */ +#ifdef HAL_SRAM_MODULE_ENABLED + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ + +/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### SRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize/de-initialize + the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SRAM device initialization sequence + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param Timing: Pointer to SRAM control timing structure + * @param ExtTiming: Pointer to SRAM extended mode timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) +{ + /* Check the SRAM handle parameter */ + if(hsram == NULL) + { + return HAL_ERROR; + } + + if(hsram->State == HAL_SRAM_STATE_RESET) + { + /* Initialize the low level hardware (MSP) */ + HAL_SRAM_MspInit(hsram); + } + + /* Initialize SRAM control Interface */ + FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); + + /* Initialize SRAM timing Interface */ + FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); + + /* Initialize SRAM extended mode timing Interface */ + FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); + + /* Enable the NORSRAM device */ + __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); + + return HAL_OK; +} + +/** + * @brief Performs the SRAM device De-initialization sequence. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) +{ + /* De-Initialize the low level hardware (MSP) */ + HAL_SRAM_MspDeInit(hsram); + + /* Configure the SRAM registers with their reset values */ + FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + + hsram->State = HAL_SRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief SRAM MSP Init. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SRAM MSP DeInit. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit buffer from SRAM memory. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint8_t * psramaddress = (uint8_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for(; BufferSize != 0; BufferSize--) + { + *pDstBuffer = *(__IO uint8_t *)psramaddress; + pDstBuffer++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Writes 8-bit buffer to SRAM memory. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint8_t * psramaddress = (uint8_t *)pAddress; + + /* Check the SRAM controller state */ + if(hsram->State == HAL_SRAM_STATE_PROTECTED) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint8_t *)psramaddress = *pSrcBuffer; + pSrcBuffer++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Reads 16-bit buffer from SRAM memory. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint16_t * psramaddress = (uint16_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for(; BufferSize != 0; BufferSize--) + { + *pDstBuffer = *(__IO uint16_t *)psramaddress; + pDstBuffer++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Writes 16-bit buffer to SRAM memory. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint16_t * psramaddress = (uint16_t *)pAddress; + + /* Check the SRAM controller state */ + if(hsram->State == HAL_SRAM_STATE_PROTECTED) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint16_t *)psramaddress = *pSrcBuffer; + pSrcBuffer++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Reads 32-bit buffer from SRAM memory. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for(; BufferSize != 0; BufferSize--) + { + *pDstBuffer = *(__IO uint32_t *)pAddress; + pDstBuffer++; + pAddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Writes 32-bit buffer to SRAM memory. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + /* Check the SRAM controller state */ + if(hsram->State == HAL_SRAM_STATE_PROTECTED) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint32_t *)pAddress = *pSrcBuffer; + pSrcBuffer++; + pAddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SRAM memory using DMA transfer. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to read start address + * @param pDstBuffer: Pointer to destination buffer + * @param BufferSize: Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Writes a Words data buffer to SRAM memory using DMA transfer. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress: Pointer to write start address + * @param pSrcBuffer: Pointer to source buffer to write + * @param BufferSize: Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + /* Check the SRAM controller state */ + if(hsram->State == HAL_SRAM_STATE_PROTECTED) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### SRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SRAM write operation. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) +{ + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Enable write operation */ + FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief Disables dynamically SRAM write operation. + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) +{ + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Disable write operation */ + FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SRAM controller state + * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL state + */ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) +{ + return hsram->State; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +#endif /* HAL_SRAM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c new file mode 100644 index 000000000..ada3b3f93 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c @@ -0,0 +1,5039 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_tim.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + Time Base Initialization + * + Time Base Start + * + Time Base Start Interruption + * + Time Base Start DMA + * + Time Output Compare/PWM Initialization + * + Time Output Compare/PWM Channel Configuration + * + Time Output Compare/PWM Start + * + Time Output Compare/PWM Start Interruption + * + Time Output Compare/PWM Start DMA + * + Time Input Capture Initialization + * + Time Input Capture Channel Configuration + * + Time Input Capture Start + * + Time Input Capture Start Interruption + * + Time Input Capture Start DMA + * + Time One Pulse Initialization + * + Time One Pulse Channel Configuration + * + Time One Pulse Start + * + Time Encoder Interface Initialization + * + Time Encoder Interface Start + * + Time Encoder Interface Start Interruption + * + Time Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + Time OCRef clear configuration + * + Time External Clock configuration + * + Time Master and Slave synchronization configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental (quadrature) encoder + + ##### How to use this driver ##### +================================================================================ + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); + +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); + +static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAError(DMA_HandleTypeDef *hdma); +static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); + +/** + * @} + */ + +/* External functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim: TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim : TIM handle + * @param pData: The source Buffer address. + * @param Length: The length of data to be transferred from memory to peripheral. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim : TIM handle + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions + * @brief Time Output Compare functions + * +@verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim: TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim : TIM OC handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData: The source Buffer address. + * @param Length: The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim : TIM Output Compare handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions + * @brief Time PWM functions + * +@verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM OPWM. + (+) De-initialize the TIM PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim: TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim : TIM handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim : TIM handle + * @param Channel : TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData: The source Buffer address. + * @param Length: The length of data to be transferred from memory to TIM peripheral + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if(((uint32_t)pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); + + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions + * @brief Time Input Capture functions + * +@verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim: TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM INput Capture MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement on in DMA mode. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData: The destination Buffer address. + * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement on in DMA mode. + * @param htim : TIM Input Capture handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions + * @brief Time One Pulse functions + * +@verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM OnePulse handle + * @param OnePulseMode: Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim: TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim : TIM One Pulse handle + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions + * @brief Time Encoder functions + * +@verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and create the associated handle. + * @param htim: TIM Encoder Interface handle + * @param sConfig: TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Reset the SMS bits */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + + /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= (~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F)); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); + tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim: TIM Encoder handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param pData1: The destination Buffer address for IC1. + * @param pData2: The destination Buffer address for IC2. + * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + } + break; + + case TIM_CHANNEL_ALL: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); + + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim : TIM Encoder Interface handle + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if(Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + else if(Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim: TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + HAL_TIM_PeriodElapsedCallback(htim); + } + } + /* TIM Trigger detection event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + HAL_TIM_TriggerCallback(htim); + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim: TIM Output Compare handle + * @param sConfig: TIM Output Compare configuration structure + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim: TIM IC handle + * @param sConfig: TIM Input Capture configuration structure + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim: TIM handle + * @param sConfig: TIM PWM configuration structure + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + } + break; + + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + } + break; + + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim: TIM One Pulse handle + * @param sConfig: TIM One Pulse configuration structure + * @param OutputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if(OutputChannel != InputChannel) + { + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Ouput compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + } + break; + default: + break; + } + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim: TIM handle + * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write + * This parameters can be on of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_DCR + * @param BurstRequestSrc: TIM DMA Request sources + * This parameters can be on of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer: The Buffer address. + * @param BurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t* BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0 ) && (BurstLength > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + } + break; + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim: TIM handle + * @param BurstRequestSrc: TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim: TIM handle + * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read + * This parameters can be on of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @param BurstRequestSrc: TIM DMA Request sources + * This parameters can be on of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer: The Buffer address. + * @param BurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((BurstBuffer == 0 ) && (BurstLength > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC1: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC2: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC3: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_CC4: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + case TIM_DMA_TRIGGER: + { + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + } + break; + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = BurstBaseAddress | BurstLength; + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim: TIM handle + * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim: TIM handle + * @param EventSource: specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note TBC can only generate an update event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim: TIM handle + * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* Clear the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + + } + break; + + case TIM_CLEARINPUTSOURCE_OCREFCLR: + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + } + break; + + default: + break; + + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; + } + else + { + /* Disable the Ocref clear feature for Channel 1 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + } + } + break; + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; + } + else + { + /* Disable the Ocref clear feature for Channel 2 */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + } + } + break; + case TIM_CHANNEL_3: + { + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; + } + else + { + /* Disable the Ocref clear feature for Channel 3 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + } + } + break; + case TIM_CHANNEL_4: + { + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + if(sClearInputConfig->ClearInputState != RESET) + { + /* Enable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; + } + else + { + /* Disable the Ocref clear feature for Channel 4 */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + } + } + break; + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim: TIM handle + * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + /* Reset the SMS and TS Bits */ + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + break; + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + } + break; + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + } + break; + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + } + break; + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + } + break; + case TIM_CLOCKSOURCE_ITR0: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); + } + break; + case TIM_CLOCKSOURCE_ITR1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); + } + break; + case TIM_CLOCKSOURCE_ITR2: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); + } + break; + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); + } + break; + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim: TIM handle. + * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim: TIM handle. + * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + + } + break; + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_ITR0: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR1: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR2: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim: TIM handle. + * @param Channel : TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0; + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) Timer Period elapsed callback + (+) Timer Output Compare callback + (+) Timer Input capture callback + (+) Timer Trigger callback + (+) Timer Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ + +} +/** + * @brief Output Compare callback in non blocking mode + * @param htim : TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} +/** + * @brief Input Capture callback in non blocking mode + * @param htim : TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base state + * @param htim: TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC state + * @param htim: TIM Ouput Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM state + * @param htim: TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture state + * @param htim: TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode state + * @param htim: TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode state + * @param htim: TIM Encoder handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @addtogroup TIM_Private_Functions + * @{ + */ + + +/** + * @brief TIM DMA error callback + * @param hdma : pointer to DMA handle. + * @retval None + */ +static void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_ErrorCallback(htim); +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_PWM_PulseFinishedCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_IC_CaptureCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_PeriodElapsedCallback(htim); +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma : pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + + HAL_TIM_TriggerCallback(htim); +} + +/** + * @brief Time Base configuration + * @param TIMx: TIM periheral + * @param Structure: TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1 = 0; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = (uint32_t)Structure->Prescaler; + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediatly */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config: The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config: The ouput configuration structure + * @retval None + */ +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4); + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config: The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8); + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config: The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx = 0; + uint32_t tmpccer = 0; + uint32_t tmpcr2 = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12); + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= (TIM_ICFilter << 4); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= (TIM_ICPolarity << 8); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0; + uint32_t tmpccer = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= (TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= (TIM_ICPolarity << 12); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) +{ + uint32_t tmpsmcr = 0; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. + * @retval None + */ +static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = (uint16_t)(TIM_CCER_CC1E << Channel); + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << Channel); +} + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ + + + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c new file mode 100644 index 000000000..8c40bfd15 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c @@ -0,0 +1,260 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_tim_ex.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer extension peripheral: + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extension features include: + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Timer remapping capabilities configuration + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIM in master mode. + * @param htim: TIM handle. + * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the MMS Bits */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; + + /* Reset the MSM Bit */ + htim->Instance->SMCR &= ~TIM_SMCR_MSM; + /* Set or Reset the MSM Bit */ + htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM2/TIM3/TIM9/TIM10/TIM11 Remapping input capabilities. + * @param htim: TIM handle. + * @param Remap: specifies the TIM remapping source. + * This parameter is a combination of the following values depending on TIM instance. + * + * For TIM2, the parameter can have the following values: + * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC + * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO + * + * For TIM3, the parameter can have the following values: + * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC + * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO + * + * For TIM9, the parameter is a combination of 2 fields (field1 | field2): + * field1 can have the following values: + * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO + * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O + * field2 can have the following values: + * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO + * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock + * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO + * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO + * + * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): + * field1 can have the following values: + * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP + * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI + * field2 can have the following values: + * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock + * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO + * field3 can have the following values: + * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO + * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock + * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock + * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt + * + * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): + * field1 can have the following values: + * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP + * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI + * field2 can have the following values: + * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock + * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO + * field3 can have the following values: + * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO + * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock + * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock + * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(htim->Instance,Remap)); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extension Callbacks functions + * @brief Extension Callbacks functions + * +@verbatim + ============================================================================== + ##### Extension Callbacks functions ##### + ============================================================================== + [..] + This section provides Extension TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extension Peripheral State functions + * @brief Extension Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extension Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c new file mode 100644 index 000000000..e154e944f --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c @@ -0,0 +1,1974 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_uart.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (##) Enable the USARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the huart Init structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. + + (#) For the Multi-Processor mode, initialize the UART registers by calling + the HAL_MultiProcessor_Init() API. + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit + and receive process. + + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed + HAL_UART_MspInit() API. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_UART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + + *** UART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in UART HAL driver. + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART HAL module driver + * @brief HAL UART module driver + * @{ + */ +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define UART_TIMEOUT_VALUE 22000 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +static void UART_SetConfig (UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Methode + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs + follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor + configuration procedures (details for the procedures are available in reference manual (RM0038)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the UART mode according to the specified parameters in + * the UART_InitTypeDef and create the associated handle. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->State= HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + huart->Instance->CR3 |= USART_CR3_HDSEL; + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->State= HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the LIN mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param BreakDetectLength: Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection + * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In LIN mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + huart->Instance->CR2 &= ~(USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + huart->Instance->CR2 |= USART_CR2_LINEN; + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->State= HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the Multi-Processor mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Address: UART node address + * @param WakeUpMethod: specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg UART_WAKEUPMETHOD_IDLELINE: Wakeup by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wakeup by an address mark + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance capabilities */ + assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance)); + + /* Check the Address & wake up method parameters */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + assert_param(IS_UART_ADDRESS(Address)); + + if(huart->State == HAL_UART_STATE_RESET) + { + /* Init the low level hardware */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In Multi-Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, Address); + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->State= HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the UART peripheral. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if(huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->State = HAL_UART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief UART MSP Init. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ + __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_MspInit could be implemented in the user file + */ +} + +/** + * @brief UART MSP DeInit. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ + __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or receive process. + The HAL_UART_ErrorCallback() user callback will be executed when + a communication error is detected. + + (#) Blocking mode APIs are: + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non Blocking mode APIs with Interrupt are: + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non Blocking mode functions with DMA are: + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in non blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + [..] + (@) In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX + can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp; + uint32_t tmp1 = 0; + + tmp1 = huart->State; + if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX)) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a non-blocking receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + while(huart->TxXferCount > 0) + { + huart->TxXferCount--; + if(huart->Init.WordLength == UART_WORDLENGTH_9B) + { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pData; + huart->Instance->DR = (*tmp & (uint16_t)0x01FF); + if(huart->Init.Parity == UART_PARITY_NONE) + { + pData +=2; + } + else + { + pData +=1; + } + } + else + { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + huart->Instance->DR = (*pData++ & (uint8_t)0xFF); + } + } + + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Check if a non-blocking receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp; + uint32_t tmp1 = 0; + + tmp1 = huart->State; + if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a non-blocking transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Check the remain data to be received */ + while(huart->RxXferCount > 0) + { + huart->RxXferCount--; + if(huart->Init.WordLength == UART_WORDLENGTH_9B) + { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pData ; + if(huart->Init.Parity == UART_PARITY_NONE) + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + pData +=2; + } + else + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); + pData +=1; + } + + } + else + { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if(huart->Init.Parity == UART_PARITY_NONE) + { + *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + + } + } + + /* Check if a non-blocking transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t tmp = 0; + + tmp = huart->State; + if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t tmp = 0; + + tmp = huart->State; + if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + uint32_t tmp1 = 0; + + tmp1 = huart->State; + if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Enable the UART transmit DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 |= USART_CR3_DMAT; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData: Pointer to data buffer + * @param Size: Amount of data to be received + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + uint32_t tmp1 = 0; + + tmp1 = huart->State; + if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Check if a transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + huart->State = HAL_UART_STATE_BUSY_TX_RX; + } + else + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Enable the DMA channel */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + huart->Instance->CR3 |= USART_CR3_DMAR; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + /* Disable the UART DMA Tx request */ + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + } + else if(huart->State == HAL_UART_STATE_BUSY_RX) + { + /* Disable the UART DMA Rx request */ + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + else if (huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + /* Disable the UART DMA Tx & Rx requests */ + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + if(huart->State == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + huart->Instance->CR3 |= USART_CR3_DMAT; + } + else if(huart->State == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); + /* Enable the UART DMA Rx request */ + huart->Instance->CR3 |= USART_CR3_DMAR; + } + else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); + /* Enable the UART DMA Tx & Rx request */ + huart->Instance->CR3 |= USART_CR3_DMAT; + huart->Instance->CR3 |= USART_CR3_DMAR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Disable the UART Tx/Rx DMA requests */ + huart->Instance->CR3 &= ~USART_CR3_DMAT; + huart->Instance->CR3 &= ~USART_CR3_DMAR; + + /* Abort the UART DMA tx channel */ + if(huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + /* Abort the UART DMA rx channel */ + if(huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + + huart->State = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE); + /* UART parity error interrupt occurred ------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_UART_CLEAR_PEFLAG(huart); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); + /* UART frame error interrupt occurred -------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_UART_CLEAR_FEFLAG(huart); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); + /* UART noise error interrupt occurred -------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_UART_CLEAR_NEFLAG(huart); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); + /* UART Over-Run interrupt occurred ----------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_UART_CLEAR_OREFLAG(huart); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE); + /* UART in mode Receiver ---------------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + UART_Receive_IT(huart); + } + + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE); + /* UART in mode Transmitter ------------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + UART_Transmit_IT(huart); + } + + tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC); + tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC); + /* UART in mode Transmitter end --------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + UART_EndTransmit_IT(huart); + } + + if(huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Set the UART state ready to be able to start again the process */ + huart->State = HAL_UART_STATE_READY; + + HAL_UART_ErrorCallback(huart); + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ + __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ + __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief UART error callbacks. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ + __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. + (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. + (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. + (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode + (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode + +@endverbatim + * @{ + */ + +/** + * @brief Transmits break characters. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Send break characters */ + huart->Instance->CR1 |= USART_CR1_SBK; + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enters the UART in mute mode. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + huart->Instance->CR1 |= USART_CR1_RWU; + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Exits the UART mute mode: wake up software. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU); + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART transmitter and disables the UART receiver. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_TE; + + /* Write to USART CR1 */ + huart->Instance->CR1 = (uint32_t)tmpreg; + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART receiver and disables the UART transmitter. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->State = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_RE; + + /* Write to USART CR1 */ + huart->Instance->CR1 = (uint32_t)tmpreg; + + huart->State = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. + (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + return huart->State; +} + +/** +* @brief Return the UART error code +* @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. +* @retval UART Error Code +*/ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @brief UART Private functions + * @{ + */ +/** + * @brief DMA UART transmit process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode*/ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + huart->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + /* Wait for UART TC Flag */ + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + huart->State = HAL_UART_STATE_TIMEOUT; + HAL_UART_ErrorCallback(huart); + } + else + { + /* No Timeout */ + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + HAL_UART_TxCpltCallback(huart); + } + } + /* DMA Circular mode */ + else + { + HAL_UART_TxCpltCallback(huart); + } +} + +/** + * @brief DMA UART transmit process half complete callback + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_UART_TxHalfCpltCallback(huart); +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode*/ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + huart->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + + /* Check if a transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + } + HAL_UART_RxCpltCallback(huart); +} + +/** + * @brief DMA UART receive process half complete callback + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_UART_RxHalfCpltCallback(huart); +} + +/** + * @brief DMA UART communication error callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + huart->RxXferCount = 0; + huart->TxXferCount = 0; + huart->State= HAL_UART_STATE_READY; + huart->ErrorCode |= HAL_UART_ERROR_DMA; + HAL_UART_ErrorCallback(huart); +} + +/** + * @brief This function handles UART Communication Timeout. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Flag: specifies the UART flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State= HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_UART_GET_FLAG(huart, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State= HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint32_t tmp1 = 0; + + tmp1 = huart->State; + if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) + { + if(huart->Init.WordLength == UART_WORDLENGTH_9B) + { + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + if(huart->Init.Parity == UART_PARITY_NONE) + { + huart->pTxBuffPtr += 2; + } + else + { + huart->pTxBuffPtr += 1; + } + } + else + { + huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); + } + + if(--huart->TxXferCount == 0) + { + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; + } + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint32_t tmp1 = 0; + + tmp1 = huart->State; + if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) + { + if(huart->Init.WordLength == UART_WORDLENGTH_9B) + { + tmp = (uint16_t*) huart->pRxBuffPtr; + if(huart->Init.Parity == UART_PARITY_NONE) + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + huart->pRxBuffPtr += 2; + } + else + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); + huart->pRxBuffPtr += 1; + } + } + else + { + if(huart->Init.Parity == UART_PARITY_NONE) + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + } + + if(--huart->RxXferCount == 0) + { + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Check if a transmit process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; + } + HAL_UART_RxCpltCallback(huart); + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the UART peripheral. + * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ + if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the UART Word Length, Parity and mode: + Set the M bits according to huart->Init.WordLength value + Set PCE and PS bits according to huart->Init.Parity value + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + + /* Check the Over Sampling */ + if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + /*-------------------------- USART BRR Configuration ---------------------*/ + if((huart->Instance == USART1)) + { + huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); + } + else + { + huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); + } + } + else + { + /*-------------------------- USART BRR Configuration ---------------------*/ + if((huart->Instance == USART1)) + { + huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); + } + else + { + huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); + } + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c new file mode 100644 index 000000000..5165676e2 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c @@ -0,0 +1,1879 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_usart.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure. + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (##) Enable the USARTx interface clock. + (##) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure these USART pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the husart Init structure. + + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_USART_MspInit(&husart) API. + + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_USART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_USART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() + (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() + (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_USART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() + (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() + (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_USART_ErrorCallback + (+) Pause the DMA Transfer using HAL_USART_DMAPause() + (+) Resume the DMA Transfer using HAL_USART_DMAResume() + (+) Stop the DMA Transfer using HAL_USART_DMAStop() + + *** USART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in USART HAL driver. + + (+) __HAL_USART_ENABLE: Enable the USART peripheral + (+) __HAL_USART_DISABLE: Disable the USART peripheral + (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not + (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag + (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt + (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt + + [..] + (@) You can refer to the USART HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup USART USART + * @brief HAL USART Synchronous module driver + * @{ + */ +#ifdef HAL_USART_MODULE_ENABLED +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +#define DUMMY_DATA 0xFFFF +#define USART_TIMEOUT_VALUE 22000 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup USART_Private_Functions USART Private Functions + * @{ + */ +static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); +static void USART_SetConfig (USART_HandleTypeDef *husart); +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + + +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous configuration + procedure (details for the procedure are available in reference manual (RM0038)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USART mode according to the specified + * parameters in the USART_InitTypeDef and create the associated handle. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if(husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + if(husart->State == HAL_USART_STATE_RESET) + { + /* Init the low level hardware */ + HAL_USART_MspInit(husart); + } + + husart->State = HAL_USART_STATE_BUSY; + + /* Set the USART Communication parameters */ + USART_SetConfig(husart); + + /* In USART mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register */ + CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + + /* Enable the Peripheral */ + __HAL_USART_ENABLE(husart); + + /* Initialize the USART state */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State= HAL_USART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the USART peripheral. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if(husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_USART_DISABLE(husart); + + /* DeInit the low level hardware */ + HAL_USART_MspDeInit(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief USART MSP Init. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_MspInit could be implemented in the user file + */ +} + +/** + * @brief USART MSP DeInit. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the USART synchronous + data transfers. + + [..] + The USART supports master mode only: it cannot receive or send data related to an input + clock (SCLK is always an output). + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() + user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_USART_ErrorCallback() user callback will be executed when a communication + error is detected + + (#) Blocking mode APIs are : + (++) HAL_USART_Transmit() in simplex mode + (++) HAL_USART_Receive() in full duplex receive only + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_USART_Transmit_IT()in simplex mode + (++) HAL_USART_Receive_IT() in full duplex receive only + (++) HAL_USART_TransmitReceive_IT() in full duplex mode + (++) HAL_USART_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_USART_Transmit_DMA()in simplex mode + (++) HAL_USART_Receive_DMA() in full duplex receive only + (++) HAL_USART_TransmitReceive_DMA() in full duplex mode + (++) HAL_USART_DMAPause() + (++) HAL_USART_DMAResume() + (++) HAL_USART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_USART_TxHalfCpltCallback() + (++) HAL_USART_TxCpltCallback() + (++) HAL_USART_RxHalfCpltCallback() + (++) HAL_USART_RxCpltCallback() + (++) HAL_USART_ErrorCallback() + (++) HAL_USART_TxRxCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Simplex Send an amount of data in blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + husart->TxXferSize = Size; + husart->TxXferCount = Size; + while(husart->TxXferCount > 0) + { + husart->TxXferCount--; + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + /* Wait for TC flag in order to write data in DR */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pTxData; + WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF)); + if(husart->Init.Parity == USART_PARITY_NONE) + { + pTxData += 2; + } + else + { + pTxData += 1; + } + } + else + { + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0xFF)); + } + } + + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Receive an amount of data in blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pRxData: Pointer to data buffer + * @param Size: Amount of data to be received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + husart->RxXferSize = Size; + husart->RxXferCount = Size; + /* Check the remain data to be received */ + while(husart->RxXferCount > 0) + { + husart->RxXferCount--; + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + /* Send dummy byte in order to generate clock */ + WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); + + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pRxData ; + if(husart->Init.Parity == USART_PARITY_NONE) + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); + pRxData +=2; + } + else + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); + pRxData +=1; + } + } + else + { + /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Send Dummy Byte in order to generate clock */ + WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF)); + + /* Wait until RXNE flag is set to receive the byte */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if(husart->Init.Parity == USART_PARITY_NONE) + { + /* Receive data */ + *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); + } + else + { + /* Receive data */ + *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); + } + + } + } + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data transmitted buffer + * @param pRxData: Pointer to data received buffer + * @param Size: Amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint16_t* tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + husart->RxXferSize = Size; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->RxXferCount = Size; + + /* Check the remain data to be received */ + while(husart->TxXferCount > 0) + { + husart->TxXferCount--; + husart->RxXferCount--; + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + /* Wait for TC flag in order to write data in DR */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pTxData; + WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF)); + if(husart->Init.Parity == USART_PARITY_NONE) + { + pTxData += 2; + } + else + { + pTxData += 1; + } + + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t*) pRxData ; + if(husart->Init.Parity == USART_PARITY_NONE) + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); + pRxData += 2; + } + else + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); + pRxData += 1; + } + } + else + { + /* Wait for TC flag in order to write data in DR */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF)); + + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if(husart->Init.Parity == USART_PARITY_NONE) + { + /* Receive data */ + *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); + } + else + { + /* Receive data */ + *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); + } + } + } + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Simplex Send an amount of data in non-blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + * @note The USART errors are not managed to avoid the overrun error. + */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +{ + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) + are not managed by the USART transmit process to avoid the overrun interrupt + when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" + to benefit for the frame error and noise interrupts the USART mode should be + configured only for transmit "USART_MODE_TX" + The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error, + Noise error interrupt */ + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Simplex Receive an amount of data in non-blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pRxData: Pointer to data buffer + * @param Size: Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + if(husart->State == HAL_USART_STATE_READY) + { + if((pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Enable the USART Data Register not empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); + + /* Enable the USART Parity Error Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_PE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Send dummy byte in order to generate the clock for the slave to send data */ + WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data transmitted buffer + * @param pRxData: Pointer to data received buffer + * @param Size: Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Enable the USART Data Register not empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); + + /* Enable the USART Parity Error Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_PE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Simplex Send an amount of data in non-blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data buffer + * @param Size: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +{ + uint32_t *tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Enable the USART transmit DMA channel */ + tmp = (uint32_t*)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Receive an amount of data in non-blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pRxData: Pointer to data buffer + * @param Size: Amount of data to be received + * @retval HAL status + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + uint32_t *tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pRxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* Enable the USART receive DMA channel */ + tmp = (uint32_t*)&pRxData; + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size); + + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive one */ + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); + + /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer + when using the USART in circular mode */ + __HAL_USART_CLEAR_OREFLAG(husart); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param pTxData: Pointer to data transmitted buffer + * @param pRxData: Pointer to data received buffer + * @param Size: Amount of data to be received + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + uint32_t *tmp=0; + + if(husart->State == HAL_USART_STATE_READY) + { + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* Enable the USART receive DMA channel */ + tmp = (uint32_t*)&pRxData; + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size); + + /* Enable the USART transmit DMA channel */ + tmp = (uint32_t*)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); + + /* Clear the Overrun flag: mandatory for the second transfer in circular mode */ + __HAL_USART_CLEAR_OREFLAG(husart); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + /* Process Locked */ + __HAL_LOCK(husart); + + /* Disable the USART DMA Tx request */ + CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_DMAT)); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + /* Process Locked */ + __HAL_LOCK(husart); + + /* Enable the USART DMA Tx request */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() + */ + + /* Abort the USART DMA Tx channel */ + if(husart->hdmatx != NULL) + { + HAL_DMA_Abort(husart->hdmatx); + } + /* Abort the USART DMA Rx channel */ + if(husart->hdmarx != NULL) + { + HAL_DMA_Abort(husart->hdmarx); + } + + /* Disable the USART Tx/Rx DMA requests */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + husart->State = HAL_USART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles USART interrupt request. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE); + /* USART parity error interrupt occurred -----------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_USART_CLEAR_PEFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); + /* USART frame error interrupt occurred ------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_USART_CLEAR_FEFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); + /* USART noise error interrupt occurred ------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_USART_CLEAR_NEFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); + /* USART Over-Run interrupt occurred ---------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + __HAL_USART_CLEAR_OREFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + if(husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* Set the USART state ready to be able to start again the process */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_ErrorCallback(husart); + } + + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE); + /* USART in mode Receiver --------------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + USART_Receive_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + } + + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE); + /* USART in mode Transmitter -----------------------------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + USART_Transmit_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + } + + tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC); + tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC); + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if((tmp1 != RESET) && (tmp2 != RESET)) + { + USART_EndTransmit_IT(husart); + } + +} + + +/** + * @brief Tx Transfer completed callbacks. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief USART error callbacks. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief USART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + USART communication + process, return Peripheral Errors occurred during communication process + (+) HAL_USART_GetState() API can be helpful to check in run-time the state + of the USART peripheral. + (+) HAL_USART_GetError() check in run-time errors that could be occurred during + communication. +@endverbatim + * @{ + */ + +/** + * @brief Returns the USART state. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL state + */ +HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +{ + return husart->State; +} + +/** + * @brief Return the USART error code + * @param husart : pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART Error Code + */ +uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @brief USART Private functions + * @{ + */ +/** + * @brief DMA USART transmit process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + husart->TxXferCount = 0; + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Wait for USART TC Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + husart->State = HAL_USART_STATE_TIMEOUT; + HAL_USART_ErrorCallback(husart); + } + else + { + /* No Timeout */ + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + husart->State= HAL_USART_STATE_READY; + HAL_USART_TxCpltCallback(husart); + } + } + } + /* DMA Circular mode */ + else + { + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + HAL_USART_TxCpltCallback(husart); + } + } +} + +/** + * @brief DMA USART transmit process half complete callback + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_USART_TxHalfCpltCallback(husart); +} + +/** + * @brief DMA USART receive process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + { + husart->RxXferCount = 0; + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + /* Disable the DMA transfer for the receiver requests by setting the DMAR bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + HAL_USART_RxCpltCallback(husart); + } + /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + else + { + /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + HAL_USART_TxRxCpltCallback(husart); + } + husart->State= HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + HAL_USART_RxCpltCallback(husart); + } + /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + else + { + HAL_USART_TxRxCpltCallback(husart); + } + } +} + +/** + * @brief DMA USART receive process half complete callback + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_USART_RxHalfCpltCallback(husart); +} + +/** + * @brief DMA USART communication error callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void USART_DMAError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + husart->RxXferCount = 0; + husart->TxXferCount = 0; + husart->ErrorCode |= HAL_USART_ERROR_DMA; + husart->State= HAL_USART_STATE_READY; + + HAL_USART_ErrorCallback(husart); +} + +/** + * @brief This function handles USART Communication Timeout. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @param Flag: specifies the USART flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_USART_GET_FLAG(husart, Flag) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State= HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_USART_GET_FLAG(husart, Flag) != RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State= HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Simplex Send an amount of data in non-blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + * @note The USART errors are not managed to avoid the overrun error. + */ +static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp=0; + + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + tmp = (uint16_t*) husart->pTxBuffPtr; + WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); + if(husart->Init.Parity == USART_PARITY_NONE) + { + husart->pTxBuffPtr += 2; + } + else + { + husart->pTxBuffPtr += 1; + } + } + else + { + WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF)); + } + + if(--husart->TxXferCount == 0) + { + /* Disable the USART Transmit data register empty Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Wraps up transmission in non blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxCpltCallback(husart); + + return HAL_OK; +} + + +/** + * @brief Simplex Receive an amount of data in non-blocking mode. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp=0; + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + tmp = (uint16_t*) husart->pRxBuffPtr; + if(husart->Init.Parity == USART_PARITY_NONE) + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); + husart->pRxBuffPtr += 2; + } + else + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); + husart->pRxBuffPtr += 1; + } + if(--husart->RxXferCount != 0x00) + { + /* Send dummy byte in order to generate the clock for the slave to send the next data */ + WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); + } + } + else + { + if(husart->Init.Parity == USART_PARITY_NONE) + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); + } + + if(--husart->RxXferCount != 0x00) + { + /* Send dummy byte in order to generate the clock for the slave to send the next data */ + WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF)); + } + } + + if(husart->RxXferCount == 0) + { + /* Disable the USART RXNE Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + + /* Disable the USART Parity Error Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + HAL_USART_RxCpltCallback(husart); + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp=0; + + if(husart->State == HAL_USART_STATE_BUSY_TX_RX) + { + if(husart->TxXferCount != 0x00) + { + if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) + { + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + tmp = (uint16_t*) husart->pTxBuffPtr; + WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); + if(husart->Init.Parity == USART_PARITY_NONE) + { + husart->pTxBuffPtr += 2; + } + else + { + husart->pTxBuffPtr += 1; + } + } + else + { + WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF)); + } + husart->TxXferCount--; + + /* Check the latest data transmitted */ + if(husart->TxXferCount == 0) + { + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + } + } + } + + if(husart->RxXferCount != 0x00) + { + if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) + { + if(husart->Init.WordLength == USART_WORDLENGTH_9B) + { + tmp = (uint16_t*) husart->pRxBuffPtr; + if(husart->Init.Parity == USART_PARITY_NONE) + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); + husart->pRxBuffPtr += 2; + } + else + { + *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); + husart->pRxBuffPtr += 1; + } + } + else + { + if(husart->Init.Parity == USART_PARITY_NONE) + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); + } + } + husart->RxXferCount--; + } + } + + /* Check the latest data received */ + if(husart->RxXferCount == 0) + { + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + + /* Disable the USART Parity Error Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the USART peripheral. + * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void USART_SetConfig(USART_HandleTypeDef *husart) +{ + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + + /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the + receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */ + CLEAR_BIT(husart->Instance->CR1, ((uint32_t)(USART_CR1_TE | USART_CR1_RE))); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/ + /* Set CPOL bit according to husart->Init.CLKPolarity value */ + /* Set CPHA bit according to husart->Init.CLKPhase value */ + /* Set LBCL bit according to husart->Init.CLKLastBit value */ + /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */ + /* Write to USART CR2 */ + MODIFY_REG(husart->Instance->CR2, + (uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP), + ((uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits))); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the USART Word Length, Parity and mode: + Set the M bits according to husart->Init.WordLength value + Set PCE and PS bits according to husart->Init.Parity value + Set TE and RE bits according to husart->Init.Mode value */ + MODIFY_REG(husart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Clear CTSE and RTSE bits */ + CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)); + + /*-------------------------- USART BRR Configuration -----------------------*/ + if((husart->Instance == USART1)) + { + husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate); + } + else + { + husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate); + } +} + +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c new file mode 100644 index 000000000..a0dffd772 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c @@ -0,0 +1,444 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_wwdg.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief WWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Window Watchdog (WWDG) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State functions + @verbatim + ============================================================================== + ##### WWDG specific features ##### + ============================================================================== + [..] + Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the counter (downcounter) + before reaching 0x3F value (i.e. a reset is generated when the counter + value rolls over from 0x40 to 0x3F). + + (+) An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + reset occurs. + (+) The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) + (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock + (+) WWDG Counter refresh is allowed between the following limits : + (++) min time (mS) = 1000 * (Counter – Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock + + (+) Min-max timeout value at @32MHz (PCLK1): ~128us / ~65.6ms. + + + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE(). + (+) Set the WWDG prescaler, refresh window and counter value + using HAL_WWDG_Init() function. + (+) Start the WWDG using HAL_WWDG_Start() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is + generated when the counter reaches 0x40, and then start the WWDG using + HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can + add his own code by customization of function pointer HAL_WWDG_WakeupCallback + Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_WWDG_Refresh() function. This operation must occur only when + the counter is lower than the refresh window value already programmed. + + *** WWDG HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in WWDG HAL driver. + + (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup WWDG WWDG + * @brief WWDG HAL module driver. + * @{ + */ + +#ifdef HAL_WWDG_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize the WWDG according to the specified parameters + in the WWDG_InitTypeDef and create the associated handle + (+) DeInitialize the WWDG peripheral + (+) Initialize the WWDG MSP + (+) DeInitialize the WWDG MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the WWDG according to the specified + * parameters in the WWDG_InitTypeDef and creates the associated handle. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) +{ + /* Check the WWDG handle allocation */ + if(hwwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); + assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); + assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); + + if(hwwdg->State == HAL_WWDG_STATE_RESET) + { + /* Init the low level hardware */ + HAL_WWDG_MspInit(hwwdg); + } + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Set WWDG Prescaler and Window */ + MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); + + /* Set WWDG Counter */ + MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the WWDG peripheral. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) +{ + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_WWDG_MspDeInit(hwwdg); + + /* Reset WWDG Control register */ + hwwdg->Instance->CR = (uint32_t)0x0000007F; + + /* Reset WWDG Configuration register */ + hwwdg->Instance->CFR = (uint32_t)0x0000007F; + + /* Reset WWDG Status register */ + hwwdg->Instance->SR = 0; + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the WWDG MSP. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_WWDG_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the WWDG MSP. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_WWDG_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the WWDG. + (+) Refresh the WWDG. + (+) Handle WWDG interrupt request. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the WWDG. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) +{ + /* Process Locked */ + __HAL_LOCK(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Enable the peripheral */ + __HAL_WWDG_ENABLE(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the WWDG with interrupt enabled. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) +{ + /* Process Locked */ + __HAL_LOCK(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Enable the Early Wakeup Interrupt */ + __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI); + + /* Enable the peripheral */ + __HAL_WWDG_ENABLE(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Refreshes the WWDG. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @param Counter: value of counter to put in WWDG counter + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) +{ + /* Process Locked */ + __HAL_LOCK(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + + /* Write to WWDG CR the WWDG Counter value to refresh with */ + MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hwwdg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles WWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) +{ + /* WWDG Early Wakeup Interrupt occurred */ + if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + { + /* Early Wakeup callback */ + HAL_WWDG_WakeupCallback(hwwdg); + + /* Change WWDG peripheral state */ + hwwdg->State = HAL_WWDG_STATE_READY; + + /* Clear the WWDG Data Ready flag */ + __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF); + + /* Process Unlocked */ + __HAL_UNLOCK(hwwdg); + } +} + +/** + * @brief Early Wakeup WWDG callback. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_WWDG_WakeupCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the WWDG state. + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL state + */ +HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) +{ + return hwwdg->State; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_WWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c new file mode 100644 index 000000000..b2b03f1f1 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_fsmc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief FSMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================= + ##### FSMC peripheral features ##### + ============================================================================= + [..] The Flexible static memory controller (FSMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + + [..] The FSMC functional block makes the interface with synchronous and asynchronous static + memories and SDRAM memories. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol. + (+) to meet the access time requirements of the external memory devices. + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FSMC performs + only one access at a time to an external device. + The main features of the FSMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM). + (++) NOR Flash memory. + (++) PSRAM (4 memory banks). + (+) Independent Chip Select control for each memory bank. + (+) Independent configuration for each memory bank. + + ============================================================================= + ##### How to use NORSRAM device driver ##### + ============================================================================= + + [..] + This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() + (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() + (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() + (+) FSMC NORSRAM bank extended timing configuration using the function + FSMC_NORSRAM_Extended_Timing_Init() + (+) FSMC NORSRAM bank enable/disable write operation using the functions + FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup FSMC_LL FSMC_LL + * @brief FSMC driver modules + * @{ + */ + +#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FSMC_Exported_Functions FSMC Exported Functions + * @{ + */ + +/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FSMC NORSRAM interface + (+) De-initialize the FSMC NORSRAM interface + (+) Configure the FSMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FSMC_NORSRAM device according to the specified + * control parameters in the FSMC_NORSRAM_InitTypeDef + * @param Device: Pointer to NORSRAM device instance + * @param Init: Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef* Init) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FSMC_MUX(Init->DataAddressMux)); + assert_param(IS_FSMC_MEMORY(Init->MemoryType)); + assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); + + /* Set NORSRAM device control parameters */ + tmpr = (uint32_t)(Init->DataAddressMux |\ + Init->MemoryType |\ + Init->MemoryDataWidth |\ + Init->BurstAccessMode |\ + Init->WaitSignalPolarity |\ + Init->WrapMode |\ + Init->WaitSignalActive |\ + Init->WriteOperation |\ + Init->WaitSignal |\ + Init->ExtendedMode |\ + Init->AsynchronousWait |\ + Init->WriteBurst + ); + + if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) + { + tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + + Device->BTCR[Init->NSBank] = tmpr; + + return HAL_OK; +} + + +/** + * @brief DeInitialize the FSMC_NORSRAM peripheral + * @param Device: Pointer to NORSRAM device instance + * @param ExDevice: Pointer to NORSRAM extended mode device instance + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + + /* Disable the FSMC_NORSRAM device */ + __FSMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FSMC_NORSRAM device */ + /* FSMC_NORSRAM_BANK1 */ + if(Bank == FSMC_BANK1_NORSRAM1) + { + Device->BTCR[Bank] = 0x000030DB; + } + /* FSMC_BANK1_NORSRAM2, FSMC_BANK1_NORSRAM3 or FSMC_BANK1_NORSRAM4 */ + else + { + Device->BTCR[Bank] = 0x000030D2; + } + + Device->BTCR[Bank + 1] = 0x0FFFFFFF; + ExDevice->BWTR[Bank] = 0x0FFFFFFF; + + return HAL_OK; +} + + +/** + * @brief Initialize the FSMC_NORSRAM Timing according to the specified + * parameters in the FSMC_NORSRAM_TimingTypeDef + * @param Device: Pointer to NORSRAM device instance + * @param Timing: Pointer to NORSRAM Timing structure + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + + /* Set FSMC_NORSRAM device timing parameters */ + tmpr = (uint32_t)(Timing->AddressSetupTime |\ + ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) |\ + ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) |\ + ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) |\ + (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) |\ + (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BTRx_DATLAT)) |\ + (Timing->AccessMode) + ); + + Device->BTCR[Bank + 1] = tmpr; + + return HAL_OK; +} + +/** + * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FSMC_NORSRAM_TimingTypeDef + * @param Device: Pointer to NORSRAM device instance + * @param Timing: Pointer to NORSRAM Timing structure + * @param Bank: NORSRAM bank number + * @param ExtendedMode: FSMC Extended Mode + * This parameter can be one of the following values: + * @arg FSMC_EXTENDED_MODE_DISABLE + * @arg FSMC_EXTENDED_MODE_ENABLE + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +{ + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); + + Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\ + ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) |\ + ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) |\ + ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)) |\ + (Timing->AccessMode)); + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFF; + } + + return HAL_OK; +} + + +/** + * @} + */ + + +/** @defgroup HAL_FSMC_NORSRAM_Group2 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FSMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FSMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FSMC_NORSRAM write operation. + * @param Device: Pointer to NORSRAM device instance + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank) +{ + /* Enable write operation */ + Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; + + return HAL_OK; +} + +/** + * @brief Disables dynamically FSMC_NORSRAM write operation. + * @param Device: Pointer to NORSRAM device instance + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank) +{ + /* Disable write operation */ + Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#endif /* HAL_FSMC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c new file mode 100644 index 000000000..d3305e557 --- /dev/null +++ b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c @@ -0,0 +1,519 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_sdmmc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief SDMMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the SDMMC peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### SDMMC peripheral features ##### + ============================================================================== + [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 + peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA + devices. + + [..] The MultiMedia Card system specifications are available through the MultiMedia Card + Association website at www.mmca.org, published by the MMCA technical committee. + SD memory card and SD I/O card system specifications are available through the SD card + Association website at www.sdcard.org. + CE-ATA system specifications are available through the CE-ATA work group web site at + www.ce-ata.org. + + [..] The SDIO features include the following: + (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support + for three different databus modes: 1-bit (default), 4-bit and 8-bit + (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) + (+) Full compliance with SD Memory Card Specifications Version 2.0 + (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two + different data bus modes: 1-bit (default) and 4-bit + (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol + Rev1.1) + (+) Data transfer up to 48 MHz for the 8 bit mode + (+) Data and command output enable signals to control external bidirectional drivers. + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a considered as a driver of service for external devices drivers + that interfaces with the SDIO peripheral. + According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs + is used in the device's driver to perform SDIO operations and functionalities. + + This driver is almost transparent for the final user, it is only used to implement other + functionalities of the external device. + + [..] + (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from the PLL. Before start working with SDIO peripheral make sure that the + PLL is well configured. + The SDIO peripheral uses two clock signals: + (++) SDIO adapter clock (SDIOCLK = 48 MHz) + (++) APB2 bus clock (PCLK2) + + -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: + Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) + + (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO + peripheral. + + (+) Enable the Power ON State using the SDIO_PowerState_ON(hsdio) + function and disable it using the function SDIO_PowerState_OFF(hsdio). + + (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. + + (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) + and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. + + (+) When using the DMA mode + (++) Configure the DMA in the MSP layer of the external device + (++) Active the needed channel Request + (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro + __SDIO_DMA_DISABLE(). + + (+) To control the CPSM (Command Path State Machine) and send + commands to the card use the SDIO_SendCommand(), + SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has + to fill the command structure (pointer to SDIO_CmdInitTypeDef) according + to the selected command to be sent. + The parameters that should be filled are: + (++) Command Argument + (++) Command Index + (++) Command Response type + (++) Command Wait + (++) CPSM Status (Enable or Disable). + + -@@- To check if the command is well received, read the SDIO_CMDRESP + register using the SDIO_GetCommandResponse(). + The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the + SDIO_GetResponse() function. + + (+) To control the DPSM (Data Path State Machine) and send/receive + data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. + + *** Read Operations *** + ======================= + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be from card (To SDIO) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDIO resources to receive the data from the card + according to selected transfer mode. + + (#) Send the selected Read command. + + (#) Use the SDIO flags/interrupts to check the transfer status. + + *** Write Operations *** + ======================== + [..] + (#) First, user has to fill the data structure (pointer to + SDIO_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be to card (To CARD) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDIO resources to send the data to the card according to + selected transfer mode. + + (#) Send the selected Write command. + + (#) Use the SDIO flags/interrupts to check the transfer status. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup SDMMC_LL SDMMC_LL + * @brief Low layer module for SD and MMC driver + * @{ + */ + +#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions + * @{ + */ + +/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDIO according to the specified + * parameters in the SDIO_InitTypeDef and create the associated handle. + * @param SDIOx: Pointer to SDIO register base + * @param Init: SDIO initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); + assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); + assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); + + /* Set SDIO configuration parameters */ + tmpreg |= (Init.ClockEdge |\ + Init.ClockBypass |\ + Init.ClockPowerSave |\ + Init.BusWide |\ + Init.HardwareFlowControl |\ + Init.ClockDiv + ); + + /* Write to SDIO CLKCR */ + MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + + + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### I/O operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SDIO data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Read data (word) from Rx FIFO in blocking mode (polling) + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) +{ + /* Read data from Rx FIFO */ + return (SDIOx->FIFO); +} + +/** + * @brief Write data (word) to Tx FIFO in blocking mode (polling) + * @param SDIOx: Pointer to SDIO register base + * @param pWriteData: pointer to data to write + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) +{ + /* Write data to FIFO */ + SDIOx->FIFO = *pWriteData; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SDIO data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Set SDIO Power state to ON. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) +{ + /* Set power state to ON */ + SDIOx->POWER = SDIO_POWER_PWRCTRL; + + return HAL_OK; +} + +/** + * @brief Set SDIO Power state to OFF. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) +{ + /* Set power state to OFF */ + SDIOx->POWER = (uint32_t)0x00000000; + + return HAL_OK; +} + +/** + * @brief Get SDIO Power state. + * @param SDIOx: Pointer to SDIO register base + * @retval Power status of the controller. The returned value can be one of the + * following values: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) +{ + return (SDIOx->POWER & SDIO_POWER_PWRCTRL); +} + +/** + * @brief Configure the SDIO command path according to the specified parameters in + * SDIO_CmdInitTypeDef structure and send the command + * @param SDIOx: Pointer to SDIO register base + * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains + * the configuration information for the SDIO command + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM)); + + /* Set the SDIO Argument value */ + SDIOx->ARG = SDIO_CmdInitStruct->Argument; + + /* Set SDIO command parameters */ + tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\ + SDIO_CmdInitStruct->Response |\ + SDIO_CmdInitStruct->WaitForInterrupt |\ + SDIO_CmdInitStruct->CPSM); + + /* Write to SDIO CMD register */ + MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + +/** + * @brief Return the command index of last command for which response received + * @param SDIOx: Pointer to SDIO register base + * @retval Command index of the last command response received + */ +uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) +{ + return (uint8_t)(SDIOx->RESPCMD); +} + + +/** + * @brief Return the response received from the card for the last command + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + /* Get the response */ + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Configure the SDIO data path according to the specified + * parameters in the SDIO_DataInitTypeDef. + * @param SDIOx: Pointer to SDIO register base + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure + * that contains the configuration information for the SDIO command. + * @retval HAL status + */ +HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM)); + + /* Set the SDIO Data TimeOut value */ + SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut; + + /* Set the SDIO DataLength value */ + SDIOx->DLEN = SDIO_DataInitStruct->DataLength; + + /* Set the SDIO data configuration parameters */ + tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\ + SDIO_DataInitStruct->TransferDir |\ + SDIO_DataInitStruct->TransferMode |\ + SDIO_DataInitStruct->DPSM); + + /* Write to SDIO DCTRL */ + MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); + + return HAL_OK; + +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param SDIOx: Pointer to SDIO register base + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) +{ + return (SDIOx->DCOUNT); +} + +/** + * @brief Get the FIFO data + * @param SDIOx: Pointer to SDIO register base + * @retval Data received + */ +uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) +{ + return (SDIOx->FIFO); +} + + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode; + + return HAL_OK; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/clock.c b/cpu/arm/stm32l152/clock.c new file mode 100644 index 000000000..14f474219 --- /dev/null +++ b/cpu/arm/stm32l152/clock.c @@ -0,0 +1,109 @@ +/* +* Copyright (c) 2012, STMicroelectronics. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the Institute nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +* +*/ + + +#include +#include "contiki.h" +#include "platform-conf.h" +#include "contiki-conf.h" +#include "dev/leds.h" + +#include "stm32l1xx.h" + +#include "stm32l1xx_hal_rcc.h" +#include "stm32l1xx_hal_cortex.h" +#include "stm32l1xx_hal.h" + +/*---------------------------------------------------------------------------*/ +#define RELOAD_VALUE ((F_CPU/CLOCK_CONF_SECOND) - 1) + +static volatile unsigned long seconds = 0; +static volatile clock_time_t ticks; +void SysTick_Handler(void); +/*---------------------------------------------------------------------------*/ + +void SysTick_Handler(void) +{ + ticks++; + if((ticks % CLOCK_SECOND) == 0) { + seconds++; + energest_flush(); + } + HAL_IncTick(); +// HAL_SYSTICK_IRQHandler(); + if(etimer_pending()) { + etimer_request_poll(); + } + +} + +void clock_init(void) +{ + ticks = 0; + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + HAL_SYSTICK_Config(RELOAD_VALUE); + +} +unsigned long clock_seconds(void) +{ + return seconds; +} + +void clock_set_seconds(unsigned long sec) +{ + seconds = sec; +} + +clock_time_t clock_time(void) +{ + return ticks; +} + +void clock_delay(unsigned int i) +{ + for(; i > 0; i--) { + unsigned int j; + for(j = 50; j > 0; j--) { + asm ("nop"); + } + } +} + +/** + * Wait for a multiple of clock ticks (7.8 ms at 128 Hz). + */ +void clock_wait(clock_time_t i) +{ + clock_time_t start; + start = clock_time(); + while(clock_time() - start < (clock_time_t)i); +} + diff --git a/cpu/arm/stm32l152/console.c b/cpu/arm/stm32l152/console.c new file mode 100644 index 000000000..3644af8ec --- /dev/null +++ b/cpu/arm/stm32l152/console.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file console.c + * @author AST + * @version V1.0.0 + * @date 26-Aug-2014 + * @brief This file provides implementation of standard input/output + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include +#include +//#include "console.h" +#include "stm32l1xx.h" +#include "stm32l1xx_hal_dma.h" +#include "stm32l1xx_hal_uart.h" + + +extern UART_HandleTypeDef UartHandle; + +/** @addtogroup STM32F4xx_HAL_Examples + * @{ + */ + +/** @addtogroup X_NUCLEO_IKC01A1_Demonstration + * @{ + */ + +/** @defgroup X_NUCLEO_IKC01A1_Demonstration_Console_Utilities + * @{ + */ + + +/** + * @brief Initialises Nucleo UART port for user IO + * @param None + * @retval 0 + */ +int consoleInit(void) +{ + UartHandle.Instance = USART2; + + UartHandle.Init.BaudRate = 9600; + UartHandle.Init.WordLength = UART_WORDLENGTH_8B; + UartHandle.Init.StopBits = UART_STOPBITS_1; + UartHandle.Init.Parity = UART_PARITY_NONE; + UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + UartHandle.Init.Mode = UART_MODE_TX_RX; + + HAL_UART_Init(&UartHandle); + + return 0; +} + + +/** @brief Sends a character to serial port + * @param ch Character to send + * @retval Character sent + */ +int uartSendChar(int ch) +{ + HAL_UART_Transmit(&UartHandle, (uint8_t *)&ch, 1, HAL_MAX_DELAY); + return ch; +} + +/** @brief Receives a character from serial port + * @param None + * @retval Character received + */ +int uartReceiveChar(void) +{ + uint8_t ch; + HAL_UART_Receive(&UartHandle, &ch, 1, HAL_MAX_DELAY); + + /* Echo character back to console */ + HAL_UART_Transmit(&UartHandle, &ch, 1, HAL_MAX_DELAY); + + /* And cope with Windows */ + if(ch == '\r'){ + uint8_t ret = '\n'; + HAL_UART_Transmit(&UartHandle, &ret, 1, HAL_MAX_DELAY); + } + + return ch; +} + + +#if defined (__IAR_SYSTEMS_ICC__) + +size_t __write(int Handle, const unsigned char * Buf, size_t Bufsize); +size_t __read(int Handle, unsigned char *Buf, size_t Bufsize); + +/** @brief IAR specific low level standard input + * @param Handle IAR internal handle + * @param Buf Buffer where to store characters read from stdin + * @param Bufsize Number of characters to read + * @retval Number of characters read + */ +size_t __read(int Handle, unsigned char *Buf, size_t Bufsize) +{ + int i; + + if (Handle != 0){ + return -1; + } + + for(i=0; i
© COPYRIGHT(c) 2014 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/** @addtogroup STM32F4xx_HAL_Examples + * @{ + */ + +/** @addtogroup X_NUCLEO_IKC01A1_Demonstration + * @{ + */ + +/** @defgroup X_NUCLEO_IKC01A1_Demonstration_Console_Utilities + * @{ + */ + + +/** + * @brief Initialises Nucleo UART port for user IO + * @param None + * @retval 0 + */ + + +#if defined (__IAR_SYSTEMS_ICC__) + +size_t __write(int Handle, const unsigned char * Buf, size_t Bufsize); +size_t __read(int Handle, unsigned char *Buf, size_t Bufsize); + + +#elif defined (__CC_ARM) + +/** + * @brief fputc call for standard output implementation + * @param ch Character to print + * @param f File pointer + * @retval Character printed + */ +int fputc(int ch, FILE *f); + +/** @brief fgetc call for standard input implementation + * @param f File pointer + * @retval Character acquired from standard input + */ +int fgetc(FILE *f); + +#elif defined (__GNUC__) + +/** @brief putchar call for standard output implementation + * @param ch Character to print + * @retval Character printed + */ +int __io_putchar(int ch); + +/** @brief getchar call for standard input implementation + * @param None + * @retval Character acquired from standard input + */ +int __io_getchar(void); + +#else +#error "Toolchain not supported" +#endif +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/cpu/arm/stm32l152/crt.c b/cpu/arm/stm32l152/crt.c new file mode 100644 index 000000000..0cc934287 --- /dev/null +++ b/cpu/arm/stm32l152/crt.c @@ -0,0 +1,88 @@ +/** +****************************************************************************** +* @file main.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief source file +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include +#include +int _lseek (int file, + int ptr, + int dir) +{ + return 0; +} +int _close (int file) +{ + return -1; +} + +void _exit (int n) +{ + /* FIXME: return code is thrown away. */ + while(1); +} + + +int _kill (int n, int m) +{ + return -1; +} +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} +int _isatty (int fd) +{ + return 1; + fd = fd; +} + +int _getpid (int n) +{ + return -1; +} +int _open (const char * path, + int flags, + ...) +{ + return -1; +} +#if 0 +int _fflush_r(struct _reent *r, FILE *f) +{ + return 0; +} +#endif diff --git a/cpu/arm/stm32l152/cube_hal.h b/cpu/arm/stm32l152/cube_hal.h new file mode 100644 index 000000000..118024e2c --- /dev/null +++ b/cpu/arm/stm32l152/cube_hal.h @@ -0,0 +1,65 @@ +/** + ****************************************************************************** + * @file Projects/Multi/Examples/DataLog/Inc/cube_hal.h + * @author CL + * @version V1.0.0 + * @date 03-November-2014 + * @brief Header for cube_hal_f4.c and cube_hal_l0.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _CUBE_HAL_H_ +#define _CUBE_HAL_H_ + +/* Includes ------------------------------------------------------------------*/ +//#ifdef USE_STM32F4XX_NUCLEO +// #include "stm32f4xx_hal.h" +// #include "stm32f4xx_nucleo.h" +// #include "stm32f4xx_hal_conf.h" +// #include "stm32f4xx_hal_def.h" +//#endif + +//#ifdef USE_STM32L0XX_NUCLEO + + #include "stm32l1xx_hal.h" + #include "stm32l1xx_nucleo.h" + #include "stm32l1xx_hal_conf.h" + #include "stm32l1xx_hal_def.h" +//#endif + +void SystemClock_Config(void); +uint32_t Get_DMA_Flag_Status(DMA_HandleTypeDef *handle_dma); +uint32_t Get_DMA_Counter(DMA_HandleTypeDef *handle_dma); +void Config_DMA_Handler(DMA_HandleTypeDef *handle_dma); + +#endif //_CUBE_HAL_H_ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/mtarch.h b/cpu/arm/stm32l152/mtarch.h new file mode 100644 index 000000000..640035036 --- /dev/null +++ b/cpu/arm/stm32l152/mtarch.h @@ -0,0 +1,13 @@ +/* + * Implementation of multithreading in ARM Cortex-M3. To be done. + */ + + +#ifndef __MTARCH_H__ +#define __MTARCH_H__ + +struct mtarch_thread { + short mt_thread; +}; + +#endif /* __MTARCH_H__ */ \ No newline at end of file diff --git a/cpu/arm/stm32l152/regs.h b/cpu/arm/stm32l152/regs.h new file mode 100644 index 000000000..5c60f682a --- /dev/null +++ b/cpu/arm/stm32l152/regs.h @@ -0,0 +1,11544 @@ +#ifndef REGS_H_ +#define REGS_H_ 1 + + +#define ReadRegister(a) a +#define WriteRegister(a, b) a = b + +/* FLASH_BASE block */ +#define DATA_FLASH_BASE_BASE (0x00000000u) +#define DATA_FLASH_BASE_END (0x0001FFFFu) +#define DATA_FLASH_BASE_SIZE (DATA_FLASH_BASE_END - DATA_FLASH_BASE_BASE + 1) + +/* FLASH block */ +#define DATA_FLASH_BASE (0x08000000u) +#define DATA_FLASH_END (0x0801FFFFu) +#define DATA_FLASH_SIZE (DATA_FLASH_END - DATA_FLASH_BASE + 1) + +/* BIG_INFO_BASE block */ +#define DATA_BIG_INFO_BASE_BASE (0x00000000u) +#define DATA_BIG_INFO_BASE_END (0x000007FFu) +#define DATA_BIG_INFO_BASE_SIZE (DATA_BIG_INFO_BASE_END - DATA_BIG_INFO_BASE_BASE + 1) + +/* BIG_INFO block */ +#define DATA_BIG_INFO_BASE (0x08040000u) +#define DATA_BIG_INFO_END (0x080407FFu) +#define DATA_BIG_INFO_SIZE (DATA_BIG_INFO_END - DATA_BIG_INFO_BASE + 1) + +/* SMALL_INFO block */ +#define DATA_SMALL_INFO_BASE (0x08040800u) +#define DATA_SMALL_INFO_END (0x080409FFu) +#define DATA_SMALL_INFO_SIZE (DATA_SMALL_INFO_END - DATA_SMALL_INFO_BASE + 1) + +/* SRAM block */ +#define DATA_SRAM_BASE (0x20000000u) +#define DATA_SRAM_END (0x20001FFFu) +#define DATA_SRAM_SIZE (DATA_SRAM_END - DATA_SRAM_BASE + 1) + +/* CM_HV block */ +#define DATA_CM_HV_BASE (0x40000000u) +#define DATA_CM_HV_END (0x40000044u) +#define DATA_CM_HV_SIZE (DATA_CM_HV_END - DATA_CM_HV_BASE + 1) + +#define HV_SPARE *((volatile uint32_t *)0x40000000u) +#define HV_SPARE_REG *((volatile uint32_t *)0x40000000u) +#define HV_SPARE_ADDR (0x40000000u) +#define HV_SPARE_RESET (0x00000000u) + /* HV_SPARE field */ + #define HV_SPARE_HV_SPARE (0x000000FFu) + #define HV_SPARE_HV_SPARE_MASK (0x000000FFu) + #define HV_SPARE_HV_SPARE_BIT (0) + #define HV_SPARE_HV_SPARE_BITS (8) + +#define EVENT_CTRL *((volatile uint32_t *)0x40000004u) +#define EVENT_CTRL_REG *((volatile uint32_t *)0x40000004u) +#define EVENT_CTRL_ADDR (0x40000004u) +#define EVENT_CTRL_RESET (0x00000000u) + /* LV_FREEZE field */ + #define LV_FREEZE (0x00000002u) + #define LV_FREEZE_MASK (0x00000002u) + #define LV_FREEZE_BIT (1) + #define LV_FREEZE_BITS (1) + +#define SLEEPTMR_CLKEN *((volatile uint32_t *)0x40000008u) +#define SLEEPTMR_CLKEN_REG *((volatile uint32_t *)0x40000008u) +#define SLEEPTMR_CLKEN_ADDR (0x40000008u) +#define SLEEPTMR_CLKEN_RESET (0x00000002u) + /* SLEEPTMR_CLK10KEN field */ + #define SLEEPTMR_CLK10KEN (0x00000002u) + #define SLEEPTMR_CLK10KEN_MASK (0x00000002u) + #define SLEEPTMR_CLK10KEN_BIT (1) + #define SLEEPTMR_CLK10KEN_BITS (1) + /* SLEEPTMR_CLK32KEN field */ + #define SLEEPTMR_CLK32KEN (0x00000001u) + #define SLEEPTMR_CLK32KEN_MASK (0x00000001u) + #define SLEEPTMR_CLK32KEN_BIT (0) + #define SLEEPTMR_CLK32KEN_BITS (1) + +#define CLKRC_TUNE *((volatile uint32_t *)0x4000000Cu) +#define CLKRC_TUNE_REG *((volatile uint32_t *)0x4000000Cu) +#define CLKRC_TUNE_ADDR (0x4000000Cu) +#define CLKRC_TUNE_RESET (0x00000000u) + /* CLKRC_TUNE_FIELD field */ + #define CLKRC_TUNE_FIELD (0x0000000Fu) + #define CLKRC_TUNE_FIELD_MASK (0x0000000Fu) + #define CLKRC_TUNE_FIELD_BIT (0) + #define CLKRC_TUNE_FIELD_BITS (4) + +#define CLK1K_CAL *((volatile uint32_t *)0x40000010u) +#define CLK1K_CAL_REG *((volatile uint32_t *)0x40000010u) +#define CLK1K_CAL_ADDR (0x40000010u) +#define CLK1K_CAL_RESET (0x00005000u) + /* CLK1K_INTEGER field */ + #define CLK1K_INTEGER (0x0000F800u) + #define CLK1K_INTEGER_MASK (0x0000F800u) + #define CLK1K_INTEGER_BIT (11) + #define CLK1K_INTEGER_BITS (5) + /* CLK1K_FRACTIONAL field */ + #define CLK1K_FRACTIONAL (0x000007FFu) + #define CLK1K_FRACTIONAL_MASK (0x000007FFu) + #define CLK1K_FRACTIONAL_BIT (0) + #define CLK1K_FRACTIONAL_BITS (11) + +#define REGEN_DSLEEP *((volatile uint32_t *)0x40000014u) +#define REGEN_DSLEEP_REG *((volatile uint32_t *)0x40000014u) +#define REGEN_DSLEEP_ADDR (0x40000014u) +#define REGEN_DSLEEP_RESET (0x00000001u) + /* REGEN_DSLEEP_FIELD field */ + #define REGEN_DSLEEP_FIELD (0x00000001u) + #define REGEN_DSLEEP_FIELD_MASK (0x00000001u) + #define REGEN_DSLEEP_FIELD_BIT (0) + #define REGEN_DSLEEP_FIELD_BITS (1) + +#define VREG *((volatile uint32_t *)0x40000018u) +#define VREG_REG *((volatile uint32_t *)0x40000018u) +#define VREG_ADDR (0x40000018u) +#define VREG_RESET (0x00000207u) + /* VREF_EN field */ + #define VREG_VREF_EN (0x00008000u) + #define VREG_VREF_EN_MASK (0x00008000u) + #define VREG_VREF_EN_BIT (15) + #define VREG_VREF_EN_BITS (1) + /* VREF_TEST field */ + #define VREG_VREF_TEST (0x00004000u) + #define VREG_VREF_TEST_MASK (0x00004000u) + #define VREG_VREF_TEST_BIT (14) + #define VREG_VREF_TEST_BITS (1) + /* VREG_1V8_EN field */ + #define VREG_VREG_1V8_EN (0x00000800u) + #define VREG_VREG_1V8_EN_MASK (0x00000800u) + #define VREG_VREG_1V8_EN_BIT (11) + #define VREG_VREG_1V8_EN_BITS (1) + /* VREG_1V8_TEST field */ + #define VREG_VREG_1V8_TEST (0x00000400u) + #define VREG_VREG_1V8_TEST_MASK (0x00000400u) + #define VREG_VREG_1V8_TEST_BIT (10) + #define VREG_VREG_1V8_TEST_BITS (1) + /* VREG_1V8_TRIM field */ + #define VREG_VREG_1V8_TRIM (0x00000380u) + #define VREG_VREG_1V8_TRIM_MASK (0x00000380u) + #define VREG_VREG_1V8_TRIM_BIT (7) + #define VREG_VREG_1V8_TRIM_BITS (3) + /* VREG_1V2_EN field */ + #define VREG_VREG_1V2_EN (0x00000010u) + #define VREG_VREG_1V2_EN_MASK (0x00000010u) + #define VREG_VREG_1V2_EN_BIT (4) + #define VREG_VREG_1V2_EN_BITS (1) + /* VREG_1V2_TEST field */ + #define VREG_VREG_1V2_TEST (0x00000008u) + #define VREG_VREG_1V2_TEST_MASK (0x00000008u) + #define VREG_VREG_1V2_TEST_BIT (3) + #define VREG_VREG_1V2_TEST_BITS (1) + /* VREG_1V2_TRIM field */ + #define VREG_VREG_1V2_TRIM (0x00000007u) + #define VREG_VREG_1V2_TRIM_MASK (0x00000007u) + #define VREG_VREG_1V2_TRIM_BIT (0) + #define VREG_VREG_1V2_TRIM_BITS (3) + +#define WAKE_SEL *((volatile uint32_t *)0x40000020u) +#define WAKE_SEL_REG *((volatile uint32_t *)0x40000020u) +#define WAKE_SEL_ADDR (0x40000020u) +#define WAKE_SEL_RESET (0x00000200u) + /* WAKE_CSYSPWRUPREQ field */ + #define WAKE_CSYSPWRUPREQ (0x00000200u) + #define WAKE_CSYSPWRUPREQ_MASK (0x00000200u) + #define WAKE_CSYSPWRUPREQ_BIT (9) + #define WAKE_CSYSPWRUPREQ_BITS (1) + /* WAKE_CDBGPWRUPREQ field */ + #define WAKE_CDBGPWRUPREQ (0x00000100u) + #define WAKE_CDBGPWRUPREQ_MASK (0x00000100u) + #define WAKE_CDBGPWRUPREQ_BIT (8) + #define WAKE_CDBGPWRUPREQ_BITS (1) + /* WAKE_WAKE_CORE field */ + #define WAKE_WAKE_CORE (0x00000080u) + #define WAKE_WAKE_CORE_MASK (0x00000080u) + #define WAKE_WAKE_CORE_BIT (7) + #define WAKE_WAKE_CORE_BITS (1) + /* WAKE_SLEEPTMRWRAP field */ + #define WAKE_SLEEPTMRWRAP (0x00000040u) + #define WAKE_SLEEPTMRWRAP_MASK (0x00000040u) + #define WAKE_SLEEPTMRWRAP_BIT (6) + #define WAKE_SLEEPTMRWRAP_BITS (1) + /* WAKE_SLEEPTMRCMPB field */ + #define WAKE_SLEEPTMRCMPB (0x00000020u) + #define WAKE_SLEEPTMRCMPB_MASK (0x00000020u) + #define WAKE_SLEEPTMRCMPB_BIT (5) + #define WAKE_SLEEPTMRCMPB_BITS (1) + /* WAKE_SLEEPTMRCMPA field */ + #define WAKE_SLEEPTMRCMPA (0x00000010u) + #define WAKE_SLEEPTMRCMPA_MASK (0x00000010u) + #define WAKE_SLEEPTMRCMPA_BIT (4) + #define WAKE_SLEEPTMRCMPA_BITS (1) + /* WAKE_IRQD field */ + #define WAKE_IRQD (0x00000008u) + #define WAKE_IRQD_MASK (0x00000008u) + #define WAKE_IRQD_BIT (3) + #define WAKE_IRQD_BITS (1) + /* WAKE_SC2 field */ + #define WAKE_SC2 (0x00000004u) + #define WAKE_SC2_MASK (0x00000004u) + #define WAKE_SC2_BIT (2) + #define WAKE_SC2_BITS (1) + /* WAKE_SC1 field */ + #define WAKE_SC1 (0x00000002u) + #define WAKE_SC1_MASK (0x00000002u) + #define WAKE_SC1_BIT (1) + #define WAKE_SC1_BITS (1) + /* GPIO_WAKE field */ + #define GPIO_WAKE (0x00000001u) + #define GPIO_WAKE_MASK (0x00000001u) + #define GPIO_WAKE_BIT (0) + #define GPIO_WAKE_BITS (1) + +#define WAKE_CORE *((volatile uint32_t *)0x40000024u) +#define WAKE_CORE_REG *((volatile uint32_t *)0x40000024u) +#define WAKE_CORE_ADDR (0x40000024u) +#define WAKE_CORE_RESET (0x00000000u) + /* WAKE_CORE_FIELD field */ + #define WAKE_CORE_FIELD (0x00000020u) + #define WAKE_CORE_FIELD_MASK (0x00000020u) + #define WAKE_CORE_FIELD_BIT (5) + #define WAKE_CORE_FIELD_BITS (1) + +#define PWRUP_EVENT *((volatile uint32_t *)0x40000028u) +#define PWRUP_EVENT_REG *((volatile uint32_t *)0x40000028u) +#define PWRUP_EVENT_ADDR (0x40000028u) +#define PWRUP_EVENT_RESET (0x00000000u) + /* PWRUP_CSYSPWRUPREQ field */ + #define PWRUP_CSYSPWRUPREQ (0x00000200u) + #define PWRUP_CSYSPWRUPREQ_MASK (0x00000200u) + #define PWRUP_CSYSPWRUPREQ_BIT (9) + #define PWRUP_CSYSPWRUPREQ_BITS (1) + /* PWRUP_CDBGPWRUPREQ field */ + #define PWRUP_CDBGPWRUPREQ (0x00000100u) + #define PWRUP_CDBGPWRUPREQ_MASK (0x00000100u) + #define PWRUP_CDBGPWRUPREQ_BIT (8) + #define PWRUP_CDBGPWRUPREQ_BITS (1) + /* PWRUP_WAKECORE field */ + #define PWRUP_WAKECORE (0x00000080u) + #define PWRUP_WAKECORE_MASK (0x00000080u) + #define PWRUP_WAKECORE_BIT (7) + #define PWRUP_WAKECORE_BITS (1) + /* PWRUP_SLEEPTMRWRAP field */ + #define PWRUP_SLEEPTMRWRAP (0x00000040u) + #define PWRUP_SLEEPTMRWRAP_MASK (0x00000040u) + #define PWRUP_SLEEPTMRWRAP_BIT (6) + #define PWRUP_SLEEPTMRWRAP_BITS (1) + /* PWRUP_SLEEPTMRCOMPB field */ + #define PWRUP_SLEEPTMRCOMPB (0x00000020u) + #define PWRUP_SLEEPTMRCOMPB_MASK (0x00000020u) + #define PWRUP_SLEEPTMRCOMPB_BIT (5) + #define PWRUP_SLEEPTMRCOMPB_BITS (1) + /* PWRUP_SLEEPTMRCOMPA field */ + #define PWRUP_SLEEPTMRCOMPA (0x00000010u) + #define PWRUP_SLEEPTMRCOMPA_MASK (0x00000010u) + #define PWRUP_SLEEPTMRCOMPA_BIT (4) + #define PWRUP_SLEEPTMRCOMPA_BITS (1) + /* PWRUP_IRQD field */ + #define PWRUP_IRQD (0x00000008u) + #define PWRUP_IRQD_MASK (0x00000008u) + #define PWRUP_IRQD_BIT (3) + #define PWRUP_IRQD_BITS (1) + /* PWRUP_SC2 field */ + #define PWRUP_SC2 (0x00000004u) + #define PWRUP_SC2_MASK (0x00000004u) + #define PWRUP_SC2_BIT (2) + #define PWRUP_SC2_BITS (1) + /* PWRUP_SC1 field */ + #define PWRUP_SC1 (0x00000002u) + #define PWRUP_SC1_MASK (0x00000002u) + #define PWRUP_SC1_BIT (1) + #define PWRUP_SC1_BITS (1) + /* PWRUP_GPIO field */ + #define PWRUP_GPIO (0x00000001u) + #define PWRUP_GPIO_MASK (0x00000001u) + #define PWRUP_GPIO_BIT (0) + #define PWRUP_GPIO_BITS (1) + +#define RESET_EVENT *((volatile uint32_t *)0x4000002Cu) +#define RESET_EVENT_REG *((volatile uint32_t *)0x4000002Cu) +#define RESET_EVENT_ADDR (0x4000002Cu) +#define RESET_EVENT_RESET (0x00000001u) + /* RESET_CPULOCKUP field */ + #define RESET_CPULOCKUP (0x00000080u) + #define RESET_CPULOCKUP_MASK (0x00000080u) + #define RESET_CPULOCKUP_BIT (7) + #define RESET_CPULOCKUP_BITS (1) + /* RESET_OPTBYTEFAIL field */ + #define RESET_OPTBYTEFAIL (0x00000040u) + #define RESET_OPTBYTEFAIL_MASK (0x00000040u) + #define RESET_OPTBYTEFAIL_BIT (6) + #define RESET_OPTBYTEFAIL_BITS (1) + /* RESET_DSLEEP field */ + #define RESET_DSLEEP (0x00000020u) + #define RESET_DSLEEP_MASK (0x00000020u) + #define RESET_DSLEEP_BIT (5) + #define RESET_DSLEEP_BITS (1) + /* RESET_SW field */ + #define RESET_SW (0x00000010u) + #define RESET_SW_MASK (0x00000010u) + #define RESET_SW_BIT (4) + #define RESET_SW_BITS (1) + /* RESET_WDOG field */ + #define RESET_WDOG (0x00000008u) + #define RESET_WDOG_MASK (0x00000008u) + #define RESET_WDOG_BIT (3) + #define RESET_WDOG_BITS (1) + /* RESET_NRESET field */ + #define RESET_NRESET (0x00000004u) + #define RESET_NRESET_MASK (0x00000004u) + #define RESET_NRESET_BIT (2) + #define RESET_NRESET_BITS (1) + /* RESET_PWRLV field */ + #define RESET_PWRLV (0x00000002u) + #define RESET_PWRLV_MASK (0x00000002u) + #define RESET_PWRLV_BIT (1) + #define RESET_PWRLV_BITS (1) + /* RESET_PWRHV field */ + #define RESET_PWRHV (0x00000001u) + #define RESET_PWRHV_MASK (0x00000001u) + #define RESET_PWRHV_BIT (0) + #define RESET_PWRHV_BITS (1) + +#define DBG_MBOX *((volatile uint32_t *)0x40000030u) +#define DBG_MBOX_REG *((volatile uint32_t *)0x40000030u) +#define DBG_MBOX_ADDR (0x40000030u) +#define DBG_MBOX_RESET (0x00000000u) + /* DBG_MBOX field */ + #define DBG_MBOX_DBG_MBOX (0x0000FFFFu) + #define DBG_MBOX_DBG_MBOX_MASK (0x0000FFFFu) + #define DBG_MBOX_DBG_MBOX_BIT (0) + #define DBG_MBOX_DBG_MBOX_BITS (16) + +#define CPWRUPREQ_STATUS *((volatile uint32_t *)0x40000034u) +#define CPWRUPREQ_STATUS_REG *((volatile uint32_t *)0x40000034u) +#define CPWRUPREQ_STATUS_ADDR (0x40000034u) +#define CPWRUPREQ_STATUS_RESET (0x00000000u) + /* CPWRUPREQ field */ + #define CPWRUPREQ_STATUS_CPWRUPREQ (0x00000001u) + #define CPWRUPREQ_STATUS_CPWRUPREQ_MASK (0x00000001u) + #define CPWRUPREQ_STATUS_CPWRUPREQ_BIT (0) + #define CPWRUPREQ_STATUS_CPWRUPREQ_BITS (1) + +#define CSYSPWRUPREQ_STATUS *((volatile uint32_t *)0x40000038u) +#define CSYSPWRUPREQ_STATUS_REG *((volatile uint32_t *)0x40000038u) +#define CSYSPWRUPREQ_STATUS_ADDR (0x40000038u) +#define CSYSPWRUPREQ_STATUS_RESET (0x00000000u) + /* CSYSPWRUPREQ field */ + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ (0x00000001u) + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_MASK (0x00000001u) + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT (0) + #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS (1) + +#define CSYSPWRUPACK_STATUS *((volatile uint32_t *)0x4000003Cu) +#define CSYSPWRUPACK_STATUS_REG *((volatile uint32_t *)0x4000003Cu) +#define CSYSPWRUPACK_STATUS_ADDR (0x4000003Cu) +#define CSYSPWRUPACK_STATUS_RESET (0x00000000u) + /* CSYSPWRUPACK field */ + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK (0x00000001u) + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_MASK (0x00000001u) + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT (0) + #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS (1) + +#define CSYSPWRUPACK_INHIBIT *((volatile uint32_t *)0x40000040u) +#define CSYSPWRUPACK_INHIBIT_REG *((volatile uint32_t *)0x40000040u) +#define CSYSPWRUPACK_INHIBIT_ADDR (0x40000040u) +#define CSYSPWRUPACK_INHIBIT_RESET (0x00000000u) + /* CSYSPWRUPACK_INHIBIT field */ + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT (0x00000001u) + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_MASK (0x00000001u) + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT (0) + #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS (1) + +#define OPT_ERR_MAINTAIN_WAKE *((volatile uint32_t *)0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE_REG *((volatile uint32_t *)0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE_ADDR (0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE_RESET (0x00000000u) + /* OPT_ERR_MAINTAIN_WAKE field */ + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE (0x00000001u) + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_MASK (0x00000001u) + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BIT (0) + #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BITS (1) + +/* BASEBAND block */ +#define DATA_BASEBAND_BASE (0x40001000u) +#define DATA_BASEBAND_END (0x40001114u) +#define DATA_BASEBAND_SIZE (DATA_BASEBAND_END - DATA_BASEBAND_BASE + 1) + +#define MOD_CAL_CTRL *((volatile uint32_t *)0x40001000u) +#define MOD_CAL_CTRL_REG *((volatile uint32_t *)0x40001000u) +#define MOD_CAL_CTRL_ADDR (0x40001000u) +#define MOD_CAL_CTRL_RESET (0x00000000u) + /* MOD_CAL_GO field */ + #define MOD_CAL_CTRL_MOD_CAL_GO (0x00008000u) + #define MOD_CAL_CTRL_MOD_CAL_GO_MASK (0x00008000u) + #define MOD_CAL_CTRL_MOD_CAL_GO_BIT (15) + #define MOD_CAL_CTRL_MOD_CAL_GO_BITS (1) + /* MOD_CAL_DONE field */ + #define MOD_CAL_CTRL_MOD_CAL_DONE (0x00000010u) + #define MOD_CAL_CTRL_MOD_CAL_DONE_MASK (0x00000010u) + #define MOD_CAL_CTRL_MOD_CAL_DONE_BIT (4) + #define MOD_CAL_CTRL_MOD_CAL_DONE_BITS (1) + /* MOD_CAL_CYCLES field */ + #define MOD_CAL_CTRL_MOD_CAL_CYCLES (0x00000003u) + #define MOD_CAL_CTRL_MOD_CAL_CYCLES_MASK (0x00000003u) + #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT (0) + #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS (2) + +#define MOD_CAL_COUNT_H *((volatile uint32_t *)0x40001004u) +#define MOD_CAL_COUNT_H_REG *((volatile uint32_t *)0x40001004u) +#define MOD_CAL_COUNT_H_ADDR (0x40001004u) +#define MOD_CAL_COUNT_H_RESET (0x00000000u) + /* MOD_CAL_COUNT_H field */ + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H (0x000000FFu) + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_MASK (0x000000FFu) + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT (0) + #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS (8) + +#define MOD_CAL_COUNT_L *((volatile uint32_t *)0x40001008u) +#define MOD_CAL_COUNT_L_REG *((volatile uint32_t *)0x40001008u) +#define MOD_CAL_COUNT_L_ADDR (0x40001008u) +#define MOD_CAL_COUNT_L_RESET (0x00000000u) + /* MOD_CAL_COUNT_L field */ + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L (0x0000FFFFu) + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_MASK (0x0000FFFFu) + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT (0) + #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS (16) + +#define RSSI_ROLLING *((volatile uint32_t *)0x4000100Cu) +#define RSSI_ROLLING_REG *((volatile uint32_t *)0x4000100Cu) +#define RSSI_ROLLING_ADDR (0x4000100Cu) +#define RSSI_ROLLING_RESET (0x00000000u) + /* RSSI_ROLLING field */ + #define RSSI_ROLLING_RSSI_ROLLING (0x00003FFFu) + #define RSSI_ROLLING_RSSI_ROLLING_MASK (0x00003FFFu) + #define RSSI_ROLLING_RSSI_ROLLING_BIT (0) + #define RSSI_ROLLING_RSSI_ROLLING_BITS (14) + +#define RSSI_PKT *((volatile uint32_t *)0x40001010u) +#define RSSI_PKT_REG *((volatile uint32_t *)0x40001010u) +#define RSSI_PKT_ADDR (0x40001010u) +#define RSSI_PKT_RESET (0x00000000u) + /* RSSI_PKT field */ + #define RSSI_PKT_RSSI_PKT (0x000000FFu) + #define RSSI_PKT_RSSI_PKT_MASK (0x000000FFu) + #define RSSI_PKT_RSSI_PKT_BIT (0) + #define RSSI_PKT_RSSI_PKT_BITS (8) + +#define RX_ADC *((volatile uint32_t *)0x40001014u) +#define RX_ADC_REG *((volatile uint32_t *)0x40001014u) +#define RX_ADC_ADDR (0x40001014u) +#define RX_ADC_RESET (0x00000024u) + /* RX_ADC field */ + #define RX_ADC_RX_ADC (0x0000007Fu) + #define RX_ADC_RX_ADC_MASK (0x0000007Fu) + #define RX_ADC_RX_ADC_BIT (0) + #define RX_ADC_RX_ADC_BITS (7) + +#define DEBUG_BB_MODE *((volatile uint32_t *)0x40001018u) +#define DEBUG_BB_MODE_REG *((volatile uint32_t *)0x40001018u) +#define DEBUG_BB_MODE_ADDR (0x40001018u) +#define DEBUG_BB_MODE_RESET (0x00000000u) + /* DEBUG_BB_MODE_EN field */ + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN (0x00008000u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_MASK (0x00008000u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BIT (15) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BITS (1) + /* DEBUG_BB_MODE field */ + #define DEBUG_BB_MODE_DEBUG_BB_MODE (0x00000003u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_MASK (0x00000003u) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_BIT (0) + #define DEBUG_BB_MODE_DEBUG_BB_MODE_BITS (2) + +#define BB_DEBUG *((volatile uint32_t *)0x4000101Cu) +#define BB_DEBUG_REG *((volatile uint32_t *)0x4000101Cu) +#define BB_DEBUG_ADDR (0x4000101Cu) +#define BB_DEBUG_RESET (0x00000002u) + /* SYNC_REG_EN field */ + #define BB_DEBUG_SYNC_REG_EN (0x00008000u) + #define BB_DEBUG_SYNC_REG_EN_MASK (0x00008000u) + #define BB_DEBUG_SYNC_REG_EN_BIT (15) + #define BB_DEBUG_SYNC_REG_EN_BITS (1) + /* DEBUG_MUX_ADDR field */ + #define BB_DEBUG_DEBUG_MUX_ADDR (0x000000F0u) + #define BB_DEBUG_DEBUG_MUX_ADDR_MASK (0x000000F0u) + #define BB_DEBUG_DEBUG_MUX_ADDR_BIT (4) + #define BB_DEBUG_DEBUG_MUX_ADDR_BITS (4) + /* BB_DEBUG_SEL field */ + #define BB_DEBUG_BB_DEBUG_SEL (0x00000003u) + #define BB_DEBUG_BB_DEBUG_SEL_MASK (0x00000003u) + #define BB_DEBUG_BB_DEBUG_SEL_BIT (0) + #define BB_DEBUG_BB_DEBUG_SEL_BITS (2) + +#define BB_DEBUG_VIEW *((volatile uint32_t *)0x40001020u) +#define BB_DEBUG_VIEW_REG *((volatile uint32_t *)0x40001020u) +#define BB_DEBUG_VIEW_ADDR (0x40001020u) +#define BB_DEBUG_VIEW_RESET (0x00000000u) + /* BB_DEBUG_VIEW field */ + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW (0x0000FFFFu) + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_MASK (0x0000FFFFu) + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT (0) + #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS (16) + +#define IF_FREQ *((volatile uint32_t *)0x40001024u) +#define IF_FREQ_REG *((volatile uint32_t *)0x40001024u) +#define IF_FREQ_ADDR (0x40001024u) +#define IF_FREQ_RESET (0x00000155u) + /* TIMING_CORR_EN field */ + #define IF_FREQ_TIMING_CORR_EN (0x00008000u) + #define IF_FREQ_TIMING_CORR_EN_MASK (0x00008000u) + #define IF_FREQ_TIMING_CORR_EN_BIT (15) + #define IF_FREQ_TIMING_CORR_EN_BITS (1) + /* IF_FREQ field */ + #define IF_FREQ_IF_FREQ (0x000001FFu) + #define IF_FREQ_IF_FREQ_MASK (0x000001FFu) + #define IF_FREQ_IF_FREQ_BIT (0) + #define IF_FREQ_IF_FREQ_BITS (9) + +#define MOD_EN *((volatile uint32_t *)0x40001028u) +#define MOD_EN_REG *((volatile uint32_t *)0x40001028u) +#define MOD_EN_ADDR (0x40001028u) +#define MOD_EN_RESET (0x00000001u) + /* MOD_EN field */ + #define MOD_EN_MOD_EN (0x00000001u) + #define MOD_EN_MOD_EN_MASK (0x00000001u) + #define MOD_EN_MOD_EN_BIT (0) + #define MOD_EN_MOD_EN_BITS (1) + +#define PRESCALE_CTRL *((volatile uint32_t *)0x4000102Cu) +#define PRESCALE_CTRL_REG *((volatile uint32_t *)0x4000102Cu) +#define PRESCALE_CTRL_ADDR (0x4000102Cu) +#define PRESCALE_CTRL_RESET (0x00000000u) + /* PRESCALE_SET field */ + #define PRESCALE_CTRL_PRESCALE_SET (0x00008000u) + #define PRESCALE_CTRL_PRESCALE_SET_MASK (0x00008000u) + #define PRESCALE_CTRL_PRESCALE_SET_BIT (15) + #define PRESCALE_CTRL_PRESCALE_SET_BITS (1) + /* PRESCALE_VAL field */ + #define PRESCALE_CTRL_PRESCALE_VAL (0x00000007u) + #define PRESCALE_CTRL_PRESCALE_VAL_MASK (0x00000007u) + #define PRESCALE_CTRL_PRESCALE_VAL_BIT (0) + #define PRESCALE_CTRL_PRESCALE_VAL_BITS (3) + +#define ADC_BYPASS_EN *((volatile uint32_t *)0x40001030u) +#define ADC_BYPASS_EN_REG *((volatile uint32_t *)0x40001030u) +#define ADC_BYPASS_EN_ADDR (0x40001030u) +#define ADC_BYPASS_EN_RESET (0x00000000u) + /* ADC_BYPASS_EN field */ + #define ADC_BYPASS_EN_ADC_BYPASS_EN (0x00000001u) + #define ADC_BYPASS_EN_ADC_BYPASS_EN_MASK (0x00000001u) + #define ADC_BYPASS_EN_ADC_BYPASS_EN_BIT (0) + #define ADC_BYPASS_EN_ADC_BYPASS_EN_BITS (1) + +#define FIXED_CODE_EN *((volatile uint32_t *)0x40001034u) +#define FIXED_CODE_EN_REG *((volatile uint32_t *)0x40001034u) +#define FIXED_CODE_EN_ADDR (0x40001034u) +#define FIXED_CODE_EN_RESET (0x00000000u) + /* FIXED_CODE_EN field */ + #define FIXED_CODE_EN_FIXED_CODE_EN (0x00000001u) + #define FIXED_CODE_EN_FIXED_CODE_EN_MASK (0x00000001u) + #define FIXED_CODE_EN_FIXED_CODE_EN_BIT (0) + #define FIXED_CODE_EN_FIXED_CODE_EN_BITS (1) + +#define FIXED_CODE_H *((volatile uint32_t *)0x40001038u) +#define FIXED_CODE_H_REG *((volatile uint32_t *)0x40001038u) +#define FIXED_CODE_H_ADDR (0x40001038u) +#define FIXED_CODE_H_RESET (0x00000000u) + /* FIXED_CODE_H field */ + #define FIXED_CODE_H_FIXED_CODE_H (0x0000FFFFu) + #define FIXED_CODE_H_FIXED_CODE_H_MASK (0x0000FFFFu) + #define FIXED_CODE_H_FIXED_CODE_H_BIT (0) + #define FIXED_CODE_H_FIXED_CODE_H_BITS (16) + +#define FIXED_CODE_L *((volatile uint32_t *)0x4000103Cu) +#define FIXED_CODE_L_REG *((volatile uint32_t *)0x4000103Cu) +#define FIXED_CODE_L_ADDR (0x4000103Cu) +#define FIXED_CODE_L_RESET (0x00000000u) + /* FIXED_CODE_L field */ + #define FIXED_CODE_L_FIXED_CODE_L (0x0000FFFFu) + #define FIXED_CODE_L_FIXED_CODE_L_MASK (0x0000FFFFu) + #define FIXED_CODE_L_FIXED_CODE_L_BIT (0) + #define FIXED_CODE_L_FIXED_CODE_L_BITS (16) + +#define FIXED_CODE_L_SHADOW *((volatile uint32_t *)0x40001040u) +#define FIXED_CODE_L_SHADOW_REG *((volatile uint32_t *)0x40001040u) +#define FIXED_CODE_L_SHADOW_ADDR (0x40001040u) +#define FIXED_CODE_L_SHADOW_RESET (0x00000000u) + /* FIXED_CODE_L_SHADOW field */ + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW (0x0000FFFFu) + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_MASK (0x0000FFFFu) + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT (0) + #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS (16) + +#define RX_GAIN_CTRL *((volatile uint32_t *)0x40001044u) +#define RX_GAIN_CTRL_REG *((volatile uint32_t *)0x40001044u) +#define RX_GAIN_CTRL_ADDR (0x40001044u) +#define RX_GAIN_CTRL_RESET (0x00000000u) + /* RX_GAIN_MUX field */ + #define RX_GAIN_CTRL_RX_GAIN_MUX (0x00008000u) + #define RX_GAIN_CTRL_RX_GAIN_MUX_MASK (0x00008000u) + #define RX_GAIN_CTRL_RX_GAIN_MUX_BIT (15) + #define RX_GAIN_CTRL_RX_GAIN_MUX_BITS (1) + /* RX_RF_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST (0x00000080u) + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_MASK (0x00000080u) + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BIT (7) + #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BITS (1) + /* RX_MIXER_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST (0x00000040u) + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_MASK (0x00000040u) + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BIT (6) + #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BITS (1) + /* RX_FILTER_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST (0x00000030u) + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_MASK (0x00000030u) + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BIT (4) + #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BITS (2) + /* RX_IF_GAIN_TEST field */ + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST (0x0000000Fu) + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_MASK (0x0000000Fu) + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT (0) + #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS (4) + +#define PD_DITHER_EN *((volatile uint32_t *)0x40001048u) +#define PD_DITHER_EN_REG *((volatile uint32_t *)0x40001048u) +#define PD_DITHER_EN_ADDR (0x40001048u) +#define PD_DITHER_EN_RESET (0x00000001u) + /* PD_DITHER_EN field */ + #define PD_DITHER_EN_PD_DITHER_EN (0x00000001u) + #define PD_DITHER_EN_PD_DITHER_EN_MASK (0x00000001u) + #define PD_DITHER_EN_PD_DITHER_EN_BIT (0) + #define PD_DITHER_EN_PD_DITHER_EN_BITS (1) + +#define RX_ERR_THRESH *((volatile uint32_t *)0x4000104Cu) +#define RX_ERR_THRESH_REG *((volatile uint32_t *)0x4000104Cu) +#define RX_ERR_THRESH_ADDR (0x4000104Cu) +#define RX_ERR_THRESH_RESET (0x00004608u) + /* LPF_RX_ERR_COEFF field */ + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF (0x0000E000u) + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_MASK (0x0000E000u) + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BIT (13) + #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BITS (3) + /* LPF_RX_ERR_THRESH field */ + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH (0x00001F00u) + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_MASK (0x00001F00u) + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BIT (8) + #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BITS (5) + /* RX_ERR_THRESH field */ + #define RX_ERR_THRESH_RX_ERR_THRESH (0x0000001Fu) + #define RX_ERR_THRESH_RX_ERR_THRESH_MASK (0x0000001Fu) + #define RX_ERR_THRESH_RX_ERR_THRESH_BIT (0) + #define RX_ERR_THRESH_RX_ERR_THRESH_BITS (5) + +#define CARRIER_THRESH *((volatile uint32_t *)0x40001050u) +#define CARRIER_THRESH_REG *((volatile uint32_t *)0x40001050u) +#define CARRIER_THRESH_ADDR (0x40001050u) +#define CARRIER_THRESH_RESET (0x00002332u) + /* CARRIER_SPIKE_THRESH field */ + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH (0x0000FF00u) + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_MASK (0x0000FF00u) + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BIT (8) + #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BITS (8) + /* CARRIER_THRESH field */ + #define CARRIER_THRESH_CARRIER_THRESH (0x000000FFu) + #define CARRIER_THRESH_CARRIER_THRESH_MASK (0x000000FFu) + #define CARRIER_THRESH_CARRIER_THRESH_BIT (0) + #define CARRIER_THRESH_CARRIER_THRESH_BITS (8) + +#define RSSI_THRESH *((volatile uint32_t *)0x40001054u) +#define RSSI_THRESH_REG *((volatile uint32_t *)0x40001054u) +#define RSSI_THRESH_ADDR (0x40001054u) +#define RSSI_THRESH_RESET (0x00000100u) + /* RSSI_THRESH field */ + #define RSSI_THRESH_RSSI_THRESH (0x0000FFFFu) + #define RSSI_THRESH_RSSI_THRESH_MASK (0x0000FFFFu) + #define RSSI_THRESH_RSSI_THRESH_BIT (0) + #define RSSI_THRESH_RSSI_THRESH_BITS (16) + +#define SYNTH_START *((volatile uint32_t *)0x40001058u) +#define SYNTH_START_REG *((volatile uint32_t *)0x40001058u) +#define SYNTH_START_ADDR (0x40001058u) +#define SYNTH_START_RESET (0x00006464u) + /* SYNTH_WARM_START field */ + #define SYNTH_START_SYNTH_WARM_START (0x0000FF00u) + #define SYNTH_START_SYNTH_WARM_START_MASK (0x0000FF00u) + #define SYNTH_START_SYNTH_WARM_START_BIT (8) + #define SYNTH_START_SYNTH_WARM_START_BITS (8) + /* SYNTH_COLD_START field */ + #define SYNTH_START_SYNTH_COLD_START (0x000000FFu) + #define SYNTH_START_SYNTH_COLD_START_MASK (0x000000FFu) + #define SYNTH_START_SYNTH_COLD_START_BIT (0) + #define SYNTH_START_SYNTH_COLD_START_BITS (8) + +#define IN_LOCK_EN *((volatile uint32_t *)0x4000105Cu) +#define IN_LOCK_EN_REG *((volatile uint32_t *)0x4000105Cu) +#define IN_LOCK_EN_ADDR (0x4000105Cu) +#define IN_LOCK_EN_RESET (0x00000001u) + /* IN_LOCK_EN field */ + #define IN_LOCK_EN_IN_LOCK_EN (0x00000001u) + #define IN_LOCK_EN_IN_LOCK_EN_MASK (0x00000001u) + #define IN_LOCK_EN_IN_LOCK_EN_BIT (0) + #define IN_LOCK_EN_IN_LOCK_EN_BITS (1) + +#define DITHER_AMPLITUDE *((volatile uint32_t *)0x40001060u) +#define DITHER_AMPLITUDE_REG *((volatile uint32_t *)0x40001060u) +#define DITHER_AMPLITUDE_ADDR (0x40001060u) +#define DITHER_AMPLITUDE_RESET (0x0000003Fu) + /* DITHER_AMP field */ + #define DITHER_AMPLITUDE_DITHER_AMP (0x0000003Fu) + #define DITHER_AMPLITUDE_DITHER_AMP_MASK (0x0000003Fu) + #define DITHER_AMPLITUDE_DITHER_AMP_BIT (0) + #define DITHER_AMPLITUDE_DITHER_AMP_BITS (6) + +#define TX_STEP_TIME *((volatile uint32_t *)0x40001064u) +#define TX_STEP_TIME_REG *((volatile uint32_t *)0x40001064u) +#define TX_STEP_TIME_ADDR (0x40001064u) +#define TX_STEP_TIME_RESET (0x00000000u) + /* TX_STEP_TIME field */ + #define TX_STEP_TIME_TX_STEP_TIME (0x000000FFu) + #define TX_STEP_TIME_TX_STEP_TIME_MASK (0x000000FFu) + #define TX_STEP_TIME_TX_STEP_TIME_BIT (0) + #define TX_STEP_TIME_TX_STEP_TIME_BITS (8) + +#define GAIN_THRESH_MAX *((volatile uint32_t *)0x40001068u) +#define GAIN_THRESH_MAX_REG *((volatile uint32_t *)0x40001068u) +#define GAIN_THRESH_MAX_ADDR (0x40001068u) +#define GAIN_THRESH_MAX_RESET (0x00000060u) + /* GAIN_THRESH_MAX field */ + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX (0x000000FFu) + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_MASK (0x000000FFu) + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT (0) + #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS (8) + +#define GAIN_THRESH_MID *((volatile uint32_t *)0x4000106Cu) +#define GAIN_THRESH_MID_REG *((volatile uint32_t *)0x4000106Cu) +#define GAIN_THRESH_MID_ADDR (0x4000106Cu) +#define GAIN_THRESH_MID_RESET (0x00000030u) + /* GAIN_THRESH_MID field */ + #define GAIN_THRESH_MID_GAIN_THRESH_MID (0x000000FFu) + #define GAIN_THRESH_MID_GAIN_THRESH_MID_MASK (0x000000FFu) + #define GAIN_THRESH_MID_GAIN_THRESH_MID_BIT (0) + #define GAIN_THRESH_MID_GAIN_THRESH_MID_BITS (8) + +#define GAIN_THRESH_MIN *((volatile uint32_t *)0x40001070u) +#define GAIN_THRESH_MIN_REG *((volatile uint32_t *)0x40001070u) +#define GAIN_THRESH_MIN_ADDR (0x40001070u) +#define GAIN_THRESH_MIN_RESET (0x00000018u) + /* GAIN_THRESH_MIN field */ + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN (0x000000FFu) + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_MASK (0x000000FFu) + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT (0) + #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS (8) + +#define GAIN_SETTING_0 *((volatile uint32_t *)0x40001074u) +#define GAIN_SETTING_0_REG *((volatile uint32_t *)0x40001074u) +#define GAIN_SETTING_0_ADDR (0x40001074u) +#define GAIN_SETTING_0_RESET (0x00000000u) + /* RX_MIXER_GAIN_0 field */ + #define GAIN_SETTING_0_RX_MIXER_GAIN_0 (0x00000040u) + #define GAIN_SETTING_0_RX_MIXER_GAIN_0_MASK (0x00000040u) + #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BIT (6) + #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BITS (1) + /* RX_FILTER_GAIN_0 field */ + #define GAIN_SETTING_0_RX_FILTER_GAIN_0 (0x00000030u) + #define GAIN_SETTING_0_RX_FILTER_GAIN_0_MASK (0x00000030u) + #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BIT (4) + #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BITS (2) + /* RX_IF_GAIN_0 field */ + #define GAIN_SETTING_0_RX_IF_GAIN_0 (0x0000000Fu) + #define GAIN_SETTING_0_RX_IF_GAIN_0_MASK (0x0000000Fu) + #define GAIN_SETTING_0_RX_IF_GAIN_0_BIT (0) + #define GAIN_SETTING_0_RX_IF_GAIN_0_BITS (4) + +#define GAIN_SETTING_1 *((volatile uint32_t *)0x40001078u) +#define GAIN_SETTING_1_REG *((volatile uint32_t *)0x40001078u) +#define GAIN_SETTING_1_ADDR (0x40001078u) +#define GAIN_SETTING_1_RESET (0x00000010u) + /* RX_MIXER_GAIN_1 field */ + #define GAIN_SETTING_1_RX_MIXER_GAIN_1 (0x00000040u) + #define GAIN_SETTING_1_RX_MIXER_GAIN_1_MASK (0x00000040u) + #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BIT (6) + #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BITS (1) + /* RX_FILTER_GAIN_1 field */ + #define GAIN_SETTING_1_RX_FILTER_GAIN_1 (0x00000030u) + #define GAIN_SETTING_1_RX_FILTER_GAIN_1_MASK (0x00000030u) + #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BIT (4) + #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BITS (2) + /* RX_IF_GAIN_1 field */ + #define GAIN_SETTING_1_RX_IF_GAIN_1 (0x0000000Fu) + #define GAIN_SETTING_1_RX_IF_GAIN_1_MASK (0x0000000Fu) + #define GAIN_SETTING_1_RX_IF_GAIN_1_BIT (0) + #define GAIN_SETTING_1_RX_IF_GAIN_1_BITS (4) + +#define GAIN_SETTING_2 *((volatile uint32_t *)0x4000107Cu) +#define GAIN_SETTING_2_REG *((volatile uint32_t *)0x4000107Cu) +#define GAIN_SETTING_2_ADDR (0x4000107Cu) +#define GAIN_SETTING_2_RESET (0x00000030u) + /* RX_MIXER_GAIN_2 field */ + #define GAIN_SETTING_2_RX_MIXER_GAIN_2 (0x00000040u) + #define GAIN_SETTING_2_RX_MIXER_GAIN_2_MASK (0x00000040u) + #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BIT (6) + #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BITS (1) + /* RX_FILTER_GAIN_2 field */ + #define GAIN_SETTING_2_RX_FILTER_GAIN_2 (0x00000030u) + #define GAIN_SETTING_2_RX_FILTER_GAIN_2_MASK (0x00000030u) + #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BIT (4) + #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BITS (2) + /* RX_IF_GAIN_2 field */ + #define GAIN_SETTING_2_RX_IF_GAIN_2 (0x0000000Fu) + #define GAIN_SETTING_2_RX_IF_GAIN_2_MASK (0x0000000Fu) + #define GAIN_SETTING_2_RX_IF_GAIN_2_BIT (0) + #define GAIN_SETTING_2_RX_IF_GAIN_2_BITS (4) + +#define GAIN_SETTING_3 *((volatile uint32_t *)0x40001080u) +#define GAIN_SETTING_3_REG *((volatile uint32_t *)0x40001080u) +#define GAIN_SETTING_3_ADDR (0x40001080u) +#define GAIN_SETTING_3_RESET (0x00000031u) + /* RX_MIXER_GAIN_3 field */ + #define GAIN_SETTING_3_RX_MIXER_GAIN_3 (0x00000040u) + #define GAIN_SETTING_3_RX_MIXER_GAIN_3_MASK (0x00000040u) + #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BIT (6) + #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BITS (1) + /* RX_FILTER_GAIN_3 field */ + #define GAIN_SETTING_3_RX_FILTER_GAIN_3 (0x00000030u) + #define GAIN_SETTING_3_RX_FILTER_GAIN_3_MASK (0x00000030u) + #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BIT (4) + #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BITS (2) + /* RX_IF_GAIN_3 field */ + #define GAIN_SETTING_3_RX_IF_GAIN_3 (0x0000000Fu) + #define GAIN_SETTING_3_RX_IF_GAIN_3_MASK (0x0000000Fu) + #define GAIN_SETTING_3_RX_IF_GAIN_3_BIT (0) + #define GAIN_SETTING_3_RX_IF_GAIN_3_BITS (4) + +#define GAIN_SETTING_4 *((volatile uint32_t *)0x40001084u) +#define GAIN_SETTING_4_REG *((volatile uint32_t *)0x40001084u) +#define GAIN_SETTING_4_ADDR (0x40001084u) +#define GAIN_SETTING_4_RESET (0x00000032u) + /* RX_MIXER_GAIN_4 field */ + #define GAIN_SETTING_4_RX_MIXER_GAIN_4 (0x00000040u) + #define GAIN_SETTING_4_RX_MIXER_GAIN_4_MASK (0x00000040u) + #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BIT (6) + #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BITS (1) + /* RX_FILTER_GAIN_4 field */ + #define GAIN_SETTING_4_RX_FILTER_GAIN_4 (0x00000030u) + #define GAIN_SETTING_4_RX_FILTER_GAIN_4_MASK (0x00000030u) + #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BIT (4) + #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BITS (2) + /* RX_IF_GAIN_4 field */ + #define GAIN_SETTING_4_RX_IF_GAIN_4 (0x0000000Fu) + #define GAIN_SETTING_4_RX_IF_GAIN_4_MASK (0x0000000Fu) + #define GAIN_SETTING_4_RX_IF_GAIN_4_BIT (0) + #define GAIN_SETTING_4_RX_IF_GAIN_4_BITS (4) + +#define GAIN_SETTING_5 *((volatile uint32_t *)0x40001088u) +#define GAIN_SETTING_5_REG *((volatile uint32_t *)0x40001088u) +#define GAIN_SETTING_5_ADDR (0x40001088u) +#define GAIN_SETTING_5_RESET (0x00000033u) + /* RX_MIXER_GAIN_5 field */ + #define GAIN_SETTING_5_RX_MIXER_GAIN_5 (0x00000040u) + #define GAIN_SETTING_5_RX_MIXER_GAIN_5_MASK (0x00000040u) + #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BIT (6) + #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BITS (1) + /* RX_FILTER_GAIN_5 field */ + #define GAIN_SETTING_5_RX_FILTER_GAIN_5 (0x00000030u) + #define GAIN_SETTING_5_RX_FILTER_GAIN_5_MASK (0x00000030u) + #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BIT (4) + #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BITS (2) + /* RX_IF_GAIN_5 field */ + #define GAIN_SETTING_5_RX_IF_GAIN_5 (0x0000000Fu) + #define GAIN_SETTING_5_RX_IF_GAIN_5_MASK (0x0000000Fu) + #define GAIN_SETTING_5_RX_IF_GAIN_5_BIT (0) + #define GAIN_SETTING_5_RX_IF_GAIN_5_BITS (4) + +#define GAIN_SETTING_6 *((volatile uint32_t *)0x4000108Cu) +#define GAIN_SETTING_6_REG *((volatile uint32_t *)0x4000108Cu) +#define GAIN_SETTING_6_ADDR (0x4000108Cu) +#define GAIN_SETTING_6_RESET (0x00000034u) + /* RX_MIXER_GAIN_6 field */ + #define GAIN_SETTING_6_RX_MIXER_GAIN_6 (0x00000040u) + #define GAIN_SETTING_6_RX_MIXER_GAIN_6_MASK (0x00000040u) + #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BIT (6) + #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BITS (1) + /* RX_FILTER_GAIN_6 field */ + #define GAIN_SETTING_6_RX_FILTER_GAIN_6 (0x00000030u) + #define GAIN_SETTING_6_RX_FILTER_GAIN_6_MASK (0x00000030u) + #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BIT (4) + #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BITS (2) + /* RX_IF_GAIN_6 field */ + #define GAIN_SETTING_6_RX_IF_GAIN_6 (0x0000000Fu) + #define GAIN_SETTING_6_RX_IF_GAIN_6_MASK (0x0000000Fu) + #define GAIN_SETTING_6_RX_IF_GAIN_6_BIT (0) + #define GAIN_SETTING_6_RX_IF_GAIN_6_BITS (4) + +#define GAIN_SETTING_7 *((volatile uint32_t *)0x40001090u) +#define GAIN_SETTING_7_REG *((volatile uint32_t *)0x40001090u) +#define GAIN_SETTING_7_ADDR (0x40001090u) +#define GAIN_SETTING_7_RESET (0x00000035u) + /* RX_MIXER_GAIN_7 field */ + #define GAIN_SETTING_7_RX_MIXER_GAIN_7 (0x00000040u) + #define GAIN_SETTING_7_RX_MIXER_GAIN_7_MASK (0x00000040u) + #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BIT (6) + #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BITS (1) + /* RX_FILTER_GAIN_7 field */ + #define GAIN_SETTING_7_RX_FILTER_GAIN_7 (0x00000030u) + #define GAIN_SETTING_7_RX_FILTER_GAIN_7_MASK (0x00000030u) + #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BIT (4) + #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BITS (2) + /* RX_IF_GAIN_7 field */ + #define GAIN_SETTING_7_RX_IF_GAIN_7 (0x0000000Fu) + #define GAIN_SETTING_7_RX_IF_GAIN_7_MASK (0x0000000Fu) + #define GAIN_SETTING_7_RX_IF_GAIN_7_BIT (0) + #define GAIN_SETTING_7_RX_IF_GAIN_7_BITS (4) + +#define GAIN_SETTING_8 *((volatile uint32_t *)0x40001094u) +#define GAIN_SETTING_8_REG *((volatile uint32_t *)0x40001094u) +#define GAIN_SETTING_8_ADDR (0x40001094u) +#define GAIN_SETTING_8_RESET (0x00000036u) + /* RX_MIXER_GAIN_8 field */ + #define GAIN_SETTING_8_RX_MIXER_GAIN_8 (0x00000040u) + #define GAIN_SETTING_8_RX_MIXER_GAIN_8_MASK (0x00000040u) + #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BIT (6) + #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BITS (1) + /* RX_FILTER_GAIN_8 field */ + #define GAIN_SETTING_8_RX_FILTER_GAIN_8 (0x00000030u) + #define GAIN_SETTING_8_RX_FILTER_GAIN_8_MASK (0x00000030u) + #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BIT (4) + #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BITS (2) + /* RX_IF_GAIN_8 field */ + #define GAIN_SETTING_8_RX_IF_GAIN_8 (0x0000000Fu) + #define GAIN_SETTING_8_RX_IF_GAIN_8_MASK (0x0000000Fu) + #define GAIN_SETTING_8_RX_IF_GAIN_8_BIT (0) + #define GAIN_SETTING_8_RX_IF_GAIN_8_BITS (4) + +#define GAIN_SETTING_9 *((volatile uint32_t *)0x40001098u) +#define GAIN_SETTING_9_REG *((volatile uint32_t *)0x40001098u) +#define GAIN_SETTING_9_ADDR (0x40001098u) +#define GAIN_SETTING_9_RESET (0x00000076u) + /* RX_MIXER_GAIN_9 field */ + #define GAIN_SETTING_9_RX_MIXER_GAIN_9 (0x00000040u) + #define GAIN_SETTING_9_RX_MIXER_GAIN_9_MASK (0x00000040u) + #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BIT (6) + #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BITS (1) + /* RX_FILTER_GAIN_9 field */ + #define GAIN_SETTING_9_RX_FILTER_GAIN_9 (0x00000030u) + #define GAIN_SETTING_9_RX_FILTER_GAIN_9_MASK (0x00000030u) + #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BIT (4) + #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BITS (2) + /* RX_IF_GAIN_9 field */ + #define GAIN_SETTING_9_RX_IF_GAIN_9 (0x0000000Fu) + #define GAIN_SETTING_9_RX_IF_GAIN_9_MASK (0x0000000Fu) + #define GAIN_SETTING_9_RX_IF_GAIN_9_BIT (0) + #define GAIN_SETTING_9_RX_IF_GAIN_9_BITS (4) + +#define GAIN_SETTING_10 *((volatile uint32_t *)0x4000109Cu) +#define GAIN_SETTING_10_REG *((volatile uint32_t *)0x4000109Cu) +#define GAIN_SETTING_10_ADDR (0x4000109Cu) +#define GAIN_SETTING_10_RESET (0x00000077u) + /* RX_MIXER_GAIN_10 field */ + #define GAIN_SETTING_10_RX_MIXER_GAIN_10 (0x00000040u) + #define GAIN_SETTING_10_RX_MIXER_GAIN_10_MASK (0x00000040u) + #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BIT (6) + #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BITS (1) + /* RX_FILTER_GAIN_10 field */ + #define GAIN_SETTING_10_RX_FILTER_GAIN_10 (0x00000030u) + #define GAIN_SETTING_10_RX_FILTER_GAIN_10_MASK (0x00000030u) + #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BIT (4) + #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BITS (2) + /* RX_IF_GAIN_10 field */ + #define GAIN_SETTING_10_RX_IF_GAIN_10 (0x0000000Fu) + #define GAIN_SETTING_10_RX_IF_GAIN_10_MASK (0x0000000Fu) + #define GAIN_SETTING_10_RX_IF_GAIN_10_BIT (0) + #define GAIN_SETTING_10_RX_IF_GAIN_10_BITS (4) + +#define GAIN_SETTING_11 *((volatile uint32_t *)0x400010A0u) +#define GAIN_SETTING_11_REG *((volatile uint32_t *)0x400010A0u) +#define GAIN_SETTING_11_ADDR (0x400010A0u) +#define GAIN_SETTING_11_RESET (0x00000078u) + /* RX_MIXER_GAIN_11 field */ + #define GAIN_SETTING_11_RX_MIXER_GAIN_11 (0x00000040u) + #define GAIN_SETTING_11_RX_MIXER_GAIN_11_MASK (0x00000040u) + #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BIT (6) + #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BITS (1) + /* RX_FILTER_GAIN_11 field */ + #define GAIN_SETTING_11_RX_FILTER_GAIN_11 (0x00000030u) + #define GAIN_SETTING_11_RX_FILTER_GAIN_11_MASK (0x00000030u) + #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BIT (4) + #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BITS (2) + /* RX_IF_GAIN_11 field */ + #define GAIN_SETTING_11_RX_IF_GAIN_11 (0x0000000Fu) + #define GAIN_SETTING_11_RX_IF_GAIN_11_MASK (0x0000000Fu) + #define GAIN_SETTING_11_RX_IF_GAIN_11_BIT (0) + #define GAIN_SETTING_11_RX_IF_GAIN_11_BITS (4) + +#define GAIN_CTRL_MIN_RF *((volatile uint32_t *)0x400010A4u) +#define GAIN_CTRL_MIN_RF_REG *((volatile uint32_t *)0x400010A4u) +#define GAIN_CTRL_MIN_RF_ADDR (0x400010A4u) +#define GAIN_CTRL_MIN_RF_RESET (0x000000F0u) + /* GAIN_CTRL_MIN_RF field */ + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF (0x000001FFu) + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_MASK (0x000001FFu) + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT (0) + #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS (9) + +#define GAIN_CTRL_MAX_RF *((volatile uint32_t *)0x400010A8u) +#define GAIN_CTRL_MAX_RF_REG *((volatile uint32_t *)0x400010A8u) +#define GAIN_CTRL_MAX_RF_ADDR (0x400010A8u) +#define GAIN_CTRL_MAX_RF_RESET (0x000000FCu) + /* GAIN_CTRL_MAX_RF field */ + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF (0x000001FFu) + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_MASK (0x000001FFu) + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT (0) + #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS (9) + +#define MIXER_GAIN_STEP *((volatile uint32_t *)0x400010ACu) +#define MIXER_GAIN_STEP_REG *((volatile uint32_t *)0x400010ACu) +#define MIXER_GAIN_STEP_ADDR (0x400010ACu) +#define MIXER_GAIN_STEP_RESET (0x0000000Cu) + /* MIXER_GAIN_STEP field */ + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP (0x0000000Fu) + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_MASK (0x0000000Fu) + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT (0) + #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS (4) + +#define PREAMBLE_EVENT *((volatile uint32_t *)0x400010B0u) +#define PREAMBLE_EVENT_REG *((volatile uint32_t *)0x400010B0u) +#define PREAMBLE_EVENT_ADDR (0x400010B0u) +#define PREAMBLE_EVENT_RESET (0x00005877u) + /* PREAMBLE_CONFIRM_THRESH field */ + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH (0x0000FF00u) + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_MASK (0x0000FF00u) + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BIT (8) + #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BITS (8) + /* PREAMBLE_EVENT_THRESH field */ + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH (0x000000FFu) + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_MASK (0x000000FFu) + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT (0) + #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS (8) + +#define PREAMBLE_ABORT_THRESH *((volatile uint32_t *)0x400010B4u) +#define PREAMBLE_ABORT_THRESH_REG *((volatile uint32_t *)0x400010B4u) +#define PREAMBLE_ABORT_THRESH_ADDR (0x400010B4u) +#define PREAMBLE_ABORT_THRESH_RESET (0x00000071u) + /* PREAMBLE_ABORT_THRESH field */ + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH (0x000000FFu) + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_MASK (0x000000FFu) + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT (0) + #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS (8) + +#define PREAMBLE_ACCEPT_WINDOW *((volatile uint32_t *)0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW_REG *((volatile uint32_t *)0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW_ADDR (0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW_RESET (0x00000003u) + /* PREAMBLE_ACCEPT_WINDOW field */ + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW (0x0000007Fu) + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_MASK (0x0000007Fu) + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT (0) + #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS (7) + +#define CCA_MODE *((volatile uint32_t *)0x400010BCu) +#define CCA_MODE_REG *((volatile uint32_t *)0x400010BCu) +#define CCA_MODE_ADDR (0x400010BCu) +#define CCA_MODE_RESET (0x00000000u) + /* CCA_MODE field */ + #define CCA_MODE_CCA_MODE (0x00000003u) + #define CCA_MODE_CCA_MODE_MASK (0x00000003u) + #define CCA_MODE_CCA_MODE_BIT (0) + #define CCA_MODE_CCA_MODE_BITS (2) + +#define TX_POWER_MAX *((volatile uint32_t *)0x400010C0u) +#define TX_POWER_MAX_REG *((volatile uint32_t *)0x400010C0u) +#define TX_POWER_MAX_ADDR (0x400010C0u) +#define TX_POWER_MAX_RESET (0x00000000u) + /* MANUAL_POWER field */ + #define TX_POWER_MAX_MANUAL_POWER (0x00008000u) + #define TX_POWER_MAX_MANUAL_POWER_MASK (0x00008000u) + #define TX_POWER_MAX_MANUAL_POWER_BIT (15) + #define TX_POWER_MAX_MANUAL_POWER_BITS (1) + /* TX_POWER_MAX field */ + #define TX_POWER_MAX_TX_POWER_MAX (0x0000001Fu) + #define TX_POWER_MAX_TX_POWER_MAX_MASK (0x0000001Fu) + #define TX_POWER_MAX_TX_POWER_MAX_BIT (0) + #define TX_POWER_MAX_TX_POWER_MAX_BITS (5) + +#define SYNTH_FREQ_H *((volatile uint32_t *)0x400010C4u) +#define SYNTH_FREQ_H_REG *((volatile uint32_t *)0x400010C4u) +#define SYNTH_FREQ_H_ADDR (0x400010C4u) +#define SYNTH_FREQ_H_RESET (0x00000003u) + /* SYNTH_FREQ_H field */ + #define SYNTH_FREQ_H_SYNTH_FREQ_H (0x00000003u) + #define SYNTH_FREQ_H_SYNTH_FREQ_H_MASK (0x00000003u) + #define SYNTH_FREQ_H_SYNTH_FREQ_H_BIT (0) + #define SYNTH_FREQ_H_SYNTH_FREQ_H_BITS (2) + +#define SYNTH_FREQ_L *((volatile uint32_t *)0x400010C8u) +#define SYNTH_FREQ_L_REG *((volatile uint32_t *)0x400010C8u) +#define SYNTH_FREQ_L_ADDR (0x400010C8u) +#define SYNTH_FREQ_L_RESET (0x00003800u) + /* SYNTH_FREQ_L field */ + #define SYNTH_FREQ_L_SYNTH_FREQ_L (0x0000FFFFu) + #define SYNTH_FREQ_L_SYNTH_FREQ_L_MASK (0x0000FFFFu) + #define SYNTH_FREQ_L_SYNTH_FREQ_L_BIT (0) + #define SYNTH_FREQ_L_SYNTH_FREQ_L_BITS (16) + +#define RSSI_INST *((volatile uint32_t *)0x400010CCu) +#define RSSI_INST_REG *((volatile uint32_t *)0x400010CCu) +#define RSSI_INST_ADDR (0x400010CCu) +#define RSSI_INST_RESET (0x00000000u) + /* NEW_RSSI_INST field */ + #define RSSI_INST_NEW_RSSI_INST (0x00000200u) + #define RSSI_INST_NEW_RSSI_INST_MASK (0x00000200u) + #define RSSI_INST_NEW_RSSI_INST_BIT (9) + #define RSSI_INST_NEW_RSSI_INST_BITS (1) + /* RSSI_INST field */ + #define RSSI_INST_RSSI_INST (0x000001FFu) + #define RSSI_INST_RSSI_INST_MASK (0x000001FFu) + #define RSSI_INST_RSSI_INST_BIT (0) + #define RSSI_INST_RSSI_INST_BITS (9) + +#define FREQ_MEAS_CTRL1 *((volatile uint32_t *)0x400010D0u) +#define FREQ_MEAS_CTRL1_REG *((volatile uint32_t *)0x400010D0u) +#define FREQ_MEAS_CTRL1_ADDR (0x400010D0u) +#define FREQ_MEAS_CTRL1_RESET (0x00000160u) + /* AUTO_TUNE_EN field */ + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN (0x00008000u) + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_MASK (0x00008000u) + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BIT (15) + #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BITS (1) + /* FREQ_MEAS_EN field */ + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN (0x00004000u) + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_MASK (0x00004000u) + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BIT (14) + #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BITS (1) + /* OPEN_LOOP_MANUAL field */ + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL (0x00002000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_MASK (0x00002000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BIT (13) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BITS (1) + /* OPEN_LOOP field */ + #define FREQ_MEAS_CTRL1_OPEN_LOOP (0x00001000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_MASK (0x00001000u) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_BIT (12) + #define FREQ_MEAS_CTRL1_OPEN_LOOP_BITS (1) + /* DELAY_FIRST_MEAS field */ + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS (0x00000400u) + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_MASK (0x00000400u) + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BIT (10) + #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BITS (1) + /* DELAY_ALL_MEAS field */ + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS (0x00000200u) + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_MASK (0x00000200u) + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BIT (9) + #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BITS (1) + /* BIN_SEARCH_MSB field */ + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB (0x000001C0u) + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_MASK (0x000001C0u) + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BIT (6) + #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BITS (3) + /* TUNE_VCO_INIT field */ + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT (0x0000003Fu) + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_MASK (0x0000003Fu) + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT (0) + #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS (6) + +#define FREQ_MEAS_CTRL2 *((volatile uint32_t *)0x400010D4u) +#define FREQ_MEAS_CTRL2_REG *((volatile uint32_t *)0x400010D4u) +#define FREQ_MEAS_CTRL2_ADDR (0x400010D4u) +#define FREQ_MEAS_CTRL2_RESET (0x0000201Eu) + /* FREQ_MEAS_TIMER field */ + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER (0x0000FF00u) + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_MASK (0x0000FF00u) + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BIT (8) + #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BITS (8) + /* TARGET_PERIOD field */ + #define FREQ_MEAS_CTRL2_TARGET_PERIOD (0x000000FFu) + #define FREQ_MEAS_CTRL2_TARGET_PERIOD_MASK (0x000000FFu) + #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT (0) + #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS (8) + +#define FREQ_MEAS_SHIFT *((volatile uint32_t *)0x400010D8u) +#define FREQ_MEAS_SHIFT_REG *((volatile uint32_t *)0x400010D8u) +#define FREQ_MEAS_SHIFT_ADDR (0x400010D8u) +#define FREQ_MEAS_SHIFT_RESET (0x00000035u) + /* FREQ_MEAS_SHIFT field */ + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT (0x000000FFu) + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_MASK (0x000000FFu) + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT (0) + #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS (8) + +#define FREQ_MEAS_STATUS1 *((volatile uint32_t *)0x400010DCu) +#define FREQ_MEAS_STATUS1_REG *((volatile uint32_t *)0x400010DCu) +#define FREQ_MEAS_STATUS1_ADDR (0x400010DCu) +#define FREQ_MEAS_STATUS1_RESET (0x00000000u) + /* INVALID_EDGE field */ + #define FREQ_MEAS_STATUS1_INVALID_EDGE (0x00008000u) + #define FREQ_MEAS_STATUS1_INVALID_EDGE_MASK (0x00008000u) + #define FREQ_MEAS_STATUS1_INVALID_EDGE_BIT (15) + #define FREQ_MEAS_STATUS1_INVALID_EDGE_BITS (1) + /* SIGN_FOUND field */ + #define FREQ_MEAS_STATUS1_SIGN_FOUND (0x00004000u) + #define FREQ_MEAS_STATUS1_SIGN_FOUND_MASK (0x00004000u) + #define FREQ_MEAS_STATUS1_SIGN_FOUND_BIT (14) + #define FREQ_MEAS_STATUS1_SIGN_FOUND_BITS (1) + /* FREQ_SIGN field */ + #define FREQ_MEAS_STATUS1_FREQ_SIGN (0x00002000u) + #define FREQ_MEAS_STATUS1_FREQ_SIGN_MASK (0x00002000u) + #define FREQ_MEAS_STATUS1_FREQ_SIGN_BIT (13) + #define FREQ_MEAS_STATUS1_FREQ_SIGN_BITS (1) + /* PERIOD_FOUND field */ + #define FREQ_MEAS_STATUS1_PERIOD_FOUND (0x00001000u) + #define FREQ_MEAS_STATUS1_PERIOD_FOUND_MASK (0x00001000u) + #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BIT (12) + #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BITS (1) + /* NEAREST_DIFF field */ + #define FREQ_MEAS_STATUS1_NEAREST_DIFF (0x000003FFu) + #define FREQ_MEAS_STATUS1_NEAREST_DIFF_MASK (0x000003FFu) + #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT (0) + #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS (10) + +#define FREQ_MEAS_STATUS2 *((volatile uint32_t *)0x400010E0u) +#define FREQ_MEAS_STATUS2_REG *((volatile uint32_t *)0x400010E0u) +#define FREQ_MEAS_STATUS2_ADDR (0x400010E0u) +#define FREQ_MEAS_STATUS2_RESET (0x00000000u) + /* BEAT_TIMER field */ + #define FREQ_MEAS_STATUS2_BEAT_TIMER (0x0000FFC0u) + #define FREQ_MEAS_STATUS2_BEAT_TIMER_MASK (0x0000FFC0u) + #define FREQ_MEAS_STATUS2_BEAT_TIMER_BIT (6) + #define FREQ_MEAS_STATUS2_BEAT_TIMER_BITS (10) + /* BEATS field */ + #define FREQ_MEAS_STATUS2_BEATS (0x0000003Fu) + #define FREQ_MEAS_STATUS2_BEATS_MASK (0x0000003Fu) + #define FREQ_MEAS_STATUS2_BEATS_BIT (0) + #define FREQ_MEAS_STATUS2_BEATS_BITS (6) + +#define FREQ_MEAS_STATUS3 *((volatile uint32_t *)0x400010E4u) +#define FREQ_MEAS_STATUS3_REG *((volatile uint32_t *)0x400010E4u) +#define FREQ_MEAS_STATUS3_ADDR (0x400010E4u) +#define FREQ_MEAS_STATUS3_RESET (0x00000020u) + /* TUNE_VCO field */ + #define FREQ_MEAS_STATUS3_TUNE_VCO (0x0000003Fu) + #define FREQ_MEAS_STATUS3_TUNE_VCO_MASK (0x0000003Fu) + #define FREQ_MEAS_STATUS3_TUNE_VCO_BIT (0) + #define FREQ_MEAS_STATUS3_TUNE_VCO_BITS (6) + +#define SCR_CTRL *((volatile uint32_t *)0x400010E8u) +#define SCR_CTRL_REG *((volatile uint32_t *)0x400010E8u) +#define SCR_CTRL_ADDR (0x400010E8u) +#define SCR_CTRL_RESET (0x00000004u) + /* SCR_RESET field */ + #define SCR_CTRL_SCR_RESET (0x00000004u) + #define SCR_CTRL_SCR_RESET_MASK (0x00000004u) + #define SCR_CTRL_SCR_RESET_BIT (2) + #define SCR_CTRL_SCR_RESET_BITS (1) + /* SCR_WRITE field */ + #define SCR_CTRL_SCR_WRITE (0x00000002u) + #define SCR_CTRL_SCR_WRITE_MASK (0x00000002u) + #define SCR_CTRL_SCR_WRITE_BIT (1) + #define SCR_CTRL_SCR_WRITE_BITS (1) + /* SCR_READ field */ + #define SCR_CTRL_SCR_READ (0x00000001u) + #define SCR_CTRL_SCR_READ_MASK (0x00000001u) + #define SCR_CTRL_SCR_READ_BIT (0) + #define SCR_CTRL_SCR_READ_BITS (1) + +#define SCR_BUSY *((volatile uint32_t *)0x400010ECu) +#define SCR_BUSY_REG *((volatile uint32_t *)0x400010ECu) +#define SCR_BUSY_ADDR (0x400010ECu) +#define SCR_BUSY_RESET (0x00000000u) + /* SCR_BUSY field */ + #define SCR_BUSY_SCR_BUSY (0x00000001u) + #define SCR_BUSY_SCR_BUSY_MASK (0x00000001u) + #define SCR_BUSY_SCR_BUSY_BIT (0) + #define SCR_BUSY_SCR_BUSY_BITS (1) + +#define SCR_ADDR *((volatile uint32_t *)0x400010F0u) +#define SCR_ADDR_REG *((volatile uint32_t *)0x400010F0u) +#define SCR_ADDR_ADDR (0x400010F0u) +#define SCR_ADDR_RESET (0x00000000u) + /* SCR_ADDR field */ + #define SCR_ADDR_SCR_ADDR (0x000000FFu) + #define SCR_ADDR_SCR_ADDR_MASK (0x000000FFu) + #define SCR_ADDR_SCR_ADDR_BIT (0) + #define SCR_ADDR_SCR_ADDR_BITS (8) + +#define SCR_WRITE *((volatile uint32_t *)0x400010F4u) +#define SCR_WRITE_REG *((volatile uint32_t *)0x400010F4u) +#define SCR_WRITE_ADDR (0x400010F4u) +#define SCR_WRITE_RESET (0x00000000u) + /* SCR_WRITE field */ + #define SCR_WRITE_SCR_WRITE (0x0000FFFFu) + #define SCR_WRITE_SCR_WRITE_MASK (0x0000FFFFu) + #define SCR_WRITE_SCR_WRITE_BIT (0) + #define SCR_WRITE_SCR_WRITE_BITS (16) + +#define SCR_READ *((volatile uint32_t *)0x400010F8u) +#define SCR_READ_REG *((volatile uint32_t *)0x400010F8u) +#define SCR_READ_ADDR (0x400010F8u) +#define SCR_READ_RESET (0x00000000u) + /* SCR_READ field */ + #define SCR_READ_SCR_READ (0x0000FFFFu) + #define SCR_READ_SCR_READ_MASK (0x0000FFFFu) + #define SCR_READ_SCR_READ_BIT (0) + #define SCR_READ_SCR_READ_BITS (16) + +#define SYNTH_LOCK *((volatile uint32_t *)0x400010FCu) +#define SYNTH_LOCK_REG *((volatile uint32_t *)0x400010FCu) +#define SYNTH_LOCK_ADDR (0x400010FCu) +#define SYNTH_LOCK_RESET (0x00000000u) + /* IN_LOCK field */ + #define SYNTH_LOCK_IN_LOCK (0x00000001u) + #define SYNTH_LOCK_IN_LOCK_MASK (0x00000001u) + #define SYNTH_LOCK_IN_LOCK_BIT (0) + #define SYNTH_LOCK_IN_LOCK_BITS (1) + +#define AN_CAL_STATUS *((volatile uint32_t *)0x40001100u) +#define AN_CAL_STATUS_REG *((volatile uint32_t *)0x40001100u) +#define AN_CAL_STATUS_ADDR (0x40001100u) +#define AN_CAL_STATUS_RESET (0x00000000u) + /* VCO_CTRL field */ + #define AN_CAL_STATUS_VCO_CTRL (0x0000000Cu) + #define AN_CAL_STATUS_VCO_CTRL_MASK (0x0000000Cu) + #define AN_CAL_STATUS_VCO_CTRL_BIT (2) + #define AN_CAL_STATUS_VCO_CTRL_BITS (2) + +#define BIAS_CAL_STATUS *((volatile uint32_t *)0x40001104u) +#define BIAS_CAL_STATUS_REG *((volatile uint32_t *)0x40001104u) +#define BIAS_CAL_STATUS_ADDR (0x40001104u) +#define BIAS_CAL_STATUS_RESET (0x00000000u) + /* VCOMP field */ + #define BIAS_CAL_STATUS_VCOMP (0x00000002u) + #define BIAS_CAL_STATUS_VCOMP_MASK (0x00000002u) + #define BIAS_CAL_STATUS_VCOMP_BIT (1) + #define BIAS_CAL_STATUS_VCOMP_BITS (1) + /* ICOMP field */ + #define BIAS_CAL_STATUS_ICOMP (0x00000001u) + #define BIAS_CAL_STATUS_ICOMP_MASK (0x00000001u) + #define BIAS_CAL_STATUS_ICOMP_BIT (0) + #define BIAS_CAL_STATUS_ICOMP_BITS (1) + +#define ATEST_SEL *((volatile uint32_t *)0x40001108u) +#define ATEST_SEL_REG *((volatile uint32_t *)0x40001108u) +#define ATEST_SEL_ADDR (0x40001108u) +#define ATEST_SEL_RESET (0x00000000u) + /* ATEST_CTRL field */ + #define ATEST_SEL_ATEST_CTRL (0x0000FF00u) + #define ATEST_SEL_ATEST_CTRL_MASK (0x0000FF00u) + #define ATEST_SEL_ATEST_CTRL_BIT (8) + #define ATEST_SEL_ATEST_CTRL_BITS (8) + /* ATEST_SEL field */ + #define ATEST_SEL_ATEST_SEL (0x0000001Fu) + #define ATEST_SEL_ATEST_SEL_MASK (0x0000001Fu) + #define ATEST_SEL_ATEST_SEL_BIT (0) + #define ATEST_SEL_ATEST_SEL_BITS (5) + +#define AN_EN_TEST *((volatile uint32_t *)0x4000110Cu) +#define AN_EN_TEST_REG *((volatile uint32_t *)0x4000110Cu) +#define AN_EN_TEST_ADDR (0x4000110Cu) +#define AN_EN_TEST_RESET (0x00000000u) + /* AN_TEST_MODE field */ + #define AN_EN_TEST_AN_TEST_MODE (0x00008000u) + #define AN_EN_TEST_AN_TEST_MODE_MASK (0x00008000u) + #define AN_EN_TEST_AN_TEST_MODE_BIT (15) + #define AN_EN_TEST_AN_TEST_MODE_BITS (1) + /* PFD_EN field */ + #define AN_EN_TEST_PFD_EN (0x00004000u) + #define AN_EN_TEST_PFD_EN_MASK (0x00004000u) + #define AN_EN_TEST_PFD_EN_BIT (14) + #define AN_EN_TEST_PFD_EN_BITS (1) + /* ADC_EN field */ + #define AN_EN_TEST_ADC_EN (0x00002000u) + #define AN_EN_TEST_ADC_EN_MASK (0x00002000u) + #define AN_EN_TEST_ADC_EN_BIT (13) + #define AN_EN_TEST_ADC_EN_BITS (1) + /* UNUSED field */ + #define AN_EN_TEST_UNUSED (0x00001000u) + #define AN_EN_TEST_UNUSED_MASK (0x00001000u) + #define AN_EN_TEST_UNUSED_BIT (12) + #define AN_EN_TEST_UNUSED_BITS (1) + /* PRE_FILT_EN field */ + #define AN_EN_TEST_PRE_FILT_EN (0x00000800u) + #define AN_EN_TEST_PRE_FILT_EN_MASK (0x00000800u) + #define AN_EN_TEST_PRE_FILT_EN_BIT (11) + #define AN_EN_TEST_PRE_FILT_EN_BITS (1) + /* IF_AMP_EN field */ + #define AN_EN_TEST_IF_AMP_EN (0x00000400u) + #define AN_EN_TEST_IF_AMP_EN_MASK (0x00000400u) + #define AN_EN_TEST_IF_AMP_EN_BIT (10) + #define AN_EN_TEST_IF_AMP_EN_BITS (1) + /* LNA_EN field */ + #define AN_EN_TEST_LNA_EN (0x00000200u) + #define AN_EN_TEST_LNA_EN_MASK (0x00000200u) + #define AN_EN_TEST_LNA_EN_BIT (9) + #define AN_EN_TEST_LNA_EN_BITS (1) + /* MIXER_EN field */ + #define AN_EN_TEST_MIXER_EN (0x00000100u) + #define AN_EN_TEST_MIXER_EN_MASK (0x00000100u) + #define AN_EN_TEST_MIXER_EN_BIT (8) + #define AN_EN_TEST_MIXER_EN_BITS (1) + /* CH_FILT_EN field */ + #define AN_EN_TEST_CH_FILT_EN (0x00000080u) + #define AN_EN_TEST_CH_FILT_EN_MASK (0x00000080u) + #define AN_EN_TEST_CH_FILT_EN_BIT (7) + #define AN_EN_TEST_CH_FILT_EN_BITS (1) + /* MOD_DAC_EN field */ + #define AN_EN_TEST_MOD_DAC_EN (0x00000040u) + #define AN_EN_TEST_MOD_DAC_EN_MASK (0x00000040u) + #define AN_EN_TEST_MOD_DAC_EN_BIT (6) + #define AN_EN_TEST_MOD_DAC_EN_BITS (1) + /* PA_EN field */ + #define AN_EN_TEST_PA_EN (0x00000010u) + #define AN_EN_TEST_PA_EN_MASK (0x00000010u) + #define AN_EN_TEST_PA_EN_BIT (4) + #define AN_EN_TEST_PA_EN_BITS (1) + /* PRESCALER_EN field */ + #define AN_EN_TEST_PRESCALER_EN (0x00000008u) + #define AN_EN_TEST_PRESCALER_EN_MASK (0x00000008u) + #define AN_EN_TEST_PRESCALER_EN_BIT (3) + #define AN_EN_TEST_PRESCALER_EN_BITS (1) + /* VCO_EN field */ + #define AN_EN_TEST_VCO_EN (0x00000004u) + #define AN_EN_TEST_VCO_EN_MASK (0x00000004u) + #define AN_EN_TEST_VCO_EN_BIT (2) + #define AN_EN_TEST_VCO_EN_BITS (1) + /* BIAS_EN field */ + #define AN_EN_TEST_BIAS_EN (0x00000001u) + #define AN_EN_TEST_BIAS_EN_MASK (0x00000001u) + #define AN_EN_TEST_BIAS_EN_BIT (0) + #define AN_EN_TEST_BIAS_EN_BITS (1) + +#define TUNE_FILTER_CTRL *((volatile uint32_t *)0x40001110u) +#define TUNE_FILTER_CTRL_REG *((volatile uint32_t *)0x40001110u) +#define TUNE_FILTER_CTRL_ADDR (0x40001110u) +#define TUNE_FILTER_CTRL_RESET (0x00000000u) + /* TUNE_FILTER_EN field */ + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN (0x00000002u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_MASK (0x00000002u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BIT (1) + #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BITS (1) + /* TUNE_FILTER_RESET field */ + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET (0x00000001u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_MASK (0x00000001u) + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT (0) + #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS (1) + +#define NOISE_EN *((volatile uint32_t *)0x40001114u) +#define NOISE_EN_REG *((volatile uint32_t *)0x40001114u) +#define NOISE_EN_ADDR (0x40001114u) +#define NOISE_EN_RESET (0x00000000u) + /* NOISE_EN field */ + #define NOISE_EN_NOISE_EN (0x00000001u) + #define NOISE_EN_NOISE_EN_MASK (0x00000001u) + #define NOISE_EN_NOISE_EN_BIT (0) + #define NOISE_EN_NOISE_EN_BITS (1) + +/* MAC block */ +#define DATA_MAC_BASE (0x40002000u) +#define DATA_MAC_END (0x400020C8u) +#define DATA_MAC_SIZE (DATA_MAC_END - DATA_MAC_BASE + 1) + +#define MAC_RX_ST_ADDR_A *((volatile uint32_t *)0x40002000u) +#define MAC_RX_ST_ADDR_A_REG *((volatile uint32_t *)0x40002000u) +#define MAC_RX_ST_ADDR_A_ADDR (0x40002000u) +#define MAC_RX_ST_ADDR_A_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_ST_ADDR_A field */ + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A (0x00001FFEu) + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_MASK (0x00001FFEu) + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT (1) + #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS (12) + +#define MAC_RX_END_ADDR_A *((volatile uint32_t *)0x40002004u) +#define MAC_RX_END_ADDR_A_REG *((volatile uint32_t *)0x40002004u) +#define MAC_RX_END_ADDR_A_ADDR (0x40002004u) +#define MAC_RX_END_ADDR_A_RESET (0x20000088u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_END_ADDR_A field */ + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A (0x00001FFEu) + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_MASK (0x00001FFEu) + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT (1) + #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS (12) + +#define MAC_RX_ST_ADDR_B *((volatile uint32_t *)0x40002008u) +#define MAC_RX_ST_ADDR_B_REG *((volatile uint32_t *)0x40002008u) +#define MAC_RX_ST_ADDR_B_ADDR (0x40002008u) +#define MAC_RX_ST_ADDR_B_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_ST_ADDR_B field */ + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B (0x00001FFEu) + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_MASK (0x00001FFEu) + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT (1) + #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS (12) + +#define MAC_RX_END_ADDR_B *((volatile uint32_t *)0x4000200Cu) +#define MAC_RX_END_ADDR_B_REG *((volatile uint32_t *)0x4000200Cu) +#define MAC_RX_END_ADDR_B_ADDR (0x4000200Cu) +#define MAC_RX_END_ADDR_B_RESET (0x20000088u) + /* MAC_RAM_OFFS field */ + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_RX_END_ADDR_B field */ + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B (0x00001FFEu) + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_MASK (0x00001FFEu) + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT (1) + #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS (12) + +#define MAC_TX_ST_ADDR_A *((volatile uint32_t *)0x40002010u) +#define MAC_TX_ST_ADDR_A_REG *((volatile uint32_t *)0x40002010u) +#define MAC_TX_ST_ADDR_A_ADDR (0x40002010u) +#define MAC_TX_ST_ADDR_A_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_ST_ADDR_A field */ + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A (0x00001FFEu) + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_MASK (0x00001FFEu) + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT (1) + #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS (12) + +#define MAC_TX_END_ADDR_A *((volatile uint32_t *)0x40002014u) +#define MAC_TX_END_ADDR_A_REG *((volatile uint32_t *)0x40002014u) +#define MAC_TX_END_ADDR_A_ADDR (0x40002014u) +#define MAC_TX_END_ADDR_A_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_END_ADDR_A field */ + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A (0x00001FFEu) + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_MASK (0x00001FFEu) + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT (1) + #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS (12) + +#define MAC_TX_ST_ADDR_B *((volatile uint32_t *)0x40002018u) +#define MAC_TX_ST_ADDR_B_REG *((volatile uint32_t *)0x40002018u) +#define MAC_TX_ST_ADDR_B_ADDR (0x40002018u) +#define MAC_TX_ST_ADDR_B_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_ST_ADDR_B field */ + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B (0x00001FFEu) + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_MASK (0x00001FFEu) + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT (1) + #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS (12) + +#define MAC_TX_END_ADDR_B *((volatile uint32_t *)0x4000201Cu) +#define MAC_TX_END_ADDR_B_REG *((volatile uint32_t *)0x4000201Cu) +#define MAC_TX_END_ADDR_B_ADDR (0x4000201Cu) +#define MAC_TX_END_ADDR_B_RESET (0x20000000u) + /* MAC_RAM_OFFS field */ + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) + #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) + /* MAC_TX_END_ADDR_B field */ + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B (0x00001FFEu) + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_MASK (0x00001FFEu) + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT (1) + #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS (12) + +#define RX_A_COUNT *((volatile uint32_t *)0x40002020u) +#define RX_A_COUNT_REG *((volatile uint32_t *)0x40002020u) +#define RX_A_COUNT_ADDR (0x40002020u) +#define RX_A_COUNT_RESET (0x00000000u) + /* RX_A_COUNT field */ + #define RX_A_COUNT_RX_A_COUNT (0x000007FFu) + #define RX_A_COUNT_RX_A_COUNT_MASK (0x000007FFu) + #define RX_A_COUNT_RX_A_COUNT_BIT (0) + #define RX_A_COUNT_RX_A_COUNT_BITS (11) + +#define RX_B_COUNT *((volatile uint32_t *)0x40002024u) +#define RX_B_COUNT_REG *((volatile uint32_t *)0x40002024u) +#define RX_B_COUNT_ADDR (0x40002024u) +#define RX_B_COUNT_RESET (0x00000000u) + /* RX_B_COUNT field */ + #define RX_B_COUNT_RX_B_COUNT (0x000007FFu) + #define RX_B_COUNT_RX_B_COUNT_MASK (0x000007FFu) + #define RX_B_COUNT_RX_B_COUNT_BIT (0) + #define RX_B_COUNT_RX_B_COUNT_BITS (11) + +#define TX_COUNT *((volatile uint32_t *)0x40002028u) +#define TX_COUNT_REG *((volatile uint32_t *)0x40002028u) +#define TX_COUNT_ADDR (0x40002028u) +#define TX_COUNT_RESET (0x00000000u) + /* TX_COUNT field */ + #define TX_COUNT_TX_COUNT (0x000007FFu) + #define TX_COUNT_TX_COUNT_MASK (0x000007FFu) + #define TX_COUNT_TX_COUNT_BIT (0) + #define TX_COUNT_TX_COUNT_BITS (11) + +#define MAC_DMA_STATUS *((volatile uint32_t *)0x4000202Cu) +#define MAC_DMA_STATUS_REG *((volatile uint32_t *)0x4000202Cu) +#define MAC_DMA_STATUS_ADDR (0x4000202Cu) +#define MAC_DMA_STATUS_RESET (0x00000000u) + /* TX_ACTIVE_B field */ + #define MAC_DMA_STATUS_TX_ACTIVE_B (0x00000008u) + #define MAC_DMA_STATUS_TX_ACTIVE_B_MASK (0x00000008u) + #define MAC_DMA_STATUS_TX_ACTIVE_B_BIT (3) + #define MAC_DMA_STATUS_TX_ACTIVE_B_BITS (1) + /* TX_ACTIVE_A field */ + #define MAC_DMA_STATUS_TX_ACTIVE_A (0x00000004u) + #define MAC_DMA_STATUS_TX_ACTIVE_A_MASK (0x00000004u) + #define MAC_DMA_STATUS_TX_ACTIVE_A_BIT (2) + #define MAC_DMA_STATUS_TX_ACTIVE_A_BITS (1) + /* RX_ACTIVE_B field */ + #define MAC_DMA_STATUS_RX_ACTIVE_B (0x00000002u) + #define MAC_DMA_STATUS_RX_ACTIVE_B_MASK (0x00000002u) + #define MAC_DMA_STATUS_RX_ACTIVE_B_BIT (1) + #define MAC_DMA_STATUS_RX_ACTIVE_B_BITS (1) + /* RX_ACTIVE_A field */ + #define MAC_DMA_STATUS_RX_ACTIVE_A (0x00000001u) + #define MAC_DMA_STATUS_RX_ACTIVE_A_MASK (0x00000001u) + #define MAC_DMA_STATUS_RX_ACTIVE_A_BIT (0) + #define MAC_DMA_STATUS_RX_ACTIVE_A_BITS (1) + +#define MAC_DMA_CONFIG *((volatile uint32_t *)0x40002030u) +#define MAC_DMA_CONFIG_REG *((volatile uint32_t *)0x40002030u) +#define MAC_DMA_CONFIG_ADDR (0x40002030u) +#define MAC_DMA_CONFIG_RESET (0x00000000u) + /* TX_DMA_RESET field */ + #define MAC_DMA_CONFIG_TX_DMA_RESET (0x00000020u) + #define MAC_DMA_CONFIG_TX_DMA_RESET_MASK (0x00000020u) + #define MAC_DMA_CONFIG_TX_DMA_RESET_BIT (5) + #define MAC_DMA_CONFIG_TX_DMA_RESET_BITS (1) + /* RX_DMA_RESET field */ + #define MAC_DMA_CONFIG_RX_DMA_RESET (0x00000010u) + #define MAC_DMA_CONFIG_RX_DMA_RESET_MASK (0x00000010u) + #define MAC_DMA_CONFIG_RX_DMA_RESET_BIT (4) + #define MAC_DMA_CONFIG_RX_DMA_RESET_BITS (1) + /* TX_LOAD_B field */ + #define MAC_DMA_CONFIG_TX_LOAD_B (0x00000008u) + #define MAC_DMA_CONFIG_TX_LOAD_B_MASK (0x00000008u) + #define MAC_DMA_CONFIG_TX_LOAD_B_BIT (3) + #define MAC_DMA_CONFIG_TX_LOAD_B_BITS (1) + /* TX_LOAD_A field */ + #define MAC_DMA_CONFIG_TX_LOAD_A (0x00000004u) + #define MAC_DMA_CONFIG_TX_LOAD_A_MASK (0x00000004u) + #define MAC_DMA_CONFIG_TX_LOAD_A_BIT (2) + #define MAC_DMA_CONFIG_TX_LOAD_A_BITS (1) + /* RX_LOAD_B field */ + #define MAC_DMA_CONFIG_RX_LOAD_B (0x00000002u) + #define MAC_DMA_CONFIG_RX_LOAD_B_MASK (0x00000002u) + #define MAC_DMA_CONFIG_RX_LOAD_B_BIT (1) + #define MAC_DMA_CONFIG_RX_LOAD_B_BITS (1) + /* RX_LOAD_A field */ + #define MAC_DMA_CONFIG_RX_LOAD_A (0x00000001u) + #define MAC_DMA_CONFIG_RX_LOAD_A_MASK (0x00000001u) + #define MAC_DMA_CONFIG_RX_LOAD_A_BIT (0) + #define MAC_DMA_CONFIG_RX_LOAD_A_BITS (1) + +#define MAC_TIMER *((volatile uint32_t *)0x40002038u) +#define MAC_TIMER_REG *((volatile uint32_t *)0x40002038u) +#define MAC_TIMER_ADDR (0x40002038u) +#define MAC_TIMER_RESET (0x00000000u) + /* MAC_TIMER field */ + #define MAC_TIMER_MAC_TIMER (0x000FFFFFu) + #define MAC_TIMER_MAC_TIMER_MASK (0x000FFFFFu) + #define MAC_TIMER_MAC_TIMER_BIT (0) + #define MAC_TIMER_MAC_TIMER_BITS (20) + +#define MAC_TIMER_COMPARE_A_H *((volatile uint32_t *)0x40002040u) +#define MAC_TIMER_COMPARE_A_H_REG *((volatile uint32_t *)0x40002040u) +#define MAC_TIMER_COMPARE_A_H_ADDR (0x40002040u) +#define MAC_TIMER_COMPARE_A_H_RESET (0x00000000u) + /* MAC_COMPARE_A_H field */ + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H (0x0000000Fu) + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_MASK (0x0000000Fu) + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT (0) + #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS (4) + +#define MAC_TIMER_COMPARE_A_L *((volatile uint32_t *)0x40002044u) +#define MAC_TIMER_COMPARE_A_L_REG *((volatile uint32_t *)0x40002044u) +#define MAC_TIMER_COMPARE_A_L_ADDR (0x40002044u) +#define MAC_TIMER_COMPARE_A_L_RESET (0x00000000u) + /* MAC_COMPARE_A_L field */ + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L (0x0000FFFFu) + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_MASK (0x0000FFFFu) + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT (0) + #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS (16) + +#define MAC_TIMER_COMPARE_B_H *((volatile uint32_t *)0x40002048u) +#define MAC_TIMER_COMPARE_B_H_REG *((volatile uint32_t *)0x40002048u) +#define MAC_TIMER_COMPARE_B_H_ADDR (0x40002048u) +#define MAC_TIMER_COMPARE_B_H_RESET (0x00000000u) + /* MAC_COMPARE_B_H field */ + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H (0x0000000Fu) + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_MASK (0x0000000Fu) + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT (0) + #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS (4) + +#define MAC_TIMER_COMPARE_B_L *((volatile uint32_t *)0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L_REG *((volatile uint32_t *)0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L_ADDR (0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L_RESET (0x00000000u) + /* MAC_COMPARE_B_L field */ + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L (0x0000FFFFu) + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_MASK (0x0000FFFFu) + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT (0) + #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS (16) + +#define MAC_TIMER_CAPTURE_H *((volatile uint32_t *)0x40002050u) +#define MAC_TIMER_CAPTURE_H_REG *((volatile uint32_t *)0x40002050u) +#define MAC_TIMER_CAPTURE_H_ADDR (0x40002050u) +#define MAC_TIMER_CAPTURE_H_RESET (0x00000000u) + /* MAC_SFD_CAPTURE_HIGH field */ + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH (0x0000000Fu) + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_MASK (0x0000000Fu) + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT (0) + #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS (4) + +#define MAC_TIMER_CAPTURE_L *((volatile uint32_t *)0x40002054u) +#define MAC_TIMER_CAPTURE_L_REG *((volatile uint32_t *)0x40002054u) +#define MAC_TIMER_CAPTURE_L_ADDR (0x40002054u) +#define MAC_TIMER_CAPTURE_L_RESET (0x00000000u) + /* MAC_SFD_CAPTURE_LOW field */ + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW (0x0000FFFFu) + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_MASK (0x0000FFFFu) + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT (0) + #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS (16) + +#define MAC_BO_TIMER *((volatile uint32_t *)0x40002058u) +#define MAC_BO_TIMER_REG *((volatile uint32_t *)0x40002058u) +#define MAC_BO_TIMER_ADDR (0x40002058u) +#define MAC_BO_TIMER_RESET (0x00000000u) + /* MAC_BO_TIMER field */ + #define MAC_BO_TIMER_MAC_BO_TIMER (0x00000FFFu) + #define MAC_BO_TIMER_MAC_BO_TIMER_MASK (0x00000FFFu) + #define MAC_BO_TIMER_MAC_BO_TIMER_BIT (0) + #define MAC_BO_TIMER_MAC_BO_TIMER_BITS (12) + +#define MAC_BOP_TIMER *((volatile uint32_t *)0x4000205Cu) +#define MAC_BOP_TIMER_REG *((volatile uint32_t *)0x4000205Cu) +#define MAC_BOP_TIMER_ADDR (0x4000205Cu) +#define MAC_BOP_TIMER_RESET (0x00000000u) + /* MAC_BOP_TIMER field */ + #define MAC_BOP_TIMER_MAC_BOP_TIMER (0x0000007Fu) + #define MAC_BOP_TIMER_MAC_BOP_TIMER_MASK (0x0000007Fu) + #define MAC_BOP_TIMER_MAC_BOP_TIMER_BIT (0) + #define MAC_BOP_TIMER_MAC_BOP_TIMER_BITS (7) + +#define MAC_TX_STROBE *((volatile uint32_t *)0x40002060u) +#define MAC_TX_STROBE_REG *((volatile uint32_t *)0x40002060u) +#define MAC_TX_STROBE_ADDR (0x40002060u) +#define MAC_TX_STROBE_RESET (0x00000000u) + /* AUTO_CRC_TX field */ + #define MAC_TX_STROBE_AUTO_CRC_TX (0x00000008u) + #define MAC_TX_STROBE_AUTO_CRC_TX_MASK (0x00000008u) + #define MAC_TX_STROBE_AUTO_CRC_TX_BIT (3) + #define MAC_TX_STROBE_AUTO_CRC_TX_BITS (1) + /* CCA_ON field */ + #define MAC_TX_STROBE_CCA_ON (0x00000004u) + #define MAC_TX_STROBE_CCA_ON_MASK (0x00000004u) + #define MAC_TX_STROBE_CCA_ON_BIT (2) + #define MAC_TX_STROBE_CCA_ON_BITS (1) + /* MAC_TX_RST field */ + #define MAC_TX_STROBE_MAC_TX_RST (0x00000002u) + #define MAC_TX_STROBE_MAC_TX_RST_MASK (0x00000002u) + #define MAC_TX_STROBE_MAC_TX_RST_BIT (1) + #define MAC_TX_STROBE_MAC_TX_RST_BITS (1) + /* START_TX field */ + #define MAC_TX_STROBE_START_TX (0x00000001u) + #define MAC_TX_STROBE_START_TX_MASK (0x00000001u) + #define MAC_TX_STROBE_START_TX_BIT (0) + #define MAC_TX_STROBE_START_TX_BITS (1) + +#define MAC_ACK_STROBE *((volatile uint32_t *)0x40002064u) +#define MAC_ACK_STROBE_REG *((volatile uint32_t *)0x40002064u) +#define MAC_ACK_STROBE_ADDR (0x40002064u) +#define MAC_ACK_STROBE_RESET (0x00000000u) + /* MANUAL_ACK field */ + #define MAC_ACK_STROBE_MANUAL_ACK (0x00000002u) + #define MAC_ACK_STROBE_MANUAL_ACK_MASK (0x00000002u) + #define MAC_ACK_STROBE_MANUAL_ACK_BIT (1) + #define MAC_ACK_STROBE_MANUAL_ACK_BITS (1) + /* FRAME_PENDING field */ + #define MAC_ACK_STROBE_FRAME_PENDING (0x00000001u) + #define MAC_ACK_STROBE_FRAME_PENDING_MASK (0x00000001u) + #define MAC_ACK_STROBE_FRAME_PENDING_BIT (0) + #define MAC_ACK_STROBE_FRAME_PENDING_BITS (1) + +#define MAC_STATUS *((volatile uint32_t *)0x40002068u) +#define MAC_STATUS_REG *((volatile uint32_t *)0x40002068u) +#define MAC_STATUS_ADDR (0x40002068u) +#define MAC_STATUS_RESET (0x00000000u) + /* RX_B_PEND_TX_ACK field */ + #define MAC_STATUS_RX_B_PEND_TX_ACK (0x00000800u) + #define MAC_STATUS_RX_B_PEND_TX_ACK_MASK (0x00000800u) + #define MAC_STATUS_RX_B_PEND_TX_ACK_BIT (11) + #define MAC_STATUS_RX_B_PEND_TX_ACK_BITS (1) + /* RX_A_PEND_TX_ACK field */ + #define MAC_STATUS_RX_A_PEND_TX_ACK (0x00000400u) + #define MAC_STATUS_RX_A_PEND_TX_ACK_MASK (0x00000400u) + #define MAC_STATUS_RX_A_PEND_TX_ACK_BIT (10) + #define MAC_STATUS_RX_A_PEND_TX_ACK_BITS (1) + /* RX_B_LAST_UNLOAD field */ + #define MAC_STATUS_RX_B_LAST_UNLOAD (0x00000200u) + #define MAC_STATUS_RX_B_LAST_UNLOAD_MASK (0x00000200u) + #define MAC_STATUS_RX_B_LAST_UNLOAD_BIT (9) + #define MAC_STATUS_RX_B_LAST_UNLOAD_BITS (1) + /* RX_A_LAST_UNLOAD field */ + #define MAC_STATUS_RX_A_LAST_UNLOAD (0x00000100u) + #define MAC_STATUS_RX_A_LAST_UNLOAD_MASK (0x00000100u) + #define MAC_STATUS_RX_A_LAST_UNLOAD_BIT (8) + #define MAC_STATUS_RX_A_LAST_UNLOAD_BITS (1) + /* WRONG_FORMAT field */ + #define MAC_STATUS_WRONG_FORMAT (0x00000080u) + #define MAC_STATUS_WRONG_FORMAT_MASK (0x00000080u) + #define MAC_STATUS_WRONG_FORMAT_BIT (7) + #define MAC_STATUS_WRONG_FORMAT_BITS (1) + /* WRONG_ADDRESS field */ + #define MAC_STATUS_WRONG_ADDRESS (0x00000040u) + #define MAC_STATUS_WRONG_ADDRESS_MASK (0x00000040u) + #define MAC_STATUS_WRONG_ADDRESS_BIT (6) + #define MAC_STATUS_WRONG_ADDRESS_BITS (1) + /* RX_ACK_REC field */ + #define MAC_STATUS_RX_ACK_REC (0x00000020u) + #define MAC_STATUS_RX_ACK_REC_MASK (0x00000020u) + #define MAC_STATUS_RX_ACK_REC_BIT (5) + #define MAC_STATUS_RX_ACK_REC_BITS (1) + /* SENDING_ACK field */ + #define MAC_STATUS_SENDING_ACK (0x00000010u) + #define MAC_STATUS_SENDING_ACK_MASK (0x00000010u) + #define MAC_STATUS_SENDING_ACK_BIT (4) + #define MAC_STATUS_SENDING_ACK_BITS (1) + /* RUN_BO field */ + #define MAC_STATUS_RUN_BO (0x00000008u) + #define MAC_STATUS_RUN_BO_MASK (0x00000008u) + #define MAC_STATUS_RUN_BO_BIT (3) + #define MAC_STATUS_RUN_BO_BITS (1) + /* TX_FRAME field */ + #define MAC_STATUS_TX_FRAME (0x00000004u) + #define MAC_STATUS_TX_FRAME_MASK (0x00000004u) + #define MAC_STATUS_TX_FRAME_BIT (2) + #define MAC_STATUS_TX_FRAME_BITS (1) + /* RX_FRAME field */ + #define MAC_STATUS_RX_FRAME (0x00000002u) + #define MAC_STATUS_RX_FRAME_MASK (0x00000002u) + #define MAC_STATUS_RX_FRAME_BIT (1) + #define MAC_STATUS_RX_FRAME_BITS (1) + /* RX_CRC_PASS field */ + #define MAC_STATUS_RX_CRC_PASS (0x00000001u) + #define MAC_STATUS_RX_CRC_PASS_MASK (0x00000001u) + #define MAC_STATUS_RX_CRC_PASS_BIT (0) + #define MAC_STATUS_RX_CRC_PASS_BITS (1) + +#define TX_CRC *((volatile uint32_t *)0x4000206Cu) +#define TX_CRC_REG *((volatile uint32_t *)0x4000206Cu) +#define TX_CRC_ADDR (0x4000206Cu) +#define TX_CRC_RESET (0x00000000u) + /* TX_CRC field */ + #define TX_CRC_TX_CRC (0x0000FFFFu) + #define TX_CRC_TX_CRC_MASK (0x0000FFFFu) + #define TX_CRC_TX_CRC_BIT (0) + #define TX_CRC_TX_CRC_BITS (16) + +#define RX_CRC *((volatile uint32_t *)0x40002070u) +#define RX_CRC_REG *((volatile uint32_t *)0x40002070u) +#define RX_CRC_ADDR (0x40002070u) +#define RX_CRC_RESET (0x00000000u) + /* RX_CRC field */ + #define RX_CRC_RX_CRC (0x0000FFFFu) + #define RX_CRC_RX_CRC_MASK (0x0000FFFFu) + #define RX_CRC_RX_CRC_BIT (0) + #define RX_CRC_RX_CRC_BITS (16) + +#define MAC_ACK_TO *((volatile uint32_t *)0x40002074u) +#define MAC_ACK_TO_REG *((volatile uint32_t *)0x40002074u) +#define MAC_ACK_TO_ADDR (0x40002074u) +#define MAC_ACK_TO_RESET (0x00000300u) + /* ACK_TO field */ + #define MAC_ACK_TO_ACK_TO (0x00003FFFu) + #define MAC_ACK_TO_ACK_TO_MASK (0x00003FFFu) + #define MAC_ACK_TO_ACK_TO_BIT (0) + #define MAC_ACK_TO_ACK_TO_BITS (14) + +#define MAC_BOP_COMPARE *((volatile uint32_t *)0x40002078u) +#define MAC_BOP_COMPARE_REG *((volatile uint32_t *)0x40002078u) +#define MAC_BOP_COMPARE_ADDR (0x40002078u) +#define MAC_BOP_COMPARE_RESET (0x00000014u) + /* MAC_BOP_COMPARE field */ + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE (0x0000007Fu) + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_MASK (0x0000007Fu) + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT (0) + #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS (7) + +#define MAC_TX_ACK_FRAME *((volatile uint32_t *)0x4000207Cu) +#define MAC_TX_ACK_FRAME_REG *((volatile uint32_t *)0x4000207Cu) +#define MAC_TX_ACK_FRAME_ADDR (0x4000207Cu) +#define MAC_TX_ACK_FRAME_RESET (0x00000002u) + /* ACK_SRC_AM field */ + #define MAC_TX_ACK_FRAME_ACK_SRC_AM (0x0000C000u) + #define MAC_TX_ACK_FRAME_ACK_SRC_AM_MASK (0x0000C000u) + #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BIT (14) + #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BITS (2) + /* RES1213 field */ + #define MAC_TX_ACK_FRAME_RES1213 (0x00003000u) + #define MAC_TX_ACK_FRAME_RES1213_MASK (0x00003000u) + #define MAC_TX_ACK_FRAME_RES1213_BIT (12) + #define MAC_TX_ACK_FRAME_RES1213_BITS (2) + /* ACK_DST_AM field */ + #define MAC_TX_ACK_FRAME_ACK_DST_AM (0x00000C00u) + #define MAC_TX_ACK_FRAME_ACK_DST_AM_MASK (0x00000C00u) + #define MAC_TX_ACK_FRAME_ACK_DST_AM_BIT (10) + #define MAC_TX_ACK_FRAME_ACK_DST_AM_BITS (2) + /* RES789 field */ + #define MAC_TX_ACK_FRAME_RES789 (0x00000380u) + #define MAC_TX_ACK_FRAME_RES789_MASK (0x00000380u) + #define MAC_TX_ACK_FRAME_RES789_BIT (7) + #define MAC_TX_ACK_FRAME_RES789_BITS (3) + /* ACK_IP field */ + #define MAC_TX_ACK_FRAME_ACK_IP (0x00000040u) + #define MAC_TX_ACK_FRAME_ACK_IP_MASK (0x00000040u) + #define MAC_TX_ACK_FRAME_ACK_IP_BIT (6) + #define MAC_TX_ACK_FRAME_ACK_IP_BITS (1) + /* ACK_ACK_REQ field */ + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ (0x00000020u) + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_MASK (0x00000020u) + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BIT (5) + #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BITS (1) + /* ACK_FRAME_P field */ + #define MAC_TX_ACK_FRAME_ACK_FRAME_P (0x00000010u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_P_MASK (0x00000010u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BIT (4) + #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BITS (1) + /* ACK_SEC_EN field */ + #define MAC_TX_ACK_FRAME_ACK_SEC_EN (0x00000008u) + #define MAC_TX_ACK_FRAME_ACK_SEC_EN_MASK (0x00000008u) + #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BIT (3) + #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BITS (1) + /* ACK_FRAME_T field */ + #define MAC_TX_ACK_FRAME_ACK_FRAME_T (0x00000007u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_T_MASK (0x00000007u) + #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT (0) + #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS (3) + +#define MAC_CONFIG *((volatile uint32_t *)0x40002080u) +#define MAC_CONFIG_REG *((volatile uint32_t *)0x40002080u) +#define MAC_CONFIG_ADDR (0x40002080u) +#define MAC_CONFIG_RESET (0x00000000u) + /* RSSI_INST_EN field */ + #define MAC_CONFIG_RSSI_INST_EN (0x00000004u) + #define MAC_CONFIG_RSSI_INST_EN_MASK (0x00000004u) + #define MAC_CONFIG_RSSI_INST_EN_BIT (2) + #define MAC_CONFIG_RSSI_INST_EN_BITS (1) + /* SPI_SPY_EN field */ + #define MAC_CONFIG_SPI_SPY_EN (0x00000002u) + #define MAC_CONFIG_SPI_SPY_EN_MASK (0x00000002u) + #define MAC_CONFIG_SPI_SPY_EN_BIT (1) + #define MAC_CONFIG_SPI_SPY_EN_BITS (1) + /* MAC_MODE field */ + #define MAC_CONFIG_MAC_MODE (0x00000001u) + #define MAC_CONFIG_MAC_MODE_MASK (0x00000001u) + #define MAC_CONFIG_MAC_MODE_BIT (0) + #define MAC_CONFIG_MAC_MODE_BITS (1) + +#define MAC_RX_CONFIG *((volatile uint32_t *)0x40002084u) +#define MAC_RX_CONFIG_REG *((volatile uint32_t *)0x40002084u) +#define MAC_RX_CONFIG_ADDR (0x40002084u) +#define MAC_RX_CONFIG_RESET (0x00000000u) + /* AUTO_ACK field */ + #define MAC_RX_CONFIG_AUTO_ACK (0x00000080u) + #define MAC_RX_CONFIG_AUTO_ACK_MASK (0x00000080u) + #define MAC_RX_CONFIG_AUTO_ACK_BIT (7) + #define MAC_RX_CONFIG_AUTO_ACK_BITS (1) + /* APPEND_INFO field */ + #define MAC_RX_CONFIG_APPEND_INFO (0x00000040u) + #define MAC_RX_CONFIG_APPEND_INFO_MASK (0x00000040u) + #define MAC_RX_CONFIG_APPEND_INFO_BIT (6) + #define MAC_RX_CONFIG_APPEND_INFO_BITS (1) + /* COORDINATOR field */ + #define MAC_RX_CONFIG_COORDINATOR (0x00000020u) + #define MAC_RX_CONFIG_COORDINATOR_MASK (0x00000020u) + #define MAC_RX_CONFIG_COORDINATOR_BIT (5) + #define MAC_RX_CONFIG_COORDINATOR_BITS (1) + /* FILT_ADDR_ON field */ + #define MAC_RX_CONFIG_FILT_ADDR_ON (0x00000010u) + #define MAC_RX_CONFIG_FILT_ADDR_ON_MASK (0x00000010u) + #define MAC_RX_CONFIG_FILT_ADDR_ON_BIT (4) + #define MAC_RX_CONFIG_FILT_ADDR_ON_BITS (1) + /* RES_FILT_PASS_ADDR field */ + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR (0x00000008u) + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_MASK (0x00000008u) + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BIT (3) + #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BITS (1) + /* RES_FILT_PASS field */ + #define MAC_RX_CONFIG_RES_FILT_PASS (0x00000004u) + #define MAC_RX_CONFIG_RES_FILT_PASS_MASK (0x00000004u) + #define MAC_RX_CONFIG_RES_FILT_PASS_BIT (2) + #define MAC_RX_CONFIG_RES_FILT_PASS_BITS (1) + /* FILT_FORMAT_ON field */ + #define MAC_RX_CONFIG_FILT_FORMAT_ON (0x00000002u) + #define MAC_RX_CONFIG_FILT_FORMAT_ON_MASK (0x00000002u) + #define MAC_RX_CONFIG_FILT_FORMAT_ON_BIT (1) + #define MAC_RX_CONFIG_FILT_FORMAT_ON_BITS (1) + /* MAC_RX_RST field */ + #define MAC_RX_CONFIG_MAC_RX_RST (0x00000001u) + #define MAC_RX_CONFIG_MAC_RX_RST_MASK (0x00000001u) + #define MAC_RX_CONFIG_MAC_RX_RST_BIT (0) + #define MAC_RX_CONFIG_MAC_RX_RST_BITS (1) + +#define MAC_TX_CONFIG *((volatile uint32_t *)0x40002088u) +#define MAC_TX_CONFIG_REG *((volatile uint32_t *)0x40002088u) +#define MAC_TX_CONFIG_ADDR (0x40002088u) +#define MAC_TX_CONFIG_RESET (0x00000008u) + /* SLOTTED field */ + #define MAC_TX_CONFIG_SLOTTED (0x00000010u) + #define MAC_TX_CONFIG_SLOTTED_MASK (0x00000010u) + #define MAC_TX_CONFIG_SLOTTED_BIT (4) + #define MAC_TX_CONFIG_SLOTTED_BITS (1) + /* CCA_DELAY field */ + #define MAC_TX_CONFIG_CCA_DELAY (0x00000008u) + #define MAC_TX_CONFIG_CCA_DELAY_MASK (0x00000008u) + #define MAC_TX_CONFIG_CCA_DELAY_BIT (3) + #define MAC_TX_CONFIG_CCA_DELAY_BITS (1) + /* SLOTTED_ACK field */ + #define MAC_TX_CONFIG_SLOTTED_ACK (0x00000004u) + #define MAC_TX_CONFIG_SLOTTED_ACK_MASK (0x00000004u) + #define MAC_TX_CONFIG_SLOTTED_ACK_BIT (2) + #define MAC_TX_CONFIG_SLOTTED_ACK_BITS (1) + /* INFINITE_CRC field */ + #define MAC_TX_CONFIG_INFINITE_CRC (0x00000002u) + #define MAC_TX_CONFIG_INFINITE_CRC_MASK (0x00000002u) + #define MAC_TX_CONFIG_INFINITE_CRC_BIT (1) + #define MAC_TX_CONFIG_INFINITE_CRC_BITS (1) + /* WAIT_ACK field */ + #define MAC_TX_CONFIG_WAIT_ACK (0x00000001u) + #define MAC_TX_CONFIG_WAIT_ACK_MASK (0x00000001u) + #define MAC_TX_CONFIG_WAIT_ACK_BIT (0) + #define MAC_TX_CONFIG_WAIT_ACK_BITS (1) + +#define MAC_TIMER_CTRL *((volatile uint32_t *)0x4000208Cu) +#define MAC_TIMER_CTRL_REG *((volatile uint32_t *)0x4000208Cu) +#define MAC_TIMER_CTRL_ADDR (0x4000208Cu) +#define MAC_TIMER_CTRL_RESET (0x00000000u) + /* COMP_A_SYNC field */ + #define MAC_TIMER_CTRL_COMP_A_SYNC (0x00000040u) + #define MAC_TIMER_CTRL_COMP_A_SYNC_MASK (0x00000040u) + #define MAC_TIMER_CTRL_COMP_A_SYNC_BIT (6) + #define MAC_TIMER_CTRL_COMP_A_SYNC_BITS (1) + /* BOP_TIMER_RST field */ + #define MAC_TIMER_CTRL_BOP_TIMER_RST (0x00000020u) + #define MAC_TIMER_CTRL_BOP_TIMER_RST_MASK (0x00000020u) + #define MAC_TIMER_CTRL_BOP_TIMER_RST_BIT (5) + #define MAC_TIMER_CTRL_BOP_TIMER_RST_BITS (1) + /* BOP_TIMER_EN field */ + #define MAC_TIMER_CTRL_BOP_TIMER_EN (0x00000010u) + #define MAC_TIMER_CTRL_BOP_TIMER_EN_MASK (0x00000010u) + #define MAC_TIMER_CTRL_BOP_TIMER_EN_BIT (4) + #define MAC_TIMER_CTRL_BOP_TIMER_EN_BITS (1) + /* BO_TIMER_RST field */ + #define MAC_TIMER_CTRL_BO_TIMER_RST (0x00000008u) + #define MAC_TIMER_CTRL_BO_TIMER_RST_MASK (0x00000008u) + #define MAC_TIMER_CTRL_BO_TIMER_RST_BIT (3) + #define MAC_TIMER_CTRL_BO_TIMER_RST_BITS (1) + /* BO_TIMER_EN field */ + #define MAC_TIMER_CTRL_BO_TIMER_EN (0x00000004u) + #define MAC_TIMER_CTRL_BO_TIMER_EN_MASK (0x00000004u) + #define MAC_TIMER_CTRL_BO_TIMER_EN_BIT (2) + #define MAC_TIMER_CTRL_BO_TIMER_EN_BITS (1) + /* MAC_TIMER_RST field */ + #define MAC_TIMER_CTRL_MAC_TIMER_RST (0x00000002u) + #define MAC_TIMER_CTRL_MAC_TIMER_RST_MASK (0x00000002u) + #define MAC_TIMER_CTRL_MAC_TIMER_RST_BIT (1) + #define MAC_TIMER_CTRL_MAC_TIMER_RST_BITS (1) + /* MAC_TIMER_EN field */ + #define MAC_TIMER_CTRL_MAC_TIMER_EN (0x00000001u) + #define MAC_TIMER_CTRL_MAC_TIMER_EN_MASK (0x00000001u) + #define MAC_TIMER_CTRL_MAC_TIMER_EN_BIT (0) + #define MAC_TIMER_CTRL_MAC_TIMER_EN_BITS (1) + +#define PAN_ID *((volatile uint32_t *)0x40002090u) +#define PAN_ID_REG *((volatile uint32_t *)0x40002090u) +#define PAN_ID_ADDR (0x40002090u) +#define PAN_ID_RESET (0x00000000u) + /* PAN_ID field */ + #define PAN_ID_PAN_ID (0x0000FFFFu) + #define PAN_ID_PAN_ID_MASK (0x0000FFFFu) + #define PAN_ID_PAN_ID_BIT (0) + #define PAN_ID_PAN_ID_BITS (16) + +#define SHORT_ADDR *((volatile uint32_t *)0x40002094u) +#define SHORT_ADDR_REG *((volatile uint32_t *)0x40002094u) +#define SHORT_ADDR_ADDR (0x40002094u) +#define SHORT_ADDR_RESET (0x00000000u) + /* SHORT_ADDR field */ + #define SHORT_ADDR_SHORT_ADDR (0x0000FFFFu) + #define SHORT_ADDR_SHORT_ADDR_MASK (0x0000FFFFu) + #define SHORT_ADDR_SHORT_ADDR_BIT (0) + #define SHORT_ADDR_SHORT_ADDR_BITS (16) + +#define EXT_ADDR_0 *((volatile uint32_t *)0x40002098u) +#define EXT_ADDR_0_REG *((volatile uint32_t *)0x40002098u) +#define EXT_ADDR_0_ADDR (0x40002098u) +#define EXT_ADDR_0_RESET (0x00000000u) + /* EXT_ADDR_0 field */ + #define EXT_ADDR_0_EXT_ADDR_0 (0x0000FFFFu) + #define EXT_ADDR_0_EXT_ADDR_0_MASK (0x0000FFFFu) + #define EXT_ADDR_0_EXT_ADDR_0_BIT (0) + #define EXT_ADDR_0_EXT_ADDR_0_BITS (16) + +#define EXT_ADDR_1 *((volatile uint32_t *)0x4000209Cu) +#define EXT_ADDR_1_REG *((volatile uint32_t *)0x4000209Cu) +#define EXT_ADDR_1_ADDR (0x4000209Cu) +#define EXT_ADDR_1_RESET (0x00000000u) + /* EXT_ADDR_1 field */ + #define EXT_ADDR_1_EXT_ADDR_1 (0x0000FFFFu) + #define EXT_ADDR_1_EXT_ADDR_1_MASK (0x0000FFFFu) + #define EXT_ADDR_1_EXT_ADDR_1_BIT (0) + #define EXT_ADDR_1_EXT_ADDR_1_BITS (16) + +#define EXT_ADDR_2 *((volatile uint32_t *)0x400020A0u) +#define EXT_ADDR_2_REG *((volatile uint32_t *)0x400020A0u) +#define EXT_ADDR_2_ADDR (0x400020A0u) +#define EXT_ADDR_2_RESET (0x00000000u) + /* EXT_ADDR_2 field */ + #define EXT_ADDR_2_EXT_ADDR_2 (0x0000FFFFu) + #define EXT_ADDR_2_EXT_ADDR_2_MASK (0x0000FFFFu) + #define EXT_ADDR_2_EXT_ADDR_2_BIT (0) + #define EXT_ADDR_2_EXT_ADDR_2_BITS (16) + +#define EXT_ADDR_3 *((volatile uint32_t *)0x400020A4u) +#define EXT_ADDR_3_REG *((volatile uint32_t *)0x400020A4u) +#define EXT_ADDR_3_ADDR (0x400020A4u) +#define EXT_ADDR_3_RESET (0x00000000u) + /* EXT_ADDR_3 field */ + #define EXT_ADDR_3_EXT_ADDR_3 (0x0000FFFFu) + #define EXT_ADDR_3_EXT_ADDR_3_MASK (0x0000FFFFu) + #define EXT_ADDR_3_EXT_ADDR_3_BIT (0) + #define EXT_ADDR_3_EXT_ADDR_3_BITS (16) + +#define MAC_STATE *((volatile uint32_t *)0x400020A8u) +#define MAC_STATE_REG *((volatile uint32_t *)0x400020A8u) +#define MAC_STATE_ADDR (0x400020A8u) +#define MAC_STATE_RESET (0x00000000u) + /* SPY_STATE field */ + #define MAC_STATE_SPY_STATE (0x00000700u) + #define MAC_STATE_SPY_STATE_MASK (0x00000700u) + #define MAC_STATE_SPY_STATE_BIT (8) + #define MAC_STATE_SPY_STATE_BITS (3) + /* ACK_STATE field */ + #define MAC_STATE_ACK_STATE (0x000000C0u) + #define MAC_STATE_ACK_STATE_MASK (0x000000C0u) + #define MAC_STATE_ACK_STATE_BIT (6) + #define MAC_STATE_ACK_STATE_BITS (2) + /* BO_STATE field */ + #define MAC_STATE_BO_STATE (0x0000003Cu) + #define MAC_STATE_BO_STATE_MASK (0x0000003Cu) + #define MAC_STATE_BO_STATE_BIT (2) + #define MAC_STATE_BO_STATE_BITS (4) + /* TOP_STATE field */ + #define MAC_STATE_TOP_STATE (0x00000003u) + #define MAC_STATE_TOP_STATE_MASK (0x00000003u) + #define MAC_STATE_TOP_STATE_BIT (0) + #define MAC_STATE_TOP_STATE_BITS (2) + +#define RX_STATE *((volatile uint32_t *)0x400020ACu) +#define RX_STATE_REG *((volatile uint32_t *)0x400020ACu) +#define RX_STATE_ADDR (0x400020ACu) +#define RX_STATE_RESET (0x00000000u) + /* RX_BUFFER_STATE field */ + #define RX_STATE_RX_BUFFER_STATE (0x000001E0u) + #define RX_STATE_RX_BUFFER_STATE_MASK (0x000001E0u) + #define RX_STATE_RX_BUFFER_STATE_BIT (5) + #define RX_STATE_RX_BUFFER_STATE_BITS (4) + /* RX_TOP_STATE field */ + #define RX_STATE_RX_TOP_STATE (0x0000001Fu) + #define RX_STATE_RX_TOP_STATE_MASK (0x0000001Fu) + #define RX_STATE_RX_TOP_STATE_BIT (0) + #define RX_STATE_RX_TOP_STATE_BITS (5) + +#define TX_STATE *((volatile uint32_t *)0x400020B0u) +#define TX_STATE_REG *((volatile uint32_t *)0x400020B0u) +#define TX_STATE_ADDR (0x400020B0u) +#define TX_STATE_RESET (0x00000000u) + /* TX_BUFFER_STATE field */ + #define TX_STATE_TX_BUFFER_STATE (0x000000F0u) + #define TX_STATE_TX_BUFFER_STATE_MASK (0x000000F0u) + #define TX_STATE_TX_BUFFER_STATE_BIT (4) + #define TX_STATE_TX_BUFFER_STATE_BITS (4) + /* TX_TOP_STATE field */ + #define TX_STATE_TX_TOP_STATE (0x0000000Fu) + #define TX_STATE_TX_TOP_STATE_MASK (0x0000000Fu) + #define TX_STATE_TX_TOP_STATE_BIT (0) + #define TX_STATE_TX_TOP_STATE_BITS (4) + +#define DMA_STATE *((volatile uint32_t *)0x400020B4u) +#define DMA_STATE_REG *((volatile uint32_t *)0x400020B4u) +#define DMA_STATE_ADDR (0x400020B4u) +#define DMA_STATE_RESET (0x00000000u) + /* DMA_RX_STATE field */ + #define DMA_STATE_DMA_RX_STATE (0x00000038u) + #define DMA_STATE_DMA_RX_STATE_MASK (0x00000038u) + #define DMA_STATE_DMA_RX_STATE_BIT (3) + #define DMA_STATE_DMA_RX_STATE_BITS (3) + /* DMA_TX_STATE field */ + #define DMA_STATE_DMA_TX_STATE (0x00000007u) + #define DMA_STATE_DMA_TX_STATE_MASK (0x00000007u) + #define DMA_STATE_DMA_TX_STATE_BIT (0) + #define DMA_STATE_DMA_TX_STATE_BITS (3) + +#define MAC_DEBUG *((volatile uint32_t *)0x400020B8u) +#define MAC_DEBUG_REG *((volatile uint32_t *)0x400020B8u) +#define MAC_DEBUG_ADDR (0x400020B8u) +#define MAC_DEBUG_RESET (0x00000000u) + /* SW_DEBUG_OUT field */ + #define MAC_DEBUG_SW_DEBUG_OUT (0x00000060u) + #define MAC_DEBUG_SW_DEBUG_OUT_MASK (0x00000060u) + #define MAC_DEBUG_SW_DEBUG_OUT_BIT (5) + #define MAC_DEBUG_SW_DEBUG_OUT_BITS (2) + /* MAC_DEBUG_MUX field */ + #define MAC_DEBUG_MAC_DEBUG_MUX (0x0000001Fu) + #define MAC_DEBUG_MAC_DEBUG_MUX_MASK (0x0000001Fu) + #define MAC_DEBUG_MAC_DEBUG_MUX_BIT (0) + #define MAC_DEBUG_MAC_DEBUG_MUX_BITS (5) + +#define MAC_DEBUG_VIEW *((volatile uint32_t *)0x400020BCu) +#define MAC_DEBUG_VIEW_REG *((volatile uint32_t *)0x400020BCu) +#define MAC_DEBUG_VIEW_ADDR (0x400020BCu) +#define MAC_DEBUG_VIEW_RESET (0x00000010u) + /* MAC_DEBUG_VIEW field */ + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW (0x0000FFFFu) + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_MASK (0x0000FFFFu) + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT (0) + #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS (16) + +#define MAC_RSSI_DELAY *((volatile uint32_t *)0x400020C0u) +#define MAC_RSSI_DELAY_REG *((volatile uint32_t *)0x400020C0u) +#define MAC_RSSI_DELAY_ADDR (0x400020C0u) +#define MAC_RSSI_DELAY_RESET (0x00000000u) + /* RSSI_INST_DELAY_OK field */ + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK (0x00000FC0u) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_MASK (0x00000FC0u) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BIT (6) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BITS (6) + /* RSSI_INST_DELAY field */ + #define MAC_RSSI_DELAY_RSSI_INST_DELAY (0x0000003Fu) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_MASK (0x0000003Fu) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT (0) + #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS (6) + +#define PANID_COUNT *((volatile uint32_t *)0x400020C4u) +#define PANID_COUNT_REG *((volatile uint32_t *)0x400020C4u) +#define PANID_COUNT_ADDR (0x400020C4u) +#define PANID_COUNT_RESET (0x00000000u) + /* PANID_COUNT field */ + #define PANID_COUNT_PANID_COUNT (0x0000FFFFu) + #define PANID_COUNT_PANID_COUNT_MASK (0x0000FFFFu) + #define PANID_COUNT_PANID_COUNT_BIT (0) + #define PANID_COUNT_PANID_COUNT_BITS (16) + +#define NONPAN_COUNT *((volatile uint32_t *)0x400020C8u) +#define NONPAN_COUNT_REG *((volatile uint32_t *)0x400020C8u) +#define NONPAN_COUNT_ADDR (0x400020C8u) +#define NONPAN_COUNT_RESET (0x00000000u) + /* NONPAN_COUNT field */ + #define NONPAN_COUNT_NONPAN_COUNT (0x0000FFFFu) + #define NONPAN_COUNT_NONPAN_COUNT_MASK (0x0000FFFFu) + #define NONPAN_COUNT_NONPAN_COUNT_BIT (0) + #define NONPAN_COUNT_NONPAN_COUNT_BITS (16) + +/* SECURITY block */ +#define DATA_SECURITY_BASE (0x40003000u) +#define DATA_SECURITY_END (0x40003044u) +#define DATA_SECURITY_SIZE (DATA_SECURITY_END - DATA_SECURITY_BASE + 1) + +#define SECURITY_CONFIG *((volatile uint32_t *)0x40003000u) +#define SECURITY_CONFIG_REG *((volatile uint32_t *)0x40003000u) +#define SECURITY_CONFIG_ADDR (0x40003000u) +#define SECURITY_CONFIG_RESET (0x00000000u) + /* SEC_RST field */ + #define SECURITY_CONFIG_SEC_RST (0x00000080u) + #define SECURITY_CONFIG_SEC_RST_MASK (0x00000080u) + #define SECURITY_CONFIG_SEC_RST_BIT (7) + #define SECURITY_CONFIG_SEC_RST_BITS (1) + /* CTR_IN field */ + #define SECURITY_CONFIG_CTR_IN (0x00000040u) + #define SECURITY_CONFIG_CTR_IN_MASK (0x00000040u) + #define SECURITY_CONFIG_CTR_IN_BIT (6) + #define SECURITY_CONFIG_CTR_IN_BITS (1) + /* MIC_XOR_CT field */ + #define SECURITY_CONFIG_MIC_XOR_CT (0x00000020u) + #define SECURITY_CONFIG_MIC_XOR_CT_MASK (0x00000020u) + #define SECURITY_CONFIG_MIC_XOR_CT_BIT (5) + #define SECURITY_CONFIG_MIC_XOR_CT_BITS (1) + /* CBC_XOR_PT field */ + #define SECURITY_CONFIG_CBC_XOR_PT (0x00000010u) + #define SECURITY_CONFIG_CBC_XOR_PT_MASK (0x00000010u) + #define SECURITY_CONFIG_CBC_XOR_PT_BIT (4) + #define SECURITY_CONFIG_CBC_XOR_PT_BITS (1) + /* CT_TO_CBC_ST field */ + #define SECURITY_CONFIG_CT_TO_CBC_ST (0x00000008u) + #define SECURITY_CONFIG_CT_TO_CBC_ST_MASK (0x00000008u) + #define SECURITY_CONFIG_CT_TO_CBC_ST_BIT (3) + #define SECURITY_CONFIG_CT_TO_CBC_ST_BITS (1) + /* WAIT_CT_READ field */ + #define SECURITY_CONFIG_WAIT_CT_READ (0x00000004u) + #define SECURITY_CONFIG_WAIT_CT_READ_MASK (0x00000004u) + #define SECURITY_CONFIG_WAIT_CT_READ_BIT (2) + #define SECURITY_CONFIG_WAIT_CT_READ_BITS (1) + /* WAIT_PT_WRITE field */ + #define SECURITY_CONFIG_WAIT_PT_WRITE (0x00000002u) + #define SECURITY_CONFIG_WAIT_PT_WRITE_MASK (0x00000002u) + #define SECURITY_CONFIG_WAIT_PT_WRITE_BIT (1) + #define SECURITY_CONFIG_WAIT_PT_WRITE_BITS (1) + /* START_AES field */ + #define SECURITY_CONFIG_START_AES (0x00000001u) + #define SECURITY_CONFIG_START_AES_MASK (0x00000001u) + #define SECURITY_CONFIG_START_AES_BIT (0) + #define SECURITY_CONFIG_START_AES_BITS (1) + +#define SECURITY_STATUS *((volatile uint32_t *)0x40003004u) +#define SECURITY_STATUS_REG *((volatile uint32_t *)0x40003004u) +#define SECURITY_STATUS_ADDR (0x40003004u) +#define SECURITY_STATUS_RESET (0x00000000u) + /* SEC_BUSY field */ + #define SECURITY_STATUS_SEC_BUSY (0x00000001u) + #define SECURITY_STATUS_SEC_BUSY_MASK (0x00000001u) + #define SECURITY_STATUS_SEC_BUSY_BIT (0) + #define SECURITY_STATUS_SEC_BUSY_BITS (1) + +#define CBC_STATE_0 *((volatile uint32_t *)0x40003008u) +#define CBC_STATE_0_REG *((volatile uint32_t *)0x40003008u) +#define CBC_STATE_0_ADDR (0x40003008u) +#define CBC_STATE_0_RESET (0x00000000u) + /* CBC_STATE field */ + #define CBC_STATE_0_CBC_STATE (0xFFFFFFFFu) + #define CBC_STATE_0_CBC_STATE_MASK (0xFFFFFFFFu) + #define CBC_STATE_0_CBC_STATE_BIT (0) + #define CBC_STATE_0_CBC_STATE_BITS (32) + +#define CBC_STATE_1 *((volatile uint32_t *)0x4000300Cu) +#define CBC_STATE_1_REG *((volatile uint32_t *)0x4000300Cu) +#define CBC_STATE_1_ADDR (0x4000300Cu) +#define CBC_STATE_1_RESET (0x00000000u) + /* CBC_STATE_1 field */ + #define CBC_STATE_1_CBC_STATE_1 (0xFFFFFFFFu) + #define CBC_STATE_1_CBC_STATE_1_MASK (0xFFFFFFFFu) + #define CBC_STATE_1_CBC_STATE_1_BIT (0) + #define CBC_STATE_1_CBC_STATE_1_BITS (32) + +#define CBC_STATE_2 *((volatile uint32_t *)0x40003010u) +#define CBC_STATE_2_REG *((volatile uint32_t *)0x40003010u) +#define CBC_STATE_2_ADDR (0x40003010u) +#define CBC_STATE_2_RESET (0x00000000u) + /* CBC_STATE_2 field */ + #define CBC_STATE_2_CBC_STATE_2 (0xFFFFFFFFu) + #define CBC_STATE_2_CBC_STATE_2_MASK (0xFFFFFFFFu) + #define CBC_STATE_2_CBC_STATE_2_BIT (0) + #define CBC_STATE_2_CBC_STATE_2_BITS (32) + +#define CBC_STATE_3 *((volatile uint32_t *)0x40003014u) +#define CBC_STATE_3_REG *((volatile uint32_t *)0x40003014u) +#define CBC_STATE_3_ADDR (0x40003014u) +#define CBC_STATE_3_RESET (0x00000000u) + /* CBC_STATE_3 field */ + #define CBC_STATE_3_CBC_STATE_3 (0xFFFFFFFFu) + #define CBC_STATE_3_CBC_STATE_3_MASK (0xFFFFFFFFu) + #define CBC_STATE_3_CBC_STATE_3_BIT (0) + #define CBC_STATE_3_CBC_STATE_3_BITS (32) + +#define PT *((volatile uint32_t *)0x40003028u) +#define PT_REG *((volatile uint32_t *)0x40003028u) +#define PT_ADDR (0x40003028u) +#define PT_RESET (0x00000000u) + /* PT field */ + #define PT_PT (0xFFFFFFFFu) + #define PT_PT_MASK (0xFFFFFFFFu) + #define PT_PT_BIT (0) + #define PT_PT_BITS (32) + +#define CT *((volatile uint32_t *)0x40003030u) +#define CT_REG *((volatile uint32_t *)0x40003030u) +#define CT_ADDR (0x40003030u) +#define CT_RESET (0x00000000u) + /* CT field */ + #define CT_CT (0xFFFFFFFFu) + #define CT_CT_MASK (0xFFFFFFFFu) + #define CT_CT_BIT (0) + #define CT_CT_BITS (32) + +#define KEY_0 *((volatile uint32_t *)0x40003038u) +#define KEY_0_REG *((volatile uint32_t *)0x40003038u) +#define KEY_0_ADDR (0x40003038u) +#define KEY_0_RESET (0x00000000u) + /* KEY_O field */ + #define KEY_0_KEY_O (0xFFFFFFFFu) + #define KEY_0_KEY_O_MASK (0xFFFFFFFFu) + #define KEY_0_KEY_O_BIT (0) + #define KEY_0_KEY_O_BITS (32) + +#define KEY_1 *((volatile uint32_t *)0x4000303Cu) +#define KEY_1_REG *((volatile uint32_t *)0x4000303Cu) +#define KEY_1_ADDR (0x4000303Cu) +#define KEY_1_RESET (0x00000000u) + /* KEY_1 field */ + #define KEY_1_KEY_1 (0xFFFFFFFFu) + #define KEY_1_KEY_1_MASK (0xFFFFFFFFu) + #define KEY_1_KEY_1_BIT (0) + #define KEY_1_KEY_1_BITS (32) + +#define KEY_2 *((volatile uint32_t *)0x40003040u) +#define KEY_2_REG *((volatile uint32_t *)0x40003040u) +#define KEY_2_ADDR (0x40003040u) +#define KEY_2_RESET (0x00000000u) + /* KEY_2 field */ + #define KEY_2_KEY_2 (0xFFFFFFFFu) + #define KEY_2_KEY_2_MASK (0xFFFFFFFFu) + #define KEY_2_KEY_2_BIT (0) + #define KEY_2_KEY_2_BITS (32) + +#define KEY_3 *((volatile uint32_t *)0x40003044u) +#define KEY_3_REG *((volatile uint32_t *)0x40003044u) +#define KEY_3_ADDR (0x40003044u) +#define KEY_3_RESET (0x00000000u) + /* KEY_3 field */ + #define KEY_3_KEY_3 (0xFFFFFFFFu) + #define KEY_3_KEY_3_MASK (0xFFFFFFFFu) + #define KEY_3_KEY_3_BIT (0) + #define KEY_3_KEY_3_BITS (32) + +/* CM_LV block */ +#define BLOCK_CM_LV_BASE (0x40004000u) +#define BLOCK_CM_LV_END (0x40004034u) +#define BLOCK_CM_LV_SIZE (BLOCK_CM_LV_END - BLOCK_CM_LV_BASE + 1) + +#define SILICON_ID *((volatile uint32_t *)0x40004000u) +#define SILICON_ID_REG *((volatile uint32_t *)0x40004000u) +#define SILICON_ID_ADDR (0x40004000u) +#define SILICON_ID_RESET (0x069A862Bu) + /* HW_VERSION field */ + #define SILICON_ID_HW_VERSION (0xF0000000u) + #define SILICON_ID_HW_VERSION_MASK (0xF0000000u) + #define SILICON_ID_HW_VERSION_BIT (28) + #define SILICON_ID_HW_VERSION_BITS (4) + /* ST_DIVISION field */ + #define SILICON_ID_ST_DIVISION (0x0F000000u) + #define SILICON_ID_ST_DIVISION_MASK (0x0F000000u) + #define SILICON_ID_ST_DIVISION_BIT (24) + #define SILICON_ID_ST_DIVISION_BITS (4) + /* CHIP_TYPE field */ + #define SILICON_ID_CHIP_TYPE (0x00FF8000u) + #define SILICON_ID_CHIP_TYPE_MASK (0x00FF8000u) + #define SILICON_ID_CHIP_TYPE_BIT (15) + #define SILICON_ID_CHIP_TYPE_BITS (9) + /* SUB_TYPE field */ + #define SILICON_ID_SUB_TYPE (0x00007000u) + #define SILICON_ID_SUB_TYPE_MASK (0x00007000u) + #define SILICON_ID_SUB_TYPE_BIT (12) + #define SILICON_ID_SUB_TYPE_BITS (3) + /* JEDEC_MAN_ID field */ + #define SILICON_ID_JEDEC_MAN_ID (0x00000FFEu) + #define SILICON_ID_JEDEC_MAN_ID_MASK (0x00000FFEu) + #define SILICON_ID_JEDEC_MAN_ID_BIT (1) + #define SILICON_ID_JEDEC_MAN_ID_BITS (11) + /* ONE field */ + #define SILICON_ID_ONE (0x00000001u) + #define SILICON_ID_ONE_MASK (0x00000001u) + #define SILICON_ID_ONE_BIT (0) + #define SILICON_ID_ONE_BITS (1) + +#define OSC24M_BIASTRIM *((volatile uint32_t *)0x40004004u) +#define OSC24M_BIASTRIM_REG *((volatile uint32_t *)0x40004004u) +#define OSC24M_BIASTRIM_ADDR (0x40004004u) +#define OSC24M_BIASTRIM_RESET (0x0000000Fu) + /* OSC24M_BIAS_TRIM field */ + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM (0x0000000Fu) + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK (0x0000000Fu) + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT (0) + #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS (4) + +#define OSCHF_TUNE *((volatile uint32_t *)0x40004008u) +#define OSCHF_TUNE_REG *((volatile uint32_t *)0x40004008u) +#define OSCHF_TUNE_ADDR (0x40004008u) +#define OSCHF_TUNE_RESET (0x00000017u) + /* OSCHF_TUNE_FIELD field */ + #define OSCHF_TUNE_FIELD (0x0000001Fu) + #define OSCHF_TUNE_FIELD_MASK (0x0000001Fu) + #define OSCHF_TUNE_FIELD_BIT (0) + #define OSCHF_TUNE_FIELD_BITS (5) + +#define OSC24M_COMP *((volatile uint32_t *)0x4000400Cu) +#define OSC24M_COMP_REG *((volatile uint32_t *)0x4000400Cu) +#define OSC24M_COMP_ADDR (0x4000400Cu) +#define OSC24M_COMP_RESET (0x00000000u) + /* OSC24M_HI field */ + #define OSC24M_HI (0x00000002u) + #define OSC24M_HI_MASK (0x00000002u) + #define OSC24M_HI_BIT (1) + #define OSC24M_HI_BITS (1) + /* OSC24M_LO field */ + #define OSC24M_LO (0x00000001u) + #define OSC24M_LO_MASK (0x00000001u) + #define OSC24M_LO_BIT (0) + #define OSC24M_LO_BITS (1) + +#define CLK_PERIODMODE *((volatile uint32_t *)0x40004010u) +#define CLK_PERIODMODE_REG *((volatile uint32_t *)0x40004010u) +#define CLK_PERIODMODE_ADDR (0x40004010u) +#define CLK_PERIODMODE_RESET (0x00000000u) + /* CLK_PERIODMODE_FIELD field */ + #define CLK_PERIODMODE_FIELD (0x00000003u) + #define CLK_PERIODMODE_FIELD_MASK (0x00000003u) + #define CLK_PERIODMODE_FIELD_BIT (0) + #define CLK_PERIODMODE_FIELD_BITS (2) + +#define CLK_PERIOD *((volatile uint32_t *)0x40004014u) +#define CLK_PERIOD_REG *((volatile uint32_t *)0x40004014u) +#define CLK_PERIOD_ADDR (0x40004014u) +#define CLK_PERIOD_RESET (0x00000000u) + /* CLK_PERIOD_FIELD field */ + #define CLK_PERIOD_FIELD (0x0000FFFFu) + #define CLK_PERIOD_FIELD_MASK (0x0000FFFFu) + #define CLK_PERIOD_FIELD_BIT (0) + #define CLK_PERIOD_FIELD_BITS (16) + +#define DITHER_DIS *((volatile uint32_t *)0x40004018u) +#define DITHER_DIS_REG *((volatile uint32_t *)0x40004018u) +#define DITHER_DIS_ADDR (0x40004018u) +#define DITHER_DIS_RESET (0x00000000u) + /* DITHER_DIS field */ + #define DITHER_DIS_DITHER_DIS (0x00000001u) + #define DITHER_DIS_DITHER_DIS_MASK (0x00000001u) + #define DITHER_DIS_DITHER_DIS_BIT (0) + #define DITHER_DIS_DITHER_DIS_BITS (1) + +#define OSC24M_CTRL *((volatile uint32_t *)0x4000401Cu) +#define OSC24M_CTRL_REG *((volatile uint32_t *)0x4000401Cu) +#define OSC24M_CTRL_ADDR (0x4000401Cu) +#define OSC24M_CTRL_RESET (0x00000000u) + /* OSC24M_EN field */ + #define OSC24M_CTRL_OSC24M_EN (0x00000002u) + #define OSC24M_CTRL_OSC24M_EN_MASK (0x00000002u) + #define OSC24M_CTRL_OSC24M_EN_BIT (1) + #define OSC24M_CTRL_OSC24M_EN_BITS (1) + /* OSC24M_SEL field */ + #define OSC24M_CTRL_OSC24M_SEL (0x00000001u) + #define OSC24M_CTRL_OSC24M_SEL_MASK (0x00000001u) + #define OSC24M_CTRL_OSC24M_SEL_BIT (0) + #define OSC24M_CTRL_OSC24M_SEL_BITS (1) + +#define CPU_CLKSEL *((volatile uint32_t *)0x40004020u) +#define CPU_CLKSEL_REG *((volatile uint32_t *)0x40004020u) +#define CPU_CLKSEL_ADDR (0x40004020u) +#define CPU_CLKSEL_RESET (0x00000000u) + /* CPU_CLKSEL_FIELD field */ + #define CPU_CLKSEL_FIELD (0x00000001u) + #define CPU_CLKSEL_FIELD_MASK (0x00000001u) + #define CPU_CLKSEL_FIELD_BIT (0) + #define CPU_CLKSEL_FIELD_BITS (1) + +#define BUS_FAULT *((volatile uint32_t *)0x40004024u) +#define BUS_FAULT_REG *((volatile uint32_t *)0x40004024u) +#define BUS_FAULT_ADDR (0x40004024u) +#define BUS_FAULT_RESET (0x00000000u) + /* WRONGSIZE field */ + #define BUS_FAULT_WRONGSIZE (0x00000008u) + #define BUS_FAULT_WRONGSIZE_MASK (0x00000008u) + #define BUS_FAULT_WRONGSIZE_BIT (3) + #define BUS_FAULT_WRONGSIZE_BITS (1) + /* PROTECTED field */ + #define BUS_FAULT_PROTECTED (0x00000004u) + #define BUS_FAULT_PROTECTED_MASK (0x00000004u) + #define BUS_FAULT_PROTECTED_BIT (2) + #define BUS_FAULT_PROTECTED_BITS (1) + /* RESERVED field */ + #define BUS_FAULT_RESERVED (0x00000002u) + #define BUS_FAULT_RESERVED_MASK (0x00000002u) + #define BUS_FAULT_RESERVED_BIT (1) + #define BUS_FAULT_RESERVED_BITS (1) + /* MISSED field */ + #define BUS_FAULT_MISSED (0x00000001u) + #define BUS_FAULT_MISSED_MASK (0x00000001u) + #define BUS_FAULT_MISSED_BIT (0) + #define BUS_FAULT_MISSED_BITS (1) + +#define PCTRACE_SEL *((volatile uint32_t *)0x40004028u) +#define PCTRACE_SEL_REG *((volatile uint32_t *)0x40004028u) +#define PCTRACE_SEL_ADDR (0x40004028u) +#define PCTRACE_SEL_RESET (0x00000000u) + /* PCTRACE_SEL_FIELD field */ + #define PCTRACE_SEL_FIELD (0x00000001u) + #define PCTRACE_SEL_FIELD_MASK (0x00000001u) + #define PCTRACE_SEL_FIELD_BIT (0) + #define PCTRACE_SEL_FIELD_BITS (1) + +#define FPEC_CLKREQ *((volatile uint32_t *)0x4000402Cu) +#define FPEC_CLKREQ_REG *((volatile uint32_t *)0x4000402Cu) +#define FPEC_CLKREQ_ADDR (0x4000402Cu) +#define FPEC_CLKREQ_RESET (0x00000000u) + /* FPEC_CLKREQ_FIELD field */ + #define FPEC_CLKREQ_FIELD (0x00000001u) + #define FPEC_CLKREQ_FIELD_MASK (0x00000001u) + #define FPEC_CLKREQ_FIELD_BIT (0) + #define FPEC_CLKREQ_FIELD_BITS (1) + +#define FPEC_CLKSTAT *((volatile uint32_t *)0x40004030u) +#define FPEC_CLKSTAT_REG *((volatile uint32_t *)0x40004030u) +#define FPEC_CLKSTAT_ADDR (0x40004030u) +#define FPEC_CLKSTAT_RESET (0x00000000u) + /* FPEC_CLKBSY field */ + #define FPEC_CLKBSY (0x00000002u) + #define FPEC_CLKBSY_MASK (0x00000002u) + #define FPEC_CLKBSY_BIT (1) + #define FPEC_CLKBSY_BITS (1) + /* FPEC_CLKACK field */ + #define FPEC_CLKACK (0x00000001u) + #define FPEC_CLKACK_MASK (0x00000001u) + #define FPEC_CLKACK_BIT (0) + #define FPEC_CLKACK_BITS (1) + +#define LV_SPARE *((volatile uint32_t *)0x40004034u) +#define LV_SPARE_REG *((volatile uint32_t *)0x40004034u) +#define LV_SPARE_ADDR (0x40004034u) +#define LV_SPARE_RESET (0x00000000u) + /* LV_SPARE field */ + #define LV_SPARE_LV_SPARE (0x000000FFu) + #define LV_SPARE_LV_SPARE_MASK (0x000000FFu) + #define LV_SPARE_LV_SPARE_BIT (0) + #define LV_SPARE_LV_SPARE_BITS (8) + +/* RAM_CTRL block */ +#define DATA_RAM_CTRL_BASE (0x40005000u) +#define DATA_RAM_CTRL_END (0x40005028u) +#define DATA_RAM_CTRL_SIZE (DATA_RAM_CTRL_END - DATA_RAM_CTRL_BASE + 1) + +#define MEM_PROT_0 *((volatile uint32_t *)0x40005000u) +#define MEM_PROT_0_REG *((volatile uint32_t *)0x40005000u) +#define MEM_PROT_0_ADDR (0x40005000u) +#define MEM_PROT_0_RESET (0x00000000u) + /* MEM_PROT_0 field */ + #define MEM_PROT_0_MEM_PROT_0 (0xFFFFFFFFu) + #define MEM_PROT_0_MEM_PROT_0_MASK (0xFFFFFFFFu) + #define MEM_PROT_0_MEM_PROT_0_BIT (0) + #define MEM_PROT_0_MEM_PROT_0_BITS (32) + +#define MEM_PROT_1 *((volatile uint32_t *)0x40005004u) +#define MEM_PROT_1_REG *((volatile uint32_t *)0x40005004u) +#define MEM_PROT_1_ADDR (0x40005004u) +#define MEM_PROT_1_RESET (0x00000000u) + /* MEM_PROT_1 field */ + #define MEM_PROT_1_MEM_PROT_1 (0xFFFFFFFFu) + #define MEM_PROT_1_MEM_PROT_1_MASK (0xFFFFFFFFu) + #define MEM_PROT_1_MEM_PROT_1_BIT (0) + #define MEM_PROT_1_MEM_PROT_1_BITS (32) + +#define MEM_PROT_2 *((volatile uint32_t *)0x40005008u) +#define MEM_PROT_2_REG *((volatile uint32_t *)0x40005008u) +#define MEM_PROT_2_ADDR (0x40005008u) +#define MEM_PROT_2_RESET (0x00000000u) + /* MEM_PROT_2 field */ + #define MEM_PROT_2_MEM_PROT_2 (0xFFFFFFFFu) + #define MEM_PROT_2_MEM_PROT_2_MASK (0xFFFFFFFFu) + #define MEM_PROT_2_MEM_PROT_2_BIT (0) + #define MEM_PROT_2_MEM_PROT_2_BITS (32) + +#define MEM_PROT_3 *((volatile uint32_t *)0x4000500Cu) +#define MEM_PROT_3_REG *((volatile uint32_t *)0x4000500Cu) +#define MEM_PROT_3_ADDR (0x4000500Cu) +#define MEM_PROT_3_RESET (0x00000000u) + /* MEM_PROT_3 field */ + #define MEM_PROT_3_MEM_PROT_3 (0xFFFFFFFFu) + #define MEM_PROT_3_MEM_PROT_3_MASK (0xFFFFFFFFu) + #define MEM_PROT_3_MEM_PROT_3_BIT (0) + #define MEM_PROT_3_MEM_PROT_3_BITS (32) + +#define MEM_PROT_4 *((volatile uint32_t *)0x40005010u) +#define MEM_PROT_4_REG *((volatile uint32_t *)0x40005010u) +#define MEM_PROT_4_ADDR (0x40005010u) +#define MEM_PROT_4_RESET (0x00000000u) + /* MEM_PROT_4 field */ + #define MEM_PROT_4_MEM_PROT_4 (0xFFFFFFFFu) + #define MEM_PROT_4_MEM_PROT_4_MASK (0xFFFFFFFFu) + #define MEM_PROT_4_MEM_PROT_4_BIT (0) + #define MEM_PROT_4_MEM_PROT_4_BITS (32) + +#define MEM_PROT_5 *((volatile uint32_t *)0x40005014u) +#define MEM_PROT_5_REG *((volatile uint32_t *)0x40005014u) +#define MEM_PROT_5_ADDR (0x40005014u) +#define MEM_PROT_5_RESET (0x00000000u) + /* MEM_PROT_5 field */ + #define MEM_PROT_5_MEM_PROT_5 (0xFFFFFFFFu) + #define MEM_PROT_5_MEM_PROT_5_MASK (0xFFFFFFFFu) + #define MEM_PROT_5_MEM_PROT_5_BIT (0) + #define MEM_PROT_5_MEM_PROT_5_BITS (32) + +#define MEM_PROT_6 *((volatile uint32_t *)0x40005018u) +#define MEM_PROT_6_REG *((volatile uint32_t *)0x40005018u) +#define MEM_PROT_6_ADDR (0x40005018u) +#define MEM_PROT_6_RESET (0x00000000u) + /* MEM_PROT_6 field */ + #define MEM_PROT_6_MEM_PROT_6 (0xFFFFFFFFu) + #define MEM_PROT_6_MEM_PROT_6_MASK (0xFFFFFFFFu) + #define MEM_PROT_6_MEM_PROT_6_BIT (0) + #define MEM_PROT_6_MEM_PROT_6_BITS (32) + +#define MEM_PROT_7 *((volatile uint32_t *)0x4000501Cu) +#define MEM_PROT_7_REG *((volatile uint32_t *)0x4000501Cu) +#define MEM_PROT_7_ADDR (0x4000501Cu) +#define MEM_PROT_7_RESET (0x00000000u) + /* MEM_PROT_7 field */ + #define MEM_PROT_7_MEM_PROT_7 (0xFFFFFFFFu) + #define MEM_PROT_7_MEM_PROT_7_MASK (0xFFFFFFFFu) + #define MEM_PROT_7_MEM_PROT_7_BIT (0) + #define MEM_PROT_7_MEM_PROT_7_BITS (32) + +#define DMA_PROT_ADDR *((volatile uint32_t *)0x40005020u) +#define DMA_PROT_ADDR_REG *((volatile uint32_t *)0x40005020u) +#define DMA_PROT_ADDR_ADDR (0x40005020u) +#define DMA_PROT_ADDR_RESET (0x20000000u) + /* DMA_PROT_OFFS field */ + #define DMA_PROT_ADDR_DMA_PROT_OFFS (0xFFFFE000u) + #define DMA_PROT_ADDR_DMA_PROT_OFFS_MASK (0xFFFFE000u) + #define DMA_PROT_ADDR_DMA_PROT_OFFS_BIT (13) + #define DMA_PROT_ADDR_DMA_PROT_OFFS_BITS (19) + /* DMA_PROT_ADDR field */ + #define DMA_PROT_ADDR_DMA_PROT_ADDR (0x00001FFFu) + #define DMA_PROT_ADDR_DMA_PROT_ADDR_MASK (0x00001FFFu) + #define DMA_PROT_ADDR_DMA_PROT_ADDR_BIT (0) + #define DMA_PROT_ADDR_DMA_PROT_ADDR_BITS (13) + +#define DMA_PROT_CH *((volatile uint32_t *)0x40005024u) +#define DMA_PROT_CH_REG *((volatile uint32_t *)0x40005024u) +#define DMA_PROT_CH_ADDR (0x40005024u) +#define DMA_PROT_CH_RESET (0x00000000u) + /* DMA_PROT_CH field */ + #define DMA_PROT_CH_DMA_PROT_CH (0x00000007u) + #define DMA_PROT_CH_DMA_PROT_CH_MASK (0x00000007u) + #define DMA_PROT_CH_DMA_PROT_CH_BIT (0) + #define DMA_PROT_CH_DMA_PROT_CH_BITS (3) + +#define MEM_PROT_EN *((volatile uint32_t *)0x40005028u) +#define MEM_PROT_EN_REG *((volatile uint32_t *)0x40005028u) +#define MEM_PROT_EN_ADDR (0x40005028u) +#define MEM_PROT_EN_RESET (0x00000000u) + /* FORCE_PROT field */ + #define MEM_PROT_EN_FORCE_PROT (0x00000004u) + #define MEM_PROT_EN_FORCE_PROT_MASK (0x00000004u) + #define MEM_PROT_EN_FORCE_PROT_BIT (2) + #define MEM_PROT_EN_FORCE_PROT_BITS (1) + /* DMA_PROT_EN_MAC field */ + #define MEM_PROT_EN_DMA_PROT_EN_MAC (0x00000002u) + #define MEM_PROT_EN_DMA_PROT_EN_MAC_MASK (0x00000002u) + #define MEM_PROT_EN_DMA_PROT_EN_MAC_BIT (1) + #define MEM_PROT_EN_DMA_PROT_EN_MAC_BITS (1) + /* DMA_PROT_EN_OTHER field */ + #define MEM_PROT_EN_DMA_PROT_EN_OTHER (0x00000001u) + #define MEM_PROT_EN_DMA_PROT_EN_OTHER_MASK (0x00000001u) + #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BIT (0) + #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BITS (1) + +/* SLOW_TIMERS block */ +#define DATA_SLOW_TIMERS_BASE (0x40006000u) +#define DATA_SLOW_TIMERS_END (0x40006024u) +#define DATA_SLOW_TIMERS_SIZE (DATA_SLOW_TIMERS_END - DATA_SLOW_TIMERS_BASE + 1) + +#define WDOG_CFG *((volatile uint32_t *)0x40006000u) +#define WDOG_CFG_REG *((volatile uint32_t *)0x40006000u) +#define WDOG_CFG_ADDR (0x40006000u) +#define WDOG_CFG_RESET (0x00000002u) + /* WDOG_DISABLE field */ + #define WDOG_DISABLE (0x00000002u) + #define WDOG_DISABLE_MASK (0x00000002u) + #define WDOG_DISABLE_BIT (1) + #define WDOG_DISABLE_BITS (1) + /* WDOG_ENABLE field */ + #define WDOG_ENABLE (0x00000001u) + #define WDOG_ENABLE_MASK (0x00000001u) + #define WDOG_ENABLE_BIT (0) + #define WDOG_ENABLE_BITS (1) + +#define WDOG_KEY *((volatile uint32_t *)0x40006004u) +#define WDOG_KEY_REG *((volatile uint32_t *)0x40006004u) +#define WDOG_KEY_ADDR (0x40006004u) +#define WDOG_KEY_RESET (0x00000000u) + /* WDOG_KEY_FIELD field */ + #define WDOG_KEY_FIELD (0x0000FFFFu) + #define WDOG_KEY_FIELD_MASK (0x0000FFFFu) + #define WDOG_KEY_FIELD_BIT (0) + #define WDOG_KEY_FIELD_BITS (16) + +#define WDOG_RESET *((volatile uint32_t *)0x40006008u) +#define WDOG_RESET_REG *((volatile uint32_t *)0x40006008u) +#define WDOG_RESET_ADDR (0x40006008u) +#define WDOG_RESET_RESET (0x00000000u) + +#define SLEEPTMR_CFG *((volatile uint32_t *)0x4000600Cu) +#define SLEEPTMR_CFG_REG *((volatile uint32_t *)0x4000600Cu) +#define SLEEPTMR_CFG_ADDR (0x4000600Cu) +#define SLEEPTMR_CFG_RESET (0x00000400u) + /* SLEEPTMR_REVERSE field */ + #define SLEEPTMR_REVERSE (0x00001000u) + #define SLEEPTMR_REVERSE_MASK (0x00001000u) + #define SLEEPTMR_REVERSE_BIT (12) + #define SLEEPTMR_REVERSE_BITS (1) + /* SLEEPTMR_ENABLE field */ + #define SLEEPTMR_ENABLE (0x00000800u) + #define SLEEPTMR_ENABLE_MASK (0x00000800u) + #define SLEEPTMR_ENABLE_BIT (11) + #define SLEEPTMR_ENABLE_BITS (1) + /* SLEEPTMR_DBGPAUSE field */ + #define SLEEPTMR_DBGPAUSE (0x00000400u) + #define SLEEPTMR_DBGPAUSE_MASK (0x00000400u) + #define SLEEPTMR_DBGPAUSE_BIT (10) + #define SLEEPTMR_DBGPAUSE_BITS (1) + /* SLEEPTMR_CLKDIV field */ + #define SLEEPTMR_CLKDIV (0x000000F0u) + #define SLEEPTMR_CLKDIV_MASK (0x000000F0u) + #define SLEEPTMR_CLKDIV_BIT (4) + #define SLEEPTMR_CLKDIV_BITS (4) + /* SLEEPTMR_CLKSEL field */ + #define SLEEPTMR_CLKSEL (0x00000001u) + #define SLEEPTMR_CLKSEL_MASK (0x00000001u) + #define SLEEPTMR_CLKSEL_BIT (0) + #define SLEEPTMR_CLKSEL_BITS (1) + +#define SLEEPTMR_CNTH *((volatile uint32_t *)0x40006010u) +#define SLEEPTMR_CNTH_REG *((volatile uint32_t *)0x40006010u) +#define SLEEPTMR_CNTH_ADDR (0x40006010u) +#define SLEEPTMR_CNTH_RESET (0x00000000u) + /* SLEEPTMR_CNTH_FIELD field */ + #define SLEEPTMR_CNTH_FIELD (0x0000FFFFu) + #define SLEEPTMR_CNTH_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CNTH_FIELD_BIT (0) + #define SLEEPTMR_CNTH_FIELD_BITS (16) + +#define SLEEPTMR_CNTL *((volatile uint32_t *)0x40006014u) +#define SLEEPTMR_CNTL_REG *((volatile uint32_t *)0x40006014u) +#define SLEEPTMR_CNTL_ADDR (0x40006014u) +#define SLEEPTMR_CNTL_RESET (0x00000000u) + /* SLEEPTMR_CNTL_FIELD field */ + #define SLEEPTMR_CNTL_FIELD (0x0000FFFFu) + #define SLEEPTMR_CNTL_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CNTL_FIELD_BIT (0) + #define SLEEPTMR_CNTL_FIELD_BITS (16) + +#define SLEEPTMR_CMPAH *((volatile uint32_t *)0x40006018u) +#define SLEEPTMR_CMPAH_REG *((volatile uint32_t *)0x40006018u) +#define SLEEPTMR_CMPAH_ADDR (0x40006018u) +#define SLEEPTMR_CMPAH_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPAH_FIELD field */ + #define SLEEPTMR_CMPAH_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPAH_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPAH_FIELD_BIT (0) + #define SLEEPTMR_CMPAH_FIELD_BITS (16) + +#define SLEEPTMR_CMPAL *((volatile uint32_t *)0x4000601Cu) +#define SLEEPTMR_CMPAL_REG *((volatile uint32_t *)0x4000601Cu) +#define SLEEPTMR_CMPAL_ADDR (0x4000601Cu) +#define SLEEPTMR_CMPAL_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPAL_FIELD field */ + #define SLEEPTMR_CMPAL_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPAL_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPAL_FIELD_BIT (0) + #define SLEEPTMR_CMPAL_FIELD_BITS (16) + +#define SLEEPTMR_CMPBH *((volatile uint32_t *)0x40006020u) +#define SLEEPTMR_CMPBH_REG *((volatile uint32_t *)0x40006020u) +#define SLEEPTMR_CMPBH_ADDR (0x40006020u) +#define SLEEPTMR_CMPBH_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPBH_FIELD field */ + #define SLEEPTMR_CMPBH_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPBH_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPBH_FIELD_BIT (0) + #define SLEEPTMR_CMPBH_FIELD_BITS (16) + +#define SLEEPTMR_CMPBL *((volatile uint32_t *)0x40006024u) +#define SLEEPTMR_CMPBL_REG *((volatile uint32_t *)0x40006024u) +#define SLEEPTMR_CMPBL_ADDR (0x40006024u) +#define SLEEPTMR_CMPBL_RESET (0x0000FFFFu) + /* SLEEPTMR_CMPBL_FIELD field */ + #define SLEEPTMR_CMPBL_FIELD (0x0000FFFFu) + #define SLEEPTMR_CMPBL_FIELD_MASK (0x0000FFFFu) + #define SLEEPTMR_CMPBL_FIELD_BIT (0) + #define SLEEPTMR_CMPBL_FIELD_BITS (16) + +/* CAL_ADC block */ +#define DATA_CAL_ADC_BASE (0x40007000u) +#define DATA_CAL_ADC_END (0x40007004u) +#define DATA_CAL_ADC_SIZE (DATA_CAL_ADC_END - DATA_CAL_ADC_BASE + 1) + +#define CAL_ADC_DATA *((volatile uint32_t *)0x40007000u) +#define CAL_ADC_DATA_REG *((volatile uint32_t *)0x40007000u) +#define CAL_ADC_DATA_ADDR (0x40007000u) +#define CAL_ADC_DATA_RESET (0x00000000u) + /* CAL_ADC_DATA field */ + #define CAL_ADC_DATA_CAL_ADC_DATA (0x0000FFFFu) + #define CAL_ADC_DATA_CAL_ADC_DATA_MASK (0x0000FFFFu) + #define CAL_ADC_DATA_CAL_ADC_DATA_BIT (0) + #define CAL_ADC_DATA_CAL_ADC_DATA_BITS (16) + +#define CAL_ADC_CONFIG *((volatile uint32_t *)0x40007004u) +#define CAL_ADC_CONFIG_REG *((volatile uint32_t *)0x40007004u) +#define CAL_ADC_CONFIG_ADDR (0x40007004u) +#define CAL_ADC_CONFIG_RESET (0x00000000u) + /* CAL_ADC_RATE field */ + #define CAL_ADC_CONFIG_CAL_ADC_RATE (0x00007000u) + #define CAL_ADC_CONFIG_CAL_ADC_RATE_MASK (0x00007000u) + #define CAL_ADC_CONFIG_CAL_ADC_RATE_BIT (12) + #define CAL_ADC_CONFIG_CAL_ADC_RATE_BITS (3) + /* CAL_ADC_MUX field */ + #define CAL_ADC_CONFIG_CAL_ADC_MUX (0x00000F80u) + #define CAL_ADC_CONFIG_CAL_ADC_MUX_MASK (0x00000F80u) + #define CAL_ADC_CONFIG_CAL_ADC_MUX_BIT (7) + #define CAL_ADC_CONFIG_CAL_ADC_MUX_BITS (5) + /* CAL_ADC_CLKSEL field */ + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL (0x00000004u) + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_MASK (0x00000004u) + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT (2) + #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BITS (1) + /* CAL_ADC_DITHER_DIS field */ + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS (0x00000002u) + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_MASK (0x00000002u) + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BIT (1) + #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BITS (1) + /* CAL_ADC_EN field */ + #define CAL_ADC_CONFIG_CAL_ADC_EN (0x00000001u) + #define CAL_ADC_CONFIG_CAL_ADC_EN_MASK (0x00000001u) + #define CAL_ADC_CONFIG_CAL_ADC_EN_BIT (0) + #define CAL_ADC_CONFIG_CAL_ADC_EN_BITS (1) + +/* FLASH_CONTROL block */ +#define DATA_FLASH_CONTROL_BASE (0x40008000u) +#define DATA_FLASH_CONTROL_END (0x40008084u) +#define DATA_FLASH_CONTROL_SIZE (DATA_FLASH_CONTROL_END - DATA_FLASH_CONTROL_BASE + 1) + +#define FLASH_ACCESS *((volatile uint32_t *)0x40008000u) +#define FLASH_ACCESS_REG *((volatile uint32_t *)0x40008000u) +#define FLASH_ACCESS_ADDR (0x40008000u) +#define FLASH_ACCESS_RESET (0x00000031u) + /* PREFETCH_STATUS field */ + #define FLASH_ACCESS_PREFETCH_STATUS (0x00000020u) + #define FLASH_ACCESS_PREFETCH_STATUS_MASK (0x00000020u) + #define FLASH_ACCESS_PREFETCH_STATUS_BIT (5) + #define FLASH_ACCESS_PREFETCH_STATUS_BITS (1) + /* PREFETCH_EN field */ + #define FLASH_ACCESS_PREFETCH_EN (0x00000010u) + #define FLASH_ACCESS_PREFETCH_EN_MASK (0x00000010u) + #define FLASH_ACCESS_PREFETCH_EN_BIT (4) + #define FLASH_ACCESS_PREFETCH_EN_BITS (1) + /* HALFCYCLE_ACCESS field */ + #define FLASH_ACCESS_HALFCYCLE_ACCESS (0x00000008u) + #define FLASH_ACCESS_HALFCYCLE_ACCESS_MASK (0x00000008u) + #define FLASH_ACCESS_HALFCYCLE_ACCESS_BIT (3) + #define FLASH_ACCESS_HALFCYCLE_ACCESS_BITS (1) + /* CODE_LATENCY field */ + #define FLASH_ACCESS_CODE_LATENCY (0x00000007u) + #define FLASH_ACCESS_CODE_LATENCY_MASK (0x00000007u) + #define FLASH_ACCESS_CODE_LATENCY_BIT (0) + #define FLASH_ACCESS_CODE_LATENCY_BITS (3) + +#define FPEC_KEY *((volatile uint32_t *)0x40008004u) +#define FPEC_KEY_REG *((volatile uint32_t *)0x40008004u) +#define FPEC_KEY_ADDR (0x40008004u) +#define FPEC_KEY_RESET (0x00000000u) + /* FKEYR field */ + #define FPEC_KEY_FKEYR (0xFFFFFFFFu) + #define FPEC_KEY_FKEYR_MASK (0xFFFFFFFFu) + #define FPEC_KEY_FKEYR_BIT (0) + #define FPEC_KEY_FKEYR_BITS (32) + +#define OPT_KEY *((volatile uint32_t *)0x40008008u) +#define OPT_KEY_REG *((volatile uint32_t *)0x40008008u) +#define OPT_KEY_ADDR (0x40008008u) +#define OPT_KEY_RESET (0x00000000u) + /* OPTKEYR field */ + #define OPT_KEY_OPTKEYR (0xFFFFFFFFu) + #define OPT_KEY_OPTKEYR_MASK (0xFFFFFFFFu) + #define OPT_KEY_OPTKEYR_BIT (0) + #define OPT_KEY_OPTKEYR_BITS (32) + +#define FLASH_STATUS *((volatile uint32_t *)0x4000800Cu) +#define FLASH_STATUS_REG *((volatile uint32_t *)0x4000800Cu) +#define FLASH_STATUS_ADDR (0x4000800Cu) +#define FLASH_STATUS_RESET (0x00000000u) + /* EOP field */ + #define FLASH_STATUS_EOP (0x00000020u) + #define FLASH_STATUS_EOP_MASK (0x00000020u) + #define FLASH_STATUS_EOP_BIT (5) + #define FLASH_STATUS_EOP_BITS (1) + /* WRP_ERR field */ + #define FLASH_STATUS_WRP_ERR (0x00000010u) + #define FLASH_STATUS_WRP_ERR_MASK (0x00000010u) + #define FLASH_STATUS_WRP_ERR_BIT (4) + #define FLASH_STATUS_WRP_ERR_BITS (1) + /* PAGE_PROG_ERR field */ + #define FLASH_STATUS_PAGE_PROG_ERR (0x00000008u) + #define FLASH_STATUS_PAGE_PROG_ERR_MASK (0x00000008u) + #define FLASH_STATUS_PAGE_PROG_ERR_BIT (3) + #define FLASH_STATUS_PAGE_PROG_ERR_BITS (1) + /* PROG_ERR field */ + #define FLASH_STATUS_PROG_ERR (0x00000004u) + #define FLASH_STATUS_PROG_ERR_MASK (0x00000004u) + #define FLASH_STATUS_PROG_ERR_BIT (2) + #define FLASH_STATUS_PROG_ERR_BITS (1) + /* EARLY_BSY field */ + #define FLASH_STATUS_EARLY_BSY (0x00000002u) + #define FLASH_STATUS_EARLY_BSY_MASK (0x00000002u) + #define FLASH_STATUS_EARLY_BSY_BIT (1) + #define FLASH_STATUS_EARLY_BSY_BITS (1) + /* FLA_BSY field */ + #define FLASH_STATUS_FLA_BSY (0x00000001u) + #define FLASH_STATUS_FLA_BSY_MASK (0x00000001u) + #define FLASH_STATUS_FLA_BSY_BIT (0) + #define FLASH_STATUS_FLA_BSY_BITS (1) + +#define FLASH_CTRL *((volatile uint32_t *)0x40008010u) +#define FLASH_CTRL_REG *((volatile uint32_t *)0x40008010u) +#define FLASH_CTRL_ADDR (0x40008010u) +#define FLASH_CTRL_RESET (0x00000080u) + /* EOPIE field */ + #define FLASH_CTRL_EOPIE (0x00001000u) + #define FLASH_CTRL_EOPIE_MASK (0x00001000u) + #define FLASH_CTRL_EOPIE_BIT (12) + #define FLASH_CTRL_EOPIE_BITS (1) + /* EARLYBSYIE field */ + #define FLASH_CTRL_EARLYBSYIE (0x00000800u) + #define FLASH_CTRL_EARLYBSYIE_MASK (0x00000800u) + #define FLASH_CTRL_EARLYBSYIE_BIT (11) + #define FLASH_CTRL_EARLYBSYIE_BITS (1) + /* ERRIE field */ + #define FLASH_CTRL_ERRIE (0x00000400u) + #define FLASH_CTRL_ERRIE_MASK (0x00000400u) + #define FLASH_CTRL_ERRIE_BIT (10) + #define FLASH_CTRL_ERRIE_BITS (1) + /* OPTWREN field */ + #define FLASH_CTRL_OPTWREN (0x00000200u) + #define FLASH_CTRL_OPTWREN_MASK (0x00000200u) + #define FLASH_CTRL_OPTWREN_BIT (9) + #define FLASH_CTRL_OPTWREN_BITS (1) + /* FSTPROG field */ + #define FLASH_CTRL_FSTPROG (0x00000100u) + #define FLASH_CTRL_FSTPROG_MASK (0x00000100u) + #define FLASH_CTRL_FSTPROG_BIT (8) + #define FLASH_CTRL_FSTPROG_BITS (1) + /* LOCK field */ + #define FLASH_CTRL_LOCK (0x00000080u) + #define FLASH_CTRL_LOCK_MASK (0x00000080u) + #define FLASH_CTRL_LOCK_BIT (7) + #define FLASH_CTRL_LOCK_BITS (1) + /* FLA_START field */ + #define FLASH_CTRL_FLA_START (0x00000040u) + #define FLASH_CTRL_FLA_START_MASK (0x00000040u) + #define FLASH_CTRL_FLA_START_BIT (6) + #define FLASH_CTRL_FLA_START_BITS (1) + /* OPTERASE field */ + #define FLASH_CTRL_OPTERASE (0x00000020u) + #define FLASH_CTRL_OPTERASE_MASK (0x00000020u) + #define FLASH_CTRL_OPTERASE_BIT (5) + #define FLASH_CTRL_OPTERASE_BITS (1) + /* OPTPROG field */ + #define FLASH_CTRL_OPTPROG (0x00000010u) + #define FLASH_CTRL_OPTPROG_MASK (0x00000010u) + #define FLASH_CTRL_OPTPROG_BIT (4) + #define FLASH_CTRL_OPTPROG_BITS (1) + /* GLOBALERASE field */ + #define FLASH_CTRL_GLOBALERASE (0x00000008u) + #define FLASH_CTRL_GLOBALERASE_MASK (0x00000008u) + #define FLASH_CTRL_GLOBALERASE_BIT (3) + #define FLASH_CTRL_GLOBALERASE_BITS (1) + /* MASSERASE field */ + #define FLASH_CTRL_MASSERASE (0x00000004u) + #define FLASH_CTRL_MASSERASE_MASK (0x00000004u) + #define FLASH_CTRL_MASSERASE_BIT (2) + #define FLASH_CTRL_MASSERASE_BITS (1) + /* PAGEERASE field */ + #define FLASH_CTRL_PAGEERASE (0x00000002u) + #define FLASH_CTRL_PAGEERASE_MASK (0x00000002u) + #define FLASH_CTRL_PAGEERASE_BIT (1) + #define FLASH_CTRL_PAGEERASE_BITS (1) + /* PROG field */ + #define FLASH_CTRL_PROG (0x00000001u) + #define FLASH_CTRL_PROG_MASK (0x00000001u) + #define FLASH_CTRL_PROG_BIT (0) + #define FLASH_CTRL_PROG_BITS (1) + +#define FLASH_ADDR *((volatile uint32_t *)0x40008014u) +#define FLASH_ADDR_REG *((volatile uint32_t *)0x40008014u) +#define FLASH_ADDR_ADDR (0x40008014u) +#define FLASH_ADDR_RESET (0x00000000u) + /* FAR field */ + #define FLASH_ADDR_FAR (0xFFFFFFFFu) + #define FLASH_ADDR_FAR_MASK (0xFFFFFFFFu) + #define FLASH_ADDR_FAR_BIT (0) + #define FLASH_ADDR_FAR_BITS (32) + +#define OPT_BYTE *((volatile uint32_t *)0x4000801Cu) +#define OPT_BYTE_REG *((volatile uint32_t *)0x4000801Cu) +#define OPT_BYTE_ADDR (0x4000801Cu) +#define OPT_BYTE_RESET (0xFBFFFFFEu) + /* RSVD field */ + #define OPT_BYTE_RSVD (0xF8000000u) + #define OPT_BYTE_RSVD_MASK (0xF8000000u) + #define OPT_BYTE_RSVD_BIT (27) + #define OPT_BYTE_RSVD_BITS (5) + /* OBR field */ + #define OPT_BYTE_OBR (0x07FFFFFCu) + #define OPT_BYTE_OBR_MASK (0x07FFFFFCu) + #define OPT_BYTE_OBR_BIT (2) + #define OPT_BYTE_OBR_BITS (25) + /* RDPROT field */ + #define OPT_BYTE_RDPROT (0x00000002u) + #define OPT_BYTE_RDPROT_MASK (0x00000002u) + #define OPT_BYTE_RDPROT_BIT (1) + #define OPT_BYTE_RDPROT_BITS (1) + /* OPT_ERR field */ + #define OPT_BYTE_OPT_ERR (0x00000001u) + #define OPT_BYTE_OPT_ERR_MASK (0x00000001u) + #define OPT_BYTE_OPT_ERR_BIT (0) + #define OPT_BYTE_OPT_ERR_BITS (1) + +#define WRPROT *((volatile uint32_t *)0x40008020u) +#define WRPROT_REG *((volatile uint32_t *)0x40008020u) +#define WRPROT_ADDR (0x40008020u) +#define WRPROT_RESET (0xFFFFFFFFu) + /* WRP field */ + #define WRPROT_WRP (0xFFFFFFFFu) + #define WRPROT_WRP_MASK (0xFFFFFFFFu) + #define WRPROT_WRP_BIT (0) + #define WRPROT_WRP_BITS (32) + +#define FLASH_TEST_CTRL *((volatile uint32_t *)0x40008080u) +#define FLASH_TEST_CTRL_REG *((volatile uint32_t *)0x40008080u) +#define FLASH_TEST_CTRL_ADDR (0x40008080u) +#define FLASH_TEST_CTRL_RESET (0x00000000u) + /* TMR field */ + #define FLASH_TEST_CTRL_TMR (0x00001000u) + #define FLASH_TEST_CTRL_TMR_MASK (0x00001000u) + #define FLASH_TEST_CTRL_TMR_BIT (12) + #define FLASH_TEST_CTRL_TMR_BITS (1) + /* ERASE field */ + #define FLASH_TEST_CTRL_ERASE (0x00000800u) + #define FLASH_TEST_CTRL_ERASE_MASK (0x00000800u) + #define FLASH_TEST_CTRL_ERASE_BIT (11) + #define FLASH_TEST_CTRL_ERASE_BITS (1) + /* MAS1 field */ + #define FLASH_TEST_CTRL_MAS1 (0x00000400u) + #define FLASH_TEST_CTRL_MAS1_MASK (0x00000400u) + #define FLASH_TEST_CTRL_MAS1_BIT (10) + #define FLASH_TEST_CTRL_MAS1_BITS (1) + /* TEST_PROG field */ + #define FLASH_TEST_CTRL_TEST_PROG (0x00000200u) + #define FLASH_TEST_CTRL_TEST_PROG_MASK (0x00000200u) + #define FLASH_TEST_CTRL_TEST_PROG_BIT (9) + #define FLASH_TEST_CTRL_TEST_PROG_BITS (1) + /* NVSTR field */ + #define FLASH_TEST_CTRL_NVSTR (0x00000100u) + #define FLASH_TEST_CTRL_NVSTR_MASK (0x00000100u) + #define FLASH_TEST_CTRL_NVSTR_BIT (8) + #define FLASH_TEST_CTRL_NVSTR_BITS (1) + /* SE field */ + #define FLASH_TEST_CTRL_SE (0x00000080u) + #define FLASH_TEST_CTRL_SE_MASK (0x00000080u) + #define FLASH_TEST_CTRL_SE_BIT (7) + #define FLASH_TEST_CTRL_SE_BITS (1) + /* IFREN field */ + #define FLASH_TEST_CTRL_IFREN (0x00000040u) + #define FLASH_TEST_CTRL_IFREN_MASK (0x00000040u) + #define FLASH_TEST_CTRL_IFREN_BIT (6) + #define FLASH_TEST_CTRL_IFREN_BITS (1) + /* YE field */ + #define FLASH_TEST_CTRL_YE (0x00000020u) + #define FLASH_TEST_CTRL_YE_MASK (0x00000020u) + #define FLASH_TEST_CTRL_YE_BIT (5) + #define FLASH_TEST_CTRL_YE_BITS (1) + /* XE field */ + #define FLASH_TEST_CTRL_XE (0x00000010u) + #define FLASH_TEST_CTRL_XE_MASK (0x00000010u) + #define FLASH_TEST_CTRL_XE_BIT (4) + #define FLASH_TEST_CTRL_XE_BITS (1) + /* SW_CTRL field */ + #define FLASH_TEST_CTRL_SW_CTRL (0x00000008u) + #define FLASH_TEST_CTRL_SW_CTRL_MASK (0x00000008u) + #define FLASH_TEST_CTRL_SW_CTRL_BIT (3) + #define FLASH_TEST_CTRL_SW_CTRL_BITS (1) + /* SW field */ + #define FLASH_TEST_CTRL_SW (0x00000006u) + #define FLASH_TEST_CTRL_SW_MASK (0x00000006u) + #define FLASH_TEST_CTRL_SW_BIT (1) + #define FLASH_TEST_CTRL_SW_BITS (2) + /* SW_EN field */ + #define FLASH_TEST_CTRL_SW_EN (0x00000001u) + #define FLASH_TEST_CTRL_SW_EN_MASK (0x00000001u) + #define FLASH_TEST_CTRL_SW_EN_BIT (0) + #define FLASH_TEST_CTRL_SW_EN_BITS (1) + +#define FLASH_DATA0 *((volatile uint32_t *)0x40008084u) +#define FLASH_DATA0_REG *((volatile uint32_t *)0x40008084u) +#define FLASH_DATA0_ADDR (0x40008084u) +#define FLASH_DATA0_RESET (0xFFFFFFFFu) + /* FDR0 field */ + #define FLASH_DATA0_FDR0 (0xFFFFFFFFu) + #define FLASH_DATA0_FDR0_MASK (0xFFFFFFFFu) + #define FLASH_DATA0_FDR0_BIT (0) + #define FLASH_DATA0_FDR0_BITS (32) + +/* EMU_REGS block */ +#define DATA_EMU_REGS_BASE (0x40009000u) +#define DATA_EMU_REGS_END (0x40009000u) +#define DATA_EMU_REGS_SIZE (DATA_EMU_REGS_END - DATA_EMU_REGS_BASE + 1) + +#define I_AM_AN_EMULATOR *((volatile uint32_t *)0x40009000u) +#define I_AM_AN_EMULATOR_REG *((volatile uint32_t *)0x40009000u) +#define I_AM_AN_EMULATOR_ADDR (0x40009000u) +#define I_AM_AN_EMULATOR_RESET (0x00000000u) + /* I_AM_AN_EMULATOR field */ + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR (0x00000001u) + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK (0x00000001u) + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT (0) + #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS (1) + +/* INTERRUPTS block */ +#define BLOCK_INTERRUPTS_BASE (0x4000A000u) +#define BLOCK_INTERRUPTS_END (0x4000A86Cu) +#define BLOCK_INTERRUPTS_SIZE (BLOCK_INTERRUPTS_END - BLOCK_INTERRUPTS_BASE + 1) + +#define MAC_RX_INT_SRC *((volatile uint32_t *)0x4000A000u) +#define MAC_RX_INT_SRC_REG *((volatile uint32_t *)0x4000A000u) +#define MAC_RX_INT_SRC_ADDR (0x4000A000u) +#define MAC_RX_INT_SRC_RESET (0x00000000u) + /* TX_B_ACK_ERR_SRC field */ + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC (0x00008000u) + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_MASK (0x00008000u) + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BIT (15) + #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BITS (1) + /* TX_A_ACK_ERR_SRC field */ + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC (0x00004000u) + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_MASK (0x00004000u) + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BIT (14) + #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BITS (1) + /* RX_OVFLW_SRC field */ + #define MAC_RX_INT_SRC_RX_OVFLW_SRC (0x00002000u) + #define MAC_RX_INT_SRC_RX_OVFLW_SRC_MASK (0x00002000u) + #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BIT (13) + #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BITS (1) + /* RX_ERROR_SRC field */ + #define MAC_RX_INT_SRC_RX_ERROR_SRC (0x00001000u) + #define MAC_RX_INT_SRC_RX_ERROR_SRC_MASK (0x00001000u) + #define MAC_RX_INT_SRC_RX_ERROR_SRC_BIT (12) + #define MAC_RX_INT_SRC_RX_ERROR_SRC_BITS (1) + /* BB_RX_LEN_ERR_SRC field */ + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC (0x00000800u) + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_MASK (0x00000800u) + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BIT (11) + #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BITS (1) + /* TX_COLL_RX_SRC field */ + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC (0x00000400u) + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_MASK (0x00000400u) + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BIT (10) + #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BITS (1) + /* RSSI_INST_MEAS_SRC field */ + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC (0x00000200u) + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_MASK (0x00000200u) + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BIT (9) + #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BITS (1) + /* TX_B_ACK_SRC field */ + #define MAC_RX_INT_SRC_TX_B_ACK_SRC (0x00000100u) + #define MAC_RX_INT_SRC_TX_B_ACK_SRC_MASK (0x00000100u) + #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BIT (8) + #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BITS (1) + /* TX_A_ACK_SRC field */ + #define MAC_RX_INT_SRC_TX_A_ACK_SRC (0x00000080u) + #define MAC_RX_INT_SRC_TX_A_ACK_SRC_MASK (0x00000080u) + #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BIT (7) + #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BITS (1) + /* RX_B_UNLOAD_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC (0x00000040u) + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_MASK (0x00000040u) + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BIT (6) + #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BITS (1) + /* RX_A_UNLOAD_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC (0x00000020u) + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_MASK (0x00000020u) + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BIT (5) + #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BITS (1) + /* RX_B_ADDR_REC_SRC field */ + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC (0x00000010u) + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_MASK (0x00000010u) + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BIT (4) + #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BITS (1) + /* RX_A_ADDR_REC_SRC field */ + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC (0x00000008u) + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_MASK (0x00000008u) + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BIT (3) + #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BITS (1) + /* RX_B_FILT_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC (0x00000004u) + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_MASK (0x00000004u) + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BIT (2) + #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BITS (1) + /* RX_A_FILT_COMP_SRC field */ + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC (0x00000002u) + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_MASK (0x00000002u) + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BIT (1) + #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BITS (1) + /* RX_FRAME_SRC field */ + #define MAC_RX_INT_SRC_RX_FRAME_SRC (0x00000001u) + #define MAC_RX_INT_SRC_RX_FRAME_SRC_MASK (0x00000001u) + #define MAC_RX_INT_SRC_RX_FRAME_SRC_BIT (0) + #define MAC_RX_INT_SRC_RX_FRAME_SRC_BITS (1) + +#define MAC_TX_INT_SRC *((volatile uint32_t *)0x4000A004u) +#define MAC_TX_INT_SRC_REG *((volatile uint32_t *)0x4000A004u) +#define MAC_TX_INT_SRC_ADDR (0x4000A004u) +#define MAC_TX_INT_SRC_RESET (0x00000000u) + /* RX_B_ACK_SRC field */ + #define MAC_TX_INT_SRC_RX_B_ACK_SRC (0x00000800u) + #define MAC_TX_INT_SRC_RX_B_ACK_SRC_MASK (0x00000800u) + #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BIT (11) + #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BITS (1) + /* RX_A_ACK_SRC field */ + #define MAC_TX_INT_SRC_RX_A_ACK_SRC (0x00000400u) + #define MAC_TX_INT_SRC_RX_A_ACK_SRC_MASK (0x00000400u) + #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BIT (10) + #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BITS (1) + /* TX_B_UNLOAD_SRC field */ + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC (0x00000200u) + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_MASK (0x00000200u) + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BIT (9) + #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BITS (1) + /* TX_A_UNLOAD_SRC field */ + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC (0x00000100u) + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_MASK (0x00000100u) + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BIT (8) + #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BITS (1) + /* ACK_EXPIRED_SRC field */ + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC (0x00000080u) + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_MASK (0x00000080u) + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BIT (7) + #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BITS (1) + /* TX_LOCK_FAIL_SRC field */ + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC (0x00000040u) + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_MASK (0x00000040u) + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BIT (6) + #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BITS (1) + /* TX_UNDERFLOW_SRC field */ + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC (0x00000020u) + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_MASK (0x00000020u) + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BIT (5) + #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BITS (1) + /* CCA_FAIL_SRC field */ + #define MAC_TX_INT_SRC_CCA_FAIL_SRC (0x00000010u) + #define MAC_TX_INT_SRC_CCA_FAIL_SRC_MASK (0x00000010u) + #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BIT (4) + #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BITS (1) + /* SFD_SENT_SRC field */ + #define MAC_TX_INT_SRC_SFD_SENT_SRC (0x00000008u) + #define MAC_TX_INT_SRC_SFD_SENT_SRC_MASK (0x00000008u) + #define MAC_TX_INT_SRC_SFD_SENT_SRC_BIT (3) + #define MAC_TX_INT_SRC_SFD_SENT_SRC_BITS (1) + /* BO_COMPLETE_SRC field */ + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC (0x00000004u) + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_MASK (0x00000004u) + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BIT (2) + #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BITS (1) + /* RX_ACK_SRC field */ + #define MAC_TX_INT_SRC_RX_ACK_SRC (0x00000002u) + #define MAC_TX_INT_SRC_RX_ACK_SRC_MASK (0x00000002u) + #define MAC_TX_INT_SRC_RX_ACK_SRC_BIT (1) + #define MAC_TX_INT_SRC_RX_ACK_SRC_BITS (1) + /* TX_COMPLETE_SRC field */ + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC (0x00000001u) + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_MASK (0x00000001u) + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT (0) + #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS (1) + +#define MAC_TIMER_INT_SRC *((volatile uint32_t *)0x4000A008u) +#define MAC_TIMER_INT_SRC_REG *((volatile uint32_t *)0x4000A008u) +#define MAC_TIMER_INT_SRC_ADDR (0x4000A008u) +#define MAC_TIMER_INT_SRC_RESET (0x00000000u) + /* TIMER_COMP_B_SRC field */ + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC (0x00000004u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_MASK (0x00000004u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BIT (2) + #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BITS (1) + /* TIMER_COMP_A_SRC field */ + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC (0x00000002u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_MASK (0x00000002u) + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BIT (1) + #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BITS (1) + /* TIMER_WRAP_SRC field */ + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC (0x00000001u) + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_MASK (0x00000001u) + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT (0) + #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS (1) + +#define BB_INT_SRC *((volatile uint32_t *)0x4000A00Cu) +#define BB_INT_SRC_REG *((volatile uint32_t *)0x4000A00Cu) +#define BB_INT_SRC_ADDR (0x4000A00Cu) +#define BB_INT_SRC_RESET (0x00000000u) + /* RSSI_INT_SRC field */ + #define BB_INT_SRC_RSSI_INT_SRC (0x00000002u) + #define BB_INT_SRC_RSSI_INT_SRC_MASK (0x00000002u) + #define BB_INT_SRC_RSSI_INT_SRC_BIT (1) + #define BB_INT_SRC_RSSI_INT_SRC_BITS (1) + /* BASEBAND_INT_SRC field */ + #define BB_INT_SRC_BASEBAND_INT_SRC (0x00000001u) + #define BB_INT_SRC_BASEBAND_INT_SRC_MASK (0x00000001u) + #define BB_INT_SRC_BASEBAND_INT_SRC_BIT (0) + #define BB_INT_SRC_BASEBAND_INT_SRC_BITS (1) + +#define SEC_INT_SRC *((volatile uint32_t *)0x4000A010u) +#define SEC_INT_SRC_REG *((volatile uint32_t *)0x4000A010u) +#define SEC_INT_SRC_ADDR (0x4000A010u) +#define SEC_INT_SRC_RESET (0x00000000u) + /* CT_WORD_VALID_SRC field */ + #define SEC_INT_SRC_CT_WORD_VALID_SRC (0x00000004u) + #define SEC_INT_SRC_CT_WORD_VALID_SRC_MASK (0x00000004u) + #define SEC_INT_SRC_CT_WORD_VALID_SRC_BIT (2) + #define SEC_INT_SRC_CT_WORD_VALID_SRC_BITS (1) + /* PT_WORD_REQ_SRC field */ + #define SEC_INT_SRC_PT_WORD_REQ_SRC (0x00000002u) + #define SEC_INT_SRC_PT_WORD_REQ_SRC_MASK (0x00000002u) + #define SEC_INT_SRC_PT_WORD_REQ_SRC_BIT (1) + #define SEC_INT_SRC_PT_WORD_REQ_SRC_BITS (1) + /* ENC_COMPLETE_SRC field */ + #define SEC_INT_SRC_ENC_COMPLETE_SRC (0x00000001u) + #define SEC_INT_SRC_ENC_COMPLETE_SRC_MASK (0x00000001u) + #define SEC_INT_SRC_ENC_COMPLETE_SRC_BIT (0) + #define SEC_INT_SRC_ENC_COMPLETE_SRC_BITS (1) + +#define INT_SLEEPTMRFLAG *((volatile uint32_t *)0x4000A014u) +#define INT_SLEEPTMRFLAG_REG *((volatile uint32_t *)0x4000A014u) +#define INT_SLEEPTMRFLAG_ADDR (0x4000A014u) +#define INT_SLEEPTMRFLAG_RESET (0x00000000u) + /* INT_SLEEPTMRCMPB field */ + #define INT_SLEEPTMRCMPB (0x00000004u) + #define INT_SLEEPTMRCMPB_MASK (0x00000004u) + #define INT_SLEEPTMRCMPB_BIT (2) + #define INT_SLEEPTMRCMPB_BITS (1) + /* INT_SLEEPTMRCMPA field */ + #define INT_SLEEPTMRCMPA (0x00000002u) + #define INT_SLEEPTMRCMPA_MASK (0x00000002u) + #define INT_SLEEPTMRCMPA_BIT (1) + #define INT_SLEEPTMRCMPA_BITS (1) + /* INT_SLEEPTMRWRAP field */ + #define INT_SLEEPTMRWRAP (0x00000001u) + #define INT_SLEEPTMRWRAP_MASK (0x00000001u) + #define INT_SLEEPTMRWRAP_BIT (0) + #define INT_SLEEPTMRWRAP_BITS (1) + +#define INT_MGMTFLAG *((volatile uint32_t *)0x4000A018u) +#define INT_MGMTFLAG_REG *((volatile uint32_t *)0x4000A018u) +#define INT_MGMTFLAG_ADDR (0x4000A018u) +#define INT_MGMTFLAG_RESET (0x00000000u) + /* INT_MGMTDMAPROT field */ + #define INT_MGMTDMAPROT (0x00000010u) + #define INT_MGMTDMAPROT_MASK (0x00000010u) + #define INT_MGMTDMAPROT_BIT (4) + #define INT_MGMTDMAPROT_BITS (1) + /* INT_MGMTCALADC field */ + #define INT_MGMTCALADC (0x00000008u) + #define INT_MGMTCALADC_MASK (0x00000008u) + #define INT_MGMTCALADC_BIT (3) + #define INT_MGMTCALADC_BITS (1) + /* INT_MGMTFPEC field */ + #define INT_MGMTFPEC (0x00000004u) + #define INT_MGMTFPEC_MASK (0x00000004u) + #define INT_MGMTFPEC_BIT (2) + #define INT_MGMTFPEC_BITS (1) + /* INT_MGMTOSC24MHI field */ + #define INT_MGMTOSC24MHI (0x00000002u) + #define INT_MGMTOSC24MHI_MASK (0x00000002u) + #define INT_MGMTOSC24MHI_BIT (1) + #define INT_MGMTOSC24MHI_BITS (1) + /* INT_MGMTOSC24MLO field */ + #define INT_MGMTOSC24MLO (0x00000001u) + #define INT_MGMTOSC24MLO_MASK (0x00000001u) + #define INT_MGMTOSC24MLO_BIT (0) + #define INT_MGMTOSC24MLO_BITS (1) + +#define INT_NMIFLAG *((volatile uint32_t *)0x4000A01Cu) +#define INT_NMIFLAG_REG *((volatile uint32_t *)0x4000A01Cu) +#define INT_NMIFLAG_ADDR (0x4000A01Cu) +#define INT_NMIFLAG_RESET (0x00000000u) + /* INT_NMICLK24M field */ + #define INT_NMICLK24M (0x00000002u) + #define INT_NMICLK24M_MASK (0x00000002u) + #define INT_NMICLK24M_BIT (1) + #define INT_NMICLK24M_BITS (1) + /* INT_NMIWDOG field */ + #define INT_NMIWDOG (0x00000001u) + #define INT_NMIWDOG_MASK (0x00000001u) + #define INT_NMIWDOG_BIT (0) + #define INT_NMIWDOG_BITS (1) + +#define INT_SLEEPTMRFORCE *((volatile uint32_t *)0x4000A020u) +#define INT_SLEEPTMRFORCE_REG *((volatile uint32_t *)0x4000A020u) +#define INT_SLEEPTMRFORCE_ADDR (0x4000A020u) +#define INT_SLEEPTMRFORCE_RESET (0x00000000u) + /* INT_SLEEPTMRCMPB field */ + #define INT_SLEEPTMRCMPB (0x00000004u) + #define INT_SLEEPTMRCMPB_MASK (0x00000004u) + #define INT_SLEEPTMRCMPB_BIT (2) + #define INT_SLEEPTMRCMPB_BITS (1) + /* INT_SLEEPTMRCMPA field */ + #define INT_SLEEPTMRCMPA (0x00000002u) + #define INT_SLEEPTMRCMPA_MASK (0x00000002u) + #define INT_SLEEPTMRCMPA_BIT (1) + #define INT_SLEEPTMRCMPA_BITS (1) + /* INT_SLEEPTMRWRAP field */ + #define INT_SLEEPTMRWRAP (0x00000001u) + #define INT_SLEEPTMRWRAP_MASK (0x00000001u) + #define INT_SLEEPTMRWRAP_BIT (0) + #define INT_SLEEPTMRWRAP_BITS (1) + +#define TEST_FORCE_ALL_INT *((volatile uint32_t *)0x4000A024u) +#define TEST_FORCE_ALL_INT_REG *((volatile uint32_t *)0x4000A024u) +#define TEST_FORCE_ALL_INT_ADDR (0x4000A024u) +#define TEST_FORCE_ALL_INT_RESET (0x00000000u) + /* FORCE_ALL_INT field */ + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT (0x00000001u) + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_MASK (0x00000001u) + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT (0) + #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS (1) + +#define MAC_RX_INT_MASK *((volatile uint32_t *)0x4000A040u) +#define MAC_RX_INT_MASK_REG *((volatile uint32_t *)0x4000A040u) +#define MAC_RX_INT_MASK_ADDR (0x4000A040u) +#define MAC_RX_INT_MASK_RESET (0x00000000u) + /* TX_B_ACK_ERR_MSK field */ + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK (0x00008000u) + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_MASK (0x00008000u) + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BIT (15) + #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BITS (1) + /* TX_A_ACK_ERR_MSK field */ + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK (0x00004000u) + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_MASK (0x00004000u) + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BIT (14) + #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BITS (1) + /* RX_OVFLW_MSK field */ + #define MAC_RX_INT_MASK_RX_OVFLW_MSK (0x00002000u) + #define MAC_RX_INT_MASK_RX_OVFLW_MSK_MASK (0x00002000u) + #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BIT (13) + #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BITS (1) + /* RX_ERROR_MSK field */ + #define MAC_RX_INT_MASK_RX_ERROR_MSK (0x00001000u) + #define MAC_RX_INT_MASK_RX_ERROR_MSK_MASK (0x00001000u) + #define MAC_RX_INT_MASK_RX_ERROR_MSK_BIT (12) + #define MAC_RX_INT_MASK_RX_ERROR_MSK_BITS (1) + /* BB_RX_LEN_ERR_MSK field */ + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK (0x00000800u) + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_MASK (0x00000800u) + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BIT (11) + #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BITS (1) + /* TX_COLL_RX_MSK field */ + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK (0x00000400u) + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_MASK (0x00000400u) + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BIT (10) + #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BITS (1) + /* RSSI_INST_MEAS_MSK field */ + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK (0x00000200u) + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_MASK (0x00000200u) + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BIT (9) + #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BITS (1) + /* TX_B_ACK_MSK field */ + #define MAC_RX_INT_MASK_TX_B_ACK_MSK (0x00000100u) + #define MAC_RX_INT_MASK_TX_B_ACK_MSK_MASK (0x00000100u) + #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BIT (8) + #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BITS (1) + /* TX_A_ACK_MSK field */ + #define MAC_RX_INT_MASK_TX_A_ACK_MSK (0x00000080u) + #define MAC_RX_INT_MASK_TX_A_ACK_MSK_MASK (0x00000080u) + #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BIT (7) + #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BITS (1) + /* RX_B_UNLOAD_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK (0x00000040u) + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_MASK (0x00000040u) + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BIT (6) + #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BITS (1) + /* RX_A_UNLOAD_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK (0x00000020u) + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_MASK (0x00000020u) + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BIT (5) + #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BITS (1) + /* RX_B_ADDR_REC_MSK field */ + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK (0x00000010u) + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_MASK (0x00000010u) + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BIT (4) + #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BITS (1) + /* RX_A_ADDR_REC_MSK field */ + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK (0x00000008u) + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_MASK (0x00000008u) + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BIT (3) + #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BITS (1) + /* RX_B_FILT_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK (0x00000004u) + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_MASK (0x00000004u) + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BIT (2) + #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BITS (1) + /* RX_A_FILT_COMP_MSK field */ + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK (0x00000002u) + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_MASK (0x00000002u) + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BIT (1) + #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BITS (1) + /* RX_FRAME_MSK field */ + #define MAC_RX_INT_MASK_RX_FRAME_MSK (0x00000001u) + #define MAC_RX_INT_MASK_RX_FRAME_MSK_MASK (0x00000001u) + #define MAC_RX_INT_MASK_RX_FRAME_MSK_BIT (0) + #define MAC_RX_INT_MASK_RX_FRAME_MSK_BITS (1) + +#define MAC_TX_INT_MASK *((volatile uint32_t *)0x4000A044u) +#define MAC_TX_INT_MASK_REG *((volatile uint32_t *)0x4000A044u) +#define MAC_TX_INT_MASK_ADDR (0x4000A044u) +#define MAC_TX_INT_MASK_RESET (0x00000000u) + /* RX_B_ACK_MSK field */ + #define MAC_TX_INT_MASK_RX_B_ACK_MSK (0x00000800u) + #define MAC_TX_INT_MASK_RX_B_ACK_MSK_MASK (0x00000800u) + #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BIT (11) + #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BITS (1) + /* RX_A_ACK_MSK field */ + #define MAC_TX_INT_MASK_RX_A_ACK_MSK (0x00000400u) + #define MAC_TX_INT_MASK_RX_A_ACK_MSK_MASK (0x00000400u) + #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BIT (10) + #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BITS (1) + /* TX_B_UNLOAD_MSK field */ + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK (0x00000200u) + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_MASK (0x00000200u) + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BIT (9) + #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BITS (1) + /* TX_A_UNLOAD_MSK field */ + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK (0x00000100u) + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_MASK (0x00000100u) + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BIT (8) + #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BITS (1) + /* ACK_EXPIRED_MSK field */ + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK (0x00000080u) + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_MASK (0x00000080u) + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BIT (7) + #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BITS (1) + /* TX_LOCK_FAIL_MSK field */ + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK (0x00000040u) + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_MASK (0x00000040u) + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BIT (6) + #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BITS (1) + /* TX_UNDERFLOW_MSK field */ + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK (0x00000020u) + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_MASK (0x00000020u) + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BIT (5) + #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BITS (1) + /* CCA_FAIL_MSK field */ + #define MAC_TX_INT_MASK_CCA_FAIL_MSK (0x00000010u) + #define MAC_TX_INT_MASK_CCA_FAIL_MSK_MASK (0x00000010u) + #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BIT (4) + #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BITS (1) + /* SFD_SENT_MSK field */ + #define MAC_TX_INT_MASK_SFD_SENT_MSK (0x00000008u) + #define MAC_TX_INT_MASK_SFD_SENT_MSK_MASK (0x00000008u) + #define MAC_TX_INT_MASK_SFD_SENT_MSK_BIT (3) + #define MAC_TX_INT_MASK_SFD_SENT_MSK_BITS (1) + /* BO_COMPLETE_MSK field */ + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK (0x00000004u) + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_MASK (0x00000004u) + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BIT (2) + #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BITS (1) + /* RX_ACK_MSK field */ + #define MAC_TX_INT_MASK_RX_ACK_MSK (0x00000002u) + #define MAC_TX_INT_MASK_RX_ACK_MSK_MASK (0x00000002u) + #define MAC_TX_INT_MASK_RX_ACK_MSK_BIT (1) + #define MAC_TX_INT_MASK_RX_ACK_MSK_BITS (1) + /* TX_COMPLETE_MSK field */ + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK (0x00000001u) + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_MASK (0x00000001u) + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT (0) + #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS (1) + +#define MAC_TIMER_INT_MASK *((volatile uint32_t *)0x4000A048u) +#define MAC_TIMER_INT_MASK_REG *((volatile uint32_t *)0x4000A048u) +#define MAC_TIMER_INT_MASK_ADDR (0x4000A048u) +#define MAC_TIMER_INT_MASK_RESET (0x00000000u) + /* TIMER_COMP_B_MSK field */ + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK (0x00000004u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_MASK (0x00000004u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BIT (2) + #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BITS (1) + /* TIMER_COMP_A_MSK field */ + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK (0x00000002u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_MASK (0x00000002u) + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BIT (1) + #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BITS (1) + /* TIMER_WRAP_MSK field */ + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK (0x00000001u) + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_MASK (0x00000001u) + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT (0) + #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS (1) + +#define BB_INT_MASK *((volatile uint32_t *)0x4000A04Cu) +#define BB_INT_MASK_REG *((volatile uint32_t *)0x4000A04Cu) +#define BB_INT_MASK_ADDR (0x4000A04Cu) +#define BB_INT_MASK_RESET (0x00000000u) + /* RSSI_INT_MSK field */ + #define BB_INT_MASK_RSSI_INT_MSK (0x00000002u) + #define BB_INT_MASK_RSSI_INT_MSK_MASK (0x00000002u) + #define BB_INT_MASK_RSSI_INT_MSK_BIT (1) + #define BB_INT_MASK_RSSI_INT_MSK_BITS (1) + /* BASEBAND_INT_MSK field */ + #define BB_INT_MASK_BASEBAND_INT_MSK (0x00000001u) + #define BB_INT_MASK_BASEBAND_INT_MSK_MASK (0x00000001u) + #define BB_INT_MASK_BASEBAND_INT_MSK_BIT (0) + #define BB_INT_MASK_BASEBAND_INT_MSK_BITS (1) + +#define SEC_INT_MASK *((volatile uint32_t *)0x4000A050u) +#define SEC_INT_MASK_REG *((volatile uint32_t *)0x4000A050u) +#define SEC_INT_MASK_ADDR (0x4000A050u) +#define SEC_INT_MASK_RESET (0x00000000u) + /* CT_WORD_VALID_MSK field */ + #define SEC_INT_MASK_CT_WORD_VALID_MSK (0x00000004u) + #define SEC_INT_MASK_CT_WORD_VALID_MSK_MASK (0x00000004u) + #define SEC_INT_MASK_CT_WORD_VALID_MSK_BIT (2) + #define SEC_INT_MASK_CT_WORD_VALID_MSK_BITS (1) + /* PT_WORD_REQ_MSK field */ + #define SEC_INT_MASK_PT_WORD_REQ_MSK (0x00000002u) + #define SEC_INT_MASK_PT_WORD_REQ_MSK_MASK (0x00000002u) + #define SEC_INT_MASK_PT_WORD_REQ_MSK_BIT (1) + #define SEC_INT_MASK_PT_WORD_REQ_MSK_BITS (1) + /* ENC_COMPLETE_MSK field */ + #define SEC_INT_MASK_ENC_COMPLETE_MSK (0x00000001u) + #define SEC_INT_MASK_ENC_COMPLETE_MSK_MASK (0x00000001u) + #define SEC_INT_MASK_ENC_COMPLETE_MSK_BIT (0) + #define SEC_INT_MASK_ENC_COMPLETE_MSK_BITS (1) + +#define INT_SLEEPTMRCFG *((volatile uint32_t *)0x4000A054u) +#define INT_SLEEPTMRCFG_REG *((volatile uint32_t *)0x4000A054u) +#define INT_SLEEPTMRCFG_ADDR (0x4000A054u) +#define INT_SLEEPTMRCFG_RESET (0x00000000u) + /* INT_SLEEPTMRCMPB field */ + #define INT_SLEEPTMRCMPB (0x00000004u) + #define INT_SLEEPTMRCMPB_MASK (0x00000004u) + #define INT_SLEEPTMRCMPB_BIT (2) + #define INT_SLEEPTMRCMPB_BITS (1) + /* INT_SLEEPTMRCMPA field */ + #define INT_SLEEPTMRCMPA (0x00000002u) + #define INT_SLEEPTMRCMPA_MASK (0x00000002u) + #define INT_SLEEPTMRCMPA_BIT (1) + #define INT_SLEEPTMRCMPA_BITS (1) + /* INT_SLEEPTMRWRAP field */ + #define INT_SLEEPTMRWRAP (0x00000001u) + #define INT_SLEEPTMRWRAP_MASK (0x00000001u) + #define INT_SLEEPTMRWRAP_BIT (0) + #define INT_SLEEPTMRWRAP_BITS (1) + +#define INT_MGMTCFG *((volatile uint32_t *)0x4000A058u) +#define INT_MGMTCFG_REG *((volatile uint32_t *)0x4000A058u) +#define INT_MGMTCFG_ADDR (0x4000A058u) +#define INT_MGMTCFG_RESET (0x00000000u) + /* INT_MGMTDMAPROT field */ + #define INT_MGMTDMAPROT (0x00000010u) + #define INT_MGMTDMAPROT_MASK (0x00000010u) + #define INT_MGMTDMAPROT_BIT (4) + #define INT_MGMTDMAPROT_BITS (1) + /* INT_MGMTCALADC field */ + #define INT_MGMTCALADC (0x00000008u) + #define INT_MGMTCALADC_MASK (0x00000008u) + #define INT_MGMTCALADC_BIT (3) + #define INT_MGMTCALADC_BITS (1) + /* INT_MGMTFPEC field */ + #define INT_MGMTFPEC (0x00000004u) + #define INT_MGMTFPEC_MASK (0x00000004u) + #define INT_MGMTFPEC_BIT (2) + #define INT_MGMTFPEC_BITS (1) + /* INT_MGMTOSC24MHI field */ + #define INT_MGMTOSC24MHI (0x00000002u) + #define INT_MGMTOSC24MHI_MASK (0x00000002u) + #define INT_MGMTOSC24MHI_BIT (1) + #define INT_MGMTOSC24MHI_BITS (1) + /* INT_MGMTOSC24MLO field */ + #define INT_MGMTOSC24MLO (0x00000001u) + #define INT_MGMTOSC24MLO_MASK (0x00000001u) + #define INT_MGMTOSC24MLO_BIT (0) + #define INT_MGMTOSC24MLO_BITS (1) + +#define INT_TIM1FLAG *((volatile uint32_t *)0x4000A800u) +#define INT_TIM1FLAG_REG *((volatile uint32_t *)0x4000A800u) +#define INT_TIM1FLAG_ADDR (0x4000A800u) +#define INT_TIM1FLAG_RESET (0x00000000u) + /* INT_TIMRSVD field */ + #define INT_TIMRSVD (0x00001E00u) + #define INT_TIMRSVD_MASK (0x00001E00u) + #define INT_TIMRSVD_BIT (9) + #define INT_TIMRSVD_BITS (4) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_TIM2FLAG *((volatile uint32_t *)0x4000A804u) +#define INT_TIM2FLAG_REG *((volatile uint32_t *)0x4000A804u) +#define INT_TIM2FLAG_ADDR (0x4000A804u) +#define INT_TIM2FLAG_RESET (0x00000000u) + /* INT_TIMRSVD field */ + #define INT_TIMRSVD (0x00001E00u) + #define INT_TIMRSVD_MASK (0x00001E00u) + #define INT_TIMRSVD_BIT (9) + #define INT_TIMRSVD_BITS (4) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_SC1FLAG *((volatile uint32_t *)0x4000A808u) +#define INT_SC1FLAG_REG *((volatile uint32_t *)0x4000A808u) +#define INT_SC1FLAG_ADDR (0x4000A808u) +#define INT_SC1FLAG_RESET (0x00000000u) + /* INT_SC1PARERR field */ + #define INT_SC1PARERR (0x00004000u) + #define INT_SC1PARERR_MASK (0x00004000u) + #define INT_SC1PARERR_BIT (14) + #define INT_SC1PARERR_BITS (1) + /* INT_SC1FRMERR field */ + #define INT_SC1FRMERR (0x00002000u) + #define INT_SC1FRMERR_MASK (0x00002000u) + #define INT_SC1FRMERR_BIT (13) + #define INT_SC1FRMERR_BITS (1) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_SC2FLAG *((volatile uint32_t *)0x4000A80Cu) +#define INT_SC2FLAG_REG *((volatile uint32_t *)0x4000A80Cu) +#define INT_SC2FLAG_ADDR (0x4000A80Cu) +#define INT_SC2FLAG_RESET (0x00000000u) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_ADCFLAG *((volatile uint32_t *)0x4000A810u) +#define INT_ADCFLAG_REG *((volatile uint32_t *)0x4000A810u) +#define INT_ADCFLAG_ADDR (0x4000A810u) +#define INT_ADCFLAG_RESET (0x00000000u) + /* INT_ADCOVF field */ + #define INT_ADCOVF (0x00000010u) + #define INT_ADCOVF_MASK (0x00000010u) + #define INT_ADCOVF_BIT (4) + #define INT_ADCOVF_BITS (1) + /* INT_ADCSAT field */ + #define INT_ADCSAT (0x00000008u) + #define INT_ADCSAT_MASK (0x00000008u) + #define INT_ADCSAT_BIT (3) + #define INT_ADCSAT_BITS (1) + /* INT_ADCULDFULL field */ + #define INT_ADCULDFULL (0x00000004u) + #define INT_ADCULDFULL_MASK (0x00000004u) + #define INT_ADCULDFULL_BIT (2) + #define INT_ADCULDFULL_BITS (1) + /* INT_ADCULDHALF field */ + #define INT_ADCULDHALF (0x00000002u) + #define INT_ADCULDHALF_MASK (0x00000002u) + #define INT_ADCULDHALF_BIT (1) + #define INT_ADCULDHALF_BITS (1) + /* INT_ADCFLAGRSVD field */ + #define INT_ADCFLAGRSVD (0x00000001u) + #define INT_ADCFLAGRSVD_MASK (0x00000001u) + #define INT_ADCFLAGRSVD_BIT (0) + #define INT_ADCFLAGRSVD_BITS (1) + +#define INT_GPIOFLAG *((volatile uint32_t *)0x4000A814u) +#define INT_GPIOFLAG_REG *((volatile uint32_t *)0x4000A814u) +#define INT_GPIOFLAG_ADDR (0x4000A814u) +#define INT_GPIOFLAG_RESET (0x00000000u) + /* INT_IRQDFLAG field */ + #define INT_IRQDFLAG (0x00000008u) + #define INT_IRQDFLAG_MASK (0x00000008u) + #define INT_IRQDFLAG_BIT (3) + #define INT_IRQDFLAG_BITS (1) + /* INT_IRQCFLAG field */ + #define INT_IRQCFLAG (0x00000004u) + #define INT_IRQCFLAG_MASK (0x00000004u) + #define INT_IRQCFLAG_BIT (2) + #define INT_IRQCFLAG_BITS (1) + /* INT_IRQBFLAG field */ + #define INT_IRQBFLAG (0x00000002u) + #define INT_IRQBFLAG_MASK (0x00000002u) + #define INT_IRQBFLAG_BIT (1) + #define INT_IRQBFLAG_BITS (1) + /* INT_IRQAFLAG field */ + #define INT_IRQAFLAG (0x00000001u) + #define INT_IRQAFLAG_MASK (0x00000001u) + #define INT_IRQAFLAG_BIT (0) + #define INT_IRQAFLAG_BITS (1) + +#define INT_TIM1MISS *((volatile uint32_t *)0x4000A818u) +#define INT_TIM1MISS_REG *((volatile uint32_t *)0x4000A818u) +#define INT_TIM1MISS_ADDR (0x4000A818u) +#define INT_TIM1MISS_RESET (0x00000000u) + /* INT_TIMMISSCC4IF field */ + #define INT_TIMMISSCC4IF (0x00001000u) + #define INT_TIMMISSCC4IF_MASK (0x00001000u) + #define INT_TIMMISSCC4IF_BIT (12) + #define INT_TIMMISSCC4IF_BITS (1) + /* INT_TIMMISSCC3IF field */ + #define INT_TIMMISSCC3IF (0x00000800u) + #define INT_TIMMISSCC3IF_MASK (0x00000800u) + #define INT_TIMMISSCC3IF_BIT (11) + #define INT_TIMMISSCC3IF_BITS (1) + /* INT_TIMMISSCC2IF field */ + #define INT_TIMMISSCC2IF (0x00000400u) + #define INT_TIMMISSCC2IF_MASK (0x00000400u) + #define INT_TIMMISSCC2IF_BIT (10) + #define INT_TIMMISSCC2IF_BITS (1) + /* INT_TIMMISSCC1IF field */ + #define INT_TIMMISSCC1IF (0x00000200u) + #define INT_TIMMISSCC1IF_MASK (0x00000200u) + #define INT_TIMMISSCC1IF_BIT (9) + #define INT_TIMMISSCC1IF_BITS (1) + /* INT_TIMMISSRSVD field */ + #define INT_TIMMISSRSVD (0x0000007Fu) + #define INT_TIMMISSRSVD_MASK (0x0000007Fu) + #define INT_TIMMISSRSVD_BIT (0) + #define INT_TIMMISSRSVD_BITS (7) + +#define INT_TIM2MISS *((volatile uint32_t *)0x4000A81Cu) +#define INT_TIM2MISS_REG *((volatile uint32_t *)0x4000A81Cu) +#define INT_TIM2MISS_ADDR (0x4000A81Cu) +#define INT_TIM2MISS_RESET (0x00000000u) + /* INT_TIMMISSCC4IF field */ + #define INT_TIMMISSCC4IF (0x00001000u) + #define INT_TIMMISSCC4IF_MASK (0x00001000u) + #define INT_TIMMISSCC4IF_BIT (12) + #define INT_TIMMISSCC4IF_BITS (1) + /* INT_TIMMISSCC3IF field */ + #define INT_TIMMISSCC3IF (0x00000800u) + #define INT_TIMMISSCC3IF_MASK (0x00000800u) + #define INT_TIMMISSCC3IF_BIT (11) + #define INT_TIMMISSCC3IF_BITS (1) + /* INT_TIMMISSCC2IF field */ + #define INT_TIMMISSCC2IF (0x00000400u) + #define INT_TIMMISSCC2IF_MASK (0x00000400u) + #define INT_TIMMISSCC2IF_BIT (10) + #define INT_TIMMISSCC2IF_BITS (1) + /* INT_TIMMISSCC1IF field */ + #define INT_TIMMISSCC1IF (0x00000200u) + #define INT_TIMMISSCC1IF_MASK (0x00000200u) + #define INT_TIMMISSCC1IF_BIT (9) + #define INT_TIMMISSCC1IF_BITS (1) + /* INT_TIMMISSRSVD field */ + #define INT_TIMMISSRSVD (0x0000007Fu) + #define INT_TIMMISSRSVD_MASK (0x0000007Fu) + #define INT_TIMMISSRSVD_BIT (0) + #define INT_TIMMISSRSVD_BITS (7) + +#define INT_MISS *((volatile uint32_t *)0x4000A820u) +#define INT_MISS_REG *((volatile uint32_t *)0x4000A820u) +#define INT_MISS_ADDR (0x4000A820u) +#define INT_MISS_RESET (0x00000000u) + /* INT_MISSIRQD field */ + #define INT_MISSIRQD (0x00008000u) + #define INT_MISSIRQD_MASK (0x00008000u) + #define INT_MISSIRQD_BIT (15) + #define INT_MISSIRQD_BITS (1) + /* INT_MISSIRQC field */ + #define INT_MISSIRQC (0x00004000u) + #define INT_MISSIRQC_MASK (0x00004000u) + #define INT_MISSIRQC_BIT (14) + #define INT_MISSIRQC_BITS (1) + /* INT_MISSIRQB field */ + #define INT_MISSIRQB (0x00002000u) + #define INT_MISSIRQB_MASK (0x00002000u) + #define INT_MISSIRQB_BIT (13) + #define INT_MISSIRQB_BITS (1) + /* INT_MISSIRQA field */ + #define INT_MISSIRQA (0x00001000u) + #define INT_MISSIRQA_MASK (0x00001000u) + #define INT_MISSIRQA_BIT (12) + #define INT_MISSIRQA_BITS (1) + /* INT_MISSADC field */ + #define INT_MISSADC (0x00000800u) + #define INT_MISSADC_MASK (0x00000800u) + #define INT_MISSADC_BIT (11) + #define INT_MISSADC_BITS (1) + /* INT_MISSMACRX field */ + #define INT_MISSMACRX (0x00000400u) + #define INT_MISSMACRX_MASK (0x00000400u) + #define INT_MISSMACRX_BIT (10) + #define INT_MISSMACRX_BITS (1) + /* INT_MISSMACTX field */ + #define INT_MISSMACTX (0x00000200u) + #define INT_MISSMACTX_MASK (0x00000200u) + #define INT_MISSMACTX_BIT (9) + #define INT_MISSMACTX_BITS (1) + /* INT_MISSMACTMR field */ + #define INT_MISSMACTMR (0x00000100u) + #define INT_MISSMACTMR_MASK (0x00000100u) + #define INT_MISSMACTMR_BIT (8) + #define INT_MISSMACTMR_BITS (1) + /* INT_MISSSEC field */ + #define INT_MISSSEC (0x00000080u) + #define INT_MISSSEC_MASK (0x00000080u) + #define INT_MISSSEC_BIT (7) + #define INT_MISSSEC_BITS (1) + /* INT_MISSSC2 field */ + #define INT_MISSSC2 (0x00000040u) + #define INT_MISSSC2_MASK (0x00000040u) + #define INT_MISSSC2_BIT (6) + #define INT_MISSSC2_BITS (1) + /* INT_MISSSC1 field */ + #define INT_MISSSC1 (0x00000020u) + #define INT_MISSSC1_MASK (0x00000020u) + #define INT_MISSSC1_BIT (5) + #define INT_MISSSC1_BITS (1) + /* INT_MISSSLEEP field */ + #define INT_MISSSLEEP (0x00000010u) + #define INT_MISSSLEEP_MASK (0x00000010u) + #define INT_MISSSLEEP_BIT (4) + #define INT_MISSSLEEP_BITS (1) + /* INT_MISSBB field */ + #define INT_MISSBB (0x00000008u) + #define INT_MISSBB_MASK (0x00000008u) + #define INT_MISSBB_BIT (3) + #define INT_MISSBB_BITS (1) + /* INT_MISSMGMT field */ + #define INT_MISSMGMT (0x00000004u) + #define INT_MISSMGMT_MASK (0x00000004u) + #define INT_MISSMGMT_BIT (2) + #define INT_MISSMGMT_BITS (1) + +#define INT_TIM1CFG *((volatile uint32_t *)0x4000A840u) +#define INT_TIM1CFG_REG *((volatile uint32_t *)0x4000A840u) +#define INT_TIM1CFG_ADDR (0x4000A840u) +#define INT_TIM1CFG_RESET (0x00000000u) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_TIM2CFG *((volatile uint32_t *)0x4000A844u) +#define INT_TIM2CFG_REG *((volatile uint32_t *)0x4000A844u) +#define INT_TIM2CFG_ADDR (0x4000A844u) +#define INT_TIM2CFG_RESET (0x00000000u) + /* INT_TIMTIF field */ + #define INT_TIMTIF (0x00000040u) + #define INT_TIMTIF_MASK (0x00000040u) + #define INT_TIMTIF_BIT (6) + #define INT_TIMTIF_BITS (1) + /* INT_TIMCC4IF field */ + #define INT_TIMCC4IF (0x00000010u) + #define INT_TIMCC4IF_MASK (0x00000010u) + #define INT_TIMCC4IF_BIT (4) + #define INT_TIMCC4IF_BITS (1) + /* INT_TIMCC3IF field */ + #define INT_TIMCC3IF (0x00000008u) + #define INT_TIMCC3IF_MASK (0x00000008u) + #define INT_TIMCC3IF_BIT (3) + #define INT_TIMCC3IF_BITS (1) + /* INT_TIMCC2IF field */ + #define INT_TIMCC2IF (0x00000004u) + #define INT_TIMCC2IF_MASK (0x00000004u) + #define INT_TIMCC2IF_BIT (2) + #define INT_TIMCC2IF_BITS (1) + /* INT_TIMCC1IF field */ + #define INT_TIMCC1IF (0x00000002u) + #define INT_TIMCC1IF_MASK (0x00000002u) + #define INT_TIMCC1IF_BIT (1) + #define INT_TIMCC1IF_BITS (1) + /* INT_TIMUIF field */ + #define INT_TIMUIF (0x00000001u) + #define INT_TIMUIF_MASK (0x00000001u) + #define INT_TIMUIF_BIT (0) + #define INT_TIMUIF_BITS (1) + +#define INT_SC1CFG *((volatile uint32_t *)0x4000A848u) +#define INT_SC1CFG_REG *((volatile uint32_t *)0x4000A848u) +#define INT_SC1CFG_ADDR (0x4000A848u) +#define INT_SC1CFG_RESET (0x00000000u) + /* INT_SC1PARERR field */ + #define INT_SC1PARERR (0x00004000u) + #define INT_SC1PARERR_MASK (0x00004000u) + #define INT_SC1PARERR_BIT (14) + #define INT_SC1PARERR_BITS (1) + /* INT_SC1FRMERR field */ + #define INT_SC1FRMERR (0x00002000u) + #define INT_SC1FRMERR_MASK (0x00002000u) + #define INT_SC1FRMERR_BIT (13) + #define INT_SC1FRMERR_BITS (1) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_SC2CFG *((volatile uint32_t *)0x4000A84Cu) +#define INT_SC2CFG_REG *((volatile uint32_t *)0x4000A84Cu) +#define INT_SC2CFG_ADDR (0x4000A84Cu) +#define INT_SC2CFG_RESET (0x00000000u) + /* INT_SCTXULDB field */ + #define INT_SCTXULDB (0x00001000u) + #define INT_SCTXULDB_MASK (0x00001000u) + #define INT_SCTXULDB_BIT (12) + #define INT_SCTXULDB_BITS (1) + /* INT_SCTXULDA field */ + #define INT_SCTXULDA (0x00000800u) + #define INT_SCTXULDA_MASK (0x00000800u) + #define INT_SCTXULDA_BIT (11) + #define INT_SCTXULDA_BITS (1) + /* INT_SCRXULDB field */ + #define INT_SCRXULDB (0x00000400u) + #define INT_SCRXULDB_MASK (0x00000400u) + #define INT_SCRXULDB_BIT (10) + #define INT_SCRXULDB_BITS (1) + /* INT_SCRXULDA field */ + #define INT_SCRXULDA (0x00000200u) + #define INT_SCRXULDA_MASK (0x00000200u) + #define INT_SCRXULDA_BIT (9) + #define INT_SCRXULDA_BITS (1) + /* INT_SCNAK field */ + #define INT_SCNAK (0x00000100u) + #define INT_SCNAK_MASK (0x00000100u) + #define INT_SCNAK_BIT (8) + #define INT_SCNAK_BITS (1) + /* INT_SCCMDFIN field */ + #define INT_SCCMDFIN (0x00000080u) + #define INT_SCCMDFIN_MASK (0x00000080u) + #define INT_SCCMDFIN_BIT (7) + #define INT_SCCMDFIN_BITS (1) + /* INT_SCTXFIN field */ + #define INT_SCTXFIN (0x00000040u) + #define INT_SCTXFIN_MASK (0x00000040u) + #define INT_SCTXFIN_BIT (6) + #define INT_SCTXFIN_BITS (1) + /* INT_SCRXFIN field */ + #define INT_SCRXFIN (0x00000020u) + #define INT_SCRXFIN_MASK (0x00000020u) + #define INT_SCRXFIN_BIT (5) + #define INT_SCRXFIN_BITS (1) + /* INT_SCTXUND field */ + #define INT_SCTXUND (0x00000010u) + #define INT_SCTXUND_MASK (0x00000010u) + #define INT_SCTXUND_BIT (4) + #define INT_SCTXUND_BITS (1) + /* INT_SCRXOVF field */ + #define INT_SCRXOVF (0x00000008u) + #define INT_SCRXOVF_MASK (0x00000008u) + #define INT_SCRXOVF_BIT (3) + #define INT_SCRXOVF_BITS (1) + /* INT_SCTXIDLE field */ + #define INT_SCTXIDLE (0x00000004u) + #define INT_SCTXIDLE_MASK (0x00000004u) + #define INT_SCTXIDLE_BIT (2) + #define INT_SCTXIDLE_BITS (1) + /* INT_SCTXFREE field */ + #define INT_SCTXFREE (0x00000002u) + #define INT_SCTXFREE_MASK (0x00000002u) + #define INT_SCTXFREE_BIT (1) + #define INT_SCTXFREE_BITS (1) + /* INT_SCRXVAL field */ + #define INT_SCRXVAL (0x00000001u) + #define INT_SCRXVAL_MASK (0x00000001u) + #define INT_SCRXVAL_BIT (0) + #define INT_SCRXVAL_BITS (1) + +#define INT_ADCCFG *((volatile uint32_t *)0x4000A850u) +#define INT_ADCCFG_REG *((volatile uint32_t *)0x4000A850u) +#define INT_ADCCFG_ADDR (0x4000A850u) +#define INT_ADCCFG_RESET (0x00000000u) + /* INT_ADCOVF field */ + #define INT_ADCOVF (0x00000010u) + #define INT_ADCOVF_MASK (0x00000010u) + #define INT_ADCOVF_BIT (4) + #define INT_ADCOVF_BITS (1) + /* INT_ADCSAT field */ + #define INT_ADCSAT (0x00000008u) + #define INT_ADCSAT_MASK (0x00000008u) + #define INT_ADCSAT_BIT (3) + #define INT_ADCSAT_BITS (1) + /* INT_ADCULDFULL field */ + #define INT_ADCULDFULL (0x00000004u) + #define INT_ADCULDFULL_MASK (0x00000004u) + #define INT_ADCULDFULL_BIT (2) + #define INT_ADCULDFULL_BITS (1) + /* INT_ADCULDHALF field */ + #define INT_ADCULDHALF (0x00000002u) + #define INT_ADCULDHALF_MASK (0x00000002u) + #define INT_ADCULDHALF_BIT (1) + #define INT_ADCULDHALF_BITS (1) + /* INT_ADCCFGRSVD field */ + #define INT_ADCCFGRSVD (0x00000001u) + #define INT_ADCCFGRSVD_MASK (0x00000001u) + #define INT_ADCCFGRSVD_BIT (0) + #define INT_ADCCFGRSVD_BITS (1) + +#define SC1_INTMODE *((volatile uint32_t *)0x4000A854u) +#define SC1_INTMODE_REG *((volatile uint32_t *)0x4000A854u) +#define SC1_INTMODE_ADDR (0x4000A854u) +#define SC1_INTMODE_RESET (0x00000000u) + /* SC_TXIDLELEVEL field */ + #define SC_TXIDLELEVEL (0x00000004u) + #define SC_TXIDLELEVEL_MASK (0x00000004u) + #define SC_TXIDLELEVEL_BIT (2) + #define SC_TXIDLELEVEL_BITS (1) + /* SC_TXFREELEVEL field */ + #define SC_TXFREELEVEL (0x00000002u) + #define SC_TXFREELEVEL_MASK (0x00000002u) + #define SC_TXFREELEVEL_BIT (1) + #define SC_TXFREELEVEL_BITS (1) + /* SC_RXVALLEVEL field */ + #define SC_RXVALLEVEL (0x00000001u) + #define SC_RXVALLEVEL_MASK (0x00000001u) + #define SC_RXVALLEVEL_BIT (0) + #define SC_RXVALLEVEL_BITS (1) + +#define SC2_INTMODE *((volatile uint32_t *)0x4000A858u) +#define SC2_INTMODE_REG *((volatile uint32_t *)0x4000A858u) +#define SC2_INTMODE_ADDR (0x4000A858u) +#define SC2_INTMODE_RESET (0x00000000u) + /* SC_TXIDLELEVEL field */ + #define SC_TXIDLELEVEL (0x00000004u) + #define SC_TXIDLELEVEL_MASK (0x00000004u) + #define SC_TXIDLELEVEL_BIT (2) + #define SC_TXIDLELEVEL_BITS (1) + /* SC_TXFREELEVEL field */ + #define SC_TXFREELEVEL (0x00000002u) + #define SC_TXFREELEVEL_MASK (0x00000002u) + #define SC_TXFREELEVEL_BIT (1) + #define SC_TXFREELEVEL_BITS (1) + /* SC_RXVALLEVEL field */ + #define SC_RXVALLEVEL (0x00000001u) + #define SC_RXVALLEVEL_MASK (0x00000001u) + #define SC_RXVALLEVEL_BIT (0) + #define SC_RXVALLEVEL_BITS (1) + +#define GPIO_INTCFGA *((volatile uint32_t *)0x4000A860u) +#define GPIO_INTCFGA_REG *((volatile uint32_t *)0x4000A860u) +#define GPIO_INTCFGA_ADDR (0x4000A860u) +#define GPIO_INTCFGA_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +#define GPIO_INTCFGB *((volatile uint32_t *)0x4000A864u) +#define GPIO_INTCFGB_REG *((volatile uint32_t *)0x4000A864u) +#define GPIO_INTCFGB_ADDR (0x4000A864u) +#define GPIO_INTCFGB_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +#define GPIO_INTCFGC *((volatile uint32_t *)0x4000A868u) +#define GPIO_INTCFGC_REG *((volatile uint32_t *)0x4000A868u) +#define GPIO_INTCFGC_ADDR (0x4000A868u) +#define GPIO_INTCFGC_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +#define GPIO_INTCFGD *((volatile uint32_t *)0x4000A86Cu) +#define GPIO_INTCFGD_REG *((volatile uint32_t *)0x4000A86Cu) +#define GPIO_INTCFGD_ADDR (0x4000A86Cu) +#define GPIO_INTCFGD_RESET (0x00000000u) + /* GPIO_INTFILT field */ + #define GPIO_INTFILT (0x00000100u) + #define GPIO_INTFILT_MASK (0x00000100u) + #define GPIO_INTFILT_BIT (8) + #define GPIO_INTFILT_BITS (1) + /* GPIO_INTMOD field */ + #define GPIO_INTMOD (0x000000E0u) + #define GPIO_INTMOD_MASK (0x000000E0u) + #define GPIO_INTMOD_BIT (5) + #define GPIO_INTMOD_BITS (3) + +/* GPIO block */ +#define BLOCK_GPIO_BASE (0x4000B000u) +#define BLOCK_GPIO_END (0x4000BC1Cu) +#define BLOCK_GPIO_SIZE (BLOCK_GPIO_END - BLOCK_GPIO_BASE + 1) + +#define GPIO_PACFGL *((volatile uint32_t *)0x4000B000u) +#define GPIO_PACFGL_REG *((volatile uint32_t *)0x4000B000u) +#define GPIO_PACFGL_ADDR (0x4000B000u) +#define GPIO_PACFGL_RESET (0x00004444u) + /* PA3_CFG field */ + #define PA3_CFG (0x0000F000u) + #define PA3_CFG_MASK (0x0000F000u) + #define PA3_CFG_BIT (12) + #define PA3_CFG_BITS (4) + /* PA2_CFG field */ + #define PA2_CFG (0x00000F00u) + #define PA2_CFG_MASK (0x00000F00u) + #define PA2_CFG_BIT (8) + #define PA2_CFG_BITS (4) + /* PA1_CFG field */ + #define PA1_CFG (0x000000F0u) + #define PA1_CFG_MASK (0x000000F0u) + #define PA1_CFG_BIT (4) + #define PA1_CFG_BITS (4) + /* PA0_CFG field */ + #define PA0_CFG (0x0000000Fu) + #define PA0_CFG_MASK (0x0000000Fu) + #define PA0_CFG_BIT (0) + #define PA0_CFG_BITS (4) + /* GPIO_PxCFGx Bit Field Values */ + #define GPIOCFG_OUT (0x1u) + #define GPIOCFG_OUT_OD (0x5u) + #define GPIOCFG_OUT_ALT (0x9u) + #define GPIOCFG_OUT_ALT_OD (0xDu) + #define GPIOCFG_ANALOG (0x0u) + #define GPIOCFG_IN (0x4u) + #define GPIOCFG_IN_PUD (0x8u) + +#define GPIO_PACFGH *((volatile uint32_t *)0x4000B004u) +#define GPIO_PACFGH_REG *((volatile uint32_t *)0x4000B004u) +#define GPIO_PACFGH_ADDR (0x4000B004u) +#define GPIO_PACFGH_RESET (0x00004444u) + /* PA7_CFG field */ + #define PA7_CFG (0x0000F000u) + #define PA7_CFG_MASK (0x0000F000u) + #define PA7_CFG_BIT (12) + #define PA7_CFG_BITS (4) + /* PA6_CFG field */ + #define PA6_CFG (0x00000F00u) + #define PA6_CFG_MASK (0x00000F00u) + #define PA6_CFG_BIT (8) + #define PA6_CFG_BITS (4) + /* PA5_CFG field */ + #define PA5_CFG (0x000000F0u) + #define PA5_CFG_MASK (0x000000F0u) + #define PA5_CFG_BIT (4) + #define PA5_CFG_BITS (4) + /* PA4_CFG field */ + #define PA4_CFG (0x0000000Fu) + #define PA4_CFG_MASK (0x0000000Fu) + #define PA4_CFG_BIT (0) + #define PA4_CFG_BITS (4) + +#define GPIO_PAIN *((volatile uint32_t *)0x4000B008u) +#define GPIO_PAIN_REG *((volatile uint32_t *)0x4000B008u) +#define GPIO_PAIN_ADDR (0x4000B008u) +#define GPIO_PAIN_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PAOUT *((volatile uint32_t *)0x4000B00Cu) +#define GPIO_PAOUT_REG *((volatile uint32_t *)0x4000B00Cu) +#define GPIO_PAOUT_ADDR (0x4000B00Cu) +#define GPIO_PAOUT_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + /* GPIO_PxOUT Bit Field Values */ + #define GPIOOUT_PULLUP (0x1u) + #define GPIOOUT_PULLDOWN (0x0u) + +#define GPIO_PASET *((volatile uint32_t *)0x4000B010u) +#define GPIO_PASET_REG *((volatile uint32_t *)0x4000B010u) +#define GPIO_PASET_ADDR (0x4000B010u) +#define GPIO_PASET_RESET (0x00000000u) + /* GPIO_PXSETRSVD field */ + #define GPIO_PXSETRSVD (0x0000FF00u) + #define GPIO_PXSETRSVD_MASK (0x0000FF00u) + #define GPIO_PXSETRSVD_BIT (8) + #define GPIO_PXSETRSVD_BITS (8) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PACLR *((volatile uint32_t *)0x4000B014u) +#define GPIO_PACLR_REG *((volatile uint32_t *)0x4000B014u) +#define GPIO_PACLR_ADDR (0x4000B014u) +#define GPIO_PACLR_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PBCFGL *((volatile uint32_t *)0x4000B400u) +#define GPIO_PBCFGL_REG *((volatile uint32_t *)0x4000B400u) +#define GPIO_PBCFGL_ADDR (0x4000B400u) +#define GPIO_PBCFGL_RESET (0x00004444u) + /* PB3_CFG field */ + #define PB3_CFG (0x0000F000u) + #define PB3_CFG_MASK (0x0000F000u) + #define PB3_CFG_BIT (12) + #define PB3_CFG_BITS (4) + /* PB2_CFG field */ + #define PB2_CFG (0x00000F00u) + #define PB2_CFG_MASK (0x00000F00u) + #define PB2_CFG_BIT (8) + #define PB2_CFG_BITS (4) + /* PB1_CFG field */ + #define PB1_CFG (0x000000F0u) + #define PB1_CFG_MASK (0x000000F0u) + #define PB1_CFG_BIT (4) + #define PB1_CFG_BITS (4) + /* PB0_CFG field */ + #define PB0_CFG (0x0000000Fu) + #define PB0_CFG_MASK (0x0000000Fu) + #define PB0_CFG_BIT (0) + #define PB0_CFG_BITS (4) + +#define GPIO_PBCFGH *((volatile uint32_t *)0x4000B404u) +#define GPIO_PBCFGH_REG *((volatile uint32_t *)0x4000B404u) +#define GPIO_PBCFGH_ADDR (0x4000B404u) +#define GPIO_PBCFGH_RESET (0x00004444u) + /* PB7_CFG field */ + #define PB7_CFG (0x0000F000u) + #define PB7_CFG_MASK (0x0000F000u) + #define PB7_CFG_BIT (12) + #define PB7_CFG_BITS (4) + /* PB6_CFG field */ + #define PB6_CFG (0x00000F00u) + #define PB6_CFG_MASK (0x00000F00u) + #define PB6_CFG_BIT (8) + #define PB6_CFG_BITS (4) + /* PB5_CFG field */ + #define PB5_CFG (0x000000F0u) + #define PB5_CFG_MASK (0x000000F0u) + #define PB5_CFG_BIT (4) + #define PB5_CFG_BITS (4) + /* PB4_CFG field */ + #define PB4_CFG (0x0000000Fu) + #define PB4_CFG_MASK (0x0000000Fu) + #define PB4_CFG_BIT (0) + #define PB4_CFG_BITS (4) + +#define GPIO_PBIN *((volatile uint32_t *)0x4000B408u) +#define GPIO_PBIN_REG *((volatile uint32_t *)0x4000B408u) +#define GPIO_PBIN_ADDR (0x4000B408u) +#define GPIO_PBIN_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PBOUT *((volatile uint32_t *)0x4000B40Cu) +#define GPIO_PBOUT_REG *((volatile uint32_t *)0x4000B40Cu) +#define GPIO_PBOUT_ADDR (0x4000B40Cu) +#define GPIO_PBOUT_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PBSET *((volatile uint32_t *)0x4000B410u) +#define GPIO_PBSET_REG *((volatile uint32_t *)0x4000B410u) +#define GPIO_PBSET_ADDR (0x4000B410u) +#define GPIO_PBSET_RESET (0x00000000u) + /* GPIO_PXSETRSVD field */ + #define GPIO_PXSETRSVD (0x0000FF00u) + #define GPIO_PXSETRSVD_MASK (0x0000FF00u) + #define GPIO_PXSETRSVD_BIT (8) + #define GPIO_PXSETRSVD_BITS (8) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PBCLR *((volatile uint32_t *)0x4000B414u) +#define GPIO_PBCLR_REG *((volatile uint32_t *)0x4000B414u) +#define GPIO_PBCLR_ADDR (0x4000B414u) +#define GPIO_PBCLR_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PCCFGL *((volatile uint32_t *)0x4000B800u) +#define GPIO_PCCFGL_REG *((volatile uint32_t *)0x4000B800u) +#define GPIO_PCCFGL_ADDR (0x4000B800u) +#define GPIO_PCCFGL_RESET (0x00004444u) + /* PC3_CFG field */ + #define PC3_CFG (0x0000F000u) + #define PC3_CFG_MASK (0x0000F000u) + #define PC3_CFG_BIT (12) + #define PC3_CFG_BITS (4) + /* PC2_CFG field */ + #define PC2_CFG (0x00000F00u) + #define PC2_CFG_MASK (0x00000F00u) + #define PC2_CFG_BIT (8) + #define PC2_CFG_BITS (4) + /* PC1_CFG field */ + #define PC1_CFG (0x000000F0u) + #define PC1_CFG_MASK (0x000000F0u) + #define PC1_CFG_BIT (4) + #define PC1_CFG_BITS (4) + /* PC0_CFG field */ + #define PC0_CFG (0x0000000Fu) + #define PC0_CFG_MASK (0x0000000Fu) + #define PC0_CFG_BIT (0) + #define PC0_CFG_BITS (4) + +#define GPIO_PCCFGH *((volatile uint32_t *)0x4000B804u) +#define GPIO_PCCFGH_REG *((volatile uint32_t *)0x4000B804u) +#define GPIO_PCCFGH_ADDR (0x4000B804u) +#define GPIO_PCCFGH_RESET (0x00004444u) + /* PC7_CFG field */ + #define PC7_CFG (0x0000F000u) + #define PC7_CFG_MASK (0x0000F000u) + #define PC7_CFG_BIT (12) + #define PC7_CFG_BITS (4) + /* PC6_CFG field */ + #define PC6_CFG (0x00000F00u) + #define PC6_CFG_MASK (0x00000F00u) + #define PC6_CFG_BIT (8) + #define PC6_CFG_BITS (4) + /* PC5_CFG field */ + #define PC5_CFG (0x000000F0u) + #define PC5_CFG_MASK (0x000000F0u) + #define PC5_CFG_BIT (4) + #define PC5_CFG_BITS (4) + /* PC4_CFG field */ + #define PC4_CFG (0x0000000Fu) + #define PC4_CFG_MASK (0x0000000Fu) + #define PC4_CFG_BIT (0) + #define PC4_CFG_BITS (4) + +#define GPIO_PCIN *((volatile uint32_t *)0x4000B808u) +#define GPIO_PCIN_REG *((volatile uint32_t *)0x4000B808u) +#define GPIO_PCIN_ADDR (0x4000B808u) +#define GPIO_PCIN_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_PCOUT *((volatile uint32_t *)0x4000B80Cu) +#define GPIO_PCOUT_REG *((volatile uint32_t *)0x4000B80Cu) +#define GPIO_PCOUT_ADDR (0x4000B80Cu) +#define GPIO_PCOUT_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_PCSET *((volatile uint32_t *)0x4000B810u) +#define GPIO_PCSET_REG *((volatile uint32_t *)0x4000B810u) +#define GPIO_PCSET_ADDR (0x4000B810u) +#define GPIO_PCSET_RESET (0x00000000u) + /* GPIO_PXSETRSVD field */ + #define GPIO_PXSETRSVD (0x0000FF00u) + #define GPIO_PXSETRSVD_MASK (0x0000FF00u) + #define GPIO_PXSETRSVD_BIT (8) + #define GPIO_PXSETRSVD_BITS (8) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_PCCLR *((volatile uint32_t *)0x4000B814u) +#define GPIO_PCCLR_REG *((volatile uint32_t *)0x4000B814u) +#define GPIO_PCCLR_ADDR (0x4000B814u) +#define GPIO_PCCLR_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_DBGCFG *((volatile uint32_t *)0x4000BC00u) +#define GPIO_DBGCFG_REG *((volatile uint32_t *)0x4000BC00u) +#define GPIO_DBGCFG_ADDR (0x4000BC00u) +#define GPIO_DBGCFG_RESET (0x00000010u) + /* GPIO_DEBUGDIS field */ + #define GPIO_DEBUGDIS (0x00000020u) + #define GPIO_DEBUGDIS_MASK (0x00000020u) + #define GPIO_DEBUGDIS_BIT (5) + #define GPIO_DEBUGDIS_BITS (1) + /* GPIO_EXTREGEN field */ + #define GPIO_EXTREGEN (0x00000010u) + #define GPIO_EXTREGEN_MASK (0x00000010u) + #define GPIO_EXTREGEN_BIT (4) + #define GPIO_EXTREGEN_BITS (1) + /* GPIO_DBGCFGRSVD field */ + #define GPIO_DBGCFGRSVD (0x00000008u) + #define GPIO_DBGCFGRSVD_MASK (0x00000008u) + #define GPIO_DBGCFGRSVD_BIT (3) + #define GPIO_DBGCFGRSVD_BITS (1) + +#define GPIO_DBGSTAT *((volatile uint32_t *)0x4000BC04u) +#define GPIO_DBGSTAT_REG *((volatile uint32_t *)0x4000BC04u) +#define GPIO_DBGSTAT_ADDR (0x4000BC04u) +#define GPIO_DBGSTAT_RESET (0x00000000u) + /* GPIO_BOOTMODE field */ + #define GPIO_BOOTMODE (0x00000008u) + #define GPIO_BOOTMODE_MASK (0x00000008u) + #define GPIO_BOOTMODE_BIT (3) + #define GPIO_BOOTMODE_BITS (1) + /* GPIO_FORCEDBG field */ + #define GPIO_FORCEDBG (0x00000002u) + #define GPIO_FORCEDBG_MASK (0x00000002u) + #define GPIO_FORCEDBG_BIT (1) + #define GPIO_FORCEDBG_BITS (1) + /* GPIO_SWEN field */ + #define GPIO_SWEN (0x00000001u) + #define GPIO_SWEN_MASK (0x00000001u) + #define GPIO_SWEN_BIT (0) + #define GPIO_SWEN_BITS (1) + +#define GPIO_PAWAKE *((volatile uint32_t *)0x4000BC08u) +#define GPIO_PAWAKE_REG *((volatile uint32_t *)0x4000BC08u) +#define GPIO_PAWAKE_ADDR (0x4000BC08u) +#define GPIO_PAWAKE_RESET (0x00000000u) + /* PA7 field */ + #define PA7 (0x00000080u) + #define PA7_MASK (0x00000080u) + #define PA7_BIT (7) + #define PA7_BITS (1) + /* PA6 field */ + #define PA6 (0x00000040u) + #define PA6_MASK (0x00000040u) + #define PA6_BIT (6) + #define PA6_BITS (1) + /* PA5 field */ + #define PA5 (0x00000020u) + #define PA5_MASK (0x00000020u) + #define PA5_BIT (5) + #define PA5_BITS (1) + /* PA4 field */ + #define PA4 (0x00000010u) + #define PA4_MASK (0x00000010u) + #define PA4_BIT (4) + #define PA4_BITS (1) + /* PA3 field */ + #define PA3 (0x00000008u) + #define PA3_MASK (0x00000008u) + #define PA3_BIT (3) + #define PA3_BITS (1) + /* PA2 field */ + #define PA2 (0x00000004u) + #define PA2_MASK (0x00000004u) + #define PA2_BIT (2) + #define PA2_BITS (1) + /* PA1 field */ + #define PA1 (0x00000002u) + #define PA1_MASK (0x00000002u) + #define PA1_BIT (1) + #define PA1_BITS (1) + /* PA0 field */ + #define PA0 (0x00000001u) + #define PA0_MASK (0x00000001u) + #define PA0_BIT (0) + #define PA0_BITS (1) + +#define GPIO_PBWAKE *((volatile uint32_t *)0x4000BC0Cu) +#define GPIO_PBWAKE_REG *((volatile uint32_t *)0x4000BC0Cu) +#define GPIO_PBWAKE_ADDR (0x4000BC0Cu) +#define GPIO_PBWAKE_RESET (0x00000000u) + /* PB7 field */ + #define PB7 (0x00000080u) + #define PB7_MASK (0x00000080u) + #define PB7_BIT (7) + #define PB7_BITS (1) + /* PB6 field */ + #define PB6 (0x00000040u) + #define PB6_MASK (0x00000040u) + #define PB6_BIT (6) + #define PB6_BITS (1) + /* PB5 field */ + #define PB5 (0x00000020u) + #define PB5_MASK (0x00000020u) + #define PB5_BIT (5) + #define PB5_BITS (1) + /* PB4 field */ + #define PB4 (0x00000010u) + #define PB4_MASK (0x00000010u) + #define PB4_BIT (4) + #define PB4_BITS (1) + /* PB3 field */ + #define PB3 (0x00000008u) + #define PB3_MASK (0x00000008u) + #define PB3_BIT (3) + #define PB3_BITS (1) + /* PB2 field */ + #define PB2 (0x00000004u) + #define PB2_MASK (0x00000004u) + #define PB2_BIT (2) + #define PB2_BITS (1) + /* PB1 field */ + #define PB1 (0x00000002u) + #define PB1_MASK (0x00000002u) + #define PB1_BIT (1) + #define PB1_BITS (1) + /* PB0 field */ + #define PB0 (0x00000001u) + #define PB0_MASK (0x00000001u) + #define PB0_BIT (0) + #define PB0_BITS (1) + +#define GPIO_PCWAKE *((volatile uint32_t *)0x4000BC10u) +#define GPIO_PCWAKE_REG *((volatile uint32_t *)0x4000BC10u) +#define GPIO_PCWAKE_ADDR (0x4000BC10u) +#define GPIO_PCWAKE_RESET (0x00000000u) + /* PC7 field */ + #define PC7 (0x00000080u) + #define PC7_MASK (0x00000080u) + #define PC7_BIT (7) + #define PC7_BITS (1) + /* PC6 field */ + #define PC6 (0x00000040u) + #define PC6_MASK (0x00000040u) + #define PC6_BIT (6) + #define PC6_BITS (1) + /* PC5 field */ + #define PC5 (0x00000020u) + #define PC5_MASK (0x00000020u) + #define PC5_BIT (5) + #define PC5_BITS (1) + /* PC4 field */ + #define PC4 (0x00000010u) + #define PC4_MASK (0x00000010u) + #define PC4_BIT (4) + #define PC4_BITS (1) + /* PC3 field */ + #define PC3 (0x00000008u) + #define PC3_MASK (0x00000008u) + #define PC3_BIT (3) + #define PC3_BITS (1) + /* PC2 field */ + #define PC2 (0x00000004u) + #define PC2_MASK (0x00000004u) + #define PC2_BIT (2) + #define PC2_BITS (1) + /* PC1 field */ + #define PC1 (0x00000002u) + #define PC1_MASK (0x00000002u) + #define PC1_BIT (1) + #define PC1_BITS (1) + /* PC0 field */ + #define PC0 (0x00000001u) + #define PC0_MASK (0x00000001u) + #define PC0_BIT (0) + #define PC0_BITS (1) + +#define GPIO_IRQCSEL *((volatile uint32_t *)0x4000BC14u) +#define GPIO_IRQCSEL_REG *((volatile uint32_t *)0x4000BC14u) +#define GPIO_IRQCSEL_ADDR (0x4000BC14u) +#define GPIO_IRQCSEL_RESET (0x0000000Fu) + /* SEL_GPIO field */ + #define SEL_GPIO (0x0000001Fu) + #define SEL_GPIO_MASK (0x0000001Fu) + #define SEL_GPIO_BIT (0) + #define SEL_GPIO_BITS (5) + +#define GPIO_IRQDSEL *((volatile uint32_t *)0x4000BC18u) +#define GPIO_IRQDSEL_REG *((volatile uint32_t *)0x4000BC18u) +#define GPIO_IRQDSEL_ADDR (0x4000BC18u) +#define GPIO_IRQDSEL_RESET (0x00000010u) + /* SEL_GPIO field */ + #define SEL_GPIO (0x0000001Fu) + #define SEL_GPIO_MASK (0x0000001Fu) + #define SEL_GPIO_BIT (0) + #define SEL_GPIO_BITS (5) + +#define GPIO_WAKEFILT *((volatile uint32_t *)0x4000BC1Cu) +#define GPIO_WAKEFILT_REG *((volatile uint32_t *)0x4000BC1Cu) +#define GPIO_WAKEFILT_ADDR (0x4000BC1Cu) +#define GPIO_WAKEFILT_RESET (0x00000000u) + /* IRQD_WAKE_FILTER field */ + #define IRQD_WAKE_FILTER (0x00000008u) + #define IRQD_WAKE_FILTER_MASK (0x00000008u) + #define IRQD_WAKE_FILTER_BIT (3) + #define IRQD_WAKE_FILTER_BITS (1) + /* SC2_WAKE_FILTER field */ + #define SC2_WAKE_FILTER (0x00000004u) + #define SC2_WAKE_FILTER_MASK (0x00000004u) + #define SC2_WAKE_FILTER_BIT (2) + #define SC2_WAKE_FILTER_BITS (1) + /* SC1_WAKE_FILTER field */ + #define SC1_WAKE_FILTER (0x00000002u) + #define SC1_WAKE_FILTER_MASK (0x00000002u) + #define SC1_WAKE_FILTER_BIT (1) + #define SC1_WAKE_FILTER_BITS (1) + /* GPIO_WAKE_FILTER field */ + #define GPIO_WAKE_FILTER (0x00000001u) + #define GPIO_WAKE_FILTER_MASK (0x00000001u) + #define GPIO_WAKE_FILTER_BIT (0) + #define GPIO_WAKE_FILTER_BITS (1) + +/* SERIAL block */ +#define BLOCK_SERIAL_BASE (0x4000C000u) +#define BLOCK_SERIAL_END (0x4000C870u) +#define BLOCK_SERIAL_SIZE (BLOCK_SERIAL_END - BLOCK_SERIAL_BASE + 1) + +#define SC2_RXBEGA *((volatile uint32_t *)0x4000C000u) +#define SC2_RXBEGA_REG *((volatile uint32_t *)0x4000C000u) +#define SC2_RXBEGA_ADDR (0x4000C000u) +#define SC2_RXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXBEGA_FIXED (0xFFFFE000u) + #define SC2_RXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC2_RXBEGA_FIXED_BIT (13) + #define SC2_RXBEGA_FIXED_BITS (19) + /* SC_RXBEGA field */ + #define SC_RXBEGA (0x00001FFFu) + #define SC_RXBEGA_MASK (0x00001FFFu) + #define SC_RXBEGA_BIT (0) + #define SC_RXBEGA_BITS (13) + +#define SC2_RXENDA *((volatile uint32_t *)0x4000C004u) +#define SC2_RXENDA_REG *((volatile uint32_t *)0x4000C004u) +#define SC2_RXENDA_ADDR (0x4000C004u) +#define SC2_RXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXENDA_FIXED (0xFFFFE000u) + #define SC2_RXENDA_FIXED_MASK (0xFFFFE000u) + #define SC2_RXENDA_FIXED_BIT (13) + #define SC2_RXENDA_FIXED_BITS (19) + /* SC_RXENDA field */ + #define SC_RXENDA (0x00001FFFu) + #define SC_RXENDA_MASK (0x00001FFFu) + #define SC_RXENDA_BIT (0) + #define SC_RXENDA_BITS (13) + +#define SC2_RXBEGB *((volatile uint32_t *)0x4000C008u) +#define SC2_RXBEGB_REG *((volatile uint32_t *)0x4000C008u) +#define SC2_RXBEGB_ADDR (0x4000C008u) +#define SC2_RXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXBEGB_FIXED (0xFFFFE000u) + #define SC2_RXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC2_RXBEGB_FIXED_BIT (13) + #define SC2_RXBEGB_FIXED_BITS (19) + /* SC_RXBEGB field */ + #define SC_RXBEGB (0x00001FFFu) + #define SC_RXBEGB_MASK (0x00001FFFu) + #define SC_RXBEGB_BIT (0) + #define SC_RXBEGB_BITS (13) + +#define SC2_RXENDB *((volatile uint32_t *)0x4000C00Cu) +#define SC2_RXENDB_REG *((volatile uint32_t *)0x4000C00Cu) +#define SC2_RXENDB_ADDR (0x4000C00Cu) +#define SC2_RXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_RXENDB_FIXED (0xFFFFE000u) + #define SC2_RXENDB_FIXED_MASK (0xFFFFE000u) + #define SC2_RXENDB_FIXED_BIT (13) + #define SC2_RXENDB_FIXED_BITS (19) + /* SC_RXENDB field */ + #define SC_RXENDB (0x00001FFFu) + #define SC_RXENDB_MASK (0x00001FFFu) + #define SC_RXENDB_BIT (0) + #define SC_RXENDB_BITS (13) + +#define SC2_TXBEGA *((volatile uint32_t *)0x4000C010u) +#define SC2_TXBEGA_REG *((volatile uint32_t *)0x4000C010u) +#define SC2_TXBEGA_ADDR (0x4000C010u) +#define SC2_TXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXBEGA_FIXED (0xFFFFE000u) + #define SC2_TXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC2_TXBEGA_FIXED_BIT (13) + #define SC2_TXBEGA_FIXED_BITS (19) + /* SC_TXBEGA field */ + #define SC_TXBEGA (0x00001FFFu) + #define SC_TXBEGA_MASK (0x00001FFFu) + #define SC_TXBEGA_BIT (0) + #define SC_TXBEGA_BITS (13) + +#define SC2_TXENDA *((volatile uint32_t *)0x4000C014u) +#define SC2_TXENDA_REG *((volatile uint32_t *)0x4000C014u) +#define SC2_TXENDA_ADDR (0x4000C014u) +#define SC2_TXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXENDA_FIXED (0xFFFFE000u) + #define SC2_TXENDA_FIXED_MASK (0xFFFFE000u) + #define SC2_TXENDA_FIXED_BIT (13) + #define SC2_TXENDA_FIXED_BITS (19) + /* SC_TXENDA field */ + #define SC_TXENDA (0x00001FFFu) + #define SC_TXENDA_MASK (0x00001FFFu) + #define SC_TXENDA_BIT (0) + #define SC_TXENDA_BITS (13) + +#define SC2_TXBEGB *((volatile uint32_t *)0x4000C018u) +#define SC2_TXBEGB_REG *((volatile uint32_t *)0x4000C018u) +#define SC2_TXBEGB_ADDR (0x4000C018u) +#define SC2_TXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXBEGB_FIXED (0xFFFFE000u) + #define SC2_TXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC2_TXBEGB_FIXED_BIT (13) + #define SC2_TXBEGB_FIXED_BITS (19) + /* SC_TXBEGB field */ + #define SC_TXBEGB (0x00001FFFu) + #define SC_TXBEGB_MASK (0x00001FFFu) + #define SC_TXBEGB_BIT (0) + #define SC_TXBEGB_BITS (13) + +#define SC2_TXENDB *((volatile uint32_t *)0x4000C01Cu) +#define SC2_TXENDB_REG *((volatile uint32_t *)0x4000C01Cu) +#define SC2_TXENDB_ADDR (0x4000C01Cu) +#define SC2_TXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC2_TXENDB_FIXED (0xFFFFE000u) + #define SC2_TXENDB_FIXED_MASK (0xFFFFE000u) + #define SC2_TXENDB_FIXED_BIT (13) + #define SC2_TXENDB_FIXED_BITS (19) + /* SC_TXENDB field */ + #define SC_TXENDB (0x00001FFFu) + #define SC_TXENDB_MASK (0x00001FFFu) + #define SC_TXENDB_BIT (0) + #define SC_TXENDB_BITS (13) + +#define SC2_RXCNTA *((volatile uint32_t *)0x4000C020u) +#define SC2_RXCNTA_REG *((volatile uint32_t *)0x4000C020u) +#define SC2_RXCNTA_ADDR (0x4000C020u) +#define SC2_RXCNTA_RESET (0x00000000u) + /* SC_RXCNTA field */ + #define SC_RXCNTA (0x00001FFFu) + #define SC_RXCNTA_MASK (0x00001FFFu) + #define SC_RXCNTA_BIT (0) + #define SC_RXCNTA_BITS (13) + +#define SC2_RXCNTB *((volatile uint32_t *)0x4000C024u) +#define SC2_RXCNTB_REG *((volatile uint32_t *)0x4000C024u) +#define SC2_RXCNTB_ADDR (0x4000C024u) +#define SC2_RXCNTB_RESET (0x00000000u) + /* SC_RXCNTB field */ + #define SC_RXCNTB (0x00001FFFu) + #define SC_RXCNTB_MASK (0x00001FFFu) + #define SC_RXCNTB_BIT (0) + #define SC_RXCNTB_BITS (13) + +#define SC2_TXCNT *((volatile uint32_t *)0x4000C028u) +#define SC2_TXCNT_REG *((volatile uint32_t *)0x4000C028u) +#define SC2_TXCNT_ADDR (0x4000C028u) +#define SC2_TXCNT_RESET (0x00000000u) + /* SC_TXCNT field */ + #define SC_TXCNT (0x00001FFFu) + #define SC_TXCNT_MASK (0x00001FFFu) + #define SC_TXCNT_BIT (0) + #define SC_TXCNT_BITS (13) + +#define SC2_DMASTAT *((volatile uint32_t *)0x4000C02Cu) +#define SC2_DMASTAT_REG *((volatile uint32_t *)0x4000C02Cu) +#define SC2_DMASTAT_ADDR (0x4000C02Cu) +#define SC2_DMASTAT_RESET (0x00000000u) + /* SC_RXSSEL field */ + #define SC_RXSSEL (0x00001C00u) + #define SC_RXSSEL_MASK (0x00001C00u) + #define SC_RXSSEL_BIT (10) + #define SC_RXSSEL_BITS (3) + /* SC_RXOVFB field */ + #define SC_RXOVFB (0x00000020u) + #define SC_RXOVFB_MASK (0x00000020u) + #define SC_RXOVFB_BIT (5) + #define SC_RXOVFB_BITS (1) + /* SC_RXOVFA field */ + #define SC_RXOVFA (0x00000010u) + #define SC_RXOVFA_MASK (0x00000010u) + #define SC_RXOVFA_BIT (4) + #define SC_RXOVFA_BITS (1) + /* SC_TXACTB field */ + #define SC_TXACTB (0x00000008u) + #define SC_TXACTB_MASK (0x00000008u) + #define SC_TXACTB_BIT (3) + #define SC_TXACTB_BITS (1) + /* SC_TXACTA field */ + #define SC_TXACTA (0x00000004u) + #define SC_TXACTA_MASK (0x00000004u) + #define SC_TXACTA_BIT (2) + #define SC_TXACTA_BITS (1) + /* SC_RXACTB field */ + #define SC_RXACTB (0x00000002u) + #define SC_RXACTB_MASK (0x00000002u) + #define SC_RXACTB_BIT (1) + #define SC_RXACTB_BITS (1) + /* SC_RXACTA field */ + #define SC_RXACTA (0x00000001u) + #define SC_RXACTA_MASK (0x00000001u) + #define SC_RXACTA_BIT (0) + #define SC_RXACTA_BITS (1) + +#define SC2_DMACTRL *((volatile uint32_t *)0x4000C030u) +#define SC2_DMACTRL_REG *((volatile uint32_t *)0x4000C030u) +#define SC2_DMACTRL_ADDR (0x4000C030u) +#define SC2_DMACTRL_RESET (0x00000000u) + /* SC_TXDMARST field */ + #define SC_TXDMARST (0x00000020u) + #define SC_TXDMARST_MASK (0x00000020u) + #define SC_TXDMARST_BIT (5) + #define SC_TXDMARST_BITS (1) + /* SC_RXDMARST field */ + #define SC_RXDMARST (0x00000010u) + #define SC_RXDMARST_MASK (0x00000010u) + #define SC_RXDMARST_BIT (4) + #define SC_RXDMARST_BITS (1) + /* SC_TXLODB field */ + #define SC_TXLODB (0x00000008u) + #define SC_TXLODB_MASK (0x00000008u) + #define SC_TXLODB_BIT (3) + #define SC_TXLODB_BITS (1) + /* SC_TXLODA field */ + #define SC_TXLODA (0x00000004u) + #define SC_TXLODA_MASK (0x00000004u) + #define SC_TXLODA_BIT (2) + #define SC_TXLODA_BITS (1) + /* SC_RXLODB field */ + #define SC_RXLODB (0x00000002u) + #define SC_RXLODB_MASK (0x00000002u) + #define SC_RXLODB_BIT (1) + #define SC_RXLODB_BITS (1) + /* SC_RXLODA field */ + #define SC_RXLODA (0x00000001u) + #define SC_RXLODA_MASK (0x00000001u) + #define SC_RXLODA_BIT (0) + #define SC_RXLODA_BITS (1) + +#define SC2_RXERRA *((volatile uint32_t *)0x4000C034u) +#define SC2_RXERRA_REG *((volatile uint32_t *)0x4000C034u) +#define SC2_RXERRA_ADDR (0x4000C034u) +#define SC2_RXERRA_RESET (0x00000000u) + /* SC_RXERRA field */ + #define SC_RXERRA (0x00001FFFu) + #define SC_RXERRA_MASK (0x00001FFFu) + #define SC_RXERRA_BIT (0) + #define SC_RXERRA_BITS (13) + +#define SC2_RXERRB *((volatile uint32_t *)0x4000C038u) +#define SC2_RXERRB_REG *((volatile uint32_t *)0x4000C038u) +#define SC2_RXERRB_ADDR (0x4000C038u) +#define SC2_RXERRB_RESET (0x00000000u) + /* SC_RXERRB field */ + #define SC_RXERRB (0x00001FFFu) + #define SC_RXERRB_MASK (0x00001FFFu) + #define SC_RXERRB_BIT (0) + #define SC_RXERRB_BITS (13) + +#define SC2_DATA *((volatile uint32_t *)0x4000C03Cu) +#define SC2_DATA_REG *((volatile uint32_t *)0x4000C03Cu) +#define SC2_DATA_ADDR (0x4000C03Cu) +#define SC2_DATA_RESET (0x00000000u) + /* SC_DATA field */ + #define SC_DATA (0x000000FFu) + #define SC_DATA_MASK (0x000000FFu) + #define SC_DATA_BIT (0) + #define SC_DATA_BITS (8) + +#define SC2_SPISTAT *((volatile uint32_t *)0x4000C040u) +#define SC2_SPISTAT_REG *((volatile uint32_t *)0x4000C040u) +#define SC2_SPISTAT_ADDR (0x4000C040u) +#define SC2_SPISTAT_RESET (0x00000000u) + /* SC_SPITXIDLE field */ + #define SC_SPITXIDLE (0x00000008u) + #define SC_SPITXIDLE_MASK (0x00000008u) + #define SC_SPITXIDLE_BIT (3) + #define SC_SPITXIDLE_BITS (1) + /* SC_SPITXFREE field */ + #define SC_SPITXFREE (0x00000004u) + #define SC_SPITXFREE_MASK (0x00000004u) + #define SC_SPITXFREE_BIT (2) + #define SC_SPITXFREE_BITS (1) + /* SC_SPIRXVAL field */ + #define SC_SPIRXVAL (0x00000002u) + #define SC_SPIRXVAL_MASK (0x00000002u) + #define SC_SPIRXVAL_BIT (1) + #define SC_SPIRXVAL_BITS (1) + /* SC_SPIRXOVF field */ + #define SC_SPIRXOVF (0x00000001u) + #define SC_SPIRXOVF_MASK (0x00000001u) + #define SC_SPIRXOVF_BIT (0) + #define SC_SPIRXOVF_BITS (1) + +#define SC2_TWISTAT *((volatile uint32_t *)0x4000C044u) +#define SC2_TWISTAT_REG *((volatile uint32_t *)0x4000C044u) +#define SC2_TWISTAT_ADDR (0x4000C044u) +#define SC2_TWISTAT_RESET (0x00000000u) + /* SC_TWICMDFIN field */ + #define SC_TWICMDFIN (0x00000008u) + #define SC_TWICMDFIN_MASK (0x00000008u) + #define SC_TWICMDFIN_BIT (3) + #define SC_TWICMDFIN_BITS (1) + /* SC_TWIRXFIN field */ + #define SC_TWIRXFIN (0x00000004u) + #define SC_TWIRXFIN_MASK (0x00000004u) + #define SC_TWIRXFIN_BIT (2) + #define SC_TWIRXFIN_BITS (1) + /* SC_TWITXFIN field */ + #define SC_TWITXFIN (0x00000002u) + #define SC_TWITXFIN_MASK (0x00000002u) + #define SC_TWITXFIN_BIT (1) + #define SC_TWITXFIN_BITS (1) + /* SC_TWIRXNAK field */ + #define SC_TWIRXNAK (0x00000001u) + #define SC_TWIRXNAK_MASK (0x00000001u) + #define SC_TWIRXNAK_BIT (0) + #define SC_TWIRXNAK_BITS (1) + +#define SC2_TWICTRL1 *((volatile uint32_t *)0x4000C04Cu) +#define SC2_TWICTRL1_REG *((volatile uint32_t *)0x4000C04Cu) +#define SC2_TWICTRL1_ADDR (0x4000C04Cu) +#define SC2_TWICTRL1_RESET (0x00000000u) + /* SC_TWISTOP field */ + #define SC_TWISTOP (0x00000008u) + #define SC_TWISTOP_MASK (0x00000008u) + #define SC_TWISTOP_BIT (3) + #define SC_TWISTOP_BITS (1) + /* SC_TWISTART field */ + #define SC_TWISTART (0x00000004u) + #define SC_TWISTART_MASK (0x00000004u) + #define SC_TWISTART_BIT (2) + #define SC_TWISTART_BITS (1) + /* SC_TWISEND field */ + #define SC_TWISEND (0x00000002u) + #define SC_TWISEND_MASK (0x00000002u) + #define SC_TWISEND_BIT (1) + #define SC_TWISEND_BITS (1) + /* SC_TWIRECV field */ + #define SC_TWIRECV (0x00000001u) + #define SC_TWIRECV_MASK (0x00000001u) + #define SC_TWIRECV_BIT (0) + #define SC_TWIRECV_BITS (1) + +#define SC2_TWICTRL2 *((volatile uint32_t *)0x4000C050u) +#define SC2_TWICTRL2_REG *((volatile uint32_t *)0x4000C050u) +#define SC2_TWICTRL2_ADDR (0x4000C050u) +#define SC2_TWICTRL2_RESET (0x00000000u) + /* SC_TWIACK field */ + #define SC_TWIACK (0x00000001u) + #define SC_TWIACK_MASK (0x00000001u) + #define SC_TWIACK_BIT (0) + #define SC_TWIACK_BITS (1) + +#define SC2_MODE *((volatile uint32_t *)0x4000C054u) +#define SC2_MODE_REG *((volatile uint32_t *)0x4000C054u) +#define SC2_MODE_ADDR (0x4000C054u) +#define SC2_MODE_RESET (0x00000000u) + /* SC_MODE field */ + #define SC_MODE (0x00000003u) + #define SC_MODE_MASK (0x00000003u) + #define SC_MODE_BIT (0) + #define SC_MODE_BITS (2) + /* SC_MODE Bit Field Values */ + #define SC2_MODE_DISABLED (0) + #define SC2_MODE_SPI (2) + #define SC2_MODE_I2C (3) + +#define SC2_SPICFG *((volatile uint32_t *)0x4000C058u) +#define SC2_SPICFG_REG *((volatile uint32_t *)0x4000C058u) +#define SC2_SPICFG_ADDR (0x4000C058u) +#define SC2_SPICFG_RESET (0x00000000u) + /* SC_SPIRXDRV field */ + #define SC_SPIRXDRV (0x00000020u) + #define SC_SPIRXDRV_MASK (0x00000020u) + #define SC_SPIRXDRV_BIT (5) + #define SC_SPIRXDRV_BITS (1) + /* SC_SPIMST field */ + #define SC_SPIMST (0x00000010u) + #define SC_SPIMST_MASK (0x00000010u) + #define SC_SPIMST_BIT (4) + #define SC_SPIMST_BITS (1) + /* SC_SPIRPT field */ + #define SC_SPIRPT (0x00000008u) + #define SC_SPIRPT_MASK (0x00000008u) + #define SC_SPIRPT_BIT (3) + #define SC_SPIRPT_BITS (1) + /* SC_SPIORD field */ + #define SC_SPIORD (0x00000004u) + #define SC_SPIORD_MASK (0x00000004u) + #define SC_SPIORD_BIT (2) + #define SC_SPIORD_BITS (1) + /* SC_SPIPHA field */ + #define SC_SPIPHA (0x00000002u) + #define SC_SPIPHA_MASK (0x00000002u) + #define SC_SPIPHA_BIT (1) + #define SC_SPIPHA_BITS (1) + /* SC_SPIPOL field */ + #define SC_SPIPOL (0x00000001u) + #define SC_SPIPOL_MASK (0x00000001u) + #define SC_SPIPOL_BIT (0) + #define SC_SPIPOL_BITS (1) + +#define SC2_RATELIN *((volatile uint32_t *)0x4000C060u) +#define SC2_RATELIN_REG *((volatile uint32_t *)0x4000C060u) +#define SC2_RATELIN_ADDR (0x4000C060u) +#define SC2_RATELIN_RESET (0x00000000u) + /* SC_RATELIN field */ + #define SC_RATELIN (0x0000000Fu) + #define SC_RATELIN_MASK (0x0000000Fu) + #define SC_RATELIN_BIT (0) + #define SC_RATELIN_BITS (4) + +#define SC2_RATEEXP *((volatile uint32_t *)0x4000C064u) +#define SC2_RATEEXP_REG *((volatile uint32_t *)0x4000C064u) +#define SC2_RATEEXP_ADDR (0x4000C064u) +#define SC2_RATEEXP_RESET (0x00000000u) + /* SC_RATEEXP field */ + #define SC_RATEEXP (0x0000000Fu) + #define SC_RATEEXP_MASK (0x0000000Fu) + #define SC_RATEEXP_BIT (0) + #define SC_RATEEXP_BITS (4) + +#define SC2_RXCNTSAVED *((volatile uint32_t *)0x4000C070u) +#define SC2_RXCNTSAVED_REG *((volatile uint32_t *)0x4000C070u) +#define SC2_RXCNTSAVED_ADDR (0x4000C070u) +#define SC2_RXCNTSAVED_RESET (0x00000000u) + /* SC_RXCNTSAVED field */ + #define SC_RXCNTSAVED (0x00001FFFu) + #define SC_RXCNTSAVED_MASK (0x00001FFFu) + #define SC_RXCNTSAVED_BIT (0) + #define SC_RXCNTSAVED_BITS (13) + +#define SC1_RXBEGA *((volatile uint32_t *)0x4000C800u) +#define SC1_RXBEGA_REG *((volatile uint32_t *)0x4000C800u) +#define SC1_RXBEGA_ADDR (0x4000C800u) +#define SC1_RXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXBEGA_FIXED (0xFFFFE000u) + #define SC1_RXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC1_RXBEGA_FIXED_BIT (13) + #define SC1_RXBEGA_FIXED_BITS (19) + /* SC_RXBEGA field */ + #define SC_RXBEGA (0x00001FFFu) + #define SC_RXBEGA_MASK (0x00001FFFu) + #define SC_RXBEGA_BIT (0) + #define SC_RXBEGA_BITS (13) + +#define SC1_RXENDA *((volatile uint32_t *)0x4000C804u) +#define SC1_RXENDA_REG *((volatile uint32_t *)0x4000C804u) +#define SC1_RXENDA_ADDR (0x4000C804u) +#define SC1_RXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXENDA_FIXED (0xFFFFE000u) + #define SC1_RXENDA_FIXED_MASK (0xFFFFE000u) + #define SC1_RXENDA_FIXED_BIT (13) + #define SC1_RXENDA_FIXED_BITS (19) + /* SC_RXENDA field */ + #define SC_RXENDA (0x00001FFFu) + #define SC_RXENDA_MASK (0x00001FFFu) + #define SC_RXENDA_BIT (0) + #define SC_RXENDA_BITS (13) + +#define SC1_RXBEGB *((volatile uint32_t *)0x4000C808u) +#define SC1_RXBEGB_REG *((volatile uint32_t *)0x4000C808u) +#define SC1_RXBEGB_ADDR (0x4000C808u) +#define SC1_RXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXBEGB_FIXED (0xFFFFE000u) + #define SC1_RXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC1_RXBEGB_FIXED_BIT (13) + #define SC1_RXBEGB_FIXED_BITS (19) + /* SC_RXBEGB field */ + #define SC_RXBEGB (0x00001FFFu) + #define SC_RXBEGB_MASK (0x00001FFFu) + #define SC_RXBEGB_BIT (0) + #define SC_RXBEGB_BITS (13) + +#define SC1_RXENDB *((volatile uint32_t *)0x4000C80Cu) +#define SC1_RXENDB_REG *((volatile uint32_t *)0x4000C80Cu) +#define SC1_RXENDB_ADDR (0x4000C80Cu) +#define SC1_RXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_RXENDB_FIXED (0xFFFFE000u) + #define SC1_RXENDB_FIXED_MASK (0xFFFFE000u) + #define SC1_RXENDB_FIXED_BIT (13) + #define SC1_RXENDB_FIXED_BITS (19) + /* SC_RXENDB field */ + #define SC_RXENDB (0x00001FFFu) + #define SC_RXENDB_MASK (0x00001FFFu) + #define SC_RXENDB_BIT (0) + #define SC_RXENDB_BITS (13) + +#define SC1_TXBEGA *((volatile uint32_t *)0x4000C810u) +#define SC1_TXBEGA_REG *((volatile uint32_t *)0x4000C810u) +#define SC1_TXBEGA_ADDR (0x4000C810u) +#define SC1_TXBEGA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXBEGA_FIXED (0xFFFFE000u) + #define SC1_TXBEGA_FIXED_MASK (0xFFFFE000u) + #define SC1_TXBEGA_FIXED_BIT (13) + #define SC1_TXBEGA_FIXED_BITS (19) + /* SC_TXBEGA field */ + #define SC_TXBEGA (0x00001FFFu) + #define SC_TXBEGA_MASK (0x00001FFFu) + #define SC_TXBEGA_BIT (0) + #define SC_TXBEGA_BITS (13) + +#define SC1_TXENDA *((volatile uint32_t *)0x4000C814u) +#define SC1_TXENDA_REG *((volatile uint32_t *)0x4000C814u) +#define SC1_TXENDA_ADDR (0x4000C814u) +#define SC1_TXENDA_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXENDA_FIXED (0xFFFFE000u) + #define SC1_TXENDA_FIXED_MASK (0xFFFFE000u) + #define SC1_TXENDA_FIXED_BIT (13) + #define SC1_TXENDA_FIXED_BITS (19) + /* SC_TXENDA field */ + #define SC_TXENDA (0x00001FFFu) + #define SC_TXENDA_MASK (0x00001FFFu) + #define SC_TXENDA_BIT (0) + #define SC_TXENDA_BITS (13) + +#define SC1_TXBEGB *((volatile uint32_t *)0x4000C818u) +#define SC1_TXBEGB_REG *((volatile uint32_t *)0x4000C818u) +#define SC1_TXBEGB_ADDR (0x4000C818u) +#define SC1_TXBEGB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXBEGB_FIXED (0xFFFFE000u) + #define SC1_TXBEGB_FIXED_MASK (0xFFFFE000u) + #define SC1_TXBEGB_FIXED_BIT (13) + #define SC1_TXBEGB_FIXED_BITS (19) + /* SC_TXBEGB field */ + #define SC_TXBEGB (0x00001FFFu) + #define SC_TXBEGB_MASK (0x00001FFFu) + #define SC_TXBEGB_BIT (0) + #define SC_TXBEGB_BITS (13) + +#define SC1_TXENDB *((volatile uint32_t *)0x4000C81Cu) +#define SC1_TXENDB_REG *((volatile uint32_t *)0x4000C81Cu) +#define SC1_TXENDB_ADDR (0x4000C81Cu) +#define SC1_TXENDB_RESET (0x20000000u) + /* FIXED field */ + #define SC1_TXENDB_FIXED (0xFFFFE000u) + #define SC1_TXENDB_FIXED_MASK (0xFFFFE000u) + #define SC1_TXENDB_FIXED_BIT (13) + #define SC1_TXENDB_FIXED_BITS (19) + /* SC_TXENDB field */ + #define SC_TXENDB (0x00001FFFu) + #define SC_TXENDB_MASK (0x00001FFFu) + #define SC_TXENDB_BIT (0) + #define SC_TXENDB_BITS (13) + +#define SC1_RXCNTA *((volatile uint32_t *)0x4000C820u) +#define SC1_RXCNTA_REG *((volatile uint32_t *)0x4000C820u) +#define SC1_RXCNTA_ADDR (0x4000C820u) +#define SC1_RXCNTA_RESET (0x00000000u) + /* SC_RXCNTA field */ + #define SC_RXCNTA (0x00001FFFu) + #define SC_RXCNTA_MASK (0x00001FFFu) + #define SC_RXCNTA_BIT (0) + #define SC_RXCNTA_BITS (13) + +#define SC1_RXCNTB *((volatile uint32_t *)0x4000C824u) +#define SC1_RXCNTB_REG *((volatile uint32_t *)0x4000C824u) +#define SC1_RXCNTB_ADDR (0x4000C824u) +#define SC1_RXCNTB_RESET (0x00000000u) + /* SC_RXCNTB field */ + #define SC_RXCNTB (0x00001FFFu) + #define SC_RXCNTB_MASK (0x00001FFFu) + #define SC_RXCNTB_BIT (0) + #define SC_RXCNTB_BITS (13) + +#define SC1_TXCNT *((volatile uint32_t *)0x4000C828u) +#define SC1_TXCNT_REG *((volatile uint32_t *)0x4000C828u) +#define SC1_TXCNT_ADDR (0x4000C828u) +#define SC1_TXCNT_RESET (0x00000000u) + /* SC_TXCNT field */ + #define SC_TXCNT (0x00001FFFu) + #define SC_TXCNT_MASK (0x00001FFFu) + #define SC_TXCNT_BIT (0) + #define SC_TXCNT_BITS (13) + +#define SC1_DMASTAT *((volatile uint32_t *)0x4000C82Cu) +#define SC1_DMASTAT_REG *((volatile uint32_t *)0x4000C82Cu) +#define SC1_DMASTAT_ADDR (0x4000C82Cu) +#define SC1_DMASTAT_RESET (0x00000000u) + /* SC_RXSSEL field */ + #define SC_RXSSEL (0x00001C00u) + #define SC_RXSSEL_MASK (0x00001C00u) + #define SC_RXSSEL_BIT (10) + #define SC_RXSSEL_BITS (3) + /* SC_RXFRMB field */ + #define SC_RXFRMB (0x00000200u) + #define SC_RXFRMB_MASK (0x00000200u) + #define SC_RXFRMB_BIT (9) + #define SC_RXFRMB_BITS (1) + /* SC_RXFRMA field */ + #define SC_RXFRMA (0x00000100u) + #define SC_RXFRMA_MASK (0x00000100u) + #define SC_RXFRMA_BIT (8) + #define SC_RXFRMA_BITS (1) + /* SC_RXPARB field */ + #define SC_RXPARB (0x00000080u) + #define SC_RXPARB_MASK (0x00000080u) + #define SC_RXPARB_BIT (7) + #define SC_RXPARB_BITS (1) + /* SC_RXPARA field */ + #define SC_RXPARA (0x00000040u) + #define SC_RXPARA_MASK (0x00000040u) + #define SC_RXPARA_BIT (6) + #define SC_RXPARA_BITS (1) + /* SC_RXOVFB field */ + #define SC_RXOVFB (0x00000020u) + #define SC_RXOVFB_MASK (0x00000020u) + #define SC_RXOVFB_BIT (5) + #define SC_RXOVFB_BITS (1) + /* SC_RXOVFA field */ + #define SC_RXOVFA (0x00000010u) + #define SC_RXOVFA_MASK (0x00000010u) + #define SC_RXOVFA_BIT (4) + #define SC_RXOVFA_BITS (1) + /* SC_TXACTB field */ + #define SC_TXACTB (0x00000008u) + #define SC_TXACTB_MASK (0x00000008u) + #define SC_TXACTB_BIT (3) + #define SC_TXACTB_BITS (1) + /* SC_TXACTA field */ + #define SC_TXACTA (0x00000004u) + #define SC_TXACTA_MASK (0x00000004u) + #define SC_TXACTA_BIT (2) + #define SC_TXACTA_BITS (1) + /* SC_RXACTB field */ + #define SC_RXACTB (0x00000002u) + #define SC_RXACTB_MASK (0x00000002u) + #define SC_RXACTB_BIT (1) + #define SC_RXACTB_BITS (1) + /* SC_RXACTA field */ + #define SC_RXACTA (0x00000001u) + #define SC_RXACTA_MASK (0x00000001u) + #define SC_RXACTA_BIT (0) + #define SC_RXACTA_BITS (1) + +#define SC1_DMACTRL *((volatile uint32_t *)0x4000C830u) +#define SC1_DMACTRL_REG *((volatile uint32_t *)0x4000C830u) +#define SC1_DMACTRL_ADDR (0x4000C830u) +#define SC1_DMACTRL_RESET (0x00000000u) + /* SC_TXDMARST field */ + #define SC_TXDMARST (0x00000020u) + #define SC_TXDMARST_MASK (0x00000020u) + #define SC_TXDMARST_BIT (5) + #define SC_TXDMARST_BITS (1) + /* SC_RXDMARST field */ + #define SC_RXDMARST (0x00000010u) + #define SC_RXDMARST_MASK (0x00000010u) + #define SC_RXDMARST_BIT (4) + #define SC_RXDMARST_BITS (1) + /* SC_TXLODB field */ + #define SC_TXLODB (0x00000008u) + #define SC_TXLODB_MASK (0x00000008u) + #define SC_TXLODB_BIT (3) + #define SC_TXLODB_BITS (1) + /* SC_TXLODA field */ + #define SC_TXLODA (0x00000004u) + #define SC_TXLODA_MASK (0x00000004u) + #define SC_TXLODA_BIT (2) + #define SC_TXLODA_BITS (1) + /* SC_RXLODB field */ + #define SC_RXLODB (0x00000002u) + #define SC_RXLODB_MASK (0x00000002u) + #define SC_RXLODB_BIT (1) + #define SC_RXLODB_BITS (1) + /* SC_RXLODA field */ + #define SC_RXLODA (0x00000001u) + #define SC_RXLODA_MASK (0x00000001u) + #define SC_RXLODA_BIT (0) + #define SC_RXLODA_BITS (1) + +#define SC1_RXERRA *((volatile uint32_t *)0x4000C834u) +#define SC1_RXERRA_REG *((volatile uint32_t *)0x4000C834u) +#define SC1_RXERRA_ADDR (0x4000C834u) +#define SC1_RXERRA_RESET (0x00000000u) + /* SC_RXERRA field */ + #define SC_RXERRA (0x00001FFFu) + #define SC_RXERRA_MASK (0x00001FFFu) + #define SC_RXERRA_BIT (0) + #define SC_RXERRA_BITS (13) + +#define SC1_RXERRB *((volatile uint32_t *)0x4000C838u) +#define SC1_RXERRB_REG *((volatile uint32_t *)0x4000C838u) +#define SC1_RXERRB_ADDR (0x4000C838u) +#define SC1_RXERRB_RESET (0x00000000u) + /* SC_RXERRB field */ + #define SC_RXERRB (0x00001FFFu) + #define SC_RXERRB_MASK (0x00001FFFu) + #define SC_RXERRB_BIT (0) + #define SC_RXERRB_BITS (13) + +#define SC1_DATA *((volatile uint32_t *)0x4000C83Cu) +#define SC1_DATA_REG *((volatile uint32_t *)0x4000C83Cu) +#define SC1_DATA_ADDR (0x4000C83Cu) +#define SC1_DATA_RESET (0x00000000u) + /* SC_DATA field */ + #define SC_DATA (0x000000FFu) + #define SC_DATA_MASK (0x000000FFu) + #define SC_DATA_BIT (0) + #define SC_DATA_BITS (8) + +#define SC1_SPISTAT *((volatile uint32_t *)0x4000C840u) +#define SC1_SPISTAT_REG *((volatile uint32_t *)0x4000C840u) +#define SC1_SPISTAT_ADDR (0x4000C840u) +#define SC1_SPISTAT_RESET (0x00000000u) + /* SC_SPITXIDLE field */ + #define SC_SPITXIDLE (0x00000008u) + #define SC_SPITXIDLE_MASK (0x00000008u) + #define SC_SPITXIDLE_BIT (3) + #define SC_SPITXIDLE_BITS (1) + /* SC_SPITXFREE field */ + #define SC_SPITXFREE (0x00000004u) + #define SC_SPITXFREE_MASK (0x00000004u) + #define SC_SPITXFREE_BIT (2) + #define SC_SPITXFREE_BITS (1) + /* SC_SPIRXVAL field */ + #define SC_SPIRXVAL (0x00000002u) + #define SC_SPIRXVAL_MASK (0x00000002u) + #define SC_SPIRXVAL_BIT (1) + #define SC_SPIRXVAL_BITS (1) + /* SC_SPIRXOVF field */ + #define SC_SPIRXOVF (0x00000001u) + #define SC_SPIRXOVF_MASK (0x00000001u) + #define SC_SPIRXOVF_BIT (0) + #define SC_SPIRXOVF_BITS (1) + +#define SC1_TWISTAT *((volatile uint32_t *)0x4000C844u) +#define SC1_TWISTAT_REG *((volatile uint32_t *)0x4000C844u) +#define SC1_TWISTAT_ADDR (0x4000C844u) +#define SC1_TWISTAT_RESET (0x00000000u) + /* SC_TWICMDFIN field */ + #define SC_TWICMDFIN (0x00000008u) + #define SC_TWICMDFIN_MASK (0x00000008u) + #define SC_TWICMDFIN_BIT (3) + #define SC_TWICMDFIN_BITS (1) + /* SC_TWIRXFIN field */ + #define SC_TWIRXFIN (0x00000004u) + #define SC_TWIRXFIN_MASK (0x00000004u) + #define SC_TWIRXFIN_BIT (2) + #define SC_TWIRXFIN_BITS (1) + /* SC_TWITXFIN field */ + #define SC_TWITXFIN (0x00000002u) + #define SC_TWITXFIN_MASK (0x00000002u) + #define SC_TWITXFIN_BIT (1) + #define SC_TWITXFIN_BITS (1) + /* SC_TWIRXNAK field */ + #define SC_TWIRXNAK (0x00000001u) + #define SC_TWIRXNAK_MASK (0x00000001u) + #define SC_TWIRXNAK_BIT (0) + #define SC_TWIRXNAK_BITS (1) + +#define SC1_UARTSTAT *((volatile uint32_t *)0x4000C848u) +#define SC1_UARTSTAT_REG *((volatile uint32_t *)0x4000C848u) +#define SC1_UARTSTAT_ADDR (0x4000C848u) +#define SC1_UARTSTAT_RESET (0x00000040u) + /* SC_UARTTXIDLE field */ + #define SC_UARTTXIDLE (0x00000040u) + #define SC_UARTTXIDLE_MASK (0x00000040u) + #define SC_UARTTXIDLE_BIT (6) + #define SC_UARTTXIDLE_BITS (1) + /* SC_UARTPARERR field */ + #define SC_UARTPARERR (0x00000020u) + #define SC_UARTPARERR_MASK (0x00000020u) + #define SC_UARTPARERR_BIT (5) + #define SC_UARTPARERR_BITS (1) + /* SC_UARTFRMERR field */ + #define SC_UARTFRMERR (0x00000010u) + #define SC_UARTFRMERR_MASK (0x00000010u) + #define SC_UARTFRMERR_BIT (4) + #define SC_UARTFRMERR_BITS (1) + /* SC_UARTRXOVF field */ + #define SC_UARTRXOVF (0x00000008u) + #define SC_UARTRXOVF_MASK (0x00000008u) + #define SC_UARTRXOVF_BIT (3) + #define SC_UARTRXOVF_BITS (1) + /* SC_UARTTXFREE field */ + #define SC_UARTTXFREE (0x00000004u) + #define SC_UARTTXFREE_MASK (0x00000004u) + #define SC_UARTTXFREE_BIT (2) + #define SC_UARTTXFREE_BITS (1) + /* SC_UARTRXVAL field */ + #define SC_UARTRXVAL (0x00000002u) + #define SC_UARTRXVAL_MASK (0x00000002u) + #define SC_UARTRXVAL_BIT (1) + #define SC_UARTRXVAL_BITS (1) + /* SC_UARTCTS field */ + #define SC_UARTCTS (0x00000001u) + #define SC_UARTCTS_MASK (0x00000001u) + #define SC_UARTCTS_BIT (0) + #define SC_UARTCTS_BITS (1) + +#define SC1_TWICTRL1 *((volatile uint32_t *)0x4000C84Cu) +#define SC1_TWICTRL1_REG *((volatile uint32_t *)0x4000C84Cu) +#define SC1_TWICTRL1_ADDR (0x4000C84Cu) +#define SC1_TWICTRL1_RESET (0x00000000u) + /* SC_TWISTOP field */ + #define SC_TWISTOP (0x00000008u) + #define SC_TWISTOP_MASK (0x00000008u) + #define SC_TWISTOP_BIT (3) + #define SC_TWISTOP_BITS (1) + /* SC_TWISTART field */ + #define SC_TWISTART (0x00000004u) + #define SC_TWISTART_MASK (0x00000004u) + #define SC_TWISTART_BIT (2) + #define SC_TWISTART_BITS (1) + /* SC_TWISEND field */ + #define SC_TWISEND (0x00000002u) + #define SC_TWISEND_MASK (0x00000002u) + #define SC_TWISEND_BIT (1) + #define SC_TWISEND_BITS (1) + /* SC_TWIRECV field */ + #define SC_TWIRECV (0x00000001u) + #define SC_TWIRECV_MASK (0x00000001u) + #define SC_TWIRECV_BIT (0) + #define SC_TWIRECV_BITS (1) + +#define SC1_TWICTRL2 *((volatile uint32_t *)0x4000C850u) +#define SC1_TWICTRL2_REG *((volatile uint32_t *)0x4000C850u) +#define SC1_TWICTRL2_ADDR (0x4000C850u) +#define SC1_TWICTRL2_RESET (0x00000000u) + /* SC_TWIACK field */ + #define SC_TWIACK (0x00000001u) + #define SC_TWIACK_MASK (0x00000001u) + #define SC_TWIACK_BIT (0) + #define SC_TWIACK_BITS (1) + +#define SC1_MODE *((volatile uint32_t *)0x4000C854u) +#define SC1_MODE_REG *((volatile uint32_t *)0x4000C854u) +#define SC1_MODE_ADDR (0x4000C854u) +#define SC1_MODE_RESET (0x00000000u) + /* SC_MODE field */ + #define SC_MODE (0x00000003u) + #define SC_MODE_MASK (0x00000003u) + #define SC_MODE_BIT (0) + #define SC_MODE_BITS (2) + /* SC_MODE Bit Field Values */ + #define SC1_MODE_DISABLED (0) + #define SC1_MODE_UART (1) + #define SC1_MODE_SPI (2) + #define SC1_MODE_I2C (3) + +#define SC1_SPICFG *((volatile uint32_t *)0x4000C858u) +#define SC1_SPICFG_REG *((volatile uint32_t *)0x4000C858u) +#define SC1_SPICFG_ADDR (0x4000C858u) +#define SC1_SPICFG_RESET (0x00000000u) + /* SC_SPIRXDRV field */ + #define SC_SPIRXDRV (0x00000020u) + #define SC_SPIRXDRV_MASK (0x00000020u) + #define SC_SPIRXDRV_BIT (5) + #define SC_SPIRXDRV_BITS (1) + /* SC_SPIMST field */ + #define SC_SPIMST (0x00000010u) + #define SC_SPIMST_MASK (0x00000010u) + #define SC_SPIMST_BIT (4) + #define SC_SPIMST_BITS (1) + /* SC_SPIRPT field */ + #define SC_SPIRPT (0x00000008u) + #define SC_SPIRPT_MASK (0x00000008u) + #define SC_SPIRPT_BIT (3) + #define SC_SPIRPT_BITS (1) + /* SC_SPIORD field */ + #define SC_SPIORD (0x00000004u) + #define SC_SPIORD_MASK (0x00000004u) + #define SC_SPIORD_BIT (2) + #define SC_SPIORD_BITS (1) + /* SC_SPIPHA field */ + #define SC_SPIPHA (0x00000002u) + #define SC_SPIPHA_MASK (0x00000002u) + #define SC_SPIPHA_BIT (1) + #define SC_SPIPHA_BITS (1) + /* SC_SPIPOL field */ + #define SC_SPIPOL (0x00000001u) + #define SC_SPIPOL_MASK (0x00000001u) + #define SC_SPIPOL_BIT (0) + #define SC_SPIPOL_BITS (1) + +#define SC1_UARTCFG *((volatile uint32_t *)0x4000C85Cu) +#define SC1_UARTCFG_REG *((volatile uint32_t *)0x4000C85Cu) +#define SC1_UARTCFG_ADDR (0x4000C85Cu) +#define SC1_UARTCFG_RESET (0x00000000u) + /* SC_UARTAUTO field */ + #define SC_UARTAUTO (0x00000040u) + #define SC_UARTAUTO_MASK (0x00000040u) + #define SC_UARTAUTO_BIT (6) + #define SC_UARTAUTO_BITS (1) + /* SC_UARTFLOW field */ + #define SC_UARTFLOW (0x00000020u) + #define SC_UARTFLOW_MASK (0x00000020u) + #define SC_UARTFLOW_BIT (5) + #define SC_UARTFLOW_BITS (1) + /* SC_UARTODD field */ + #define SC_UARTODD (0x00000010u) + #define SC_UARTODD_MASK (0x00000010u) + #define SC_UARTODD_BIT (4) + #define SC_UARTODD_BITS (1) + /* SC_UARTPAR field */ + #define SC_UARTPAR (0x00000008u) + #define SC_UARTPAR_MASK (0x00000008u) + #define SC_UARTPAR_BIT (3) + #define SC_UARTPAR_BITS (1) + /* SC_UART2STP field */ + #define SC_UART2STP (0x00000004u) + #define SC_UART2STP_MASK (0x00000004u) + #define SC_UART2STP_BIT (2) + #define SC_UART2STP_BITS (1) + /* SC_UART8BIT field */ + #define SC_UART8BIT (0x00000002u) + #define SC_UART8BIT_MASK (0x00000002u) + #define SC_UART8BIT_BIT (1) + #define SC_UART8BIT_BITS (1) + /* SC_UARTRTS field */ + #define SC_UARTRTS (0x00000001u) + #define SC_UARTRTS_MASK (0x00000001u) + #define SC_UARTRTS_BIT (0) + #define SC_UARTRTS_BITS (1) + +#define SC1_RATELIN *((volatile uint32_t *)0x4000C860u) +#define SC1_RATELIN_REG *((volatile uint32_t *)0x4000C860u) +#define SC1_RATELIN_ADDR (0x4000C860u) +#define SC1_RATELIN_RESET (0x00000000u) + /* SC_RATELIN field */ + #define SC_RATELIN (0x0000000Fu) + #define SC_RATELIN_MASK (0x0000000Fu) + #define SC_RATELIN_BIT (0) + #define SC_RATELIN_BITS (4) + +#define SC1_RATEEXP *((volatile uint32_t *)0x4000C864u) +#define SC1_RATEEXP_REG *((volatile uint32_t *)0x4000C864u) +#define SC1_RATEEXP_ADDR (0x4000C864u) +#define SC1_RATEEXP_RESET (0x00000000u) + /* SC_RATEEXP field */ + #define SC_RATEEXP (0x0000000Fu) + #define SC_RATEEXP_MASK (0x0000000Fu) + #define SC_RATEEXP_BIT (0) + #define SC_RATEEXP_BITS (4) + +#define SC1_UARTPER *((volatile uint32_t *)0x4000C868u) +#define SC1_UARTPER_REG *((volatile uint32_t *)0x4000C868u) +#define SC1_UARTPER_ADDR (0x4000C868u) +#define SC1_UARTPER_RESET (0x00000000u) + /* SC_UARTPER field */ + #define SC_UARTPER (0x0000FFFFu) + #define SC_UARTPER_MASK (0x0000FFFFu) + #define SC_UARTPER_BIT (0) + #define SC_UARTPER_BITS (16) + +#define SC1_UARTFRAC *((volatile uint32_t *)0x4000C86Cu) +#define SC1_UARTFRAC_REG *((volatile uint32_t *)0x4000C86Cu) +#define SC1_UARTFRAC_ADDR (0x4000C86Cu) +#define SC1_UARTFRAC_RESET (0x00000000u) + /* SC_UARTFRAC field */ + #define SC_UARTFRAC (0x00000001u) + #define SC_UARTFRAC_MASK (0x00000001u) + #define SC_UARTFRAC_BIT (0) + #define SC_UARTFRAC_BITS (1) + +#define SC1_RXCNTSAVED *((volatile uint32_t *)0x4000C870u) +#define SC1_RXCNTSAVED_REG *((volatile uint32_t *)0x4000C870u) +#define SC1_RXCNTSAVED_ADDR (0x4000C870u) +#define SC1_RXCNTSAVED_RESET (0x00000000u) + /* SC_RXCNTSAVED field */ + #define SC_RXCNTSAVED (0x00001FFFu) + #define SC_RXCNTSAVED_MASK (0x00001FFFu) + #define SC_RXCNTSAVED_BIT (0) + #define SC_RXCNTSAVED_BITS (13) + +/* ADC block */ +#define BLOCK_ADC_BASE (0x4000D000u) +#define BLOCK_ADC_END (0x4000D024u) +#define BLOCK_ADC_SIZE (BLOCK_ADC_END - BLOCK_ADC_BASE + 1) + +#define ADC_DATA *((volatile uint32_t *)0x4000D000u) +#define ADC_DATA_REG *((volatile uint32_t *)0x4000D000u) +#define ADC_DATA_ADDR (0x4000D000u) +#define ADC_DATA_RESET (0x00000000u) + /* ADC_DATA_FIELD field */ + #define ADC_DATA_FIELD (0x0000FFFFu) + #define ADC_DATA_FIELD_MASK (0x0000FFFFu) + #define ADC_DATA_FIELD_BIT (0) + #define ADC_DATA_FIELD_BITS (16) + +#define ADC_CFG *((volatile uint32_t *)0x4000D004u) +#define ADC_CFG_REG *((volatile uint32_t *)0x4000D004u) +#define ADC_CFG_ADDR (0x4000D004u) +#define ADC_CFG_RESET (0x00001800u) + /* ADC_PERIOD field */ + #define ADC_PERIOD (0x0000E000u) + #define ADC_PERIOD_MASK (0x0000E000u) + #define ADC_PERIOD_BIT (13) + #define ADC_PERIOD_BITS (3) + /* ADC_HVSELP field */ + #define ADC_HVSELP (0x00001000u) + #define ADC_HVSELP_MASK (0x00001000u) + #define ADC_HVSELP_BIT (12) + #define ADC_HVSELP_BITS (1) + /* ADC_HVSELN field */ + #define ADC_HVSELN (0x00000800u) + #define ADC_HVSELN_MASK (0x00000800u) + #define ADC_HVSELN_BIT (11) + #define ADC_HVSELN_BITS (1) + /* ADC_MUXP field */ + #define ADC_MUXP (0x00000780u) + #define ADC_MUXP_MASK (0x00000780u) + #define ADC_MUXP_BIT (7) + #define ADC_MUXP_BITS (4) + /* ADC_MUXN field */ + #define ADC_MUXN (0x00000078u) + #define ADC_MUXN_MASK (0x00000078u) + #define ADC_MUXN_BIT (3) + #define ADC_MUXN_BITS (4) + /* ADC_1MHZCLK field */ + #define ADC_1MHZCLK (0x00000004u) + #define ADC_1MHZCLK_MASK (0x00000004u) + #define ADC_1MHZCLK_BIT (2) + #define ADC_1MHZCLK_BITS (1) + /* ADC_CFGRSVD field */ + #define ADC_CFGRSVD (0x00000002u) + #define ADC_CFGRSVD_MASK (0x00000002u) + #define ADC_CFGRSVD_BIT (1) + #define ADC_CFGRSVD_BITS (1) + /* ADC_ENABLE field */ + #define ADC_ENABLE (0x00000001u) + #define ADC_ENABLE_MASK (0x00000001u) + #define ADC_ENABLE_BIT (0) + #define ADC_ENABLE_BITS (1) + +#define ADC_OFFSET *((volatile uint32_t *)0x4000D008u) +#define ADC_OFFSET_REG *((volatile uint32_t *)0x4000D008u) +#define ADC_OFFSET_ADDR (0x4000D008u) +#define ADC_OFFSET_RESET (0x00000000u) + /* ADC_OFFSET_FIELD field */ + #define ADC_OFFSET_FIELD (0x0000FFFFu) + #define ADC_OFFSET_FIELD_MASK (0x0000FFFFu) + #define ADC_OFFSET_FIELD_BIT (0) + #define ADC_OFFSET_FIELD_BITS (16) + +#define ADC_GAIN *((volatile uint32_t *)0x4000D00Cu) +#define ADC_GAIN_REG *((volatile uint32_t *)0x4000D00Cu) +#define ADC_GAIN_ADDR (0x4000D00Cu) +#define ADC_GAIN_RESET (0x00008000u) + /* ADC_GAIN_FIELD field */ + #define ADC_GAIN_FIELD (0x0000FFFFu) + #define ADC_GAIN_FIELD_MASK (0x0000FFFFu) + #define ADC_GAIN_FIELD_BIT (0) + #define ADC_GAIN_FIELD_BITS (16) + +#define ADC_DMACFG *((volatile uint32_t *)0x4000D010u) +#define ADC_DMACFG_REG *((volatile uint32_t *)0x4000D010u) +#define ADC_DMACFG_ADDR (0x4000D010u) +#define ADC_DMACFG_RESET (0x00000000u) + /* ADC_DMARST field */ + #define ADC_DMARST (0x00000010u) + #define ADC_DMARST_MASK (0x00000010u) + #define ADC_DMARST_BIT (4) + #define ADC_DMARST_BITS (1) + /* ADC_DMAAUTOWRAP field */ + #define ADC_DMAAUTOWRAP (0x00000002u) + #define ADC_DMAAUTOWRAP_MASK (0x00000002u) + #define ADC_DMAAUTOWRAP_BIT (1) + #define ADC_DMAAUTOWRAP_BITS (1) + /* ADC_DMALOAD field */ + #define ADC_DMALOAD (0x00000001u) + #define ADC_DMALOAD_MASK (0x00000001u) + #define ADC_DMALOAD_BIT (0) + #define ADC_DMALOAD_BITS (1) + +#define ADC_DMASTAT *((volatile uint32_t *)0x4000D014u) +#define ADC_DMASTAT_REG *((volatile uint32_t *)0x4000D014u) +#define ADC_DMASTAT_ADDR (0x4000D014u) +#define ADC_DMASTAT_RESET (0x00000000u) + /* ADC_DMAOVF field */ + #define ADC_DMAOVF (0x00000002u) + #define ADC_DMAOVF_MASK (0x00000002u) + #define ADC_DMAOVF_BIT (1) + #define ADC_DMAOVF_BITS (1) + /* ADC_DMAACT field */ + #define ADC_DMAACT (0x00000001u) + #define ADC_DMAACT_MASK (0x00000001u) + #define ADC_DMAACT_BIT (0) + #define ADC_DMAACT_BITS (1) + +#define ADC_DMABEG *((volatile uint32_t *)0x4000D018u) +#define ADC_DMABEG_REG *((volatile uint32_t *)0x4000D018u) +#define ADC_DMABEG_ADDR (0x4000D018u) +#define ADC_DMABEG_RESET (0x20000000u) + /* ADC_DMABEG_FIXED field */ + #define ADC_DMABEG_FIXED (0xFFFFE000u) + #define ADC_DMABEG_FIXED_MASK (0xFFFFE000u) + #define ADC_DMABEG_FIXED_BIT (13) + #define ADC_DMABEG_FIXED_BITS (19) + /* ADC_DMABEG_FIELD field */ + #define ADC_DMABEG_FIELD (0x00001FFFu) + #define ADC_DMABEG_FIELD_MASK (0x00001FFFu) + #define ADC_DMABEG_FIELD_BIT (0) + #define ADC_DMABEG_FIELD_BITS (13) + +#define ADC_DMASIZE *((volatile uint32_t *)0x4000D01Cu) +#define ADC_DMASIZE_REG *((volatile uint32_t *)0x4000D01Cu) +#define ADC_DMASIZE_ADDR (0x4000D01Cu) +#define ADC_DMASIZE_RESET (0x00000000u) + /* ADC_DMASIZE_FIELD field */ + #define ADC_DMASIZE_FIELD (0x00000FFFu) + #define ADC_DMASIZE_FIELD_MASK (0x00000FFFu) + #define ADC_DMASIZE_FIELD_BIT (0) + #define ADC_DMASIZE_FIELD_BITS (12) + +#define ADC_DMACUR *((volatile uint32_t *)0x4000D020u) +#define ADC_DMACUR_REG *((volatile uint32_t *)0x4000D020u) +#define ADC_DMACUR_ADDR (0x4000D020u) +#define ADC_DMACUR_RESET (0x20000000u) + /* ADC_DMACUR_FIXED field */ + #define ADC_DMACUR_FIXED (0xFFFFE000u) + #define ADC_DMACUR_FIXED_MASK (0xFFFFE000u) + #define ADC_DMACUR_FIXED_BIT (13) + #define ADC_DMACUR_FIXED_BITS (19) + /* ADC_DMACUR_FIELD field */ + #define ADC_DMACUR_FIELD (0x00001FFFu) + #define ADC_DMACUR_FIELD_MASK (0x00001FFFu) + #define ADC_DMACUR_FIELD_BIT (0) + #define ADC_DMACUR_FIELD_BITS (13) + +#define ADC_DMACNT *((volatile uint32_t *)0x4000D024u) +#define ADC_DMACNT_REG *((volatile uint32_t *)0x4000D024u) +#define ADC_DMACNT_ADDR (0x4000D024u) +#define ADC_DMACNT_RESET (0x00000000u) + /* ADC_DMACNT_FIELD field */ + #define ADC_DMACNT_FIELD (0x00000FFFu) + #define ADC_DMACNT_FIELD_MASK (0x00000FFFu) + #define ADC_DMACNT_FIELD_BIT (0) + #define ADC_DMACNT_FIELD_BITS (12) + +/* TIM1 block */ +#define BLOCK_TIM1_BASE (0x4000E000u) +#define BLOCK_TIM1_END (0x4000E050u) +#define BLOCK_TIM1_SIZE (BLOCK_TIM1_END - BLOCK_TIM1_BASE + 1) + +#define TIM1_CR1 *((volatile uint32_t *)0x4000E000u) +#define TIM1_CR1_REG *((volatile uint32_t *)0x4000E000u) +#define TIM1_CR1_ADDR (0x4000E000u) +#define TIM1_CR1_RESET (0x00000000u) + /* TIM_ARBE field */ + #define TIM_ARBE (0x00000080u) + #define TIM_ARBE_MASK (0x00000080u) + #define TIM_ARBE_BIT (7) + #define TIM_ARBE_BITS (1) + /* TIM_CMS field */ + #define TIM_CMS (0x00000060u) + #define TIM_CMS_MASK (0x00000060u) + #define TIM_CMS_BIT (5) + #define TIM_CMS_BITS (2) + /* TIM_DIR field */ + #define TIM_DIR (0x00000010u) + #define TIM_DIR_MASK (0x00000010u) + #define TIM_DIR_BIT (4) + #define TIM_DIR_BITS (1) + /* TIM_OPM field */ + #define TIM_OPM (0x00000008u) + #define TIM_OPM_MASK (0x00000008u) + #define TIM_OPM_BIT (3) + #define TIM_OPM_BITS (1) + /* TIM_URS field */ + #define TIM_URS (0x00000004u) + #define TIM_URS_MASK (0x00000004u) + #define TIM_URS_BIT (2) + #define TIM_URS_BITS (1) + /* TIM_UDIS field */ + #define TIM_UDIS (0x00000002u) + #define TIM_UDIS_MASK (0x00000002u) + #define TIM_UDIS_BIT (1) + #define TIM_UDIS_BITS (1) + /* TIM_CEN field */ + #define TIM_CEN (0x00000001u) + #define TIM_CEN_MASK (0x00000001u) + #define TIM_CEN_BIT (0) + #define TIM_CEN_BITS (1) + +#define TIM1_CR2 *((volatile uint32_t *)0x4000E004u) +#define TIM1_CR2_REG *((volatile uint32_t *)0x4000E004u) +#define TIM1_CR2_ADDR (0x4000E004u) +#define TIM1_CR2_RESET (0x00000000u) + /* TIM_TI1S field */ + #define TIM_TI1S (0x00000080u) + #define TIM_TI1S_MASK (0x00000080u) + #define TIM_TI1S_BIT (7) + #define TIM_TI1S_BITS (1) + /* TIM_MMS field */ + #define TIM_MMS (0x00000070u) + #define TIM_MMS_MASK (0x00000070u) + #define TIM_MMS_BIT (4) + #define TIM_MMS_BITS (3) + +#define TIM1_SMCR *((volatile uint32_t *)0x4000E008u) +#define TIM1_SMCR_REG *((volatile uint32_t *)0x4000E008u) +#define TIM1_SMCR_ADDR (0x4000E008u) +#define TIM1_SMCR_RESET (0x00000000u) + /* TIM_ETP field */ + #define TIM_ETP (0x00008000u) + #define TIM_ETP_MASK (0x00008000u) + #define TIM_ETP_BIT (15) + #define TIM_ETP_BITS (1) + /* TIM_ECE field */ + #define TIM_ECE (0x00004000u) + #define TIM_ECE_MASK (0x00004000u) + #define TIM_ECE_BIT (14) + #define TIM_ECE_BITS (1) + /* TIM_ETPS field */ + #define TIM_ETPS (0x00003000u) + #define TIM_ETPS_MASK (0x00003000u) + #define TIM_ETPS_BIT (12) + #define TIM_ETPS_BITS (2) + /* TIM_ETF field */ + #define TIM_ETF (0x00000F00u) + #define TIM_ETF_MASK (0x00000F00u) + #define TIM_ETF_BIT (8) + #define TIM_ETF_BITS (4) + /* TIM_MSM field */ + #define TIM_MSM (0x00000080u) + #define TIM_MSM_MASK (0x00000080u) + #define TIM_MSM_BIT (7) + #define TIM_MSM_BITS (1) + /* TIM_TS field */ + #define TIM_TS (0x00000070u) + #define TIM_TS_MASK (0x00000070u) + #define TIM_TS_BIT (4) + #define TIM_TS_BITS (3) + /* TIM_SMS field */ + #define TIM_SMS (0x00000007u) + #define TIM_SMS_MASK (0x00000007u) + #define TIM_SMS_BIT (0) + #define TIM_SMS_BITS (3) + +#define TMR1_DIER *((volatile uint32_t *)0x4000E00Cu) +#define TMR1_DIER_REG *((volatile uint32_t *)0x4000E00Cu) +#define TMR1_DIER_ADDR (0x4000E00Cu) +#define TMR1_DIER_RESET (0x00000000u) + /* TIE field */ + #define TMR1_DIER_TIE (0x00000040u) + #define TMR1_DIER_TIE_MASK (0x00000040u) + #define TMR1_DIER_TIE_BIT (6) + #define TMR1_DIER_TIE_BITS (1) + /* CC4IE field */ + #define TMR1_DIER_CC4IE (0x00000010u) + #define TMR1_DIER_CC4IE_MASK (0x00000010u) + #define TMR1_DIER_CC4IE_BIT (4) + #define TMR1_DIER_CC4IE_BITS (1) + /* CC3IE field */ + #define TMR1_DIER_CC3IE (0x00000008u) + #define TMR1_DIER_CC3IE_MASK (0x00000008u) + #define TMR1_DIER_CC3IE_BIT (3) + #define TMR1_DIER_CC3IE_BITS (1) + /* CC2IE field */ + #define TMR1_DIER_CC2IE (0x00000004u) + #define TMR1_DIER_CC2IE_MASK (0x00000004u) + #define TMR1_DIER_CC2IE_BIT (2) + #define TMR1_DIER_CC2IE_BITS (1) + /* CC1IE field */ + #define TMR1_DIER_CC1IE (0x00000002u) + #define TMR1_DIER_CC1IE_MASK (0x00000002u) + #define TMR1_DIER_CC1IE_BIT (1) + #define TMR1_DIER_CC1IE_BITS (1) + /* UIE field */ + #define TMR1_DIER_UIE (0x00000001u) + #define TMR1_DIER_UIE_MASK (0x00000001u) + #define TMR1_DIER_UIE_BIT (0) + #define TMR1_DIER_UIE_BITS (1) + +#define TMR1_SR *((volatile uint32_t *)0x4000E010u) +#define TMR1_SR_REG *((volatile uint32_t *)0x4000E010u) +#define TMR1_SR_ADDR (0x4000E010u) +#define TMR1_SR_RESET (0x00000000u) + /* CC4OF field */ + #define TMR1_SR_CC4OF (0x00001000u) + #define TMR1_SR_CC4OF_MASK (0x00001000u) + #define TMR1_SR_CC4OF_BIT (12) + #define TMR1_SR_CC4OF_BITS (1) + /* CC3OF field */ + #define TMR1_SR_CC3OF (0x00000800u) + #define TMR1_SR_CC3OF_MASK (0x00000800u) + #define TMR1_SR_CC3OF_BIT (11) + #define TMR1_SR_CC3OF_BITS (1) + /* CC2OF field */ + #define TMR1_SR_CC2OF (0x00000400u) + #define TMR1_SR_CC2OF_MASK (0x00000400u) + #define TMR1_SR_CC2OF_BIT (10) + #define TMR1_SR_CC2OF_BITS (1) + /* CC1OF field */ + #define TMR1_SR_CC1OF (0x00000200u) + #define TMR1_SR_CC1OF_MASK (0x00000200u) + #define TMR1_SR_CC1OF_BIT (9) + #define TMR1_SR_CC1OF_BITS (1) + /* TIF field */ + #define TMR1_SR_TIF (0x00000040u) + #define TMR1_SR_TIF_MASK (0x00000040u) + #define TMR1_SR_TIF_BIT (6) + #define TMR1_SR_TIF_BITS (1) + /* CC4IF field */ + #define TMR1_SR_CC4IF (0x00000010u) + #define TMR1_SR_CC4IF_MASK (0x00000010u) + #define TMR1_SR_CC4IF_BIT (4) + #define TMR1_SR_CC4IF_BITS (1) + /* CC3IF field */ + #define TMR1_SR_CC3IF (0x00000008u) + #define TMR1_SR_CC3IF_MASK (0x00000008u) + #define TMR1_SR_CC3IF_BIT (3) + #define TMR1_SR_CC3IF_BITS (1) + /* CC2IF field */ + #define TMR1_SR_CC2IF (0x00000004u) + #define TMR1_SR_CC2IF_MASK (0x00000004u) + #define TMR1_SR_CC2IF_BIT (2) + #define TMR1_SR_CC2IF_BITS (1) + /* CC1IF field */ + #define TMR1_SR_CC1IF (0x00000002u) + #define TMR1_SR_CC1IF_MASK (0x00000002u) + #define TMR1_SR_CC1IF_BIT (1) + #define TMR1_SR_CC1IF_BITS (1) + /* UIF field */ + #define TMR1_SR_UIF (0x00000001u) + #define TMR1_SR_UIF_MASK (0x00000001u) + #define TMR1_SR_UIF_BIT (0) + #define TMR1_SR_UIF_BITS (1) + +#define TIM1_EGR *((volatile uint32_t *)0x4000E014u) +#define TIM1_EGR_REG *((volatile uint32_t *)0x4000E014u) +#define TIM1_EGR_ADDR (0x4000E014u) +#define TIM1_EGR_RESET (0x00000000u) + /* TIM_TG field */ + #define TIM_TG (0x00000040u) + #define TIM_TG_MASK (0x00000040u) + #define TIM_TG_BIT (6) + #define TIM_TG_BITS (1) + /* TIM_CC4G field */ + #define TIM_CC4G (0x00000010u) + #define TIM_CC4G_MASK (0x00000010u) + #define TIM_CC4G_BIT (4) + #define TIM_CC4G_BITS (1) + /* TIM_CC3G field */ + #define TIM_CC3G (0x00000008u) + #define TIM_CC3G_MASK (0x00000008u) + #define TIM_CC3G_BIT (3) + #define TIM_CC3G_BITS (1) + /* TIM_CC2G field */ + #define TIM_CC2G (0x00000004u) + #define TIM_CC2G_MASK (0x00000004u) + #define TIM_CC2G_BIT (2) + #define TIM_CC2G_BITS (1) + /* TIM_CC1G field */ + #define TIM_CC1G (0x00000002u) + #define TIM_CC1G_MASK (0x00000002u) + #define TIM_CC1G_BIT (1) + #define TIM_CC1G_BITS (1) + /* TIM_UG field */ + #define TIM_UG (0x00000001u) + #define TIM_UG_MASK (0x00000001u) + #define TIM_UG_BIT (0) + #define TIM_UG_BITS (1) + +#define TIM1_CCMR1 *((volatile uint32_t *)0x4000E018u) +#define TIM1_CCMR1_REG *((volatile uint32_t *)0x4000E018u) +#define TIM1_CCMR1_ADDR (0x4000E018u) +#define TIM1_CCMR1_RESET (0x00000000u) + /* TIM_IC2F field */ + #define TIM_IC2F (0x0000F000u) + #define TIM_IC2F_MASK (0x0000F000u) + #define TIM_IC2F_BIT (12) + #define TIM_IC2F_BITS (4) + /* TIM_IC2PSC field */ + #define TIM_IC2PSC (0x00000C00u) + #define TIM_IC2PSC_MASK (0x00000C00u) + #define TIM_IC2PSC_BIT (10) + #define TIM_IC2PSC_BITS (2) + /* TIM_IC1F field */ + #define TIM_IC1F (0x000000F0u) + #define TIM_IC1F_MASK (0x000000F0u) + #define TIM_IC1F_BIT (4) + #define TIM_IC1F_BITS (4) + /* TIM_IC1PSC field */ + #define TIM_IC1PSC (0x0000000Cu) + #define TIM_IC1PSC_MASK (0x0000000Cu) + #define TIM_IC1PSC_BIT (2) + #define TIM_IC1PSC_BITS (2) + /* TIM_OC2CE field */ + #define TIM_OC2CE (0x00008000u) + #define TIM_OC2CE_MASK (0x00008000u) + #define TIM_OC2CE_BIT (15) + #define TIM_OC2CE_BITS (1) + /* TIM_OC2M field */ + #define TIM_OC2M (0x00007000u) + #define TIM_OC2M_MASK (0x00007000u) + #define TIM_OC2M_BIT (12) + #define TIM_OC2M_BITS (3) + /* TIM_OC2BE field */ + #define TIM_OC2BE (0x00000800u) + #define TIM_OC2BE_MASK (0x00000800u) + #define TIM_OC2BE_BIT (11) + #define TIM_OC2BE_BITS (1) + /* TIM_OC2FE field */ + #define TIM_OC2FE (0x00000400u) + #define TIM_OC2FE_MASK (0x00000400u) + #define TIM_OC2FE_BIT (10) + #define TIM_OC2FE_BITS (1) + /* TIM_CC2S field */ + #define TIM_CC2S (0x00000300u) + #define TIM_CC2S_MASK (0x00000300u) + #define TIM_CC2S_BIT (8) + #define TIM_CC2S_BITS (2) + /* TIM_OC1CE field */ + #define TIM_OC1CE (0x00000080u) + #define TIM_OC1CE_MASK (0x00000080u) + #define TIM_OC1CE_BIT (7) + #define TIM_OC1CE_BITS (1) + /* TIM_OC1M field */ + #define TIM_OC1M (0x00000070u) + #define TIM_OC1M_MASK (0x00000070u) + #define TIM_OC1M_BIT (4) + #define TIM_OC1M_BITS (3) + /* TIM_OC1PE field */ + #define TIM_OC1PE (0x00000008u) + #define TIM_OC1PE_MASK (0x00000008u) + #define TIM_OC1PE_BIT (3) + #define TIM_OC1PE_BITS (1) + /* TIM_OC1FE field */ + #define TIM_OC1FE (0x00000004u) + #define TIM_OC1FE_MASK (0x00000004u) + #define TIM_OC1FE_BIT (2) + #define TIM_OC1FE_BITS (1) + /* TIM_CC1S field */ + #define TIM_CC1S (0x00000003u) + #define TIM_CC1S_MASK (0x00000003u) + #define TIM_CC1S_BIT (0) + #define TIM_CC1S_BITS (2) + +#define TIM1_CCMR2 *((volatile uint32_t *)0x4000E01Cu) +#define TIM1_CCMR2_REG *((volatile uint32_t *)0x4000E01Cu) +#define TIM1_CCMR2_ADDR (0x4000E01Cu) +#define TIM1_CCMR2_RESET (0x00000000u) + /* TIM_IC4F field */ + #define TIM_IC4F (0x0000F000u) + #define TIM_IC4F_MASK (0x0000F000u) + #define TIM_IC4F_BIT (12) + #define TIM_IC4F_BITS (4) + /* TIM_IC4PSC field */ + #define TIM_IC4PSC (0x00000C00u) + #define TIM_IC4PSC_MASK (0x00000C00u) + #define TIM_IC4PSC_BIT (10) + #define TIM_IC4PSC_BITS (2) + /* TIM_IC3F field */ + #define TIM_IC3F (0x000000F0u) + #define TIM_IC3F_MASK (0x000000F0u) + #define TIM_IC3F_BIT (4) + #define TIM_IC3F_BITS (4) + /* TIM_IC3PSC field */ + #define TIM_IC3PSC (0x0000000Cu) + #define TIM_IC3PSC_MASK (0x0000000Cu) + #define TIM_IC3PSC_BIT (2) + #define TIM_IC3PSC_BITS (2) + /* TIM_OC4CE field */ + #define TIM_OC4CE (0x00008000u) + #define TIM_OC4CE_MASK (0x00008000u) + #define TIM_OC4CE_BIT (15) + #define TIM_OC4CE_BITS (1) + /* TIM_OC4M field */ + #define TIM_OC4M (0x00007000u) + #define TIM_OC4M_MASK (0x00007000u) + #define TIM_OC4M_BIT (12) + #define TIM_OC4M_BITS (3) + /* TIM_OC4BE field */ + #define TIM_OC4BE (0x00000800u) + #define TIM_OC4BE_MASK (0x00000800u) + #define TIM_OC4BE_BIT (11) + #define TIM_OC4BE_BITS (1) + /* TIM_OC4FE field */ + #define TIM_OC4FE (0x00000400u) + #define TIM_OC4FE_MASK (0x00000400u) + #define TIM_OC4FE_BIT (10) + #define TIM_OC4FE_BITS (1) + /* TIM_CC4S field */ + #define TIM_CC4S (0x00000300u) + #define TIM_CC4S_MASK (0x00000300u) + #define TIM_CC4S_BIT (8) + #define TIM_CC4S_BITS (2) + /* TIM_OC3CE field */ + #define TIM_OC3CE (0x00000080u) + #define TIM_OC3CE_MASK (0x00000080u) + #define TIM_OC3CE_BIT (7) + #define TIM_OC3CE_BITS (1) + /* TIM_OC3M field */ + #define TIM_OC3M (0x00000070u) + #define TIM_OC3M_MASK (0x00000070u) + #define TIM_OC3M_BIT (4) + #define TIM_OC3M_BITS (3) + /* TIM_OC3BE field */ + #define TIM_OC3BE (0x00000008u) + #define TIM_OC3BE_MASK (0x00000008u) + #define TIM_OC3BE_BIT (3) + #define TIM_OC3BE_BITS (1) + /* TIM_OC3FE field */ + #define TIM_OC3FE (0x00000004u) + #define TIM_OC3FE_MASK (0x00000004u) + #define TIM_OC3FE_BIT (2) + #define TIM_OC3FE_BITS (1) + /* TIM_CC3S field */ + #define TIM_CC3S (0x00000003u) + #define TIM_CC3S_MASK (0x00000003u) + #define TIM_CC3S_BIT (0) + #define TIM_CC3S_BITS (2) + +#define TIM1_CCER *((volatile uint32_t *)0x4000E020u) +#define TIM1_CCER_REG *((volatile uint32_t *)0x4000E020u) +#define TIM1_CCER_ADDR (0x4000E020u) +#define TIM1_CCER_RESET (0x00000000u) + /* TIM_CC4P field */ + #define TIM_CC4P (0x00002000u) + #define TIM_CC4P_MASK (0x00002000u) + #define TIM_CC4P_BIT (13) + #define TIM_CC4P_BITS (1) + /* TIM_CC4E field */ + #define TIM_CC4E (0x00001000u) + #define TIM_CC4E_MASK (0x00001000u) + #define TIM_CC4E_BIT (12) + #define TIM_CC4E_BITS (1) + /* TIM_CC3P field */ + #define TIM_CC3P (0x00000200u) + #define TIM_CC3P_MASK (0x00000200u) + #define TIM_CC3P_BIT (9) + #define TIM_CC3P_BITS (1) + /* TIM_CC3E field */ + #define TIM_CC3E (0x00000100u) + #define TIM_CC3E_MASK (0x00000100u) + #define TIM_CC3E_BIT (8) + #define TIM_CC3E_BITS (1) + /* TIM_CC2P field */ + #define TIM_CC2P (0x00000020u) + #define TIM_CC2P_MASK (0x00000020u) + #define TIM_CC2P_BIT (5) + #define TIM_CC2P_BITS (1) + /* TIM_CC2E field */ + #define TIM_CC2E (0x00000010u) + #define TIM_CC2E_MASK (0x00000010u) + #define TIM_CC2E_BIT (4) + #define TIM_CC2E_BITS (1) + /* TIM_CC1P field */ + #define TIM_CC1P (0x00000002u) + #define TIM_CC1P_MASK (0x00000002u) + #define TIM_CC1P_BIT (1) + #define TIM_CC1P_BITS (1) + /* TIM_CC1E field */ + #define TIM_CC1E (0x00000001u) + #define TIM_CC1E_MASK (0x00000001u) + #define TIM_CC1E_BIT (0) + #define TIM_CC1E_BITS (1) + +#define TIM1_CNT *((volatile uint32_t *)0x4000E024u) +#define TIM1_CNT_REG *((volatile uint32_t *)0x4000E024u) +#define TIM1_CNT_ADDR (0x4000E024u) +#define TIM1_CNT_RESET (0x00000000u) + /* TIM_CNT field */ + #define TIM_CNT (0x0000FFFFu) + #define TIM_CNT_MASK (0x0000FFFFu) + #define TIM_CNT_BIT (0) + #define TIM_CNT_BITS (16) + +#define TIM1_PSC *((volatile uint32_t *)0x4000E028u) +#define TIM1_PSC_REG *((volatile uint32_t *)0x4000E028u) +#define TIM1_PSC_ADDR (0x4000E028u) +#define TIM1_PSC_RESET (0x00000000u) + /* TIM_PSC field */ + #define TIM_PSC (0x0000000Fu) + #define TIM_PSC_MASK (0x0000000Fu) + #define TIM_PSC_BIT (0) + #define TIM_PSC_BITS (4) + +#define TIM1_ARR *((volatile uint32_t *)0x4000E02Cu) +#define TIM1_ARR_REG *((volatile uint32_t *)0x4000E02Cu) +#define TIM1_ARR_ADDR (0x4000E02Cu) +#define TIM1_ARR_RESET (0x0000FFFFu) + /* TIM_ARR field */ + #define TIM_ARR (0x0000FFFFu) + #define TIM_ARR_MASK (0x0000FFFFu) + #define TIM_ARR_BIT (0) + #define TIM_ARR_BITS (16) + +#define TIM1_CCR1 *((volatile uint32_t *)0x4000E034u) +#define TIM1_CCR1_REG *((volatile uint32_t *)0x4000E034u) +#define TIM1_CCR1_ADDR (0x4000E034u) +#define TIM1_CCR1_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_CCR2 *((volatile uint32_t *)0x4000E038u) +#define TIM1_CCR2_REG *((volatile uint32_t *)0x4000E038u) +#define TIM1_CCR2_ADDR (0x4000E038u) +#define TIM1_CCR2_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_CCR3 *((volatile uint32_t *)0x4000E03Cu) +#define TIM1_CCR3_REG *((volatile uint32_t *)0x4000E03Cu) +#define TIM1_CCR3_ADDR (0x4000E03Cu) +#define TIM1_CCR3_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_CCR4 *((volatile uint32_t *)0x4000E040u) +#define TIM1_CCR4_REG *((volatile uint32_t *)0x4000E040u) +#define TIM1_CCR4_ADDR (0x4000E040u) +#define TIM1_CCR4_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM1_OR *((volatile uint32_t *)0x4000E050u) +#define TIM1_OR_REG *((volatile uint32_t *)0x4000E050u) +#define TIM1_OR_ADDR (0x4000E050u) +#define TIM1_OR_RESET (0x00000000u) + /* TIM_ORRSVD field */ + #define TIM_ORRSVD (0x00000008u) + #define TIM_ORRSVD_MASK (0x00000008u) + #define TIM_ORRSVD_BIT (3) + #define TIM_ORRSVD_BITS (1) + /* TIM_CLKMSKEN field */ + #define TIM_CLKMSKEN (0x00000004u) + #define TIM_CLKMSKEN_MASK (0x00000004u) + #define TIM_CLKMSKEN_BIT (2) + #define TIM_CLKMSKEN_BITS (1) + /* TIM1_EXTRIGSEL field */ + #define TIM1_EXTRIGSEL (0x00000003u) + #define TIM1_EXTRIGSEL_MASK (0x00000003u) + #define TIM1_EXTRIGSEL_BIT (0) + #define TIM1_EXTRIGSEL_BITS (2) + +/* TIM2 block */ +#define BLOCK_TIM2_BASE (0x4000F000u) +#define BLOCK_TIM2_END (0x4000F050u) +#define BLOCK_TIM2_SIZE (BLOCK_TIM2_END - BLOCK_TIM2_BASE + 1) + +#define TIM2_CR1 *((volatile uint32_t *)0x4000F000u) +#define TIM2_CR1_REG *((volatile uint32_t *)0x4000F000u) +#define TIM2_CR1_ADDR (0x4000F000u) +#define TIM2_CR1_RESET (0x00000000u) + /* TIM_ARBE field */ + #define TIM_ARBE (0x00000080u) + #define TIM_ARBE_MASK (0x00000080u) + #define TIM_ARBE_BIT (7) + #define TIM_ARBE_BITS (1) + /* TIM_CMS field */ + #define TIM_CMS (0x00000060u) + #define TIM_CMS_MASK (0x00000060u) + #define TIM_CMS_BIT (5) + #define TIM_CMS_BITS (2) + /* TIM_DIR field */ + #define TIM_DIR (0x00000010u) + #define TIM_DIR_MASK (0x00000010u) + #define TIM_DIR_BIT (4) + #define TIM_DIR_BITS (1) + /* TIM_OPM field */ + #define TIM_OPM (0x00000008u) + #define TIM_OPM_MASK (0x00000008u) + #define TIM_OPM_BIT (3) + #define TIM_OPM_BITS (1) + /* TIM_URS field */ + #define TIM_URS (0x00000004u) + #define TIM_URS_MASK (0x00000004u) + #define TIM_URS_BIT (2) + #define TIM_URS_BITS (1) + /* TIM_UDIS field */ + #define TIM_UDIS (0x00000002u) + #define TIM_UDIS_MASK (0x00000002u) + #define TIM_UDIS_BIT (1) + #define TIM_UDIS_BITS (1) + /* TIM_CEN field */ + #define TIM_CEN (0x00000001u) + #define TIM_CEN_MASK (0x00000001u) + #define TIM_CEN_BIT (0) + #define TIM_CEN_BITS (1) + +#define TIM2_CR2 *((volatile uint32_t *)0x4000F004u) +#define TIM2_CR2_REG *((volatile uint32_t *)0x4000F004u) +#define TIM2_CR2_ADDR (0x4000F004u) +#define TIM2_CR2_RESET (0x00000000u) + /* TIM_TI1S field */ + #define TIM_TI1S (0x00000080u) + #define TIM_TI1S_MASK (0x00000080u) + #define TIM_TI1S_BIT (7) + #define TIM_TI1S_BITS (1) + /* TIM_MMS field */ + #define TIM_MMS (0x00000070u) + #define TIM_MMS_MASK (0x00000070u) + #define TIM_MMS_BIT (4) + #define TIM_MMS_BITS (3) + +#define TIM2_SMCR *((volatile uint32_t *)0x4000F008u) +#define TIM2_SMCR_REG *((volatile uint32_t *)0x4000F008u) +#define TIM2_SMCR_ADDR (0x4000F008u) +#define TIM2_SMCR_RESET (0x00000000u) + /* TIM_ETP field */ + #define TIM_ETP (0x00008000u) + #define TIM_ETP_MASK (0x00008000u) + #define TIM_ETP_BIT (15) + #define TIM_ETP_BITS (1) + /* TIM_ECE field */ + #define TIM_ECE (0x00004000u) + #define TIM_ECE_MASK (0x00004000u) + #define TIM_ECE_BIT (14) + #define TIM_ECE_BITS (1) + /* TIM_ETPS field */ + #define TIM_ETPS (0x00003000u) + #define TIM_ETPS_MASK (0x00003000u) + #define TIM_ETPS_BIT (12) + #define TIM_ETPS_BITS (2) + /* TIM_ETF field */ + #define TIM_ETF (0x00000F00u) + #define TIM_ETF_MASK (0x00000F00u) + #define TIM_ETF_BIT (8) + #define TIM_ETF_BITS (4) + /* TIM_MSM field */ + #define TIM_MSM (0x00000080u) + #define TIM_MSM_MASK (0x00000080u) + #define TIM_MSM_BIT (7) + #define TIM_MSM_BITS (1) + /* TIM_TS field */ + #define TIM_TS (0x00000070u) + #define TIM_TS_MASK (0x00000070u) + #define TIM_TS_BIT (4) + #define TIM_TS_BITS (3) + /* TIM_SMS field */ + #define TIM_SMS (0x00000007u) + #define TIM_SMS_MASK (0x00000007u) + #define TIM_SMS_BIT (0) + #define TIM_SMS_BITS (3) + +#define TMR2_DIER *((volatile uint32_t *)0x4000F00Cu) +#define TMR2_DIER_REG *((volatile uint32_t *)0x4000F00Cu) +#define TMR2_DIER_ADDR (0x4000F00Cu) +#define TMR2_DIER_RESET (0x00000000u) + /* TIE field */ + #define TMR2_DIER_TIE (0x00000040u) + #define TMR2_DIER_TIE_MASK (0x00000040u) + #define TMR2_DIER_TIE_BIT (6) + #define TMR2_DIER_TIE_BITS (1) + /* CC4IE field */ + #define TMR2_DIER_CC4IE (0x00000010u) + #define TMR2_DIER_CC4IE_MASK (0x00000010u) + #define TMR2_DIER_CC4IE_BIT (4) + #define TMR2_DIER_CC4IE_BITS (1) + /* CC3IE field */ + #define TMR2_DIER_CC3IE (0x00000008u) + #define TMR2_DIER_CC3IE_MASK (0x00000008u) + #define TMR2_DIER_CC3IE_BIT (3) + #define TMR2_DIER_CC3IE_BITS (1) + /* CC2IE field */ + #define TMR2_DIER_CC2IE (0x00000004u) + #define TMR2_DIER_CC2IE_MASK (0x00000004u) + #define TMR2_DIER_CC2IE_BIT (2) + #define TMR2_DIER_CC2IE_BITS (1) + /* CC1IE field */ + #define TMR2_DIER_CC1IE (0x00000002u) + #define TMR2_DIER_CC1IE_MASK (0x00000002u) + #define TMR2_DIER_CC1IE_BIT (1) + #define TMR2_DIER_CC1IE_BITS (1) + /* UIE field */ + #define TMR2_DIER_UIE (0x00000001u) + #define TMR2_DIER_UIE_MASK (0x00000001u) + #define TMR2_DIER_UIE_BIT (0) + #define TMR2_DIER_UIE_BITS (1) + +#define TMR2_SR *((volatile uint32_t *)0x4000F010u) +#define TMR2_SR_REG *((volatile uint32_t *)0x4000F010u) +#define TMR2_SR_ADDR (0x4000F010u) +#define TMR2_SR_RESET (0x00000000u) + /* CC4OF field */ + #define TMR2_SR_CC4OF (0x00001000u) + #define TMR2_SR_CC4OF_MASK (0x00001000u) + #define TMR2_SR_CC4OF_BIT (12) + #define TMR2_SR_CC4OF_BITS (1) + /* CC3OF field */ + #define TMR2_SR_CC3OF (0x00000800u) + #define TMR2_SR_CC3OF_MASK (0x00000800u) + #define TMR2_SR_CC3OF_BIT (11) + #define TMR2_SR_CC3OF_BITS (1) + /* CC2OF field */ + #define TMR2_SR_CC2OF (0x00000400u) + #define TMR2_SR_CC2OF_MASK (0x00000400u) + #define TMR2_SR_CC2OF_BIT (10) + #define TMR2_SR_CC2OF_BITS (1) + /* CC1OF field */ + #define TMR2_SR_CC1OF (0x00000200u) + #define TMR2_SR_CC1OF_MASK (0x00000200u) + #define TMR2_SR_CC1OF_BIT (9) + #define TMR2_SR_CC1OF_BITS (1) + /* TIF field */ + #define TMR2_SR_TIF (0x00000040u) + #define TMR2_SR_TIF_MASK (0x00000040u) + #define TMR2_SR_TIF_BIT (6) + #define TMR2_SR_TIF_BITS (1) + /* CC4IF field */ + #define TMR2_SR_CC4IF (0x00000010u) + #define TMR2_SR_CC4IF_MASK (0x00000010u) + #define TMR2_SR_CC4IF_BIT (4) + #define TMR2_SR_CC4IF_BITS (1) + /* CC3IF field */ + #define TMR2_SR_CC3IF (0x00000008u) + #define TMR2_SR_CC3IF_MASK (0x00000008u) + #define TMR2_SR_CC3IF_BIT (3) + #define TMR2_SR_CC3IF_BITS (1) + /* CC2IF field */ + #define TMR2_SR_CC2IF (0x00000004u) + #define TMR2_SR_CC2IF_MASK (0x00000004u) + #define TMR2_SR_CC2IF_BIT (2) + #define TMR2_SR_CC2IF_BITS (1) + /* CC1IF field */ + #define TMR2_SR_CC1IF (0x00000002u) + #define TMR2_SR_CC1IF_MASK (0x00000002u) + #define TMR2_SR_CC1IF_BIT (1) + #define TMR2_SR_CC1IF_BITS (1) + /* UIF field */ + #define TMR2_SR_UIF (0x00000001u) + #define TMR2_SR_UIF_MASK (0x00000001u) + #define TMR2_SR_UIF_BIT (0) + #define TMR2_SR_UIF_BITS (1) + +#define TIM2_EGR *((volatile uint32_t *)0x4000F014u) +#define TIM2_EGR_REG *((volatile uint32_t *)0x4000F014u) +#define TIM2_EGR_ADDR (0x4000F014u) +#define TIM2_EGR_RESET (0x00000000u) + /* TIM_TG field */ + #define TIM_TG (0x00000040u) + #define TIM_TG_MASK (0x00000040u) + #define TIM_TG_BIT (6) + #define TIM_TG_BITS (1) + /* TIM_CC4G field */ + #define TIM_CC4G (0x00000010u) + #define TIM_CC4G_MASK (0x00000010u) + #define TIM_CC4G_BIT (4) + #define TIM_CC4G_BITS (1) + /* TIM_CC3G field */ + #define TIM_CC3G (0x00000008u) + #define TIM_CC3G_MASK (0x00000008u) + #define TIM_CC3G_BIT (3) + #define TIM_CC3G_BITS (1) + /* TIM_CC2G field */ + #define TIM_CC2G (0x00000004u) + #define TIM_CC2G_MASK (0x00000004u) + #define TIM_CC2G_BIT (2) + #define TIM_CC2G_BITS (1) + /* TIM_CC1G field */ + #define TIM_CC1G (0x00000002u) + #define TIM_CC1G_MASK (0x00000002u) + #define TIM_CC1G_BIT (1) + #define TIM_CC1G_BITS (1) + /* TIM_UG field */ + #define TIM_UG (0x00000001u) + #define TIM_UG_MASK (0x00000001u) + #define TIM_UG_BIT (0) + #define TIM_UG_BITS (1) + +#define TIM2_CCMR1 *((volatile uint32_t *)0x4000F018u) +#define TIM2_CCMR1_REG *((volatile uint32_t *)0x4000F018u) +#define TIM2_CCMR1_ADDR (0x4000F018u) +#define TIM2_CCMR1_RESET (0x00000000u) + /* TIM_IC2F field */ + #define TIM_IC2F (0x0000F000u) + #define TIM_IC2F_MASK (0x0000F000u) + #define TIM_IC2F_BIT (12) + #define TIM_IC2F_BITS (4) + /* TIM_IC2PSC field */ + #define TIM_IC2PSC (0x00000C00u) + #define TIM_IC2PSC_MASK (0x00000C00u) + #define TIM_IC2PSC_BIT (10) + #define TIM_IC2PSC_BITS (2) + /* TIM_IC1F field */ + #define TIM_IC1F (0x000000F0u) + #define TIM_IC1F_MASK (0x000000F0u) + #define TIM_IC1F_BIT (4) + #define TIM_IC1F_BITS (4) + /* TIM_IC1PSC field */ + #define TIM_IC1PSC (0x0000000Cu) + #define TIM_IC1PSC_MASK (0x0000000Cu) + #define TIM_IC1PSC_BIT (2) + #define TIM_IC1PSC_BITS (2) + /* TIM_OC2CE field */ + #define TIM_OC2CE (0x00008000u) + #define TIM_OC2CE_MASK (0x00008000u) + #define TIM_OC2CE_BIT (15) + #define TIM_OC2CE_BITS (1) + /* TIM_OC2M field */ + #define TIM_OC2M (0x00007000u) + #define TIM_OC2M_MASK (0x00007000u) + #define TIM_OC2M_BIT (12) + #define TIM_OC2M_BITS (3) + /* TIM_OC2BE field */ + #define TIM_OC2BE (0x00000800u) + #define TIM_OC2BE_MASK (0x00000800u) + #define TIM_OC2BE_BIT (11) + #define TIM_OC2BE_BITS (1) + /* TIM_OC2FE field */ + #define TIM_OC2FE (0x00000400u) + #define TIM_OC2FE_MASK (0x00000400u) + #define TIM_OC2FE_BIT (10) + #define TIM_OC2FE_BITS (1) + /* TIM_CC2S field */ + #define TIM_CC2S (0x00000300u) + #define TIM_CC2S_MASK (0x00000300u) + #define TIM_CC2S_BIT (8) + #define TIM_CC2S_BITS (2) + /* TIM_OC1CE field */ + #define TIM_OC1CE (0x00000080u) + #define TIM_OC1CE_MASK (0x00000080u) + #define TIM_OC1CE_BIT (7) + #define TIM_OC1CE_BITS (1) + /* TIM_OC1M field */ + #define TIM_OC1M (0x00000070u) + #define TIM_OC1M_MASK (0x00000070u) + #define TIM_OC1M_BIT (4) + #define TIM_OC1M_BITS (3) + /* TIM_OC1PE field */ + #define TIM_OC1PE (0x00000008u) + #define TIM_OC1PE_MASK (0x00000008u) + #define TIM_OC1PE_BIT (3) + #define TIM_OC1PE_BITS (1) + /* TIM_OC1FE field */ + #define TIM_OC1FE (0x00000004u) + #define TIM_OC1FE_MASK (0x00000004u) + #define TIM_OC1FE_BIT (2) + #define TIM_OC1FE_BITS (1) + /* TIM_CC1S field */ + #define TIM_CC1S (0x00000003u) + #define TIM_CC1S_MASK (0x00000003u) + #define TIM_CC1S_BIT (0) + #define TIM_CC1S_BITS (2) + +#define TIM2_CCMR2 *((volatile uint32_t *)0x4000F01Cu) +#define TIM2_CCMR2_REG *((volatile uint32_t *)0x4000F01Cu) +#define TIM2_CCMR2_ADDR (0x4000F01Cu) +#define TIM2_CCMR2_RESET (0x00000000u) + /* TIM_IC4F field */ + #define TIM_IC4F (0x0000F000u) + #define TIM_IC4F_MASK (0x0000F000u) + #define TIM_IC4F_BIT (12) + #define TIM_IC4F_BITS (4) + /* TIM_IC4PSC field */ + #define TIM_IC4PSC (0x00000C00u) + #define TIM_IC4PSC_MASK (0x00000C00u) + #define TIM_IC4PSC_BIT (10) + #define TIM_IC4PSC_BITS (2) + /* TIM_IC3F field */ + #define TIM_IC3F (0x000000F0u) + #define TIM_IC3F_MASK (0x000000F0u) + #define TIM_IC3F_BIT (4) + #define TIM_IC3F_BITS (4) + /* TIM_IC3PSC field */ + #define TIM_IC3PSC (0x0000000Cu) + #define TIM_IC3PSC_MASK (0x0000000Cu) + #define TIM_IC3PSC_BIT (2) + #define TIM_IC3PSC_BITS (2) + /* TIM_OC4CE field */ + #define TIM_OC4CE (0x00008000u) + #define TIM_OC4CE_MASK (0x00008000u) + #define TIM_OC4CE_BIT (15) + #define TIM_OC4CE_BITS (1) + /* TIM_OC4M field */ + #define TIM_OC4M (0x00007000u) + #define TIM_OC4M_MASK (0x00007000u) + #define TIM_OC4M_BIT (12) + #define TIM_OC4M_BITS (3) + /* TIM_OC4BE field */ + #define TIM_OC4BE (0x00000800u) + #define TIM_OC4BE_MASK (0x00000800u) + #define TIM_OC4BE_BIT (11) + #define TIM_OC4BE_BITS (1) + /* TIM_OC4FE field */ + #define TIM_OC4FE (0x00000400u) + #define TIM_OC4FE_MASK (0x00000400u) + #define TIM_OC4FE_BIT (10) + #define TIM_OC4FE_BITS (1) + /* TIM_CC4S field */ + #define TIM_CC4S (0x00000300u) + #define TIM_CC4S_MASK (0x00000300u) + #define TIM_CC4S_BIT (8) + #define TIM_CC4S_BITS (2) + /* TIM_OC3CE field */ + #define TIM_OC3CE (0x00000080u) + #define TIM_OC3CE_MASK (0x00000080u) + #define TIM_OC3CE_BIT (7) + #define TIM_OC3CE_BITS (1) + /* TIM_OC3M field */ + #define TIM_OC3M (0x00000070u) + #define TIM_OC3M_MASK (0x00000070u) + #define TIM_OC3M_BIT (4) + #define TIM_OC3M_BITS (3) + /* TIM_OC3BE field */ + #define TIM_OC3BE (0x00000008u) + #define TIM_OC3BE_MASK (0x00000008u) + #define TIM_OC3BE_BIT (3) + #define TIM_OC3BE_BITS (1) + /* TIM_OC3FE field */ + #define TIM_OC3FE (0x00000004u) + #define TIM_OC3FE_MASK (0x00000004u) + #define TIM_OC3FE_BIT (2) + #define TIM_OC3FE_BITS (1) + /* TIM_CC3S field */ + #define TIM_CC3S (0x00000003u) + #define TIM_CC3S_MASK (0x00000003u) + #define TIM_CC3S_BIT (0) + #define TIM_CC3S_BITS (2) + +#define TIM2_CCER *((volatile uint32_t *)0x4000F020u) +#define TIM2_CCER_REG *((volatile uint32_t *)0x4000F020u) +#define TIM2_CCER_ADDR (0x4000F020u) +#define TIM2_CCER_RESET (0x00000000u) + /* TIM_CC4P field */ + #define TIM_CC4P (0x00002000u) + #define TIM_CC4P_MASK (0x00002000u) + #define TIM_CC4P_BIT (13) + #define TIM_CC4P_BITS (1) + /* TIM_CC4E field */ + #define TIM_CC4E (0x00001000u) + #define TIM_CC4E_MASK (0x00001000u) + #define TIM_CC4E_BIT (12) + #define TIM_CC4E_BITS (1) + /* TIM_CC3P field */ + #define TIM_CC3P (0x00000200u) + #define TIM_CC3P_MASK (0x00000200u) + #define TIM_CC3P_BIT (9) + #define TIM_CC3P_BITS (1) + /* TIM_CC3E field */ + #define TIM_CC3E (0x00000100u) + #define TIM_CC3E_MASK (0x00000100u) + #define TIM_CC3E_BIT (8) + #define TIM_CC3E_BITS (1) + /* TIM_CC2P field */ + #define TIM_CC2P (0x00000020u) + #define TIM_CC2P_MASK (0x00000020u) + #define TIM_CC2P_BIT (5) + #define TIM_CC2P_BITS (1) + /* TIM_CC2E field */ + #define TIM_CC2E (0x00000010u) + #define TIM_CC2E_MASK (0x00000010u) + #define TIM_CC2E_BIT (4) + #define TIM_CC2E_BITS (1) + /* TIM_CC1P field */ + #define TIM_CC1P (0x00000002u) + #define TIM_CC1P_MASK (0x00000002u) + #define TIM_CC1P_BIT (1) + #define TIM_CC1P_BITS (1) + /* TIM_CC1E field */ + #define TIM_CC1E (0x00000001u) + #define TIM_CC1E_MASK (0x00000001u) + #define TIM_CC1E_BIT (0) + #define TIM_CC1E_BITS (1) + +#define TIM2_CNT *((volatile uint32_t *)0x4000F024u) +#define TIM2_CNT_REG *((volatile uint32_t *)0x4000F024u) +#define TIM2_CNT_ADDR (0x4000F024u) +#define TIM2_CNT_RESET (0x00000000u) + /* TIM_CNT field */ + #define TIM_CNT (0x0000FFFFu) + #define TIM_CNT_MASK (0x0000FFFFu) + #define TIM_CNT_BIT (0) + #define TIM_CNT_BITS (16) + +#define TIM2_PSC *((volatile uint32_t *)0x4000F028u) +#define TIM2_PSC_REG *((volatile uint32_t *)0x4000F028u) +#define TIM2_PSC_ADDR (0x4000F028u) +#define TIM2_PSC_RESET (0x00000000u) + /* TIM_PSC field */ + #define TIM_PSC (0x0000000Fu) + #define TIM_PSC_MASK (0x0000000Fu) + #define TIM_PSC_BIT (0) + #define TIM_PSC_BITS (4) + +#define TIM2_ARR *((volatile uint32_t *)0x4000F02Cu) +#define TIM2_ARR_REG *((volatile uint32_t *)0x4000F02Cu) +#define TIM2_ARR_ADDR (0x4000F02Cu) +#define TIM2_ARR_RESET (0x0000FFFFu) + /* TIM_ARR field */ + #define TIM_ARR (0x0000FFFFu) + #define TIM_ARR_MASK (0x0000FFFFu) + #define TIM_ARR_BIT (0) + #define TIM_ARR_BITS (16) + +#define TIM2_CCR1 *((volatile uint32_t *)0x4000F034u) +#define TIM2_CCR1_REG *((volatile uint32_t *)0x4000F034u) +#define TIM2_CCR1_ADDR (0x4000F034u) +#define TIM2_CCR1_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_CCR2 *((volatile uint32_t *)0x4000F038u) +#define TIM2_CCR2_REG *((volatile uint32_t *)0x4000F038u) +#define TIM2_CCR2_ADDR (0x4000F038u) +#define TIM2_CCR2_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_CCR3 *((volatile uint32_t *)0x4000F03Cu) +#define TIM2_CCR3_REG *((volatile uint32_t *)0x4000F03Cu) +#define TIM2_CCR3_ADDR (0x4000F03Cu) +#define TIM2_CCR3_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_CCR4 *((volatile uint32_t *)0x4000F040u) +#define TIM2_CCR4_REG *((volatile uint32_t *)0x4000F040u) +#define TIM2_CCR4_ADDR (0x4000F040u) +#define TIM2_CCR4_RESET (0x00000000u) + /* TIM_CCR field */ + #define TIM_CCR (0x0000FFFFu) + #define TIM_CCR_MASK (0x0000FFFFu) + #define TIM_CCR_BIT (0) + #define TIM_CCR_BITS (16) + +#define TIM2_OR *((volatile uint32_t *)0x4000F050u) +#define TIM2_OR_REG *((volatile uint32_t *)0x4000F050u) +#define TIM2_OR_ADDR (0x4000F050u) +#define TIM2_OR_RESET (0x00000000u) + /* TIM_REMAPC4 field */ + #define TIM_REMAPC4 (0x00000080u) + #define TIM_REMAPC4_MASK (0x00000080u) + #define TIM_REMAPC4_BIT (7) + #define TIM_REMAPC4_BITS (1) + /* TIM_REMAPC3 field */ + #define TIM_REMAPC3 (0x00000040u) + #define TIM_REMAPC3_MASK (0x00000040u) + #define TIM_REMAPC3_BIT (6) + #define TIM_REMAPC3_BITS (1) + /* TIM_REMAPC2 field */ + #define TIM_REMAPC2 (0x00000020u) + #define TIM_REMAPC2_MASK (0x00000020u) + #define TIM_REMAPC2_BIT (5) + #define TIM_REMAPC2_BITS (1) + /* TIM_REMAPC1 field */ + #define TIM_REMAPC1 (0x00000010u) + #define TIM_REMAPC1_MASK (0x00000010u) + #define TIM_REMAPC1_BIT (4) + #define TIM_REMAPC1_BITS (1) + /* TIM_ORRSVD field */ + #define TIM_ORRSVD (0x00000008u) + #define TIM_ORRSVD_MASK (0x00000008u) + #define TIM_ORRSVD_BIT (3) + #define TIM_ORRSVD_BITS (1) + /* TIM_CLKMSKEN field */ + #define TIM_CLKMSKEN (0x00000004u) + #define TIM_CLKMSKEN_MASK (0x00000004u) + #define TIM_CLKMSKEN_BIT (2) + #define TIM_CLKMSKEN_BITS (1) + /* TIM1_EXTRIGSEL field */ + #define TIM1_EXTRIGSEL (0x00000003u) + #define TIM1_EXTRIGSEL_MASK (0x00000003u) + #define TIM1_EXTRIGSEL_BIT (0) + #define TIM1_EXTRIGSEL_BITS (2) + +/* EXT_RAM block */ +#define DATA_EXT_RAM_BASE (0x60000000u) +#define DATA_EXT_RAM_END (0x9FFFFFFFu) +#define DATA_EXT_RAM_SIZE (DATA_EXT_RAM_END - DATA_EXT_RAM_BASE + 1) + +/* EXT_DEVICE block */ +#define DATA_EXT_DEVICE_BASE (0xA0000000u) +#define DATA_EXT_DEVICE_END (0xDFFFFFFFu) +#define DATA_EXT_DEVICE_SIZE (DATA_EXT_DEVICE_END - DATA_EXT_DEVICE_BASE + 1) + +/* ITM block */ +#define DATA_ITM_BASE (0xE0000000u) +#define DATA_ITM_END (0xE0000FFFu) +#define DATA_ITM_SIZE (DATA_ITM_END - DATA_ITM_BASE + 1) + +#define ITM_SP0 *((volatile uint32_t *)0xE0000000u) +#define ITM_SP0_REG *((volatile uint32_t *)0xE0000000u) +#define ITM_SP0_ADDR (0xE0000000u) +#define ITM_SP0_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP0_FIFOREADY (0x00000001u) + #define ITM_SP0_FIFOREADY_MASK (0x00000001u) + #define ITM_SP0_FIFOREADY_BIT (0) + #define ITM_SP0_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP0_STIMULUS (0xFFFFFFFFu) + #define ITM_SP0_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP0_STIMULUS_BIT (0) + #define ITM_SP0_STIMULUS_BITS (32) + +#define ITM_SP1 *((volatile uint32_t *)0xE0000004u) +#define ITM_SP1_REG *((volatile uint32_t *)0xE0000004u) +#define ITM_SP1_ADDR (0xE0000004u) +#define ITM_SP1_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP1_FIFOREADY (0x00000001u) + #define ITM_SP1_FIFOREADY_MASK (0x00000001u) + #define ITM_SP1_FIFOREADY_BIT (0) + #define ITM_SP1_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP1_STIMULUS (0xFFFFFFFFu) + #define ITM_SP1_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP1_STIMULUS_BIT (0) + #define ITM_SP1_STIMULUS_BITS (32) + +#define ITM_SP2 *((volatile uint32_t *)0xE0000008u) +#define ITM_SP2_REG *((volatile uint32_t *)0xE0000008u) +#define ITM_SP2_ADDR (0xE0000008u) +#define ITM_SP2_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP2_FIFOREADY (0x00000001u) + #define ITM_SP2_FIFOREADY_MASK (0x00000001u) + #define ITM_SP2_FIFOREADY_BIT (0) + #define ITM_SP2_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP2_STIMULUS (0xFFFFFFFFu) + #define ITM_SP2_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP2_STIMULUS_BIT (0) + #define ITM_SP2_STIMULUS_BITS (32) + +#define ITM_SP3 *((volatile uint32_t *)0xE000000Cu) +#define ITM_SP3_REG *((volatile uint32_t *)0xE000000Cu) +#define ITM_SP3_ADDR (0xE000000Cu) +#define ITM_SP3_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP3_FIFOREADY (0x00000001u) + #define ITM_SP3_FIFOREADY_MASK (0x00000001u) + #define ITM_SP3_FIFOREADY_BIT (0) + #define ITM_SP3_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP3_STIMULUS (0xFFFFFFFFu) + #define ITM_SP3_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP3_STIMULUS_BIT (0) + #define ITM_SP3_STIMULUS_BITS (32) + +#define ITM_SP4 *((volatile uint32_t *)0xE0000010u) +#define ITM_SP4_REG *((volatile uint32_t *)0xE0000010u) +#define ITM_SP4_ADDR (0xE0000010u) +#define ITM_SP4_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP4_FIFOREADY (0x00000001u) + #define ITM_SP4_FIFOREADY_MASK (0x00000001u) + #define ITM_SP4_FIFOREADY_BIT (0) + #define ITM_SP4_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP4_STIMULUS (0xFFFFFFFFu) + #define ITM_SP4_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP4_STIMULUS_BIT (0) + #define ITM_SP4_STIMULUS_BITS (32) + +#define ITM_SP5 *((volatile uint32_t *)0xE0000014u) +#define ITM_SP5_REG *((volatile uint32_t *)0xE0000014u) +#define ITM_SP5_ADDR (0xE0000014u) +#define ITM_SP5_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP5_FIFOREADY (0x00000001u) + #define ITM_SP5_FIFOREADY_MASK (0x00000001u) + #define ITM_SP5_FIFOREADY_BIT (0) + #define ITM_SP5_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP5_STIMULUS (0xFFFFFFFFu) + #define ITM_SP5_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP5_STIMULUS_BIT (0) + #define ITM_SP5_STIMULUS_BITS (32) + +#define ITM_SP6 *((volatile uint32_t *)0xE0000018u) +#define ITM_SP6_REG *((volatile uint32_t *)0xE0000018u) +#define ITM_SP6_ADDR (0xE0000018u) +#define ITM_SP6_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP6_FIFOREADY (0x00000001u) + #define ITM_SP6_FIFOREADY_MASK (0x00000001u) + #define ITM_SP6_FIFOREADY_BIT (0) + #define ITM_SP6_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP6_STIMULUS (0xFFFFFFFFu) + #define ITM_SP6_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP6_STIMULUS_BIT (0) + #define ITM_SP6_STIMULUS_BITS (32) + +#define ITM_SP7 *((volatile uint32_t *)0xE000001Cu) +#define ITM_SP7_REG *((volatile uint32_t *)0xE000001Cu) +#define ITM_SP7_ADDR (0xE000001Cu) +#define ITM_SP7_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP7_FIFOREADY (0x00000001u) + #define ITM_SP7_FIFOREADY_MASK (0x00000001u) + #define ITM_SP7_FIFOREADY_BIT (0) + #define ITM_SP7_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP7_STIMULUS (0xFFFFFFFFu) + #define ITM_SP7_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP7_STIMULUS_BIT (0) + #define ITM_SP7_STIMULUS_BITS (32) + +#define ITM_SP8 *((volatile uint32_t *)0xE0000020u) +#define ITM_SP8_REG *((volatile uint32_t *)0xE0000020u) +#define ITM_SP8_ADDR (0xE0000020u) +#define ITM_SP8_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP8_FIFOREADY (0x00000001u) + #define ITM_SP8_FIFOREADY_MASK (0x00000001u) + #define ITM_SP8_FIFOREADY_BIT (0) + #define ITM_SP8_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP8_STIMULUS (0xFFFFFFFFu) + #define ITM_SP8_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP8_STIMULUS_BIT (0) + #define ITM_SP8_STIMULUS_BITS (32) + +#define ITM_SP9 *((volatile uint32_t *)0xE0000024u) +#define ITM_SP9_REG *((volatile uint32_t *)0xE0000024u) +#define ITM_SP9_ADDR (0xE0000024u) +#define ITM_SP9_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP9_FIFOREADY (0x00000001u) + #define ITM_SP9_FIFOREADY_MASK (0x00000001u) + #define ITM_SP9_FIFOREADY_BIT (0) + #define ITM_SP9_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP9_STIMULUS (0xFFFFFFFFu) + #define ITM_SP9_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP9_STIMULUS_BIT (0) + #define ITM_SP9_STIMULUS_BITS (32) + +#define ITM_SP10 *((volatile uint32_t *)0xE0000028u) +#define ITM_SP10_REG *((volatile uint32_t *)0xE0000028u) +#define ITM_SP10_ADDR (0xE0000028u) +#define ITM_SP10_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP10_FIFOREADY (0x00000001u) + #define ITM_SP10_FIFOREADY_MASK (0x00000001u) + #define ITM_SP10_FIFOREADY_BIT (0) + #define ITM_SP10_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP10_STIMULUS (0xFFFFFFFFu) + #define ITM_SP10_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP10_STIMULUS_BIT (0) + #define ITM_SP10_STIMULUS_BITS (32) + +#define ITM_SP11 *((volatile uint32_t *)0xE000002Cu) +#define ITM_SP11_REG *((volatile uint32_t *)0xE000002Cu) +#define ITM_SP11_ADDR (0xE000002Cu) +#define ITM_SP11_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP11_FIFOREADY (0x00000001u) + #define ITM_SP11_FIFOREADY_MASK (0x00000001u) + #define ITM_SP11_FIFOREADY_BIT (0) + #define ITM_SP11_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP11_STIMULUS (0xFFFFFFFFu) + #define ITM_SP11_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP11_STIMULUS_BIT (0) + #define ITM_SP11_STIMULUS_BITS (32) + +#define ITM_SP12 *((volatile uint32_t *)0xE0000030u) +#define ITM_SP12_REG *((volatile uint32_t *)0xE0000030u) +#define ITM_SP12_ADDR (0xE0000030u) +#define ITM_SP12_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP12_FIFOREADY (0x00000001u) + #define ITM_SP12_FIFOREADY_MASK (0x00000001u) + #define ITM_SP12_FIFOREADY_BIT (0) + #define ITM_SP12_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP12_STIMULUS (0xFFFFFFFFu) + #define ITM_SP12_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP12_STIMULUS_BIT (0) + #define ITM_SP12_STIMULUS_BITS (32) + +#define ITM_SP13 *((volatile uint32_t *)0xE0000034u) +#define ITM_SP13_REG *((volatile uint32_t *)0xE0000034u) +#define ITM_SP13_ADDR (0xE0000034u) +#define ITM_SP13_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP13_FIFOREADY (0x00000001u) + #define ITM_SP13_FIFOREADY_MASK (0x00000001u) + #define ITM_SP13_FIFOREADY_BIT (0) + #define ITM_SP13_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP13_STIMULUS (0xFFFFFFFFu) + #define ITM_SP13_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP13_STIMULUS_BIT (0) + #define ITM_SP13_STIMULUS_BITS (32) + +#define ITM_SP14 *((volatile uint32_t *)0xE0000038u) +#define ITM_SP14_REG *((volatile uint32_t *)0xE0000038u) +#define ITM_SP14_ADDR (0xE0000038u) +#define ITM_SP14_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP14_FIFOREADY (0x00000001u) + #define ITM_SP14_FIFOREADY_MASK (0x00000001u) + #define ITM_SP14_FIFOREADY_BIT (0) + #define ITM_SP14_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP14_STIMULUS (0xFFFFFFFFu) + #define ITM_SP14_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP14_STIMULUS_BIT (0) + #define ITM_SP14_STIMULUS_BITS (32) + +#define ITM_SP15 *((volatile uint32_t *)0xE000003Cu) +#define ITM_SP15_REG *((volatile uint32_t *)0xE000003Cu) +#define ITM_SP15_ADDR (0xE000003Cu) +#define ITM_SP15_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP15_FIFOREADY (0x00000001u) + #define ITM_SP15_FIFOREADY_MASK (0x00000001u) + #define ITM_SP15_FIFOREADY_BIT (0) + #define ITM_SP15_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP15_STIMULUS (0xFFFFFFFFu) + #define ITM_SP15_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP15_STIMULUS_BIT (0) + #define ITM_SP15_STIMULUS_BITS (32) + +#define ITM_SP16 *((volatile uint32_t *)0xE0000040u) +#define ITM_SP16_REG *((volatile uint32_t *)0xE0000040u) +#define ITM_SP16_ADDR (0xE0000040u) +#define ITM_SP16_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP16_FIFOREADY (0x00000001u) + #define ITM_SP16_FIFOREADY_MASK (0x00000001u) + #define ITM_SP16_FIFOREADY_BIT (0) + #define ITM_SP16_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP16_STIMULUS (0xFFFFFFFFu) + #define ITM_SP16_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP16_STIMULUS_BIT (0) + #define ITM_SP16_STIMULUS_BITS (32) + +#define ITM_SP17 *((volatile uint32_t *)0xE0000044u) +#define ITM_SP17_REG *((volatile uint32_t *)0xE0000044u) +#define ITM_SP17_ADDR (0xE0000044u) +#define ITM_SP17_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP17_FIFOREADY (0x00000001u) + #define ITM_SP17_FIFOREADY_MASK (0x00000001u) + #define ITM_SP17_FIFOREADY_BIT (0) + #define ITM_SP17_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP17_STIMULUS (0xFFFFFFFFu) + #define ITM_SP17_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP17_STIMULUS_BIT (0) + #define ITM_SP17_STIMULUS_BITS (32) + +#define ITM_SP18 *((volatile uint32_t *)0xE0000048u) +#define ITM_SP18_REG *((volatile uint32_t *)0xE0000048u) +#define ITM_SP18_ADDR (0xE0000048u) +#define ITM_SP18_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP18_FIFOREADY (0x00000001u) + #define ITM_SP18_FIFOREADY_MASK (0x00000001u) + #define ITM_SP18_FIFOREADY_BIT (0) + #define ITM_SP18_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP18_STIMULUS (0xFFFFFFFFu) + #define ITM_SP18_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP18_STIMULUS_BIT (0) + #define ITM_SP18_STIMULUS_BITS (32) + +#define ITM_SP19 *((volatile uint32_t *)0xE000004Cu) +#define ITM_SP19_REG *((volatile uint32_t *)0xE000004Cu) +#define ITM_SP19_ADDR (0xE000004Cu) +#define ITM_SP19_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP19_FIFOREADY (0x00000001u) + #define ITM_SP19_FIFOREADY_MASK (0x00000001u) + #define ITM_SP19_FIFOREADY_BIT (0) + #define ITM_SP19_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP19_STIMULUS (0xFFFFFFFFu) + #define ITM_SP19_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP19_STIMULUS_BIT (0) + #define ITM_SP19_STIMULUS_BITS (32) + +#define ITM_SP20 *((volatile uint32_t *)0xE0000050u) +#define ITM_SP20_REG *((volatile uint32_t *)0xE0000050u) +#define ITM_SP20_ADDR (0xE0000050u) +#define ITM_SP20_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP20_FIFOREADY (0x00000001u) + #define ITM_SP20_FIFOREADY_MASK (0x00000001u) + #define ITM_SP20_FIFOREADY_BIT (0) + #define ITM_SP20_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP20_STIMULUS (0xFFFFFFFFu) + #define ITM_SP20_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP20_STIMULUS_BIT (0) + #define ITM_SP20_STIMULUS_BITS (32) + +#define ITM_SP21 *((volatile uint32_t *)0xE0000054u) +#define ITM_SP21_REG *((volatile uint32_t *)0xE0000054u) +#define ITM_SP21_ADDR (0xE0000054u) +#define ITM_SP21_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP21_FIFOREADY (0x00000001u) + #define ITM_SP21_FIFOREADY_MASK (0x00000001u) + #define ITM_SP21_FIFOREADY_BIT (0) + #define ITM_SP21_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP21_STIMULUS (0xFFFFFFFFu) + #define ITM_SP21_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP21_STIMULUS_BIT (0) + #define ITM_SP21_STIMULUS_BITS (32) + +#define ITM_SP22 *((volatile uint32_t *)0xE0000058u) +#define ITM_SP22_REG *((volatile uint32_t *)0xE0000058u) +#define ITM_SP22_ADDR (0xE0000058u) +#define ITM_SP22_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP22_FIFOREADY (0x00000001u) + #define ITM_SP22_FIFOREADY_MASK (0x00000001u) + #define ITM_SP22_FIFOREADY_BIT (0) + #define ITM_SP22_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP22_STIMULUS (0xFFFFFFFFu) + #define ITM_SP22_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP22_STIMULUS_BIT (0) + #define ITM_SP22_STIMULUS_BITS (32) + +#define ITM_SP23 *((volatile uint32_t *)0xE000005Cu) +#define ITM_SP23_REG *((volatile uint32_t *)0xE000005Cu) +#define ITM_SP23_ADDR (0xE000005Cu) +#define ITM_SP23_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP23_FIFOREADY (0x00000001u) + #define ITM_SP23_FIFOREADY_MASK (0x00000001u) + #define ITM_SP23_FIFOREADY_BIT (0) + #define ITM_SP23_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP23_STIMULUS (0xFFFFFFFFu) + #define ITM_SP23_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP23_STIMULUS_BIT (0) + #define ITM_SP23_STIMULUS_BITS (32) + +#define ITM_SP24 *((volatile uint32_t *)0xE0000060u) +#define ITM_SP24_REG *((volatile uint32_t *)0xE0000060u) +#define ITM_SP24_ADDR (0xE0000060u) +#define ITM_SP24_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP24_FIFOREADY (0x00000001u) + #define ITM_SP24_FIFOREADY_MASK (0x00000001u) + #define ITM_SP24_FIFOREADY_BIT (0) + #define ITM_SP24_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP24_STIMULUS (0xFFFFFFFFu) + #define ITM_SP24_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP24_STIMULUS_BIT (0) + #define ITM_SP24_STIMULUS_BITS (32) + +#define ITM_SP25 *((volatile uint32_t *)0xE0000064u) +#define ITM_SP25_REG *((volatile uint32_t *)0xE0000064u) +#define ITM_SP25_ADDR (0xE0000064u) +#define ITM_SP25_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP25_FIFOREADY (0x00000001u) + #define ITM_SP25_FIFOREADY_MASK (0x00000001u) + #define ITM_SP25_FIFOREADY_BIT (0) + #define ITM_SP25_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP25_STIMULUS (0xFFFFFFFFu) + #define ITM_SP25_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP25_STIMULUS_BIT (0) + #define ITM_SP25_STIMULUS_BITS (32) + +#define ITM_SP26 *((volatile uint32_t *)0xE0000068u) +#define ITM_SP26_REG *((volatile uint32_t *)0xE0000068u) +#define ITM_SP26_ADDR (0xE0000068u) +#define ITM_SP26_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP26_FIFOREADY (0x00000001u) + #define ITM_SP26_FIFOREADY_MASK (0x00000001u) + #define ITM_SP26_FIFOREADY_BIT (0) + #define ITM_SP26_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP26_STIMULUS (0xFFFFFFFFu) + #define ITM_SP26_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP26_STIMULUS_BIT (0) + #define ITM_SP26_STIMULUS_BITS (32) + +#define ITM_SP27 *((volatile uint32_t *)0xE000006Cu) +#define ITM_SP27_REG *((volatile uint32_t *)0xE000006Cu) +#define ITM_SP27_ADDR (0xE000006Cu) +#define ITM_SP27_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP27_FIFOREADY (0x00000001u) + #define ITM_SP27_FIFOREADY_MASK (0x00000001u) + #define ITM_SP27_FIFOREADY_BIT (0) + #define ITM_SP27_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP27_STIMULUS (0xFFFFFFFFu) + #define ITM_SP27_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP27_STIMULUS_BIT (0) + #define ITM_SP27_STIMULUS_BITS (32) + +#define ITM_SP28 *((volatile uint32_t *)0xE0000070u) +#define ITM_SP28_REG *((volatile uint32_t *)0xE0000070u) +#define ITM_SP28_ADDR (0xE0000070u) +#define ITM_SP28_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP28_FIFOREADY (0x00000001u) + #define ITM_SP28_FIFOREADY_MASK (0x00000001u) + #define ITM_SP28_FIFOREADY_BIT (0) + #define ITM_SP28_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP28_STIMULUS (0xFFFFFFFFu) + #define ITM_SP28_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP28_STIMULUS_BIT (0) + #define ITM_SP28_STIMULUS_BITS (32) + +#define ITM_SP29 *((volatile uint32_t *)0xE0000074u) +#define ITM_SP29_REG *((volatile uint32_t *)0xE0000074u) +#define ITM_SP29_ADDR (0xE0000074u) +#define ITM_SP29_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP29_FIFOREADY (0x00000001u) + #define ITM_SP29_FIFOREADY_MASK (0x00000001u) + #define ITM_SP29_FIFOREADY_BIT (0) + #define ITM_SP29_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP29_STIMULUS (0xFFFFFFFFu) + #define ITM_SP29_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP29_STIMULUS_BIT (0) + #define ITM_SP29_STIMULUS_BITS (32) + +#define ITM_SP30 *((volatile uint32_t *)0xE0000078u) +#define ITM_SP30_REG *((volatile uint32_t *)0xE0000078u) +#define ITM_SP30_ADDR (0xE0000078u) +#define ITM_SP30_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP30_FIFOREADY (0x00000001u) + #define ITM_SP30_FIFOREADY_MASK (0x00000001u) + #define ITM_SP30_FIFOREADY_BIT (0) + #define ITM_SP30_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP30_STIMULUS (0xFFFFFFFFu) + #define ITM_SP30_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP30_STIMULUS_BIT (0) + #define ITM_SP30_STIMULUS_BITS (32) + +#define ITM_SP31 *((volatile uint32_t *)0xE000007Cu) +#define ITM_SP31_REG *((volatile uint32_t *)0xE000007Cu) +#define ITM_SP31_ADDR (0xE000007Cu) +#define ITM_SP31_RESET (0x00000000u) + /* FIFOREADY field */ + #define ITM_SP31_FIFOREADY (0x00000001u) + #define ITM_SP31_FIFOREADY_MASK (0x00000001u) + #define ITM_SP31_FIFOREADY_BIT (0) + #define ITM_SP31_FIFOREADY_BITS (1) + /* STIMULUS field */ + #define ITM_SP31_STIMULUS (0xFFFFFFFFu) + #define ITM_SP31_STIMULUS_MASK (0xFFFFFFFFu) + #define ITM_SP31_STIMULUS_BIT (0) + #define ITM_SP31_STIMULUS_BITS (32) + +#define ITM_TER *((volatile uint32_t *)0xE0000E00u) +#define ITM_TER_REG *((volatile uint32_t *)0xE0000E00u) +#define ITM_TER_ADDR (0xE0000E00u) +#define ITM_TER_RESET (0x00000000u) + /* STIMENA field */ + #define ITM_TER_STIMENA (0xFFFFFFFFu) + #define ITM_TER_STIMENA_MASK (0xFFFFFFFFu) + #define ITM_TER_STIMENA_BIT (0) + #define ITM_TER_STIMENA_BITS (32) + +#define ITM_TPR *((volatile uint32_t *)0xE0000E40u) +#define ITM_TPR_REG *((volatile uint32_t *)0xE0000E40u) +#define ITM_TPR_ADDR (0xE0000E40u) +#define ITM_TPR_RESET (0x00000000u) + /* PRIVMASK field */ + #define ITM_TPR_PRIVMASK (0x0000000Fu) + #define ITM_TPR_PRIVMASK_MASK (0x0000000Fu) + #define ITM_TPR_PRIVMASK_BIT (0) + #define ITM_TPR_PRIVMASK_BITS (4) + +#define ITM_TCR *((volatile uint32_t *)0xE0000E80u) +#define ITM_TCR_REG *((volatile uint32_t *)0xE0000E80u) +#define ITM_TCR_ADDR (0xE0000E80u) +#define ITM_TCR_RESET (0x00000000u) + /* BUSY field */ + #define ITM_TCR_BUSY (0x00800000u) + #define ITM_TCR_BUSY_MASK (0x00800000u) + #define ITM_TCR_BUSY_BIT (23) + #define ITM_TCR_BUSY_BITS (1) + /* ATBID field */ + #define ITM_TCR_ATBID (0x007F0000u) + #define ITM_TCR_ATBID_MASK (0x007F0000u) + #define ITM_TCR_ATBID_BIT (16) + #define ITM_TCR_ATBID_BITS (7) + /* TSPRESCALE field */ + #define ITM_TCR_TSPRESCALE (0x00000300u) + #define ITM_TCR_TSPRESCALE_MASK (0x00000300u) + #define ITM_TCR_TSPRESCALE_BIT (8) + #define ITM_TCR_TSPRESCALE_BITS (2) + /* SWOENA field */ + #define ITM_TCR_SWOENA (0x00000010u) + #define ITM_TCR_SWOENA_MASK (0x00000010u) + #define ITM_TCR_SWOENA_BIT (4) + #define ITM_TCR_SWOENA_BITS (1) + /* DWTENA field */ + #define ITM_TCR_DWTENA (0x00000008u) + #define ITM_TCR_DWTENA_MASK (0x00000008u) + #define ITM_TCR_DWTENA_BIT (3) + #define ITM_TCR_DWTENA_BITS (1) + /* SYNCENA field */ + #define ITM_TCR_SYNCENA (0x00000004u) + #define ITM_TCR_SYNCENA_MASK (0x00000004u) + #define ITM_TCR_SYNCENA_BIT (2) + #define ITM_TCR_SYNCENA_BITS (1) + /* TSENA field */ + #define ITM_TCR_TSENA (0x00000002u) + #define ITM_TCR_TSENA_MASK (0x00000002u) + #define ITM_TCR_TSENA_BIT (1) + #define ITM_TCR_TSENA_BITS (1) + /* ITMEN field */ + #define ITM_TCR_ITMEN (0x00000001u) + #define ITM_TCR_ITMEN_MASK (0x00000001u) + #define ITM_TCR_ITMEN_BIT (0) + #define ITM_TCR_ITMEN_BITS (1) + +#define ITM_IW *((volatile uint32_t *)0xE0000EF8u) +#define ITM_IW_REG *((volatile uint32_t *)0xE0000EF8u) +#define ITM_IW_ADDR (0xE0000EF8u) +#define ITM_IW_RESET (0x00000000u) + /* ATVALIDM field */ + #define ITM_IW_ATVALIDM (0x00000001u) + #define ITM_IW_ATVALIDM_MASK (0x00000001u) + #define ITM_IW_ATVALIDM_BIT (0) + #define ITM_IW_ATVALIDM_BITS (1) + +#define ITM_IR *((volatile uint32_t *)0xE0000EFCu) +#define ITM_IR_REG *((volatile uint32_t *)0xE0000EFCu) +#define ITM_IR_ADDR (0xE0000EFCu) +#define ITM_IR_RESET (0x00000000u) + /* ATREADYM field */ + #define ITM_IR_ATREADYM (0x00000001u) + #define ITM_IR_ATREADYM_MASK (0x00000001u) + #define ITM_IR_ATREADYM_BIT (0) + #define ITM_IR_ATREADYM_BITS (1) + +#define ITM_IMC *((volatile uint32_t *)0xE0000F00u) +#define ITM_IMC_REG *((volatile uint32_t *)0xE0000F00u) +#define ITM_IMC_ADDR (0xE0000F00u) +#define ITM_IMC_RESET (0x00000000u) + /* INTEGRATION field */ + #define ITM_IMC_INTEGRATION (0x00000001u) + #define ITM_IMC_INTEGRATION_MASK (0x00000001u) + #define ITM_IMC_INTEGRATION_BIT (0) + #define ITM_IMC_INTEGRATION_BITS (1) + +#define ITM_LA *((volatile uint32_t *)0xE0000FB0u) +#define ITM_LA_REG *((volatile uint32_t *)0xE0000FB0u) +#define ITM_LA_ADDR (0xE0000FB0u) +#define ITM_LA_RESET (0x00000000u) + /* LOCKACC field */ + #define ITM_LA_LOCKACC (0xFFFFFFFFu) + #define ITM_LA_LOCKACC_MASK (0xFFFFFFFFu) + #define ITM_LA_LOCKACC_BIT (0) + #define ITM_LA_LOCKACC_BITS (32) + +#define ITM_LS *((volatile uint32_t *)0xE0000FB4u) +#define ITM_LS_REG *((volatile uint32_t *)0xE0000FB4u) +#define ITM_LS_ADDR (0xE0000FB4u) +#define ITM_LS_RESET (0x00000000u) + /* BYTEACC field */ + #define ITM_LS_BYTEACC (0x00000004u) + #define ITM_LS_BYTEACC_MASK (0x00000004u) + #define ITM_LS_BYTEACC_BIT (2) + #define ITM_LS_BYTEACC_BITS (1) + /* ACCESS field */ + #define ITM_LS_ACCESS (0x00000002u) + #define ITM_LS_ACCESS_MASK (0x00000002u) + #define ITM_LS_ACCESS_BIT (1) + #define ITM_LS_ACCESS_BITS (1) + /* PRESENT field */ + #define ITM_LS_PRESENT (0x00000001u) + #define ITM_LS_PRESENT_MASK (0x00000001u) + #define ITM_LS_PRESENT_BIT (0) + #define ITM_LS_PRESENT_BITS (1) + +#define ITM_PERIPHID4 *((volatile uint32_t *)0xE0000FD0u) +#define ITM_PERIPHID4_REG *((volatile uint32_t *)0xE0000FD0u) +#define ITM_PERIPHID4_ADDR (0xE0000FD0u) +#define ITM_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define ITM_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID4_PERIPHID_BIT (0) + #define ITM_PERIPHID4_PERIPHID_BITS (32) + +#define ITM_PERIPHID5 *((volatile uint32_t *)0xE0000FD4u) +#define ITM_PERIPHID5_REG *((volatile uint32_t *)0xE0000FD4u) +#define ITM_PERIPHID5_ADDR (0xE0000FD4u) +#define ITM_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID5_PERIPHID_BIT (0) + #define ITM_PERIPHID5_PERIPHID_BITS (32) + +#define ITM_PERIPHID6 *((volatile uint32_t *)0xE0000FD8u) +#define ITM_PERIPHID6_REG *((volatile uint32_t *)0xE0000FD8u) +#define ITM_PERIPHID6_ADDR (0xE0000FD8u) +#define ITM_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID6_PERIPHID_BIT (0) + #define ITM_PERIPHID6_PERIPHID_BITS (32) + +#define ITM_PERIPHID7 *((volatile uint32_t *)0xE0000FDCu) +#define ITM_PERIPHID7_REG *((volatile uint32_t *)0xE0000FDCu) +#define ITM_PERIPHID7_ADDR (0xE0000FDCu) +#define ITM_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID7_PERIPHID_BIT (0) + #define ITM_PERIPHID7_PERIPHID_BITS (32) + +#define ITM_PERIPHID0 *((volatile uint32_t *)0xE0000FE0u) +#define ITM_PERIPHID0_REG *((volatile uint32_t *)0xE0000FE0u) +#define ITM_PERIPHID0_ADDR (0xE0000FE0u) +#define ITM_PERIPHID0_RESET (0x00000001u) + /* PERIPHID field */ + #define ITM_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID0_PERIPHID_BIT (0) + #define ITM_PERIPHID0_PERIPHID_BITS (32) + +#define ITM_PERIPHID1 *((volatile uint32_t *)0xE0000FE4u) +#define ITM_PERIPHID1_REG *((volatile uint32_t *)0xE0000FE4u) +#define ITM_PERIPHID1_ADDR (0xE0000FE4u) +#define ITM_PERIPHID1_RESET (0x000000B0u) + /* PERIPHID field */ + #define ITM_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID1_PERIPHID_BIT (0) + #define ITM_PERIPHID1_PERIPHID_BITS (32) + +#define ITM_PERIPHID2 *((volatile uint32_t *)0xE0000FE8u) +#define ITM_PERIPHID2_REG *((volatile uint32_t *)0xE0000FE8u) +#define ITM_PERIPHID2_ADDR (0xE0000FE8u) +#define ITM_PERIPHID2_RESET (0x0000001Bu) + /* PERIPHID field */ + #define ITM_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID2_PERIPHID_BIT (0) + #define ITM_PERIPHID2_PERIPHID_BITS (32) + +#define ITM_PERIPHID3 *((volatile uint32_t *)0xE0000FECu) +#define ITM_PERIPHID3_REG *((volatile uint32_t *)0xE0000FECu) +#define ITM_PERIPHID3_ADDR (0xE0000FECu) +#define ITM_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define ITM_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define ITM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_PERIPHID3_PERIPHID_BIT (0) + #define ITM_PERIPHID3_PERIPHID_BITS (32) + +#define ITM_CELLID0 *((volatile uint32_t *)0xE0000FF0u) +#define ITM_CELLID0_REG *((volatile uint32_t *)0xE0000FF0u) +#define ITM_CELLID0_ADDR (0xE0000FF0u) +#define ITM_CELLID0_RESET (0x0000000Du) + /* PERIPHID field */ + #define ITM_CELLID0_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID0_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID0_PERIPHID_BIT (0) + #define ITM_CELLID0_PERIPHID_BITS (32) + +#define ITM_CELLID1 *((volatile uint32_t *)0xE0000FF4u) +#define ITM_CELLID1_REG *((volatile uint32_t *)0xE0000FF4u) +#define ITM_CELLID1_ADDR (0xE0000FF4u) +#define ITM_CELLID1_RESET (0x000000E0u) + /* PERIPHID field */ + #define ITM_CELLID1_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID1_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID1_PERIPHID_BIT (0) + #define ITM_CELLID1_PERIPHID_BITS (32) + +#define ITM_CELLID2 *((volatile uint32_t *)0xE0000FF8u) +#define ITM_CELLID2_REG *((volatile uint32_t *)0xE0000FF8u) +#define ITM_CELLID2_ADDR (0xE0000FF8u) +#define ITM_CELLID2_RESET (0x00000005u) + /* PERIPHID field */ + #define ITM_CELLID2_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID2_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID2_PERIPHID_BIT (0) + #define ITM_CELLID2_PERIPHID_BITS (32) + +#define ITM_CELLID3 *((volatile uint32_t *)0xE0000FFCu) +#define ITM_CELLID3_REG *((volatile uint32_t *)0xE0000FFCu) +#define ITM_CELLID3_ADDR (0xE0000FFCu) +#define ITM_CELLID3_RESET (0x000000B1u) + /* PERIPHID field */ + #define ITM_CELLID3_PERIPHID (0xFFFFFFFFu) + #define ITM_CELLID3_PERIPHID_MASK (0xFFFFFFFFu) + #define ITM_CELLID3_PERIPHID_BIT (0) + #define ITM_CELLID3_PERIPHID_BITS (32) + +/* DWT block */ +#define DATA_DWT_BASE (0xE0001000u) +#define DATA_DWT_END (0xE0001FFFu) +#define DATA_DWT_SIZE (DATA_DWT_END - DATA_DWT_BASE + 1) + +#define DWT_CTRL *((volatile uint32_t *)0xE0001000u) +#define DWT_CTRL_REG *((volatile uint32_t *)0xE0001000u) +#define DWT_CTRL_ADDR (0xE0001000u) +#define DWT_CTRL_RESET (0x40000000u) + /* NUMCOMP field */ + #define DWT_CTRL_NUMCOMP (0xF0000000u) + #define DWT_CTRL_NUMCOMP_MASK (0xF0000000u) + #define DWT_CTRL_NUMCOMP_BIT (28) + #define DWT_CTRL_NUMCOMP_BITS (4) + /* CYCEVTENA field */ + #define DWT_CTRL_CYCEVTENA (0x00400000u) + #define DWT_CTRL_CYCEVTENA_MASK (0x00400000u) + #define DWT_CTRL_CYCEVTENA_BIT (22) + #define DWT_CTRL_CYCEVTENA_BITS (1) + /* FOLDEVTENA field */ + #define DWT_CTRL_FOLDEVTENA (0x00200000u) + #define DWT_CTRL_FOLDEVTENA_MASK (0x00200000u) + #define DWT_CTRL_FOLDEVTENA_BIT (21) + #define DWT_CTRL_FOLDEVTENA_BITS (1) + /* LSUEVTENA field */ + #define DWT_CTRL_LSUEVTENA (0x00100000u) + #define DWT_CTRL_LSUEVTENA_MASK (0x00100000u) + #define DWT_CTRL_LSUEVTENA_BIT (20) + #define DWT_CTRL_LSUEVTENA_BITS (1) + /* SLEEPEVTENA field */ + #define DWT_CTRL_SLEEPEVTENA (0x00080000u) + #define DWT_CTRL_SLEEPEVTENA_MASK (0x00080000u) + #define DWT_CTRL_SLEEPEVTENA_BIT (19) + #define DWT_CTRL_SLEEPEVTENA_BITS (1) + /* EXCEVTENA field */ + #define DWT_CTRL_EXCEVTENA (0x00040000u) + #define DWT_CTRL_EXCEVTENA_MASK (0x00040000u) + #define DWT_CTRL_EXCEVTENA_BIT (18) + #define DWT_CTRL_EXCEVTENA_BITS (1) + /* CPIEVTENA field */ + #define DWT_CTRL_CPIEVTENA (0x00020000u) + #define DWT_CTRL_CPIEVTENA_MASK (0x00020000u) + #define DWT_CTRL_CPIEVTENA_BIT (17) + #define DWT_CTRL_CPIEVTENA_BITS (1) + /* EXCTRCENA field */ + #define DWT_CTRL_EXCTRCENA (0x00010000u) + #define DWT_CTRL_EXCTRCENA_MASK (0x00010000u) + #define DWT_CTRL_EXCTRCENA_BIT (16) + #define DWT_CTRL_EXCTRCENA_BITS (1) + /* PCSAMPLEENA field */ + #define DWT_CTRL_PCSAMPLEENA (0x00001000u) + #define DWT_CTRL_PCSAMPLEENA_MASK (0x00001000u) + #define DWT_CTRL_PCSAMPLEENA_BIT (12) + #define DWT_CTRL_PCSAMPLEENA_BITS (1) + /* SYNCTAP field */ + #define DWT_CTRL_SYNCTAP (0x00000C00u) + #define DWT_CTRL_SYNCTAP_MASK (0x00000C00u) + #define DWT_CTRL_SYNCTAP_BIT (10) + #define DWT_CTRL_SYNCTAP_BITS (2) + /* CYCTAP field */ + #define DWT_CTRL_CYCTAP (0x00000200u) + #define DWT_CTRL_CYCTAP_MASK (0x00000200u) + #define DWT_CTRL_CYCTAP_BIT (9) + #define DWT_CTRL_CYCTAP_BITS (1) + /* POSTCNT field */ + #define DWT_CTRL_POSTCNT (0x000001E0u) + #define DWT_CTRL_POSTCNT_MASK (0x000001E0u) + #define DWT_CTRL_POSTCNT_BIT (5) + #define DWT_CTRL_POSTCNT_BITS (4) + /* POSTPRESET field */ + #define DWT_CTRL_POSTPRESET (0x0000001Eu) + #define DWT_CTRL_POSTPRESET_MASK (0x0000001Eu) + #define DWT_CTRL_POSTPRESET_BIT (1) + #define DWT_CTRL_POSTPRESET_BITS (4) + /* CYCCNTENA field */ + #define DWT_CTRL_CYCCNTENA (0x00000001u) + #define DWT_CTRL_CYCCNTENA_MASK (0x00000001u) + #define DWT_CTRL_CYCCNTENA_BIT (0) + #define DWT_CTRL_CYCCNTENA_BITS (1) + +#define DWT_CYCCNT *((volatile uint32_t *)0xE0001004u) +#define DWT_CYCCNT_REG *((volatile uint32_t *)0xE0001004u) +#define DWT_CYCCNT_ADDR (0xE0001004u) +#define DWT_CYCCNT_RESET (0x00000000u) + /* CYCCNT field */ + #define DWT_CYCCNT_CYCCNT (0xFFFFFFFFu) + #define DWT_CYCCNT_CYCCNT_MASK (0xFFFFFFFFu) + #define DWT_CYCCNT_CYCCNT_BIT (0) + #define DWT_CYCCNT_CYCCNT_BITS (32) + +#define DWT_CPICNT *((volatile uint32_t *)0xE0001008u) +#define DWT_CPICNT_REG *((volatile uint32_t *)0xE0001008u) +#define DWT_CPICNT_ADDR (0xE0001008u) +#define DWT_CPICNT_RESET (0x00000000u) + /* CPICNT field */ + #define DWT_CPICNT_CPICNT (0x000000FFu) + #define DWT_CPICNT_CPICNT_MASK (0x000000FFu) + #define DWT_CPICNT_CPICNT_BIT (0) + #define DWT_CPICNT_CPICNT_BITS (8) + +#define DWT_EXCCNT *((volatile uint32_t *)0xE000100Cu) +#define DWT_EXCCNT_REG *((volatile uint32_t *)0xE000100Cu) +#define DWT_EXCCNT_ADDR (0xE000100Cu) +#define DWT_EXCCNT_RESET (0x00000000u) + /* EXCCNT field */ + #define DWT_EXCCNT_EXCCNT (0x000000FFu) + #define DWT_EXCCNT_EXCCNT_MASK (0x000000FFu) + #define DWT_EXCCNT_EXCCNT_BIT (0) + #define DWT_EXCCNT_EXCCNT_BITS (8) + +#define DWT_SLEEPCNT *((volatile uint32_t *)0xE0001010u) +#define DWT_SLEEPCNT_REG *((volatile uint32_t *)0xE0001010u) +#define DWT_SLEEPCNT_ADDR (0xE0001010u) +#define DWT_SLEEPCNT_RESET (0x00000000u) + /* SLEEPCNT field */ + #define DWT_SLEEPCNT_SLEEPCNT (0x000000FFu) + #define DWT_SLEEPCNT_SLEEPCNT_MASK (0x000000FFu) + #define DWT_SLEEPCNT_SLEEPCNT_BIT (0) + #define DWT_SLEEPCNT_SLEEPCNT_BITS (8) + +#define DWT_LSUCNT *((volatile uint32_t *)0xE0001014u) +#define DWT_LSUCNT_REG *((volatile uint32_t *)0xE0001014u) +#define DWT_LSUCNT_ADDR (0xE0001014u) +#define DWT_LSUCNT_RESET (0x00000000u) + /* CPICNT field */ + #define DWT_LSUCNT_CPICNT (0x000000FFu) + #define DWT_LSUCNT_CPICNT_MASK (0x000000FFu) + #define DWT_LSUCNT_CPICNT_BIT (0) + #define DWT_LSUCNT_CPICNT_BITS (8) + +#define DWT_FOLDCNT *((volatile uint32_t *)0xE0001018u) +#define DWT_FOLDCNT_REG *((volatile uint32_t *)0xE0001018u) +#define DWT_FOLDCNT_ADDR (0xE0001018u) +#define DWT_FOLDCNT_RESET (0x00000000u) + /* CPICNT field */ + #define DWT_FOLDCNT_CPICNT (0x000000FFu) + #define DWT_FOLDCNT_CPICNT_MASK (0x000000FFu) + #define DWT_FOLDCNT_CPICNT_BIT (0) + #define DWT_FOLDCNT_CPICNT_BITS (8) + +#define DWT_PCSR *((volatile uint32_t *)0xE000101Cu) +#define DWT_PCSR_REG *((volatile uint32_t *)0xE000101Cu) +#define DWT_PCSR_ADDR (0xE000101Cu) +#define DWT_PCSR_RESET (0x00000000u) + /* EIASAMPLE field */ + #define DWT_PCSR_EIASAMPLE (0xFFFFFFFFu) + #define DWT_PCSR_EIASAMPLE_MASK (0xFFFFFFFFu) + #define DWT_PCSR_EIASAMPLE_BIT (0) + #define DWT_PCSR_EIASAMPLE_BITS (32) + +#define DWT_COMP0 *((volatile uint32_t *)0xE0001020u) +#define DWT_COMP0_REG *((volatile uint32_t *)0xE0001020u) +#define DWT_COMP0_ADDR (0xE0001020u) +#define DWT_COMP0_RESET (0x00000000u) + /* COMP0 field */ + #define DWT_COMP0_COMP0 (0xFFFFFFFFu) + #define DWT_COMP0_COMP0_MASK (0xFFFFFFFFu) + #define DWT_COMP0_COMP0_BIT (0) + #define DWT_COMP0_COMP0_BITS (32) + +#define DWT_MASK0 *((volatile uint32_t *)0xE0001024u) +#define DWT_MASK0_REG *((volatile uint32_t *)0xE0001024u) +#define DWT_MASK0_ADDR (0xE0001024u) +#define DWT_MASK0_RESET (0x00000000u) + /* MASK0 field */ + #define DWT_MASK0_MASK0 (0x0000001Fu) + #define DWT_MASK0_MASK0_MASK (0x0000001Fu) + #define DWT_MASK0_MASK0_BIT (0) + #define DWT_MASK0_MASK0_BITS (5) + +#define DWT_FUNCTION0 *((volatile uint32_t *)0xE0001028u) +#define DWT_FUNCTION0_REG *((volatile uint32_t *)0xE0001028u) +#define DWT_FUNCTION0_ADDR (0xE0001028u) +#define DWT_FUNCTION0_RESET (0x00000000u) + /* MATCHED field */ + #define DWT_FUNCTION0_MATCHED (0x01000000u) + #define DWT_FUNCTION0_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION0_MATCHED_BIT (24) + #define DWT_FUNCTION0_MATCHED_BITS (1) + /* CYCMATCH field */ + #define DWT_FUNCTION0_CYCMATCH (0x00000080u) + #define DWT_FUNCTION0_CYCMATCH_MASK (0x00000080u) + #define DWT_FUNCTION0_CYCMATCH_BIT (7) + #define DWT_FUNCTION0_CYCMATCH_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION0_EMITRANGE (0x00000020u) + #define DWT_FUNCTION0_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION0_EMITRANGE_BIT (5) + #define DWT_FUNCTION0_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION0_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION0_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION0_FUNCTION_BIT (0) + #define DWT_FUNCTION0_FUNCTION_BITS (4) + +#define DWT_COMP1 *((volatile uint32_t *)0xE0001030u) +#define DWT_COMP1_REG *((volatile uint32_t *)0xE0001030u) +#define DWT_COMP1_ADDR (0xE0001030u) +#define DWT_COMP1_RESET (0x00000000u) + /* COMP1 field */ + #define DWT_COMP1_COMP1 (0xFFFFFFFFu) + #define DWT_COMP1_COMP1_MASK (0xFFFFFFFFu) + #define DWT_COMP1_COMP1_BIT (0) + #define DWT_COMP1_COMP1_BITS (32) + +#define DWT_MASK1 *((volatile uint32_t *)0xE0001034u) +#define DWT_MASK1_REG *((volatile uint32_t *)0xE0001034u) +#define DWT_MASK1_ADDR (0xE0001034u) +#define DWT_MASK1_RESET (0x00000000u) + /* MASK1 field */ + #define DWT_MASK1_MASK1 (0x0000001Fu) + #define DWT_MASK1_MASK1_MASK (0x0000001Fu) + #define DWT_MASK1_MASK1_BIT (0) + #define DWT_MASK1_MASK1_BITS (5) + +#define DWT_FUNCTION1 *((volatile uint32_t *)0xE0001038u) +#define DWT_FUNCTION1_REG *((volatile uint32_t *)0xE0001038u) +#define DWT_FUNCTION1_ADDR (0xE0001038u) +#define DWT_FUNCTION1_RESET (0x00000200u) + /* MATCHED field */ + #define DWT_FUNCTION1_MATCHED (0x01000000u) + #define DWT_FUNCTION1_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION1_MATCHED_BIT (24) + #define DWT_FUNCTION1_MATCHED_BITS (1) + /* DATAVADDR1 field */ + #define DWT_FUNCTION1_DATAVADDR1 (0x000F0000u) + #define DWT_FUNCTION1_DATAVADDR1_MASK (0x000F0000u) + #define DWT_FUNCTION1_DATAVADDR1_BIT (16) + #define DWT_FUNCTION1_DATAVADDR1_BITS (4) + /* DATAVADDR0 field */ + #define DWT_FUNCTION1_DATAVADDR0 (0x0000F000u) + #define DWT_FUNCTION1_DATAVADDR0_MASK (0x0000F000u) + #define DWT_FUNCTION1_DATAVADDR0_BIT (12) + #define DWT_FUNCTION1_DATAVADDR0_BITS (4) + /* DATAVSIZE field */ + #define DWT_FUNCTION1_DATAVSIZE (0x00000C00u) + #define DWT_FUNCTION1_DATAVSIZE_MASK (0x00000C00u) + #define DWT_FUNCTION1_DATAVSIZE_BIT (10) + #define DWT_FUNCTION1_DATAVSIZE_BITS (2) + /* LNK1ENA field */ + #define DWT_FUNCTION1_LNK1ENA (0x00000200u) + #define DWT_FUNCTION1_LNK1ENA_MASK (0x00000200u) + #define DWT_FUNCTION1_LNK1ENA_BIT (9) + #define DWT_FUNCTION1_LNK1ENA_BITS (1) + /* DATAVMATCH field */ + #define DWT_FUNCTION1_DATAVMATCH (0x00000100u) + #define DWT_FUNCTION1_DATAVMATCH_MASK (0x00000100u) + #define DWT_FUNCTION1_DATAVMATCH_BIT (8) + #define DWT_FUNCTION1_DATAVMATCH_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION1_EMITRANGE (0x00000020u) + #define DWT_FUNCTION1_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION1_EMITRANGE_BIT (5) + #define DWT_FUNCTION1_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION1_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION1_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION1_FUNCTION_BIT (0) + #define DWT_FUNCTION1_FUNCTION_BITS (4) + +#define DWT_COMP2 *((volatile uint32_t *)0xE0001040u) +#define DWT_COMP2_REG *((volatile uint32_t *)0xE0001040u) +#define DWT_COMP2_ADDR (0xE0001040u) +#define DWT_COMP2_RESET (0x00000000u) + /* COMP2 field */ + #define DWT_COMP2_COMP2 (0xFFFFFFFFu) + #define DWT_COMP2_COMP2_MASK (0xFFFFFFFFu) + #define DWT_COMP2_COMP2_BIT (0) + #define DWT_COMP2_COMP2_BITS (32) + +#define DWT_MASK2 *((volatile uint32_t *)0xE0001044u) +#define DWT_MASK2_REG *((volatile uint32_t *)0xE0001044u) +#define DWT_MASK2_ADDR (0xE0001044u) +#define DWT_MASK2_RESET (0x00000000u) + /* MASK2 field */ + #define DWT_MASK2_MASK2 (0x0000001Fu) + #define DWT_MASK2_MASK2_MASK (0x0000001Fu) + #define DWT_MASK2_MASK2_BIT (0) + #define DWT_MASK2_MASK2_BITS (5) + +#define DWT_FUNCTION2 *((volatile uint32_t *)0xE0001048u) +#define DWT_FUNCTION2_REG *((volatile uint32_t *)0xE0001048u) +#define DWT_FUNCTION2_ADDR (0xE0001048u) +#define DWT_FUNCTION2_RESET (0x00000000u) + /* MATCHED field */ + #define DWT_FUNCTION2_MATCHED (0x01000000u) + #define DWT_FUNCTION2_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION2_MATCHED_BIT (24) + #define DWT_FUNCTION2_MATCHED_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION2_EMITRANGE (0x00000020u) + #define DWT_FUNCTION2_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION2_EMITRANGE_BIT (5) + #define DWT_FUNCTION2_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION2_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION2_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION2_FUNCTION_BIT (0) + #define DWT_FUNCTION2_FUNCTION_BITS (4) + +#define DWT_COMP3 *((volatile uint32_t *)0xE0001050u) +#define DWT_COMP3_REG *((volatile uint32_t *)0xE0001050u) +#define DWT_COMP3_ADDR (0xE0001050u) +#define DWT_COMP3_RESET (0x00000000u) + /* COMP3 field */ + #define DWT_COMP3_COMP3 (0xFFFFFFFFu) + #define DWT_COMP3_COMP3_MASK (0xFFFFFFFFu) + #define DWT_COMP3_COMP3_BIT (0) + #define DWT_COMP3_COMP3_BITS (32) + +#define DWT_MASK3 *((volatile uint32_t *)0xE0001054u) +#define DWT_MASK3_REG *((volatile uint32_t *)0xE0001054u) +#define DWT_MASK3_ADDR (0xE0001054u) +#define DWT_MASK3_RESET (0x00000000u) + /* MASK3 field */ + #define DWT_MASK3_MASK3 (0x0000001Fu) + #define DWT_MASK3_MASK3_MASK (0x0000001Fu) + #define DWT_MASK3_MASK3_BIT (0) + #define DWT_MASK3_MASK3_BITS (5) + +#define DWT_FUNCTION3 *((volatile uint32_t *)0xE0001058u) +#define DWT_FUNCTION3_REG *((volatile uint32_t *)0xE0001058u) +#define DWT_FUNCTION3_ADDR (0xE0001058u) +#define DWT_FUNCTION3_RESET (0x00000000u) + /* MATCHED field */ + #define DWT_FUNCTION3_MATCHED (0x01000000u) + #define DWT_FUNCTION3_MATCHED_MASK (0x01000000u) + #define DWT_FUNCTION3_MATCHED_BIT (24) + #define DWT_FUNCTION3_MATCHED_BITS (1) + /* EMITRANGE field */ + #define DWT_FUNCTION3_EMITRANGE (0x00000020u) + #define DWT_FUNCTION3_EMITRANGE_MASK (0x00000020u) + #define DWT_FUNCTION3_EMITRANGE_BIT (5) + #define DWT_FUNCTION3_EMITRANGE_BITS (1) + /* FUNCTION field */ + #define DWT_FUNCTION3_FUNCTION (0x0000000Fu) + #define DWT_FUNCTION3_FUNCTION_MASK (0x0000000Fu) + #define DWT_FUNCTION3_FUNCTION_BIT (0) + #define DWT_FUNCTION3_FUNCTION_BITS (4) + +#define DWT_PERIPHID4 *((volatile uint32_t *)0xE0001FD0u) +#define DWT_PERIPHID4_REG *((volatile uint32_t *)0xE0001FD0u) +#define DWT_PERIPHID4_ADDR (0xE0001FD0u) +#define DWT_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define DWT_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID4_PERIPHID_BIT (0) + #define DWT_PERIPHID4_PERIPHID_BITS (32) + +#define DWT_PERIPHID5 *((volatile uint32_t *)0xE0001FD4u) +#define DWT_PERIPHID5_REG *((volatile uint32_t *)0xE0001FD4u) +#define DWT_PERIPHID5_ADDR (0xE0001FD4u) +#define DWT_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID5_PERIPHID_BIT (0) + #define DWT_PERIPHID5_PERIPHID_BITS (32) + +#define DWT_PERIPHID6 *((volatile uint32_t *)0xE0001FD8u) +#define DWT_PERIPHID6_REG *((volatile uint32_t *)0xE0001FD8u) +#define DWT_PERIPHID6_ADDR (0xE0001FD8u) +#define DWT_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID6_PERIPHID_BIT (0) + #define DWT_PERIPHID6_PERIPHID_BITS (32) + +#define DWT_PERIPHID7 *((volatile uint32_t *)0xE0001FDCu) +#define DWT_PERIPHID7_REG *((volatile uint32_t *)0xE0001FDCu) +#define DWT_PERIPHID7_ADDR (0xE0001FDCu) +#define DWT_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID7_PERIPHID_BIT (0) + #define DWT_PERIPHID7_PERIPHID_BITS (32) + +#define DWT_PERIPHID0 *((volatile uint32_t *)0xE0001FE0u) +#define DWT_PERIPHID0_REG *((volatile uint32_t *)0xE0001FE0u) +#define DWT_PERIPHID0_ADDR (0xE0001FE0u) +#define DWT_PERIPHID0_RESET (0x00000002u) + /* PERIPHID field */ + #define DWT_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID0_PERIPHID_BIT (0) + #define DWT_PERIPHID0_PERIPHID_BITS (32) + +#define DWT_PERIPHID1 *((volatile uint32_t *)0xE0001FE4u) +#define DWT_PERIPHID1_REG *((volatile uint32_t *)0xE0001FE4u) +#define DWT_PERIPHID1_ADDR (0xE0001FE4u) +#define DWT_PERIPHID1_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID1_PERIPHID_BIT (0) + #define DWT_PERIPHID1_PERIPHID_BITS (32) + +#define DWT_PERIPHID2 *((volatile uint32_t *)0xE0001FE8u) +#define DWT_PERIPHID2_REG *((volatile uint32_t *)0xE0001FE8u) +#define DWT_PERIPHID2_ADDR (0xE0001FE8u) +#define DWT_PERIPHID2_RESET (0x0000001Bu) + /* PERIPHID field */ + #define DWT_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID2_PERIPHID_BIT (0) + #define DWT_PERIPHID2_PERIPHID_BITS (32) + +#define DWT_PERIPHID3 *((volatile uint32_t *)0xE0001FECu) +#define DWT_PERIPHID3_REG *((volatile uint32_t *)0xE0001FECu) +#define DWT_PERIPHID3_ADDR (0xE0001FECu) +#define DWT_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define DWT_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define DWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define DWT_PERIPHID3_PERIPHID_BIT (0) + #define DWT_PERIPHID3_PERIPHID_BITS (32) + +#define DWT_CELLID0 *((volatile uint32_t *)0xE0001FF0u) +#define DWT_CELLID0_REG *((volatile uint32_t *)0xE0001FF0u) +#define DWT_CELLID0_ADDR (0xE0001FF0u) +#define DWT_CELLID0_RESET (0x0000000Du) + /* CELLID field */ + #define DWT_CELLID0_CELLID (0xFFFFFFFFu) + #define DWT_CELLID0_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID0_CELLID_BIT (0) + #define DWT_CELLID0_CELLID_BITS (32) + +#define DWT_CELLID1 *((volatile uint32_t *)0xE0001FF4u) +#define DWT_CELLID1_REG *((volatile uint32_t *)0xE0001FF4u) +#define DWT_CELLID1_ADDR (0xE0001FF4u) +#define DWT_CELLID1_RESET (0x000000E0u) + /* CELLID field */ + #define DWT_CELLID1_CELLID (0xFFFFFFFFu) + #define DWT_CELLID1_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID1_CELLID_BIT (0) + #define DWT_CELLID1_CELLID_BITS (32) + +#define DWT_CELLID2 *((volatile uint32_t *)0xE0001FF8u) +#define DWT_CELLID2_REG *((volatile uint32_t *)0xE0001FF8u) +#define DWT_CELLID2_ADDR (0xE0001FF8u) +#define DWT_CELLID2_RESET (0x00000005u) + /* CELLID field */ + #define DWT_CELLID2_CELLID (0xFFFFFFFFu) + #define DWT_CELLID2_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID2_CELLID_BIT (0) + #define DWT_CELLID2_CELLID_BITS (32) + +#define DWT_CELLID3 *((volatile uint32_t *)0xE0001FFCu) +#define DWT_CELLID3_REG *((volatile uint32_t *)0xE0001FFCu) +#define DWT_CELLID3_ADDR (0xE0001FFCu) +#define DWT_CELLID3_RESET (0x000000B1u) + /* CELLID field */ + #define DWT_CELLID3_CELLID (0xFFFFFFFFu) + #define DWT_CELLID3_CELLID_MASK (0xFFFFFFFFu) + #define DWT_CELLID3_CELLID_BIT (0) + #define DWT_CELLID3_CELLID_BITS (32) + +/* FPB block */ +#define DATA_FPB_BASE (0xE0002000u) +#define DATA_FPB_END (0xE0002FFFu) +#define DATA_FPB_SIZE (DATA_FPB_END - DATA_FPB_BASE + 1) + +#define FPB_CTRL *((volatile uint32_t *)0xE0002000u) +#define FPB_CTRL_REG *((volatile uint32_t *)0xE0002000u) +#define FPB_CTRL_ADDR (0xE0002000u) +#define FPB_CTRL_RESET (0x00000000u) + /* NUM_LIT field */ + #define FPB_CTRL_NUM_LIT (0x00000F00u) + #define FPB_CTRL_NUM_LIT_MASK (0x00000F00u) + #define FPB_CTRL_NUM_LIT_BIT (8) + #define FPB_CTRL_NUM_LIT_BITS (4) + /* NUM_CODE field */ + #define FPB_CTRL_NUM_CODE (0x000000F0u) + #define FPB_CTRL_NUM_CODE_MASK (0x000000F0u) + #define FPB_CTRL_NUM_CODE_BIT (4) + #define FPB_CTRL_NUM_CODE_BITS (4) + /* KEY field */ + #define FPB_CTRL_KEY (0x00000002u) + #define FPB_CTRL_KEY_MASK (0x00000002u) + #define FPB_CTRL_KEY_BIT (1) + #define FPB_CTRL_KEY_BITS (1) + /* enable field */ + #define FPB_CTRL_enable (0x00000001u) + #define FPB_CTRL_enable_MASK (0x00000001u) + #define FPB_CTRL_enable_BIT (0) + #define FPB_CTRL_enable_BITS (1) + +#define FPB_REMAP *((volatile uint32_t *)0xE0002004u) +#define FPB_REMAP_REG *((volatile uint32_t *)0xE0002004u) +#define FPB_REMAP_ADDR (0xE0002004u) +#define FPB_REMAP_RESET (0x20000000u) + /* REMAP field */ + #define FPB_REMAP_REMAP (0x1FFFFFE0u) + #define FPB_REMAP_REMAP_MASK (0x1FFFFFE0u) + #define FPB_REMAP_REMAP_BIT (5) + #define FPB_REMAP_REMAP_BITS (24) + +#define FPB_COMP0 *((volatile uint32_t *)0xE0002008u) +#define FPB_COMP0_REG *((volatile uint32_t *)0xE0002008u) +#define FPB_COMP0_ADDR (0xE0002008u) +#define FPB_COMP0_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP0_REPLACE (0xC0000000u) + #define FPB_COMP0_REPLACE_MASK (0xC0000000u) + #define FPB_COMP0_REPLACE_BIT (30) + #define FPB_COMP0_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP0_COMP (0x1FFFFFFCu) + #define FPB_COMP0_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP0_COMP_BIT (2) + #define FPB_COMP0_COMP_BITS (27) + /* enable field */ + #define FPB_COMP0_enable (0x00000001u) + #define FPB_COMP0_enable_MASK (0x00000001u) + #define FPB_COMP0_enable_BIT (0) + #define FPB_COMP0_enable_BITS (1) + +#define FPB_COMP1 *((volatile uint32_t *)0xE000200Cu) +#define FPB_COMP1_REG *((volatile uint32_t *)0xE000200Cu) +#define FPB_COMP1_ADDR (0xE000200Cu) +#define FPB_COMP1_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP1_REPLACE (0xC0000000u) + #define FPB_COMP1_REPLACE_MASK (0xC0000000u) + #define FPB_COMP1_REPLACE_BIT (30) + #define FPB_COMP1_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP1_COMP (0x1FFFFFFCu) + #define FPB_COMP1_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP1_COMP_BIT (2) + #define FPB_COMP1_COMP_BITS (27) + /* enable field */ + #define FPB_COMP1_enable (0x00000001u) + #define FPB_COMP1_enable_MASK (0x00000001u) + #define FPB_COMP1_enable_BIT (0) + #define FPB_COMP1_enable_BITS (1) + +#define FPB_COMP2 *((volatile uint32_t *)0xE0002010u) +#define FPB_COMP2_REG *((volatile uint32_t *)0xE0002010u) +#define FPB_COMP2_ADDR (0xE0002010u) +#define FPB_COMP2_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP2_REPLACE (0xC0000000u) + #define FPB_COMP2_REPLACE_MASK (0xC0000000u) + #define FPB_COMP2_REPLACE_BIT (30) + #define FPB_COMP2_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP2_COMP (0x1FFFFFFCu) + #define FPB_COMP2_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP2_COMP_BIT (2) + #define FPB_COMP2_COMP_BITS (27) + /* enable field */ + #define FPB_COMP2_enable (0x00000001u) + #define FPB_COMP2_enable_MASK (0x00000001u) + #define FPB_COMP2_enable_BIT (0) + #define FPB_COMP2_enable_BITS (1) + +#define FPB_COMP3 *((volatile uint32_t *)0xE0002014u) +#define FPB_COMP3_REG *((volatile uint32_t *)0xE0002014u) +#define FPB_COMP3_ADDR (0xE0002014u) +#define FPB_COMP3_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP3_REPLACE (0xC0000000u) + #define FPB_COMP3_REPLACE_MASK (0xC0000000u) + #define FPB_COMP3_REPLACE_BIT (30) + #define FPB_COMP3_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP3_COMP (0x1FFFFFFCu) + #define FPB_COMP3_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP3_COMP_BIT (2) + #define FPB_COMP3_COMP_BITS (27) + /* enable field */ + #define FPB_COMP3_enable (0x00000001u) + #define FPB_COMP3_enable_MASK (0x00000001u) + #define FPB_COMP3_enable_BIT (0) + #define FPB_COMP3_enable_BITS (1) + +#define FPB_COMP4 *((volatile uint32_t *)0xE0002018u) +#define FPB_COMP4_REG *((volatile uint32_t *)0xE0002018u) +#define FPB_COMP4_ADDR (0xE0002018u) +#define FPB_COMP4_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP4_REPLACE (0xC0000000u) + #define FPB_COMP4_REPLACE_MASK (0xC0000000u) + #define FPB_COMP4_REPLACE_BIT (30) + #define FPB_COMP4_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP4_COMP (0x1FFFFFFCu) + #define FPB_COMP4_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP4_COMP_BIT (2) + #define FPB_COMP4_COMP_BITS (27) + /* enable field */ + #define FPB_COMP4_enable (0x00000001u) + #define FPB_COMP4_enable_MASK (0x00000001u) + #define FPB_COMP4_enable_BIT (0) + #define FPB_COMP4_enable_BITS (1) + +#define FPB_COMP5 *((volatile uint32_t *)0xE000201Cu) +#define FPB_COMP5_REG *((volatile uint32_t *)0xE000201Cu) +#define FPB_COMP5_ADDR (0xE000201Cu) +#define FPB_COMP5_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP5_REPLACE (0xC0000000u) + #define FPB_COMP5_REPLACE_MASK (0xC0000000u) + #define FPB_COMP5_REPLACE_BIT (30) + #define FPB_COMP5_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP5_COMP (0x1FFFFFFCu) + #define FPB_COMP5_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP5_COMP_BIT (2) + #define FPB_COMP5_COMP_BITS (27) + /* enable field */ + #define FPB_COMP5_enable (0x00000001u) + #define FPB_COMP5_enable_MASK (0x00000001u) + #define FPB_COMP5_enable_BIT (0) + #define FPB_COMP5_enable_BITS (1) + +#define FPB_COMP6 *((volatile uint32_t *)0xE0002020u) +#define FPB_COMP6_REG *((volatile uint32_t *)0xE0002020u) +#define FPB_COMP6_ADDR (0xE0002020u) +#define FPB_COMP6_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP6_REPLACE (0xC0000000u) + #define FPB_COMP6_REPLACE_MASK (0xC0000000u) + #define FPB_COMP6_REPLACE_BIT (30) + #define FPB_COMP6_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP6_COMP (0x1FFFFFFCu) + #define FPB_COMP6_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP6_COMP_BIT (2) + #define FPB_COMP6_COMP_BITS (27) + /* enable field */ + #define FPB_COMP6_enable (0x00000001u) + #define FPB_COMP6_enable_MASK (0x00000001u) + #define FPB_COMP6_enable_BIT (0) + #define FPB_COMP6_enable_BITS (1) + +#define FPB_COMP7 *((volatile uint32_t *)0xE0002024u) +#define FPB_COMP7_REG *((volatile uint32_t *)0xE0002024u) +#define FPB_COMP7_ADDR (0xE0002024u) +#define FPB_COMP7_RESET (0x00000000u) + /* REPLACE field */ + #define FPB_COMP7_REPLACE (0xC0000000u) + #define FPB_COMP7_REPLACE_MASK (0xC0000000u) + #define FPB_COMP7_REPLACE_BIT (30) + #define FPB_COMP7_REPLACE_BITS (2) + /* COMP field */ + #define FPB_COMP7_COMP (0x1FFFFFFCu) + #define FPB_COMP7_COMP_MASK (0x1FFFFFFCu) + #define FPB_COMP7_COMP_BIT (2) + #define FPB_COMP7_COMP_BITS (27) + /* enable field */ + #define FPB_COMP7_enable (0x00000001u) + #define FPB_COMP7_enable_MASK (0x00000001u) + #define FPB_COMP7_enable_BIT (0) + #define FPB_COMP7_enable_BITS (1) + +#define FPB_PERIPHID4 *((volatile uint32_t *)0xE0002FD0u) +#define FPB_PERIPHID4_REG *((volatile uint32_t *)0xE0002FD0u) +#define FPB_PERIPHID4_ADDR (0xE0002FD0u) +#define FPB_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define FPB_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID4_PERIPHID_BIT (0) + #define FPB_PERIPHID4_PERIPHID_BITS (32) + +#define FPB_PERIPHID5 *((volatile uint32_t *)0xE0002FD4u) +#define FPB_PERIPHID5_REG *((volatile uint32_t *)0xE0002FD4u) +#define FPB_PERIPHID5_ADDR (0xE0002FD4u) +#define FPB_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID5_PERIPHID_BIT (0) + #define FPB_PERIPHID5_PERIPHID_BITS (32) + +#define FPB_PERIPHID6 *((volatile uint32_t *)0xE0002FD8u) +#define FPB_PERIPHID6_REG *((volatile uint32_t *)0xE0002FD8u) +#define FPB_PERIPHID6_ADDR (0xE0002FD8u) +#define FPB_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID6_PERIPHID_BIT (0) + #define FPB_PERIPHID6_PERIPHID_BITS (32) + +#define FPB_PERIPHID7 *((volatile uint32_t *)0xE0002FDCu) +#define FPB_PERIPHID7_REG *((volatile uint32_t *)0xE0002FDCu) +#define FPB_PERIPHID7_ADDR (0xE0002FDCu) +#define FPB_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID7_PERIPHID_BIT (0) + #define FPB_PERIPHID7_PERIPHID_BITS (32) + +#define FPB_PERIPHID0 *((volatile uint32_t *)0xE0002FE0u) +#define FPB_PERIPHID0_REG *((volatile uint32_t *)0xE0002FE0u) +#define FPB_PERIPHID0_ADDR (0xE0002FE0u) +#define FPB_PERIPHID0_RESET (0x00000003u) + /* PERIPHID field */ + #define FPB_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID0_PERIPHID_BIT (0) + #define FPB_PERIPHID0_PERIPHID_BITS (32) + +#define FPB_PERIPHID1 *((volatile uint32_t *)0xE0002FE4u) +#define FPB_PERIPHID1_REG *((volatile uint32_t *)0xE0002FE4u) +#define FPB_PERIPHID1_ADDR (0xE0002FE4u) +#define FPB_PERIPHID1_RESET (0x000000B0u) + /* PERIPHID field */ + #define FPB_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID1_PERIPHID_BIT (0) + #define FPB_PERIPHID1_PERIPHID_BITS (32) + +#define FPB_PERIPHID2 *((volatile uint32_t *)0xE0002FE8u) +#define FPB_PERIPHID2_REG *((volatile uint32_t *)0xE0002FE8u) +#define FPB_PERIPHID2_ADDR (0xE0002FE8u) +#define FPB_PERIPHID2_RESET (0x0000000Bu) + /* PERIPHID field */ + #define FPB_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID2_PERIPHID_BIT (0) + #define FPB_PERIPHID2_PERIPHID_BITS (32) + +#define FPB_PERIPHID3 *((volatile uint32_t *)0xE0002FECu) +#define FPB_PERIPHID3_REG *((volatile uint32_t *)0xE0002FECu) +#define FPB_PERIPHID3_ADDR (0xE0002FECu) +#define FPB_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define FPB_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define FPB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define FPB_PERIPHID3_PERIPHID_BIT (0) + #define FPB_PERIPHID3_PERIPHID_BITS (32) + +#define FPB_CELLID0 *((volatile uint32_t *)0xE0002FF0u) +#define FPB_CELLID0_REG *((volatile uint32_t *)0xE0002FF0u) +#define FPB_CELLID0_ADDR (0xE0002FF0u) +#define FPB_CELLID0_RESET (0x0000000Du) + /* CELLID field */ + #define FPB_CELLID0_CELLID (0xFFFFFFFFu) + #define FPB_CELLID0_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID0_CELLID_BIT (0) + #define FPB_CELLID0_CELLID_BITS (32) + +#define FPB_CELLID1 *((volatile uint32_t *)0xE0002FF4u) +#define FPB_CELLID1_REG *((volatile uint32_t *)0xE0002FF4u) +#define FPB_CELLID1_ADDR (0xE0002FF4u) +#define FPB_CELLID1_RESET (0x000000E0u) + /* CELLID field */ + #define FPB_CELLID1_CELLID (0xFFFFFFFFu) + #define FPB_CELLID1_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID1_CELLID_BIT (0) + #define FPB_CELLID1_CELLID_BITS (32) + +#define FPB_CELLID2 *((volatile uint32_t *)0xE0002FF8u) +#define FPB_CELLID2_REG *((volatile uint32_t *)0xE0002FF8u) +#define FPB_CELLID2_ADDR (0xE0002FF8u) +#define FPB_CELLID2_RESET (0x00000005u) + /* CELLID field */ + #define FPB_CELLID2_CELLID (0xFFFFFFFFu) + #define FPB_CELLID2_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID2_CELLID_BIT (0) + #define FPB_CELLID2_CELLID_BITS (32) + +#define FPB_CELLID3 *((volatile uint32_t *)0xE0002FFCu) +#define FPB_CELLID3_REG *((volatile uint32_t *)0xE0002FFCu) +#define FPB_CELLID3_ADDR (0xE0002FFCu) +#define FPB_CELLID3_RESET (0x000000B1u) + /* CELLID field */ + #define FPB_CELLID3_CELLID (0xFFFFFFFFu) + #define FPB_CELLID3_CELLID_MASK (0xFFFFFFFFu) + #define FPB_CELLID3_CELLID_BIT (0) + #define FPB_CELLID3_CELLID_BITS (32) + +/* NVIC block */ +#define BLOCK_NVIC_BASE (0xE000E000u) +#define BLOCK_NVIC_END (0xE000EFFFu) +#define BLOCK_NVIC_SIZE (BLOCK_NVIC_END - BLOCK_NVIC_BASE + 1) + +#define NVIC_MCR *((volatile uint32_t *)0xE000E000u) +#define NVIC_MCR_REG *((volatile uint32_t *)0xE000E000u) +#define NVIC_MCR_ADDR (0xE000E000u) +#define NVIC_MCR_RESET (0x00000000u) + +#define NVIC_ICTR *((volatile uint32_t *)0xE000E004u) +#define NVIC_ICTR_REG *((volatile uint32_t *)0xE000E004u) +#define NVIC_ICTR_ADDR (0xE000E004u) +#define NVIC_ICTR_RESET (0x00000000u) + /* INTLINESNUM field */ + #define NVIC_ICTR_INTLINESNUM (0x0000001Fu) + #define NVIC_ICTR_INTLINESNUM_MASK (0x0000001Fu) + #define NVIC_ICTR_INTLINESNUM_BIT (0) + #define NVIC_ICTR_INTLINESNUM_BITS (5) + +#define ST_CSR *((volatile uint32_t *)0xE000E010u) +#define ST_CSR_REG *((volatile uint32_t *)0xE000E010u) +#define ST_CSR_ADDR (0xE000E010u) +#define ST_CSR_RESET (0x00000000u) + /* COUNTFLAG field */ + #define ST_CSR_COUNTFLAG (0x00010000u) + #define ST_CSR_COUNTFLAG_MASK (0x00010000u) + #define ST_CSR_COUNTFLAG_BIT (16) + #define ST_CSR_COUNTFLAG_BITS (1) + /* CLKSOURCE field */ + #define ST_CSR_CLKSOURCE (0x00000004u) + #define ST_CSR_CLKSOURCE_MASK (0x00000004u) + #define ST_CSR_CLKSOURCE_BIT (2) + #define ST_CSR_CLKSOURCE_BITS (1) + /* TICKINT field */ + #define ST_CSR_TICKINT (0x00000002u) + #define ST_CSR_TICKINT_MASK (0x00000002u) + #define ST_CSR_TICKINT_BIT (1) + #define ST_CSR_TICKINT_BITS (1) + /* ENABLE field */ + #define ST_CSR_ENABLE (0x00000001u) + #define ST_CSR_ENABLE_MASK (0x00000001u) + #define ST_CSR_ENABLE_BIT (0) + #define ST_CSR_ENABLE_BITS (1) + +#define ST_RVR *((volatile uint32_t *)0xE000E014u) +#define ST_RVR_REG *((volatile uint32_t *)0xE000E014u) +#define ST_RVR_ADDR (0xE000E014u) +#define ST_RVR_RESET (0x00000000u) + /* RELOAD field */ + #define ST_RVR_RELOAD (0x00FFFFFFu) + #define ST_RVR_RELOAD_MASK (0x00FFFFFFu) + #define ST_RVR_RELOAD_BIT (0) + #define ST_RVR_RELOAD_BITS (24) + +#define ST_CVR *((volatile uint32_t *)0xE000E018u) +#define ST_CVR_REG *((volatile uint32_t *)0xE000E018u) +#define ST_CVR_ADDR (0xE000E018u) +#define ST_CVR_RESET (0x00000000u) + /* CURRENT field */ + #define ST_CVR_CURRENT (0xFFFFFFFFu) + #define ST_CVR_CURRENT_MASK (0xFFFFFFFFu) + #define ST_CVR_CURRENT_BIT (0) + #define ST_CVR_CURRENT_BITS (32) + +#define ST_CALVR *((volatile uint32_t *)0xE000E01Cu) +#define ST_CALVR_REG *((volatile uint32_t *)0xE000E01Cu) +#define ST_CALVR_ADDR (0xE000E01Cu) +#define ST_CALVR_RESET (0x00000000u) + /* NOREF field */ + #define ST_CALVR_NOREF (0x80000000u) + #define ST_CALVR_NOREF_MASK (0x80000000u) + #define ST_CALVR_NOREF_BIT (31) + #define ST_CALVR_NOREF_BITS (1) + /* SKEW field */ + #define ST_CALVR_SKEW (0x40000000u) + #define ST_CALVR_SKEW_MASK (0x40000000u) + #define ST_CALVR_SKEW_BIT (30) + #define ST_CALVR_SKEW_BITS (1) + /* TENMS field */ + #define ST_CALVR_TENMS (0x00FFFFFFu) + #define ST_CALVR_TENMS_MASK (0x00FFFFFFu) + #define ST_CALVR_TENMS_BIT (0) + #define ST_CALVR_TENMS_BITS (24) + +#define INT_CFGSET *((volatile uint32_t *)0xE000E100u) +#define INT_CFGSET_REG *((volatile uint32_t *)0xE000E100u) +#define INT_CFGSET_ADDR (0xE000E100u) +#define INT_CFGSET_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_CFGCLR *((volatile uint32_t *)0xE000E180u) +#define INT_CFGCLR_REG *((volatile uint32_t *)0xE000E180u) +#define INT_CFGCLR_ADDR (0xE000E180u) +#define INT_CFGCLR_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_PENDSET *((volatile uint32_t *)0xE000E200u) +#define INT_PENDSET_REG *((volatile uint32_t *)0xE000E200u) +#define INT_PENDSET_ADDR (0xE000E200u) +#define INT_PENDSET_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_PENDCLR *((volatile uint32_t *)0xE000E280u) +#define INT_PENDCLR_REG *((volatile uint32_t *)0xE000E280u) +#define INT_PENDCLR_ADDR (0xE000E280u) +#define INT_PENDCLR_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define INT_ACTIVE *((volatile uint32_t *)0xE000E300u) +#define INT_ACTIVE_REG *((volatile uint32_t *)0xE000E300u) +#define INT_ACTIVE_ADDR (0xE000E300u) +#define INT_ACTIVE_RESET (0x00000000u) + /* INT_DEBUG field */ + #define INT_DEBUG (0x00010000u) + #define INT_DEBUG_MASK (0x00010000u) + #define INT_DEBUG_BIT (16) + #define INT_DEBUG_BITS (1) + /* INT_IRQD field */ + #define INT_IRQD (0x00008000u) + #define INT_IRQD_MASK (0x00008000u) + #define INT_IRQD_BIT (15) + #define INT_IRQD_BITS (1) + /* INT_IRQC field */ + #define INT_IRQC (0x00004000u) + #define INT_IRQC_MASK (0x00004000u) + #define INT_IRQC_BIT (14) + #define INT_IRQC_BITS (1) + /* INT_IRQB field */ + #define INT_IRQB (0x00002000u) + #define INT_IRQB_MASK (0x00002000u) + #define INT_IRQB_BIT (13) + #define INT_IRQB_BITS (1) + /* INT_IRQA field */ + #define INT_IRQA (0x00001000u) + #define INT_IRQA_MASK (0x00001000u) + #define INT_IRQA_BIT (12) + #define INT_IRQA_BITS (1) + /* INT_ADC field */ + #define INT_ADC (0x00000800u) + #define INT_ADC_MASK (0x00000800u) + #define INT_ADC_BIT (11) + #define INT_ADC_BITS (1) + /* INT_MACRX field */ + #define INT_MACRX (0x00000400u) + #define INT_MACRX_MASK (0x00000400u) + #define INT_MACRX_BIT (10) + #define INT_MACRX_BITS (1) + /* INT_MACTX field */ + #define INT_MACTX (0x00000200u) + #define INT_MACTX_MASK (0x00000200u) + #define INT_MACTX_BIT (9) + #define INT_MACTX_BITS (1) + /* INT_MACTMR field */ + #define INT_MACTMR (0x00000100u) + #define INT_MACTMR_MASK (0x00000100u) + #define INT_MACTMR_BIT (8) + #define INT_MACTMR_BITS (1) + /* INT_SEC field */ + #define INT_SEC (0x00000080u) + #define INT_SEC_MASK (0x00000080u) + #define INT_SEC_BIT (7) + #define INT_SEC_BITS (1) + /* INT_SC2 field */ + #define INT_SC2 (0x00000040u) + #define INT_SC2_MASK (0x00000040u) + #define INT_SC2_BIT (6) + #define INT_SC2_BITS (1) + /* INT_SC1 field */ + #define INT_SC1 (0x00000020u) + #define INT_SC1_MASK (0x00000020u) + #define INT_SC1_BIT (5) + #define INT_SC1_BITS (1) + /* INT_SLEEPTMR field */ + #define INT_SLEEPTMR (0x00000010u) + #define INT_SLEEPTMR_MASK (0x00000010u) + #define INT_SLEEPTMR_BIT (4) + #define INT_SLEEPTMR_BITS (1) + /* INT_BB field */ + #define INT_BB (0x00000008u) + #define INT_BB_MASK (0x00000008u) + #define INT_BB_BIT (3) + #define INT_BB_BITS (1) + /* INT_MGMT field */ + #define INT_MGMT (0x00000004u) + #define INT_MGMT_MASK (0x00000004u) + #define INT_MGMT_BIT (2) + #define INT_MGMT_BITS (1) + /* INT_TIM2 field */ + #define INT_TIM2 (0x00000002u) + #define INT_TIM2_MASK (0x00000002u) + #define INT_TIM2_BIT (1) + #define INT_TIM2_BITS (1) + /* INT_TIM1 field */ + #define INT_TIM1 (0x00000001u) + #define INT_TIM1_MASK (0x00000001u) + #define INT_TIM1_BIT (0) + #define INT_TIM1_BITS (1) + +#define NVIC_IPR_3to0 *((volatile uint32_t *)0xE000E400u) +#define NVIC_IPR_3to0_REG *((volatile uint32_t *)0xE000E400u) +#define NVIC_IPR_3to0_ADDR (0xE000E400u) +#define NVIC_IPR_3to0_RESET (0x00000000u) + /* PRI_3 field */ + #define NVIC_IPR_3to0_PRI_3 (0xFF000000u) + #define NVIC_IPR_3to0_PRI_3_MASK (0xFF000000u) + #define NVIC_IPR_3to0_PRI_3_BIT (24) + #define NVIC_IPR_3to0_PRI_3_BITS (8) + /* PRI_2 field */ + #define NVIC_IPR_3to0_PRI_2 (0x00FF0000u) + #define NVIC_IPR_3to0_PRI_2_MASK (0x00FF0000u) + #define NVIC_IPR_3to0_PRI_2_BIT (16) + #define NVIC_IPR_3to0_PRI_2_BITS (8) + /* PRI_1 field */ + #define NVIC_IPR_3to0_PRI_1 (0x0000FF00u) + #define NVIC_IPR_3to0_PRI_1_MASK (0x0000FF00u) + #define NVIC_IPR_3to0_PRI_1_BIT (8) + #define NVIC_IPR_3to0_PRI_1_BITS (8) + /* PRI_0 field */ + #define NVIC_IPR_3to0_PRI_0 (0x000000FFu) + #define NVIC_IPR_3to0_PRI_0_MASK (0x000000FFu) + #define NVIC_IPR_3to0_PRI_0_BIT (0) + #define NVIC_IPR_3to0_PRI_0_BITS (8) + +#define NVIC_IPR_7to4 *((volatile uint32_t *)0xE000E404u) +#define NVIC_IPR_7to4_REG *((volatile uint32_t *)0xE000E404u) +#define NVIC_IPR_7to4_ADDR (0xE000E404u) +#define NVIC_IPR_7to4_RESET (0x00000000u) + /* PRI_7 field */ + #define NVIC_IPR_7to4_PRI_7 (0xFF000000u) + #define NVIC_IPR_7to4_PRI_7_MASK (0xFF000000u) + #define NVIC_IPR_7to4_PRI_7_BIT (24) + #define NVIC_IPR_7to4_PRI_7_BITS (8) + /* PRI_6 field */ + #define NVIC_IPR_7to4_PRI_6 (0x00FF0000u) + #define NVIC_IPR_7to4_PRI_6_MASK (0x00FF0000u) + #define NVIC_IPR_7to4_PRI_6_BIT (16) + #define NVIC_IPR_7to4_PRI_6_BITS (8) + /* PRI_5 field */ + #define NVIC_IPR_7to4_PRI_5 (0x0000FF00u) + #define NVIC_IPR_7to4_PRI_5_MASK (0x0000FF00u) + #define NVIC_IPR_7to4_PRI_5_BIT (8) + #define NVIC_IPR_7to4_PRI_5_BITS (8) + /* PRI_4 field */ + #define NVIC_IPR_7to4_PRI_4 (0x000000FFu) + #define NVIC_IPR_7to4_PRI_4_MASK (0x000000FFu) + #define NVIC_IPR_7to4_PRI_4_BIT (0) + #define NVIC_IPR_7to4_PRI_4_BITS (8) + +#define NVIC_IPR_11to8 *((volatile uint32_t *)0xE000E408u) +#define NVIC_IPR_11to8_REG *((volatile uint32_t *)0xE000E408u) +#define NVIC_IPR_11to8_ADDR (0xE000E408u) +#define NVIC_IPR_11to8_RESET (0x00000000u) + /* PRI_11 field */ + #define NVIC_IPR_11to8_PRI_11 (0xFF000000u) + #define NVIC_IPR_11to8_PRI_11_MASK (0xFF000000u) + #define NVIC_IPR_11to8_PRI_11_BIT (24) + #define NVIC_IPR_11to8_PRI_11_BITS (8) + /* PRI_10 field */ + #define NVIC_IPR_11to8_PRI_10 (0x00FF0000u) + #define NVIC_IPR_11to8_PRI_10_MASK (0x00FF0000u) + #define NVIC_IPR_11to8_PRI_10_BIT (16) + #define NVIC_IPR_11to8_PRI_10_BITS (8) + /* PRI_9 field */ + #define NVIC_IPR_11to8_PRI_9 (0x0000FF00u) + #define NVIC_IPR_11to8_PRI_9_MASK (0x0000FF00u) + #define NVIC_IPR_11to8_PRI_9_BIT (8) + #define NVIC_IPR_11to8_PRI_9_BITS (8) + /* PRI_8 field */ + #define NVIC_IPR_11to8_PRI_8 (0x000000FFu) + #define NVIC_IPR_11to8_PRI_8_MASK (0x000000FFu) + #define NVIC_IPR_11to8_PRI_8_BIT (0) + #define NVIC_IPR_11to8_PRI_8_BITS (8) + +#define NVIC_IPR_15to12 *((volatile uint32_t *)0xE000E40Cu) +#define NVIC_IPR_15to12_REG *((volatile uint32_t *)0xE000E40Cu) +#define NVIC_IPR_15to12_ADDR (0xE000E40Cu) +#define NVIC_IPR_15to12_RESET (0x00000000u) + /* PRI_15 field */ + #define NVIC_IPR_15to12_PRI_15 (0xFF000000u) + #define NVIC_IPR_15to12_PRI_15_MASK (0xFF000000u) + #define NVIC_IPR_15to12_PRI_15_BIT (24) + #define NVIC_IPR_15to12_PRI_15_BITS (8) + /* PRI_14 field */ + #define NVIC_IPR_15to12_PRI_14 (0x00FF0000u) + #define NVIC_IPR_15to12_PRI_14_MASK (0x00FF0000u) + #define NVIC_IPR_15to12_PRI_14_BIT (16) + #define NVIC_IPR_15to12_PRI_14_BITS (8) + /* PRI_13 field */ + #define NVIC_IPR_15to12_PRI_13 (0x0000FF00u) + #define NVIC_IPR_15to12_PRI_13_MASK (0x0000FF00u) + #define NVIC_IPR_15to12_PRI_13_BIT (8) + #define NVIC_IPR_15to12_PRI_13_BITS (8) + /* PRI_12 field */ + #define NVIC_IPR_15to12_PRI_12 (0x000000FFu) + #define NVIC_IPR_15to12_PRI_12_MASK (0x000000FFu) + #define NVIC_IPR_15to12_PRI_12_BIT (0) + #define NVIC_IPR_15to12_PRI_12_BITS (8) + +#define NVIC_IPR_19to16 *((volatile uint32_t *)0xE000E410u) +#define NVIC_IPR_19to16_REG *((volatile uint32_t *)0xE000E410u) +#define NVIC_IPR_19to16_ADDR (0xE000E410u) +#define NVIC_IPR_19to16_RESET (0x00000000u) + /* PRI_19 field */ + #define NVIC_IPR_19to16_PRI_19 (0xFF000000u) + #define NVIC_IPR_19to16_PRI_19_MASK (0xFF000000u) + #define NVIC_IPR_19to16_PRI_19_BIT (24) + #define NVIC_IPR_19to16_PRI_19_BITS (8) + /* PRI_18 field */ + #define NVIC_IPR_19to16_PRI_18 (0x00FF0000u) + #define NVIC_IPR_19to16_PRI_18_MASK (0x00FF0000u) + #define NVIC_IPR_19to16_PRI_18_BIT (16) + #define NVIC_IPR_19to16_PRI_18_BITS (8) + /* PRI_17 field */ + #define NVIC_IPR_19to16_PRI_17 (0x0000FF00u) + #define NVIC_IPR_19to16_PRI_17_MASK (0x0000FF00u) + #define NVIC_IPR_19to16_PRI_17_BIT (8) + #define NVIC_IPR_19to16_PRI_17_BITS (8) + /* PRI_16 field */ + #define NVIC_IPR_19to16_PRI_16 (0x000000FFu) + #define NVIC_IPR_19to16_PRI_16_MASK (0x000000FFu) + #define NVIC_IPR_19to16_PRI_16_BIT (0) + #define NVIC_IPR_19to16_PRI_16_BITS (8) + +#define SCS_CPUID *((volatile uint32_t *)0xE000ED00u) +#define SCS_CPUID_REG *((volatile uint32_t *)0xE000ED00u) +#define SCS_CPUID_ADDR (0xE000ED00u) +#define SCS_CPUID_RESET (0x411FC231u) + /* IMPLEMENTER field */ + #define SCS_CPUID_IMPLEMENTER (0xFF000000u) + #define SCS_CPUID_IMPLEMENTER_MASK (0xFF000000u) + #define SCS_CPUID_IMPLEMENTER_BIT (24) + #define SCS_CPUID_IMPLEMENTER_BITS (8) + /* VARIANT field */ + #define SCS_CPUID_VARIANT (0x00F00000u) + #define SCS_CPUID_VARIANT_MASK (0x00F00000u) + #define SCS_CPUID_VARIANT_BIT (20) + #define SCS_CPUID_VARIANT_BITS (4) + /* CONSTANT field */ + #define SCS_CPUID_CONSTANT (0x000F0000u) + #define SCS_CPUID_CONSTANT_MASK (0x000F0000u) + #define SCS_CPUID_CONSTANT_BIT (16) + #define SCS_CPUID_CONSTANT_BITS (4) + /* PARTNO field */ + #define SCS_CPUID_PARTNO (0x0000FFF0u) + #define SCS_CPUID_PARTNO_MASK (0x0000FFF0u) + #define SCS_CPUID_PARTNO_BIT (4) + #define SCS_CPUID_PARTNO_BITS (12) + /* REVISION field */ + #define SCS_CPUID_REVISION (0x0000000Fu) + #define SCS_CPUID_REVISION_MASK (0x0000000Fu) + #define SCS_CPUID_REVISION_BIT (0) + #define SCS_CPUID_REVISION_BITS (4) + +#define SCS_ICSR *((volatile uint32_t *)0xE000ED04u) +#define SCS_ICSR_REG *((volatile uint32_t *)0xE000ED04u) +#define SCS_ICSR_ADDR (0xE000ED04u) +#define SCS_ICSR_RESET (0x00000000u) + /* NMIPENDSET field */ + #define SCS_ICSR_NMIPENDSET (0x80000000u) + #define SCS_ICSR_NMIPENDSET_MASK (0x80000000u) + #define SCS_ICSR_NMIPENDSET_BIT (31) + #define SCS_ICSR_NMIPENDSET_BITS (1) + /* PENDSVSET field */ + #define SCS_ICSR_PENDSVSET (0x10000000u) + #define SCS_ICSR_PENDSVSET_MASK (0x10000000u) + #define SCS_ICSR_PENDSVSET_BIT (28) + #define SCS_ICSR_PENDSVSET_BITS (1) + /* PENDSVCLR field */ + #define SCS_ICSR_PENDSVCLR (0x08000000u) + #define SCS_ICSR_PENDSVCLR_MASK (0x08000000u) + #define SCS_ICSR_PENDSVCLR_BIT (27) + #define SCS_ICSR_PENDSVCLR_BITS (1) + /* PENDSTSET field */ + #define SCS_ICSR_PENDSTSET (0x04000000u) + #define SCS_ICSR_PENDSTSET_MASK (0x04000000u) + #define SCS_ICSR_PENDSTSET_BIT (26) + #define SCS_ICSR_PENDSTSET_BITS (1) + /* PENDSTCLR field */ + #define SCS_ICSR_PENDSTCLR (0x02000000u) + #define SCS_ICSR_PENDSTCLR_MASK (0x02000000u) + #define SCS_ICSR_PENDSTCLR_BIT (25) + #define SCS_ICSR_PENDSTCLR_BITS (1) + /* ISRPREEMPT field */ + #define SCS_ICSR_ISRPREEMPT (0x00800000u) + #define SCS_ICSR_ISRPREEMPT_MASK (0x00800000u) + #define SCS_ICSR_ISRPREEMPT_BIT (23) + #define SCS_ICSR_ISRPREEMPT_BITS (1) + /* ISRPENDING field */ + #define SCS_ICSR_ISRPENDING (0x00400000u) + #define SCS_ICSR_ISRPENDING_MASK (0x00400000u) + #define SCS_ICSR_ISRPENDING_BIT (22) + #define SCS_ICSR_ISRPENDING_BITS (1) + /* VECTPENDING field */ + #define SCS_ICSR_VECTPENDING (0x001FF000u) + #define SCS_ICSR_VECTPENDING_MASK (0x001FF000u) + #define SCS_ICSR_VECTPENDING_BIT (12) + #define SCS_ICSR_VECTPENDING_BITS (9) + /* RETTOBASE field */ + #define SCS_ICSR_RETTOBASE (0x00000800u) + #define SCS_ICSR_RETTOBASE_MASK (0x00000800u) + #define SCS_ICSR_RETTOBASE_BIT (11) + #define SCS_ICSR_RETTOBASE_BITS (1) + /* VECACTIVE field */ + #define SCS_ICSR_VECACTIVE (0x000001FFu) + #define SCS_ICSR_VECACTIVE_MASK (0x000001FFu) + #define SCS_ICSR_VECACTIVE_BIT (0) + #define SCS_ICSR_VECACTIVE_BITS (9) + +#define SCS_VTOR *((volatile uint32_t *)0xE000ED08u) +#define SCS_VTOR_REG *((volatile uint32_t *)0xE000ED08u) +#define SCS_VTOR_ADDR (0xE000ED08u) +#define SCS_VTOR_RESET (0x00000000u) + /* TBLBASE field */ + #define SCS_VTOR_TBLBASE (0x20000000u) + #define SCS_VTOR_TBLBASE_MASK (0x20000000u) + #define SCS_VTOR_TBLBASE_BIT (29) + #define SCS_VTOR_TBLBASE_BITS (1) + /* TBLOFF field */ + #define SCS_VTOR_TBLOFF (0x1FFFFF00u) + #define SCS_VTOR_TBLOFF_MASK (0x1FFFFF00u) + #define SCS_VTOR_TBLOFF_BIT (8) + #define SCS_VTOR_TBLOFF_BITS (21) + +#define SCS_AIRCR *((volatile uint32_t *)0xE000ED0Cu) +#define SCS_AIRCR_REG *((volatile uint32_t *)0xE000ED0Cu) +#define SCS_AIRCR_ADDR (0xE000ED0Cu) +#define SCS_AIRCR_RESET (0x00000000u) + /* VECTKEYSTAT field */ + #define SCS_AIRCR_VECTKEYSTAT (0xFFFF0000u) + #define SCS_AIRCR_VECTKEYSTAT_MASK (0xFFFF0000u) + #define SCS_AIRCR_VECTKEYSTAT_BIT (16) + #define SCS_AIRCR_VECTKEYSTAT_BITS (16) + /* VECTKEY field */ + #define SCS_AIRCR_VECTKEY (0xFFFF0000u) + #define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u) + #define SCS_AIRCR_VECTKEY_BIT (16) + #define SCS_AIRCR_VECTKEY_BITS (16) + /* ENDIANESS field */ + #define SCS_AIRCR_ENDIANESS (0x00008000u) + #define SCS_AIRCR_ENDIANESS_MASK (0x00008000u) + #define SCS_AIRCR_ENDIANESS_BIT (15) + #define SCS_AIRCR_ENDIANESS_BITS (1) + /* PRIGROUP field */ + #define SCS_AIRCR_PRIGROUP (0x00000700u) + #define SCS_AIRCR_PRIGROUP_MASK (0x00000700u) + #define SCS_AIRCR_PRIGROUP_BIT (8) + #define SCS_AIRCR_PRIGROUP_BITS (3) + /* SYSRESETREQ field */ + #define SCS_AIRCR_SYSRESETREQ (0x00000004u) + #define SCS_AIRCR_SYSRESETREQ_MASK (0x00000004u) + #define SCS_AIRCR_SYSRESETREQ_BIT (2) + #define SCS_AIRCR_SYSRESETREQ_BITS (1) + /* VECTCLRACTIVE field */ + #define SCS_AIRCR_VECTCLRACTIVE (0x00000002u) + #define SCS_AIRCR_VECTCLRACTIVE_MASK (0x00000002u) + #define SCS_AIRCR_VECTCLRACTIVE_BIT (1) + #define SCS_AIRCR_VECTCLRACTIVE_BITS (1) + /* VECTRESET field */ + #define SCS_AIRCR_VECTRESET (0x00000001u) + #define SCS_AIRCR_VECTRESET_MASK (0x00000001u) + #define SCS_AIRCR_VECTRESET_BIT (0) + #define SCS_AIRCR_VECTRESET_BITS (1) + +#define SCS_SCR *((volatile uint32_t *)0xE000ED10u) +#define SCS_SCR_REG *((volatile uint32_t *)0xE000ED10u) +#define SCS_SCR_ADDR (0xE000ED10u) +#define SCS_SCR_RESET (0x00000000u) + /* SEVONPEND field */ + #define SCS_SCR_SEVONPEND (0x00000010u) + #define SCS_SCR_SEVONPEND_MASK (0x00000010u) + #define SCS_SCR_SEVONPEND_BIT (4) + #define SCS_SCR_SEVONPEND_BITS (1) + /* SLEEPDEEP field */ + #define SCS_SCR_SLEEPDEEP (0x00000004u) + #define SCS_SCR_SLEEPDEEP_MASK (0x00000004u) + #define SCS_SCR_SLEEPDEEP_BIT (2) + #define SCS_SCR_SLEEPDEEP_BITS (1) + /* SLEEPONEXIT field */ + #define SCS_SCR_SLEEPONEXIT (0x00000002u) + #define SCS_SCR_SLEEPONEXIT_MASK (0x00000002u) + #define SCS_SCR_SLEEPONEXIT_BIT (1) + #define SCS_SCR_SLEEPONEXIT_BITS (1) + +#define SCS_CCR *((volatile uint32_t *)0xE000ED14u) +#define SCS_CCR_REG *((volatile uint32_t *)0xE000ED14u) +#define SCS_CCR_ADDR (0xE000ED14u) +#define SCS_CCR_RESET (0x00000000u) + /* STKALIGN field */ + #define SCS_CCR_STKALIGN (0x00000200u) + #define SCS_CCR_STKALIGN_MASK (0x00000200u) + #define SCS_CCR_STKALIGN_BIT (9) + #define SCS_CCR_STKALIGN_BITS (1) + /* BFHFNMIGN field */ + #define SCS_CCR_BFHFNMIGN (0x00000100u) + #define SCS_CCR_BFHFNMIGN_MASK (0x00000100u) + #define SCS_CCR_BFHFNMIGN_BIT (8) + #define SCS_CCR_BFHFNMIGN_BITS (1) + /* DIV_0_TRP field */ + #define SCS_CCR_DIV_0_TRP (0x00000010u) + #define SCS_CCR_DIV_0_TRP_MASK (0x00000010u) + #define SCS_CCR_DIV_0_TRP_BIT (4) + #define SCS_CCR_DIV_0_TRP_BITS (1) + /* UNALIGN_TRP field */ + #define SCS_CCR_UNALIGN_TRP (0x00000008u) + #define SCS_CCR_UNALIGN_TRP_MASK (0x00000008u) + #define SCS_CCR_UNALIGN_TRP_BIT (3) + #define SCS_CCR_UNALIGN_TRP_BITS (1) + /* USERSETMPEND field */ + #define SCS_CCR_USERSETMPEND (0x00000002u) + #define SCS_CCR_USERSETMPEND_MASK (0x00000002u) + #define SCS_CCR_USERSETMPEND_BIT (1) + #define SCS_CCR_USERSETMPEND_BITS (1) + /* NONBASETHRDENA field */ + #define SCS_CCR_NONBASETHRDENA (0x00000001u) + #define SCS_CCR_NONBASETHRDENA_MASK (0x00000001u) + #define SCS_CCR_NONBASETHRDENA_BIT (0) + #define SCS_CCR_NONBASETHRDENA_BITS (1) + +#define SCS_SHPR_7to4 *((volatile uint32_t *)0xE000ED18u) +#define SCS_SHPR_7to4_REG *((volatile uint32_t *)0xE000ED18u) +#define SCS_SHPR_7to4_ADDR (0xE000ED18u) +#define SCS_SHPR_7to4_RESET (0x00000000u) + /* PRI_7 field */ + #define SCS_SHPR_7to4_PRI_7 (0xFF000000u) + #define SCS_SHPR_7to4_PRI_7_MASK (0xFF000000u) + #define SCS_SHPR_7to4_PRI_7_BIT (24) + #define SCS_SHPR_7to4_PRI_7_BITS (8) + /* PRI_6 field */ + #define SCS_SHPR_7to4_PRI_6 (0x00FF0000u) + #define SCS_SHPR_7to4_PRI_6_MASK (0x00FF0000u) + #define SCS_SHPR_7to4_PRI_6_BIT (16) + #define SCS_SHPR_7to4_PRI_6_BITS (8) + /* PRI_5 field */ + #define SCS_SHPR_7to4_PRI_5 (0x0000FF00u) + #define SCS_SHPR_7to4_PRI_5_MASK (0x0000FF00u) + #define SCS_SHPR_7to4_PRI_5_BIT (8) + #define SCS_SHPR_7to4_PRI_5_BITS (8) + /* PRI_4 field */ + #define SCS_SHPR_7to4_PRI_4 (0x000000FFu) + #define SCS_SHPR_7to4_PRI_4_MASK (0x000000FFu) + #define SCS_SHPR_7to4_PRI_4_BIT (0) + #define SCS_SHPR_7to4_PRI_4_BITS (8) + +#define SCS_SHPR_11to8 *((volatile uint32_t *)0xE000ED1Cu) +#define SCS_SHPR_11to8_REG *((volatile uint32_t *)0xE000ED1Cu) +#define SCS_SHPR_11to8_ADDR (0xE000ED1Cu) +#define SCS_SHPR_11to8_RESET (0x00000000u) + /* PRI_11 field */ + #define SCS_SHPR_11to8_PRI_11 (0xFF000000u) + #define SCS_SHPR_11to8_PRI_11_MASK (0xFF000000u) + #define SCS_SHPR_11to8_PRI_11_BIT (24) + #define SCS_SHPR_11to8_PRI_11_BITS (8) + /* PRI_10 field */ + #define SCS_SHPR_11to8_PRI_10 (0x00FF0000u) + #define SCS_SHPR_11to8_PRI_10_MASK (0x00FF0000u) + #define SCS_SHPR_11to8_PRI_10_BIT (16) + #define SCS_SHPR_11to8_PRI_10_BITS (8) + /* PRI_9 field */ + #define SCS_SHPR_11to8_PRI_9 (0x0000FF00u) + #define SCS_SHPR_11to8_PRI_9_MASK (0x0000FF00u) + #define SCS_SHPR_11to8_PRI_9_BIT (8) + #define SCS_SHPR_11to8_PRI_9_BITS (8) + /* PRI_8 field */ + #define SCS_SHPR_11to8_PRI_8 (0x000000FFu) + #define SCS_SHPR_11to8_PRI_8_MASK (0x000000FFu) + #define SCS_SHPR_11to8_PRI_8_BIT (0) + #define SCS_SHPR_11to8_PRI_8_BITS (8) + +#define SCS_SHPR_15to12 *((volatile uint32_t *)0xE000ED20u) +#define SCS_SHPR_15to12_REG *((volatile uint32_t *)0xE000ED20u) +#define SCS_SHPR_15to12_ADDR (0xE000ED20u) +#define SCS_SHPR_15to12_RESET (0x00000000u) + /* PRI_15 field */ + #define SCS_SHPR_15to12_PRI_15 (0xFF000000u) + #define SCS_SHPR_15to12_PRI_15_MASK (0xFF000000u) + #define SCS_SHPR_15to12_PRI_15_BIT (24) + #define SCS_SHPR_15to12_PRI_15_BITS (8) + /* PRI_14 field */ + #define SCS_SHPR_15to12_PRI_14 (0x00FF0000u) + #define SCS_SHPR_15to12_PRI_14_MASK (0x00FF0000u) + #define SCS_SHPR_15to12_PRI_14_BIT (16) + #define SCS_SHPR_15to12_PRI_14_BITS (8) + /* PRI_13 field */ + #define SCS_SHPR_15to12_PRI_13 (0x0000FF00u) + #define SCS_SHPR_15to12_PRI_13_MASK (0x0000FF00u) + #define SCS_SHPR_15to12_PRI_13_BIT (8) + #define SCS_SHPR_15to12_PRI_13_BITS (8) + /* PRI_12 field */ + #define SCS_SHPR_15to12_PRI_12 (0x000000FFu) + #define SCS_SHPR_15to12_PRI_12_MASK (0x000000FFu) + #define SCS_SHPR_15to12_PRI_12_BIT (0) + #define SCS_SHPR_15to12_PRI_12_BITS (8) + +#define SCS_SHCSR *((volatile uint32_t *)0xE000ED24u) +#define SCS_SHCSR_REG *((volatile uint32_t *)0xE000ED24u) +#define SCS_SHCSR_ADDR (0xE000ED24u) +#define SCS_SHCSR_RESET (0x00000000u) + /* USGFAULTENA field */ + #define SCS_SHCSR_USGFAULTENA (0x00040000u) + #define SCS_SHCSR_USGFAULTENA_MASK (0x00040000u) + #define SCS_SHCSR_USGFAULTENA_BIT (18) + #define SCS_SHCSR_USGFAULTENA_BITS (1) + /* BUSFAULTENA field */ + #define SCS_SHCSR_BUSFAULTENA (0x00020000u) + #define SCS_SHCSR_BUSFAULTENA_MASK (0x00020000u) + #define SCS_SHCSR_BUSFAULTENA_BIT (17) + #define SCS_SHCSR_BUSFAULTENA_BITS (1) + /* MEMFAULTENA field */ + #define SCS_SHCSR_MEMFAULTENA (0x00010000u) + #define SCS_SHCSR_MEMFAULTENA_MASK (0x00010000u) + #define SCS_SHCSR_MEMFAULTENA_BIT (16) + #define SCS_SHCSR_MEMFAULTENA_BITS (1) + /* SVCALLPENDED field */ + #define SCS_SHCSR_SVCALLPENDED (0x00008000u) + #define SCS_SHCSR_SVCALLPENDED_MASK (0x00008000u) + #define SCS_SHCSR_SVCALLPENDED_BIT (15) + #define SCS_SHCSR_SVCALLPENDED_BITS (1) + /* BUSFAULTPENDED field */ + #define SCS_SHCSR_BUSFAULTPENDED (0x00004000u) + #define SCS_SHCSR_BUSFAULTPENDED_MASK (0x00004000u) + #define SCS_SHCSR_BUSFAULTPENDED_BIT (14) + #define SCS_SHCSR_BUSFAULTPENDED_BITS (1) + /* MEMFAULTPENDED field */ + #define SCS_SHCSR_MEMFAULTPENDED (0x00002000u) + #define SCS_SHCSR_MEMFAULTPENDED_MASK (0x00002000u) + #define SCS_SHCSR_MEMFAULTPENDED_BIT (13) + #define SCS_SHCSR_MEMFAULTPENDED_BITS (1) + /* USGFAULTPENDED field */ + #define SCS_SHCSR_USGFAULTPENDED (0x00001000u) + #define SCS_SHCSR_USGFAULTPENDED_MASK (0x00001000u) + #define SCS_SHCSR_USGFAULTPENDED_BIT (12) + #define SCS_SHCSR_USGFAULTPENDED_BITS (1) + /* SYSTICKACT field */ + #define SCS_SHCSR_SYSTICKACT (0x00000800u) + #define SCS_SHCSR_SYSTICKACT_MASK (0x00000800u) + #define SCS_SHCSR_SYSTICKACT_BIT (11) + #define SCS_SHCSR_SYSTICKACT_BITS (1) + /* PENDSVACT field */ + #define SCS_SHCSR_PENDSVACT (0x00000400u) + #define SCS_SHCSR_PENDSVACT_MASK (0x00000400u) + #define SCS_SHCSR_PENDSVACT_BIT (10) + #define SCS_SHCSR_PENDSVACT_BITS (1) + /* MONITORACT field */ + #define SCS_SHCSR_MONITORACT (0x00000100u) + #define SCS_SHCSR_MONITORACT_MASK (0x00000100u) + #define SCS_SHCSR_MONITORACT_BIT (8) + #define SCS_SHCSR_MONITORACT_BITS (1) + /* SVCALLACT field */ + #define SCS_SHCSR_SVCALLACT (0x00000080u) + #define SCS_SHCSR_SVCALLACT_MASK (0x00000080u) + #define SCS_SHCSR_SVCALLACT_BIT (7) + #define SCS_SHCSR_SVCALLACT_BITS (1) + /* USGFAULTACT field */ + #define SCS_SHCSR_USGFAULTACT (0x00000008u) + #define SCS_SHCSR_USGFAULTACT_MASK (0x00000008u) + #define SCS_SHCSR_USGFAULTACT_BIT (3) + #define SCS_SHCSR_USGFAULTACT_BITS (1) + /* BUSFAULTACT field */ + #define SCS_SHCSR_BUSFAULTACT (0x00000002u) + #define SCS_SHCSR_BUSFAULTACT_MASK (0x00000002u) + #define SCS_SHCSR_BUSFAULTACT_BIT (1) + #define SCS_SHCSR_BUSFAULTACT_BITS (1) + /* MEMFAULTACT field */ + #define SCS_SHCSR_MEMFAULTACT (0x00000001u) + #define SCS_SHCSR_MEMFAULTACT_MASK (0x00000001u) + #define SCS_SHCSR_MEMFAULTACT_BIT (0) + #define SCS_SHCSR_MEMFAULTACT_BITS (1) + +#define SCS_CFSR *((volatile uint32_t *)0xE000ED28u) +#define SCS_CFSR_REG *((volatile uint32_t *)0xE000ED28u) +#define SCS_CFSR_ADDR (0xE000ED28u) +#define SCS_CFSR_RESET (0x00000000u) + /* DIVBYZERO field */ + #define SCS_CFSR_DIVBYZERO (0x02000000u) + #define SCS_CFSR_DIVBYZERO_MASK (0x02000000u) + #define SCS_CFSR_DIVBYZERO_BIT (25) + #define SCS_CFSR_DIVBYZERO_BITS (1) + /* UNALIGNED field */ + #define SCS_CFSR_UNALIGNED (0x01000000u) + #define SCS_CFSR_UNALIGNED_MASK (0x01000000u) + #define SCS_CFSR_UNALIGNED_BIT (24) + #define SCS_CFSR_UNALIGNED_BITS (1) + /* NOCP field */ + #define SCS_CFSR_NOCP (0x00080000u) + #define SCS_CFSR_NOCP_MASK (0x00080000u) + #define SCS_CFSR_NOCP_BIT (19) + #define SCS_CFSR_NOCP_BITS (1) + /* INVPC field */ + #define SCS_CFSR_INVPC (0x00040000u) + #define SCS_CFSR_INVPC_MASK (0x00040000u) + #define SCS_CFSR_INVPC_BIT (18) + #define SCS_CFSR_INVPC_BITS (1) + /* INVSTATE field */ + #define SCS_CFSR_INVSTATE (0x00020000u) + #define SCS_CFSR_INVSTATE_MASK (0x00020000u) + #define SCS_CFSR_INVSTATE_BIT (17) + #define SCS_CFSR_INVSTATE_BITS (1) + /* UNDEFINSTR field */ + #define SCS_CFSR_UNDEFINSTR (0x00010000u) + #define SCS_CFSR_UNDEFINSTR_MASK (0x00010000u) + #define SCS_CFSR_UNDEFINSTR_BIT (16) + #define SCS_CFSR_UNDEFINSTR_BITS (1) + /* BFARVALID field */ + #define SCS_CFSR_BFARVALID (0x00008000u) + #define SCS_CFSR_BFARVALID_MASK (0x00008000u) + #define SCS_CFSR_BFARVALID_BIT (15) + #define SCS_CFSR_BFARVALID_BITS (1) + /* STKERR field */ + #define SCS_CFSR_STKERR (0x00001000u) + #define SCS_CFSR_STKERR_MASK (0x00001000u) + #define SCS_CFSR_STKERR_BIT (12) + #define SCS_CFSR_STKERR_BITS (1) + /* UNSTKERR field */ + #define SCS_CFSR_UNSTKERR (0x00000800u) + #define SCS_CFSR_UNSTKERR_MASK (0x00000800u) + #define SCS_CFSR_UNSTKERR_BIT (11) + #define SCS_CFSR_UNSTKERR_BITS (1) + /* IMPRECISERR field */ + #define SCS_CFSR_IMPRECISERR (0x00000400u) + #define SCS_CFSR_IMPRECISERR_MASK (0x00000400u) + #define SCS_CFSR_IMPRECISERR_BIT (10) + #define SCS_CFSR_IMPRECISERR_BITS (1) + /* PRECISERR field */ + #define SCS_CFSR_PRECISERR (0x00000200u) + #define SCS_CFSR_PRECISERR_MASK (0x00000200u) + #define SCS_CFSR_PRECISERR_BIT (9) + #define SCS_CFSR_PRECISERR_BITS (1) + /* IBUSERR field */ + #define SCS_CFSR_IBUSERR (0x00000100u) + #define SCS_CFSR_IBUSERR_MASK (0x00000100u) + #define SCS_CFSR_IBUSERR_BIT (8) + #define SCS_CFSR_IBUSERR_BITS (1) + /* MMARVALID field */ + #define SCS_CFSR_MMARVALID (0x00000080u) + #define SCS_CFSR_MMARVALID_MASK (0x00000080u) + #define SCS_CFSR_MMARVALID_BIT (7) + #define SCS_CFSR_MMARVALID_BITS (1) + /* MSTKERR field */ + #define SCS_CFSR_MSTKERR (0x00000010u) + #define SCS_CFSR_MSTKERR_MASK (0x00000010u) + #define SCS_CFSR_MSTKERR_BIT (4) + #define SCS_CFSR_MSTKERR_BITS (1) + /* MUNSTKERR field */ + #define SCS_CFSR_MUNSTKERR (0x00000008u) + #define SCS_CFSR_MUNSTKERR_MASK (0x00000008u) + #define SCS_CFSR_MUNSTKERR_BIT (3) + #define SCS_CFSR_MUNSTKERR_BITS (1) + /* DACCVIOL field */ + #define SCS_CFSR_DACCVIOL (0x00000002u) + #define SCS_CFSR_DACCVIOL_MASK (0x00000002u) + #define SCS_CFSR_DACCVIOL_BIT (1) + #define SCS_CFSR_DACCVIOL_BITS (1) + /* IACCVIOL field */ + #define SCS_CFSR_IACCVIOL (0x00000001u) + #define SCS_CFSR_IACCVIOL_MASK (0x00000001u) + #define SCS_CFSR_IACCVIOL_BIT (0) + #define SCS_CFSR_IACCVIOL_BITS (1) + +#define SCS_HFSR *((volatile uint32_t *)0xE000ED2Cu) +#define SCS_HFSR_REG *((volatile uint32_t *)0xE000ED2Cu) +#define SCS_HFSR_ADDR (0xE000ED2Cu) +#define SCS_HFSR_RESET (0x00000000u) + /* DEBUGEVT field */ + #define SCS_HFSR_DEBUGEVT (0x80000000u) + #define SCS_HFSR_DEBUGEVT_MASK (0x80000000u) + #define SCS_HFSR_DEBUGEVT_BIT (31) + #define SCS_HFSR_DEBUGEVT_BITS (1) + /* FORCED field */ + #define SCS_HFSR_FORCED (0x40000000u) + #define SCS_HFSR_FORCED_MASK (0x40000000u) + #define SCS_HFSR_FORCED_BIT (30) + #define SCS_HFSR_FORCED_BITS (1) + /* VECTTBL field */ + #define SCS_HFSR_VECTTBL (0x00000002u) + #define SCS_HFSR_VECTTBL_MASK (0x00000002u) + #define SCS_HFSR_VECTTBL_BIT (1) + #define SCS_HFSR_VECTTBL_BITS (1) + +#define SCS_DFSR *((volatile uint32_t *)0xE000ED30u) +#define SCS_DFSR_REG *((volatile uint32_t *)0xE000ED30u) +#define SCS_DFSR_ADDR (0xE000ED30u) +#define SCS_DFSR_RESET (0x00000000u) + /* EXTERNAL field */ + #define SCS_DFSR_EXTERNAL (0x00000010u) + #define SCS_DFSR_EXTERNAL_MASK (0x00000010u) + #define SCS_DFSR_EXTERNAL_BIT (4) + #define SCS_DFSR_EXTERNAL_BITS (1) + /* VCATCH field */ + #define SCS_DFSR_VCATCH (0x00000008u) + #define SCS_DFSR_VCATCH_MASK (0x00000008u) + #define SCS_DFSR_VCATCH_BIT (3) + #define SCS_DFSR_VCATCH_BITS (1) + /* DWTTRAP field */ + #define SCS_DFSR_DWTTRAP (0x00000004u) + #define SCS_DFSR_DWTTRAP_MASK (0x00000004u) + #define SCS_DFSR_DWTTRAP_BIT (2) + #define SCS_DFSR_DWTTRAP_BITS (1) + /* BKPT field */ + #define SCS_DFSR_BKPT (0x00000002u) + #define SCS_DFSR_BKPT_MASK (0x00000002u) + #define SCS_DFSR_BKPT_BIT (1) + #define SCS_DFSR_BKPT_BITS (1) + /* HALTED field */ + #define SCS_DFSR_HALTED (0x00000001u) + #define SCS_DFSR_HALTED_MASK (0x00000001u) + #define SCS_DFSR_HALTED_BIT (0) + #define SCS_DFSR_HALTED_BITS (1) + +#define SCS_MMAR *((volatile uint32_t *)0xE000ED34u) +#define SCS_MMAR_REG *((volatile uint32_t *)0xE000ED34u) +#define SCS_MMAR_ADDR (0xE000ED34u) +#define SCS_MMAR_RESET (0x00000000u) + /* ADDRESS field */ + #define SCS_MMAR_ADDRESS (0xFFFFFFFFu) + #define SCS_MMAR_ADDRESS_MASK (0xFFFFFFFFu) + #define SCS_MMAR_ADDRESS_BIT (0) + #define SCS_MMAR_ADDRESS_BITS (32) + +#define SCS_BFAR *((volatile uint32_t *)0xE000ED38u) +#define SCS_BFAR_REG *((volatile uint32_t *)0xE000ED38u) +#define SCS_BFAR_ADDR (0xE000ED38u) +#define SCS_BFAR_RESET (0x00000000u) + /* ADDRESS field */ + #define SCS_BFAR_ADDRESS (0xFFFFFFFFu) + #define SCS_BFAR_ADDRESS_MASK (0xFFFFFFFFu) + #define SCS_BFAR_ADDRESS_BIT (0) + #define SCS_BFAR_ADDRESS_BITS (32) + +#define SCS_AFSR *((volatile uint32_t *)0xE000ED3Cu) +#define SCS_AFSR_REG *((volatile uint32_t *)0xE000ED3Cu) +#define SCS_AFSR_ADDR (0xE000ED3Cu) +#define SCS_AFSR_RESET (0x00000000u) + /* WRONGSIZE field */ + #define SCS_AFSR_WRONGSIZE (0x00000008u) + #define SCS_AFSR_WRONGSIZE_MASK (0x00000008u) + #define SCS_AFSR_WRONGSIZE_BIT (3) + #define SCS_AFSR_WRONGSIZE_BITS (1) + /* PROTECTED field */ + #define SCS_AFSR_PROTECTED (0x00000004u) + #define SCS_AFSR_PROTECTED_MASK (0x00000004u) + #define SCS_AFSR_PROTECTED_BIT (2) + #define SCS_AFSR_PROTECTED_BITS (1) + /* RESERVED field */ + #define SCS_AFSR_RESERVED (0x00000002u) + #define SCS_AFSR_RESERVED_MASK (0x00000002u) + #define SCS_AFSR_RESERVED_BIT (1) + #define SCS_AFSR_RESERVED_BITS (1) + /* MISSED field */ + #define SCS_AFSR_MISSED (0x00000001u) + #define SCS_AFSR_MISSED_MASK (0x00000001u) + #define SCS_AFSR_MISSED_BIT (0) + #define SCS_AFSR_MISSED_BITS (1) + +#define SCS_PFR0 *((volatile uint32_t *)0xE000ED40u) +#define SCS_PFR0_REG *((volatile uint32_t *)0xE000ED40u) +#define SCS_PFR0_ADDR (0xE000ED40u) +#define SCS_PFR0_RESET (0x00000030u) + /* FEATURE field */ + #define SCS_PFR0_FEATURE (0xFFFFFFFFu) + #define SCS_PFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_PFR0_FEATURE_BIT (0) + #define SCS_PFR0_FEATURE_BITS (32) + +#define SCS_PFR1 *((volatile uint32_t *)0xE000ED44u) +#define SCS_PFR1_REG *((volatile uint32_t *)0xE000ED44u) +#define SCS_PFR1_ADDR (0xE000ED44u) +#define SCS_PFR1_RESET (0x00000200u) + /* FEATURE field */ + #define SCS_PFR1_FEATURE (0xFFFFFFFFu) + #define SCS_PFR1_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_PFR1_FEATURE_BIT (0) + #define SCS_PFR1_FEATURE_BITS (32) + +#define SCS_DFR0 *((volatile uint32_t *)0xE000ED48u) +#define SCS_DFR0_REG *((volatile uint32_t *)0xE000ED48u) +#define SCS_DFR0_ADDR (0xE000ED48u) +#define SCS_DFR0_RESET (0x00100000u) + /* FEATURE field */ + #define SCS_DFR0_FEATURE (0xFFFFFFFFu) + #define SCS_DFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_DFR0_FEATURE_BIT (0) + #define SCS_DFR0_FEATURE_BITS (32) + +#define SCS_AFR0 *((volatile uint32_t *)0xE000ED4Cu) +#define SCS_AFR0_REG *((volatile uint32_t *)0xE000ED4Cu) +#define SCS_AFR0_ADDR (0xE000ED4Cu) +#define SCS_AFR0_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_AFR0_FEATURE (0xFFFFFFFFu) + #define SCS_AFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_AFR0_FEATURE_BIT (0) + #define SCS_AFR0_FEATURE_BITS (32) + +#define SCS_MMFR0 *((volatile uint32_t *)0xE000ED50u) +#define SCS_MMFR0_REG *((volatile uint32_t *)0xE000ED50u) +#define SCS_MMFR0_ADDR (0xE000ED50u) +#define SCS_MMFR0_RESET (0x00000030u) + /* FEATURE field */ + #define SCS_MMFR0_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR0_FEATURE_BIT (0) + #define SCS_MMFR0_FEATURE_BITS (32) + +#define SCS_MMFR1 *((volatile uint32_t *)0xE000ED54u) +#define SCS_MMFR1_REG *((volatile uint32_t *)0xE000ED54u) +#define SCS_MMFR1_ADDR (0xE000ED54u) +#define SCS_MMFR1_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_MMFR1_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR1_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR1_FEATURE_BIT (0) + #define SCS_MMFR1_FEATURE_BITS (32) + +#define SCS_MMFR2 *((volatile uint32_t *)0xE000ED58u) +#define SCS_MMFR2_REG *((volatile uint32_t *)0xE000ED58u) +#define SCS_MMFR2_ADDR (0xE000ED58u) +#define SCS_MMFR2_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_MMFR2_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR2_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR2_FEATURE_BIT (0) + #define SCS_MMFR2_FEATURE_BITS (32) + +#define SCS_MMFR3 *((volatile uint32_t *)0xE000ED5Cu) +#define SCS_MMFR3_REG *((volatile uint32_t *)0xE000ED5Cu) +#define SCS_MMFR3_ADDR (0xE000ED5Cu) +#define SCS_MMFR3_RESET (0x00000000u) + /* FEATURE field */ + #define SCS_MMFR3_FEATURE (0xFFFFFFFFu) + #define SCS_MMFR3_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_MMFR3_FEATURE_BIT (0) + #define SCS_MMFR3_FEATURE_BITS (32) + +#define SCS_ISAFR0 *((volatile uint32_t *)0xE000ED60u) +#define SCS_ISAFR0_REG *((volatile uint32_t *)0xE000ED60u) +#define SCS_ISAFR0_ADDR (0xE000ED60u) +#define SCS_ISAFR0_RESET (0x01141110u) + /* FEATURE field */ + #define SCS_ISAFR0_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR0_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR0_FEATURE_BIT (0) + #define SCS_ISAFR0_FEATURE_BITS (32) + +#define SCS_ISAFR1 *((volatile uint32_t *)0xE000ED64u) +#define SCS_ISAFR1_REG *((volatile uint32_t *)0xE000ED64u) +#define SCS_ISAFR1_ADDR (0xE000ED64u) +#define SCS_ISAFR1_RESET (0x02111000u) + /* FEATURE field */ + #define SCS_ISAFR1_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR1_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR1_FEATURE_BIT (0) + #define SCS_ISAFR1_FEATURE_BITS (32) + +#define SCS_ISAFR2 *((volatile uint32_t *)0xE000ED68u) +#define SCS_ISAFR2_REG *((volatile uint32_t *)0xE000ED68u) +#define SCS_ISAFR2_ADDR (0xE000ED68u) +#define SCS_ISAFR2_RESET (0x21112231u) + /* FEATURE field */ + #define SCS_ISAFR2_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR2_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR2_FEATURE_BIT (0) + #define SCS_ISAFR2_FEATURE_BITS (32) + +#define SCS_ISAFR3 *((volatile uint32_t *)0xE000ED6Cu) +#define SCS_ISAFR3_REG *((volatile uint32_t *)0xE000ED6Cu) +#define SCS_ISAFR3_ADDR (0xE000ED6Cu) +#define SCS_ISAFR3_RESET (0x11111110u) + /* FEATURE field */ + #define SCS_ISAFR3_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR3_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR3_FEATURE_BIT (0) + #define SCS_ISAFR3_FEATURE_BITS (32) + +#define SCS_ISAFR4 *((volatile uint32_t *)0xE000ED70u) +#define SCS_ISAFR4_REG *((volatile uint32_t *)0xE000ED70u) +#define SCS_ISAFR4_ADDR (0xE000ED70u) +#define SCS_ISAFR4_RESET (0x01310102u) + /* FEATURE field */ + #define SCS_ISAFR4_FEATURE (0xFFFFFFFFu) + #define SCS_ISAFR4_FEATURE_MASK (0xFFFFFFFFu) + #define SCS_ISAFR4_FEATURE_BIT (0) + #define SCS_ISAFR4_FEATURE_BITS (32) + +#define MPU_TYPE *((volatile uint32_t *)0xE000ED90u) +#define MPU_TYPE_REG *((volatile uint32_t *)0xE000ED90u) +#define MPU_TYPE_ADDR (0xE000ED90u) +#define MPU_TYPE_RESET (0x00000800u) + /* IREGION field */ + #define MPU_TYPE_IREGION (0x00FF0000u) + #define MPU_TYPE_IREGION_MASK (0x00FF0000u) + #define MPU_TYPE_IREGION_BIT (16) + #define MPU_TYPE_IREGION_BITS (8) + /* DREGION field */ + #define MPU_TYPE_DREGION (0x0000FF00u) + #define MPU_TYPE_DREGION_MASK (0x0000FF00u) + #define MPU_TYPE_DREGION_BIT (8) + #define MPU_TYPE_DREGION_BITS (8) + +#define MPU_CTRL *((volatile uint32_t *)0xE000ED94u) +#define MPU_CTRL_REG *((volatile uint32_t *)0xE000ED94u) +#define MPU_CTRL_ADDR (0xE000ED94u) +#define MPU_CTRL_RESET (0x00000000u) + /* PRIVDEFENA field */ + #define MPU_CTRL_PRIVDEFENA (0x00000004u) + #define MPU_CTRL_PRIVDEFENA_MASK (0x00000004u) + #define MPU_CTRL_PRIVDEFENA_BIT (2) + #define MPU_CTRL_PRIVDEFENA_BITS (1) + /* HFNMIENA field */ + #define MPU_CTRL_HFNMIENA (0x00000002u) + #define MPU_CTRL_HFNMIENA_MASK (0x00000002u) + #define MPU_CTRL_HFNMIENA_BIT (1) + #define MPU_CTRL_HFNMIENA_BITS (1) + /* ENABLE field */ + #define MPU_CTRL_ENABLE (0x00000001u) + #define MPU_CTRL_ENABLE_MASK (0x00000001u) + #define MPU_CTRL_ENABLE_BIT (0) + #define MPU_CTRL_ENABLE_BITS (1) + +#define MPU_REGION *((volatile uint32_t *)0xE000ED98u) +#define MPU_REGION_REG *((volatile uint32_t *)0xE000ED98u) +#define MPU_REGION_ADDR (0xE000ED98u) +#define MPU_REGION_RESET (0x00000000u) + /* REGION field */ + #define MPU_REGION_REGION (0x000000FFu) + #define MPU_REGION_REGION_MASK (0x000000FFu) + #define MPU_REGION_REGION_BIT (0) + #define MPU_REGION_REGION_BITS (8) + +#define MPU_BASE *((volatile uint32_t *)0xE000ED9Cu) +#define MPU_BASE_REG *((volatile uint32_t *)0xE000ED9Cu) +#define MPU_BASE_ADDR (0xE000ED9Cu) +#define MPU_BASE_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE_ADDRESS_BIT (5) + #define MPU_BASE_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE_VALID (0x00000010u) + #define MPU_BASE_VALID_MASK (0x00000010u) + #define MPU_BASE_VALID_BIT (4) + #define MPU_BASE_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE_REGION (0x0000000Fu) + #define MPU_BASE_REGION_MASK (0x0000000Fu) + #define MPU_BASE_REGION_BIT (0) + #define MPU_BASE_REGION_BITS (4) + +#define MPU_ATTR *((volatile uint32_t *)0xE000EDA0u) +#define MPU_ATTR_REG *((volatile uint32_t *)0xE000EDA0u) +#define MPU_ATTR_ADDR (0xE000EDA0u) +#define MPU_ATTR_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR_XN (0x10000000u) + #define MPU_ATTR_XN_MASK (0x10000000u) + #define MPU_ATTR_XN_BIT (28) + #define MPU_ATTR_XN_BITS (1) + /* AP field */ + #define MPU_ATTR_AP (0x07000000u) + #define MPU_ATTR_AP_MASK (0x07000000u) + #define MPU_ATTR_AP_BIT (24) + #define MPU_ATTR_AP_BITS (3) + /* TEX field */ + #define MPU_ATTR_TEX (0x00380000u) + #define MPU_ATTR_TEX_MASK (0x00380000u) + #define MPU_ATTR_TEX_BIT (19) + #define MPU_ATTR_TEX_BITS (3) + /* S field */ + #define MPU_ATTR_S (0x00040000u) + #define MPU_ATTR_S_MASK (0x00040000u) + #define MPU_ATTR_S_BIT (18) + #define MPU_ATTR_S_BITS (1) + /* C field */ + #define MPU_ATTR_C (0x00020000u) + #define MPU_ATTR_C_MASK (0x00020000u) + #define MPU_ATTR_C_BIT (17) + #define MPU_ATTR_C_BITS (1) + /* B field */ + #define MPU_ATTR_B (0x00010000u) + #define MPU_ATTR_B_MASK (0x00010000u) + #define MPU_ATTR_B_BIT (16) + #define MPU_ATTR_B_BITS (1) + /* SRD field */ + #define MPU_ATTR_SRD (0x0000FF00u) + #define MPU_ATTR_SRD_MASK (0x0000FF00u) + #define MPU_ATTR_SRD_BIT (8) + #define MPU_ATTR_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR_SIZE (0x0000003Eu) + #define MPU_ATTR_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR_SIZE_BIT (1) + #define MPU_ATTR_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR_ENABLE (0x00000001u) + #define MPU_ATTR_ENABLE_MASK (0x00000001u) + #define MPU_ATTR_ENABLE_BIT (0) + #define MPU_ATTR_ENABLE_BITS (1) + +#define MPU_BASE1 *((volatile uint32_t *)0xE000EDA4u) +#define MPU_BASE1_REG *((volatile uint32_t *)0xE000EDA4u) +#define MPU_BASE1_ADDR (0xE000EDA4u) +#define MPU_BASE1_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE1_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE1_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE1_ADDRESS_BIT (5) + #define MPU_BASE1_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE1_VALID (0x00000010u) + #define MPU_BASE1_VALID_MASK (0x00000010u) + #define MPU_BASE1_VALID_BIT (4) + #define MPU_BASE1_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE1_REGION (0x0000000Fu) + #define MPU_BASE1_REGION_MASK (0x0000000Fu) + #define MPU_BASE1_REGION_BIT (0) + #define MPU_BASE1_REGION_BITS (4) + +#define MPU_ATTR1 *((volatile uint32_t *)0xE000EDA8u) +#define MPU_ATTR1_REG *((volatile uint32_t *)0xE000EDA8u) +#define MPU_ATTR1_ADDR (0xE000EDA8u) +#define MPU_ATTR1_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR1_XN (0x10000000u) + #define MPU_ATTR1_XN_MASK (0x10000000u) + #define MPU_ATTR1_XN_BIT (28) + #define MPU_ATTR1_XN_BITS (1) + /* AP field */ + #define MPU_ATTR1_AP (0x07000000u) + #define MPU_ATTR1_AP_MASK (0x07000000u) + #define MPU_ATTR1_AP_BIT (24) + #define MPU_ATTR1_AP_BITS (3) + /* TEX field */ + #define MPU_ATTR1_TEX (0x00380000u) + #define MPU_ATTR1_TEX_MASK (0x00380000u) + #define MPU_ATTR1_TEX_BIT (19) + #define MPU_ATTR1_TEX_BITS (3) + /* S field */ + #define MPU_ATTR1_S (0x00040000u) + #define MPU_ATTR1_S_MASK (0x00040000u) + #define MPU_ATTR1_S_BIT (18) + #define MPU_ATTR1_S_BITS (1) + /* C field */ + #define MPU_ATTR1_C (0x00020000u) + #define MPU_ATTR1_C_MASK (0x00020000u) + #define MPU_ATTR1_C_BIT (17) + #define MPU_ATTR1_C_BITS (1) + /* B field */ + #define MPU_ATTR1_B (0x00010000u) + #define MPU_ATTR1_B_MASK (0x00010000u) + #define MPU_ATTR1_B_BIT (16) + #define MPU_ATTR1_B_BITS (1) + /* SRD field */ + #define MPU_ATTR1_SRD (0x0000FF00u) + #define MPU_ATTR1_SRD_MASK (0x0000FF00u) + #define MPU_ATTR1_SRD_BIT (8) + #define MPU_ATTR1_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR1_SIZE (0x0000003Eu) + #define MPU_ATTR1_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR1_SIZE_BIT (1) + #define MPU_ATTR1_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR1_ENABLE (0x00000001u) + #define MPU_ATTR1_ENABLE_MASK (0x00000001u) + #define MPU_ATTR1_ENABLE_BIT (0) + #define MPU_ATTR1_ENABLE_BITS (1) + +#define MPU_BASE2 *((volatile uint32_t *)0xE000EDACu) +#define MPU_BASE2_REG *((volatile uint32_t *)0xE000EDACu) +#define MPU_BASE2_ADDR (0xE000EDACu) +#define MPU_BASE2_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE2_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE2_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE2_ADDRESS_BIT (5) + #define MPU_BASE2_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE2_VALID (0x00000010u) + #define MPU_BASE2_VALID_MASK (0x00000010u) + #define MPU_BASE2_VALID_BIT (4) + #define MPU_BASE2_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE2_REGION (0x0000000Fu) + #define MPU_BASE2_REGION_MASK (0x0000000Fu) + #define MPU_BASE2_REGION_BIT (0) + #define MPU_BASE2_REGION_BITS (4) + +#define MPU_ATTR2 *((volatile uint32_t *)0xE000EDB0u) +#define MPU_ATTR2_REG *((volatile uint32_t *)0xE000EDB0u) +#define MPU_ATTR2_ADDR (0xE000EDB0u) +#define MPU_ATTR2_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR2_XN (0x10000000u) + #define MPU_ATTR2_XN_MASK (0x10000000u) + #define MPU_ATTR2_XN_BIT (28) + #define MPU_ATTR2_XN_BITS (1) + /* AP field */ + #define MPU_ATTR2_AP (0x1F000000u) + #define MPU_ATTR2_AP_MASK (0x1F000000u) + #define MPU_ATTR2_AP_BIT (24) + #define MPU_ATTR2_AP_BITS (5) + /* TEX field */ + #define MPU_ATTR2_TEX (0x00380000u) + #define MPU_ATTR2_TEX_MASK (0x00380000u) + #define MPU_ATTR2_TEX_BIT (19) + #define MPU_ATTR2_TEX_BITS (3) + /* S field */ + #define MPU_ATTR2_S (0x00040000u) + #define MPU_ATTR2_S_MASK (0x00040000u) + #define MPU_ATTR2_S_BIT (18) + #define MPU_ATTR2_S_BITS (1) + /* C field */ + #define MPU_ATTR2_C (0x00020000u) + #define MPU_ATTR2_C_MASK (0x00020000u) + #define MPU_ATTR2_C_BIT (17) + #define MPU_ATTR2_C_BITS (1) + /* B field */ + #define MPU_ATTR2_B (0x00010000u) + #define MPU_ATTR2_B_MASK (0x00010000u) + #define MPU_ATTR2_B_BIT (16) + #define MPU_ATTR2_B_BITS (1) + /* SRD field */ + #define MPU_ATTR2_SRD (0x0000FF00u) + #define MPU_ATTR2_SRD_MASK (0x0000FF00u) + #define MPU_ATTR2_SRD_BIT (8) + #define MPU_ATTR2_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR2_SIZE (0x0000003Eu) + #define MPU_ATTR2_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR2_SIZE_BIT (1) + #define MPU_ATTR2_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR2_ENABLE (0x00000003u) + #define MPU_ATTR2_ENABLE_MASK (0x00000003u) + #define MPU_ATTR2_ENABLE_BIT (0) + #define MPU_ATTR2_ENABLE_BITS (2) + +#define MPU_BASE3 *((volatile uint32_t *)0xE000EDB4u) +#define MPU_BASE3_REG *((volatile uint32_t *)0xE000EDB4u) +#define MPU_BASE3_ADDR (0xE000EDB4u) +#define MPU_BASE3_RESET (0x00000000u) + /* ADDRESS field */ + #define MPU_BASE3_ADDRESS (0xFFFFFFE0u) + #define MPU_BASE3_ADDRESS_MASK (0xFFFFFFE0u) + #define MPU_BASE3_ADDRESS_BIT (5) + #define MPU_BASE3_ADDRESS_BITS (27) + /* VALID field */ + #define MPU_BASE3_VALID (0x00000010u) + #define MPU_BASE3_VALID_MASK (0x00000010u) + #define MPU_BASE3_VALID_BIT (4) + #define MPU_BASE3_VALID_BITS (1) + /* REGION field */ + #define MPU_BASE3_REGION (0x0000000Fu) + #define MPU_BASE3_REGION_MASK (0x0000000Fu) + #define MPU_BASE3_REGION_BIT (0) + #define MPU_BASE3_REGION_BITS (4) + +#define MPU_ATTR3 *((volatile uint32_t *)0xE000EDBCu) +#define MPU_ATTR3_REG *((volatile uint32_t *)0xE000EDBCu) +#define MPU_ATTR3_ADDR (0xE000EDBCu) +#define MPU_ATTR3_RESET (0x00000000u) + /* XN field */ + #define MPU_ATTR3_XN (0x10000000u) + #define MPU_ATTR3_XN_MASK (0x10000000u) + #define MPU_ATTR3_XN_BIT (28) + #define MPU_ATTR3_XN_BITS (1) + /* AP field */ + #define MPU_ATTR3_AP (0x1F000000u) + #define MPU_ATTR3_AP_MASK (0x1F000000u) + #define MPU_ATTR3_AP_BIT (24) + #define MPU_ATTR3_AP_BITS (5) + /* TEX field */ + #define MPU_ATTR3_TEX (0x00380000u) + #define MPU_ATTR3_TEX_MASK (0x00380000u) + #define MPU_ATTR3_TEX_BIT (19) + #define MPU_ATTR3_TEX_BITS (3) + /* S field */ + #define MPU_ATTR3_S (0x00040000u) + #define MPU_ATTR3_S_MASK (0x00040000u) + #define MPU_ATTR3_S_BIT (18) + #define MPU_ATTR3_S_BITS (1) + /* C field */ + #define MPU_ATTR3_C (0x00020000u) + #define MPU_ATTR3_C_MASK (0x00020000u) + #define MPU_ATTR3_C_BIT (17) + #define MPU_ATTR3_C_BITS (1) + /* B field */ + #define MPU_ATTR3_B (0x00010000u) + #define MPU_ATTR3_B_MASK (0x00010000u) + #define MPU_ATTR3_B_BIT (16) + #define MPU_ATTR3_B_BITS (1) + /* SRD field */ + #define MPU_ATTR3_SRD (0x0000FF00u) + #define MPU_ATTR3_SRD_MASK (0x0000FF00u) + #define MPU_ATTR3_SRD_BIT (8) + #define MPU_ATTR3_SRD_BITS (8) + /* SIZE field */ + #define MPU_ATTR3_SIZE (0x0000003Eu) + #define MPU_ATTR3_SIZE_MASK (0x0000003Eu) + #define MPU_ATTR3_SIZE_BIT (1) + #define MPU_ATTR3_SIZE_BITS (5) + /* ENABLE field */ + #define MPU_ATTR3_ENABLE (0x00000003u) + #define MPU_ATTR3_ENABLE_MASK (0x00000003u) + #define MPU_ATTR3_ENABLE_BIT (0) + #define MPU_ATTR3_ENABLE_BITS (2) + +#define DEBUG_HCSR *((volatile uint32_t *)0xE000EDF0u) +#define DEBUG_HCSR_REG *((volatile uint32_t *)0xE000EDF0u) +#define DEBUG_HCSR_ADDR (0xE000EDF0u) +#define DEBUG_HCSR_RESET (0x00000000u) + /* S_RESET_ST field */ + #define DEBUG_HCSR_S_RESET_ST (0x02000000u) + #define DEBUG_HCSR_S_RESET_ST_MASK (0x02000000u) + #define DEBUG_HCSR_S_RESET_ST_BIT (25) + #define DEBUG_HCSR_S_RESET_ST_BITS (1) + /* S_RETIRE_ST field */ + #define DEBUG_HCSR_S_RETIRE_ST (0x01000000u) + #define DEBUG_HCSR_S_RETIRE_ST_MASK (0x01000000u) + #define DEBUG_HCSR_S_RETIRE_ST_BIT (24) + #define DEBUG_HCSR_S_RETIRE_ST_BITS (1) + /* S_LOCKUP field */ + #define DEBUG_HCSR_S_LOCKUP (0x00080000u) + #define DEBUG_HCSR_S_LOCKUP_MASK (0x00080000u) + #define DEBUG_HCSR_S_LOCKUP_BIT (19) + #define DEBUG_HCSR_S_LOCKUP_BITS (1) + /* S_SLEEP field */ + #define DEBUG_HCSR_S_SLEEP (0x00040000u) + #define DEBUG_HCSR_S_SLEEP_MASK (0x00040000u) + #define DEBUG_HCSR_S_SLEEP_BIT (18) + #define DEBUG_HCSR_S_SLEEP_BITS (1) + /* S_HALT field */ + #define DEBUG_HCSR_S_HALT (0x00020000u) + #define DEBUG_HCSR_S_HALT_MASK (0x00020000u) + #define DEBUG_HCSR_S_HALT_BIT (17) + #define DEBUG_HCSR_S_HALT_BITS (1) + /* S_REGRDY field */ + #define DEBUG_HCSR_S_REGRDY (0x00010000u) + #define DEBUG_HCSR_S_REGRDY_MASK (0x00010000u) + #define DEBUG_HCSR_S_REGRDY_BIT (16) + #define DEBUG_HCSR_S_REGRDY_BITS (1) + /* DBGKEY field */ + #define DEBUG_HCSR_DBGKEY (0xFFFF0000u) + #define DEBUG_HCSR_DBGKEY_MASK (0xFFFF0000u) + #define DEBUG_HCSR_DBGKEY_BIT (16) + #define DEBUG_HCSR_DBGKEY_BITS (16) + /* C_SNAPSTALL field */ + #define DEBUG_HCSR_C_SNAPSTALL (0x00000020u) + #define DEBUG_HCSR_C_SNAPSTALL_MASK (0x00000020u) + #define DEBUG_HCSR_C_SNAPSTALL_BIT (5) + #define DEBUG_HCSR_C_SNAPSTALL_BITS (1) + /* C_MASKINTS field */ + #define DEBUG_HCSR_C_MASKINTS (0x00000008u) + #define DEBUG_HCSR_C_MASKINTS_MASK (0x00000008u) + #define DEBUG_HCSR_C_MASKINTS_BIT (3) + #define DEBUG_HCSR_C_MASKINTS_BITS (1) + /* C_STEP field */ + #define DEBUG_HCSR_C_STEP (0x00000004u) + #define DEBUG_HCSR_C_STEP_MASK (0x00000004u) + #define DEBUG_HCSR_C_STEP_BIT (2) + #define DEBUG_HCSR_C_STEP_BITS (1) + /* C_HALT field */ + #define DEBUG_HCSR_C_HALT (0x00000002u) + #define DEBUG_HCSR_C_HALT_MASK (0x00000002u) + #define DEBUG_HCSR_C_HALT_BIT (1) + #define DEBUG_HCSR_C_HALT_BITS (1) + /* C_DEBUGEN field */ + #define DEBUG_HCSR_C_DEBUGEN (0x00000001u) + #define DEBUG_HCSR_C_DEBUGEN_MASK (0x00000001u) + #define DEBUG_HCSR_C_DEBUGEN_BIT (0) + #define DEBUG_HCSR_C_DEBUGEN_BITS (1) + +#define DEBUG_CRSR *((volatile uint32_t *)0xE000EDF4u) +#define DEBUG_CRSR_REG *((volatile uint32_t *)0xE000EDF4u) +#define DEBUG_CRSR_ADDR (0xE000EDF4u) +#define DEBUG_CRSR_RESET (0x00000000u) + /* REGWnR field */ + #define DEBUG_CRSR_REGWnR (0x00010000u) + #define DEBUG_CRSR_REGWnR_MASK (0x00010000u) + #define DEBUG_CRSR_REGWnR_BIT (16) + #define DEBUG_CRSR_REGWnR_BITS (1) + /* REGSEL field */ + #define DEBUG_CRSR_REGSEL (0x0000001Fu) + #define DEBUG_CRSR_REGSEL_MASK (0x0000001Fu) + #define DEBUG_CRSR_REGSEL_BIT (0) + #define DEBUG_CRSR_REGSEL_BITS (5) + +#define DEBUG_CRDR *((volatile uint32_t *)0xE000EDF8u) +#define DEBUG_CRDR_REG *((volatile uint32_t *)0xE000EDF8u) +#define DEBUG_CRDR_ADDR (0xE000EDF8u) +#define DEBUG_CRDR_RESET (0x00000000u) + /* DBGTMP field */ + #define DEBUG_CRDR_DBGTMP (0xFFFFFFFFu) + #define DEBUG_CRDR_DBGTMP_MASK (0xFFFFFFFFu) + #define DEBUG_CRDR_DBGTMP_BIT (0) + #define DEBUG_CRDR_DBGTMP_BITS (32) + +#define DEBUG_EMCR *((volatile uint32_t *)0xE000EDFCu) +#define DEBUG_EMCR_REG *((volatile uint32_t *)0xE000EDFCu) +#define DEBUG_EMCR_ADDR (0xE000EDFCu) +#define DEBUG_EMCR_RESET (0x00000000u) + /* TRCENA field */ + #define DEBUG_EMCR_TRCENA (0x01000000u) + #define DEBUG_EMCR_TRCENA_MASK (0x01000000u) + #define DEBUG_EMCR_TRCENA_BIT (24) + #define DEBUG_EMCR_TRCENA_BITS (1) + /* MON_REQ field */ + #define DEBUG_EMCR_MON_REQ (0x00080000u) + #define DEBUG_EMCR_MON_REQ_MASK (0x00080000u) + #define DEBUG_EMCR_MON_REQ_BIT (19) + #define DEBUG_EMCR_MON_REQ_BITS (1) + /* MON_STEP field */ + #define DEBUG_EMCR_MON_STEP (0x00040000u) + #define DEBUG_EMCR_MON_STEP_MASK (0x00040000u) + #define DEBUG_EMCR_MON_STEP_BIT (18) + #define DEBUG_EMCR_MON_STEP_BITS (1) + /* MON_PEND field */ + #define DEBUG_EMCR_MON_PEND (0x00020000u) + #define DEBUG_EMCR_MON_PEND_MASK (0x00020000u) + #define DEBUG_EMCR_MON_PEND_BIT (17) + #define DEBUG_EMCR_MON_PEND_BITS (1) + /* MON_EN field */ + #define DEBUG_EMCR_MON_EN (0x00010000u) + #define DEBUG_EMCR_MON_EN_MASK (0x00010000u) + #define DEBUG_EMCR_MON_EN_BIT (16) + #define DEBUG_EMCR_MON_EN_BITS (1) + /* VC_HARDERR field */ + #define DEBUG_EMCR_VC_HARDERR (0x00000400u) + #define DEBUG_EMCR_VC_HARDERR_MASK (0x00000400u) + #define DEBUG_EMCR_VC_HARDERR_BIT (10) + #define DEBUG_EMCR_VC_HARDERR_BITS (1) + /* VC_INTERR field */ + #define DEBUG_EMCR_VC_INTERR (0x00000200u) + #define DEBUG_EMCR_VC_INTERR_MASK (0x00000200u) + #define DEBUG_EMCR_VC_INTERR_BIT (9) + #define DEBUG_EMCR_VC_INTERR_BITS (1) + /* VC_BUSERR field */ + #define DEBUG_EMCR_VC_BUSERR (0x00000100u) + #define DEBUG_EMCR_VC_BUSERR_MASK (0x00000100u) + #define DEBUG_EMCR_VC_BUSERR_BIT (8) + #define DEBUG_EMCR_VC_BUSERR_BITS (1) + /* VC_STATERR field */ + #define DEBUG_EMCR_VC_STATERR (0x00000080u) + #define DEBUG_EMCR_VC_STATERR_MASK (0x00000080u) + #define DEBUG_EMCR_VC_STATERR_BIT (7) + #define DEBUG_EMCR_VC_STATERR_BITS (1) + /* VC_CHKERR field */ + #define DEBUG_EMCR_VC_CHKERR (0x00000040u) + #define DEBUG_EMCR_VC_CHKERR_MASK (0x00000040u) + #define DEBUG_EMCR_VC_CHKERR_BIT (6) + #define DEBUG_EMCR_VC_CHKERR_BITS (1) + /* VC_NOCPERR field */ + #define DEBUG_EMCR_VC_NOCPERR (0x00000020u) + #define DEBUG_EMCR_VC_NOCPERR_MASK (0x00000020u) + #define DEBUG_EMCR_VC_NOCPERR_BIT (5) + #define DEBUG_EMCR_VC_NOCPERR_BITS (1) + /* VC_MMERR field */ + #define DEBUG_EMCR_VC_MMERR (0x00000010u) + #define DEBUG_EMCR_VC_MMERR_MASK (0x00000010u) + #define DEBUG_EMCR_VC_MMERR_BIT (4) + #define DEBUG_EMCR_VC_MMERR_BITS (1) + /* VC_CORERESET field */ + #define DEBUG_EMCR_VC_CORERESET (0x00000001u) + #define DEBUG_EMCR_VC_CORERESET_MASK (0x00000001u) + #define DEBUG_EMCR_VC_CORERESET_BIT (0) + #define DEBUG_EMCR_VC_CORERESET_BITS (1) + +#define NVIC_STIR *((volatile uint32_t *)0xE000EF00u) +#define NVIC_STIR_REG *((volatile uint32_t *)0xE000EF00u) +#define NVIC_STIR_ADDR (0xE000EF00u) +#define NVIC_STIR_RESET (0x00000000u) + /* INTID field */ + #define NVIC_STIR_INTID (0x000003FFu) + #define NVIC_STIR_INTID_MASK (0x000003FFu) + #define NVIC_STIR_INTID_BIT (0) + #define NVIC_STIR_INTID_BITS (10) + +#define NVIC_PERIPHID4 *((volatile uint32_t *)0xE000EFD0u) +#define NVIC_PERIPHID4_REG *((volatile uint32_t *)0xE000EFD0u) +#define NVIC_PERIPHID4_ADDR (0xE000EFD0u) +#define NVIC_PERIPHID4_RESET (0x00000004u) + /* PERIPHID field */ + #define NVIC_PERIPHID4_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID4_PERIPHID_BIT (0) + #define NVIC_PERIPHID4_PERIPHID_BITS (32) + +#define NVIC_PERIPHID5 *((volatile uint32_t *)0xE000EFD4u) +#define NVIC_PERIPHID5_REG *((volatile uint32_t *)0xE000EFD4u) +#define NVIC_PERIPHID5_ADDR (0xE000EFD4u) +#define NVIC_PERIPHID5_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID5_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID5_PERIPHID_BIT (0) + #define NVIC_PERIPHID5_PERIPHID_BITS (32) + +#define NVIC_PERIPHID6 *((volatile uint32_t *)0xE000EFD8u) +#define NVIC_PERIPHID6_REG *((volatile uint32_t *)0xE000EFD8u) +#define NVIC_PERIPHID6_ADDR (0xE000EFD8u) +#define NVIC_PERIPHID6_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID6_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID6_PERIPHID_BIT (0) + #define NVIC_PERIPHID6_PERIPHID_BITS (32) + +#define NVIC_PERIPHID7 *((volatile uint32_t *)0xE000EFDCu) +#define NVIC_PERIPHID7_REG *((volatile uint32_t *)0xE000EFDCu) +#define NVIC_PERIPHID7_ADDR (0xE000EFDCu) +#define NVIC_PERIPHID7_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID7_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID7_PERIPHID_BIT (0) + #define NVIC_PERIPHID7_PERIPHID_BITS (32) + +#define NVIC_PERIPHID0 *((volatile uint32_t *)0xE000EFE0u) +#define NVIC_PERIPHID0_REG *((volatile uint32_t *)0xE000EFE0u) +#define NVIC_PERIPHID0_ADDR (0xE000EFE0u) +#define NVIC_PERIPHID0_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID0_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID0_PERIPHID_BIT (0) + #define NVIC_PERIPHID0_PERIPHID_BITS (32) + +#define NVIC_PERIPHID1 *((volatile uint32_t *)0xE000EFE4u) +#define NVIC_PERIPHID1_REG *((volatile uint32_t *)0xE000EFE4u) +#define NVIC_PERIPHID1_ADDR (0xE000EFE4u) +#define NVIC_PERIPHID1_RESET (0x000000B0u) + /* PERIPHID field */ + #define NVIC_PERIPHID1_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID1_PERIPHID_BIT (0) + #define NVIC_PERIPHID1_PERIPHID_BITS (32) + +#define NVIC_PERIPHID2 *((volatile uint32_t *)0xE000EFE8u) +#define NVIC_PERIPHID2_REG *((volatile uint32_t *)0xE000EFE8u) +#define NVIC_PERIPHID2_ADDR (0xE000EFE8u) +#define NVIC_PERIPHID2_RESET (0x0000001Bu) + /* PERIPHID field */ + #define NVIC_PERIPHID2_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID2_PERIPHID_BIT (0) + #define NVIC_PERIPHID2_PERIPHID_BITS (32) + +#define NVIC_PERIPHID3 *((volatile uint32_t *)0xE000EFECu) +#define NVIC_PERIPHID3_REG *((volatile uint32_t *)0xE000EFECu) +#define NVIC_PERIPHID3_ADDR (0xE000EFECu) +#define NVIC_PERIPHID3_RESET (0x00000000u) + /* PERIPHID field */ + #define NVIC_PERIPHID3_PERIPHID (0xFFFFFFFFu) + #define NVIC_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) + #define NVIC_PERIPHID3_PERIPHID_BIT (0) + #define NVIC_PERIPHID3_PERIPHID_BITS (32) + +#define NVIC_PCELLID0 *((volatile uint32_t *)0xE000EFF0u) +#define NVIC_PCELLID0_REG *((volatile uint32_t *)0xE000EFF0u) +#define NVIC_PCELLID0_ADDR (0xE000EFF0u) +#define NVIC_PCELLID0_RESET (0x0000000Du) + /* PCELLID field */ + #define NVIC_PCELLID0_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID0_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID0_PCELLID_BIT (0) + #define NVIC_PCELLID0_PCELLID_BITS (32) + +#define NVIC_PCELLID1 *((volatile uint32_t *)0xE000EFF4u) +#define NVIC_PCELLID1_REG *((volatile uint32_t *)0xE000EFF4u) +#define NVIC_PCELLID1_ADDR (0xE000EFF4u) +#define NVIC_PCELLID1_RESET (0x000000E0u) + /* PCELLID field */ + #define NVIC_PCELLID1_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID1_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID1_PCELLID_BIT (0) + #define NVIC_PCELLID1_PCELLID_BITS (32) + +#define NVIC_PCELLID2 *((volatile uint32_t *)0xE000EFF8u) +#define NVIC_PCELLID2_REG *((volatile uint32_t *)0xE000EFF8u) +#define NVIC_PCELLID2_ADDR (0xE000EFF8u) +#define NVIC_PCELLID2_RESET (0x00000005u) + /* PCELLID field */ + #define NVIC_PCELLID2_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID2_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID2_PCELLID_BIT (0) + #define NVIC_PCELLID2_PCELLID_BITS (32) + +#define NVIC_PCELLID3 *((volatile uint32_t *)0xE000EFFCu) +#define NVIC_PCELLID3_REG *((volatile uint32_t *)0xE000EFFCu) +#define NVIC_PCELLID3_ADDR (0xE000EFFCu) +#define NVIC_PCELLID3_RESET (0x000000B1u) + /* PCELLID field */ + #define NVIC_PCELLID3_PCELLID (0xFFFFFFFFu) + #define NVIC_PCELLID3_PCELLID_MASK (0xFFFFFFFFu) + #define NVIC_PCELLID3_PCELLID_BIT (0) + #define NVIC_PCELLID3_PCELLID_BITS (32) + +/* TPIU block */ +#define DATA_TPIU_BASE (0xE0040000u) +#define DATA_TPIU_END (0xE0040EF8u) +#define DATA_TPIU_SIZE (DATA_TPIU_END - DATA_TPIU_BASE + 1) + +#define TPIU_SPS *((volatile uint32_t *)0xE0040000u) +#define TPIU_SPS_REG *((volatile uint32_t *)0xE0040000u) +#define TPIU_SPS_ADDR (0xE0040000u) +#define TPIU_SPS_RESET (0x00000000u) + /* SPS_04 field */ + #define TPIU_SPS_SPS_04 (0x00000008u) + #define TPIU_SPS_SPS_04_MASK (0x00000008u) + #define TPIU_SPS_SPS_04_BIT (3) + #define TPIU_SPS_SPS_04_BITS (1) + /* SPS_03 field */ + #define TPIU_SPS_SPS_03 (0x00000004u) + #define TPIU_SPS_SPS_03_MASK (0x00000004u) + #define TPIU_SPS_SPS_03_BIT (2) + #define TPIU_SPS_SPS_03_BITS (1) + /* SPS_02 field */ + #define TPIU_SPS_SPS_02 (0x00000002u) + #define TPIU_SPS_SPS_02_MASK (0x00000002u) + #define TPIU_SPS_SPS_02_BIT (1) + #define TPIU_SPS_SPS_02_BITS (1) + /* SPS_01 field */ + #define TPIU_SPS_SPS_01 (0x00000001u) + #define TPIU_SPS_SPS_01_MASK (0x00000001u) + #define TPIU_SPS_SPS_01_BIT (0) + #define TPIU_SPS_SPS_01_BITS (1) + +#define TPIU_CPS *((volatile uint32_t *)0xE0040004u) +#define TPIU_CPS_REG *((volatile uint32_t *)0xE0040004u) +#define TPIU_CPS_ADDR (0xE0040004u) +#define TPIU_CPS_RESET (0x00000001u) + /* CPS_04 field */ + #define TPIU_CPS_CPS_04 (0x00000008u) + #define TPIU_CPS_CPS_04_MASK (0x00000008u) + #define TPIU_CPS_CPS_04_BIT (3) + #define TPIU_CPS_CPS_04_BITS (1) + /* CPS_03 field */ + #define TPIU_CPS_CPS_03 (0x00000004u) + #define TPIU_CPS_CPS_03_MASK (0x00000004u) + #define TPIU_CPS_CPS_03_BIT (2) + #define TPIU_CPS_CPS_03_BITS (1) + /* CPS_02 field */ + #define TPIU_CPS_CPS_02 (0x00000002u) + #define TPIU_CPS_CPS_02_MASK (0x00000002u) + #define TPIU_CPS_CPS_02_BIT (1) + #define TPIU_CPS_CPS_02_BITS (1) + /* CPS_01 field */ + #define TPIU_CPS_CPS_01 (0x00000001u) + #define TPIU_CPS_CPS_01_MASK (0x00000001u) + #define TPIU_CPS_CPS_01_BIT (0) + #define TPIU_CPS_CPS_01_BITS (1) + +#define TPIU_COSD *((volatile uint32_t *)0xE0040010u) +#define TPIU_COSD_REG *((volatile uint32_t *)0xE0040010u) +#define TPIU_COSD_ADDR (0xE0040010u) +#define TPIU_COSD_RESET (0x00000000u) + /* PRESCALER field */ + #define TPIU_COSD_PRESCALER (0x00001FFFu) + #define TPIU_COSD_PRESCALER_MASK (0x00001FFFu) + #define TPIU_COSD_PRESCALER_BIT (0) + #define TPIU_COSD_PRESCALER_BITS (13) + +#define TPIU_SPP *((volatile uint32_t *)0xE00400F0u) +#define TPIU_SPP_REG *((volatile uint32_t *)0xE00400F0u) +#define TPIU_SPP_ADDR (0xE00400F0u) +#define TPIU_SPP_RESET (0x00000001u) + /* PROTOCOL field */ + #define TPIU_SPP_PROTOCOL (0x00000003u) + #define TPIU_SPP_PROTOCOL_MASK (0x00000003u) + #define TPIU_SPP_PROTOCOL_BIT (0) + #define TPIU_SPP_PROTOCOL_BITS (2) + +#define TPIU_FFS *((volatile uint32_t *)0xE0040300u) +#define TPIU_FFS_REG *((volatile uint32_t *)0xE0040300u) +#define TPIU_FFS_ADDR (0xE0040300u) +#define TPIU_FFS_RESET (0x00000008u) + /* FTNONSTOP field */ + #define TPIU_FFS_FTNONSTOP (0x00000008u) + #define TPIU_FFS_FTNONSTOP_MASK (0x00000008u) + #define TPIU_FFS_FTNONSTOP_BIT (3) + #define TPIU_FFS_FTNONSTOP_BITS (1) + /* TCPRESENT field */ + #define TPIU_FFS_TCPRESENT (0x00000004u) + #define TPIU_FFS_TCPRESENT_MASK (0x00000004u) + #define TPIU_FFS_TCPRESENT_BIT (2) + #define TPIU_FFS_TCPRESENT_BITS (1) + /* FTSTOPPED field */ + #define TPIU_FFS_FTSTOPPED (0x00000002u) + #define TPIU_FFS_FTSTOPPED_MASK (0x00000002u) + #define TPIU_FFS_FTSTOPPED_BIT (1) + #define TPIU_FFS_FTSTOPPED_BITS (1) + /* FLINPROG field */ + #define TPIU_FFS_FLINPROG (0x00000001u) + #define TPIU_FFS_FLINPROG_MASK (0x00000001u) + #define TPIU_FFS_FLINPROG_BIT (0) + #define TPIU_FFS_FLINPROG_BITS (1) + +#define TPIU_FFC *((volatile uint32_t *)0xE0040304u) +#define TPIU_FFC_REG *((volatile uint32_t *)0xE0040304u) +#define TPIU_FFC_ADDR (0xE0040304u) +#define TPIU_FFC_RESET (0x00000102u) + /* TRIGIN field */ + #define TPIU_FFC_TRIGIN (0x00000100u) + #define TPIU_FFC_TRIGIN_MASK (0x00000100u) + #define TPIU_FFC_TRIGIN_BIT (8) + #define TPIU_FFC_TRIGIN_BITS (1) + /* ENFCONT field */ + #define TPIU_FFC_ENFCONT (0x00000002u) + #define TPIU_FFC_ENFCONT_MASK (0x00000002u) + #define TPIU_FFC_ENFCONT_BIT (1) + #define TPIU_FFC_ENFCONT_BITS (1) + +#define TPIU_FSC *((volatile uint32_t *)0xE0040308u) +#define TPIU_FSC_REG *((volatile uint32_t *)0xE0040308u) +#define TPIU_FSC_ADDR (0xE0040308u) +#define TPIU_FSC_RESET (0x00000000u) + /* FSC field */ + #define TPIU_FSC_FSC (0xFFFFFFFFu) + #define TPIU_FSC_FSC_MASK (0xFFFFFFFFu) + #define TPIU_FSC_FSC_BIT (0) + #define TPIU_FSC_FSC_BITS (32) + +#define TPIU_ITATBCTR2 *((volatile uint32_t *)0xE0040EF0u) +#define TPIU_ITATBCTR2_REG *((volatile uint32_t *)0xE0040EF0u) +#define TPIU_ITATBCTR2_ADDR (0xE0040EF0u) +#define TPIU_ITATBCTR2_RESET (0x00000000u) + /* ATREADY1 field */ + #define TPIU_ITATBCTR2_ATREADY1 (0x00000001u) + #define TPIU_ITATBCTR2_ATREADY1_MASK (0x00000001u) + #define TPIU_ITATBCTR2_ATREADY1_BIT (0) + #define TPIU_ITATBCTR2_ATREADY1_BITS (1) + +#define TPIU_ITATBCTR0 *((volatile uint32_t *)0xE0040EF8u) +#define TPIU_ITATBCTR0_REG *((volatile uint32_t *)0xE0040EF8u) +#define TPIU_ITATBCTR0_ADDR (0xE0040EF8u) +#define TPIU_ITATBCTR0_RESET (0x00000000u) + /* ATREADY1 field */ + #define TPIU_ITATBCTR0_ATREADY1 (0x00000001u) + #define TPIU_ITATBCTR0_ATREADY1_MASK (0x00000001u) + #define TPIU_ITATBCTR0_ATREADY1_BIT (0) + #define TPIU_ITATBCTR0_ATREADY1_BITS (1) + +/* ETM block */ +#define DATA_ETM_BASE (0xE0041000u) +#define DATA_ETM_END (0xE0041FFFu) +#define DATA_ETM_SIZE (DATA_ETM_END - DATA_ETM_BASE + 1) + +/* ROM_TAB block */ +#define DATA_ROM_TAB_BASE (0xE00FF000u) +#define DATA_ROM_TAB_END (0xE00FFFFFu) +#define DATA_ROM_TAB_SIZE (DATA_ROM_TAB_END - DATA_ROM_TAB_BASE + 1) + +#define ROM_SCS *((volatile uint32_t *)0xE00FF000u) +#define ROM_SCS_REG *((volatile uint32_t *)0xE00FF000u) +#define ROM_SCS_ADDR (0xE00FF000u) +#define ROM_SCS_RESET (0xFFF0F003u) + /* ADDR_OFF field */ + #define ROM_SCS_ADDR_OFF (0xFFFFF000u) + #define ROM_SCS_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_SCS_ADDR_OFF_BIT (12) + #define ROM_SCS_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_SCS_FORMAT (0x00000002u) + #define ROM_SCS_FORMAT_MASK (0x00000002u) + #define ROM_SCS_FORMAT_BIT (1) + #define ROM_SCS_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_SCS_ENTRY_PRES (0x00000001u) + #define ROM_SCS_ENTRY_PRES_MASK (0x00000001u) + #define ROM_SCS_ENTRY_PRES_BIT (0) + #define ROM_SCS_ENTRY_PRES_BITS (1) + +#define ROM_DWT *((volatile uint32_t *)0xE00FF004u) +#define ROM_DWT_REG *((volatile uint32_t *)0xE00FF004u) +#define ROM_DWT_ADDR (0xE00FF004u) +#define ROM_DWT_RESET (0xFFF02003u) + /* ADDR_OFF field */ + #define ROM_DWT_ADDR_OFF (0xFFFFF000u) + #define ROM_DWT_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_DWT_ADDR_OFF_BIT (12) + #define ROM_DWT_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_DWT_FORMAT (0x00000002u) + #define ROM_DWT_FORMAT_MASK (0x00000002u) + #define ROM_DWT_FORMAT_BIT (1) + #define ROM_DWT_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_DWT_ENTRY_PRES (0x00000001u) + #define ROM_DWT_ENTRY_PRES_MASK (0x00000001u) + #define ROM_DWT_ENTRY_PRES_BIT (0) + #define ROM_DWT_ENTRY_PRES_BITS (1) + +#define ROM_FPB *((volatile uint32_t *)0xE00FF008u) +#define ROM_FPB_REG *((volatile uint32_t *)0xE00FF008u) +#define ROM_FPB_ADDR (0xE00FF008u) +#define ROM_FPB_RESET (0xFFF03003u) + /* ADDR_OFF field */ + #define ROM_FPB_ADDR_OFF (0xFFFFF000u) + #define ROM_FPB_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_FPB_ADDR_OFF_BIT (12) + #define ROM_FPB_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_FPB_FORMAT (0x00000002u) + #define ROM_FPB_FORMAT_MASK (0x00000002u) + #define ROM_FPB_FORMAT_BIT (1) + #define ROM_FPB_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_FPB_ENTRY_PRES (0x00000001u) + #define ROM_FPB_ENTRY_PRES_MASK (0x00000001u) + #define ROM_FPB_ENTRY_PRES_BIT (0) + #define ROM_FPB_ENTRY_PRES_BITS (1) + +#define ROM_ITM *((volatile uint32_t *)0xE00FF00Cu) +#define ROM_ITM_REG *((volatile uint32_t *)0xE00FF00Cu) +#define ROM_ITM_ADDR (0xE00FF00Cu) +#define ROM_ITM_RESET (0xFFF01003u) + /* ADDR_OFF field */ + #define ROM_ITM_ADDR_OFF (0xFFFFF000u) + #define ROM_ITM_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_ITM_ADDR_OFF_BIT (12) + #define ROM_ITM_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_ITM_FORMAT (0x00000002u) + #define ROM_ITM_FORMAT_MASK (0x00000002u) + #define ROM_ITM_FORMAT_BIT (1) + #define ROM_ITM_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_ITM_ENTRY_PRES (0x00000001u) + #define ROM_ITM_ENTRY_PRES_MASK (0x00000001u) + #define ROM_ITM_ENTRY_PRES_BIT (0) + #define ROM_ITM_ENTRY_PRES_BITS (1) + +#define ROM_TPIU *((volatile uint32_t *)0xE00FF010u) +#define ROM_TPIU_REG *((volatile uint32_t *)0xE00FF010u) +#define ROM_TPIU_ADDR (0xE00FF010u) +#define ROM_TPIU_RESET (0xFFF0F003u) + /* ADDR_OFF field */ + #define ROM_TPIU_ADDR_OFF (0xFFFFF000u) + #define ROM_TPIU_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_TPIU_ADDR_OFF_BIT (12) + #define ROM_TPIU_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_TPIU_FORMAT (0x00000002u) + #define ROM_TPIU_FORMAT_MASK (0x00000002u) + #define ROM_TPIU_FORMAT_BIT (1) + #define ROM_TPIU_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_TPIU_ENTRY_PRES (0x00000001u) + #define ROM_TPIU_ENTRY_PRES_MASK (0x00000001u) + #define ROM_TPIU_ENTRY_PRES_BIT (0) + #define ROM_TPIU_ENTRY_PRES_BITS (1) + +#define ROM_ETM *((volatile uint32_t *)0xE00FF014u) +#define ROM_ETM_REG *((volatile uint32_t *)0xE00FF014u) +#define ROM_ETM_ADDR (0xE00FF014u) +#define ROM_ETM_RESET (0xFFF0F002u) + /* ADDR_OFF field */ + #define ROM_ETM_ADDR_OFF (0xFFFFF000u) + #define ROM_ETM_ADDR_OFF_MASK (0xFFFFF000u) + #define ROM_ETM_ADDR_OFF_BIT (12) + #define ROM_ETM_ADDR_OFF_BITS (20) + /* FORMAT field */ + #define ROM_ETM_FORMAT (0x00000002u) + #define ROM_ETM_FORMAT_MASK (0x00000002u) + #define ROM_ETM_FORMAT_BIT (1) + #define ROM_ETM_FORMAT_BITS (1) + /* ENTRY_PRES field */ + #define ROM_ETM_ENTRY_PRES (0x00000001u) + #define ROM_ETM_ENTRY_PRES_MASK (0x00000001u) + #define ROM_ETM_ENTRY_PRES_BIT (0) + #define ROM_ETM_ENTRY_PRES_BITS (1) + +#define ROM_END *((volatile uint32_t *)0xE00FF018u) +#define ROM_END_REG *((volatile uint32_t *)0xE00FF018u) +#define ROM_END_ADDR (0xE00FF018u) +#define ROM_END_RESET (0x00000000u) + /* END field */ + #define ROM_END_END (0xFFFFFFFFu) + #define ROM_END_END_MASK (0xFFFFFFFFu) + #define ROM_END_END_BIT (0) + #define ROM_END_END_BITS (32) + +#define ROM_MEMTYPE *((volatile uint32_t *)0xE00FFFCCu) +#define ROM_MEMTYPE_REG *((volatile uint32_t *)0xE00FFFCCu) +#define ROM_MEMTYPE_ADDR (0xE00FFFCCu) +#define ROM_MEMTYPE_RESET (0x00000001u) + /* MEMTYPE field */ + #define ROM_MEMTYPE_MEMTYPE (0x00000001u) + #define ROM_MEMTYPE_MEMTYPE_MASK (0x00000001u) + #define ROM_MEMTYPE_MEMTYPE_BIT (0) + #define ROM_MEMTYPE_MEMTYPE_BITS (1) + +#define ROM_PID4 *((volatile uint32_t *)0xE00FFFD0u) +#define ROM_PID4_REG *((volatile uint32_t *)0xE00FFFD0u) +#define ROM_PID4_ADDR (0xE00FFFD0u) +#define ROM_PID4_RESET (0x00000000u) + /* PID field */ + #define ROM_PID4_PID (0x0000000Fu) + #define ROM_PID4_PID_MASK (0x0000000Fu) + #define ROM_PID4_PID_BIT (0) + #define ROM_PID4_PID_BITS (4) + +#define ROM_PID5 *((volatile uint32_t *)0xE00FFFD4u) +#define ROM_PID5_REG *((volatile uint32_t *)0xE00FFFD4u) +#define ROM_PID5_ADDR (0xE00FFFD4u) +#define ROM_PID5_RESET (0x00000000u) + /* PID field */ + #define ROM_PID5_PID (0x0000000Fu) + #define ROM_PID5_PID_MASK (0x0000000Fu) + #define ROM_PID5_PID_BIT (0) + #define ROM_PID5_PID_BITS (4) + +#define ROM_PID6 *((volatile uint32_t *)0xE00FFFD8u) +#define ROM_PID6_REG *((volatile uint32_t *)0xE00FFFD8u) +#define ROM_PID6_ADDR (0xE00FFFD8u) +#define ROM_PID6_RESET (0x00000000u) + /* PID field */ + #define ROM_PID6_PID (0x0000000Fu) + #define ROM_PID6_PID_MASK (0x0000000Fu) + #define ROM_PID6_PID_BIT (0) + #define ROM_PID6_PID_BITS (4) + +#define ROM_PID7 *((volatile uint32_t *)0xE00FFFDCu) +#define ROM_PID7_REG *((volatile uint32_t *)0xE00FFFDCu) +#define ROM_PID7_ADDR (0xE00FFFDCu) +#define ROM_PID7_RESET (0x00000000u) + /* PID field */ + #define ROM_PID7_PID (0x0000000Fu) + #define ROM_PID7_PID_MASK (0x0000000Fu) + #define ROM_PID7_PID_BIT (0) + #define ROM_PID7_PID_BITS (4) + +#define ROM_PID0 *((volatile uint32_t *)0xE00FFFE0u) +#define ROM_PID0_REG *((volatile uint32_t *)0xE00FFFE0u) +#define ROM_PID0_ADDR (0xE00FFFE0u) +#define ROM_PID0_RESET (0x00000000u) + /* PID field */ + #define ROM_PID0_PID (0x0000000Fu) + #define ROM_PID0_PID_MASK (0x0000000Fu) + #define ROM_PID0_PID_BIT (0) + #define ROM_PID0_PID_BITS (4) + +#define ROM_PID1 *((volatile uint32_t *)0xE00FFFE4u) +#define ROM_PID1_REG *((volatile uint32_t *)0xE00FFFE4u) +#define ROM_PID1_ADDR (0xE00FFFE4u) +#define ROM_PID1_RESET (0x00000000u) + /* PID field */ + #define ROM_PID1_PID (0x0000000Fu) + #define ROM_PID1_PID_MASK (0x0000000Fu) + #define ROM_PID1_PID_BIT (0) + #define ROM_PID1_PID_BITS (4) + +#define ROM_PID2 *((volatile uint32_t *)0xE00FFFE8u) +#define ROM_PID2_REG *((volatile uint32_t *)0xE00FFFE8u) +#define ROM_PID2_ADDR (0xE00FFFE8u) +#define ROM_PID2_RESET (0x00000000u) + /* PID field */ + #define ROM_PID2_PID (0x0000000Fu) + #define ROM_PID2_PID_MASK (0x0000000Fu) + #define ROM_PID2_PID_BIT (0) + #define ROM_PID2_PID_BITS (4) + +#define ROM_PID3 *((volatile uint32_t *)0xE00FFFECu) +#define ROM_PID3_REG *((volatile uint32_t *)0xE00FFFECu) +#define ROM_PID3_ADDR (0xE00FFFECu) +#define ROM_PID3_RESET (0x00000000u) + /* PID field */ + #define ROM_PID3_PID (0x0000000Fu) + #define ROM_PID3_PID_MASK (0x0000000Fu) + #define ROM_PID3_PID_BIT (0) + #define ROM_PID3_PID_BITS (4) + +#define ROM_CID0 *((volatile uint32_t *)0xE00FFFF0u) +#define ROM_CID0_REG *((volatile uint32_t *)0xE00FFFF0u) +#define ROM_CID0_ADDR (0xE00FFFF0u) +#define ROM_CID0_RESET (0x0000000Du) + /* CID field */ + #define ROM_CID0_CID (0x000000FFu) + #define ROM_CID0_CID_MASK (0x000000FFu) + #define ROM_CID0_CID_BIT (0) + #define ROM_CID0_CID_BITS (8) + +#define ROM_CID1 *((volatile uint32_t *)0xE00FFFF4u) +#define ROM_CID1_REG *((volatile uint32_t *)0xE00FFFF4u) +#define ROM_CID1_ADDR (0xE00FFFF4u) +#define ROM_CID1_RESET (0x00000010u) + /* CID field */ + #define ROM_CID1_CID (0x000000FFu) + #define ROM_CID1_CID_MASK (0x000000FFu) + #define ROM_CID1_CID_BIT (0) + #define ROM_CID1_CID_BITS (8) + +#define ROM_CID2 *((volatile uint32_t *)0xE00FFFF8u) +#define ROM_CID2_REG *((volatile uint32_t *)0xE00FFFF8u) +#define ROM_CID2_ADDR (0xE00FFFF8u) +#define ROM_CID2_RESET (0x00000005u) + /* CID field */ + #define ROM_CID2_CID (0x000000FFu) + #define ROM_CID2_CID_MASK (0x000000FFu) + #define ROM_CID2_CID_BIT (0) + #define ROM_CID2_CID_BITS (8) + +#define ROM_CID3 *((volatile uint32_t *)0xE00FFFFCu) +#define ROM_CID3_REG *((volatile uint32_t *)0xE00FFFFCu) +#define ROM_CID3_ADDR (0xE00FFFFCu) +#define ROM_CID3_RESET (0x000000B1u) + /* CID field */ + #define ROM_CID3_CID (0x000000FFu) + #define ROM_CID3_CID_MASK (0x000000FFu) + #define ROM_CID3_CID_BIT (0) + #define ROM_CID3_CID_BITS (8) + +/* VENDOR block */ +#define DATA_VENDOR_BASE (0xE0100000u) +#define DATA_VENDOR_END (0xFFFFFFFFu) +#define DATA_VENDOR_SIZE (DATA_VENDOR_END - DATA_VENDOR_BASE + 1) + + +#endif /*REGS_H_*/ diff --git a/cpu/arm/stm32l152/rtimer-arch.c b/cpu/arm/stm32l152/rtimer-arch.c new file mode 100644 index 000000000..2a47efc87 --- /dev/null +++ b/cpu/arm/stm32l152/rtimer-arch.c @@ -0,0 +1,105 @@ +/* +* Copyright (c) 2012, STMicroelectronics. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the Institute nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +* +*/ + +#include "contiki.h" +#include "platform-conf.h" + +#include "sys/rtimer.h" +#include "sys/process.h" +#include "dev/watchdog.h" + +#include "stm32l1xx.h" +#include "stm32l1xx_hal_gpio.h" +#include "stm32l1xx_hal_rcc.h" +#include "stm32l1xx_hal_tim.h" +#include "stm32l1xx_hal_cortex.h" + + +volatile uint32_t rtimer_clock = 0uL; + +TIM_HandleTypeDef htim2; + +void TIM2_IRQHandler(void) +{ + /* clear interrupt pending flag */ + __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); + + rtimer_clock++; + +} + + +void rtimer_arch_init(void) +{ + TIM_ClockConfigTypeDef sClockSourceConfig; + TIM_OC_InitTypeDef sConfigOC; + + __TIM2_CLK_ENABLE(); + htim2.Instance = TIM2; + htim2.Init.Prescaler = PRESCALER; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 1; + + HAL_TIM_Base_Init(&htim2); + HAL_TIM_Base_Start_IT(&htim2); + + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig); + + HAL_TIM_OC_Init(&htim2); + + sConfigOC.OCMode = TIM_OCMODE_TIMING; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1); + + + __HAL_TIM_CLEAR_FLAG(&htim2, TIM_FLAG_UPDATE); + + /* Enable TIM2 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim2, TIM_IT_UPDATE); + + __HAL_TIM_ENABLE(&htim2); + + HAL_NVIC_SetPriority((IRQn_Type) TIM2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ((IRQn_Type)(TIM2_IRQn)); + +} + +rtimer_clock_t rtimer_arch_now(void) +{ + return rtimer_clock; +} + +void rtimer_arch_schedule(rtimer_clock_t t) +{ + +} diff --git a/cpu/arm/stm32l152/rtimer-arch.h b/cpu/arm/stm32l152/rtimer-arch.h new file mode 100644 index 000000000..d0c40dbcd --- /dev/null +++ b/cpu/arm/stm32l152/rtimer-arch.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + */ + +#ifndef __RTIMER_ARCH_H__ +#define __RTIMER_ARCH_H__ + +#include "contiki-conf.h" +#include "sys/clock.h" + +rtimer_clock_t rtimer_arch_now(void); +void rtimer_arch_disable_irq(void); +void rtimer_arch_enable_irq(void); + +#endif /* __RTIMER_ARCH_H__ */ diff --git a/cpu/arm/stm32l152/startup_stm32l152xe-IAR.s b/cpu/arm/stm32l152/startup_stm32l152xe-IAR.s new file mode 100644 index 000000000..3543a4546 --- /dev/null +++ b/cpu/arm/stm32l152/startup_stm32l152xe-IAR.s @@ -0,0 +1,546 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32l152xe.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 5-September-2014 +;* Description : STM32L152XE Devices vector for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;*

© COPYRIGHT(c) 2014 STMicroelectronics

+;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK COMP_ACQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_ACQ_IRQHandler + B COMP_ACQ_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/startup_stm32l152xe.s b/cpu/arm/stm32l152/startup_stm32l152xe.s new file mode 100644 index 000000000..a4e083e1d --- /dev/null +++ b/cpu/arm/stm32l152/startup_stm32l152xe.s @@ -0,0 +1,427 @@ +/** + ****************************************************************************** + * @file startup_stm32l152xe.s + * @author MCD Application Team + * @version V2.1.0 + * @date 16-January-2015 + * @brief STM32L152XE Devices vector table for + * Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L152XE devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + // .weak EXTI9_5_IRQHandler + // .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/cpu/arm/stm32l152/stm32l152xe_flash.icf b/cpu/arm/stm32l152/stm32l152xe_flash.icf new file mode 100644 index 000000000..3c134b79d --- /dev/null +++ b/cpu/arm/stm32l152/stm32l152xe_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20020000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/cpu/arm/stm32l152/stm32l1xx.h b/cpu/arm/stm32l152/stm32l1xx.h new file mode 100644 index 000000000..dcd0a4ccb --- /dev/null +++ b/cpu/arm/stm32l152/stm32l1xx.h @@ -0,0 +1,5169 @@ +/** + ****************************************************************************** + * @file stm32l1xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 31-December-2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx devices. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx + * @{ + */ + +#ifndef __STM32L1XX_H +#define __STM32L1XX_H + +#include "stdint.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32L1XX_MD) + #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx + microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. + + */ + +#if !defined (STM32L1XX_MD) + #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +//#define HSE_VALUE ((uint32_t)32000000) /*!< Value of the External oscillator in Hz*/ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ + +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ + +/** + * @brief STM32L1xx Standard Peripheral Library version number + */ +#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32L1XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 1 /*!< STM32L provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ +} IRQn_Type; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef int32_t vs32; +typedef int16_t vs16; +typedef int8_t vs8; + +typedef int32_t vsc32; /*!< Read Only */ +typedef int16_t vsc16; /*!< Read Only */ +typedef int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef uint32_t vu32; +typedef uint16_t vu16; +typedef uint8_t vu8; + +typedef uint32_t vuc32; /*!< Read Only */ +typedef uint16_t vuc16; /*!< Read Only */ +typedef uint8_t vuc8; /*!< Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source + module. Using the 'Options for File' dialog you can simply change the + 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + 'Options for Target' dialog. +*/ + #define __RAM_FUNC FLASH_Status + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ + #define __RAM_FUNC __ramfunc FLASH_Status + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".data")))". +*/ + #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) + +#elif defined ( __TASKING__ ) +/* TASKING Compiler + ---------------- + RAM functions are defined using a specific toolchain pragma. This pragma is + defined in the stm32l1xx_flash_ramfunc.c +*/ + #define __RAM_FUNC FLASH_Status + +#endif + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t SMPR3; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t SQR4; + __IO uint32_t SQR5; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t CCR; +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; + __IO uint32_t SR; +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t PECR; + __IO uint32_t PDKEYR; + __IO uint32_t PEKEYR; + __IO uint32_t PRGKEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t RDP; + __IO uint32_t USER; + __IO uint32_t WRP01; + __IO uint32_t WRP23; +} OB_TypeDef; + +/** + * @brief General Purpose IO + */ + +typedef struct +{ + __IO uint32_t MODER; + __IO uint16_t OTYPER; + uint16_t RESERVED0; + __IO uint32_t OSPEEDR; + __IO uint32_t PUPDR; + __IO uint16_t IDR; + uint16_t RESERVED1; + __IO uint16_t ODR; + uint16_t RESERVED2; + __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */ + __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */ + __IO uint32_t LCKR; + __IO uint32_t AFR[2]; +} GPIO_TypeDef; + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ + __IO uint32_t MEMRMP; + __IO uint32_t PMC; + __IO uint32_t EXTICR[4]; +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t FCR; + __IO uint32_t SR; + __IO uint32_t CLR; + uint32_t RESERVED; + __IO uint32_t RAM[16]; +} LCD_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t ICSCR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t AHBRSTR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t AHBLPENR; + __IO uint32_t APB2LPENR; + __IO uint32_t APB1LPENR; + __IO uint32_t CSR; +} RCC_TypeDef; + +/** + * @brief Routing Interface + */ + +typedef struct +{ + __IO uint32_t ICR; + __IO uint32_t ASCR1; + __IO uint32_t ASCR2; + __IO uint32_t HYSCR1; + __IO uint32_t HYSCR2; + __IO uint32_t HYSCR3; +} RI_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; + __IO uint32_t DR; + __IO uint32_t CR; + __IO uint32_t ISR; + __IO uint32_t PRER; + __IO uint32_t WUTR; + __IO uint32_t CALIBR; + __IO uint32_t ALRMAR; + __IO uint32_t ALRMBR; + __IO uint32_t WPR; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t TSTR; + __IO uint32_t TSDR; + uint32_t RESERVED3; + uint32_t RESERVED4; + __IO uint32_t TAFCR; + uint32_t RESERVED5; + uint32_t RESERVED6; + uint32_t RESERVED7; + __IO uint32_t BKP0R; + __IO uint32_t BKP1R; + __IO uint32_t BKP2R; + __IO uint32_t BKP3R; + __IO uint32_t BKP4R; + __IO uint32_t BKP5R; + __IO uint32_t BKP6R; + __IO uint32_t BKP7R; + __IO uint32_t BKP8R; + __IO uint32_t BKP9R; + __IO uint32_t BKP10R; + __IO uint32_t BKP11R; + __IO uint32_t BKP12R; + __IO uint32_t BKP13R; + __IO uint32_t BKP14R; + __IO uint32_t BKP15R; + __IO uint32_t BKP16R; + __IO uint32_t BKP17R; + __IO uint32_t BKP18R; + __IO uint32_t BKP19R; +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + uint32_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + uint32_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; + __IO uint16_t OR; + uint16_t RESERVED20; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define COMP_BASE (APB1PERIPH_BASE + 0x7C00) +#define RI_BASE (APB1PERIPH_BASE + 0x7C04) + +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define TIM9_BASE (APB2PERIPH_BASE + 0x0800) +#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) +#define TIM11_BASE (APB2PERIPH_BASE + 0x1000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC_BASE (APB2PERIPH_BASE + 0x2700) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define RCC_BASE (AHBPERIPH_BASE + 0x3800) + + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x6000) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) + + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define COMP ((COMP_TypeDef *) COMP_BASE) +#define RI ((RI_TypeDef *) RI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ +#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ + +#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR3 register *******************/ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR4 register *******************/ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR5 register *******************/ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ + + +/******************* Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ +#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ + +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for COMP_CSR register ********************/ +#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ + +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ + +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ + +#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*! +#include + +/* Variables */ +extern int errno; +register char * stack_ptr asm("sp"); + +/* Functions */ + +/** + _sbrk + Increase program data space. Malloc and related functions depend on this +**/ +caddr_t _sbrk(int incr) +{ + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) + { + errno = ENOMEM; + return (caddr_t) -1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + diff --git a/cpu/arm/stm32l152/uart.c b/cpu/arm/stm32l152/uart.c new file mode 100644 index 000000000..9813909d6 --- /dev/null +++ b/cpu/arm/stm32l152/uart.c @@ -0,0 +1,61 @@ +/** +****************************************************************************** +* @file uart.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Source file for UART read/write +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#include "console.h" +#include + + +size_t +_write(int handle, const unsigned char *buffer, size_t size) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < size; DataIdx++) + { + __io_putchar( *buffer++ ); + } + return size; +} + +size_t +_read(int handle, unsigned char *buffer, size_t size) +{ + /* scanf calls _read() with len=1024, so eat one character at time */ + *buffer = __io_getchar(); + return 1; +} diff --git a/cpu/arm/stm32l152/watchdog.c b/cpu/arm/stm32l152/watchdog.c new file mode 100644 index 000000000..8d8774140 --- /dev/null +++ b/cpu/arm/stm32l152/watchdog.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + * $Id: watchdog.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ + */ +/*---------------------------------------------------------------------------*/ +/** +* \file +* Watchdog +* \author +* Salvatore Pitrulli +*/ +/*---------------------------------------------------------------------------*/ + +#include + +#include "dev/watchdog.h" + + +/*---------------------------------------------------------------------------*/ +void +watchdog_init(void) +{ + +} +/*---------------------------------------------------------------------------*/ +void +watchdog_start(void) +{ + /* We setup the watchdog to reset the device after 2.048 seconds, + unless watchdog_periodic() is called. */ + //halInternalEnableWatchDog(); +} +/*---------------------------------------------------------------------------*/ +void +watchdog_periodic(void) +{ + /* This function is called periodically to restart the watchdog + timer. */ + //halResetWatchdog(); +} +/*---------------------------------------------------------------------------*/ +void +watchdog_stop(void) +{ + //halInternalDisableWatchDog(MICRO_DISABLE_WATCH_DOG_KEY); +} +/*---------------------------------------------------------------------------*/ +void +watchdog_reboot(void) +{ + //halReboot(); +} +/*---------------------------------------------------------------------------*/ diff --git a/examples/stm32nucleo-spirit1/sensor-demo/Makefile b/examples/stm32nucleo-spirit1/sensor-demo/Makefile new file mode 100644 index 000000000..2c980b1ec --- /dev/null +++ b/examples/stm32nucleo-spirit1/sensor-demo/Makefile @@ -0,0 +1,8 @@ +CONTIKI_PROJECT = sensor-demo +all: $(CONTIKI_PROJECT) + +TARGET=stm32nucleo-spirit1 +USE_SENSOR_BOARD=1 + +CONTIKI = ../../.. +include $(CONTIKI)/Makefile.include diff --git a/examples/stm32nucleo-spirit1/sensor-demo/README.md b/examples/stm32nucleo-spirit1/sensor-demo/README.md new file mode 100644 index 000000000..ee0213df9 --- /dev/null +++ b/examples/stm32nucleo-spirit1/sensor-demo/README.md @@ -0,0 +1,15 @@ +Sensors Demo +============ + +The sensors demo can be used to read the value of all sensors and print it every 5 seconds on the terminal. + +In order to use this example the X-NUCLEO-IKS01A1 expansion board featuring ST environmental and motions sensors +must used. It needs to be connected on top of the STM32 Nucleo L1 and the X-NUCLEO-IDS01A4 (or A5) +sub-1GHz RF communication boards. + +To build the example type: + + make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 USE_SENSOR_BOARD=1 + + + diff --git a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c new file mode 100644 index 000000000..779092199 --- /dev/null +++ b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c @@ -0,0 +1,139 @@ +/** +****************************************************************************** +* @file contiki-spirit1-main.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Contiki main file for SPIRIT1 platform +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/** + * \file + * A very simple Contiki application showing sensor values for ST Nucleo + */ + +#include "contiki.h" + +#include /* For printf() */ + +#include "net/ip/uip.h" +#include "net/ipv6/uip-ds6.h" +#include "net/ip/uip-udp-packet.h" + +#include "dev/button-sensor.h" +#include "dev/leds.h" + +#ifdef COMPILE_SENSORS +#include "dev/temperature-sensor.h" +#include "dev/humidity-sensor.h" +#include "dev/pressure-sensor.h" +#include "dev/magneto-sensor.h" +#include "dev/acceleration-sensor.h" +#include "dev/gyroscope-sensor.h" +#endif /*COMPILE_SENSORS*/ + +#define DEBUG DEBUG_PRINT +#include "net/ip/uip-debug.h" + +#define PRINT_INTERVAL 5*CLOCK_SECOND + +/*---------------------------------------------------------------------------*/ +PROCESS(sensor_demo_process, "Sensor demo process"); +AUTOSTART_PROCESSES(&sensor_demo_process); +/*---------------------------------------------------------------------------*/ +PROCESS_THREAD(sensor_demo_process, ev, data) +{ + static struct etimer etimer; + static unsigned long _button_pressed; + + PROCESS_BEGIN(); + PROCESS_PAUSE(); + + SENSORS_ACTIVATE(button_sensor); + +#ifdef COMPILE_SENSORS + SENSORS_ACTIVATE(temperature_sensor); + SENSORS_ACTIVATE(humidity_sensor); + SENSORS_ACTIVATE(pressure_sensor); + SENSORS_ACTIVATE(magneto_sensor); + SENSORS_ACTIVATE(acceleration_sensor); + SENSORS_ACTIVATE(gyroscope_sensor); +#endif + + while(1) + { + etimer_set(&etimer, PRINT_INTERVAL); + + PROCESS_WAIT_EVENT(); + if (ev == sensors_event && data == &button_sensor) + { + printf("Sensor event detected: Button Pressed.\n\n"); + printf("Toggling Leds\n"); + _button_pressed++; + leds_toggle(LEDS_ALL); + } + + + printf("Button state:\t%s (pressed %lu times)\n", button_sensor.value(0)?"Released":"Pressed", + _button_pressed); + +#ifdef COMPILE_SENSORS + printf("LEDs status:\tRED:n/a GREEN:%s\n", leds_get()&LEDS_GREEN?"on":"off"); +#else + printf("LEDs status:\tRED:%s GREEN:%s\n", leds_get()&LEDS_RED?"on":"off", + leds_get()&LEDS_GREEN?"on":"off"); +#endif /*COMPILE_SENSORS*/ + +#ifdef COMPILE_SENSORS + printf("Temperature:\t%d.%d C\n", temperature_sensor.value(0)/10, temperature_sensor.value(0)%10); + + printf("Humidity:\t%d.%d rH\n", humidity_sensor.value(0)/10, humidity_sensor.value(0)%10); + + printf("Pressure:\t%d.%d mbar\n", pressure_sensor.value(0)/10, pressure_sensor.value(0)%10); + + printf("Magneto:\t%d/%d/%d (X/Y/Z) mgauss\n", magneto_sensor.value(X_AXIS), + magneto_sensor.value(Y_AXIS), + magneto_sensor.value(Z_AXIS)); + + printf("Acceleration:\t%d/%d/%d (X/Y/Z) mg\n", acceleration_sensor.value(X_AXIS), + acceleration_sensor.value(Y_AXIS), + acceleration_sensor.value(Z_AXIS)); + + printf("Gyroscope:\t%d/%d/%d (X/Y/Z) mdps\n", gyroscope_sensor.value(X_AXIS), + gyroscope_sensor.value(Y_AXIS), + gyroscope_sensor.value(Z_AXIS)); +#endif + + printf ("\n"); + } + + PROCESS_END(); +} +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 new file mode 100644 index 000000000..037e64be8 --- /dev/null +++ b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 @@ -0,0 +1,207 @@ + +CONTIKI_TARGET_DIRS = . + + +ifeq ($(USE_SENSOR_BOARD),1) + COMPILE_SENSORS=TRUE + CFLAGS += -DCOMPILE_SENSORS + ${info Compiling with Sensor Files} +else + COMPILE_SENSORS=FALSE + ${info NOT compiling Sensor Files} +endif + + +ifeq ($(USE_SUBGHZ_BOARD),IDS01A4) + CFLAGS += -DX_NUCLEO_IDS01A4 + ${info Using 868 MHz SPIRIT1 Board} +else ifeq ($(USE_SUBGHZ_BOARD),IDS01A5) + CFLAGS += -DX_NUCLEO_IDS01A5 + ${info Using 915 MHz SPIRIT1 Board} +else + ${info You must specify which SPIRIT1 board you use:} + ${info make USE_SUBGHZ_BOARD=IDS01A4 for 868 MHz} + ${info make USE_SUBGHZ_BOARD=IDS01A5 for 915 MHz} + ${error } +endif + + +#Currently we support only GCC +GCC=1 + +CONTIKI_TARGET_DIRS += stm32cube-hal/Src +CONTIKI_TARGET_DIRS += dev +CONTIKI_TARGET_DIRS += drivers/stm32l1xx_nucleo +CONTIKI_TARGET_DIRS += drivers/x_nucleo_ids01ax +CONTIKI_TARGET_DIRS += drivers/Common +CONTIKI_TARGET_DIRS += drivers/spirit1/src drivers/spirit1/inc + +ifeq ($(COMPILE_SENSORS),TRUE) +CONTIKI_TARGET_DIRS += drivers/x_nucleo_iks01a1 +CONTIKI_TARGET_DIRS += drivers/sensors/hts221 drivers/sensors/lps25h drivers/sensors/lps25hb\ + drivers/sensors/lsm6ds0 drivers/sensors/lsm6ds3 drivers/sensors/lis3mdl +endif + + +ARCH_DEV = button-sensor.c leds-arch.c + +ARCH_DEV_SENSORS = temperature-sensor.c humidity-sensor.c pressure-sensor.c magneto-sensor.c acceleration-sensor.c gyroscope-sensor.c + +ARCH_NUCLEOSPIRIT1 = contiki-spirit1-main.c uart-msg.c spirit1-arch.c spirit1.c node-id.c + +ARCH_NUCLEOSPIRIT1_STM32CUBEHAL = spirit1_appli.c stm32l1xx_hal_msp.c stm32l1xx_it.c stm32cube_hal_init.c + +ARCH_DRIVERS_STM32L1xx = stm32l1xx_nucleo.c + +ARCH_DRIVERS_IDS01AX = radio_gpio.c radio_shield_config.c radio_spi.c + +ARCH_DRIVERS_SPIRIT1 = \ + SPIRIT1_Util.c \ + SPIRIT_Aes.c \ + SPIRIT_Calibration.c \ + SPIRIT_Commands.c \ + SPIRIT_Csma.c \ + SPIRIT_DirectRF.c \ + SPIRIT_General.c \ + SPIRIT_Gpio.c \ + SPIRIT_Irq.c \ + SPIRIT_LinearFifo.c \ + SPIRIT_Management.c \ + SPIRIT_PktBasic.c \ + SPIRIT_PktCommon.c \ + SPIRIT_PktMbus.c \ + SPIRIT_PktStack.c \ + SPIRIT_Qi.c \ + SPIRIT_Radio.c \ + SPIRIT_Timer.c \ + SPIRIT_Types.c + +ARCH_DRIVERS_IKS01A1 = x_nucleo_iks01a1.c x_nucleo_iks01a1_hum_temp.c x_nucleo_iks01a1_imu_6axes.c \ + x_nucleo_iks01a1_magneto.c x_nucleo_iks01a1_pressure.c + +ARCH_DRIVERS_SENSORS = hts221.c \ + lis3mdl.c \ + lps25h.c \ + lps25hb.c \ + lsm6ds0.c \ + lsm6ds3.c + +ARCH+=$(ARCH_DEV) +ARCH+=$(ARCH_NUCLEOSPIRIT1) +ARCH+=$(ARCH_NUCLEOSPIRIT1_STM32CUBEHAL) +ARCH+=$(ARCH_DRIVERS_STM32L1xx) +ARCH+=$(ARCH_DRIVERS_IDS01AX) +ARCH+=$(ARCH_DRIVERS_SPIRIT1) + +ifeq ($(COMPILE_SENSORS),TRUE) + ARCH+=$(ARCH_DEV_SENSORS) + ARCH+=$(ARCH_DRIVERS_IKS01A1) + ARCH+=$(ARCH_DRIVERS_SENSORS) +endif + +CFLAGS += -DUSE_STM32L152_EVAL \ + -DSTM32L152xE \ + -DUSE_STM32L1XX_NUCLEO \ + -DUSE_HAL_DRIVER \ + -DUSE_STDPERIPH_DRIVER \ + -DNO_EEPROM \ + -DSPIRIT1_ST_SHIELD \ + -DSPIRIT_MODULE \ + -DUSE_SPIRIT1_DEFAULT + +CFLAGS += -I. \ + -I$(CONTIKI)/platform/$(TARGET)/ \ + -I$(CONTIKI)/platform/$(TARGET)/stm32cube-hal/Inc \ + -I$(CONTIKI)/platform/$(TARGET)/drivers/Common \ + -I$(CONTIKI)/platform/$(TARGET)/divers/x_nucleo_ids01ax\ + -I$(CONTIKI)/platform/$(TARGET)/drivers/spirit1/inc \ + -I$(CONTIKI)/cpu/arm/stm32l152/CMSIS \ + -I$(CONTIKI)/platform/$(TARGET)/drvers/stm32l1xx_nucleo \ + -I$(CONTIKI)/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc \ + -I$(CONTIKI)/cpu/arm/stm32l152 \ + -I$(CONTIKI)/core \ + -I$(CONTIKI)/platform/$(TARGET)/dev + + +ifdef UIP_CONF_IPV6 +CFLAGS += -DWITH_UIP6=1 +endif + + +ifndef CONTIKI_TARGET_MAIN +CONTIKI_TARGET_MAIN = contiki-spirit1-main.c +endif + +CONTIKI_TARGET_SOURCEFILES += $(ARCH) $(CONTIKI_TARGET_MAIN) + +MCU=stm32l152 +CONTIKI_CPU=$(CONTIKI)/cpu/arm/stm32l152 +include $(CONTIKI)/cpu/arm/stm32l152/Makefile.stm32l152 + + +MODULES+=core/net \ + core/net/mac core/net/mac/contikimac \ + core/net/llsec + + +# build rules ------------------------------------ + +CLEAN += *.stm32nucleo-spirit1 symbols.c symbols.h contiki-stm32nucleo-spirit1.log + +contiki-$(TARGET).a: ${addprefix $(OBJECTDIR)/,symbols.o} + +help: + @echo A few useful make commands: + @echo make help - shows this help + @echo make TARGET=stm32nucleo-spirit1 savetarget - stores selection of target to avoid using TARGET= on every make invokation + @echo make program.upload - compiles and uploads program to connected board + @echo make program.upload IAR=1 - uses the IAR compiler instead of gcc (not implemented yet) + @echo make program.upload NODEID=x - uploads with node_id set to x + +# Serialdump rules +ifeq ($(HOST_OS),Windows) + SERIALDUMP = serialdump-windows + # this ID is a string with which the node identifies itself as, and is used to + # find the proper /dev/comX-port in Cygwin to connect to. + CYGWIN_DEV_ID="stm32nucleo-spirit1 Spirit1 Platform" +# include $(CONTIKI)/tools/cygwin/Makefile.cygwin +endif +ifeq ($(HOST_OS),Darwin) + SERIALDUMP = serialdump-macos +endif +ifndef SERIALDUMP + # Assume Linux + SERIALDUMP = serialdump-linux +endif + +# IAR/windows/cygwin only for now; after GCC port, see if stm32flash works with Linux +STLINKCLI=ST-LINK_CLI.exe +%.upload: %.hex + #Note: this command only uploads to a single connected device + #$(STLINKCLI) -ME || $(STLINKCLI) -ME || $(STLINKCLI) -ME || $(STLINKCLI) -ME + $(STLINKCLI) -Q -P $*.hex -V -Run + + +# devcon requires WinDriverKit, downloadable from microsoft.com +DEVCON=devcon.exe +DEVCON_ALLDEVS=$(shell $(DEVCON) find =USB | grep "STMicroelectronics STLink dongle" | cut -d " " -f 1) +devcon_enableonly: + devcon disable =USB @"USB\VID_0483&PID_3748\*" + devcon enable =USB @"$(ID)" + +%.uploadall: %.hex + $(foreach D,$(DEVCON_ALLDEVS), echo D IS "$(D)" && make devcon_enableonly ID="$(D)" && make $*.upload && ) echo "Done" + devcon enable =USB @"USB\VID_0483&PID_3748\*" + +login: + @echo "Connecting to $(COMPORT)" + $(CONTIKI)/tools/sky/$(SERIALDUMP) -b115200 $(COMPORT) + +%.ramusage: %.$(TARGET) + $(NM) -S $< --size-sort --line-numbers | grep -v " T " | grep -v " t " +%.romusage: %.$(TARGET) + $(NM) -S $< --size-sort --line-numbers | grep -v " b " | grep -v " B " | grep -v " d " | grep -v " D " + + + + diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md new file mode 100644 index 000000000..ab4498f05 --- /dev/null +++ b/platform/stm32nucleo-spirit1/README.md @@ -0,0 +1,131 @@ +Getting Started with Contiki for STM32 Nucleo equipped with sub-1GHz SPIRIT1 expansion boards +============================================================================================= + +This guide explains how get started with the STM32 Nucleo and expansion boards port to Contiki. + +Port Feature +============ + +The port supports the following boards from ST: +- NUCLEO-L152RE board, based on the STM32L152RET6 ultra-low power microcontroller +- X-NUCLEO-IDS01A4 based on sub-1GHz SPSGRF-868 SPIRIT1 module (operating at 868 MHz) +- X-NUCLEO-IDS01A5 based on sub-1GHz SPSGRF-915 SPIRIT1 module (operating at 915 MHz) +- X-NUCLEO-IKS01A1 featuring motion MEMS and environmental sensors (optional) + +The following drivers are included: +- LEDs and buttons (user, reset) +- USB +- SPIRIT1 sub-1GHz transceiver +- HTS221, LIS3MDL, LPS25H, LSM6DS0 sensors + + +Hardware Requirements +===================== + +* NUCLEO-L152RE development board + + >The NUCLEO-L152RE board belongs to the STM32 Nucleo family. +It features an STM32L152RET6 ultra-low power microcontroller based on ARM Cortex M3 MCU. +Detailed information on the NUCLEO-L152RE development board can be found at: +http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002 + + +* X-NUCLEO-IDS01Ax sub-1GHz expansion board + + >The X-NUCLEO-IDS01A4 and X-NUCLEO-IDS01A5 are STM32 Nucleo expansion boards that use +the module SPSGRF-868 or SPSGRF-915 based on SPIRIT1 low data rate, low power sub-1 GHz transceiver. +The user can select the X-NUCLEO-IDS01A4 board to operate the SPIRIT1 transceiver at 868MHz +or the X-NUCLEO-IDS01A5 board to operate the SPIRIT1 transceiver at 915MHz. +Detailed information on the X-NUCLEO-IDS01A4 expansion board can be found at: +http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261982 +Detailed information on the X-NUCLEO-IDS01A5 expansion board can be found at: +http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261983 +Detailed information on the SPIRIT1 sub-1GHz transceiver can be found at: +http://www.st.com/web/catalog/sense_power/FM2185/SC1845/PF253167 + +* X-NUCLEO-IKS01A1, motion MEMS and environmental sensors expansion board (OPTIONAL) + + >The X-NUCLEO-IKS01A1 is a motion MEMS and environmental sensor evaluation board. +The use of this board is optional in the stm32nucleo-spirit1 Contiki platform. +Drivers are currently included in the platform folder but the sensors APIs are not +yet integrated with Contiki APIs. This feature will be provided soon. +Detailed information on the X-NUCLEO-IKS01A1 expansion board can be found at: +http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261191 + + +* USB type A to Mini-B USB cable, to connect the STM32 Nucleo board to the PC + +Software Requirements +===================== + +The following software are needed: + +* ST port of Contiki for STM32 Nucleo and expansion boards. +>The port is installed automatically when the Contiki repository is cloned. +The platform name is: stm32nucleo-spirit1 + +* A toolchain to build the firmware: The port has been developed and tested with GNU Tools +for ARM Embedded Processors. +>The toolchain can be found at: https://launchpad.net/gcc-arm-embedded +The port was developed and tested using this version: gcc-arm-none-eabi v4.83 + + +Examples +======== + +The following examples have been successfully tested: + +* Examples located in: examples/ipv6/simple-udp-rpl + + +Build an example +================ +In order to build an example go to the selected example directory (see a list of tested +examples in the previous section). + +For example, go to examples/ipv6/simple-udp-rpl directory. + + +If the X-NUCLEO-IDS01A4 sub-1GHz RF expansion board is used, the following must be run: + + make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 clean + make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 + +If the X-NUCLEO-IDS01A5 sub-1GHz RF expansion board is used, the following must be run: + + make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A5 clean + make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A5 + + +This will create executables for UDP sender and receiver nodes. + +These executables can be programmed on the nodes using the procedure described hereafter. + +System setup +============ + +1. Check that the jumper on the J1 connector on the X-NUCLEO-IDS01Ax expansion board is connected. +This jumper provides the required voltage to the devices on the board. + +2. Connect the X-NUCLEO-IDS01Ax board to the STM32 Nucleo board (NUCLEO-L152RE) from the top. + +3. Power the STM32 Nucleo board using the Mini-B USB cable connected to the PC. + +4. Program the firmware on the STM32 Nucleo board. +This can be done by copying the binary file on the USB mass storage that is +automatically created when plugging the STM32 Nucleo board to the PC. +On Linux machines the serial port device is located in /dev/ttyACMx (x depends on the PC). + +5. Reset the MCU by using the reset button on the STM32 Nucleo board + + +Know Limitations +================ + +* The border router functionality is not yet fully supported. + + + + + + diff --git a/platform/stm32nucleo-spirit1/contiki-conf.h b/platform/stm32nucleo-spirit1/contiki-conf.h new file mode 100644 index 000000000..f77e4d35d --- /dev/null +++ b/platform/stm32nucleo-spirit1/contiki-conf.h @@ -0,0 +1,154 @@ +/** +****************************************************************************** +* @file contiki-conf.h +* @author System LAB +* @version V1.0.0 +* @date 17-May-2015 +* @brief Contiki configuration parameters +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + +#ifndef __CONTIKI_CONF_H__ +#define __CONTIKI_CONF_H__ + +#include "platform-conf.h" + +#define SLIP_BRIDGE_CONF_NO_PUTCHAR 1 + +#define NETSTACK_CONF_RDC_CHANNEL_CHECK_RATE 8 +#define NULLRDC_CONF_802154_AUTOACK 0 +#define NETSTACK_CONF_FRAMER framer_802154 +#define NETSTACK_CONF_NETWORK sicslowpan_driver + +#undef NETSTACK_CONF_RDC +#define NETSTACK_CONF_RDC nullrdc_driver +#define NETSTACK_RDC_HEADER_LEN 0 + +#undef NETSTACK_CONF_MAC +#define NETSTACK_CONF_MAC csma_driver +#define NETSTACK_MAC_HEADER_LEN 0 + +#define SICSLOWPAN_CONF_MAC_MAX_PAYLOAD \ + (NETSTACK_RADIO_MAX_PAYLOAD_LEN - NETSTACK_MAC_HEADER_LEN - \ + NETSTACK_RDC_HEADER_LEN ) + +#define RIMESTATS_CONF_ENABLED 0 +#define RIMESTATS_CONF_ON 0 + + +/* Network setup for IPv6 */ + + +#define CXMAC_CONF_ANNOUNCEMENTS 0 + + +/* A trick to resolve a compilation error with IAR. */ +#ifdef __ICCARM__ +#define UIP_CONF_DS6_AADDR_NBU 1 +#endif + +/* radio driver blocks until ACK is received */ +#define NULLRDC_CONF_ACK_WAIT_TIME (0) +#define CONTIKIMAC_CONF_BROADCAST_RATE_LIMIT 0 +#define IEEE802154_CONF_PANID 0xABCD + +#define AODV_COMPLIANCE + +#define WITH_ASCII 1 + +#define PROCESS_CONF_NUMEVENTS 8 +#define PROCESS_CONF_STATS 1 +/*#define PROCESS_CONF_FASTPOLL 4*/ + + +#define LINKADDR_CONF_SIZE 8 + +#define UIP_CONF_LL_802154 1 +#define UIP_CONF_LLH_LEN 0 + +#define UIP_CONF_ROUTER 1 + +/* configure number of neighbors and routes */ +#ifndef UIP_CONF_DS6_ROUTE_NBU +#define UIP_CONF_DS6_ROUTE_NBU 30 +#endif /* UIP_CONF_DS6_ROUTE_NBU */ + +#define UIP_CONF_ND6_SEND_RA 0 +#define UIP_CONF_ND6_REACHABLE_TIME 600000 //90000// 600000 +#define UIP_CONF_ND6_RETRANS_TIMER 10000 + + +#define UIP_CONF_IPV6 1 +#ifndef UIP_CONF_IPV6_QUEUE_PKT +#define UIP_CONF_IPV6_QUEUE_PKT 0 +#endif /* UIP_CONF_IPV6_QUEUE_PKT */ +#define UIP_CONF_IP_FORWARD 0 +#ifndef UIP_CONF_BUFFER_SIZE +#define UIP_CONF_BUFFER_SIZE 280 +//#define UIP_CONF_BUFFER_SIZE 600 +#endif + +#define SICSLOWPAN_CONF_MAXAGE 4 +#define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS 2 + + +#ifndef SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS +#define SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS 5 +#endif /* SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS */ + +#define UIP_CONF_ICMP_DEST_UNREACH 1 + +#define UIP_CONF_DHCP_LIGHT +#define UIP_CONF_LLH_LEN 0 +#ifndef UIP_CONF_RECEIVE_WINDOW +#define UIP_CONF_RECEIVE_WINDOW 150 +#endif +#ifndef UIP_CONF_TCP_MSS +#define UIP_CONF_TCP_MSS UIP_CONF_RECEIVE_WINDOW +#endif +#define UIP_CONF_MAX_CONNECTIONS 4 +#define UIP_CONF_MAX_LISTENPORTS 8 +#define UIP_CONF_UDP_CONNS 12 +#define UIP_CONF_FWCACHE_SIZE 30 +#define UIP_CONF_BROADCAST 1 +#define UIP_ARCH_IPCHKSUM 0 +#define UIP_CONF_UDP 1 +#define UIP_CONF_UDP_CHECKSUMS 1 +#define UIP_CONF_TCP 1 + +/* include the project config */ +/* PROJECT_CONF_H might be defined in the project Makefile */ +#ifdef PROJECT_CONF_H +#include PROJECT_CONF_H +#endif /* PROJECT_CONF_H */ + + + +#endif /* CONTIKI_CONF_H */ diff --git a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c new file mode 100644 index 000000000..8e25ba9a7 --- /dev/null +++ b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c @@ -0,0 +1,195 @@ +/** +****************************************************************************** +* @file contiki-spirit1-main.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Contiki main file for SPIRIT1 platform +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include "stm32cube_hal_init.h" +#include "contiki.h" +#include "contiki-net.h" +#include "sys/autostart.h" +#include "dev/leds.h" +#include "dev/serial-line.h" +#include "dev/slip.h" +#include "dev/watchdog.h" +#include "dev/xmem.h" +#include "lib/random.h" +#include "net/netstack.h" +#include "net/ip/uip.h" +#include "net/mac/frame802154.h" +#include "net/rime/rime.h" +#include "stm32l1xx.h" +#include "SPIRIT_Config.h" +#include "SPIRIT_Management.h" +#include "spirit1.h" +#include "spirit1-arch.h" +#include "node-id.h" +#include "hw-config.h" +#include "stdbool.h" +#include "dev/button-sensor.h" + +#if NETSTACK_CONF_WITH_IPV6 +#include "net/ipv6/uip-ds6.h" +#endif /*NETSTACK_CONF_WITH_IPV6*/ + +#if COMPILE_SENSORS +extern const struct sensors_sensor temperature_sensor; +extern const struct sensors_sensor humidity_sensor; +extern const struct sensors_sensor pressure_sensor; +extern const struct sensors_sensor magneto_sensor; +extern const struct sensors_sensor acceleration_sensor; +extern const struct sensors_sensor gyroscope_sensor; +SENSORS(&button_sensor, + &temperature_sensor, + &humidity_sensor, + &pressure_sensor, + &magneto_sensor, + &acceleration_sensor, + &gyroscope_sensor); +#else +SENSORS(&button_sensor); +#endif + +extern unsigned char node_mac[8]; +#ifdef __GNUC__ +/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf +set to 'Yes') calls __io_putchar() */ +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + + +#if NETSTACK_CONF_WITH_IPV6 +PROCINIT(&etimer_process, &tcpip_process); +#else +PROCINIT(&etimer_process); +#warning "No TCP/IP process!" +#endif + +#define BUSYWAIT_UNTIL(cond, max_time) \ +do { \ + rtimer_clock_t t0; \ + t0 = RTIMER_NOW(); \ + while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ +} while(0) + + +/*---------------------------------------------------------------------------*/ +static void set_rime_addr(void); +int Stack_6LoWPAN_Init(int argc, char *argv[]); + +/*---------------------------------------------------------------------------*/ +#if 0 +static void panic_main(void) +{ + volatile uint16_t k; + while(1) { + leds_toggle(LEDS_ALL); + for(k = 0; k < 0xffff/8; k += 1) { } + } +} +#endif +/*---------------------------------------------------------------------------*/ +int main (int argc, char *argv[]) +{ + + stm32cube_hal_init(); + + /* init LEDs */ + leds_init(); + + /* Initialize Contiki and our processes. */ + clock_init(); + ctimer_init(); + rtimer_init(); + watchdog_init(); + process_init(); + process_start(&etimer_process, NULL); + + + /* Restore node id if such has been stored in external mem */ + node_id_restore(); /* also configures node_mac[] */ + + set_rime_addr(); + random_init(node_id); + + netstack_init(); + spirit_radio_driver.on(); + + energest_init(); + + +#if NETSTACK_CONF_WITH_IPV6 + memcpy(&uip_lladdr.addr, node_mac, sizeof(uip_lladdr.addr)); + + queuebuf_init(); + process_start(&tcpip_process, NULL); + + uip_ipaddr_t ipaddr; + uip_ip6addr(&ipaddr, 0xfc00, 0, 0, 0, 0, 0, 0, 0); + uip_ds6_set_addr_iid(&ipaddr, &uip_lladdr); + uip_ds6_addr_add(&ipaddr, 0, ADDR_AUTOCONF); +#endif /* NETSTACK_CONF_WITH_IPV6*/ + + process_start(&sensors_process, NULL); + + autostart_start(autostart_processes); + + watchdog_start(); + + while(1) + { + + int r = 0; + do { + r = process_run(); + } while(r > 0); + + } +} + + +/*---------------------------------------------------------------------------*/ +static void set_rime_addr(void) +{ + linkaddr_t addr; + + memset(&addr, 0, sizeof(linkaddr_t)); + memcpy(addr.u8, node_mac, sizeof(addr.u8)); + + linkaddr_set_node_addr(&addr); +} diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c new file mode 100644 index 000000000..20eb12dec --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c @@ -0,0 +1,131 @@ +/** +****************************************************************************** +* @file acceleration-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable aceleration sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#if COMPILE_SENSORS +#include "lib/sensors.h" +#include "acceleration-sensor.h" + +#include "x_nucleo_iks01a1_imu_6axes.h" + +static int _active = 1; + +static void init(void) +{ + /*Acceleration and Gyroscope sensors share the same hw*/ + if (!BSP_IMU_6AXES_isInitialized()) + { + if (IMU_6AXES_OK == BSP_IMU_6AXES_Init()) + { + _active = 1; + } + } +} + +static void activate(void) +{ + _active = 1; +} + +static void deactivate(void) +{ + _active = 0; +} + + +static int active(void) +{ + return _active; +} + + +static int value(int type) +{ + int32_t RetVal; + volatile AxesRaw_TypeDef AxesRaw_Data; + + BSP_IMU_6AXES_X_GetAxesRaw(&AxesRaw_Data); + + switch (type) + { + case X_AXIS: + RetVal = AxesRaw_Data.AXIS_X ; + break; + case Y_AXIS: + RetVal = AxesRaw_Data.AXIS_Y ; + break; + case Z_AXIS: + RetVal = AxesRaw_Data.AXIS_Z ; + break; + default: + break; + } + + return (RetVal); +} + +static int configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) + activate(); + else + deactivate(); + return 1; + } + + return 0; +} + +static int status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} + +SENSORS_SENSOR(acceleration_sensor, ACCELERATION_SENSOR, value, configure, status); + +#endif /*COMPILE_SENSORS*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h new file mode 100644 index 000000000..b61592241 --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h @@ -0,0 +1,49 @@ +/** +****************************************************************************** +* @file acceleration-sensor.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable aceleration sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#ifndef ACCELERATION_SENSOR_H_ +#define ACCELERATION_SENSOR_H_ + +#include "lib/sensors.h" +#include "sensor-common.h" + +extern const struct sensors_sensor acceleration_sensor; + +#define ACCELERATION_SENSOR "Acceleration" + +#endif /* ACCELERATION_SENSOR_H_ */ + diff --git a/platform/stm32nucleo-spirit1/dev/button-sensor.c b/platform/stm32nucleo-spirit1/dev/button-sensor.c new file mode 100644 index 000000000..ab2ca12ec --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/button-sensor.c @@ -0,0 +1,105 @@ +/** +****************************************************************************** +* @file button-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable button sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#include "dev/button-sensor.h" +#include "lib/sensors.h" + +#include "stm32l1xx_nucleo.h" + +static int _active = 0 ; + +static void init(void) +{ + /* See spirit1_appli.c for the Callback: it triggers the relevant + * sensors_changed event + */ + BSP_PB_Init(BUTTON_USER, BUTTON_MODE_EXTI); +} + +static void activate(void) +{ + _active = 1; +} + +static void deactivate(void) +{ + _active = 0; +} + +static int active(void) +{ + return active; +} + +static int value(int type) +{ + return BSP_PB_GetState(BUTTON_USER); +} + +static int configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) + activate(); + else + deactivate(); + return 1; + } + + return 0; +} + +static int status(int type) +{ + switch(type) { + + case SENSORS_READY: + return active(); + } + + return 0; +} + + +SENSORS_SENSOR(button_sensor, BUTTON_SENSOR, value, configure, status); + +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c new file mode 100644 index 000000000..f7140652b --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c @@ -0,0 +1,131 @@ +/** +****************************************************************************** +* @file gyroscope-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable aceleration sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#if COMPILE_SENSORS +#include "lib/sensors.h" +#include "gyroscope-sensor.h" + +#include "x_nucleo_iks01a1_imu_6axes.h" + +static int _active = 1; + +static void init(void) +{ + /*Acceleration and Gyroscope sensors share the same hw*/ + if (!BSP_IMU_6AXES_isInitialized()) + { + if (IMU_6AXES_OK == BSP_IMU_6AXES_Init()) + { + _active = 1; + } + } +} + +static void activate(void) +{ + _active = 1; +} + +static void deactivate(void) +{ + _active = 0; +} + + +static int active(void) +{ + return _active; +} + + +static int value(int type) +{ + int32_t RetVal; + volatile AxesRaw_TypeDef AxesRaw_Data; + + BSP_IMU_6AXES_G_GetAxesRaw(&AxesRaw_Data); + + switch (type) + { + case X_AXIS: + RetVal = AxesRaw_Data.AXIS_X ; + break; + case Y_AXIS: + RetVal = AxesRaw_Data.AXIS_Y ; + break; + case Z_AXIS: + RetVal = AxesRaw_Data.AXIS_Z ; + break; + default: + break; + } + + return (RetVal); +} + +static int configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) + activate(); + else + deactivate(); + return 1; + } + + return 0; +} + +static int status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} + +SENSORS_SENSOR(gyroscope_sensor, GYROSCOPE_SENSOR, value, configure, status); + +#endif /*COMPILE_SENSORS*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h new file mode 100644 index 000000000..083525ef8 --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h @@ -0,0 +1,49 @@ +/** +****************************************************************************** +* @file gyroscope-sensor.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable aceleration sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#ifndef GYROSCOPE_SENSOR_H_ +#define GYROSCOPE_SENSOR_H_ + +#include "lib/sensors.h" +#include "sensor-common.h" + +extern const struct sensors_sensor gyroscope_sensor; + +#define GYROSCOPE_SENSOR "Gyroscope" + +#endif /* GYROSCOPE_SENSOR_H_ */ + diff --git a/platform/stm32nucleo-spirit1/dev/humidity-sensor.c b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c new file mode 100644 index 000000000..ec3772677 --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c @@ -0,0 +1,117 @@ +/** +****************************************************************************** +* @file humidity-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable humidity sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + + +#if COMPILE_SENSORS +#include "lib/sensors.h" +#include "humidity-sensor.h" + +#include "x_nucleo_iks01a1_hum_temp.h" + +static int _active = 1; + +static void init(void) +{ + /*Temperature and Humity sensors share the same hw*/ + if (!BSP_HUM_TEMP_isInitialized()) + { + BSP_HUM_TEMP_Init(); + _active = 1; + } +} + +static void activate(void) +{ + _active = 1; +} + +static void deactivate(void) +{ + _active = 0; +} + + +static int active(void) +{ + return _active; +} + + +static int value(int type) +{ + uint32_t humidity; + volatile float HUMIDITY_Value; + + BSP_HUM_TEMP_GetHumidity((float *)&HUMIDITY_Value); + + humidity = HUMIDITY_Value * 10; + return(humidity); +} + + +static int configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) + activate(); + else + deactivate(); + return 1; + } + + return 0; +} + +static int status(int type) +{ + switch(type) + { + case SENSORS_READY: + return active(); + } + + return 0; +} + +SENSORS_SENSOR(humidity_sensor, HUMIDITY_SENSOR, value, configure, status); +#endif /*COMPILE_SENSORS*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/humidity-sensor.h b/platform/stm32nucleo-spirit1/dev/humidity-sensor.h new file mode 100644 index 000000000..fc18349bb --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/humidity-sensor.h @@ -0,0 +1,48 @@ +/** +****************************************************************************** +* @file humidity-sensor.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable humidity sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#ifndef HUMIDITY_SENSOR_H_ +#define HUMIDITY_SENSOR_H_ + +#include "lib/sensors.h" + +extern const struct sensors_sensor humidity_sensor; + +#define HUMIDITY_SENSOR "Humidity" + +#endif /* HUMIDITY_SENSOR_H_ */ + diff --git a/platform/stm32nucleo-spirit1/dev/leds-arch.c b/platform/stm32nucleo-spirit1/dev/leds-arch.c new file mode 100644 index 000000000..52e2a9cfb --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/leds-arch.c @@ -0,0 +1,111 @@ +/** +****************************************************************************** +* @file leds-arch.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Contiki LEDs API binding for the boards in use: Nucleo and SPIRIT1 +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include "contiki-conf.h" +#include "dev/leds.h" +#include "stm32l1xx_nucleo.h" + +#ifndef COMPILE_SENSORS +#include "radio_shield_config.h" +extern GPIO_TypeDef* aLED_GPIO_PORT[]; +extern const uint16_t aLED_GPIO_PIN[]; +#endif /*COMPILE_SENSORS*/ + +extern GPIO_TypeDef* GPIO_PORT[]; +extern const uint16_t GPIO_PIN[]; + + +/*---------------------------------------------------------------------------*/ +void leds_arch_init(void) +{ + /* We have two led, one on the Nucleo (GREEN) ....*/ + BSP_LED_Init(LED2); + BSP_LED_Off(LED2); + +#ifndef COMPILE_SENSORS + /* ... and one the SPIRIT1 (RED) ....*/ + RadioShieldLedInit(RADIO_SHIELD_LED); + RadioShieldLedOff(RADIO_SHIELD_LED); +#endif /*COMPILE_SENSORS*/ +} + +/*---------------------------------------------------------------------------*/ +unsigned char leds_arch_get(void) +{ + unsigned char ret = 0 ; + if (HAL_GPIO_ReadPin(GPIO_PORT[LED2],GPIO_PIN[LED2])) + { + ret |= LEDS_GREEN; + } + +#ifndef COMPILE_SENSORS + if (HAL_GPIO_ReadPin(aLED_GPIO_PORT[RADIO_SHIELD_LED], + aLED_GPIO_PIN[RADIO_SHIELD_LED]) + ) + { + ret |= LEDS_RED; + } +#endif /*COMPILE_SENSORS*/ + + return ret; +} + +/*---------------------------------------------------------------------------*/ +void leds_arch_set(unsigned char leds) +{ + if (leds & LEDS_GREEN) + { + BSP_LED_On(LED2); + } + else + { + BSP_LED_Off(LED2); + } + +#ifndef COMPILE_SENSORS + if (leds & LEDS_RED) + { + RadioShieldLedOn(RADIO_SHIELD_LED); + } + else + { + RadioShieldLedOff(RADIO_SHIELD_LED); + } +#endif /*COMPILE_SENSORS*/ +} +/*---------------------------------------------------------------------------*/ + diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c new file mode 100644 index 000000000..b2f23f67c --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c @@ -0,0 +1,125 @@ +/** +****************************************************************************** +* @file magneto-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable magneto sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#if COMPILE_SENSORS +#include "lib/sensors.h" +#include "magneto-sensor.h" + +#include "x_nucleo_iks01a1_magneto.h" + +static int _active = 1; + +static void init(void) +{ + BSP_MAGNETO_Init(); + _active = 1; +} + +static void activate(void) +{ + _active = 1; +} + +static void deactivate(void) +{ + _active = 0; +} + + +static int active(void) +{ + return _active; +} + + +static int value(int type) +{ + int32_t RetVal; + volatile AxesRaw_TypeDef AxesRaw_Data; + + BSP_MAGNETO_M_GetAxesRaw(&AxesRaw_Data); + + switch (type) + { + case X_AXIS: + RetVal = AxesRaw_Data.AXIS_X ; + break; + case Y_AXIS: + RetVal = AxesRaw_Data.AXIS_Y ; + break; + case Z_AXIS: + RetVal = AxesRaw_Data.AXIS_Z ; + break; + default: + break; + } + + return(RetVal); +} + +static int configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) + activate(); + else + deactivate(); + return 1; + } + + return 0; +} + +static int status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} + +SENSORS_SENSOR(magneto_sensor, MAGNETO_SENSOR, value, configure, status); + +#endif /*COMPILE_SENSORS*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.h b/platform/stm32nucleo-spirit1/dev/magneto-sensor.h new file mode 100644 index 000000000..adaeef7ad --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.h @@ -0,0 +1,49 @@ +/** +****************************************************************************** +* @file magneto-sensor.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable magneto sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#ifndef MAGNETO_SENSOR_H_ +#define MAGNETO_SENSOR_H_ + +#include "lib/sensors.h" +#include "sensor-common.h" + +extern const struct sensors_sensor magneto_sensor; + +#define MAGNETO_SENSOR "Magneto" + +#endif /* MAGNETO_SENSOR_H_ */ + diff --git a/platform/stm32nucleo-spirit1/dev/pressure-sensor.c b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c new file mode 100644 index 000000000..c9535ab59 --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c @@ -0,0 +1,112 @@ +/** +****************************************************************************** +* @file pressure-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable pressure sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#if COMPILE_SENSORS +#include "lib/sensors.h" +#include "pressure-sensor.h" + +#include "x_nucleo_iks01a1_pressure.h" + +static int _active = 1; + +static void init(void) +{ + BSP_PRESSURE_Init(); + _active =1; +} + + +static void activate(void) +{ + _active = 1; +} + +static void deactivate(void) +{ + _active = 0; +} + + +static int active(void) +{ + return _active; +} + + +static int value(int type) +{ + uint16_t pressure; + volatile float PRESSURE_Value; + + BSP_PRESSURE_GetPressure((float *)&PRESSURE_Value); + pressure = PRESSURE_Value * 10; + + return(pressure); +} + +static int configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) + activate(); + else + deactivate(); + return 1; + } + + return 0; +} + +static int status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} + +SENSORS_SENSOR(pressure_sensor, PRESSURE_SENSOR, value, configure, status); + +#endif /*COMPILE_SENSORS*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/pressure-sensor.h b/platform/stm32nucleo-spirit1/dev/pressure-sensor.h new file mode 100644 index 000000000..d68ce27a5 --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/pressure-sensor.h @@ -0,0 +1,48 @@ +/** +****************************************************************************** +* @file pressure-sensor.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable pressure sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#ifndef PRESSURE_SENSOR_H_ +#define PRESSURE_SENSOR_H_ + +#include "lib/sensors.h" + +extern const struct sensors_sensor pressure_sensor; + +#define PRESSURE_SENSOR "Pressure" + +#endif /* PRESSURE_SENSOR_H_ */ + diff --git a/platform/stm32nucleo-spirit1/dev/sensor-common.h b/platform/stm32nucleo-spirit1/dev/sensor-common.h new file mode 100644 index 000000000..8748dfaeb --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/sensor-common.h @@ -0,0 +1,45 @@ +/** +****************************************************************************** +* @file sensor-common.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Common defines for sensors data structurers +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#ifndef SENSOR_COMMON_H_ +#define SENSOR_COMMON_H_ + +#define X_AXIS 0x00 +#define Y_AXIS 0x01 +#define Z_AXIS 0x02 + +#endif /*SENSOR_COMMON_H_*/ diff --git a/platform/stm32nucleo-spirit1/dev/temperature-sensor.c b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c new file mode 100644 index 000000000..17e187934 --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c @@ -0,0 +1,112 @@ +/** +****************************************************************************** +* @file temperature-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable temperature sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#if COMPILE_SENSORS +#include "lib/sensors.h" +#include "temperature-sensor.h" + +#include "x_nucleo_iks01a1_hum_temp.h" + +static int _active = 0; + +static void init(void) +{ + /*Temperature and Humity sensors share the same hw*/ + if (!BSP_HUM_TEMP_isInitialized()) + { + BSP_HUM_TEMP_Init(); + _active=1; + } +} + +static void activate(void) +{ + _active = 1; +} + +static void deactivate(void) +{ + _active = 0; +} + + +static int active(void) +{ + return _active; +} + +static int value(int type) +{ + int32_t temperature; + volatile float TEMPERATURE_Value; + + BSP_HUM_TEMP_GetTemperature((float *)&TEMPERATURE_Value); + temperature = TEMPERATURE_Value * 10; + return(temperature); +} + +static int configure(int type, int value) +{ + switch(type){ + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) + activate(); + else + deactivate(); + return 1; + } + + return 0; +} + +static int status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} + +SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, value, configure, status); +#endif /*COMPILE_SENSORS*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/temperature-sensor.h b/platform/stm32nucleo-spirit1/dev/temperature-sensor.h new file mode 100644 index 000000000..c54fb47ef --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/temperature-sensor.h @@ -0,0 +1,48 @@ +/** +****************************************************************************** +* @file temperature-sensor.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Enable temperature sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#ifndef TEMPERATURE_SENSOR_H_ +#define TEMPERATURE_SENSOR_H_ + +#include "lib/sensors.h" + +extern const struct sensors_sensor temperature_sensor; + +#define TEMPERATURE_SENSOR "Temperature" + +#endif /* TEMPERATURE_SENSOR_H_ */ + diff --git a/platform/stm32nucleo-spirit1/dev/uart1.h b/platform/stm32nucleo-spirit1/dev/uart1.h new file mode 100644 index 000000000..7867bc5ec --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/uart1.h @@ -0,0 +1,47 @@ +/** +****************************************************************************** +* @file uart1.h +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Include file for BAUD2UBR macro +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + + +#ifndef UART1_H_ +#define UART1_H_ + +#define BAUD2UBR(baud) baud + + +#endif /* UART1_H_ */ + diff --git a/platform/stm32nucleo-spirit1/drivers/Common/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/Common/Release_Notes.html new file mode 100644 index 000000000..e3b4d49a2 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/Common/Release_Notes.html @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + Release Notes for BSP Components Common Drivers + + + + + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
+

Back to Release page

+
+ +

Release +Notes for BSP Components Common  Drivers

+ +

Copyright +2014 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+

V1.2.1 / 02-December-2014

+

Main +Changes

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
  • gyro.h: change “__GIRO_H” by “__GYRO_H” to fix compilation issue under Mac OS
    • +
+ +

V1.2.0 / 18-June-2014

Main +Changes

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
  • EPD (E Paper Display)  driver function prototype added (epd.h file)
    +

V1.1.0 / 21-March-2014

Main +Changes

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
  • Temperature Sensor driver function prototype added

V1.0.0 / 18-February-2014

+ + + + + + + + + + + + + + + + +

Main +Changes

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
  • First official release with  Accelerometer, Audio, Camera, Gyroscope, IO, LCD and Touch Screen drivers function prototypes

License

+
+Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met:
+ +
  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions +in binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
    +     +
+        from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +
+

+ + +
+
+

For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ + \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/Common/hum_temp.h b/platform/stm32nucleo-spirit1/drivers/Common/hum_temp.h new file mode 100644 index 000000000..460708ef6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/Common/hum_temp.h @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file hum_temp.h + * @author MEMS Application Team + * @version V1.2.0 + * @date 28-January-2015 + * @brief This header file contains the functions prototypes for the + * humidity and temperature driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HUM_TEMP_H +#define __HUM_TEMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup HUM_TEMP + * @{ + */ + +/** @defgroup HUM_TEMP_Exported_Types + * @{ + */ + +/** + * @brief Humidity and temperature init structure definition + */ +typedef struct +{ + uint8_t Power_Mode; /* Power-down/Sleep/Normal Mode */ + uint8_t Data_Update_Mode; /* continuous update/output registers not updated until MSB and LSB reading*/ + uint8_t Reboot_Mode; /* Normal Mode/Reboot memory content */ + uint8_t Humidity_Resolutin; /* Humidity Resolution */ + uint8_t Temperature_Resolution; /* Temperature Resolution */ + uint8_t OutputDataRate; /* One-shot / 1Hz / 7 Hz / 12.5 Hz */ +} HUM_TEMP_InitTypeDef; + +/** + * @brief Humidity and temperature status enumerator definition + */ +typedef enum +{ + HUM_TEMP_OK = 0, + HUM_TEMP_ERROR = 1, + HUM_TEMP_TIMEOUT = 2, + HUM_TEMP_NOT_IMPLEMENTED = 3 +} HUM_TEMP_StatusTypeDef; + +/** + * @brief Humidity and temperature component id enumerator definition + */ +typedef enum +{ + HUM_TEMP_NONE_COMPONENT = 0, + HUM_TEMP_HTS221_COMPONENT = 1 +} HUM_TEMP_ComponentTypeDef; + +/** + * @brief Humidity and temperature driver extended structure definition + */ +typedef struct +{ + HUM_TEMP_ComponentTypeDef + id; /* This id must be unique for each component belonging to this class that wants to extend common class */ + void *pData; /* This pointer is specific for each component */ +} HUM_TEMP_DrvExtTypeDef; + +/** + * @brief Humidity and temperature driver structure definition + */ +typedef struct +{ + HUM_TEMP_StatusTypeDef (*Init)(HUM_TEMP_InitTypeDef *); + HUM_TEMP_StatusTypeDef (*PowerOFF)(void); + HUM_TEMP_StatusTypeDef (*ReadID)(uint8_t *); + HUM_TEMP_StatusTypeDef (*Reset)(void); + void (*ConfigIT)(uint16_t); + void (*EnableIT)(uint8_t); + void (*DisableIT)(uint8_t); + uint8_t (*ITStatus)(uint16_t, uint16_t); + void (*ClearIT)(uint16_t, uint16_t); + HUM_TEMP_StatusTypeDef (*GetHumidity)(float *); + HUM_TEMP_StatusTypeDef (*GetTemperature)(float *); + HUM_TEMP_DrvExtTypeDef *extData; +} HUM_TEMP_DrvTypeDef; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HUM_TEMP_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/Common/imu_6axes.h b/platform/stm32nucleo-spirit1/drivers/Common/imu_6axes.h new file mode 100644 index 000000000..44099539b --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/Common/imu_6axes.h @@ -0,0 +1,161 @@ +/** + ****************************************************************************** + * @file imu_6axes.h + * @author MEMS Application Team + * @version V1.2.0 + * @date 28-January-2015 + * @brief This header file contains the functions prototypes for the + * accelerometer and gyroscope driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __IMU_6AXES_H +#define __IMU_6AXES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup IMU_6AXES + * @{ + */ + +/** @defgroup IMU_6AXES_Exported_Types + * @{ + */ + +/** + * @brief IMU_6AXES init structure definition + */ +typedef struct +{ + float G_OutputDataRate; + float G_FullScale; + uint8_t G_X_Axis; + uint8_t G_Y_Axis; + uint8_t G_Z_Axis; + float X_OutputDataRate; + float X_FullScale; + uint8_t X_X_Axis; + uint8_t X_Y_Axis; + uint8_t X_Z_Axis; +} IMU_6AXES_InitTypeDef; + +/** + * @brief IMU_6AXES status enumerator definition + */ +typedef enum +{ + IMU_6AXES_OK = 0, + IMU_6AXES_ERROR = 1, + IMU_6AXES_TIMEOUT = 2, + IMU_6AXES_NOT_IMPLEMENTED = 3 +} IMU_6AXES_StatusTypeDef; + +/** + * @brief IMU_6AXES component id enumerator definition + */ +typedef enum +{ + IMU_6AXES_NONE_COMPONENT = 0, + IMU_6AXES_LSM6DS0_COMPONENT = 1, + IMU_6AXES_LSM6DS3_DIL24_COMPONENT = 2 +} IMU_6AXES_ComponentTypeDef; + +/** + * @brief IMU_6AXES driver extended structure definition + */ +typedef struct +{ + IMU_6AXES_ComponentTypeDef + id; /* This id must be unique for each component belonging to this class that wants to extend common class */ + void *pData; /* This pointer is specific for each component */ +} IMU_6AXES_DrvExtTypeDef; + +/** + * @brief IMU_6AXES driver structure definition + */ +typedef struct +{ + IMU_6AXES_StatusTypeDef (*Init)(IMU_6AXES_InitTypeDef *); + IMU_6AXES_StatusTypeDef (*Read_XG_ID)(uint8_t *); + IMU_6AXES_StatusTypeDef (*Get_X_Axes)(int32_t *); + IMU_6AXES_StatusTypeDef (*Get_X_AxesRaw)(int16_t *); + IMU_6AXES_StatusTypeDef (*Get_G_Axes)(int32_t *); + IMU_6AXES_StatusTypeDef (*Get_G_AxesRaw)(int16_t *); + IMU_6AXES_StatusTypeDef (*Get_X_ODR) (float *); + IMU_6AXES_StatusTypeDef (*Set_X_ODR) (float); + IMU_6AXES_StatusTypeDef (*Get_X_Sensitivity) (float *); + IMU_6AXES_StatusTypeDef (*Get_X_FS) (float *); + IMU_6AXES_StatusTypeDef (*Set_X_FS) (float); + IMU_6AXES_StatusTypeDef (*Get_G_ODR) (float *); + IMU_6AXES_StatusTypeDef (*Set_G_ODR) (float); + IMU_6AXES_StatusTypeDef (*Get_G_Sensitivity) (float *); + IMU_6AXES_StatusTypeDef (*Get_G_FS) (float *); + IMU_6AXES_StatusTypeDef (*Set_G_FS) (float); + IMU_6AXES_DrvExtTypeDef *extData; +} IMU_6AXES_DrvTypeDef; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IMU_6AXES_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/Common/magneto.h b/platform/stm32nucleo-spirit1/drivers/Common/magneto.h new file mode 100644 index 000000000..b22da5af7 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/Common/magneto.h @@ -0,0 +1,142 @@ +/** + ****************************************************************************** + * @file magneto.h + * @author MEMS Application Team + * @version V1.2.0 + * @date 28-January-2015 + * @brief This header file contains the functions prototypes for the + * magneto driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAGNETO_H +#define __MAGNETO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup MAGNETO + * @{ + */ + +/** @defgroup MAGNETO_Exported_Types + * @{ + */ + +/** +* @brief MAGNETO init structure definition +*/ +typedef struct +{ + uint8_t M_OutputDataRate; + uint8_t M_OperatingMode; + uint8_t M_FullScale; + uint8_t M_XYOperativeMode; +} MAGNETO_InitTypeDef; + +/** +* @brief MAGNETO status enumerator definition +*/ +typedef enum +{ + MAGNETO_OK = 0, + MAGNETO_ERROR = 1, + MAGNETO_TIMEOUT = 2, + MAGNETO_NOT_IMPLEMENTED = 3 +} MAGNETO_StatusTypeDef; + +/** + * @brief MAGNETO component id enumerator definition + */ +typedef enum +{ + MAGNETO_NONE_COMPONENT = 0, + MAGNETO_LIS3MDL_COMPONENT = 1 +} MAGNETO_ComponentTypeDef; + +/** + * @brief MAGNETO driver extended structure definition + */ +typedef struct +{ + MAGNETO_ComponentTypeDef + id; /* This id must be unique for each component belonging to this class that wants to extend common class */ + void *pData; /* This pointer is specific for each component */ +} MAGNETO_DrvExtTypeDef; + +/** +* @brief MAGNETO driver structure definition +*/ +typedef struct +{ + MAGNETO_StatusTypeDef (*Init)(MAGNETO_InitTypeDef *); + MAGNETO_StatusTypeDef (*Read_M_ID)(uint8_t *); + MAGNETO_StatusTypeDef (*Get_M_Axes)(int32_t *); + MAGNETO_StatusTypeDef (*Get_M_AxesRaw)(int16_t *); + MAGNETO_DrvExtTypeDef *extData; +} MAGNETO_DrvTypeDef; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAGNETO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/Common/pressure.h b/platform/stm32nucleo-spirit1/drivers/Common/pressure.h new file mode 100644 index 000000000..5bcd8e099 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/Common/pressure.h @@ -0,0 +1,153 @@ +/** + ****************************************************************************** + * @file pressure.h + * @author MEMS Application Team + * @version V1.2.0 + * @date 28-January-2015 + * @brief This header file contains the functions prototypes for the + * pressure driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PRESSURE_H +#define __PRESSURE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup PRESSURE + * @{ + */ + +/** @defgroup PRESSURE_Exported_Types + * @{ + */ + +/** + * @brief PRESSURE init structure definition + */ +typedef struct +{ + uint8_t OutputDataRate; + uint8_t PressureResolution; + uint8_t TemperatureResolution; + uint8_t DiffEnable; + uint8_t BlockDataUpdate; + uint8_t SPIMode; +} PRESSURE_InitTypeDef; + +/** + * @brief PRESSURE status enumerator definition + */ +typedef enum +{ + PRESSURE_OK = 0, + PRESSURE_ERROR = 1, + PRESSURE_TIMEOUT = 2, + PRESSURE_NOT_IMPLEMENTED = 3 +} PRESSURE_StatusTypeDef; + +/** + * @brief PRESSURE component id enumerator definition + */ +typedef enum +{ + PRESSURE_NONE_COMPONENT = 0, + PRESSURE_LPS25H_COMPONENT = 1, + PRESSURE_LPS25HB_DIL24_COMPONENT = 2 +} PRESSURE_ComponentTypeDef; + +/** + * @brief PRESSURE driver extended structure definition + */ +typedef struct +{ + PRESSURE_ComponentTypeDef + id; /* This id must be unique for each component belonging to this class that wants to extend common class */ + void *pData; /* This pointer is specific for each component */ +} PRESSURE_DrvExtTypeDef; + +/** + * @brief PRESSURE driver structure definition + */ +typedef struct +{ + PRESSURE_StatusTypeDef (*Init)(PRESSURE_InitTypeDef *); + PRESSURE_StatusTypeDef (*PowerOff)(void); + PRESSURE_StatusTypeDef (*ReadID)(uint8_t *); + PRESSURE_StatusTypeDef (*Reset)(void); + void (*ConfigIT)(uint16_t); + void (*EnableIT)(uint8_t); + void (*DisableIT)(uint8_t); + uint8_t (*ITStatus)(uint16_t, uint16_t); + void (*ClearIT)(uint16_t, uint16_t); + PRESSURE_StatusTypeDef (*GetPressure)(float *); + PRESSURE_StatusTypeDef (*GetTemperature)(float *); + void (*SlaveAddrRemap)(uint8_t); + PRESSURE_DrvExtTypeDef *extData; +} PRESSURE_DrvTypeDef; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PRESSURE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/Release_Notes.html new file mode 100644 index 000000000..f2cac615b --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/Release_Notes.html @@ -0,0 +1,191 @@ + + + + + +Release Notes for STM32 BlueEnergy Library + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
+

Back to Release page

+
+

Release Notes for HTS221 component

+

Copyright +2015 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+ + +

V1.2.0 +/ 11-February-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add extended features support for the Component +
    • +
+ +

V1.1.0 +/ 12-December-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • Add error control in the Component API +
    • +
+ +

V1.0.0 +/ 10-September-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • First +official release
    • +
+ + +

License
+

+ + +Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

+ + +
+ http://www.st.com/software_license_agreement_liberty_v2


+ +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + + + + +

+ +
+
+

For +complete documentation on STM32 STM BlueNRG +visit www.st.com/BlueNRG

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.c b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.c new file mode 100644 index 000000000..9d084c066 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.c @@ -0,0 +1,503 @@ +/** + ****************************************************************************** + * @file hts221.c + * @author MEMS Application Team + * @version V1.2.0 + * @date 11-February-2015 + * @brief This file provides a set of functions needed to manage the hts221. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "hts221.h" +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup HTS221 + * @{ + */ + +static HUM_TEMP_StatusTypeDef HTS221_Init(HUM_TEMP_InitTypeDef *HTS221_Init); +static HUM_TEMP_StatusTypeDef HTS221_Power_OFF(void); +static HUM_TEMP_StatusTypeDef HTS221_ReadID(uint8_t *ht_id); +static HUM_TEMP_StatusTypeDef HTS221_RebootCmd(void); +static HUM_TEMP_StatusTypeDef HTS221_GetHumidity(float* pfData); +static HUM_TEMP_StatusTypeDef HTS221_GetTemperature(float* pfData); + +/** @defgroup HTS221_Private_Variables HTS221_Private_Variables + * @{ + */ + +HUM_TEMP_DrvTypeDef Hts221Drv = +{ + HTS221_Init, + HTS221_Power_OFF, + HTS221_ReadID, + HTS221_RebootCmd, + 0, + 0, + 0, + 0, + 0, + HTS221_GetHumidity, + HTS221_GetTemperature, + NULL +}; + +/* ------------------------------------------------------- */ +/* Here you should declare the variable that implements */ +/* the internal struct of extended features of HTS221. */ +/* Then you must update the NULL pointer in the variable */ +/* of the extended features below. */ +/* See the example of LSM6DS3 in lsm6ds3.c */ +/* ------------------------------------------------------- */ + +HUM_TEMP_DrvExtTypeDef Hts221Drv_ext = +{ + HUM_TEMP_HTS221_COMPONENT, /* unique ID for HTS221 in the humidity and temperature driver class */ + NULL /* pointer to internal struct of extended features of HTS221 */ +}; + + +/* Temperature in degree for calibration */ +float T0_degC, T1_degC; + +/* Output temperature value for calibration */ +int16_t T0_out, T1_out; + + +/* Humidity for calibration */ +float H0_rh, H1_rh; + +/* Output Humidity value for calibration */ +int16_t H0_T0_out, H1_T0_out; + +/** + * @} + */ + +static HUM_TEMP_StatusTypeDef HTS221_Power_On(void); +static HUM_TEMP_StatusTypeDef HTS221_Calibration(void); + +/** @defgroup HTS221_Private_Functions HTS221_Private_Functions + * @{ + */ + +/** + * @brief HTS221 Calibration procedure + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_Calibration(void) +{ + /* Temperature Calibration */ + /* Temperature in degree for calibration ( "/8" to obtain float) */ + uint16_t T0_degC_x8_L, T0_degC_x8_H, T1_degC_x8_L, T1_degC_x8_H; + uint8_t H0_rh_x2, H1_rh_x2; + uint8_t tempReg[2] = {0, 0}; + + if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T0_degC_X8_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + T0_degC_x8_L = (uint16_t)tempReg[0]; + + if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T1_T0_MSB_X8_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + T0_degC_x8_H = (uint16_t) (tempReg[0] & 0x03); + T0_degC = ((float)((T0_degC_x8_H << 8) | (T0_degC_x8_L))) / 8; + + if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T1_degC_X8_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + T1_degC_x8_L = (uint16_t)tempReg[0]; + + if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T1_T0_MSB_X8_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + T1_degC_x8_H = (uint16_t) (tempReg[0] & 0x0C); + T1_degC_x8_H = T1_degC_x8_H >> 2; + T1_degC = ((float)((T1_degC_x8_H << 8) | (T1_degC_x8_L))) / 8; + + if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, (HTS221_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), 2) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, (HTS221_T1_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), 2) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + T1_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + /* Humidity Calibration */ + /* Humidity in degree for calibration ( "/2" to obtain float) */ + + if(HTS221_IO_Read(&H0_rh_x2, HTS221_ADDRESS, HTS221_H0_RH_X2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + if(HTS221_IO_Read(&H1_rh_x2, HTS221_ADDRESS, HTS221_H1_RH_X2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_H0_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), + 2) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + H0_T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_H1_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), + 2) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + H1_T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + H0_rh = ((float)H0_rh_x2) / 2; + H1_rh = ((float)H1_rh_x2) / 2; + + return HUM_TEMP_OK; +} + + +/** + * @brief Set HTS221 Initialization + * @param HTS221_Init the configuration setting for the HTS221 + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_Init(HUM_TEMP_InitTypeDef *HTS221_Init) +{ + uint8_t tmp = 0x00; + + /* Configure the low level interface ---------------------------------------*/ + if(HTS221_IO_Init() != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + if(HTS221_Power_On() != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + if(HTS221_Calibration() != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Output Data Rate selection */ + tmp &= ~(HTS221_ODR_MASK); + tmp |= HTS221_Init->OutputDataRate; + + if(HTS221_IO_Write(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + HTS221_IO_ITConfig(); + + return HUM_TEMP_OK; +} + +/** + * @brief Read ID address of HTS221 + * @param ht_id the pointer where the ID of the device is stored + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_ReadID(uint8_t *ht_id) +{ + if(!ht_id) + { + return HUM_TEMP_ERROR; + } + + return HTS221_IO_Read(ht_id, HTS221_ADDRESS, HTS221_WHO_AM_I_ADDR, 1); +} + +/** + * @brief Reboot memory content of HTS221 + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_RebootCmd(void) +{ + uint8_t tmpreg; + + /* Read CTRL_REG2 register */ + if(HTS221_IO_Read(&tmpreg, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Enable or Disable the reboot memory */ + tmpreg |= HTS221_BOOT_REBOOTMEMORY; + + /* Write value to MEMS CTRL_REG2 regsister */ + if(HTS221_IO_Write(&tmpreg, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + return HUM_TEMP_OK; +} + + +/** + * @brief Read HTS221 output register, and calculate the humidity + * @param pfData the pointer to data output + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_GetHumidity(float* pfData) +{ + int16_t H_T_out, humidity_t; + uint8_t tempReg[2] = {0, 0}; + uint8_t tmp = 0x00; + float H_rh; + + if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Output Data Rate selection */ + tmp &= (HTS221_ODR_MASK); + + if(tmp == 0x00) + { + if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Serial Interface Mode selection */ + tmp &= ~(HTS221_ONE_SHOT_MASK); + tmp |= HTS221_ONE_SHOT_START; + + if(HTS221_IO_Write(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + do + { + + if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_STATUS_REG_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + } + while(!(tmp && 0x02)); + } + + + if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_HUMIDITY_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), + 2) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + H_T_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + H_rh = ( float )(((( H_T_out - H0_T0_out ) * ( H1_rh - H0_rh )) / ( H1_T0_out - H0_T0_out )) + H0_rh ); + + // Truncate to specific number of decimal digits + humidity_t = (uint16_t)(H_rh * pow(10, HUM_DECIMAL_DIGITS)); + *pfData = ((float)humidity_t) / pow(10, HUM_DECIMAL_DIGITS); + + // Prevent data going below 0% and above 100% due to linear interpolation + if ( *pfData < 0.0f ) *pfData = 0.0f; + if ( *pfData > 100.0f ) *pfData = 100.0f; + + return HUM_TEMP_OK; +} + +/** + * @brief Read HTS221 output register, and calculate the temperature + * @param pfData the pointer to data output + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_GetTemperature(float* pfData) +{ + int16_t T_out, temperature_t; + uint8_t tempReg[2] = {0, 0}; + uint8_t tmp = 0x00; + float T_degC; + + if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Output Data Rate selection */ + tmp &= (HTS221_ODR_MASK); + + if(tmp == 0x00) + { + if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Serial Interface Mode selection */ + tmp &= ~(HTS221_ONE_SHOT_MASK); + tmp |= HTS221_ONE_SHOT_START; + + if(HTS221_IO_Write(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + do + { + + if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_STATUS_REG_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + } + while(!(tmp && 0x01)); + } + + if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_TEMP_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), + 2) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + T_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + T_degC = ((float)(T_out - T0_out)) / (T1_out - T0_out) * (T1_degC - T0_degC) + T0_degC; + + temperature_t = (int16_t)(T_degC * pow(10, TEMP_DECIMAL_DIGITS)); + + *pfData = ((float)temperature_t) / pow(10, TEMP_DECIMAL_DIGITS); + + return HUM_TEMP_OK; +} + + +/** + * @brief Exit the shutdown mode for HTS221 + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_Power_On(void) +{ + uint8_t tmpReg; + + /* Read the register content */ + if(HTS221_IO_Read(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Set the power down bit */ + tmpReg |= HTS221_MODE_ACTIVE; + + /* Write register */ + if(HTS221_IO_Write(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + return HUM_TEMP_OK; +} + +/** + * @brief Enter the shutdown mode for HTS221 + * @retval HUM_TEMP_OK in case of success, an error code otherwise + */ +static HUM_TEMP_StatusTypeDef HTS221_Power_OFF(void) +{ + uint8_t tmpReg; + + /* Read the register content */ + if(HTS221_IO_Read(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + /* Reset the power down bit */ + tmpReg &= ~(HTS221_MODE_ACTIVE); + + /* Write register */ + if(HTS221_IO_Write(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + return HUM_TEMP_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.h b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.h new file mode 100644 index 000000000..3dfd16109 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.h @@ -0,0 +1,599 @@ +/** + ****************************************************************************** + * @file hts221.h + * @author MEMS Application Team + * @version V1.2.0 + * @date 11-February-2015 + * @brief This file contains definitions for the hts221.c + * firmware driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HTS221_H +#define __HTS221_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "hum_temp.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup HTS221 + * @{ + */ + +/** @defgroup HTS221_Exported_Defines HTS221_Exported_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif + +/** + * @brief Device Address + */ +#define HTS221_ADDRESS 0xBE + +/******************************************************************************/ +/*************************** START REGISTER MAPPING **************************/ +/******************************************************************************/ + + +/** + * @brief Device identification register. + * \code + * Read + * Default value: 0xBC + * 7:0 This read-only register contains the device identifier that, for HTS221, is set to BCh. + * \endcode +*/ +#define HTS221_WHO_AM_I_ADDR 0x0F + + +/** + * @brief Humidity resolution Register + * \code + * Read/write + * Default value: 0x1B + * 7:6 RFU + * 5:3 AVGT2-AVGT0: Temperature internal average. + * AVGT2 | AVGT1 | AVGT0 | Nr. Internal Average + * ------------------------------------------------------ + * 0 | 0 | 0 | 2 + * 0 | 0 | 1 | 4 + * 0 | 1 | 0 | 8 + * 0 | 1 | 1 | 16 + * 1 | 0 | 0 | 32 + * 1 | 0 | 1 | 64 + * 1 | 1 | 0 | 128 + * 1 | 1 | 1 | 256 + * + * 2:0 AVGH2-AVGH0: Humidity internal average. + * AVGH2 | AVGH1 | AVGH0 | Nr. Internal Average + * ------------------------------------------------------ + * 0 | 0 | 0 | 4 + * 0 | 0 | 1 | 8 + * 0 | 1 | 0 | 16 + * 0 | 1 | 1 | 32 + * 1 | 0 | 0 | 64 + * 1 | 0 | 1 | 128 + * 1 | 1 | 0 | 256 + * 1 | 1 | 1 | 512 + * + * \endcode + */ +#define HTS221_RES_CONF_ADDR 0x10 + + +/** +* @brief INFO Register (LSB data) +* \code +* Read/write +* Default value: 0x00 +* 7:0 INFO7-INFO0: Lower part of the INFO reference +* used for traceability of the sample. +* \endcode +*/ +#define HTS221_INFO_L_ADDR 0x1E + + +/** +* @brief INFO & Calibration Version Register (LSB data) +* \code +* Read/write +* Default value: 0x00 +* 7:6 CALVER1:CALVER0 +* 5:0 INFO13-INFO8: Higher part of the INFO reference +* used for traceability of the sample. +* \endcode +*/ +#define HTS221_INFO_H_ADDR 0x1F + + +/** +* @brief Humidity sensor control register 1 +* \code +* Read/write +* Default value: 0x00 +* 7 PD: power down control. 0 - disable; 1 - enable +* 6:3 RFU +* 2 BDU: block data update. 0 - disable; 1 - enable +* 1:0 RFU +* \endcode +*/ + +#define HTS221_CTRL_REG1_ADDR 0x20 + + +/** +* @brief Humidity sensor control register 2 +* \code +* Read/write +* Default value: 0x00 +* 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content +* 6:3 Reserved. +* 2 Reserved. +* 1 Reserved. +* 0 ONE_SHOT: One shot enable. 0: waiting for start of conversion; 1: start for a new dataset +* \endcode +*/ +#define HTS221_CTRL_REG2_ADDR 0x21 + + +/** +* @brief Humidity sensor control register 3 +* \code +* Read/write +* Default value: 0x00 +* [7] DRDY_H_L: Data Ready output signal active high, low (0: active high -default;1: active low) +* [6] PP_OD: Push-pull / Open Drain selection on pin 3 (DRDY) (0: push-pull - default; 1: open drain) +* [5:3] Reserved +* [2] DRDY_EN: Data Ready enable (0: Data Ready disabled - default;1: Data Ready signal available on pin 3) +* [1:0] Reserved +* \endcode +*/ +#define HTS221_CTRL_REG3_ADDR 0x22 + + +/** +* @brief Status Register +* \code +* Read +* Default value: 0x00 +* 7:2 RFU +* 1 H_DA: Humidity data available. 0: new data for Humidity is not yet available; 1: new data for Humidity is available. +* 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. +* \endcode +*/ +#define HTS221_STATUS_REG_ADDR 0x27 + + +/** +* @brief Humidity data (LSB). +* \code +* Read +* Default value: 0x00. +* POUT7 - POUT0: Humidity data LSB (2's complement) => signed 16 bits +* RAW Humidity output data: Hout(%)=(HUMIDITY_OUT_H & HUMIDITY_OUT_L). +* \endcode +*/ +#define HTS221_HUMIDITY_OUT_L_ADDR 0x28 + + +/** +* @brief Humidity data (MSB). +* \code +* Read +* Default value: 0x00. +* POUT7 - POUT0: Humidity data LSB (2's complement) => signed 16 bits +* RAW Humidity output data: Hout(%)=(HUMIDITY_OUT_H & HUMIDITY_OUT_L). +* \endcode +*/ +#define HTS221_HUMIDITY_OUT_H_ADDR 0x29 + + +/** +* @brief Temperature data (LSB). +* \code +* Read +* Default value: 0x00. +* TOUT7 - TOUT0: temperature data LSB (2's complement) => signed 16 bits +* RAW Temperature output data: Tout (LSB)=(TEMP_OUT_H & TEMP_OUT_L). +* \endcode +*/ +#define HTS221_TEMP_OUT_L_ADDR 0x2A + + +/** +* @brief Temperature data (MSB). +* \code +* Read +* Default value: 0x00. +* TOUT15 - TOUT8: temperature data MSB (2's complement) => signed 16 bits +* RAW Temperature output data: Tout (LSB)=(TEMP_OUT_H & TEMP_OUT_L). +* \endcode +*/ +#define HTS221_TEMP_OUT_H_ADDR 0x2B + + +/** +*@brief Humidity 0 Register in %RH with sensitivity=2 +*\code +* Read +* Value: (Unsigned 8 Bit)/2 +*\endcode +*/ +#define HTS221_H0_RH_X2_ADDR 0x30 + + +/** +*@brief Humidity 1 Register in %RH with sensitivity=2 +*\code +* Read +* Value: (Unsigned 8 Bit)/2 +*\endcode +*/ +#define HTS221_H1_RH_X2_ADDR 0x31 + + +/** +*@brief Temperature 0 Register in deg with sensitivity=8 +*\code +* Read +* Value: (Unsigned 16 Bit)/2 +*\endcode +*/ +#define HTS221_T0_degC_X8_ADDR 0x32 + + +/** +*@brief Temperature 1 Register in deg with sensitivity=8 +*\code +* Read +* Value: (Unsigned 16 Bit)/2 +*\endcode +*/ +#define HTS221_T1_degC_X8_ADDR 0x33 + + +/** +*@brief Temperature 1/0 MSB Register in deg with sensitivity=8 +*\code +* Read +* Value: (Unsigned 16 Bit)/2 +* 3:2 T1(9):T1(8) MSB T1_degC_X8 bits +* 1:0 T0(9):T0(8) MSB T0_degC_X8 bits +*\endcode +*/ +#define HTS221_T1_T0_MSB_X8_ADDR 0x35 + + +/** +*@brief Humidity LOW CALIBRATION Register +*\code +* Read +* Default value: 0x00. +* H0_T0_TOUT7 - H0_T0_TOUT0: HUMIDITY data lSB (2's complement) => signed 16 bits +*\endcode +*/ +#define HTS221_H0_T0_OUT_L_ADDR 0x36 + + +/** +*@brief Humidity LOW CALIBRATION Register +*\code +* Read +* Default value: 0x00. +* H0_T0_TOUT15 - H0_T0_TOUT8: HUMIDITY data mSB (2's complement) => signed 16 bits +*\endcode +*/ +#define HTS221_H0_T0_OUT_H_ADDR 0x37 + + +/** +*@brief Humidity HIGH CALIBRATION Register +*\code +* Read +* Default value: 0x00. +* H1_T0_TOUT7 - H1_T0_TOUT0: HUMIDITY data lSB (2's complement) => signed 16 bits +*\endcode +*/ +#define HTS221_H1_T0_OUT_L_ADDR 0x3A + + +/** +*@brief Humidity HIGH CALIBRATION Register +*\code +* Read +* Default value: 0x00. +* H1_T0_TOUT15 - H1_T0_TOUT8: HUMIDITY data mSB (2's complement) => signed 16 bits +*\endcode +*/ +#define HTS221_H1_T0_OUT_H_ADDR 0x3B + + +/** +* @brief Low Calibration Temperature Register (LSB). +* \code +* Read +* Default value: 0x00. +* T0_OUT7 - T0_OUT0: temperature data LSB (2's complement) => signed 16 bits +* RAW LOW Calibration data: T0_OUT (LSB)=(T0_OUT_H & T0_OUT_L). +* \endcode +*/ +#define HTS221_T0_OUT_L_ADDR 0x3C + + +/** +* @brief Low Calibration Temperature Register (MSB) +* \code +* Read +* Default value: 0x00. +* T0_OUT15 - T0_OUT8: temperature data MSB (2's complement) => signed 16 bits +* RAW LOW Calibration data: T0_OUT (LSB)=(T0_OUT_H & T0_OUT_L). +* \endcode +*/ +#define HTS221_T0_OUT_H_ADDR 0x3D + + +/** +* @brief Low Calibration Temperature Register (LSB). +* \code +* Read +* Default value: 0x00. +* T1_OUT7 - T1_OUT0: temperature data LSB (2's complement) => signed 16 bits +* RAW LOW Calibration data: T1_OUT (LSB)=(T1_OUT_H & T1_OUT_L). +* \endcode +*/ +#define HTS221_T1_OUT_L_ADDR 0x3E + + +/** +* @brief Low Calibration Temperature Register (MSB) +* \code +* Read +* Default value: 0x00. +* T1_OUT15 - T1_OUT8: temperature data MSB (2's complement) => signed 16 bits +* RAW LOW Calibration data: T1_OUT (LSB)=(T1_OUT_H & T1_OUT_L). +* \endcode +*/ +#define HTS221_T1_OUT_H_ADDR 0x3F + + +/******************************************************************************/ +/**************************** END REGISTER MAPPING ***************************/ +/******************************************************************************/ + +/** + * @brief Multiple Byte. Mask for enabling multiple byte read/write command. + */ +#define HTS221_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) + +/** + * @brief Device Identifier. Default value of the WHO_AM_I register. + */ +#define I_AM_HTS221 ((uint8_t)0xBC) + + +/** @defgroup HTS221_Power_Mode_Selection_CTRL_REG1 HTS221_Power_Mode_Selection_CTRL_REG1 + * @{ + */ +#define HTS221_MODE_POWERDOWN ((uint8_t)0x00) +#define HTS221_MODE_ACTIVE ((uint8_t)0x80) + +#define HTS221_MODE_MASK ((uint8_t)0x80) +/** + * @} + */ + + +/** @defgroup HTS221_Block_Data_Update_Mode_Selection_CTRL_REG1 HTS221_Block_Data_Update_Mode_Selection_CTRL_REG1 + * @{ + */ +#define HTS221_BDU_CONTINUOUS ((uint8_t)0x00) +#define HTS221_BDU_NOT_UNTIL_READING ((uint8_t)0x04) + +#define HTS221_BDU_MASK ((uint8_t)0x04) +/** + * @} + */ + +/** @defgroup HTS221_Output_Data_Rate_Selection_CTRL_REG1 HTS221_Output_Data_Rate_Selection_CTRL_REG1 + * @{ + */ +#define HTS221_ODR_ONE_SHOT ((uint8_t)0x00) /*!< Output Data Rate: H - one shot, T - one shot */ +#define HTS221_ODR_1Hz ((uint8_t)0x01) /*!< Output Data Rate: H - 1Hz, T - 1Hz */ +#define HTS221_ODR_7Hz ((uint8_t)0x02) /*!< Output Data Rate: H - 7Hz, T - 7Hz */ +#define HTS221_ODR_12_5Hz ((uint8_t)0x03) /*!< Output Data Rate: H - 12.5Hz, T - 12.5Hz */ + +#define HTS221_ODR_MASK ((uint8_t)0x03) +/** +* @} +*/ + + +/** @defgroup HTS221_Boot_Mode_Selection_CTRL_REG2 HTS221_Boot_Mode_Selection_CTRL_REG2 + * @{ + */ +#define HTS221_BOOT_NORMALMODE ((uint8_t)0x00) +#define HTS221_BOOT_REBOOTMEMORY ((uint8_t)0x80) + +#define HTS221_BOOT_MASK ((uint8_t)0x80) +/** + * @} + */ + + +/** @defgroup HTS221_One_Shot_Selection_CTRL_REG2 HTS221_One_Shot_Selection_CTRL_REG2 + * @{ + */ +#define HTS221_ONE_SHOT_START ((uint8_t)0x01) + +#define HTS221_ONE_SHOT_MASK ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup HTS221_PushPull_OpenDrain_Selection_CTRL_REG3 HTS221_PushPull_OpenDrain_Selection_CTRL_REG3 + * @{ + */ +#define HTS221_PP_OD_PUSH_PULL ((uint8_t)0x00) +#define HTS221_PP_OD_OPEN_DRAIN ((uint8_t)0x40) + +#define HTS221_PP_OD_MASK ((uint8_t)0x40) +/** + * @} + */ + + +/** @defgroup HTS221_Data_Ready_Selection_CTRL_REG3 HTS221_Data_Ready_Selection_CTRL_REG3 + * @{ + */ +#define HTS221_DRDY_DISABLE ((uint8_t)0x00) +#define HTS221_DRDY_AVAILABLE ((uint8_t)0x04) + +#define HTS221_DRDY_MASK ((uint8_t)0x04) +/** + * @} + */ + + +/** @defgroup HTS221_Humidity_Resolution_Selection_RES_CONF HTS221_Humidity_Resolution_Selection_RES_CONF + * @{ + */ +#define HTS221_H_RES_AVG_4 ((uint8_t)0x00) +#define HTS221_H_RES_AVG_8 ((uint8_t)0x01) +#define HTS221_H_RES_AVG_16 ((uint8_t)0x02) +#define HTS221_H_RES_AVG_32 ((uint8_t)0x03) +#define HTS221_H_RES_AVG_64 ((uint8_t)0x04) +#define HTS221_H_RES_AVG_128 ((uint8_t)0x05) + +#define HTS221_H_RES_MASK ((uint8_t)0x07) +/** + * @} + */ + + +/** @defgroup HTS221_Temperature_Resolution_Selection_RES_CONF HTS221_Temperature_Resolution_Selection_RES_CONF + * @{ + */ +#define HTS221_T_RES_AVG_2 ((uint8_t)0x00) +#define HTS221_T_RES_AVG_4 ((uint8_t)0x08) +#define HTS221_T_RES_AVG_8 ((uint8_t)0x10) +#define HTS221_T_RES_AVG_16 ((uint8_t)0x18) +#define HTS221_T_RES_AVG_32 ((uint8_t)0x20) +#define HTS221_T_RES_AVG_64 ((uint8_t)0x28) + +#define HTS221_T_RES_MASK ((uint8_t)0x38) +/** + * @} + */ + + +/** @defgroup HTS221_Temperature_Humidity_Data_Available_STATUS_REG HTS221_Temperature_Humidity_Data_Available_STATUS_REG + * @{ + */ +#define HTS221_H_DATA_AVAILABLE_MASK ((uint8_t)0x02) +#define HTS221_T_DATA_AVAILABLE_MASK ((uint8_t)0x01) +/** + * @} + */ + +/* Data resolution */ +#define HUM_DECIMAL_DIGITS (2) +#define TEMP_DECIMAL_DIGITS (2) + +/** + * @} + */ + + +/** @defgroup HTS221_Imported_Functions HTS221_Imported_Functions + * @{ + */ +/* HUM_TEMP sensor IO functions */ +extern HUM_TEMP_StatusTypeDef HTS221_IO_Init(void); +extern HUM_TEMP_StatusTypeDef HTS221_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToWrite); +extern HUM_TEMP_StatusTypeDef HTS221_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToRead); +extern void HTS221_IO_ITConfig( void ); + +/** + * @} + */ + +/* ------------------------------------------------------- */ +/* Here you should declare the internal struct of */ +/* extended features of HTS221. See the example of */ +/* LSM6DS3 in lsm6ds3.h */ +/* ------------------------------------------------------- */ + +/** @addtogroup HTS221_Exported_Variables HTS221_Exported_Variables + * @{ + */ +/* HUM_TEMP sensor driver structure */ +extern HUM_TEMP_DrvTypeDef Hts221Drv; +extern HUM_TEMP_DrvExtTypeDef Hts221Drv_ext; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HTS221_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/Release_Notes.html new file mode 100644 index 000000000..6992e69ea --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/Release_Notes.html @@ -0,0 +1,209 @@ + + + + + +Release Notes for STM32 BlueEnergy Library + + + + + +
+


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Back to Release page

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+

Release Notes for LIS3MDL component

+

Copyright +2015 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+ + +

V1.3.0 +/ 28-May-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add LIS3MDL_M_GetAxes API +
    • +
+ +

V1.2.0 +/ 11-February-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add extended features support for the Component +
    • +
+ +

V1.1.0 +/ 12-December-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • Add error control in the Component API +
    • +
+ +

V1.0.0 +/ 10-September-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • First +official release
    • +
+ + +

License
+

+ + +Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

+ + +
+ http://www.st.com/software_license_agreement_liberty_v2


+ +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + + + + +

+ +
+
+

For +complete documentation on STM32 STM BlueNRG +visit www.st.com/BlueNRG

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.c b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.c new file mode 100644 index 000000000..00be3ea3d --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.c @@ -0,0 +1,280 @@ +/** + ****************************************************************************** + * @file lis3mdl.c + * @author MEMS Application Team + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file provides a set of functions needed to manage the lis3mdl. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "lis3mdl.h" +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LIS3MDL + * @{ + */ + +static MAGNETO_StatusTypeDef LIS3MDL_Init(MAGNETO_InitTypeDef *LIS3MDL_Init); +static MAGNETO_StatusTypeDef LIS3MDL_Read_M_ID(uint8_t *m_id); +static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxes(int32_t *pData); +static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxesRaw(int16_t *pData); + +/** @defgroup LIS3MDL_Private_Variables LIS3MDL_Private_Variables + * @{ + */ +MAGNETO_DrvTypeDef LIS3MDLDrv = +{ + LIS3MDL_Init, + LIS3MDL_Read_M_ID, + LIS3MDL_M_GetAxes, + LIS3MDL_M_GetAxesRaw, + NULL +}; + +/* ------------------------------------------------------- */ +/* Here you should declare the variable that implements */ +/* the internal struct of extended features of LIS3MDL. */ +/* Then you must update the NULL pointer in the variable */ +/* of the extended features below. */ +/* See the example of LSM6DS3 in lsm6ds3.c */ +/* ------------------------------------------------------- */ + +MAGNETO_DrvExtTypeDef LIS3MDLDrv_ext = +{ + MAGNETO_LIS3MDL_COMPONENT, /* unique ID for LIS3MDL in the MAGNETO driver class */ + NULL /* pointer to internal struct of extended features of LIS3MDL */ +}; + +/** + * @} + */ + +/** @defgroup LIS3MDL_Private_Functions LIS3MDL_Private_Functions + * @{ + */ + +/** + * @brief Set LIS3MDL Initialization + * @param LIS3MDL_Init the configuration setting for the LIS3MDL + * @retval MAGNETO_OK in case of success, an error code otherwise + */ +static MAGNETO_StatusTypeDef LIS3MDL_Init(MAGNETO_InitTypeDef *LIS3MDL_Init) +{ + uint8_t tmp1 = 0x00; + + /* Configure the low level interface ---------------------------------------*/ + if(LIS3MDL_IO_Init() != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + /****** Magnetic sensor *******/ + + if(LIS3MDL_IO_Read(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG3_M, 1) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + /* Conversion mode selection */ + tmp1 &= ~(LIS3MDL_M_MD_MASK); + tmp1 |= LIS3MDL_Init->M_OperatingMode; + + if(LIS3MDL_IO_Write(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG3_M, 1) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + if(LIS3MDL_IO_Read(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG1_M, 1) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + /* Output data rate selection */ + tmp1 &= ~(LIS3MDL_M_DO_MASK); + tmp1 |= LIS3MDL_Init->M_OutputDataRate; + + /* X and Y axes Operative mode selection */ + tmp1 &= ~(LIS3MDL_M_OM_MASK); + tmp1 |= LIS3MDL_Init->M_XYOperativeMode; + + if(LIS3MDL_IO_Write(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG1_M, 1) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + if(LIS3MDL_IO_Read(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG2_M, 1) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + /* Full scale selection */ + tmp1 &= ~(LIS3MDL_M_FS_MASK); + tmp1 |= LIS3MDL_Init->M_FullScale; + + if(LIS3MDL_IO_Write(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG2_M, 1) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + /* Configure interrupt lines */ + LIS3MDL_IO_ITConfig(); + + return MAGNETO_OK; + + /******************************/ +} + + +/** + * @brief Read ID of LIS3MDL Magnetic sensor + * @param m_id the pointer where the ID of the device is stored + * @retval MAGNETO_OK in case of success, an error code otherwise + */ +static MAGNETO_StatusTypeDef LIS3MDL_Read_M_ID(uint8_t *m_id) +{ + if(!m_id) + { + return MAGNETO_ERROR; + } + + return LIS3MDL_IO_Read(m_id, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_WHO_AM_I_ADDR, 1); +} + + +/** + * @brief Read raw data from LIS3MDL Magnetic sensor output register + * @param pData the pointer where the magnetometer raw data are stored + * @retval MAGNETO_OK in case of success, an error code otherwise + */ +static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxesRaw(int16_t *pData) +{ + uint8_t tempReg[2] = {0, 0}; + + if(LIS3MDL_IO_Read(&tempReg[0], LIS3MDL_M_MEMS_ADDRESS, (LIS3MDL_M_OUT_X_L_M | LIS3MDL_I2C_MULTIPLEBYTE_CMD), + 2) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LIS3MDL_IO_Read(&tempReg[0], LIS3MDL_M_MEMS_ADDRESS, (LIS3MDL_M_OUT_Y_L_M | LIS3MDL_I2C_MULTIPLEBYTE_CMD), + 2) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LIS3MDL_IO_Read(&tempReg[0], LIS3MDL_M_MEMS_ADDRESS, (LIS3MDL_M_OUT_Z_L_M | LIS3MDL_I2C_MULTIPLEBYTE_CMD), + 2) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + return MAGNETO_OK; +} + + +/** + * @brief Read data from LIS3MDL Magnetic sensor and calculate Magnetic in mgauss + * @param pData the pointer where the magnetometer data are stored + * @retval MAGNETO_OK in case of success, an error code otherwise + */ +static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxes(int32_t *pData) +{ + uint8_t tempReg = 0x00; + int16_t pDataRaw[3]; + float sensitivity = 0; + + if(LIS3MDL_M_GetAxesRaw(pDataRaw) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + if(LIS3MDL_IO_Read(&tempReg, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG2_M, 1) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + tempReg &= LIS3MDL_M_FS_MASK; + + switch(tempReg) + { + case LIS3MDL_M_FS_4: + sensitivity = 0.14; + break; + case LIS3MDL_M_FS_8: + sensitivity = 0.29; + break; + case LIS3MDL_M_FS_12: + sensitivity = 0.43; + break; + case LIS3MDL_M_FS_16: + sensitivity = 0.58; + break; + } + + pData[0] = (int32_t)(pDataRaw[0] * sensitivity); + pData[1] = (int32_t)(pDataRaw[1] * sensitivity); + pData[2] = (int32_t)(pDataRaw[2] * sensitivity); + + return MAGNETO_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.h b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.h new file mode 100644 index 000000000..08096e7f0 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.h @@ -0,0 +1,455 @@ +/** + ****************************************************************************** + * @file lis3mdl.h + * @author MEMS Application Team + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file contains definitions for the lis3mdl.c + * firmware driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LIS3MDL_H +#define __LIS3MDL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "magneto.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LIS3MDL + * @{ + */ + +/** @defgroup LIS3MDL_Exported_Defines LIS3MDL_Exported_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif + + +/******************************************************************************/ +/***************** START MAGNETIC SENSOR REGISTER MAPPING ********************/ +/******************************************************************************/ + +/** + * @brief Device identifier register. + * \code + * Read + * Default value: + * 7:0 This read-only register contains the device identifier + * \endcode +*/ +#define LIS3MDL_M_WHO_AM_I_ADDR 0x0F + + +/** + * @brief Magnetic sensor Control Register 1 + * \code + * Read/write + * Default value: 0x10 + * [7] TEMP_COMP: Temperature compensation enable + * [6:5] OM1-0: X and Y axes operative mode selection + * [4:2] DO2-0: Output data rate selection + * [1] This bit must be set to ‘0’ for the correct operation of the device + * [0] ST: Self-test enable + * \endcode + */ +#define LIS3MDL_M_CTRL_REG1_M 0x20 + + +/** + * @brief Magnetic sensor Control Register 2 + * \code + * Read/write + * Default value: 0x00 + * [7] These bits must be set to ‘0’ for the correct operation of the device + * [6:5] FS1-0: Full-scale configuration + * [4] These bits must be set to ‘0’ for the correct operation of the device + * [3] REBOOT: Reboot memory content + * [2] SOFT_RST: Configuration registers and user register reset function + * [1:0] These bits must be set to ‘0’ for the correct operation of the device + * \endcode + */ +#define LIS3MDL_M_CTRL_REG2_M 0x21 + + +/** + * @brief Magnetic sensor Control Register 3 + * \code + * Read/write + * Default value: 0x03 + * [7] I2C_DISABLE: Disable I2C interface + * [6] These bits must be set to ‘0’ for the correct operation of the device + * [5] LP: Low-power mode configuration + * [4:3] These bits must be set to ‘0’ for the correct operation of the device + * [2] SIM: SPI Serial Interface mode selection + * [1:0] MD1-0: Operating mode selection + * \endcode + */ +#define LIS3MDL_M_CTRL_REG3_M 0x22 + + +/** + * @brief Magnetic sensor data (LSB) + * \code + * Read + * \endcode + */ +#define LIS3MDL_M_OUT_X_L_M 0x28 + + +/** + * @brief Magnetic sensor data (MSB) + * \code + * Read + * \endcode + */ +#define LIS3MDL_M_OUT_X_H_M 0x29 + + +/** + * @brief Magnetic sensor data (LSB) + * \code + * Read + * \endcode + */ +#define LIS3MDL_M_OUT_Y_L_M 0x2A + + +/** + * @brief Magnetic sensor data (MSB) + * \code + * Read + * \endcode + */ +#define LIS3MDL_M_OUT_Y_H_M 0x2B + + +/** + * @brief Magnetic sensor data (LSB) + * \code + * Read + * \endcode + */ +#define LIS3MDL_M_OUT_Z_L_M 0x2C + + +/** + * @brief Magnetic sensor data (MSB) + * \code + * Read + * \endcode + */ +#define LIS3MDL_M_OUT_Z_H_M 0x2D + + +/** + * @brief Magnetic sensor Interrupt config register + * \code + * Read/write + * Default value: 0x00 + * [7] XIEN: Enable interrupt generation on X axis + * [6] YIEN: Enable interrupt generation on Y axis + * [5] ZIEN: Enable interrupt generation on Z axis + * [4:3] Must be 0 + * [2] IEA: Interrupt active configuration on INT + * [1] LIR: Latch interrupt request + * [0] IEN: Interrupt enable on INT pin + * \endcode + */ +#define LIS3MDL_M_INT_CFG 0x30 + + +/** + * @brief Magnetic sensor Interrupt source register + * \code + * Read/write + * Default value: 0x00 + * [7] PTH_X: Value on X-axis exceeds the threshold on the positive side + * [6] PTH_Y: Value on Y-axis exceeds the threshold on the positive side + * [5] PTH_Z: Value on Z-axis exceeds the threshold on the positive side + * [4] NTH_X: Value on X-axis exceeds the threshold on the negative side + * [3] NTH_Y: Value on Y-axis exceeds the threshold on the negative side + * [2] NTH_Z: Value on Z-axis exceeds the threshold on the negative side + * [1] MROI: Internal measurement range overflow on magnetic value + * [0] INT: This bit signals when interrupt event occours + * \endcode + */ +#define LIS3MDL_M_INT_SRC 0x31 + + +/** + * @brief Magnetic sensor Interrupt threshold register low + * \code + * Read/write + * Default value: 0x00 + * [7:0] THS7-0: Least 8 significant bits of interrupt threshold + * \endcode + */ +#define LIS3MDL_M_INT_THS_L_M 0x32 + + +/** + * @brief Magnetic sensor Interrupt threshold register high + * \code + * Read/write + * Default value: 0x00 + * [7] Must be 0 + * [6:0] THS14-8: Most 7 significant bits of interrupt threshold + * \endcode + */ +#define LIS3MDL_M_INT_THS_H_M 0x33 + +/******************************************************************************/ +/******************* END MAGNETIC SENSOR REGISTER MAPPING ********************/ +/******************************************************************************/ + +/** + * @brief Multiple Byte. Mask for enabling multiple byte read/write command. + */ +#define LIS3MDL_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) + +/** + * @brief Device Address + */ + +#define LIS3MDL_M_MEMS_ADDRESS 0x3C // SAD[1] = 1 + +/** + * @brief Device Identifier. Default value of the WHO_AM_I register. + */ +#define I_AM_LIS3MDL_M ((uint8_t)0x3D) + + +/*********************************** MAGNETIC SENSOR REGISTERS VALUE ****************************************/ + +/** @defgroup LIS3MDL_M_Temperature_Compensation_Enable_Selection_CTRL_REG1_M LIS3MDL_M_Temperature_Compensation_Enable_Selection_CTRL_REG1_M + * @{ + */ +#define LIS3MDL_M_TEMP_COMP_DISABLE ((uint8_t)0x00) /*!< Temperature compensation: disable */ +#define LIS3MDL_M_TEMP_COMP_ENABLE ((uint8_t)0x80) /*!< Temperature compensation: enable */ + +#define LIS3MDL_M_TEMP_COMP_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_X_And_Y_Axes_Operative_Mode_Selection_CTRL_REG1_M LIS3MDL_M_X_And_Y_Axes_Operative_Mode_Selection_CTRL_REG1_M + * @{ + */ +#define LIS3MDL_M_OM_LP ((uint8_t)0x00) /*!< X and Y axes operative mode: Low-power mode */ +#define LIS3MDL_M_OM_MP ((uint8_t)0x20) /*!< X and Y axes operative mode: Medium-performance mode */ +#define LIS3MDL_M_OM_HP ((uint8_t)0x40) /*!< X and Y axes operative mode: High-performance mode */ +#define LIS3MDL_M_OM_UHP ((uint8_t)0x60) /*!< X and Y axes operative mode: Ultra-high performance mode */ + +#define LIS3MDL_M_OM_MASK ((uint8_t)0x60) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Output_Data_Rate_Selection_CTRL_REG1_M LIS3MDL_M_Output_Data_Rate_Selection_CTRL_REG1_M + * @{ + */ +#define LIS3MDL_M_DO_0_625 ((uint8_t)0x00) /*!< Output data rate selection: 0.625 */ +#define LIS3MDL_M_DO_1_25 ((uint8_t)0x04) /*!< Output data rate selection: 1.25 */ +#define LIS3MDL_M_DO_2_5 ((uint8_t)0x08) /*!< Output data rate selection: 2.5 */ +#define LIS3MDL_M_DO_5 ((uint8_t)0x0C) /*!< Output data rate selection: 5 */ +#define LIS3MDL_M_DO_10 ((uint8_t)0x10) /*!< Output data rate selection: 10 */ +#define LIS3MDL_M_DO_20 ((uint8_t)0x14) /*!< Output data rate selection: 20 */ +#define LIS3MDL_M_DO_40 ((uint8_t)0x18) /*!< Output data rate selection: 40 */ +#define LIS3MDL_M_DO_80 ((uint8_t)0x1C) /*!< Output data rate selection: 80 */ + +#define LIS3MDL_M_DO_MASK ((uint8_t)0x1C) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Self_Test_Enable_Selection_CTRL_REG1_M LIS3MDL_M_Self_Test_Enable_Selection_CTRL_REG1_M + * @{ + */ +#define LIS3MDL_M_ST_DISABLE ((uint8_t)0x00) /*!< Self-test: disable */ +#define LIS3MDL_M_ST_ENABLE ((uint8_t)0x01) /*!< Self-test: enable */ + +#define LIS3MDL_M_ST_MASK ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Full_Scale_Selection_CTRL_REG2_M LIS3MDL_M_Full_Scale_Selection_CTRL_REG2_M + * @{ + */ +#define LIS3MDL_M_FS_4 ((uint8_t)0x00) /*!< Full scale: +-4 guass */ +#define LIS3MDL_M_FS_8 ((uint8_t)0x20) /*!< Full scale: +-8 gauss */ +#define LIS3MDL_M_FS_12 ((uint8_t)0x40) /*!< Full scale: +-12 gauss */ +#define LIS3MDL_M_FS_16 ((uint8_t)0x60) /*!< Full scale: +-16 gauss */ + +#define LIS3MDL_M_FS_MASK ((uint8_t)0x60) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Reboot_Memory_Selection_CTRL_REG2_M LIS3MDL_M_Reboot_Memory_Selection_CTRL_REG2_M + * @{ + */ +#define LIS3MDL_M_REBOOT_NORMAL ((uint8_t)0x00) /*!< Reboot mode: normal mode */ +#define LIS3MDL_M_REBOOT_MEM_CONTENT ((uint8_t)0x08) /*!< Reboot mode: reboot memory content */ + +#define LIS3MDL_M_REBOOT_MASK ((uint8_t)0x08) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Configuration_Registers_And_User_Register_Reset_CTRL_REG2_M LIS3MDL_M_Configuration_Registers_And_User_Register_Reset_CTRL_REG2_M + * @{ + */ +#define LIS3MDL_M_SOFT_RST_DEFAULT ((uint8_t)0x00) /*!< Reset function: default value */ +#define LIS3MDL_M_SOFT_RST_RESET ((uint8_t)0x04) /*!< Reset function: reset operation */ + +#define LIS3MDL_M_SOFT_RST_MASK ((uint8_t)0x04) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Disable_I2C_Interface_Selection_CTRL_REG3_M LIS3MDL_M_Disable_I2C_Interface_Selection_CTRL_REG3_M + * @{ + */ +#define LIS3MDL_M_I2C_ENABLE ((uint8_t)0x00) /*!< I2C interface: enable */ +#define LIS3MDL_M_I2C_DISABLE ((uint8_t)0x80) /*!< I2C interface: disable */ + +#define LIS3MDL_M_I2C_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Low_Power_Mode_Selection_CTRL_REG3_M LIS3MDL_M_Low_Power_Mode_Selection_CTRL_REG3_M + * @{ + */ +#define LIS3MDL_M_LP_ENABLE ((uint8_t)0x00) /*!< Low-power mode: magnetic data rate is configured by + the DO bits in the CTRL_REG1_M */ +#define LIS3MDL_M_LP_DISABLE ((uint8_t)0x20) /*!< Low-power mode: the DO bits is set to 0.625 Hz and the system performs, + for each channel, the minimum number of averages */ + +#define LIS3MDL_M_LP_MASK ((uint8_t)0x20) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_SPI_Serial_Interface_Mode_Selection_CTRL_REG3_M LIS3MDL_M_SPI_Serial_Interface_Mode_Selection_CTRL_REG3_M + * @{ + */ +#define LIS3MDL_M_SPI_R_ENABLE ((uint8_t)0x00) /*!< SPI Serial Interface mode: only write operations enabled */ +#define LIS3MDL_M_SPI_R_DISABLE ((uint8_t)0x40) /*!< SPI Serial Interface mode: read and write operations enable */ + +#define LIS3MDL_M_SPI_R_MASK ((uint8_t)0x40) +/** + * @} + */ + +/** @defgroup LIS3MDL_M_Operating_Mode_Selection_CTRL_REG3_M LIS3MDL_M_Operating_Mode_Selection_CTRL_REG3_M + * @{ + */ +#define LIS3MDL_M_MD_CONTINUOUS ((uint8_t)0x00) /*!< Operating mode: Continuous-conversion mode */ +#define LIS3MDL_M_MD_SINGLE ((uint8_t)0x01) /*!< Operating mode: Single-conversion mode has to be used with sampling frequency from 0.625 Hz to 80 Hz. */ +#define LIS3MDL_M_MD_PD ((uint8_t)0x02) /*!< Operating mode: Power-down mode */ + +#define LIS3MDL_M_MD_MASK ((uint8_t)0x03) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LIS3MDL_Imported_Functions LIS3MDL_Imported_Functions + * @{ + */ + +/* Magneto sensor IO functions */ +extern MAGNETO_StatusTypeDef LIS3MDL_IO_Init(void); +extern MAGNETO_StatusTypeDef LIS3MDL_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToWrite); +extern MAGNETO_StatusTypeDef LIS3MDL_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToRead); +extern void LIS3MDL_IO_ITConfig( void ); + +/** + * @} + */ + +/* ------------------------------------------------------- */ +/* Here you should declare the internal struct of */ +/* extended features of LSM6DS0. See the example of */ +/* LSM6DS3 in lsm6ds3.h */ +/* ------------------------------------------------------- */ + +/** @addtogroup LIS3MDL_Exported_Variables LIS3MDL_Exported_Variables + * @{ + */ +/* Magneto sensor driver structure */ +extern MAGNETO_DrvTypeDef LIS3MDLDrv; +extern MAGNETO_DrvExtTypeDef LIS3MDLDrv_ext; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LIS3MDL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/Release_Notes.html new file mode 100644 index 000000000..d60d45e68 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/Release_Notes.html @@ -0,0 +1,191 @@ + + + + + +Release Notes for STM32 BlueEnergy Library + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
+

Back to Release page

+
+

Release Notes for LPS25H component

+

Copyright +2015 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+ + +

V1.2.0 +/ 11-February-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add extended features support for the Component +
    • +
+ +

V1.1.0 +/ 12-December-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • Add error control in the Component API +
    • +
+ +

V1.0.0 +/ 10-September-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • First +official release
    • +
+ + +

License
+

+ + +Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

+ + +
+ http://www.st.com/software_license_agreement_liberty_v2


+ +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + + + + +

+ +
+
+

For +complete documentation on STM32 STM BlueNRG +visit www.st.com/BlueNRG

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.c b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.c new file mode 100644 index 000000000..d2f1348b6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.c @@ -0,0 +1,394 @@ +/** + ****************************************************************************** + * @file lps25h.c + * @author MEMS Application Team + * @version V1.2.0 + * @date 11-February-2015 + * @brief This file provides a set of functions needed to manage the lps25h. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "lps25h.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LPS25H + * @{ + */ + +static PRESSURE_StatusTypeDef LPS25H_Init(PRESSURE_InitTypeDef *LPS25H_Init); +static PRESSURE_StatusTypeDef LPS25H_ReadID(uint8_t *p_id); +static PRESSURE_StatusTypeDef LPS25H_RebootCmd(void); +static PRESSURE_StatusTypeDef LPS25H_GetPressure(float* pfData); +static PRESSURE_StatusTypeDef LPS25H_GetTemperature(float* pfData); +static PRESSURE_StatusTypeDef LPS25H_PowerOff(void); +static void LPS25H_SlaveAddrRemap(uint8_t SA0_Bit_Status); + +/** @defgroup LPS25H_Private_Variables LPS25H_Private_Variables + * @{ + */ +PRESSURE_DrvTypeDef LPS25HDrv = +{ + LPS25H_Init, + LPS25H_PowerOff, + LPS25H_ReadID, + LPS25H_RebootCmd, + 0, + 0, + 0, + 0, + 0, + LPS25H_GetPressure, + LPS25H_GetTemperature, + LPS25H_SlaveAddrRemap, + NULL +}; + +/* ------------------------------------------------------- */ +/* Here you should declare the variable that implements */ +/* the internal struct of extended features of LPS25H. */ +/* Then you must update the NULL pointer in the variable */ +/* of the extended features below. */ +/* See the example of LSM6DS3 in lsm6ds3.c */ +/* ------------------------------------------------------- */ + +PRESSURE_DrvExtTypeDef LPS25HDrv_ext = +{ + PRESSURE_LPS25H_COMPONENT, /* unique ID for LPS25H in the PRESSURE driver class */ + NULL /* pointer to internal struct of extended features of LPS25H */ +}; + +uint8_t LPS25H_SlaveAddress = LPS25H_ADDRESS_HIGH; + +/** + * @} + */ + +static PRESSURE_StatusTypeDef LPS25H_PowerOn(void); +static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawPressure(int32_t *raw_press); +static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawTemperature(int16_t *raw_data); + +/** @defgroup LPS25H_Private_Functions LPS25H_Private_Functions + * @{ + */ + +/** + * @brief Set LPS25H Initialization + * @param LPS25H_Init the configuration setting for the LPS25H + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_Init(PRESSURE_InitTypeDef *LPS25H_Init) +{ + uint8_t tmp1 = 0x00; + + /* Configure the low level interface ---------------------------------------*/ + if(LPS25H_IO_Init() != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + if(LPS25H_PowerOn() != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + if(LPS25H_IO_Read(&tmp1, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Output Data Rate selection */ + tmp1 &= ~(LPS25H_ODR_MASK); + tmp1 |= LPS25H_Init->OutputDataRate; + + /* Interrupt circuit selection */ + tmp1 &= ~(LPS25H_DIFF_EN_MASK); + tmp1 |= LPS25H_Init->DiffEnable; + + /* Block Data Update selection */ + tmp1 &= ~(LPS25H_BDU_MASK); + tmp1 |= LPS25H_Init->BlockDataUpdate; + + /* Serial Interface Mode selection */ + tmp1 &= ~(LPS25H_SPI_SIM_MASK); + tmp1 |= LPS25H_Init->SPIMode; + + if(LPS25H_IO_Write(&tmp1, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + if(LPS25H_IO_Read(&tmp1, LPS25H_SlaveAddress, LPS25H_RES_CONF_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Serial Interface Mode selection */ + tmp1 &= ~(LPS25H_P_RES_MASK); + tmp1 |= LPS25H_Init->PressureResolution; + + /* Serial Interface Mode selection */ + tmp1 &= ~(LPS25H_T_RES_MASK); + tmp1 |= LPS25H_Init->TemperatureResolution; + + if(LPS25H_IO_Write(&tmp1, LPS25H_SlaveAddress, LPS25H_RES_CONF_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + LPS25H_IO_ITConfig(); + + return PRESSURE_OK; +} + +/** + * @brief Read ID address of LPS25H + * @param ht_id the pointer where the ID of the device is stored + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_ReadID(uint8_t *p_id) +{ + if(!p_id) + { + return PRESSURE_ERROR; + } + + return LPS25H_IO_Read(p_id, LPS25H_SlaveAddress, LPS25H_WHO_AM_I_ADDR, 1); +} + +/** + * @brief Reboot memory content of LPS25H + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_RebootCmd(void) +{ + uint8_t tmpreg; + + /* Read CTRL_REG5 register */ + if(LPS25H_IO_Read(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG2_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Enable or Disable the reboot memory */ + tmpreg |= LPS25H_RESET_MEMORY; + + /* Write value to MEMS CTRL_REG5 regsister */ + if(LPS25H_IO_Write(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG2_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + return PRESSURE_OK; +} + + +/** + * @brief Read LPS25H output register, and calculate the raw pressure + * @param raw_press the pressure raw value + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawPressure(int32_t *raw_press) +{ + uint8_t buffer[3], i; + uint32_t tempVal = 0; + + /* Read the register content */ + + if(LPS25H_IO_Read(buffer, LPS25H_SlaveAddress, (LPS25H_PRESS_POUT_XL_ADDR | LPS25H_I2C_MULTIPLEBYTE_CMD), + 3) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Build the raw data */ + for (i = 0 ; i < 3 ; i++) + tempVal |= (((uint32_t) buffer[i]) << (8 * i)); + + /* convert the 2's complement 24 bit to 2's complement 32 bit */ + if (tempVal & 0x00800000) + tempVal |= 0xFF000000; + + /* return the built value */ + *raw_press = ((int32_t) tempVal); + + return PRESSURE_OK; +} + +/** + * @brief Read LPS25H output register, and calculate the pressure in mbar + * @param pfData the pressure value in mbar + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_GetPressure(float* pfData) +{ + int32_t raw_press = 0; + + if(LPS25H_I2C_ReadRawPressure(&raw_press) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + *pfData = (float)raw_press / 4096.0f; + + return PRESSURE_OK; +} + +/** + * @brief Read LPS25H output register, and calculate the raw temperature + * @param raw_data the temperature raw value + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawTemperature(int16_t *raw_data) +{ + uint8_t buffer[2]; + uint16_t tempVal = 0; + + /* Read the register content */ + if(LPS25H_IO_Read(buffer, LPS25H_SlaveAddress, (LPS25H_TEMP_OUT_L_ADDR | LPS25H_I2C_MULTIPLEBYTE_CMD), + 2) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Build the raw value */ + tempVal = (((uint16_t)buffer[1]) << 8) + (uint16_t)buffer[0]; + + /* Return it */ + *raw_data = ((int16_t)tempVal); + + return PRESSURE_OK; +} + +/** + * @brief Read LPS25H output register, and calculate the temperature + * @param pfData the temperature value + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_GetTemperature(float *pfData) +{ + int16_t raw_data; + + if(LPS25H_I2C_ReadRawTemperature(&raw_data) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + *pfData = (float)((((float)raw_data / 480.0f) + 42.5f)); + + return PRESSURE_OK; +} +/** + * @brief Exit the shutdown mode for LPS25H + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_PowerOn(void) +{ + uint8_t tmpreg; + + /* Read the register content */ + if(LPS25H_IO_Read(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Set the power down bit */ + tmpreg |= LPS25H_MODE_ACTIVE; + + /* Write register */ + if(LPS25H_IO_Write(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + return PRESSURE_OK; +} + + +/** + * @brief Enter the shutdown mode for LPS25H + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25H_PowerOff(void) +{ + uint8_t tmpreg; + + /* Read the register content */ + if(LPS25H_IO_Read(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Reset the power down bit */ + tmpreg &= ~(LPS25H_MODE_ACTIVE); + + /* Write register */ + if(LPS25H_IO_Write(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + return PRESSURE_OK; +} + +/** + * @brief Set the slave address according to SA0 bit + * @param SA0_Bit_Status LPS25H_SA0_LOW or LPS25H_SA0_HIGH + * @retval None + */ +static void LPS25H_SlaveAddrRemap(uint8_t SA0_Bit_Status) +{ + LPS25H_SlaveAddress = (SA0_Bit_Status == LPS25H_SA0_LOW ? LPS25H_ADDRESS_LOW : LPS25H_ADDRESS_HIGH); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.h b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.h new file mode 100644 index 000000000..7a9f9f7c7 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.h @@ -0,0 +1,572 @@ +/** + ****************************************************************************** + * @file lps25h.h + * @author MEMS Application Team + * @version V1.2.0 + * @date 11-February-2015 + * @brief This file contains definitions for the lps25h.c + * firmware driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LPS25H_H +#define __LPS25H_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "pressure.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LPS25H + * @{ + */ + +/** @defgroup LPS25H_Exported_Defines LPS25H_Exported_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif + + +/******************************************************************************/ +/*************************** START REGISTER MAPPING **************************/ +/******************************************************************************/ + + +/** + * @brief Reference pressure (LSB data) + * \code + * Read/write + * Default value: 0x00 + * 7:0 REF7-ODR0: Lower part of the reference pressure that + * is sum to the sensor output pressure. + * \endcode + */ +#define LPS25H_REF_P_XL_ADDR 0x08 + +/** + * @brief Reference pressure (middle part) + * \code + * Read/write + * Default value: 0x00 + * 7:0 REF15-ODR8: Middle part of the reference pressure that + * is sum to the sensor output pressure. + * \endcode + */ +#define LPS25H_REF_P_L_ADDR 0x09 + +/** + * @brief Reference pressure (MSB part) + * \code + * Read/write + * Default value: 0x00 + * 7:0 REF15-ODR8: Higher part of the reference pressure that + * is sum to the sensor output pressure. + * \endcode + */ +#define LPS25H_REF_P_H_ADDR 0x0A + +/** + * @brief Device identifier register. + * \code + * Read + * Default value: 0xBD + * 7:0 This read-only register contains the device identifier that, + for LPS25H, is set to 0xCA. + * \endcode + */ +#define LPS25H_WHO_AM_I_ADDR 0x0F + +/** + * @brief Pressure and temperature resolution mode register. + * \code + * Read + * Default value: 0x05 + * [7:4] Reserved + * [3:2] AVGP1-0: select the pressure internal average. + * [1:0] AVGT1-0: select the temperature internal average. + * \endcode + */ +#define LPS25H_RES_CONF_ADDR 0x10 + +/** + * @brief Pressure sensor control register 1 + * \code + * Read/write + * Default value: 0x00 + * 7 PD: power down control. 0 - disable; 1 - enable + * 6:4 ODR2, ODR1, ODR0: output data rate selection. + * ODR2 | ODR1 | ODR0 | Pressure output data-rate(Hz) | Temperature output data-rate(Hz) + * ---------------------------------------------------------------------------------- + * 0 | 0 | 0 | one shot | one shot + * 0 | 0 | 1 | 1 | 1 + * 0 | 1 | 0 | 7 | 7 + * 0 | 1 | 1 | 12.5 | 12.5 + * 1 | 0 | 0 | 25 | 25 + * 1 | 0 | 1 | Reserved | Reserved + * 1 | 1 | 0 | Reserved | Reserved + * 1 | 1 | 1 | Reserved | Reserved + * + * 3 DIFF_EN: Interrupt circuit. 0 - disable; 1 - enable + * 2 BDU: block data update. 0 - disable; 1 - enable + * 1 DELTA_EN: delta pressure. 0 - disable; 1 - enable + * 1 RESET_AZ: reset AutoZero. 0 - disable; 1 - enable ///////ALE REVIEW + * 0 SIM: SPI Serial Interface Mode selection. 0 - SPI 4-wire; 1 - SPI 3-wire ///////ALE REVIEW + * \endcode + */ +#define LPS25H_CTRL_REG1_ADDR 0x20 + +/** + * @brief Pressure sensor control register 2 + * \code + * Read/write + * Default value: 0x00 + * 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content + * 6 FIFO_EN: FIFO. 0: disable; 1: enable + * 5 WTM_EN: FIFO Watermark level use. 0: disable; 1: enable + * 4:3 Reserved. keep these bits at 0 + * 2 SWRESET: Software reset. 0: normal mode; 1: SW reset. + * 1 AUTO_ZERO: Autozero enable. 0: normal mode; 1: autozero enable. + * 0 ONE_SHOT: One shot enable. 0: waiting for start of conversion; 1: start for a new dataset + * \endcode + */ +#define LPS25H_CTRL_REG2_ADDR 0x21 + +/** + * @brief Pressure sensor control register 3 + * \code + * Read/write + * Default value: 0x00 + * 7 INT_H_L: Interrupt. 0:active high; 1: active low. + * 6 PP_OD: Push-Pull/OpenDrain selection on interrupt pads. 0: Push-pull; 1: open drain. + * 5 Reserved + * 4:3 INT2_S2, INT2_S1: INT2 output signal selection control bits. // TO DO + * 1:0 INT1_S2, INT1_S1: data signal on INT1 pad control bits. + * INT1(2)_S2 | INT1(2)_S1 | INT1(2) pin + * ------------------------------------------------------ + * 0 | 0 | Data signal + * 0 | 1 | Pressure high (P_high) + * 1 | 0 | Pressure low (P_low) + * 1 | 1 | P_low OR P_high + + + * \endcode + */ +#define LPS25H_CTRL_REG3_ADDR 0x22 + +/** + * @brief Pressure sensor control register 4 + * \code + * Read/write + * Default value: 0x00 + * 7 P2_EMPTY: Empty Signal on INT2 pin. + * 6 P2_WTM: Watermark Signal on INT2 pin. + * 5 P2_Overrun:Overrun Signal on INT2 pin. + * 4 P2_DRDY: Data Ready Signal on INT2 pin. + * 3 P1_EMPTY: Empty Signal on INT1 pin. + * 2 P1_WTM: Watermark Signal on INT1 pin. + * 1 P1_Overrunn:Overrun Signal on INT1 pin. + * 0 P1_DRDY: Data Ready Signal on INT1 pin. + * \endcode + */ +#define LPS25H_CTRL_REG4_ADDR 0x23 + +/** + * @brief Interrupt configuration Register + * \code + * Read/write + * Default value: 0x00. + * 7:3 Reserved. + * 2 LIR: Latch Interrupt request into INT_SOURCE register. 0 - disable; 1 - enable + * 1 PL_E: Enable interrupt generation on differential pressure low event. 0 - disable; 1 - enable + * 0 PH_E: Enable interrupt generation on differential pressure high event. 0 - disable; 1 - enable + * \endcode + */ +#define LPS25H_INT_CFG_REG_ADDR 0x24 + +/** + * @brief Interrupt source Register + * \code + * Read + * Default value: 0x00. + * 7:3 0. + * 2 IA: Interrupt Active.0: no interrupt has been generated; 1: one or more interrupt events have been generated. + * 1 PL: Differential pressure Low. 0: no interrupt has been generated; 1: Low differential pressure event has occurred. + * 0 PH: Differential pressure High. 0: no interrupt has been generated; 1: High differential pressure event has occurred. + * \endcode + */ +#define LPS25H_INT_SOURCE_REG_ADDR 0x25 + +/** + * @brief Threshold pressure (LSB) + * \code + * Read + * Default value: 0x00. + * 7:0 THS7-THS0: Low part of threshold value for pressure interrupt + * generation. The complete threshold value is given by THS_P_H & THS_P_L and is + * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. + * \endcode + */ +#define LPS25H_THS_P_LOW_REG_ADDR 0x30 + +/** + * @brief Threshold pressure (MSB) + * \code + * Read + * Default value: 0x00. + * 7:0 THS15-THS8: High part of threshold value for pressure interrupt + * generation. The complete threshold value is given by THS_P_H & THS_P_L and is + * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. + * \endcode + */ +#define LPS25H_THS_P_HIGH_REG_ADDR 0x31 + +/** + * @brief Status Register + * \code + * Read + * Default value: 0x00 + * 7:6 0 + * 5 P_OR: Pressure data overrun. 0: no overrun has occurred; 1: new data for pressure has overwritten the previous one. + * 4 T_OR: Temperature data overrun. 0: no overrun has occurred; 1: a new data for temperature has overwritten the previous one. + * 3:2 0 + * 1 P_DA: Pressure data available. 0: new data for pressure is not yet available; 1: new data for pressure is available. + * 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. + * \endcode + */ +#define LPS25H_STATUS_REG_ADDR 0x27 + +/** + * @brief Pressure data (LSB). + * \code + * Read + * Default value: 0x00. + * POUT7 - POUT0: Pressure data LSB (2's complement). + * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & + * PRESS_OUT_XL)[dec]/4096. + * \endcode + */ +#define LPS25H_PRESS_POUT_XL_ADDR 0x28 + +/** + * @brief Pressure data (Middle part). + * \code + * Read + * Default value: 0x80. + * POUT15 - POUT8: Pressure data middle part (2's complement). + * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & + * PRESS_OUT_XL)[dec]/4096. + * \endcode + */ +#define LPS25H_PRESS_OUT_L_ADDR 0x29 + +/** + * @brief Pressure data (MSB). + * \code + * Read + * Default value: 0x2F. + * POUT23 - POUT16: Pressure data MSB (2's complement). + * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & + * PRESS_OUT_XL)[dec]/4096. + * \endcode + */ +#define LPS25H_PRESS_OUT_H_ADDR 0x2A + +/** + * @brief Temperature data (LSB). + * \code + * Read + * Default value: 0x00. + * TOUT7 - TOUT0: temperature data LSB. + * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. + * \endcode + */ +#define LPS25H_TEMP_OUT_L_ADDR 0x2B + +/** + * @brief Temperature data (MSB). + * \code + * Read + * Default value: 0x00. + * TOUT15 - TOUT8: temperature data MSB. + * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. + * \endcode + */ +#define LPS25H_TEMP_OUT_H_ADDR 0x2C + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * 7:5 F_MODE2, F_MODE1, F_MODE0: FIFO mode selection. + * FM2 | FM1 | FM0 | FIFO MODE + * --------------------------------------------------- + * 0 | 0 | 0 | BYPASS MODE + * 0 | 0 | 1 | FIFO MODE. Stops collecting data when full + * 0 | 1 | 0 | STREAM MODE: Keep the newest measurements in the FIFO + * 0 | 1 | 1 | STREAM MODE until trigger deasserted, then change to FIFO MODE + * 1 | 0 | 0 | BYPASS MODE until trigger deasserted, then STREAM MODE + * 1 | 0 | 1 | Reserved + * 1 | 1 | 0 | FIFO_MEAN MODE: Fifo is used to generate a running average filtered pressure + * 1 | 1 | 1 | BYPASS mode until trigger deasserted, then FIFO MODE + * + * 4:0 FIFO Mean Mode Sample size + * WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | Sample Size + * ---------------------------------------------------------------------------------- + * 0 | 0 | 0 | 0 | 1 | 2 + * 0 | 0 | 0 | 1 | 1 | 4 + * 0 | 0 | 1 | 1 | 1 | 8 + * 0 | 1 | 1 | 1 | 1 | 16 + * 1 | 1 | 1 | 1 | 1 | 32 + * other values operation not guaranteed + * \endcode + */ +#define LPS25H_CTRL_FIFO_ADDR 0x2E + +/** + * @brief FIFO Status register + * \code + * Read/write + * Default value: 0x00 + * 7 WTM_FIFO: Watermark status. 0:FIFO filling is lower than watermark level; 1: FIFO is equal or higher than watermark level. + * 6 FULL_FIFO: Overrun bit status. 0 - FIFO not full; 1 -FIFO is full. + * 5 EMPTY_FIFO: Empty FIFO bit. 0 - FIFO not empty; 1 -FIFO is empty. + * 4:0 DIFF_POINT4...0: FIFOsStored data level. + * \endcode + */ +#define LPS25H_STATUS_FIFO_ADDR 0x2F + +/** + * @brief Pressure offset register + * \code + * Read/write + * Default value: 0x00 + * 7:0 RPDS15...8:Pressure Offset for 1 point calibration after soldering. + * \endcode + */ +#define LPS25H_RPDS_TRIM_L_ADDR 0x39 + +/** + * @brief Pressure offset register + * \code + * Read/write + * Default value: 0x00 + * 7:0 RPDS23...16:Pressure Offset for 1 point calibration after soldering. + * \endcode + */ +#define LPS25H_RPDS_TRIM_H_ADDR 0x3A + +/******************************************************************************/ +/**************************** END REGISTER MAPPING ***************************/ +/******************************************************************************/ + +/** + * @brief Multiple Byte. Mask for enabling multiple byte read/write command. + */ +#define LPS25H_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) + +/** + * @brief Device Address + */ +#define LPS25H_ADDRESS_LOW 0xB8 +#define LPS25H_ADDRESS_HIGH 0xBA + + +/** + * @brief Device Identifier. Default value of the WHO_AM_I register. + */ +#define I_AM_LPS25H ((uint8_t)0xBD) + +/** @defgroup LPS25H_Power_Mode_Selection_CTRL_REG1 LPS25H_Power_Mode_Selection_CTRL_REG1 + * @{ + */ +#define LPS25H_MODE_POWERDOWN ((uint8_t)0x00) +#define LPS25H_MODE_ACTIVE ((uint8_t)0x80) + +#define LPS25H_MODE_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup LPS25H_Output_Data_Rate_Selection_CTRL_REG1 LPS25H_Output_Data_Rate_Selection_CTRL_REG1 + * @{ + */ +#define LPS25H_ODR_ONE_SHOT ((uint8_t)0x00) /*!< Output Data Rate: P - one shot, T - one shot */ +#define LPS25H_ODR_1Hz ((uint8_t)0x10) /*!< Output Data Rate: P - 1Hz, T - 1Hz */ +#define LPS25H_ODR_7Hz ((uint8_t)0x20) /*!< Output Data Rate: P - 7Hz, T - 7Hz */ +#define LPS25H_ODR_12_5Hz ((uint8_t)0x30) /*!< Output Data Rate: P - 12.5Hz, T - 12.5Hz */ +#define LPS25H_ODR_25Hz ((uint8_t)0x40) /*!< Output Data Rate: P - 25Hz, T - 25Hz */ + +#define LPS25H_ODR_MASK ((uint8_t)0x70) +/** + * @} + */ + +/** @defgroup LPS25H_Interrupt_Circuit_Enable_CTRL_REG1 LPS25H_Interrupt_Circuit_Enable_CTRL_REG1 + * @{ + */ +#define LPS25H_DIFF_DISABLE ((uint8_t)0x00) /*!< interrupt circuit enabled */ +#define LPS25H_DIFF_ENABLE ((uint8_t)0x08) /*!< interrupt generation disabled */ + +#define LPS25H_DIFF_EN_MASK ((uint8_t)0x08) +/** + * @} + */ + +/** @defgroup LPS25H_Block_Data_Update_CTRL_REG1 LPS25H_Block_Data_Update_CTRL_REG1 + * @{ + */ +#define LPS25H_BDU_CONT ((uint8_t)0x00) /*!< continuous update */ +#define LPS25H_BDU_READ ((uint8_t)0x04) /*!< output registers not updated until MSB and LSB reading */ + +#define LPS25H_BDU_MASK ((uint8_t)0x04) +/** + * @} + */ + +/** @defgroup LPS25H_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 LPS25H_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 + * @{ + */ +#define LPS25H_SPI_SIM_4W ((uint8_t)0x00) /*!< 4-wire interface */ +#define LPS25H_SPI_SIM_3W ((uint8_t)0x01) /*!< 3-wire interface */ + +#define LPS25H_SPI_SIM_MASK ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup LPS25H_Refresh_Registers_Flash_Memory_CTRL_REG2 LPS25H_Refresh_Registers_Flash_Memory_CTRL_REG2 + * @{ + */ +#define LPS25H_NORMAL_MODE ((uint8_t)0x00) +#define LPS25H_RESET_MEMORY ((uint8_t)0x80) + +#define LPS25H_RESET_MEMORY_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup LPS25H_Pressure_Resolution_Selection_RES_CONF LPS25H_Pressure_Resolution_Selection_RES_CONF + * @{ + */ +#define LPS25H_P_RES_AVG_8 ((uint8_t)0x00) +#define LPS25H_P_RES_AVG_32 ((uint8_t)0x01) +#define LPS25H_P_RES_AVG_128 ((uint8_t)0x02) +#define LPS25H_P_RES_AVG_512 ((uint8_t)0x03) + +#define LPS25H_P_RES_MASK ((uint8_t)0x03) +/** + * @} + */ + +/** @defgroup LPS25H_Temperature_Resolution_Selection_RES_CONF LPS25H_Temperature_Resolution_Selection_RES_CONF + * @{ + */ +#define LPS25H_T_RES_AVG_8 ((uint8_t)0x00) +#define LPS25H_T_RES_AVG_16 ((uint8_t)0x04) +#define LPS25H_T_RES_AVG_32 ((uint8_t)0x08) +#define LPS25H_T_RES_AVG_64 ((uint8_t)0x0C) + +#define LPS25H_T_RES_MASK ((uint8_t)0x0C) +/** + * @} + */ + +#define LPS25H_SA0_LOW ((uint8_t)0x00) +#define LPS25H_SA0_HIGH ((uint8_t)0x01) + +/** + * @} + */ + +/** @defgroup LPS25H_Imported_Functions LPS25H_Imported_Functions + * @{ + */ +/* Pressure sensor IO functions */ +extern PRESSURE_StatusTypeDef LPS25H_IO_Init(void); +extern PRESSURE_StatusTypeDef LPS25H_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToWrite); +extern PRESSURE_StatusTypeDef LPS25H_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToRead); +extern void LPS25H_IO_ITConfig( void ); + +/** + * @} + */ + +/* ------------------------------------------------------- */ +/* Here you should declare the internal struct of */ +/* extended features of LPS25H. See the example of */ +/* LSM6DS3 in lsm6ds3.h */ +/* ------------------------------------------------------- */ + +/** @addtogroup LPS25H_Exported_Variables LPS25H_Exported_Variables + * @{ + */ +/* Pressure sensor driver structure */ +extern PRESSURE_DrvTypeDef LPS25HDrv; +extern PRESSURE_DrvExtTypeDef LPS25HDrv_ext; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LPS25H_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/Release_Notes.html new file mode 100644 index 000000000..7eff65b16 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/Release_Notes.html @@ -0,0 +1,155 @@ + + + + + +Release Notes for STM32 BlueEnergy Library + + + + + +
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Release Notes for LPS25HB component

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Copyright +2015 STMicroelectronics

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Update History

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V1.0.0 +/ 11-February-2015

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+ + + + + + + + + +
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  • First +official release
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+ + +Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

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+ +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + + + + +

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+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.c b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.c new file mode 100644 index 000000000..742ba74c1 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.c @@ -0,0 +1,394 @@ +/** + ****************************************************************************** + * @file lps25hb.c + * @author MEMS Application Team + * @version V1.0.0 + * @date 11-February-2015 + * @brief This file provides a set of functions needed to manage the lps25hb. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "lps25hb.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LPS25HB + * @{ + */ + +static PRESSURE_StatusTypeDef LPS25HB_Init(PRESSURE_InitTypeDef *LPS25HB_Init); +static PRESSURE_StatusTypeDef LPS25HB_ReadID(uint8_t *p_id); +static PRESSURE_StatusTypeDef LPS25HB_RebootCmd(void); +static PRESSURE_StatusTypeDef LPS25HB_GetPressure(float* pfData); +static PRESSURE_StatusTypeDef LPS25HB_GetTemperature(float* pfData); +static PRESSURE_StatusTypeDef LPS25HB_PowerOff(void); +static void LPS25HB_SlaveAddrRemap(uint8_t SA0_Bit_Status); + +/** @defgroup LPS25HB_Private_Variables LPS25HB_Private_Variables + * @{ + */ +PRESSURE_DrvTypeDef LPS25HBDrv = +{ + LPS25HB_Init, + LPS25HB_PowerOff, + LPS25HB_ReadID, + LPS25HB_RebootCmd, + 0, + 0, + 0, + 0, + 0, + LPS25HB_GetPressure, + LPS25HB_GetTemperature, + LPS25HB_SlaveAddrRemap, + NULL +}; + +/* ------------------------------------------------------- */ +/* Here you should declare the variable that implements */ +/* the internal struct of extended features of LPS25HB. */ +/* Then you must update the NULL pointer in the variable */ +/* of the extended features below. */ +/* See the example of LSM6DS3 in lsm6ds3.c */ +/* ------------------------------------------------------- */ + +PRESSURE_DrvExtTypeDef LPS25HBDrv_ext = +{ + PRESSURE_LPS25HB_DIL24_COMPONENT, /* unique ID for LPS25HB in the PRESSURE driver class */ + NULL /* pointer to internal struct of extended features of LPS25HB */ +}; + +uint8_t LPS25HB_SlaveAddress = LPS25HB_ADDRESS_LOW; + +/** + * @} + */ + +static PRESSURE_StatusTypeDef LPS25HB_PowerOn(void); +static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawPressure(int32_t *raw_press); +static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawTemperature(int16_t *raw_data); + +/** @defgroup LPS25HB_Private_Functions LPS25HB_Private_Functions + * @{ + */ + +/** + * @brief Set LPS25HB Initialization + * @param LPS25HB_Init the configuration setting for the LPS25HB + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_Init(PRESSURE_InitTypeDef *LPS25HB_Init) +{ + uint8_t tmp1 = 0x00; + + /* Configure the low level interface ---------------------------------------*/ + if(LPS25HB_IO_Init() != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + if(LPS25HB_PowerOn() != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + if(LPS25HB_IO_Read(&tmp1, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Output Data Rate selection */ + tmp1 &= ~(LPS25HB_ODR_MASK); + tmp1 |= LPS25HB_Init->OutputDataRate; + + /* Interrupt circuit selection */ + tmp1 &= ~(LPS25HB_DIFF_EN_MASK); + tmp1 |= LPS25HB_Init->DiffEnable; + + /* Block Data Update selection */ + tmp1 &= ~(LPS25HB_BDU_MASK); + tmp1 |= LPS25HB_Init->BlockDataUpdate; + + /* Serial Interface Mode selection */ + tmp1 &= ~(LPS25HB_SPI_SIM_MASK); + tmp1 |= LPS25HB_Init->SPIMode; + + if(LPS25HB_IO_Write(&tmp1, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + if(LPS25HB_IO_Read(&tmp1, LPS25HB_SlaveAddress, LPS25HB_RES_CONF_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Serial Interface Mode selection */ + tmp1 &= ~(LPS25HB_P_RES_MASK); + tmp1 |= LPS25HB_Init->PressureResolution; + + /* Serial Interface Mode selection */ + tmp1 &= ~(LPS25HB_T_RES_MASK); + tmp1 |= LPS25HB_Init->TemperatureResolution; + + if(LPS25HB_IO_Write(&tmp1, LPS25HB_SlaveAddress, LPS25HB_RES_CONF_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + LPS25HB_IO_ITConfig(); + + return PRESSURE_OK; +} + +/** + * @brief Read ID address of LPS25HB + * @param ht_id the pointer where the ID of the device is stored + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_ReadID(uint8_t *p_id) +{ + if(!p_id) + { + return PRESSURE_ERROR; + } + + return LPS25HB_IO_Read(p_id, LPS25HB_SlaveAddress, LPS25HB_WHO_AM_I_ADDR, 1); +} + +/** + * @brief Reboot memory content of LPS25HB + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_RebootCmd(void) +{ + uint8_t tmpreg; + + /* Read CTRL_REG5 register */ + if(LPS25HB_IO_Read(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG2_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Enable or Disable the reboot memory */ + tmpreg |= LPS25HB_RESET_MEMORY; + + /* Write value to MEMS CTRL_REG5 regsister */ + if(LPS25HB_IO_Write(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG2_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + return PRESSURE_OK; +} + + +/** + * @brief Read LPS25HB output register, and calculate the raw pressure + * @param raw_press the pressure raw value + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawPressure(int32_t *raw_press) +{ + uint8_t buffer[3], i; + uint32_t tempVal = 0; + + /* Read the register content */ + + if(LPS25HB_IO_Read(buffer, LPS25HB_SlaveAddress, (LPS25HB_PRESS_POUT_XL_ADDR | LPS25HB_I2C_MULTIPLEBYTE_CMD), + 3) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Build the raw data */ + for (i = 0 ; i < 3 ; i++) + tempVal |= (((uint32_t) buffer[i]) << (8 * i)); + + /* convert the 2's complement 24 bit to 2's complement 32 bit */ + if (tempVal & 0x00800000) + tempVal |= 0xFF000000; + + /* return the built value */ + *raw_press = ((int32_t) tempVal); + + return PRESSURE_OK; +} + +/** + * @brief Read LPS25HB output register, and calculate the pressure in mbar + * @param pfData the pressure value in mbar + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_GetPressure(float* pfData) +{ + int32_t raw_press = 0; + + if(LPS25HB_I2C_ReadRawPressure(&raw_press) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + *pfData = (float)raw_press / 4096.0f; + + return PRESSURE_OK; +} + +/** + * @brief Read LPS25HB output register, and calculate the raw temperature + * @param raw_data the temperature raw value + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawTemperature(int16_t *raw_data) +{ + uint8_t buffer[2]; + uint16_t tempVal = 0; + + /* Read the register content */ + if(LPS25HB_IO_Read(buffer, LPS25HB_SlaveAddress, (LPS25HB_TEMP_OUT_L_ADDR | LPS25HB_I2C_MULTIPLEBYTE_CMD), + 2) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Build the raw value */ + tempVal = (((uint16_t)buffer[1]) << 8) + (uint16_t)buffer[0]; + + /* Return it */ + *raw_data = ((int16_t)tempVal); + + return PRESSURE_OK; +} + +/** + * @brief Read LPS25HB output register, and calculate the temperature + * @param pfData the temperature value + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_GetTemperature(float *pfData) +{ + int16_t raw_data; + + if(LPS25HB_I2C_ReadRawTemperature(&raw_data) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + *pfData = (float)((((float)raw_data / 480.0f) + 42.5f)); + + return PRESSURE_OK; +} +/** + * @brief Exit the shutdown mode for LPS25HB + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_PowerOn(void) +{ + uint8_t tmpreg; + + /* Read the register content */ + if(LPS25HB_IO_Read(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Set the power down bit */ + tmpreg |= LPS25HB_MODE_ACTIVE; + + /* Write register */ + if(LPS25HB_IO_Write(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + return PRESSURE_OK; +} + + +/** + * @brief Enter the shutdown mode for LPS25HB + * @retval PRESSURE_OK in case of success, an error code otherwise + */ +static PRESSURE_StatusTypeDef LPS25HB_PowerOff(void) +{ + uint8_t tmpreg; + + /* Read the register content */ + if(LPS25HB_IO_Read(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + /* Reset the power down bit */ + tmpreg &= ~(LPS25HB_MODE_ACTIVE); + + /* Write register */ + if(LPS25HB_IO_Write(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + return PRESSURE_OK; +} + +/** + * @brief Set the slave address according to SA0 bit + * @param SA0_Bit_Status LPS25HB_SA0_LOW or LPS25HB_SA0_HIGH + * @retval None + */ +static void LPS25HB_SlaveAddrRemap(uint8_t SA0_Bit_Status) +{ + LPS25HB_SlaveAddress = (SA0_Bit_Status == LPS25HB_SA0_LOW ? LPS25HB_ADDRESS_LOW : LPS25HB_ADDRESS_HIGH); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.h b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.h new file mode 100644 index 000000000..d600dc37d --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.h @@ -0,0 +1,572 @@ +/** + ****************************************************************************** + * @file lps25hb.h + * @author MEMS Application Team + * @version V1.0.0 + * @date 11-February-2015 + * @brief This file contains definitions for the lps25hb.c + * firmware driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LPS25HB_H +#define __LPS25HB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "pressure.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LPS25HB + * @{ + */ + +/** @defgroup LPS25HB_Exported_Defines LPS25HB_Exported_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif + + +/******************************************************************************/ +/*************************** START REGISTER MAPPING **************************/ +/******************************************************************************/ + + +/** + * @brief Reference pressure (LSB data) + * \code + * Read/write + * Default value: 0x00 + * 7:0 REF7-ODR0: Lower part of the reference pressure that + * is sum to the sensor output pressure. + * \endcode + */ +#define LPS25HB_REF_P_XL_ADDR 0x08 + +/** + * @brief Reference pressure (middle part) + * \code + * Read/write + * Default value: 0x00 + * 7:0 REF15-ODR8: Middle part of the reference pressure that + * is sum to the sensor output pressure. + * \endcode + */ +#define LPS25HB_REF_P_L_ADDR 0x09 + +/** + * @brief Reference pressure (MSB part) + * \code + * Read/write + * Default value: 0x00 + * 7:0 REF15-ODR8: Higher part of the reference pressure that + * is sum to the sensor output pressure. + * \endcode + */ +#define LPS25HB_REF_P_H_ADDR 0x0A + +/** + * @brief Device identifier register. + * \code + * Read + * Default value: 0xBD + * 7:0 This read-only register contains the device identifier that, + for LPS25HB, is set to 0xCA. + * \endcode + */ +#define LPS25HB_WHO_AM_I_ADDR 0x0F + +/** + * @brief Pressure and temperature resolution mode register. + * \code + * Read + * Default value: 0x05 + * [7:4] Reserved + * [3:2] AVGP1-0: select the pressure internal average. + * [1:0] AVGT1-0: select the temperature internal average. + * \endcode + */ +#define LPS25HB_RES_CONF_ADDR 0x10 + +/** + * @brief Pressure sensor control register 1 + * \code + * Read/write + * Default value: 0x00 + * 7 PD: power down control. 0 - disable; 1 - enable + * 6:4 ODR2, ODR1, ODR0: output data rate selection. + * ODR2 | ODR1 | ODR0 | Pressure output data-rate(Hz) | Temperature output data-rate(Hz) + * ---------------------------------------------------------------------------------- + * 0 | 0 | 0 | one shot | one shot + * 0 | 0 | 1 | 1 | 1 + * 0 | 1 | 0 | 7 | 7 + * 0 | 1 | 1 | 12.5 | 12.5 + * 1 | 0 | 0 | 25 | 25 + * 1 | 0 | 1 | Reserved | Reserved + * 1 | 1 | 0 | Reserved | Reserved + * 1 | 1 | 1 | Reserved | Reserved + * + * 3 DIFF_EN: Interrupt circuit. 0 - disable; 1 - enable + * 2 BDU: block data update. 0 - disable; 1 - enable + * 1 DELTA_EN: delta pressure. 0 - disable; 1 - enable + * 1 RESET_AZ: reset AutoZero. 0 - disable; 1 - enable ///////ALE REVIEW + * 0 SIM: SPI Serial Interface Mode selection. 0 - SPI 4-wire; 1 - SPI 3-wire ///////ALE REVIEW + * \endcode + */ +#define LPS25HB_CTRL_REG1_ADDR 0x20 + +/** + * @brief Pressure sensor control register 2 + * \code + * Read/write + * Default value: 0x00 + * 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content + * 6 FIFO_EN: FIFO. 0: disable; 1: enable + * 5 WTM_EN: FIFO Watermark level use. 0: disable; 1: enable + * 4:3 Reserved. keep these bits at 0 + * 2 SWRESET: Software reset. 0: normal mode; 1: SW reset. + * 1 AUTO_ZERO: Autozero enable. 0: normal mode; 1: autozero enable. + * 0 ONE_SHOT: One shot enable. 0: waiting for start of conversion; 1: start for a new dataset + * \endcode + */ +#define LPS25HB_CTRL_REG2_ADDR 0x21 + +/** + * @brief Pressure sensor control register 3 + * \code + * Read/write + * Default value: 0x00 + * 7 INT_H_L: Interrupt. 0:active high; 1: active low. + * 6 PP_OD: Push-Pull/OpenDrain selection on interrupt pads. 0: Push-pull; 1: open drain. + * 5 Reserved + * 4:3 INT2_S2, INT2_S1: INT2 output signal selection control bits. // TO DO + * 1:0 INT1_S2, INT1_S1: data signal on INT1 pad control bits. + * INT1(2)_S2 | INT1(2)_S1 | INT1(2) pin + * ------------------------------------------------------ + * 0 | 0 | Data signal + * 0 | 1 | Pressure high (P_high) + * 1 | 0 | Pressure low (P_low) + * 1 | 1 | P_low OR P_high + + + * \endcode + */ +#define LPS25HB_CTRL_REG3_ADDR 0x22 + +/** + * @brief Pressure sensor control register 4 + * \code + * Read/write + * Default value: 0x00 + * 7 P2_EMPTY: Empty Signal on INT2 pin. + * 6 P2_WTM: Watermark Signal on INT2 pin. + * 5 P2_Overrun:Overrun Signal on INT2 pin. + * 4 P2_DRDY: Data Ready Signal on INT2 pin. + * 3 P1_EMPTY: Empty Signal on INT1 pin. + * 2 P1_WTM: Watermark Signal on INT1 pin. + * 1 P1_Overrunn:Overrun Signal on INT1 pin. + * 0 P1_DRDY: Data Ready Signal on INT1 pin. + * \endcode + */ +#define LPS25HB_CTRL_REG4_ADDR 0x23 + +/** + * @brief Interrupt configuration Register + * \code + * Read/write + * Default value: 0x00. + * 7:3 Reserved. + * 2 LIR: Latch Interrupt request into INT_SOURCE register. 0 - disable; 1 - enable + * 1 PL_E: Enable interrupt generation on differential pressure low event. 0 - disable; 1 - enable + * 0 PH_E: Enable interrupt generation on differential pressure high event. 0 - disable; 1 - enable + * \endcode + */ +#define LPS25HB_INT_CFG_REG_ADDR 0x24 + +/** + * @brief Interrupt source Register + * \code + * Read + * Default value: 0x00. + * 7:3 0. + * 2 IA: Interrupt Active.0: no interrupt has been generated; 1: one or more interrupt events have been generated. + * 1 PL: Differential pressure Low. 0: no interrupt has been generated; 1: Low differential pressure event has occurred. + * 0 PH: Differential pressure High. 0: no interrupt has been generated; 1: High differential pressure event has occurred. + * \endcode + */ +#define LPS25HB_INT_SOURCE_REG_ADDR 0x25 + +/** + * @brief Threshold pressure (LSB) + * \code + * Read + * Default value: 0x00. + * 7:0 THS7-THS0: Low part of threshold value for pressure interrupt + * generation. The complete threshold value is given by THS_P_H & THS_P_L and is + * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. + * \endcode + */ +#define LPS25HB_THS_P_LOW_REG_ADDR 0x30 + +/** + * @brief Threshold pressure (MSB) + * \code + * Read + * Default value: 0x00. + * 7:0 THS15-THS8: High part of threshold value for pressure interrupt + * generation. The complete threshold value is given by THS_P_H & THS_P_L and is + * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. + * \endcode + */ +#define LPS25HB_THS_P_HIGH_REG_ADDR 0x31 + +/** + * @brief Status Register + * \code + * Read + * Default value: 0x00 + * 7:6 0 + * 5 P_OR: Pressure data overrun. 0: no overrun has occurred; 1: new data for pressure has overwritten the previous one. + * 4 T_OR: Temperature data overrun. 0: no overrun has occurred; 1: a new data for temperature has overwritten the previous one. + * 3:2 0 + * 1 P_DA: Pressure data available. 0: new data for pressure is not yet available; 1: new data for pressure is available. + * 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. + * \endcode + */ +#define LPS25HB_STATUS_REG_ADDR 0x27 + +/** + * @brief Pressure data (LSB). + * \code + * Read + * Default value: 0x00. + * POUT7 - POUT0: Pressure data LSB (2's complement). + * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & + * PRESS_OUT_XL)[dec]/4096. + * \endcode + */ +#define LPS25HB_PRESS_POUT_XL_ADDR 0x28 + +/** + * @brief Pressure data (Middle part). + * \code + * Read + * Default value: 0x80. + * POUT15 - POUT8: Pressure data middle part (2's complement). + * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & + * PRESS_OUT_XL)[dec]/4096. + * \endcode + */ +#define LPS25HB_PRESS_OUT_L_ADDR 0x29 + +/** + * @brief Pressure data (MSB). + * \code + * Read + * Default value: 0x2F. + * POUT23 - POUT16: Pressure data MSB (2's complement). + * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & + * PRESS_OUT_XL)[dec]/4096. + * \endcode + */ +#define LPS25HB_PRESS_OUT_H_ADDR 0x2A + +/** + * @brief Temperature data (LSB). + * \code + * Read + * Default value: 0x00. + * TOUT7 - TOUT0: temperature data LSB. + * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. + * \endcode + */ +#define LPS25HB_TEMP_OUT_L_ADDR 0x2B + +/** + * @brief Temperature data (MSB). + * \code + * Read + * Default value: 0x00. + * TOUT15 - TOUT8: temperature data MSB. + * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. + * \endcode + */ +#define LPS25HB_TEMP_OUT_H_ADDR 0x2C + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * 7:5 F_MODE2, F_MODE1, F_MODE0: FIFO mode selection. + * FM2 | FM1 | FM0 | FIFO MODE + * --------------------------------------------------- + * 0 | 0 | 0 | BYPASS MODE + * 0 | 0 | 1 | FIFO MODE. Stops collecting data when full + * 0 | 1 | 0 | STREAM MODE: Keep the newest measurements in the FIFO + * 0 | 1 | 1 | STREAM MODE until trigger deasserted, then change to FIFO MODE + * 1 | 0 | 0 | BYPASS MODE until trigger deasserted, then STREAM MODE + * 1 | 0 | 1 | Reserved + * 1 | 1 | 0 | FIFO_MEAN MODE: Fifo is used to generate a running average filtered pressure + * 1 | 1 | 1 | BYPASS mode until trigger deasserted, then FIFO MODE + * + * 4:0 FIFO Mean Mode Sample size + * WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | Sample Size + * ---------------------------------------------------------------------------------- + * 0 | 0 | 0 | 0 | 1 | 2 + * 0 | 0 | 0 | 1 | 1 | 4 + * 0 | 0 | 1 | 1 | 1 | 8 + * 0 | 1 | 1 | 1 | 1 | 16 + * 1 | 1 | 1 | 1 | 1 | 32 + * other values operation not guaranteed + * \endcode + */ +#define LPS25HB_CTRL_FIFO_ADDR 0x2E + +/** + * @brief FIFO Status register + * \code + * Read/write + * Default value: 0x00 + * 7 WTM_FIFO: Watermark status. 0:FIFO filling is lower than watermark level; 1: FIFO is equal or higher than watermark level. + * 6 FULL_FIFO: Overrun bit status. 0 - FIFO not full; 1 -FIFO is full. + * 5 EMPTY_FIFO: Empty FIFO bit. 0 - FIFO not empty; 1 -FIFO is empty. + * 4:0 DIFF_POINT4...0: FIFOsStored data level. + * \endcode + */ +#define LPS25HB_STATUS_FIFO_ADDR 0x2F + +/** + * @brief Pressure offset register + * \code + * Read/write + * Default value: 0x00 + * 7:0 RPDS15...8:Pressure Offset for 1 point calibration after soldering. + * \endcode + */ +#define LPS25HB_RPDS_TRIM_L_ADDR 0x39 + +/** + * @brief Pressure offset register + * \code + * Read/write + * Default value: 0x00 + * 7:0 RPDS23...16:Pressure Offset for 1 point calibration after soldering. + * \endcode + */ +#define LPS25HB_RPDS_TRIM_H_ADDR 0x3A + +/******************************************************************************/ +/**************************** END REGISTER MAPPING ***************************/ +/******************************************************************************/ + +/** + * @brief Multiple Byte. Mask for enabling multiple byte read/write command. + */ +#define LPS25HB_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) + +/** + * @brief Device Address + */ +#define LPS25HB_ADDRESS_LOW 0xB8 +#define LPS25HB_ADDRESS_HIGH 0xBA + + +/** + * @brief Device Identifier. Default value of the WHO_AM_I register. + */ +#define I_AM_LPS25HB ((uint8_t)0xBD) + +/** @defgroup LPS25HB_Power_Mode_Selection_CTRL_REG1 LPS25HB_Power_Mode_Selection_CTRL_REG1 + * @{ + */ +#define LPS25HB_MODE_POWERDOWN ((uint8_t)0x00) +#define LPS25HB_MODE_ACTIVE ((uint8_t)0x80) + +#define LPS25HB_MODE_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup LPS25HB_Output_Data_Rate_Selection_CTRL_REG1 LPS25HB_Output_Data_Rate_Selection_CTRL_REG1 + * @{ + */ +#define LPS25HB_ODR_ONE_SHOT ((uint8_t)0x00) /*!< Output Data Rate: P - one shot, T - one shot */ +#define LPS25HB_ODR_1Hz ((uint8_t)0x10) /*!< Output Data Rate: P - 1Hz, T - 1Hz */ +#define LPS25HB_ODR_7Hz ((uint8_t)0x20) /*!< Output Data Rate: P - 7Hz, T - 7Hz */ +#define LPS25HB_ODR_12_5Hz ((uint8_t)0x30) /*!< Output Data Rate: P - 12.5Hz, T - 12.5Hz */ +#define LPS25HB_ODR_25Hz ((uint8_t)0x40) /*!< Output Data Rate: P - 25Hz, T - 25Hz */ + +#define LPS25HB_ODR_MASK ((uint8_t)0x70) +/** + * @} + */ + +/** @defgroup LPS25HB_Interrupt_Circuit_Enable_CTRL_REG1 LPS25HB_Interrupt_Circuit_Enable_CTRL_REG1 + * @{ + */ +#define LPS25HB_DIFF_DISABLE ((uint8_t)0x00) /*!< interrupt circuit enabled */ +#define LPS25HB_DIFF_ENABLE ((uint8_t)0x08) /*!< interrupt generation disabled */ + +#define LPS25HB_DIFF_EN_MASK ((uint8_t)0x08) +/** + * @} + */ + +/** @defgroup LPS25HB_Block_Data_Update_CTRL_REG1 LPS25HB_Block_Data_Update_CTRL_REG1 + * @{ + */ +#define LPS25HB_BDU_CONT ((uint8_t)0x00) /*!< continuous update */ +#define LPS25HB_BDU_READ ((uint8_t)0x04) /*!< output registers not updated until MSB and LSB reading */ + +#define LPS25HB_BDU_MASK ((uint8_t)0x04) +/** + * @} + */ + +/** @defgroup LPS25HB_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 LPS25HB_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 + * @{ + */ +#define LPS25HB_SPI_SIM_4W ((uint8_t)0x00) /*!< 4-wire interface */ +#define LPS25HB_SPI_SIM_3W ((uint8_t)0x01) /*!< 3-wire interface */ + +#define LPS25HB_SPI_SIM_MASK ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup LPS25HB_Refresh_Registers_Flash_Memory_CTRL_REG2 LPS25HB_Refresh_Registers_Flash_Memory_CTRL_REG2 + * @{ + */ +#define LPS25HB_NORMAL_MODE ((uint8_t)0x00) +#define LPS25HB_RESET_MEMORY ((uint8_t)0x80) + +#define LPS25HB_RESET_MEMORY_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup LPS25HB_Pressure_Resolution_Selection_RES_CONF LPS25HB_Pressure_Resolution_Selection_RES_CONF + * @{ + */ +#define LPS25HB_P_RES_AVG_8 ((uint8_t)0x00) +#define LPS25HB_P_RES_AVG_32 ((uint8_t)0x01) +#define LPS25HB_P_RES_AVG_128 ((uint8_t)0x02) +#define LPS25HB_P_RES_AVG_512 ((uint8_t)0x03) + +#define LPS25HB_P_RES_MASK ((uint8_t)0x03) +/** + * @} + */ + +/** @defgroup LPS25HB_Temperature_Resolution_Selection_RES_CONF LPS25HB_Temperature_Resolution_Selection_RES_CONF + * @{ + */ +#define LPS25HB_T_RES_AVG_8 ((uint8_t)0x00) +#define LPS25HB_T_RES_AVG_16 ((uint8_t)0x04) +#define LPS25HB_T_RES_AVG_32 ((uint8_t)0x08) +#define LPS25HB_T_RES_AVG_64 ((uint8_t)0x0C) + +#define LPS25HB_T_RES_MASK ((uint8_t)0x0C) +/** + * @} + */ + +#define LPS25HB_SA0_LOW ((uint8_t)0x00) +#define LPS25HB_SA0_HIGH ((uint8_t)0x01) + +/** + * @} + */ + +/** @defgroup LPS25HB_Imported_Functions LPS25HB_Imported_Functions + * @{ + */ +/* Pressure sensor IO functions */ +extern PRESSURE_StatusTypeDef LPS25HB_IO_Init(void); +extern PRESSURE_StatusTypeDef LPS25HB_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToWrite); +extern PRESSURE_StatusTypeDef LPS25HB_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToRead); +extern void LPS25HB_IO_ITConfig( void ); + +/** + * @} + */ + +/* ------------------------------------------------------- */ +/* Here you should declare the internal struct of */ +/* extended features of LPS25HB. See the example of */ +/* LSM6DS3 in lsm6ds3.h */ +/* ------------------------------------------------------- */ + +/** @addtogroup LPS25HB_Exported_Variables LPS25HB_Exported_Variables + * @{ + */ +/* Pressure sensor driver structure */ +extern PRESSURE_DrvTypeDef LPS25HBDrv; +extern PRESSURE_DrvExtTypeDef LPS25HBDrv_ext; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LPS25HB_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/Release_Notes.html new file mode 100644 index 000000000..3e823ebb6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/Release_Notes.html @@ -0,0 +1,211 @@ + + + + + +Release Notes for STM32 BlueEnergy Library + + + + + +
+


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Release Notes for LSM6DS0 component

+

Copyright +2015 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+ + +

V1.3.0 +/ 28-May-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add output data rate and full scale settings APIs for the Component +
    • +
  • Add LSM6DS0_X_GetAxes and LSM6DS0_G_GetAxes APIs +
    • +
+ +

V1.2.0 +/ 11-February-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add extended features support for the Component +
    • +
+ +

V1.1.0 +/ 12-December-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • Add error control in the Component API +
    • +
+ +

V1.0.0 +/ 10-September-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • First +official release
    • +
+ + +

License
+

+ + +Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

+ + +
+ http://www.st.com/software_license_agreement_liberty_v2


+ +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + + + + +

+ +
+
+

For +complete documentation on STM32 STM BlueNRG +visit www.st.com/BlueNRG

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.c b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.c new file mode 100644 index 000000000..5d9f8f541 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.c @@ -0,0 +1,795 @@ +/** + ****************************************************************************** + * @file lsm6ds0.c + * @author MEMS Application Team + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file provides a set of functions needed to manage the lsm6ds0. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "lsm6ds0.h" +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LSM6DS0 + * @{ + */ + +static IMU_6AXES_StatusTypeDef LSM6DS0_Init(IMU_6AXES_InitTypeDef *LSM6DS0_Init); +static IMU_6AXES_StatusTypeDef LSM6DS0_Read_XG_ID(uint8_t *xg_id); +static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxes(int32_t *pData); +static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxesRaw(int16_t *pData); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxes(int32_t *pData); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxesRaw(int16_t *pData); +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_ODR( float *odr ); +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_ODR( float odr ); +static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetSensitivity( float *pfData ); +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_FS( float *fullScale ); +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_FS( float fullScale ); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_ODR( float *odr ); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_ODR( float odr ); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetSensitivity( float *pfData ); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_FS( float *fullScale ); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_FS( float fullScale ); + +/** @defgroup LSM6DS0_Private_Variables LSM6DS0_Private_Variables + * @{ + */ + +IMU_6AXES_DrvTypeDef LSM6DS0Drv = +{ + LSM6DS0_Init, + LSM6DS0_Read_XG_ID, + LSM6DS0_X_GetAxes, + LSM6DS0_X_GetAxesRaw, + LSM6DS0_G_GetAxes, + LSM6DS0_G_GetAxesRaw, + LSM6DS0_X_Get_ODR, + LSM6DS0_X_Set_ODR, + LSM6DS0_X_GetSensitivity, + LSM6DS0_X_Get_FS, + LSM6DS0_X_Set_FS, + LSM6DS0_G_Get_ODR, + LSM6DS0_G_Set_ODR, + LSM6DS0_G_GetSensitivity, + LSM6DS0_G_Get_FS, + LSM6DS0_G_Set_FS, + NULL +}; + +/* ------------------------------------------------------- */ +/* Here you should declare the variable that implements */ +/* the internal struct of extended features of LSM6DS0. */ +/* Then you must update the NULL pointer in the variable */ +/* of the extended features below. */ +/* See the example of LSM6DS3 in lsm6ds3.c */ +/* ------------------------------------------------------- */ + +IMU_6AXES_DrvExtTypeDef LSM6DS0Drv_ext = +{ + IMU_6AXES_LSM6DS0_COMPONENT, /* unique ID for LSM6DS0 in the IMU 6-axes driver class */ + NULL /* pointer to internal struct of extended features of LSM6DS0 */ +}; + +/** + * @} + */ + +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); + +/** @defgroup LSM6DS0_Private_Functions LSM6DS0_Private_Functions + * @{ + */ + +/** + * @brief Set LSM6DS0 Initialization + * @param LSM6DS0_Init the configuration setting for the LSM6DS0 + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_Init(IMU_6AXES_InitTypeDef *LSM6DS0_Init) +{ + /* Configure the low level interface ---------------------------------------*/ + if(LSM6DS0_IO_Init() != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /******* Gyroscope init *******/ + + if(LSM6DS0_G_Set_ODR( LSM6DS0_Init->G_OutputDataRate ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS0_G_Set_FS( LSM6DS0_Init->G_FullScale ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS0_G_Set_Axes_Status(LSM6DS0_Init->G_X_Axis, LSM6DS0_Init->G_Y_Axis, LSM6DS0_Init->G_Z_Axis) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /******************************/ + + /***** Accelerometer init *****/ + + if(LSM6DS0_X_Set_ODR( LSM6DS0_Init->X_OutputDataRate ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS0_X_Set_FS( LSM6DS0_Init->X_FullScale ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS0_X_Set_Axes_Status(LSM6DS0_Init->X_X_Axis, LSM6DS0_Init->X_Y_Axis, LSM6DS0_Init->X_Z_Axis) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Configure interrupt lines */ + LSM6DS0_IO_ITConfig(); + + return IMU_6AXES_OK; + + /******************************/ +} + + +/** + * @brief Read ID of LSM6DS0 Accelerometer and Gyroscope + * @param xg_id the pointer where the ID of the device is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_Read_XG_ID(uint8_t *xg_id) +{ + if(!xg_id) + { + return IMU_6AXES_ERROR; + } + + return LSM6DS0_IO_Read(xg_id, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_WHO_AM_I_ADDR, 1); +} + + +/** + * @brief Read raw data from LSM6DS0 Accelerometer output register + * @param pData the pointer where the accelerometer raw data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxesRaw(int16_t *pData) +{ + uint8_t tempReg[2] = {0, 0}; + + if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_X_L_XL | LSM6DS0_I2C_MULTIPLEBYTE_CMD), + 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Y_L_XL | LSM6DS0_I2C_MULTIPLEBYTE_CMD), + 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Z_L_XL | LSM6DS0_I2C_MULTIPLEBYTE_CMD), + 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + return IMU_6AXES_OK; +} + + +/** + * @brief Read data from LSM6DS0 Accelerometer and calculate linear acceleration in mg + * @param pData the pointer where the accelerometer data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxes(int32_t *pData) +{ + int16_t pDataRaw[3]; + float sensitivity = 0; + + if(LSM6DS0_X_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS0_X_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = (int32_t)(pDataRaw[0] * sensitivity); + pData[1] = (int32_t)(pDataRaw[1] * sensitivity); + pData[2] = (int32_t)(pDataRaw[2] * sensitivity); + + return IMU_6AXES_OK; +} + + +/** + * @brief Read raw data from LSM6DS0 Gyroscope output register + * @param pData the pointer where the gyroscope raw data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxesRaw(int16_t *pData) +{ + uint8_t tempReg[2] = {0, 0}; + + if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_X_L_G | LSM6DS0_I2C_MULTIPLEBYTE_CMD), + 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Y_L_G | LSM6DS0_I2C_MULTIPLEBYTE_CMD), + 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Z_L_G | LSM6DS0_I2C_MULTIPLEBYTE_CMD), + 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + return IMU_6AXES_OK; +} + +/** + * @brief Set the status of the axes for accelerometer + * @param enableX the status of the x axis to be set + * @param enableY the status of the y axis to be set + * @param enableZ the status of the z axis to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) +{ + uint8_t tmp1 = 0x00; + uint8_t eX = 0x00; + uint8_t eY = 0x00; + uint8_t eZ = 0x00; + + eX = ( enableX == 0 ) ? LSM6DS0_XL_XEN_DISABLE : LSM6DS0_XL_XEN_ENABLE; + eY = ( enableY == 0 ) ? LSM6DS0_XL_YEN_DISABLE : LSM6DS0_XL_YEN_ENABLE; + eZ = ( enableZ == 0 ) ? LSM6DS0_XL_ZEN_DISABLE : LSM6DS0_XL_ZEN_ENABLE; + + if(LSM6DS0_IO_Read(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG5_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Enable X axis selection */ + tmp1 &= ~(LSM6DS0_XL_XEN_MASK); + tmp1 |= eX; + + /* Enable Y axis selection */ + tmp1 &= ~(LSM6DS0_XL_YEN_MASK); + tmp1 |= eY; + + /* Enable Z axis selection */ + tmp1 &= ~(LSM6DS0_XL_ZEN_MASK); + tmp1 |= eZ; + + if(LSM6DS0_IO_Write(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG5_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Set the status of the axes for gyroscope + * @param enableX the status of the x axis to be set + * @param enableY the status of the y axis to be set + * @param enableZ the status of the z axis to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) +{ + uint8_t tmp1 = 0x00; + uint8_t eX = 0x00; + uint8_t eY = 0x00; + uint8_t eZ = 0x00; + + eX = ( enableX == 0 ) ? LSM6DS0_G_XEN_DISABLE : LSM6DS0_G_XEN_ENABLE; + eY = ( enableY == 0 ) ? LSM6DS0_G_YEN_DISABLE : LSM6DS0_G_YEN_ENABLE; + eZ = ( enableZ == 0 ) ? LSM6DS0_G_ZEN_DISABLE : LSM6DS0_G_ZEN_ENABLE; + + if(LSM6DS0_IO_Read(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG4, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Enable X axis selection */ + tmp1 &= ~(LSM6DS0_G_XEN_MASK); + tmp1 |= eX; + + /* Enable Y axis selection */ + tmp1 &= ~(LSM6DS0_G_YEN_MASK); + tmp1 |= eY; + + /* Enable Z axis selection */ + tmp1 &= ~(LSM6DS0_G_ZEN_MASK); + tmp1 |= eZ; + + if(LSM6DS0_IO_Write(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG4, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + + +/** + * @brief Read data from LSM6DS0 Gyroscope and calculate angular rate in mdps + * @param pData the pointer where the gyroscope data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxes(int32_t *pData) +{ + int16_t pDataRaw[3]; + float sensitivity = 0; + + if(LSM6DS0_G_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS0_G_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = (int32_t)(pDataRaw[0] * sensitivity); + pData[1] = (int32_t)(pDataRaw[1] * sensitivity); + pData[2] = (int32_t)(pDataRaw[2] * sensitivity); + + return IMU_6AXES_OK; +} + +/** + * @brief Read Accelero Output Data Rate + * @param odr the pointer where the accelerometer output data rate is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_ODR( float *odr ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS0_XL_ODR_MASK; + + switch( tempReg ) + { + case LSM6DS0_XL_ODR_PD: + *odr = 0.0f; + break; + case LSM6DS0_XL_ODR_10HZ: + *odr = 10.0f; + break; + case LSM6DS0_XL_ODR_50HZ: + *odr = 50.0f; + break; + case LSM6DS0_XL_ODR_119HZ: + *odr = 119.0f; + break; + case LSM6DS0_XL_ODR_238HZ: + *odr = 238.0f; + break; + case LSM6DS0_XL_ODR_476HZ: + *odr = 476.0f; + break; + case LSM6DS0_XL_ODR_952HZ: + *odr = 952.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Accelero Output Data Rate + * @param odr the accelerometer output data rate to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_ODR( float odr ) +{ + uint8_t new_odr = 0x00; + uint8_t tempReg = 0x00; + + new_odr = ( odr <= 0.0f ) ? LSM6DS0_XL_ODR_PD /* Power Down */ + : ( odr <= 10.0f ) ? LSM6DS0_XL_ODR_10HZ + : ( odr <= 50.0f ) ? LSM6DS0_XL_ODR_50HZ + : ( odr <= 119.0f ) ? LSM6DS0_XL_ODR_119HZ + : ( odr <= 238.0f ) ? LSM6DS0_XL_ODR_238HZ + : ( odr <= 476.0f ) ? LSM6DS0_XL_ODR_476HZ + : LSM6DS0_XL_ODR_952HZ; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS0_XL_ODR_MASK); + tempReg |= new_odr; + + if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Accelero Sensitivity + * @param pfData the pointer where the accelerometer sensitivity is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetSensitivity( float *pfData ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS0_XL_FS_MASK; + + switch( tempReg ) + { + case LSM6DS0_XL_FS_2G: + *pfData = 0.061f; + break; + case LSM6DS0_XL_FS_4G: + *pfData = 0.122f; + break; + case LSM6DS0_XL_FS_8G: + *pfData = 0.244f; + break; + case LSM6DS0_XL_FS_16G: + *pfData = 0.732f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Accelero Full Scale + * @param fullScale the pointer where the accelerometer full scale is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_FS( float *fullScale ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS0_XL_FS_MASK; + + switch( tempReg ) + { + case LSM6DS0_XL_FS_2G: + *fullScale = 2.0f; + break; + case LSM6DS0_XL_FS_4G: + *fullScale = 4.0f; + break; + case LSM6DS0_XL_FS_8G: + *fullScale = 8.0f; + break; + case LSM6DS0_XL_FS_16G: + *fullScale = 16.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Accelero Full Scale + * @param fullScale the accelerometer full scale to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_FS( float fullScale ) +{ + uint8_t new_fs = 0x00; + uint8_t tempReg = 0x00; + + new_fs = ( fullScale <= 2.0f ) ? LSM6DS0_XL_FS_2G + : ( fullScale <= 4.0f ) ? LSM6DS0_XL_FS_4G + : ( fullScale <= 8.0f ) ? LSM6DS0_XL_FS_8G + : LSM6DS0_XL_FS_16G; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS0_XL_FS_MASK); + tempReg |= new_fs; + + if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Gyro Output Data Rate + * @param odr the pointer where the gyroscope output data rate is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_ODR( float *odr ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS0_G_ODR_MASK; + + switch( tempReg ) + { + case LSM6DS0_G_ODR_PD: + *odr = 0.0f; + break; + case LSM6DS0_G_ODR_14_9HZ: + *odr = 14.9f; + break; + case LSM6DS0_G_ODR_59_5HZ: + *odr = 59.5f; + break; + case LSM6DS0_G_ODR_119HZ: + *odr = 119.0f; + break; + case LSM6DS0_G_ODR_238HZ: + *odr = 238.0f; + break; + case LSM6DS0_G_ODR_476HZ: + *odr = 476.0f; + break; + case LSM6DS0_G_ODR_952HZ: + *odr = 952.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Gyro Output Data Rate + * @param odr the gyroscope output data rate to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_ODR( float odr ) +{ + uint8_t new_odr = 0x00; + uint8_t tempReg = 0x00; + + new_odr = ( odr <= 0.0f ) ? LSM6DS0_G_ODR_PD /* Power Down */ + : ( odr <= 14.9f ) ? LSM6DS0_G_ODR_14_9HZ + : ( odr <= 59.5f ) ? LSM6DS0_G_ODR_59_5HZ + : ( odr <= 119.0f ) ? LSM6DS0_G_ODR_119HZ + : ( odr <= 238.0f ) ? LSM6DS0_G_ODR_238HZ + : ( odr <= 476.0f ) ? LSM6DS0_G_ODR_476HZ + : LSM6DS0_G_ODR_952HZ; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS0_G_ODR_MASK); + tempReg |= new_odr; + + if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Gyro Sensitivity + * @param pfData the pointer where the gyroscope sensitivity is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetSensitivity( float *pfData ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS0_G_FS_MASK; + + switch( tempReg ) + { + case LSM6DS0_G_FS_245: + *pfData = 8.75f; + break; + case LSM6DS0_G_FS_500: + *pfData = 17.50f; + break; + case LSM6DS0_G_FS_2000: + *pfData = 70.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Gyro Full Scale + * @param fullScale the pointer where the gyroscope full scale is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_FS( float *fullScale ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS0_G_FS_MASK; + + switch( tempReg ) + { + case LSM6DS0_G_FS_245: + *fullScale = 245.0f; + break; + case LSM6DS0_G_FS_500: + *fullScale = 500.0f; + break; + case LSM6DS0_G_FS_2000: + *fullScale = 2000.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Gyro Full Scale + * @param fullScale the gyroscope full scale to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_FS( float fullScale ) +{ + uint8_t new_fs = 0x00; + uint8_t tempReg = 0x00; + + new_fs = ( fullScale <= 245.0f ) ? LSM6DS0_G_FS_245 + : ( fullScale <= 500.0f ) ? LSM6DS0_G_FS_500 + : LSM6DS0_G_FS_2000; + + if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS0_G_FS_MASK); + tempReg |= new_fs; + + if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.h b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.h new file mode 100644 index 000000000..a8600642d --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.h @@ -0,0 +1,602 @@ +/** + ****************************************************************************** + * @file lsm6ds0.h + * @author MEMS Application Team + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file contains definitions for the lsm6ds0.c + * firmware driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LSM6DS0_H +#define __LSM6DS0_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "imu_6axes.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LSM6DS0 + * @{ + */ + +/** @defgroup LSM6DS0_Exported_Defines LSM6DS0_Exported_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif + + +/******************************************************************************/ +/*********** START ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ +/******************************************************************************/ + + +/***************************************** COMMON REGISTERS ********************************************/ + +/** + * @brief Interrupt config register + * \code + * Read/write + * Default value: 0x00 + * [7] INT_IG_G: Gyroscope interrupt enable on INT pin + * [6] INT_IG_XL: Accelerometer interrupt generator on INT pin + * [5] INT_FSS5: FSS5 interrupt enable on INT pin + * [4] INT_OVR: Overrun interrupt on INT pin + * [3] INT_FTH: Gyroscope interrupt enable on INT pin + * [2] INT_BOOT: Accelerometer interrupt generator on INT pin + * [1] INT_DRDY_G: FSS5 interrupt enable on INT pin + * [0] INT_DRDY_XL: Overrun interrupt on INT pin + * \endcode + */ +#define LSM6DS0_XG_INT_CTRL 0x0C + + +/** + * @brief Device identifier register. + * \code + * Read + * Default value: + * [7:0] This read-only register contains the device identifier + * \endcode +*/ +#define LSM6DS0_XG_WHO_AM_I_ADDR 0x0F + + +/** + * @brief Control Register 4 + * \code + * Read/write + * Default value: 0x38 + * [5] Zen_G: Gyroscope’s Z-axis output enable + * [4] Yen_G: Gyroscope’s Y-axis output enable + * [3] Xen_G: Gyroscope’s X-axis output enable + * \endcode +*/ +#define LSM6DS0_XG_CTRL_REG4 0x1E + + +/** + * @brief Control Register 10 + * \code + * Read/write + * Default value: 0x00 + * [2] ST_G: Gyro selftest disable (0) / enable (1) + * [0] ST_XL: Accel selftest disable (0) / enable (1) + * \endcode +*/ +#define LSM6DS0_XG_CTRL_REG10 0x24 + + +/***************************************** GYROSCOPE REGISTERS ********************************************/ + +/** + * @brief Angular rate sensor Control Register 1 + * \code + * Read/write + * Default value: 0x00 + * [7:5] ODR_G2-0: Gyroscope output data rate selection + * [4:3] FS_G1-0: Gyroscope full-scale selection + * [2] This bit must be set to ‘0’ for the correct operation of the device + * [1:0] BW_G1-0: Gyroscope bandwidth selection + * \endcode + */ +#define LSM6DS0_XG_CTRL_REG1_G 0x10 + + +/** + * @brief Gyroscope data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_X_L_G 0x18 + + +/** + * @brief Gyroscope data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_X_H_G 0x19 + + +/** + * @brief Gyroscope data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Y_L_G 0x1A + + +/** + * @brief Gyroscope data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Y_H_G 0x1B + + +/** + * @brief Gyroscope data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Z_L_G 0x1C + + +/** + * @brief Gyroscope data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Z_H_G 0x1D + + + +/*************************************** ACCELEROMETER REGISTERS *******************************************/ + +/** + * @brief Linear acceleration sensor Control Register 6 + * \code + * Read/write + * Default value: 0x00 + * [7:5] ODR_XL2-0: Accelerometer Output data rate and power mode selection + * [4:3] FS1_XL-FS0_XL: Accelerometer full-scale selection + * [2] BW_SCAL_ODR: Bandwidth selection + * [1:0] BW_XL1-0: Anti-aliasing filter bandwidth selection + * \endcode + */ +#define LSM6DS0_XG_CTRL_REG6_XL 0x20 + + +/** + * @brief Linear acceleration sensor Control Register 5 + * \code + * Read/write + * Default value: 0x38 + * [7:6] DEC1-0: Decimation of acceleration data on OUT REG and FIFO + * [5] Zen_XL: Accelerometer’s Z-axis output enable + * [4] Yen_XL: Accelerometer’s Y-axis output enable + * [3] Xen_XL: Accelerometer’s X-axis output enable + * [2:0] These bits must be set to ‘0’ for the correct operation of the device + * \endcode + */ +#define LSM6DS0_XG_CTRL_REG5_XL 0x1F + + +/** + * @brief Accelerometer data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_X_L_XL 0x28 + + +/** + * @brief Accelerometer data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_X_H_XL 0x29 + + +/** + * @brief Accelerometer data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Y_L_XL 0x2A + + +/** + * @brief Accelerometer data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Y_H_XL 0x2B + + +/** + * @brief Accelerometer data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Z_L_XL 0x2C + + +/** + * @brief Accelerometer data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS0_XG_OUT_Z_H_XL 0x2D + +/******************************************************************************/ +/************* END ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ +/******************************************************************************/ + +/** + * @brief Multiple Byte. Mask for enabling multiple byte read/write command. + */ +#define LSM6DS0_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) + +/** +* @brief Device Address +*/ +#define LSM6DS0_ADDRESS_LOW 0xD4 // SAD[0] = 0 +#define LSM6DS0_ADDRESS_HIGH 0xD6 // SAD[0] = 1 +#define LSM6DS0_XG_MEMS_ADDRESS LSM6DS0_ADDRESS_HIGH // SAD[0] = 1 + +/** + * @brief Device Identifier. Default value of the WHO_AM_I register. + */ +#define I_AM_LSM6DS0_XG ((uint8_t)0x68) + + + +/************************************** GYROSCOPE REGISTERS VALUE *******************************************/ + + +/** @defgroup LSM6DS0_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G LSM6DS0_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G + * @{ + */ +#define LSM6DS0_G_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ +#define LSM6DS0_G_ODR_14_9HZ ((uint8_t)0x20) /*!< Output Data Rate: 14.9 Hz, cutoff 5Hz */ +#define LSM6DS0_G_ODR_59_5HZ ((uint8_t)0x40) /*!< Output Data Rate: 59.5 Hz, cutoff 19Hz */ +#define LSM6DS0_G_ODR_119HZ ((uint8_t)0x60) /*!< Output Data Rate: 119 Hz, cutoff 38Hz*/ +#define LSM6DS0_G_ODR_238HZ ((uint8_t)0x80) /*!< Output Data Rate: 238 Hz, cutoff 76Hz*/ +#define LSM6DS0_G_ODR_476HZ ((uint8_t)0xA0) /*!< Output Data Rate: 476 Hz, cutoff 100Hz*/ +#define LSM6DS0_G_ODR_952HZ ((uint8_t)0xC0) /*!< Output Data Rate: 952 Hz, cutoff 100Hz*/ + +#define LSM6DS0_G_ODR_MASK ((uint8_t)0xE0) +/** + * @} + */ + + +/** @defgroup LSM6DS0_XG_Gyroscope_Bandwidth_Selection_CTRL_REG1_G LSM6DS0_XG_Gyroscope_Bandwidth_Selection_CTRL_REG1_G + * @{ + */ +#define LSM6DS0_G_BW_00 ((uint8_t)0x00) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down + - cutoff = n.a. when ODR = 14.9 + - cutoff = 16 when ODR = 59.5 + - cutoff = 14 when ODR = 119 + - cutoff = 14 when ODR = 238 + - cutoff = 21 when ODR = 476 + - cutoff = 33 when ODR = 952 */ +#define LSM6DS0_G_BW_01 ((uint8_t)0x01) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down + - cutoff = n.a. when ODR = 14.9 + - cutoff = 16 when ODR = 59.5 + - cutoff = 31 when ODR = 119 + - cutoff = 29 when ODR = 238 + - cutoff = 28 when ODR = 476 + - cutoff = 40 when ODR = 952 */ +#define LSM6DS0_G_BW_10 ((uint8_t)0x02) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down + - cutoff = n.a. when ODR = 14.9 + - cutoff = 16 when ODR = 59.5 + - cutoff = 31 when ODR = 119 + - cutoff = 63 when ODR = 238 + - cutoff = 57 when ODR = 476 + - cutoff = 58 when ODR = 952 */ +#define LSM6DS0_G_BW_11 ((uint8_t)0x03) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down + - cutoff = n.a. when ODR = 14.9 + - cutoff = 16 when ODR = 59.5 + - cutoff = 31 when ODR = 119 + - cutoff = 78 when ODR = 238 + - cutoff = 100 when ODR = 476 + - cutoff = 100 when ODR = 952 */ + +#define LSM6DS0_G_BW_MASK ((uint8_t)0x03) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Gyroscope_Full_Scale_Selection_CTRL_REG1_G LSM6DS0_XG_Gyroscope_Full_Scale_Selection_CTRL_REG1_G + * @{ + */ +#define LSM6DS0_G_FS_245 ((uint8_t)0x00) /*!< Full scale: 245 dps*/ +#define LSM6DS0_G_FS_500 ((uint8_t)0x08) /*!< Full scale: 500 dps */ +#define LSM6DS0_G_FS_2000 ((uint8_t)0x18) /*!< Full scale: 2000 dps */ + +#define LSM6DS0_G_FS_MASK ((uint8_t)0x18) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL_REG4 LSM6DS0_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL_REG4 + * @{ + */ +#define LSM6DS0_G_ZEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Z-axis output enable: disable */ +#define LSM6DS0_G_ZEN_ENABLE ((uint8_t)0x20) /*!< Gyroscope’s Z-axis output enable: enable */ + +#define LSM6DS0_G_ZEN_MASK ((uint8_t)0x20) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL_REG4 LSM6DS0_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL_REG4 + * @{ + */ +#define LSM6DS0_G_YEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Y-axis output enable: disable */ +#define LSM6DS0_G_YEN_ENABLE ((uint8_t)0x10) /*!< Gyroscope’s Y-axis output enable: enable */ + +#define LSM6DS0_G_YEN_MASK ((uint8_t)0x10) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL_REG4 LSM6DS0_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL_REG4 + * @{ + */ +#define LSM6DS0_G_XEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s X-axis output enable: disable */ +#define LSM6DS0_G_XEN_ENABLE ((uint8_t)0x08) /*!< Gyroscope’s X-axis output enable: enable */ + +#define LSM6DS0_G_XEN_MASK ((uint8_t)0x08) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Gyroscope_Selftest_Enable_Selection_CTRL_REG10 LSM6DS0_XG_Gyroscope_Selftest_Enable_Selection_CTRL_REG10 + * @{ + */ +#define LSM6DS0_G_ST_DISABLE ((uint8_t)0x00) /*!< Gyro selftest disable */ +#define LSM6DS0_G_ST_ENABLE ((uint8_t)0x04) /*!< Gyro selftest enable */ + +#define LSM6DS0_G_ST_MASK ((uint8_t)0x04) +/** + * @} + */ + + +/************************************ ACCELEROMETER REGISTERS VALUE *****************************************/ + +/** @defgroup LSM6DS0_XG_Accelerometer_Output_Data_Rate_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Output_Data_Rate_Selection_CTRL_REG6_XL + * @{ + */ +#define LSM6DS0_XL_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ +#define LSM6DS0_XL_ODR_10HZ ((uint8_t)0x20) /*!< Output Data Rate: 10 Hz*/ +#define LSM6DS0_XL_ODR_50HZ ((uint8_t)0x40) /*!< Output Data Rate: 50 Hz */ +#define LSM6DS0_XL_ODR_119HZ ((uint8_t)0x60) /*!< Output Data Rate: 119 Hz */ +#define LSM6DS0_XL_ODR_238HZ ((uint8_t)0x80) /*!< Output Data Rate: 238 Hz */ +#define LSM6DS0_XL_ODR_476HZ ((uint8_t)0xA0) /*!< Output Data Rate: 476 Hz */ +#define LSM6DS0_XL_ODR_952HZ ((uint8_t)0xC0) /*!< Output Data Rate: 952 Hz */ + +#define LSM6DS0_XL_ODR_MASK ((uint8_t)0xE0) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Accelerometer_Full_Scale_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Full_Scale_Selection_CTRL_REG6_XL + * @{ + */ +#define LSM6DS0_XL_FS_2G ((uint8_t)0x00) /*!< Full scale: +- 2g */ +#define LSM6DS0_XL_FS_4G ((uint8_t)0x10) /*!< Full scale: +- 4g */ +#define LSM6DS0_XL_FS_8G ((uint8_t)0x18) /*!< Full scale: +- 8g */ +#define LSM6DS0_XL_FS_16G ((uint8_t)0x08) /*!< Full scale: +- 16g */ + +#define LSM6DS0_XL_FS_MASK ((uint8_t)0x18) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Accelerometer_Bandwidth_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Bandwidth_Selection_CTRL_REG6_XL + * @{ + */ +#define LSM6DS0_XL_BW_SCAL_ODR ((uint8_t)0x00) /*!< Bandwidth selection: determined by ODR: + - BW = 408Hz when ODR = 952Hz, 50Hz, 10Hz + - BW = 211Hz when ODR = 476Hz + - BW = 105Hz when ODR = 238Hz + - BW = 50Hz when ODR = 119Hz */ +#define LSM6DS0_XL_BW_SCAL_BW ((uint8_t)0x04) /*!< Bandwidth selection: selected according to Anti aliasing filter bandwidth */ + +#define LSM6DS0_XL_BW_SCAL_MASK ((uint8_t)0x04) +/** + * @} + */ + + +/** @defgroup LSM6DS0_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL_REG6_XL + * @{ + */ +#define LSM6DS0_XL_BW_408HZ ((uint8_t)0x00) /*!< Anti-aliasing filter bandwidht: 408 Hz */ +#define LSM6DS0_XL_BW_211HZ ((uint8_t)0x01) /*!< Anti-aliasing filter bandwidht: 211 Hz */ +#define LSM6DS0_XL_BW_105HZ ((uint8_t)0x02) /*!< Anti-aliasing filter bandwidht: 105 Hz */ +#define LSM6DS0_XL_BW_50HZ ((uint8_t)0x03) /*!< Anti-aliasing filter bandwidht: 50 Hz */ + +#define LSM6DS0_XL_BW_MASK ((uint8_t)0x03) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Accelerometer_Decimation_Acceleration_Data_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_Decimation_Acceleration_Data_Selection_CTRL_REG5_XL + * @{ + */ +#define LSM6DS0_XL_DEC_NO ((uint8_t)0x00) /*!< Decimation of acceleration data: no decimation */ +#define LSM6DS0_XL_DEC_EVERY_2S ((uint8_t)0x40) /*!< Decimation of acceleration data: update every 2 samples */ +#define LSM6DS0_XL_DEC_EVERY_4S ((uint8_t)0x80) /*!< Decimation of acceleration data: update every 4 samples */ +#define LSM6DS0_XL_DEC_EVERY_8S ((uint8_t)0xC0) /*!< Decimation of acceleration data: update every 8 samples */ + +#define LSM6DS0_XL_DEC_MASK ((uint8_t)0xC0) +/** + * @} + */ + + +/** @defgroup LSM6DS0_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL_REG5_XL + * @{ + */ +#define LSM6DS0_XL_ZEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Z-axis output enable: disable */ +#define LSM6DS0_XL_ZEN_ENABLE ((uint8_t)0x20) /*!< Accelerometer’s Z-axis output enable: enable */ + +#define LSM6DS0_XL_ZEN_MASK ((uint8_t)0x20) +/** + * @} + */ + +/** @defgroup LSM6DS0_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL_REG5_XL + * @{ + */ +#define LSM6DS0_XL_YEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Y-axis output enable: disable */ +#define LSM6DS0_XL_YEN_ENABLE ((uint8_t)0x10) /*!< Accelerometer’s Y-axis output enable: enable */ + +#define LSM6DS0_XL_YEN_MASK ((uint8_t)0x10) +/** + * @} + */ + + +/** @defgroup LSM6DS0_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL_REG5_XL + * @{ + */ +#define LSM6DS0_XL_XEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s X-axis output enable: disable */ +#define LSM6DS0_XL_XEN_ENABLE ((uint8_t)0x08) /*!< Accelerometer’s X-axis output enable: enable */ + +#define LSM6DS0_XL_XEN_MASK ((uint8_t)0x08) + +/** + * @} + */ + + +/** @defgroup LSM6DS0_XG_Accelerometer_Selftest_Enable_Selection_CTRL_REG10 LSM6DS0_XG_Accelerometer_Selftest_Enable_Selection_CTRL_REG10 + * @{ + */ +#define LSM6DS0_XL_ST_DISABLE ((uint8_t)0x00) /*!< Accel selftest disable */ +#define LSM6DS0_XL_ST_ENABLE ((uint8_t)0x01) /*!< Accel selftest enable */ + +#define LSM6DS0_XL_ST_MASK ((uint8_t)0x01) + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup LSM6DS0_Imported_Functions LSM6DS0_Imported_Functions + * @{ + */ + +/* Six axes sensor IO functions */ +extern IMU_6AXES_StatusTypeDef LSM6DS0_IO_Init(void); +extern IMU_6AXES_StatusTypeDef LSM6DS0_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToWrite); +extern IMU_6AXES_StatusTypeDef LSM6DS0_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToRead); +extern void LSM6DS0_IO_ITConfig( void ); + +/** + * @} + */ + +/* ------------------------------------------------------- */ +/* Here you should declare the internal struct of */ +/* extended features of LIS3MDL. See the example of */ +/* LSM6DS3 in lsm6ds3.h */ +/* ------------------------------------------------------- */ + +/** @addtogroup LSM6DS0_Exported_Variables LSM6DS0_Exported_Variables + * @{ + */ + +/* Six axes sensor driver structure */ +extern IMU_6AXES_DrvTypeDef LSM6DS0Drv; +extern IMU_6AXES_DrvExtTypeDef LSM6DS0Drv_ext; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LSM6DS0_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/Release_Notes.html new file mode 100644 index 000000000..c6ebdd291 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/Release_Notes.html @@ -0,0 +1,195 @@ + + + + + +Release Notes for STM32 BlueEnergy Library + + + + + +
+


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+ + + + + + +
+ + + + + + + + + +
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Release Notes for LSM6DS3 component

+

Copyright +2015 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+ + +

V1.2.0 +/ 28-May-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add output data rate and full scale settings APIs for the Component +
    • +
  • Add LSM6DS3_X_GetAxes and LSM6DS3_G_GetAxes APIs +
    • +
+ +

V1.1.0 +/ 11-February-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add extended features support for the Component +
    • +
  • Add support for free fall detection feature for the Component +
    • +
+ +

V1.0.0 +/ 12-December-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • First +official release
    • +
+ + +

License
+

+ + +Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

+ + +
+ http://www.st.com/software_license_agreement_liberty_v2


+ +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + + + + +

+ +
+
+

For +complete documentation on STM32 STM BlueNRG +visit www.st.com/BlueNRG

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.c b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.c new file mode 100644 index 000000000..1c1e9e1c7 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.c @@ -0,0 +1,1111 @@ +/** + ****************************************************************************** + * @file lsm6ds3.c + * @author MEMS Application Team + * @version V1.2.0 + * @date 28-May-2015 + * @brief This file provides a set of functions needed to manage the LSM6DS3 sensor + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lsm6ds3.h" +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LSM6DS3 + * @{ + */ + +static IMU_6AXES_StatusTypeDef LSM6DS3_Init( IMU_6AXES_InitTypeDef *LSM6DS3_Init ); +static IMU_6AXES_StatusTypeDef LSM6DS3_Read_XG_ID( uint8_t *xg_id); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxes( int32_t *pData ); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxesRaw(int16_t *pData); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxes( int32_t *pData ); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxesRaw(int16_t *pData); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_ODR( float *odr ); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_ODR( float odr ); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetSensitivity( float *pfData ); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_FS( float *fullScale ); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_FS( float fullScale ); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_ODR( float *odr ); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_ODR( float odr ); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetSensitivity( float *pfData ); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_FS( float *fullScale ); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_FS( float fullScale ); +static IMU_6AXES_StatusTypeDef LSM6DS3_Enable_Free_Fall_Detection( void ); +static IMU_6AXES_StatusTypeDef LSM6DS3_Disable_Free_Fall_Detection( void ); +static IMU_6AXES_StatusTypeDef LSM6DS3_Get_Status_Free_Fall_Detection( uint8_t *status ); + +/** @addtogroup LSM6DS3_Private_Variables LSM6DS3_Private_Variables + * @{ + */ +IMU_6AXES_DrvTypeDef LSM6DS3Drv = +{ + LSM6DS3_Init, + LSM6DS3_Read_XG_ID, + LSM6DS3_X_GetAxes, + LSM6DS3_X_GetAxesRaw, + LSM6DS3_G_GetAxes, + LSM6DS3_G_GetAxesRaw, + LSM6DS3_X_Get_ODR, + LSM6DS3_X_Set_ODR, + LSM6DS3_X_GetSensitivity, + LSM6DS3_X_Get_FS, + LSM6DS3_X_Set_FS, + LSM6DS3_G_Get_ODR, + LSM6DS3_G_Set_ODR, + LSM6DS3_G_GetSensitivity, + LSM6DS3_G_Get_FS, + LSM6DS3_G_Set_FS, + NULL +}; + +LSM6DS3_DrvExtTypeDef LSM6DS3Drv_ext_internal = +{ + + LSM6DS3_Enable_Free_Fall_Detection, + LSM6DS3_Disable_Free_Fall_Detection, + LSM6DS3_Get_Status_Free_Fall_Detection +}; + +IMU_6AXES_DrvExtTypeDef LSM6DS3Drv_ext = +{ + IMU_6AXES_LSM6DS3_DIL24_COMPONENT, /* unique ID for LSM6DS3 in the IMU 6-axes driver class */ + &LSM6DS3Drv_ext_internal /* pointer to internal struct of extended features of LSM6DS3 */ +}; + +/** + * @} + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_Common_Sensor_Enable(void); +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); + +/** @addtogroup LSM6DS3_Private_Functions LSM6DS3_Private_Functions + * @{ + */ + +/** + * @brief Set LSM6DS3 Initialization + * @param LSM6DS3_Init the configuration setting for the LSM6DS3 + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_Init( IMU_6AXES_InitTypeDef *LSM6DS3_Init ) +{ + /*Here we have to add the check if the parameters are valid*/ + + /* Configure the low level interface -------------------------------------*/ + if(LSM6DS3_IO_Init() != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + + /******** Common init *********/ + + if(LSM6DS3_Common_Sensor_Enable() != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + + /******* Gyroscope init *******/ + + if(LSM6DS3_G_Set_ODR( LSM6DS3_Init->G_OutputDataRate ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_G_Set_FS( LSM6DS3_Init->G_FullScale ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_G_Set_Axes_Status(LSM6DS3_Init->G_X_Axis, LSM6DS3_Init->G_Y_Axis, LSM6DS3_Init->G_Z_Axis) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + + /***** Accelerometer init *****/ + + if(LSM6DS3_X_Set_ODR( LSM6DS3_Init->X_OutputDataRate ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_X_Set_FS( LSM6DS3_Init->X_FullScale ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_X_Set_Axes_Status(LSM6DS3_Init->X_X_Axis, LSM6DS3_Init->X_Y_Axis, LSM6DS3_Init->X_Z_Axis) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Configure interrupt lines */ + LSM6DS3_IO_ITConfig(); + + return IMU_6AXES_OK; +} + +/** + * @brief Read ID of LSM6DS3 Accelerometer and Gyroscope + * @param xg_id the pointer where the ID of the device is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_Read_XG_ID( uint8_t *xg_id) +{ + if(!xg_id) + { + return IMU_6AXES_ERROR; + } + + return LSM6DS3_IO_Read(xg_id, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WHO_AM_I_ADDR, 1); +} + +/** + * @brief Set LSM6DS3 common initialization + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_Common_Sensor_Enable(void) +{ + uint8_t tmp1 = 0x00; + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL3_C, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Enable register address automatically incremented during a multiple byte + access with a serial interface (I2C or SPI) */ + tmp1 &= ~(LSM6DS3_XG_IF_INC_MASK); + tmp1 |= LSM6DS3_XG_IF_INC; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL3_C, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_FIFO_CTRL5, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* FIFO ODR selection */ + tmp1 &= ~(LSM6DS3_XG_FIFO_ODR_MASK); + tmp1 |= LSM6DS3_XG_FIFO_ODR_NA; + + /* FIFO mode selection */ + tmp1 &= ~(LSM6DS3_XG_FIFO_MODE_MASK); + tmp1 |= LSM6DS3_XG_FIFO_MODE_BYPASS; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_FIFO_CTRL5, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read raw data from LSM6DS3 Accelerometer output register + * @param pData the pointer where the accelerometer raw data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxesRaw( int16_t *pData ) +{ + /*Here we have to add the check if the parameters are valid*/ + + uint8_t tempReg[2] = {0, 0}; + + + if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_X_L_XL, 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Y_L_XL, 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Z_L_XL, 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + return IMU_6AXES_OK; +} + + + +/** + * @brief Read data from LSM6DS3 Accelerometer and calculate linear acceleration in mg + * @param pData the pointer where the accelerometer data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxes( int32_t *pData ) +{ + /*Here we have to add the check if the parameters are valid*/ + int16_t pDataRaw[3]; + float sensitivity = 0.0f; + + if(LSM6DS3_X_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_X_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = (int32_t)(pDataRaw[0] * sensitivity); + pData[1] = (int32_t)(pDataRaw[1] * sensitivity); + pData[2] = (int32_t)(pDataRaw[2] * sensitivity); + + return IMU_6AXES_OK; +} + + + +/** + * @brief Read raw data from LSM6DS3 Gyroscope output register + * @param pData the pointer where the gyroscope raw data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxesRaw( int16_t *pData ) +{ + /*Here we have to add the check if the parameters are valid*/ + + uint8_t tempReg[2] = {0, 0}; + + + if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_X_L_G, 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Y_L_G, 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Z_L_G, 2) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); + + return IMU_6AXES_OK; +} + +/** + * @brief Set the status of the axes for accelerometer + * @param enableX the status of the x axis to be set + * @param enableY the status of the y axis to be set + * @param enableZ the status of the z axis to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) +{ + uint8_t tmp1 = 0x00; + uint8_t eX = 0x00; + uint8_t eY = 0x00; + uint8_t eZ = 0x00; + + eX = ( enableX == 0 ) ? LSM6DS3_XL_XEN_DISABLE : LSM6DS3_XL_XEN_ENABLE; + eY = ( enableY == 0 ) ? LSM6DS3_XL_YEN_DISABLE : LSM6DS3_XL_YEN_ENABLE; + eZ = ( enableZ == 0 ) ? LSM6DS3_XL_ZEN_DISABLE : LSM6DS3_XL_ZEN_ENABLE; + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL9_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Enable X axis selection */ + tmp1 &= ~(LSM6DS3_XL_XEN_MASK); + tmp1 |= eX; + + /* Enable Y axis selection */ + tmp1 &= ~(LSM6DS3_XL_YEN_MASK); + tmp1 |= eY; + + /* Enable Z axis selection */ + tmp1 &= ~(LSM6DS3_XL_ZEN_MASK); + tmp1 |= eZ; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL9_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Set the status of the axes for gyroscope + * @param enableX the status of the x axis to be set + * @param enableY the status of the y axis to be set + * @param enableZ the status of the z axis to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) +{ + uint8_t tmp1 = 0x00; + uint8_t eX = 0x00; + uint8_t eY = 0x00; + uint8_t eZ = 0x00; + + eX = ( enableX == 0 ) ? LSM6DS3_G_XEN_DISABLE : LSM6DS3_G_XEN_ENABLE; + eY = ( enableY == 0 ) ? LSM6DS3_G_YEN_DISABLE : LSM6DS3_G_YEN_ENABLE; + eZ = ( enableZ == 0 ) ? LSM6DS3_G_ZEN_DISABLE : LSM6DS3_G_ZEN_ENABLE; + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL10_C, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Enable X axis selection */ + tmp1 &= ~(LSM6DS3_G_XEN_MASK); + tmp1 |= eX; + + /* Enable Y axis selection */ + tmp1 &= ~(LSM6DS3_G_YEN_MASK); + tmp1 |= eY; + + /* Enable Z axis selection */ + tmp1 &= ~(LSM6DS3_G_ZEN_MASK); + tmp1 |= eZ; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL10_C, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read data from LSM6DS3 Gyroscope and calculate angular rate in mdps + * @param pData the pointer where the gyroscope data are stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxes( int32_t *pData ) +{ + /*Here we have to add the check if the parameters are valid*/ + int16_t pDataRaw[3]; + float sensitivity = 0.0f; + + if(LSM6DS3_G_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_G_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + pData[0] = (int32_t)(pDataRaw[0] * sensitivity); + pData[1] = (int32_t)(pDataRaw[1] * sensitivity); + pData[2] = (int32_t)(pDataRaw[2] * sensitivity); + + return IMU_6AXES_OK; +} + +/** + * @brief Read Accelero Output Data Rate + * @param odr the pointer where the accelerometer output data rate is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_ODR( float *odr ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_XL_ODR_MASK; + + switch( tempReg ) + { + case LSM6DS3_XL_ODR_PD: + *odr = 0.0f; + break; + case LSM6DS3_XL_ODR_13HZ: + *odr = 13.0f; + break; + case LSM6DS3_XL_ODR_26HZ: + *odr = 26.0f; + break; + case LSM6DS3_XL_ODR_52HZ: + *odr = 52.0f; + break; + case LSM6DS3_XL_ODR_104HZ: + *odr = 104.0f; + break; + case LSM6DS3_XL_ODR_208HZ: + *odr = 208.0f; + break; + case LSM6DS3_XL_ODR_416HZ: + *odr = 416.0f; + break; + case LSM6DS3_XL_ODR_833HZ: + *odr = 833.0f; + break; + case LSM6DS3_XL_ODR_1660HZ: + *odr = 1660.0f; + break; + case LSM6DS3_XL_ODR_3330HZ: + *odr = 3330.0f; + break; + case LSM6DS3_XL_ODR_6660HZ: + *odr = 6660.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Accelero Output Data Rate + * @param odr the accelerometer output data rate to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_ODR( float odr ) +{ + uint8_t new_odr = 0x00; + uint8_t tempReg = 0x00; + + new_odr = ( odr <= 0.0f ) ? LSM6DS3_XL_ODR_PD /* Power Down */ + : ( odr <= 13.0f ) ? LSM6DS3_XL_ODR_13HZ + : ( odr <= 26.0f ) ? LSM6DS3_XL_ODR_26HZ + : ( odr <= 52.0f ) ? LSM6DS3_XL_ODR_52HZ + : ( odr <= 104.0f ) ? LSM6DS3_XL_ODR_104HZ + : ( odr <= 208.0f ) ? LSM6DS3_XL_ODR_208HZ + : ( odr <= 416.0f ) ? LSM6DS3_XL_ODR_416HZ + : ( odr <= 833.0f ) ? LSM6DS3_XL_ODR_833HZ + : ( odr <= 1660.0f ) ? LSM6DS3_XL_ODR_1660HZ + : ( odr <= 3330.0f ) ? LSM6DS3_XL_ODR_3330HZ + : LSM6DS3_XL_ODR_6660HZ; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS3_XL_ODR_MASK); + tempReg |= new_odr; + + if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Accelero Sensitivity + * @param pfData the pointer where the accelerometer sensitivity is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetSensitivity( float *pfData ) +{ + /*Here we have to add the check if the parameters are valid*/ + + uint8_t tempReg = 0x00; + + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_XL_FS_MASK; + + switch( tempReg ) + { + case LSM6DS3_XL_FS_2G: + *pfData = 0.061f; + break; + case LSM6DS3_XL_FS_4G: + *pfData = 0.122f; + break; + case LSM6DS3_XL_FS_8G: + *pfData = 0.244f; + break; + case LSM6DS3_XL_FS_16G: + *pfData = 0.488f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Accelero Full Scale + * @param fullScale the pointer where the accelerometer full scale is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_FS( float *fullScale ) +{ + /*Here we have to add the check if the parameters are valid*/ + + uint8_t tempReg = 0x00; + + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_XL_FS_MASK; + + switch( tempReg ) + { + case LSM6DS3_XL_FS_2G: + *fullScale = 2.0f; + break; + case LSM6DS3_XL_FS_4G: + *fullScale = 4.0f; + break; + case LSM6DS3_XL_FS_8G: + *fullScale = 8.0f; + break; + case LSM6DS3_XL_FS_16G: + *fullScale = 16.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Accelero Full Scale + * @param fullScale the accelerometer full scale to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_FS( float fullScale ) +{ + uint8_t new_fs = 0x00; + uint8_t tempReg = 0x00; + + new_fs = ( fullScale <= 2.0f ) ? LSM6DS3_XL_FS_2G + : ( fullScale <= 4.0f ) ? LSM6DS3_XL_FS_4G + : ( fullScale <= 8.0f ) ? LSM6DS3_XL_FS_8G + : LSM6DS3_XL_FS_16G; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS3_XL_FS_MASK); + tempReg |= new_fs; + + if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Gyro Output Data Rate + * @param odr the pointer where the gyroscope output data rate is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_ODR( float *odr ) +{ + /*Here we have to add the check if the parameters are valid*/ + uint8_t tempReg = 0x00; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_G_ODR_MASK; + + switch( tempReg ) + { + case LSM6DS3_G_ODR_PD: + *odr = 0.0f; + break; + case LSM6DS3_G_ODR_13HZ: + *odr = 13.0f; + break; + case LSM6DS3_G_ODR_26HZ: + *odr = 26.0f; + break; + case LSM6DS3_G_ODR_52HZ: + *odr = 52.0f; + break; + case LSM6DS3_G_ODR_104HZ: + *odr = 104.0f; + break; + case LSM6DS3_G_ODR_208HZ: + *odr = 208.0f; + break; + case LSM6DS3_G_ODR_416HZ: + *odr = 416.0f; + break; + case LSM6DS3_G_ODR_833HZ: + *odr = 833.0f; + break; + case LSM6DS3_G_ODR_1660HZ: + *odr = 1660.0f; + break; + default: + break; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Gyro Output Data Rate + * @param odr the gyroscope output data rate to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise + */ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_ODR( float odr ) +{ + uint8_t new_odr = 0x00; + uint8_t tempReg = 0x00; + + new_odr = ( odr <= 0.0f ) ? LSM6DS3_G_ODR_PD /* Power Down */ + : ( odr <= 13.0f ) ? LSM6DS3_G_ODR_13HZ + : ( odr <= 26.0f ) ? LSM6DS3_G_ODR_26HZ + : ( odr <= 52.0f ) ? LSM6DS3_G_ODR_52HZ + : ( odr <= 104.0f ) ? LSM6DS3_G_ODR_104HZ + : ( odr <= 208.0f ) ? LSM6DS3_G_ODR_208HZ + : ( odr <= 416.0f ) ? LSM6DS3_G_ODR_416HZ + : ( odr <= 833.0f ) ? LSM6DS3_G_ODR_833HZ + : LSM6DS3_G_ODR_1660HZ; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS3_G_ODR_MASK); + tempReg |= new_odr; + + if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Gyro Sensitivity + * @param pfData the pointer where the gyroscope sensitivity is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetSensitivity( float *pfData ) +{ + /*Here we have to add the check if the parameters are valid*/ + + uint8_t tempReg = 0x00; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_G_FS_125_MASK; + + if(tempReg == LSM6DS3_G_FS_125_ENABLE) + { + *pfData = 4.375f; + } + else + { + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_G_FS_MASK; + + switch( tempReg ) + { + case LSM6DS3_G_FS_245: + *pfData = 8.75f; + break; + case LSM6DS3_G_FS_500: + *pfData = 17.50f; + break; + case LSM6DS3_G_FS_1000: + *pfData = 35.0f; + break; + case LSM6DS3_G_FS_2000: + *pfData = 70.0f; + break; + default: + break; + } + } + + return IMU_6AXES_OK; +} + +/** + * @brief Read Gyro Full Scale + * @param fullScale the pointer where the gyroscope full scale is stored + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_FS( float *fullScale ) +{ + /*Here we have to add the check if the parameters are valid*/ + + uint8_t tempReg = 0x00; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_G_FS_125_MASK; + + if(tempReg == LSM6DS3_G_FS_125_ENABLE) + { + *fullScale = 125.0f; + } + else + { + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= LSM6DS3_G_FS_MASK; + + switch( tempReg ) + { + case LSM6DS3_G_FS_245: + *fullScale = 245.0f; + break; + case LSM6DS3_G_FS_500: + *fullScale = 500.0f; + break; + case LSM6DS3_G_FS_1000: + *fullScale = 1000.0f; + break; + case LSM6DS3_G_FS_2000: + *fullScale = 2000.0f; + break; + default: + break; + } + } + + return IMU_6AXES_OK; +} + +/** + * @brief Write Gyro Full Scale + * @param fullScale the gyroscope full scale to be set + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_FS( float fullScale ) +{ + uint8_t new_fs = 0x00; + uint8_t tempReg = 0x00; + + if(fullScale <= 125.0f) + { + new_fs = LSM6DS3_G_FS_125_ENABLE; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS3_G_FS_125_MASK); + tempReg |= new_fs; + + if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + } + else + { + /* Disable G FS 125dpp */ + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS3_G_FS_125_MASK); + tempReg |= LSM6DS3_G_FS_125_DISABLE; + + if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + new_fs = ( fullScale <= 245.0f ) ? LSM6DS3_G_FS_245 + : ( fullScale <= 500.0f ) ? LSM6DS3_G_FS_500 + : ( fullScale <= 1000.0f ) ? LSM6DS3_G_FS_1000 + : LSM6DS3_G_FS_2000; + + if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tempReg &= ~(LSM6DS3_G_FS_MASK); + tempReg |= new_fs; + + if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + } + + return IMU_6AXES_OK; +} + +/** + * @brief Enable free fall detection + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS3_Enable_Free_Fall_Detection( void ) +{ + uint8_t tmp1 = 0x00; + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* Output Data Rate selection */ + tmp1 &= ~(LSM6DS3_XL_ODR_MASK); + tmp1 |= LSM6DS3_XL_ODR_416HZ; + + /* Full scale selection */ + tmp1 &= ~(LSM6DS3_XL_FS_MASK); + tmp1 |= LSM6DS3_XL_FS_2G; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_UP_DUR, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* FF_DUR5 setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_MASK); + tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_DEFAULT; + + /* WAKE_DUR setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_MASK); + tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_DEFAULT; + + /* TIMER_HR setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_MASK); + tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_DEFAULT; + + /* SLEEP_DUR setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_MASK); + tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_DEFAULT; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_UP_DUR, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* FF_DUR setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK); + tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_TYPICAL; + + /* FF_THS setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK); + tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_312MG; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* INT1_FF setting */ + tmp1 &= ~(LSM6DS3_XG_MD1_CFG_INT1_FF_MASK); + tmp1 |= LSM6DS3_XG_MD1_CFG_INT1_FF_ENABLE; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Disable free fall detection + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS3_Disable_Free_Fall_Detection( void ) +{ + uint8_t tmp1 = 0x00; + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* INT1_FF setting */ + tmp1 &= ~(LSM6DS3_XG_MD1_CFG_INT1_FF_MASK); + tmp1 |= LSM6DS3_XG_MD1_CFG_INT1_FF_DISABLE; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + /* FF_DUR setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK); + tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_DEFAULT; + + /* FF_THS setting */ + tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK); + tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_156MG; + + if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + return IMU_6AXES_OK; +} + +/** + * @brief Get status of free fall detection + * @param status the pointer where the status of free fall detection is stored; 0 means no detection, 1 means detection happened + * @retval IMU_6AXES_OK in case of success, an error code otherwise +*/ +static IMU_6AXES_StatusTypeDef LSM6DS3_Get_Status_Free_Fall_Detection( uint8_t *status ) +{ + uint8_t tmp1 = 0x00; + + if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_UP_SRC, 1) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + tmp1 &= LSM6DS3_XG_WAKE_UP_SRC_FF_IA_MASK; + + switch( tmp1 ) + { + case LSM6DS3_XG_WAKE_UP_SRC_FF_IA_ENABLE: + *status = 1; + break; + case LSM6DS3_XG_WAKE_UP_SRC_FF_IA_DISABLE: + default: + *status = 0; + break; + } + + return IMU_6AXES_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.h b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.h new file mode 100644 index 000000000..72fced378 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.h @@ -0,0 +1,1481 @@ +/** + ****************************************************************************** + * @file lsm6ds3.h + * @author MEMS Application Team + * @version V1.2.0 + * @date 28-May-2015 + * @brief This file contains definitions for the lsm6ds3.c firmware driver + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LSM6DS3_H +#define __LSM6DS3_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "imu_6axes.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup LSM6DS3 + * @{ + */ + +/** @addtogroup LSM6DS3_Exported_Defines LSM6DS3_Exported_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif + +/******************************************************************************/ +/*********** START ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ +/******************************************************************************/ + + +/***************************************** COMMON REGISTERS ********************************************/ + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7] FUNC_CFG_EN: Enable access to the embedded functions configuration registers (1) from address 02h to 32h. Default value: 0. + * [6:0] This bit must be set to ‘0’ for the correct operation of the device + * \endcode +*/ +#define LSM6DS3_XG_FUNC_CFG_ACCESS 0x01 + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7:0] TPH_[7:0]: Sensor SyncronizationTime Frame with the step of 500ms and full range of 5s. Default: 0000 0000 + * \endcode +*/ +#define LSM6DS3_XG_SENSOR_SYNC_TIME_FRAME 0x04 + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7:2] This bit must be set to ‘0’ for the correct operation of the device + * [1] HP_RST: Gyro digital HP filter reset. Default: 0 + * [1] SENSOR_SYNC_ENHP_RST: Enable sensor synchronization feature. Default 0 + * \endcode +*/ +#define LSM6DS3_XG_SENSOR_SYNC_ENABLE 0x05 + + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7:0] FTH_7-0 FIFO threshold level setting - watermark flag is toggled when the number of bytes written to FIFO is greater or equal to threshold level. + * \endcode +*/ +#define LSM6DS3_XG_FIFO_CTRL1 0x06 + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7] TIMER_PEDO_FIFO_EN: Enable Pedometer step counter and time stamp as 4th sensor FIFO data. Default: 0 disabled + * [6] TIMER_PEDO_FIFO_DRDY : Pedometer FIFO write mode. Default: 0 disabled + * [5:4] This bit must be set to ‘0’ for the correct operation of the device + * [3:0] FTH_[11:8] FIFO threshold level setting(1). Default value: 0000 + * \endcode +*/ +#define LSM6DS3_XG_FIFO_CTRL2 0x07 + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7:6] This bit must be set to ‘0’ for the correct operation of the device + * [5:3] DEC_FIFO_GYRO[2:0]: Gyro FIFO decimation setting. Default value: 000 + * [2:0] DEC_FIFO_XL[2:0]: XL FIFO decimation setting. Default value: 000 + * \endcode +*/ +#define LSM6DS3_XG_FIFO_CTRL3 0x08 + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7] This bit must be set to ‘0’ for the correct operation of the device + * [6] ONLY_HIGH_DATA :8 bit data storing in FIFO. Default: 0 + * [5:3] DEC_SLV1_FIFO[2:0] Second external sensor FIFO decimation setting. Default: 000 + * [2:0] DEC_SLV1_FIFO[2:0] First external sensor FIFO decimation setting. Default: 000 + * \endcode +*/ +#define LSM6DS3_XG_FIFO_CTRL4 0x09 + + +/** + * @brief FIFO control register + * \code + * Read/write + * Default value: 0x00 + * [7] This bit must be set to ‘0’ for the correct operation of the device + * [6:3] ODR_FIFO_[3:0]: FIFO ODR selection. Default: 0000 + * [2:0] FIFO_MODE_[2:0] : FIFO mode selection bits. Default value: 000 + * \endcode +*/ +#define LSM6DS3_XG_FIFO_CTRL5 0x0A + + +/** + * @brief Angular rate sensor sign and orientation register + * \code + * Read/write + * Default value: 0x00 + * [7:6] This bit must be set to ‘0’ for the correct operation of the device + * [5] SignX_G: Pitch axis (X) Angular rate sign. Default value: 0 + * [5] SignY_G: Roll axis (Y) Angular rate sign. Default value: 0 + * [5] SignZ_G: Pitch axis (Z) Angular rate sign. Default value: 0 + * [2:0] Orient[2:0] : Directional user orientation selection. Default Value: 000 + * \endcode +*/ +#define LSM6DS3_XG_ORIENT_CFG_G 0x0B + +/** + * @brief INT1 pad control registrer + * \code + * Read/write + * Default value: 0x00 + * [7] INT1_PEDO: Pedometer step recognition interrupt enable on INT1 pad. Default value: 0 + * [6] INT1_SIGN_MOT: Significant motion interrupt enable on INT1 pad. Default value: 0 + * [5] INT1_FULL_FLAG: Full flag Interrupt Enable on INT1 pad. Default value: 0 + * [4] INT1_OVR: Overrun Interrupt on INT1 pad. Default value: 0 + * [3] INT1_FTH: FIFO threshold interrupt on INT1 pad. Default value: 0 + * [2] INT1_BOOT: Overrun Interrupt on INT1 pad. Default value: 0 + * [1] INT1_DRDY_G: Gyroscope Data Ready on INT1 pad. Default value: 0. + * [0] INT1_DRDY_XL: Accelerometer Data Ready on INT1 pad. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_INT1_CTRL 0x0D + + +//new, done +/** + * @brief INT2 pad control registrer + * \code + * Read/write + * Default value: 0x00 + * [7] INT2_PEDO: Pedometer step recognition interrupt enable on INT1 pad. Default value: 0 + * [6] INT2_SIGN_MOT: Significant motion interrupt enable on INT1 pad. Default value: 0 + * [5] INT2_FULL_FLAG: Full flag Interrupt Enable on INT1 pad. Default value: 0 + * [4] INT2_OVR: Overrun Interrupt on INT1 pad. Default value: 0 + * [3] INT2_FTH: FIFO threshold interrupt on INT1 pad. Default value: 0 + * [2] INT2_BOOT: Overrun Interrupt on INT1 pad. Default value: 0 + * [1] INT2_DRDY_G: Gyroscope Data Ready on INT1 pad. Default value: 0. + * [0] INT2_DRDY_XL: Accelerometer Data Ready on INT1 pad. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_INT2_CTRL 0x0E + + +/** + * @brief Device identifier register. + * \code + * Read + * Default value:69 + * [7:0] This read-only register contains the device identifier + * \endcode +*/ +#define LSM6DS3_XG_WHO_AM_I_ADDR 0x0F + + +/** + * @brief Control Register 3 + * \code + * Read/write + * Default value: 0x00 + * [7] BOOT: Reboot memory content. Default value: 0 + * [6] BDU: Block Data Update. Default value: 0 + * [5] H_LACTIVE: Interrupt activation level. Default value: 0 + * [4] PP_OD: Push-pull/Open Drain selection on INT pad. Default value: 0 + * [3] SIM: SPI Serial Interface Mode selection. Default value: 0 + * [2] IF_INC: Register address automatically incremented during a multiple byte access with a serial interface (I2C or SPI). Default value: 0 + * [1] BLE: Big/Little Endian Data Selection. Default value: 0 + * [0] SW_RESET: Software Reset. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_CTRL3_C 0x12 + +/** + * @brief Control Register 4 + * \code + * Read/write + * Default value: 0x00 + * [7] BW_SCAL_ODR: Accelerometer bandwidth selection. Default value: 0 + * [6] SLEEP_G: Gyroscope sleep mode enable. Default value: 0 + * [5] INT2_on_INT1: All interrupt signals available on INT1 pad enable. Default value: 0 + * [4] This bit must be set to ‘0’ for the correct operation of the device + * [3] DRDY_MASK: Configuration 1(3) Data Available Enable bit. Default Value: 0 + * [2] I2C_disable Disable I2C interface. Default value: 0 + * [1] MODE3_EN Enable auxiliary SPI interface (Mode3, refer to Table 1.). Default value: 0 + * [0] STOP_ON_FTH Enable FIFO threshold level use. Default value: 0. + + * \endcode +*/ +#define LSM6DS3_XG_CTRL4_C 0x13 + +/** + * @brief Control Register 4 + * \code + * Read/write + * Default value: 0x00 + * [7:4] This bit must be set to ‘0’ for the correct operation of the device + * [3:2] ST_G[1:0]: Angular rate sensor Self Test Enable. Default value: 00 + * [1:0] ST_XL[1:0]: Linear acceleration sensor Self Test Enable. Default value: 00 + * \endcode +*/ +#define LSM6DS3_XG_CTRL5_C 0x14 + + +/** + * @brief Control Register 10 + * \code + * Read/write + * Default value: 0x38 + * [7:6] These bits must be set to ‘0’ for the correct operation of the device + * [5] Zen_G: Gyroscope’s Z-axis output enable. Default value: 1 + * [4] Yen_G: Gyroscope’s Y-axis output enable. Default value: 1 + * [3] Xen_G: Gyroscope’s X-axis output enable. Default value: 1 + * [2] FUNC_EN: Enable embedded functionalities (pedometer, tilt and significant motion) . Default value: 0 + * [1] PEDO_RST_STEP: Reset pedometer step counter . Default value: 0 + * [0] SIGN_MOTION_EN: Enable significant motion function. For a correct functionality of significant motion function, TILT_EN bit in FUNC_SRC (53h) register must be set to 1 . Default value: 1 + * \endcode +*/ +#define LSM6DS3_XG_CTRL10_C 0x19 + + +/** + * @brief Sensor hub Master config Register + * \code + * Read/write + * Default value: 0x00 + * [7] DRDY_ON_INT1:Manage the DRDY signal on INT1 pad. Default: 0 + * [6] DATA_VALID_SEL_FIFO: Selection of FIFO data-valid signal. Default value: 0 + * [5] This bit must be set to ‘0’ for the correct operation of the device + * [4] START_CONFIG: Sensor Hub trigger signal selection. Default value: 0 + * [3] PULL_UP_EN: Auxiliary I2C pull-up. Default value: 0 + * [2] PASS_THROUGH_MODE: I2C interface pass-through. Default value: 0 + * [1] IRON_EN:Enable soft iron correction algorithm for magnetometer. Default value: 0. + * [0] MASTER_ON: Sensor Hub I2C master enable. Default: 0 + * \endcode +*/ +#define LSM6DS3_XG_MASTER_CONFIG 0x1A + + +/** + * @brief Wake up interrupt source register + * \code + * Read + * Default value: output + * [7:6] This bit must be set to ‘0’ for the correct operation of the device + * [5] FF_IA: Free fall event detection status. Default: 0 + * [4] SLEEP_STATE_IA: Sleep event status. Default value: 0 + * [3] WU_IA: Wake up event detection status. Default + * [2] X_WU: detection status on X axis. Default value: 0 + * [1] Y_WU: detection status on Y axis. Default value: 0 + * [0] Z_WU: detection status on Z axis. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_WAKE_UP_SRC 0x1B + +/** + * @brief Tap source register + * \code + * Read + * Default value: output + * [7] This bit must be set to ‘0’ for the correct operation of the device + * [6] TAP_IA: Tap event detection status. Default: 0 + * [5] SINGLE_TAP: Single tap event status. Default value: 0 + * [4] DOUBLE_TAP: Double tap event detection status. Default value: 0 + * [3] TAP_SIGN: Sign of acceleration detected by tap event. Default: 0 + * [2] X_TAP: Tap event detection status on X axis. Default value: 0 + * [1] Y_TAP: Tap event detection status on Y axis. Default value: 0 + * [0] Z_TAP: Tap event detection status on Z axis. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_TAP_SRC 0x1C + +/** + * @brief Portrait, landscape face-up and face-down source register + * \code + * Read + * Default value: output + * [7] This bit must be set to ‘0’ for the correct operation of the device + * [6] D6D_IA: Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0 + * [5] ZH: Z-axis high event (over-threshold). Default value: 0 + * [4] ZL: Z-axis low event (under-threshold). Default value: 0 + * [5] YH: Y-axis high event (over-threshold). Default value: 0 + * [4] YL: Y-axis low event (under-threshold). Default value: 0 + * [5] X_H: X-axis high event (over-threshold). Default value: 0 + * [4] X_L: X-axis low event (under-threshold). Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_D6D_SRC 0x1D + +/** + * @brief Status register + * \code + * Read + * Default value: output + * [7:4] No meaning set + * [3] EV_BOOT: Boot running flag signal. Default value: 0 + * [2] No meaning set + * [1] GDA: Gyroscope new data avaialble. Default value: 0 + * [0] XLDA: Accelerometer new data avaialble. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_STATUS_REG 0x1E + +/** + * @brief FIFO status control register + * \code + * Read + * Default value: 0x00 + * [7:0] DIFF_FIFO_[7:0]: Number of unread words (16 bit axes) stored in FIFO . For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS2 (3Bh) + * \endcode +*/ +#define LSM6DS3_XG_FIFO_STATUS1 0x3A + +/** + * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. + * \code + * Read + * Default value: 0x00 + * [7] FTH FIFO watermark status. Deafult value: 0 + * [6] OVER_RUN: FIFO overrun status. Default value: 0 + * [5] FIFO_FULL: FIFO full status. Default value: 0 + * [5] FIFO_EMPTY: FIFO empty bit. Default value: 0; 0: FIFO contains data; 1: FIFO is empty + * [3:0] DIFF_FIFO_[11:8] Number of unread words (16 bit axes) stored in FIFO : For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS1 (3Ah) + * \endcode +*/ +#define LSM6DS3_XG_FIFO_STATUS2 0x3B + +/** + * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0 + * \code + * Read + * Default value: 0x00 + * [7:0] FIFO_PATTERN_[7:0] : Word of recursive pattern read at the next reading + * \endcode +*/ +#define LSM6DS3_XG_FIFO_STATUS3 0x3C + +/** + * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0 + * \code + * Read + * Default value: 0x00 + * [1:0] FIFO_PATTERN_[9:8] : Word of recursive pattern read at the next reading + * \endcode +*/ +#define LSM6DS3_XG_FIFO_STATUS4 0x3D + +/** + * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. + * \code + * Read + * Default value: 0x00 + * [4:0] FIFO_PATTERN_[9:8] : Word of recursive pattern read at the next reading + * \endcode +*/ +#define LSM6DS3_XG_FIFO_STATUS4 0x3D + +/** + * @brief FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. + * \code + * Read + * Default value: 0x00 + * [7:0] DATA_OUT_FIFO_L_[7:0]: FIFO data output (First byte) + * \endcode +*/ +#define LSM6DS3_XG_FIFO_DATA_OUT_L 0x3E + +/** + * @brief FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. + * \code + * Read + * Default value: 0x00 + * [7:0] DATA_OUT_FIFO_H_[7:0]: FIFO data output (second byte) + * \endcode +*/ +#define LSM6DS3_XG_FIFO_DATA_OUT_H 0x3F + +/** + * @brief Time stamp first byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). + * \code + * Read + * Default value: output + * [7:0] TIMESTAMP0_[7:0]: FIFO first byte data output + * \endcode +*/ +#define LSM6DS3_XG_TIMESTAMP0_REG 0x40 + +/** + * @brief Time stamp second byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). + * \code + * Read + * Default value: output + * [7:0] TIMESTAMP1_[7:0]: FIFO second byte data output + * \endcode +*/ +#define LSM6DS3_XG_TIMESTAMP1_REG 0x41 + +/** + * @brief Time stamp third byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). + * \code + * Read + * Default value: output + * [7:0] TIMESTAMP2_[7:0]: FIFO third byte data output + * \endcode +*/ +#define LSM6DS3_XG_TIMESTAMP2_REG 0x42 + +/** + * @brief Step counter output register (r). + * \code + * Read + * Default value: output + * [7:0] STEP_COUNTER_L_[7:0]: Step counter output (LSbyte) + * \endcode +*/ +#define LSM6DS3_XG_STEP_COUNTER_L 0x4B + +/** + * @brief Step counter output register (r). + * \code + * Read + * Default value: output + * [7:0] STEP_COUNTER_H_[7:0]: Step counter output (MSbyte) + * \endcode +*/ +#define LSM6DS3_XG_STEP_COUNTER_H 0x4C + +/** + * @brief Significant motion, tilt, step detector, soft iron and sensor hub interrupt source register + * \code + * Read + * Default value: output + * [7] This bit must be set to ‘0’ for the correct operation of the device + * [6] SIGN_MOTION_IA: Significant motion event detection status. Default value: 0 + * [5] TILT_IA: Tilt event detection status. Default value: 0 + * [5] STEP_DETECTED: Step detector event detection status. Default value: 0 + * [3:2] This bit must be set to ‘0’ for the correct operation of the device + * [1] SI_END_OP:Soft iron calculation status. Default value: 0 + * [0] SENSORHUB_END_OP:Senso hub communication status. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_FUNC_SRC 0x53 + +/** + * @brief Time stamp, pedometer, tilt, filtering, and tap recognition functions configuration register + * \code + * Read/write + * Default value: 0x00 + * [7] TIMER_EN: Time stamp count enable, output data are collected in TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h), TIMESTAMP2_REG (42h) register. Default: 0 + * [6] PEDO_EN: Pedometer algorithm enable(1). Default value: 0 + * [5] TILT_EN: Tilt calculation enable.(2) Default value: 0 + * [4] This bit must be set to ‘0’ for the correct operation of the device + * [3] TAP_X_EN: Enable X direction in tap recognition. Default value: 0 + * [2] TAP_Y_EN: Enable Z direction in tap recognition. Default value: 0 + * [1] TAP_Z_EN: Enable Z direction in tap recognition. Default value: 0 + * [0] LIR: Relatch of the time stamp, pedometer, tilt, filtering, and tap recognition functions routed to PINs. + * \endcode +*/ +#define LSM6DS3_XG_TAP_CFG 0x58 + +/** + * @brief Portrait/landscape position and tap function threshold register + * \code + * Read/write + * Default value: 0x00 + * [7] This bit must be set to ‘0’ for the correct operation of the device + * [6:5] SIXD_THS[1:0]: Threshold for D6D function. Default value: 00 + * [4:0] TAP_THS[4:0]: Threshold for tap recognition. Default value: 0000 + * \endcode +*/ +#define LSM6DS3_XG_TAP_THS_6D 0x59 + +/** + * @brief Tap recognition function setting register (r/w) + * \code + * Read/write + * Default value: 0x00 + * [7:4] DUR[3:0]: Duration of maximum time gap for double tap recognition. Default: 0000 + * [3:2] QUIET[1:0]: Expected quiet time after a tap detection. Default value: 00 + * [1:0] SHOCK[1:0]: Maximum duration of over-threshold event. Default value: 00 + * \endcode +*/ +#define LSM6DS3_XG_INT_DUR2 0x5A + +/** + * @brief Tap recognition function setting register + * \code + * Read/write + * Default value: 0x00 + * [7] SINGLE_DOUBLE_TAP: Single/double tap event detection. Default: 0 + * [6] INACTIVITY: Inactivity event enable. Default value: 0 + * [5:0] WK_THS[5:0]:Threshold for wake-up. Default value: 0000 + * \endcode +*/ +#define LSM6DS3_XG_WAKE_UP_THS 0x5B + +/** + * @brief Free-fall, wake-up, time stamp and sleep mode functions duration setting register (r/w). + * \code + * Read/write + * Default value: 0x00 + * [7] FF_DUR5:Free fall duration event. Default: 0 + * [6:5] WAKE_DUR[1:0]: Wake up duration event. Default: 00 + * [4] TIMER_HR: Time stamp register resolution setting(1). Default value: 0 + * [3:0] SLEEP_DUR[3:0] : Duration to go in sleep mode. Default value: 0000 + * \endcode +*/ +#define LSM6DS3_XG_WAKE_UP_DUR 0x5C + +/** + * @brief Free-fall function duration setting register + * \code + * Read/write + * Default value: 0x00 + * [7:3] FF_DUR[4:0]: Free fall duration event. Default: 0. For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch) configuration + * [2:0] FF_THS[2:0]: Free fall threshold setting. Default: 000. + * \endcode +*/ +#define LSM6DS3_XG_WAKE_FREE_FALL 0x5D + +/** + * @brief Functions routing on INT1 register + * \code + * Read/write + * Default value: 0x00 + * [7] INT1_INACT_STATE: Routing on INT1 of inactivity mode. Default: 0 + * [6] INT1_SINGLE_TAP: Single tap recognition routing on INT1. Default: 0 + * [5] INT1_WU: Routing of wake-up event on INT1. Default value: 0 + * [4] INT1_FF: Routing of free-fall event on INT1. Default value: 0 + * [3] INT1_TAP: Routing of tap event on INT1. Default value: 0 + * [2] INT1_6D: Routing of 6D event on INT1. Default value: 0 + * [1] INT1_TILT: Routing of tilt event on INT1. Default value: 0 + * [0] INT1_TIMER: Routing of end counter event of timer on INT1. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_MD1_CFG 0x5E + +/** + * @brief Functions routing on INT2 register + * \code + * Read/write + * Default value: 0x00 + * [7] INT2_INACT_STATE: Routing on INT1 of inactivity mode. Default: 0 + * [6] INT2_SINGLE_TAP: Single tap recognition routing on INT1. Default: 0 + * [5] INT2_WU: Routing of wake-up event on INT1. Default value: 0 + * [4] INT2_FF: Routing of free-fall event on INT1. Default value: 0 + * [3] INT2_TAP: Routing of tap event on INT1. Default value: 0 + * [2] INT2_6D: Routing of 6D event on INT1. Default value: 0 + * [1] INT2_TILT: Routing of tilt event on INT1. Default value: 0 + * [0] INT2_TIMER: Routing of end counter event of timer on INT1. Default value: 0 + * \endcode +*/ +#define LSM6DS3_XG_MD2_CFG 0x5F + +/***************************************** SENSORHUB REGISTERS ********************************************/ + +/** + * @brief SENSORHUB REGISTER 1 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB1[7:0]: SLV0 first external sensor, first byte of the first axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB1_REG 0x2E + +/** + * @brief SENSORHUB REGISTER 2 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB2[7:0]: SLV0 first external sensor, second byte of the first axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB2_REG 0x2F + +/** + * @brief SENSORHUB REGISTER 3 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB3[7:0]: SLV0 first external sensor, first byte of the second axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB3_REG 0x30 + +/** + * @brief SENSORHUB REGISTER 4 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB4[7:0]: SLV0 first external sensor, second byte of the second axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB4_REG 0x31 + +/** + * @brief SENSORHUB REGISTER 5 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB5[7:0]: SLV0 first external sensor, second byte of the second axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB5_REG 0x32 + +/** + * @brief SENSORHUB REGISTER 6 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB6[7:0]: SLV0 first external sensor, second byte of the third axis + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB6_REG 0x33 + +/** + * @brief SENSORHUB REGISTER 7 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB7[7:0]: SLV1 second external sensor, first byte of the first axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB7_REG 0x34 + +/** + * @brief SENSORHUB REGISTER 8 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB8[7:0]: SLV1 second external sensor, second byte of the first axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB8_REG 0x35 + +/** + * @brief SENSORHUB REGISTER 9 : SLV1 second external sensor,, second axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB9[7:0]: SLV1 second external sensor, first byte of the second axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB9_REG 0x36 + +/** + * @brief SLV1 second external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB10[7:0]: SLV1 second external sensor, second byte of the second axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB10_REG 0x37 + +/** + * @brief SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB11[7:0]: SLV1 second external sensor, first byte of the third axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB11_REG 0x38 + +/** + * @brief SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement + * \code + * Read + * Default value: 0x00 + * [7:0] SHUB12[7:0]: SLV1 second external sensor, second byte of the third axis. + * \endcode +*/ +#define LSM6DS3_XG_SENSORHUB12_REG 0x39 + + + + +/***************************************** GYROSCOPE REGISTERS ********************************************/ + +/** + * @brief Angular rate sensor Control Register 2 + * \code + * Read/write + * Default value: 0x00 + * [7:4] ODR_G[3:0]: Gyroscope output data rate selection + * [3:2] FS_G[1-0]: Gyroscope full-scale selection + * [1] FS_125: Gyroscope full-scale at 125 dps + * [0] This bit must be set to ‘0’ for the correct operation of the device + * \endcode + */ +#define LSM6DS3_XG_CTRL2_G 0x11 + + +/** + * @brief Angular rate sensor Control Register 6 + * \code + * Read/write + * Default value: 0x00 + * [7] TRIG_EN: Data edge sensitive trigger Enable. Default value: 0 + * [6] LVLen: Data level sensitive trigger Enable. Default value: 0 + * [5] LVL2en: Level sensitive latched Enable. Default value: 0 + * [4] XL_H_MODE: High Performance operating mode disable for accelerometer(1). Default value: 0 + * [3:0] This bit must be set to ‘0’ for the correct operation of the device + * \endcode + */ +#define LSM6DS3_XG_CTRL6_G 0x15 + + +/** +* @brief Angular rate sensor Control Register 7 +* \code +* Read/write +* Default value: 0x00 +* [7] G_H_MODE: High Performance operating mode disable for Gyroscope(1) . Default: 0 +* [6] HP_EN: High Pass filter Enable. Default Value: 0 +* [5:4] HPCF_G[1:0]: Gyroscope High Pass filter Cut Off frequency selection. Default value: 00 +* [3:0] This bit must be set to ‘0’ for the correct operation of the device +* \endcode +*/ +#define LSM6DS3_XG_CTRL7_G 0x16 + +/** + * @brief Gyroscope data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_X_L_G 0x22 + + +/** + * @brief Gyroscope data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_X_H_G 0x23 + + +/** + * @brief Gyroscope data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Y_L_G 0x24 + + +/** + * @brief Gyroscope data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Y_H_G 0x25 + + +/** + * @brief Gyroscope data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Z_L_G 0x26 + + +/** + * @brief Gyroscope data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Z_H_G 0x27 + + + +/*************************************** ACCELEROMETER REGISTERS *******************************************/ + +/** + * @brief Linear acceleration sensor Control Register 1 + * \code + * Read/write + * Default value: 0x00 + * [7:4] ODR_XL3-0: Accelerometer Output data rate and power mode selection + * [3:2] FS_XL1-0: Accelerometer full-scale selection + * [1:0] BW_XL1-0: Anti-aliasing filter bandwidth selection + * \endcode + */ +#define LSM6DS3_XG_CTRL1_XL 0x10 + +/** +* @brief XL sensor Control Register 8 +* \code +* Read/write +* Default value: 0x00 +* [7:3] This bit must be set to ‘0’ for the correct operation of the device +* [2] SLOPE_FDS: Enable HP filter on output registers and FIFO. Default value: 0 +* [1:0] This bit must be set to ‘0’ for the correct operation of the device +* \endcode +*/ +#define LSM6DS3_XG_CTRL8_XL 0x17 + +/** + * @brief Linear acceleration sensor Control Register 9 + * \code + * Read/write + * Default value: 0x38 + * [7:6] These bits must be set to ‘0’ for the correct operation of the device + * [5] Zen_XL: Accelerometers’s Z-axis output enable + * [4] Yen_XL: Accelerometers’s Y-axis output enable + * [3] Xen_XL: Accelerometers’s X-axis output enable + * [2:0] These bits must be set to ‘0’ for the correct operation of the device + * \endcode +*/ +#define LSM6DS3_XG_CTRL9_XL 0x18 + + +/** + * @brief Accelerometer data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_X_L_XL 0x28 + + +/** + * @brief Accelerometer data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_X_H_XL 0x29 + + +/** + * @brief Accelerometer data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Y_L_XL 0x2A + + +/** + * @brief Accelerometer data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Y_H_XL 0x2B + + +/** + * @brief Accelerometer data (LSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Z_L_XL 0x2C + + +/** + * @brief Accelerometer data (MSB) + * \code + * Read + * \endcode + */ +#define LSM6DS3_XG_OUT_Z_H_XL 0x2D + +/******************************************************************************/ +/************* END ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ +/******************************************************************************/ + + +/************************************** COMMON REGISTERS VALUE *******************************************/ + +/** +* @brief Device Address +*/ +#define LSM6DS3_ADDRESS_LOW 0xD4 // SAD[0] = 0 +#define LSM6DS3_ADDRESS_HIGH 0xD6 // SAD[0] = 1 +#define LSM6DS3_XG_MEMS_ADDRESS LSM6DS3_ADDRESS_LOW // SAD[0] = 0 + + +/** + * @brief Device Identifier. Default value of the WHO_AM_I register. + */ +#define I_AM_LSM6DS3_XG ((uint8_t)0x69) + + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface (I2C or SPI). Default value of the + * LSM6DS3_XG_CTRL3_C register. + */ +#define LSM6DS3_XG_IF_INC ((uint8_t)0x04) + +#define LSM6DS3_XG_IF_INC_MASK ((uint8_t)0x04) + +/** @defgroup LSM6DS3_XG_FIFO_Output_Data_Rate_Selection_FIFO_CTRL5 LSM6DS3_XG_FIFO_Output_Data_Rate_Selection_FIFO_CTRL5 + * @{ + */ +#define LSM6DS3_XG_FIFO_ODR_NA ((uint8_t)0x00) /*!< FIFO ODR NA */ +#define LSM6DS3_XG_FIFO_ODR_10HZ ((uint8_t)0x08) /*!< FIFO ODR 10Hz */ +#define LSM6DS3_XG_FIFO_ODR_25HZ ((uint8_t)0x10) /*!< FIFO ODR 25Hz */ +#define LSM6DS3_XG_FIFO_ODR_50HZ ((uint8_t)0x18) /*!< FIFO ODR 50Hz */ +#define LSM6DS3_XG_FIFO_ODR_100HZ ((uint8_t)0x20) /*!< FIFO ODR 100Hz */ +#define LSM6DS3_XG_FIFO_ODR_200HZ ((uint8_t)0x28) /*!< FIFO ODR 200Hz */ +#define LSM6DS3_XG_FIFO_ODR_400HZ ((uint8_t)0x30) /*!< FIFO ODR 400Hz */ +#define LSM6DS3_XG_FIFO_ODR_800HZ ((uint8_t)0x38) /*!< FIFO ODR 800Hz */ +#define LSM6DS3_XG_FIFO_ODR_1600HZ ((uint8_t)0x40) /*!< FIFO ODR 1600Hz */ +#define LSM6DS3_XG_FIFO_ODR_3300HZ ((uint8_t)0x48) /*!< FIFO ODR 3300Hz */ +#define LSM6DS3_XG_FIFO_ODR_6600HZ ((uint8_t)0x50) /*!< FIFO ODR 6600Hz */ + +#define LSM6DS3_XG_FIFO_ODR_MASK ((uint8_t)0x78) +/** + * @} + */ + +/** @defgroup LSM6DS3_XG_FIFO_Mode_Selection_FIFO_CTRL5 LSM6DS3_XG_FIFO_Mode_Selection_FIFO_CTRL5 + * @{ + */ +#define LSM6DS3_XG_FIFO_MODE_BYPASS ((uint8_t)0x00) /*!< BYPASS Mode. FIFO turned off */ +#define LSM6DS3_XG_FIFO_MODE_FIFO ((uint8_t)0x01) /*!< FIFO Mode. Stop collecting data when FIFO is full */ +#define LSM6DS3_XG_FIFO_MODE_CONTINUOUS_THEN_FIFO ((uint8_t)0x03) /*!< CONTINUOUS mode until trigger is deasserted, then FIFO mode */ +#define LSM6DS3_XG_FIFO_MODE_BYPASS_THEN_CONTINUOUS ((uint8_t)0x04) /*!< BYPASS mode until trigger is deasserted, then CONTINUOUS mode */ +#define LSM6DS3_XG_FIFO_MODE_CONTINUOUS_OVERWRITE ((uint8_t)0x05) /*!< CONTINUOUS mode. If the FIFO is full the new sample overwrite the older one */ + +#define LSM6DS3_XG_FIFO_MODE_MASK ((uint8_t)0x07) +/** + * @} + */ + + +/************************************** GYROSCOPE REGISTERS VALUE *******************************************/ + + +/** @addtogroup LSM6DS3_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G LSM6DS3_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G + * @{ + */ +#define LSM6DS3_G_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ +#define LSM6DS3_G_ODR_13HZ ((uint8_t)0x10) /*!< Output Data Rate: 13 Hz*/ +#define LSM6DS3_G_ODR_26HZ ((uint8_t)0x20) /*!< Output Data Rate: 26 Hz*/ +#define LSM6DS3_G_ODR_52HZ ((uint8_t)0x30) /*!< Output Data Rate: 52 Hz */ +#define LSM6DS3_G_ODR_104HZ ((uint8_t)0x40) /*!< Output Data Rate: 104 Hz */ +#define LSM6DS3_G_ODR_208HZ ((uint8_t)0x50) /*!< Output Data Rate: 208 Hz */ +#define LSM6DS3_G_ODR_416HZ ((uint8_t)0x60) /*!< Output Data Rate: 416 Hz */ +#define LSM6DS3_G_ODR_833HZ ((uint8_t)0x70) /*!< Output Data Rate: 833 Hz */ +#define LSM6DS3_G_ODR_1660HZ ((uint8_t)0x80) /*!< Output Data Rate: 1.66 kHz */ + +#define LSM6DS3_G_ODR_MASK ((uint8_t)0xF0) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Gyroscope_Full_Scale_Selection_CTRL2_G LSM6DS3_XG_Gyroscope_Full_Scale_Selection_CTRL2_G + * @{ + */ +#define LSM6DS3_G_FS_125_DISABLE ((uint8_t)0x00) /*!< Full scale: 125 dps enable: disable */ +#define LSM6DS3_G_FS_125_ENABLE ((uint8_t)0x02) /*!< Full scale: 125 dps enable: enable */ + +#define LSM6DS3_G_FS_125_MASK ((uint8_t)0x02) + +#define LSM6DS3_G_FS_245 ((uint8_t)0x00) /*!< Full scale: 245 dps*/ +#define LSM6DS3_G_FS_500 ((uint8_t)0x04) /*!< Full scale: 500 dps */ +#define LSM6DS3_G_FS_1000 ((uint8_t)0x08) /*!< Full scale: 1000 dps */ +#define LSM6DS3_G_FS_2000 ((uint8_t)0x0C) /*!< Full scale: 2000 dps */ + +#define LSM6DS3_G_FS_MASK ((uint8_t)0x0C) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL10_C + * @{ + */ +#define LSM6DS3_G_ZEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Z-axis output enable: disable */ +#define LSM6DS3_G_ZEN_ENABLE ((uint8_t)0x20) /*!< Gyroscope’s Z-axis output enable: enable */ + +#define LSM6DS3_G_ZEN_MASK ((uint8_t)0x20) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL10_C + * @{ + */ +#define LSM6DS3_G_YEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Y-axis output enable: disable */ +#define LSM6DS3_G_YEN_ENABLE ((uint8_t)0x10) /*!< Gyroscope’s Y-axis output enable: enable */ + +#define LSM6DS3_G_YEN_MASK ((uint8_t)0x10) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL10_C + * @{ + */ +#define LSM6DS3_G_XEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s X-axis output enable: disable */ +#define LSM6DS3_G_XEN_ENABLE ((uint8_t)0x08) /*!< Gyroscope’s X-axis output enable: enable */ + +#define LSM6DS3_G_XEN_MASK ((uint8_t)0x08) + +/** + * @} + */ + + +/************************************ ACCELEROMETER REGISTERS VALUE *****************************************/ + +/** @addtogroup LSM6DS3_XG_Accelerometer_Output_Data_Rate_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Output_Data_Rate_Selection_CTRL1_XL + * @{ + */ +#define LSM6DS3_XL_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ +#define LSM6DS3_XL_ODR_13HZ ((uint8_t)0x10) /*!< Output Data Rate: 13 Hz*/ +#define LSM6DS3_XL_ODR_26HZ ((uint8_t)0x20) /*!< Output Data Rate: 26 Hz*/ +#define LSM6DS3_XL_ODR_52HZ ((uint8_t)0x30) /*!< Output Data Rate: 52 Hz */ +#define LSM6DS3_XL_ODR_104HZ ((uint8_t)0x40) /*!< Output Data Rate: 104 Hz */ +#define LSM6DS3_XL_ODR_208HZ ((uint8_t)0x50) /*!< Output Data Rate: 208 Hz */ +#define LSM6DS3_XL_ODR_416HZ ((uint8_t)0x60) /*!< Output Data Rate: 416 Hz */ +#define LSM6DS3_XL_ODR_833HZ ((uint8_t)0x70) /*!< Output Data Rate: 833 Hz */ +#define LSM6DS3_XL_ODR_1660HZ ((uint8_t)0x80) /*!< Output Data Rate: 1.66 kHz */ +#define LSM6DS3_XL_ODR_3330HZ ((uint8_t)0x90) /*!< Output Data Rate: 3.33 kHz */ +#define LSM6DS3_XL_ODR_6660HZ ((uint8_t)0xA0) /*!< Output Data Rate: 6.66 kHz */ + +#define LSM6DS3_XL_ODR_MASK ((uint8_t)0xF0) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Accelerometer_Full_Scale_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Full_Scale_Selection_CTRL1_XL + * @{ + */ +#define LSM6DS3_XL_FS_2G ((uint8_t)0x00) /*!< Full scale: +- 2g */ +#define LSM6DS3_XL_FS_4G ((uint8_t)0x08) /*!< Full scale: +- 4g */ +#define LSM6DS3_XL_FS_8G ((uint8_t)0x0C) /*!< Full scale: +- 8g */ +#define LSM6DS3_XL_FS_16G ((uint8_t)0x04) /*!< Full scale: +- 16g */ + +#define LSM6DS3_XL_FS_MASK ((uint8_t)0x0C) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL1_XL + * @{ + */ +#define LSM6DS3_XL_BW_400HZ ((uint8_t)0x00) /*!< Anti-aliasing filter bandwidht: 400 Hz */ +#define LSM6DS3_XL_BW_200HZ ((uint8_t)0x01) /*!< Anti-aliasing filter bandwidht: 200 Hz */ +#define LSM6DS3_XL_BW_100HZ ((uint8_t)0x02) /*!< Anti-aliasing filter bandwidht: 100 Hz */ +#define LSM6DS3_XL_BW_50HZ ((uint8_t)0x03) /*!< Anti-aliasing filter bandwidht: 50 Hz */ + +#define LSM6DS3_XL_BW_MASK ((uint8_t)0x03) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL9_XL + * @{ + */ +#define LSM6DS3_XL_ZEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Z-axis output enable: disable */ +#define LSM6DS3_XL_ZEN_ENABLE ((uint8_t)0x20) /*!< Accelerometer’s Z-axis output enable: enable */ + +#define LSM6DS3_XL_ZEN_MASK ((uint8_t)0x20) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL9_XL + * @{ + */ +#define LSM6DS3_XL_YEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Y-axis output enable: disable */ +#define LSM6DS3_XL_YEN_ENABLE ((uint8_t)0x10) /*!< Accelerometer’s Y-axis output enable: enable */ + +#define LSM6DS3_XL_YEN_MASK ((uint8_t)0x10) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL9_XL + * @{ + */ +#define LSM6DS3_XL_XEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s X-axis output enable: disable */ +#define LSM6DS3_XL_XEN_ENABLE ((uint8_t)0x08) /*!< Accelerometer’s X-axis output enable: enable */ + +#define LSM6DS3_XL_XEN_MASK ((uint8_t)0x08) + +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_FF_DUR5_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_FF_DUR5_Selection_WAKE_UP_DUR + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_DEFAULT ((uint8_t)0x00) + +#define LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_WAKE_DUR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_WAKE_DUR_Selection_WAKE_UP_DUR + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_DEFAULT ((uint8_t)0x00) + +#define LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_MASK ((uint8_t)0x60) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_TIMER_HR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_TIMER_HR_Selection_WAKE_UP_DUR + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_DEFAULT ((uint8_t)0x00) + +#define LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_MASK ((uint8_t)0x10) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_SLEEP_DUR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_SLEEP_DUR_Selection_WAKE_UP_DUR + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_DEFAULT ((uint8_t)0x00) + +#define LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_MASK ((uint8_t)0x0F) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_FF_DUR_Selection_FREE_FALL LSM6DS3_XG_Accelerometer_FF_DUR_Selection_FREE_FALL + * @{ + */ +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_DEFAULT ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_TYPICAL ((uint8_t)0x30) + +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK ((uint8_t)0xF8) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_FF_THS_Selection_FREE_FALL LSM6DS3_XG_Accelerometer_FF_THS_Selection_FREE_FALL + * @{ + */ +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_156MG ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_219MG ((uint8_t)0x01) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_250MG ((uint8_t)0x02) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_312MG ((uint8_t)0x03) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_344MG ((uint8_t)0x04) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_406MG ((uint8_t)0x05) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_469MG ((uint8_t)0x06) +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_500MG ((uint8_t)0x07) + +#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK ((uint8_t)0x07) + +/** + * @} + */ + + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_INACT_STATE_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_INACT_STATE_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_ENABLE ((uint8_t)0x80) + +#define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_MASK ((uint8_t)0x80) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_SINGLE_TAP_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_SINGLE_TAP_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_ENABLE ((uint8_t)0x40) + +#define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_MASK ((uint8_t)0x40) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_WU_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_WU_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_WU_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_WU_ENABLE ((uint8_t)0x20) + +#define LSM6DS3_XG_MD1_CFG_INT1_WU_MASK ((uint8_t)0x20) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_FF_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_FF_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_FF_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_FF_ENABLE ((uint8_t)0x10) + +#define LSM6DS3_XG_MD1_CFG_INT1_FF_MASK ((uint8_t)0x10) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_DOUBLE_TAP_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_DOUBLE_TAP_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_ENABLE ((uint8_t)0x08) + +#define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_MASK ((uint8_t)0x08) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_6D_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_6D_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_6D_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_6D_ENABLE ((uint8_t)0x04) + +#define LSM6DS3_XG_MD1_CFG_INT1_6D_MASK ((uint8_t)0x04) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_TILT_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_TILT_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_TILT_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_TILT_ENABLE ((uint8_t)0x02) + +#define LSM6DS3_XG_MD1_CFG_INT1_TILT_MASK ((uint8_t)0x02) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_TIMER_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_TIMER_Selection_MD1_CFG + * @{ + */ +#define LSM6DS3_XG_MD1_CFG_INT1_TIMER_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_MD1_CFG_INT1_TIMER_ENABLE ((uint8_t)0x01) + +#define LSM6DS3_XG_MD1_CFG_INT1_TIMER_MASK ((uint8_t)0x01) + +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_FF_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_FF_IA_Enable_WAKE_UP_SRC + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_ENABLE ((uint8_t)0x20) + +#define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_MASK ((uint8_t)0x20) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_SLEEP_STATE_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_SLEEP_STATE_IA_Enable_WAKE_UP_SRC + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_ENABLE ((uint8_t)0x10) + +#define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_MASK ((uint8_t)0x10) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_WU_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_WU_IA_Enable_WAKE_UP_SRC + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_ENABLE ((uint8_t)0x08) + +#define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_MASK ((uint8_t)0x08) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_X_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_X_WU_Enable_WAKE_UP_SRC + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_SRC_X_WU_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_UP_SRC_X_WU_ENABLE ((uint8_t)0x04) + +#define LSM6DS3_XG_WAKE_UP_SRC_X_WU_MASK ((uint8_t)0x04) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_Y_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_Y_WU_Enable_WAKE_UP_SRC + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_ENABLE ((uint8_t)0x02) + + +#define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_MASK ((uint8_t)0x02) +/** + * @} + */ + +/** @addtogroup LSM6DS3_XG_Accelerometer_Z_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_Z_WU_Enable_WAKE_UP_SRC + * @{ + */ +#define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_DISABLE ((uint8_t)0x00) +#define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_ENABLE ((uint8_t)0x01) + +#define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_MASK ((uint8_t)0x01) +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup LSM6DS3_Imported_Functions LSM6DS3_Imported_Functions + * @{ + */ + +/* Six axes sensor IO functions */ +extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Init( void ); +extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Write( uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToWrite ); +extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Read( uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToRead ); +extern void LSM6DS3_IO_ITConfig( void ); + +/** + * @} + */ + +/** @addtogroup LSM6DS3_Exported_Types LSM6DS3_Exported_Types + * @{ + */ +/** + * @brief LSM6DS3 driver extended internal structure definition + */ +typedef struct +{ + IMU_6AXES_StatusTypeDef (*Enable_Free_Fall_Detection) (void); + IMU_6AXES_StatusTypeDef (*Disable_Free_Fall_Detection) (void); + IMU_6AXES_StatusTypeDef (*Get_Status_Free_Fall_Detection) (uint8_t *); +} LSM6DS3_DrvExtTypeDef; + +/** + * @} + */ + +/** @addtogroup LSM6DS3_Exported_Variables LSM6DS3_Exported_Variables + * @{ + */ + +/* Six axes sensor driver structure */ +extern IMU_6AXES_DrvTypeDef LSM6DS3Drv; +extern IMU_6AXES_DrvExtTypeDef LSM6DS3Drv_ext; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LSM6DS3_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/MCU_Interface.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/MCU_Interface.h new file mode 100644 index 000000000..1a801cee1 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/MCU_Interface.h @@ -0,0 +1,152 @@ +/** + * @file MCU_Interface.h + * @author VMA division - AMS + * @version V2.0.2 + * @date Febrary 7, 2015 + * @brief Header file for low level SPIRIT SPI driver. + * @details + * + * This header file constitutes an interface to the SPI driver used to + * communicate with Spirit. + * It exports some function prototypes to write/read registers and FIFOs + * and to send command strobes. + * Since the Spirit libraries are totally platform independent, the implementation + * of these functions are not provided here. The user have to implement these functions + * taking care to keep the exported prototypes. + * + * These functions are: + * + *
    + *
  • SpiritSpiInit + *
  • SpiritSpiWriteRegisters + *
  • SpiritSpiReadRegisters + *
  • SpiritSpiCommandStrobes + *
  • SpiritSpiWriteLinearFifo + *
  • SpiritSpiReadLinearFifo + *
+ * + * @note An example of SPI driver implementation is available in the Sdk_Eval library. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * THIS SOURCE CODE IS PROTECTED BY A LICENSE. + * FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED + * IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. + * + *

© COPYRIGHT 2015 STMicroelectronics

+ */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MCU_INTERFACE_H +#define __MCU_INTERFACE_H + + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** @defgroup SPIRIT_SPI_Driver SPI Driver + * @brief Header file for low level SPIRIT SPI driver. + * @details See the file @ref MCU_Interface.h for more details. + * @{ + */ + + + +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @} + */ + + + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** + * @} + */ + + + +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** + * @} + */ + + + +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +typedef SpiritStatus StatusBytes; + +void SdkEvalSpiInit(void); +StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); +StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); +StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode); +StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer); +StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer); + +void SdkEvalEnterShutdown(void); +void SdkEvalExitShutdown(void); +SpiritFlagStatus SdkEvalCheckShutdown(void); + +#define SpiritEnterShutdown SdkEvalEnterShutdown +#define SpiritExitShutdown SdkEvalExitShutdown +#define SpiritCheckShutdown (SpiritFlagStatus)SdkEvalCheckShutdown + + +#define SpiritSpiInit SdkEvalSpiInit +#define SpiritSpiWriteRegisters(cRegAddress, cNbBytes, pcBuffer) SdkEvalSpiWriteRegisters(cRegAddress, cNbBytes, pcBuffer) +#define SpiritSpiReadRegisters(cRegAddress, cNbBytes, pcBuffer) SdkEvalSpiReadRegisters(cRegAddress, cNbBytes, pcBuffer) +#define SpiritSpiCommandStrobes(cCommandCode) SdkEvalSpiCommandStrobes(cCommandCode) +#define SpiritSpiWriteLinearFifo(cNbBytes, pcBuffer) SdkEvalSpiWriteFifo(cNbBytes, pcBuffer) +#define SpiritSpiReadLinearFifo(cNbBytes, pcBuffer) SdkEvalSpiReadFifo(cNbBytes, pcBuffer) + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT1_Util.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT1_Util.h new file mode 100644 index 000000000..45a1e950f --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT1_Util.h @@ -0,0 +1,117 @@ +/** + * @file SPIRIT1_Util.h + * @author High End Analog & RF BU - AMS / ART Team IMS-Systems Lab + * @version V3.0.1 + * @date November 19, 2012 + * @brief Identification functions for SPIRIT DK. + * @details + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * THIS SOURCE CODE IS PROTECTED BY A LICENSE. + * FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED + * IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. + * + *

© COPYRIGHT 2012 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT1_UTIL_H +#define __SPIRIT1_UTIL_H + + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Config.h" +#include "radio_gpio.h" + +#ifdef __cplusplus + "C" { +#endif + + +/** + * @addtogroup ST_SPIRIT1 + * @{ + */ + +typedef struct +{ + uint16_t nSpiritVersion; + SpiritVersion xSpiritVersion; +}SpiritVersionMap; + +#define CUT_MAX_NO 3 +#define CUT_2_1v3 0x0103 +#define CUT_2_1v4 0x0104 +#define CUT_3_0 0x0130 + +/** + * @brief Range extender type + */ +typedef enum +{ + RANGE_EXT_NONE = 0x00, + RANGE_EXT_SKYWORKS_169, + RANGE_EXT_SKYWORKS_868 +} RangeExtType; + +/** + * @addgroup SPIRIT1_Util_FUNCTIONS + * @{ + */ +void SpiritManagementIdentificationRFBoard(void); + +RangeExtType SpiritManagementGetRangeExtender(void); +void SpiritManagementSetRangeExtender(RangeExtType xRangeType); +void SpiritManagementRangeExtInit(void); +void SpiritManagementSetBand(uint8_t value); +uint8_t SpiritManagementGetBand(void); + +uint8_t SdkEvalGetHasEeprom(void); + +void Spirit1InterfaceInit(void); +void Spirit1GpioIrqInit(SGpioInit *pGpioIRQ); +void Spirit1RadioInit(SRadioInit *pRadioInit); +void Spirit1SetPower(uint8_t cIndex, float fPowerdBm); +void Spirit1PacketConfig(void); +void Spirit1SetPayloadlength(uint8_t length); +void Spirit1SetDestinationAddress(uint8_t address); +void Spirit1EnableTxIrq(void); +void Spirit1EnableRxIrq(void); +void Spirit1DisableIrq(void); +void Spirit1SetRxTimeout(float cRxTimeOut); +void Spirit1EnableSQI(void); +void Spirit1SetRssiTH(int dbmValue); +float Spirit1GetRssiTH(void); +void Spirit1ClearIRQ(void); +void Spirit1StartRx(void); +void Spirit1GetRxPacket(uint8_t *buffer, uint8_t size ); +void Spirit1StartTx(uint8_t *buffer, uint8_t size); + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +#ifdef __cplusplus +} +#endif + + +#endif + + + /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/ + diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Aes.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Aes.h new file mode 100644 index 000000000..1e41bafb3 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Aes.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file SPIRIT_Aes.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT AES Engine. + * + * @details + * + * In order to encrypt data, the user must manage the AES_END IRQ. + * The data have to be splitted in blocks of 16 bytes and written + * into the AES DATA IN registers. Then, after the key is written + * into the AES KEY registers, a command of Execute encryption + * has to be sent. + * + * Example: + * @code + * + * SpiritAesWriteDataIn(data_buff , N_BYTES); + * SpiritAesExecuteEncryption(); + * + * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq + * aes_end_flag=RESET; + * + * SpiritAesReadDataOut(enc_data_buff , N_BYTES); + * + * @endcode + * + * In order to decrypt data, the user must manage the AES_END IRQ and have a decryption key. + * There are two operative modes to make the data decryption: + *
    + *
  • Derive the decryption key from the encryption key and decrypt data directly + * using the SpiritAesDeriveDecKeyExecuteDec() function + * + * Example: + * @code + * + * SpiritAesWriteDataIn(enc_data_buff , N_BYTES); + * SpiritAesDeriveDecKeyExecuteDec(); + * + * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq + * aes_end_flag=RESET; + * + * SpiritAesReadDataOut(data_buff , N_BYTES); + * + * @endcode + *
    • + * + *
  • Derive the decryption key from the encryption key using the SpiritAesDeriveDecKeyFromEnc() + * function, store it into the AES KEY registers and then decrypt data using the + * SpiritAesExecuteDecryption() function + * + * Example: + * @code + * + * SpiritAesWriteDataIn(key_enc , 16); + * SpiritAesDeriveDecKeyFromEnc(); + * + * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq + * aes_end_flag=RESET; + * + * SpiritAesReadDataOut(key_dec , 16); + * + * SpiritAesWriteKey(key_dec); + * SpiritAesWriteDataIn(enc_data_buff , 16); + * SpiritAesExecuteDecryption(); + * + * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq + * aes_end_flag=RESET; + * + * SpiritAesReadDataOut(data_buff , N_BYTES); + * + * @endcode + *
    • + *
+ * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_AES_H +#define __SPIRIT_AES_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Aes AES + * @brief Configuration and management of SPIRIT AES Engine. + * @details See the file @ref SPIRIT_Aes.h for more details. + * @{ + */ + +/** + * @defgroup Aes_Exported_Types AES Exported Types + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Aes_Exported_Constants AES Exported Constants + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup Aes_Exported_Macros AES Exported Macros + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup Aes_Exported_Functions AES Exported Functions + * @{ + */ + +void SpiritAesMode(SpiritFunctionalState xNewState); +void SpiritAesWriteDataIn(uint8_t* pcBufferDataIn, uint8_t cDataLength); +void SpiritAesReadDataOut(uint8_t* pcBufferDataOut, uint8_t cDataLength); +void SpiritAesWriteKey(uint8_t* pcKey); +void SpiritAesReadKey(uint8_t* pcKey); +void SpiritAesDeriveDecKeyFromEnc(void); +void SpiritAesExecuteEncryption(void); +void SpiritAesExecuteDecryption(void); +void SpiritAesDeriveDecKeyExecuteDec(void); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Calibration.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Calibration.h new file mode 100644 index 000000000..6edc42442 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Calibration.h @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file SPIRIT_Calibration.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT VCO-RCO calibration. + * + * @details + * + * This module allows the user to set some parameters which deal + * with the oscillators calibration. + * The state machine of Spirit contemplates some optional calibrating operations + * in the transition between the READY and the LOCK state. + * The user is allowed to enable or disable the automatic RCO/VCO calibration + * by calling the functions @ref SpiritCalibrationVco() and @ref SpiritCalibrationRco(). + * The following example shows how to do an initial calibration of VCO. + * + * Example: + * @code + * uint8_t calData; + * + * SpiritCalibrationVco(S_ENABLE); + * SpiritCmdStrobeLockTx(); + * + * while(g_xStatus.MC_STATE != MC_STATE_LOCK){ + * SpiritRefreshStatus(); + * } + * + * calData = SpiritCalibrationGetVcoCalDataTx(); + * SpiritCalibrationSetVcoCalDataTx(calData); + * + * SpiritCmdStrobeReady(); + * SpiritCalibrationVco(S_DISABLE); + * + * @endcode + * + * Similar operations can be done for the RCO calibrator. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_CALIBRATION_H +#define __SPIRIT_CALIBRATION_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Calibration Calibration + * @brief Configuration and management of SPIRIT VCO-RCO calibration. + * @details See the file @ref SPIRIT_Calibration.h for more details. + * @{ + */ + +/** + * @defgroup Calibration_Exported_Types Calibration Exported Types + * @{ + */ + + +/** + * @brief VCO / RCO calibration window. + */ +typedef enum +{ + + CALIB_TIME_7_33_US_24MHZ = 0x00, /*!< calibration window of 7.33 us with XTAL=24MHz */ + CALIB_TIME_14_67_US_24MHZ, /*!< calibration window of 14.67 us with XTAL=24MHz */ + CALIB_TIME_29_33_US_24MHZ, /*!< calibration window of 29.33 us with XTAL=24MHz */ + CALIB_TIME_58_67_US_24MHZ, /*!< calibration window of 58.67 us with XTAL=24MHz */ + + CALIB_TIME_6_77_US_26MHZ = 0x00, /*!< calibration window of 6.77 us with XTAL=26MHz */ + CALIB_TIME_13_54_US_26MHZ, /*!< calibration window of 13.54 us with XTAL=26MHz */ + CALIB_TIME_27_08_US_26MHZ, /*!< calibration window of 27.08 us with XTAL=26MHz */ + CALIB_TIME_54_15_US_26MHZ /*!< calibration window of 54.15 us with XTAL=26MHz */ + +} VcoWin; + + +#define IS_VCO_WIN(REF) (REF == CALIB_TIME_7_33_US_24MHZ ||\ + REF == CALIB_TIME_14_67_US_24MHZ ||\ + REF == CALIB_TIME_29_33_US_24MHZ ||\ + REF == CALIB_TIME_58_67_US_24MHZ ||\ + REF == CALIB_TIME_6_77_US_26MHZ ||\ + REF == CALIB_TIME_13_54_US_26MHZ ||\ + REF == CALIB_TIME_27_08_US_26MHZ ||\ + REF == CALIB_TIME_54_15_US_26MHZ \ + ) + +/** + * @brief VCO_H / VCO_L selection. + */ +typedef enum +{ + + VCO_L = 0x00, /*!< VCO lower */ + VCO_H, /*!< VCO higher */ +} VcoSel; + + +#define IS_VCO_SEL(REF) (REF == VCO_L ||\ + REF == VCO_H \ + ) + + +/** + * @} + */ + + +/** + * @defgroup Calibration_Exported_Constants Calibration Exported Constants + * @{ + */ + +/** + * @} + */ + + + +/** @defgroup VCO_Calibration VCO Calibration + * @{ + */ + +/** + * @} + */ + + + + +/** + * @defgroup Calibration_Exported_Macros Calibration Exported Macros + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup Calibration_Exported_Functions Calibration Exported Functions + * @{ + */ + +void SpiritCalibrationRco(SpiritFunctionalState xNewState); +void SpiritCalibrationVco(SpiritFunctionalState xNewState); +void SpiritCalibrationSetRcoCalWords(uint8_t cRwt, uint8_t cRfb); +void SpiritCalibrationGetRcoCalWords(uint8_t* pcRwt, uint8_t* pcRfb); +uint8_t SpiritCalibrationGetVcoCalData(void); +void SpiritCalibrationSetVcoCalDataTx(uint8_t cVcoCalData); +uint8_t SpiritCalibrationGetVcoCalDataTx(void); +void SpiritCalibrationSetVcoCalDataRx(uint8_t cVcoCalData); +uint8_t SpiritCalibrationGetVcoCalDataRx(void); +void SpiritCalibrationSetVcoWindow(VcoWin xRefWord); +VcoWin SpiritCalibrationGetVcoWindow(void); +VcoSel SpiritCalibrationGetVcoSelecttion(void); +void SpiritCalibrationSelectVco(VcoSel xVco); + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Commands.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Commands.h new file mode 100644 index 000000000..7a8fa07fc --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Commands.h @@ -0,0 +1,336 @@ +/** + ****************************************************************************** + * @file SPIRIT_Commands.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Management of SPIRIT Commands. + * + * @details + * + * In this module can be found all the API used to strobe commands to + * Spirit. + * Every command strobe is an SPI transaction with a specific command code. + * + * Example: + * @code + * ... + * + * SpiritCmdStrobeRx(); + * + * ... + * @endcode + * + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_COMMANDS_H +#define __SPIRIT_COMMANDS_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Commands Commands + * @brief Management of SPIRIT Commands. + * @details See the file @ref SPIRIT_Commands.h for more details. + * @{ + */ + +/** + * @defgroup Commands_Exported_Types Commands Exported Types + * @{ + */ + +/** + * @brief SPIRIT Commands codes enumeration + */ +typedef enum +{ + CMD_TX = COMMAND_TX, /*!< Start to transmit; valid only from READY */ + CMD_RX = COMMAND_RX, /*!< Start to receive; valid only from READY */ + CMD_READY = COMMAND_READY, /*!< Go to READY; valid only from STANDBY or SLEEP or LOCK */ + CMD_STANDBY = COMMAND_STANDBY, /*!< Go to STANDBY; valid only from READY */ + CMD_SLEEP = COMMAND_SLEEP, /*!< Go to SLEEP; valid only from READY */ + CMD_LOCKRX = COMMAND_LOCKRX, /*!< Go to LOCK state by using the RX configuration of the synth; valid only from READY */ + CMD_LOCKTX = COMMAND_LOCKTX, /*!< Go to LOCK state by using the TX configuration of the synth; valid only from READY */ + CMD_SABORT = COMMAND_SABORT, /*!< Force exit form TX or RX states and go to READY state; valid only from TX or RX */ + CMD_LDC_RELOAD = COMMAND_LDC_RELOAD, /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER registers; valid from all states */ + CMD_SEQUENCE_UPDATE = COMMAND_SEQUENCE_UPDATE, /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register valid from all states */ + CMD_AES_ENC = COMMAND_AES_ENC, /*!< Commands: Start the encryption routine; valid from all states; valid from all states */ + CMD_AES_KEY = COMMAND_AES_KEY, /*!< Commands: Start the procedure to compute the key for the decryption; valid from all states */ + CMD_AES_DEC = COMMAND_AES_DEC, /*!< Commands: Start the decryption routine using the current key; valid from all states */ + CMD_AES_KEY_DEC = COMMAND_AES_KEY_DEC, /*!< Commands: Compute the key and start the decryption; valid from all states */ + CMD_SRES = COMMAND_SRES, /*!< Reset of all digital part, except SPI registers */ + CMD_FLUSHRXFIFO = COMMAND_FLUSHRXFIFO, /*!< Clean the RX FIFO; valid from all states */ + CMD_FLUSHTXFIFO = COMMAND_FLUSHTXFIFO, /*!< Clean the TX FIFO; valid from all states */ +} SpiritCmd; + +#define IS_SPIRIT_CMD(CMD) (CMD == CMD_TX || \ + CMD == CMD_RX || \ + CMD == CMD_READY || \ + CMD == CMD_STANDBY || \ + CMD == CMD_SLEEP || \ + CMD == CMD_LOCKRX || \ + CMD == CMD_LOCKTX || \ + CMD == CMD_SABORT || \ + CMD == CMD_LDC_RELOAD || \ + CMD == CMD_SEQUENCE_UPDATE || \ + CMD == CMD_AES_ENC || \ + CMD == CMD_AES_KEY || \ + CMD == CMD_AES_DEC || \ + CMD == CMD_AES_KEY_DEC || \ + CMD == CMD_SRES || \ + CMD == CMD_FLUSHRXFIFO || \ + CMD == CMD_FLUSHTXFIFO \ + ) + +/** + * @} + */ + + +/** + * @defgroup Commands_Exported_Constants Commands Exported Constants + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup Commands_Exported_Macros Commands Exported Macros + * @{ + */ + +/** + * @brief Sends the TX command to SPIRIT. Start to transmit. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeTx() {SpiritManagementWaCmdStrobeTx(); \ + SpiritCmdStrobeCommand(CMD_TX);} + + +/** + * @brief Sends the RX command to SPIRIT. Start to receive. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeRx() {SpiritManagementWaCmdStrobeRx(); \ + SpiritCmdStrobeCommand(CMD_RX); \ + } + + +/** + * @brief Sends the Ready state command to SPIRIT. Go to READY. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeReady() SpiritCmdStrobeCommand(CMD_READY) + + + +/** + * @brief Sends the Standby command to SPIRIT. Go to STANDBY. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeStandby() SpiritCmdStrobeCommand(CMD_STANDBY) + + + +/** + * @brief Sends the Sleep command to SPIRIT. Go to SLEEP. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeSleep() SpiritCmdStrobeCommand(CMD_SLEEP) + + + +/** + * @brief Sends the LOCK_RX command to SPIRIT. Go to the LOCK state by using the RX configuration of the synthesizer. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeLockRx() SpiritCmdStrobeCommand(CMD_LOCKRX) + + + +/** + * @brief Sends the LOCK_TX command to SPIRIT. Go to the LOCK state by using the TX configuration of the synthesizer. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeLockTx() SpiritCmdStrobeCommand(CMD_LOCKTX) + + + +/** + * @brief Sends the SABORT command to SPIRIT. Exit from TX or RX states and go to READY state. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeSabort() SpiritCmdStrobeCommand(CMD_SABORT) + + +/** + * @brief Sends the LDC_RELOAD command to SPIRIT. Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER registers. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeLdcReload() SpiritCmdStrobeCommand(CMD_LDC_RELOAD) + + + +/** + * @brief Sends the SEQUENCE_UPDATE command to SPIRIT. Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeSequenceUpdate() SpiritCmdStrobeCommand(CMD_SEQUENCE_UPDATE) + + + +/** + * @brief Sends the AES_ENC command to SPIRIT. Starts the encryption routine. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeAesEnc() SpiritCmdStrobeCommand(CMD_AES_ENC) + + + +/** + * @brief Sends the AES_KEY command to SPIRIT. Starts the procedure to compute the key for the decryption. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeAesKey() SpiritCmdStrobeCommand(CMD_AES_KEY) + + + +/** + * @brief Sends the AES_DEC command to SPIRIT. Starts the decryption using the current key. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeAesDec() SpiritCmdStrobeCommand(CMD_AES_DEC) + + + +/** + * @brief Sends the KEY_DEC command to SPIRIT. Computes the key derivation and start the decryption. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeAesKeyDec() SpiritCmdStrobeCommand(CMD_AES_KEY_DEC) + +/** + * @brief Sends the SRES command to SPIRIT. Partial reset: all digital circuit will be reset (exception for SPI only). + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeSres() SpiritCmdStrobeCommand(CMD_SRES) + + +/** + * @brief Sends the FLUSHRXFIFO command to SPIRIT. Clean the RX FIFO. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeFlushRxFifo() SpiritCmdStrobeCommand(CMD_FLUSHRXFIFO) + + + +/** + * @brief Sends the FLUSHTXFIFO command to SPIRIT. Clean the TX FIFO. + * @param None. + * @retval None. + */ +#define SpiritCmdStrobeFlushTxFifo() SpiritCmdStrobeCommand(CMD_FLUSHTXFIFO) + + + +/** + * @} + */ + + +/** + * @defgroup Commands_Exported_Functions Commands Exported Functions + * @{ + */ +void SpiritCmdStrobeCommand(SpiritCmd xCommandCode); + + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Config.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Config.h new file mode 100644 index 000000000..9d96975c4 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Config.h @@ -0,0 +1,147 @@ +/** + ****************************************************************************** + * @file SPIRIT_Config.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Spirit Configuration and useful defines + * + * @details + * + * This file is used to include all or a part of the Spirit + * libraries into the application program which will be used. + * Moreover some important parameters are defined here and the + * user is allowed to edit them. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_CONFIG_H +#define __SPIRIT_CONFIG_H + + + /* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Regs.h" +#include "SPIRIT_Aes.h" +#include "SPIRIT_Calibration.h" +#include "SPIRIT_Commands.h" +#include "SPIRIT_Csma.h" +#include "SPIRIT_DirectRF.h" +#include "SPIRIT_General.h" +#include "SPIRIT_Gpio.h" +#include "SPIRIT_Irq.h" +#include "SPIRIT_Timer.h" +#include "SPIRIT_LinearFifo.h" +#include "SPIRIT_PktBasic.h" +#include "SPIRIT_PktMbus.h" +#include "SPIRIT_PktStack.h" + +#include "SPIRIT_Qi.h" +#include "SPIRIT_Radio.h" +#include "MCU_Interface.h" +#include "SPIRIT_Types.h" +#include "SPIRIT_Management.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup SPIRIT_Libraries SPIRIT Libraries + * @brief This firmware implements libraries which allow the user + * to manage the features of Spirit without knowing the hardware details. + * @details The SPIRIT_Libraries modules are totally platform independent. The library provides one + * module for each device feature. Each module refers to some functions whose prototypes are located in the + * header file @ref MCU_Interface.h. The user who want to use these libraries on a particular + * platform has to implement these functions respecting them signatures. + * @{ + */ + +/** @defgroup SPIRIT_Configuration Configuration + * @brief Spirit Configuration and useful defines. + * @details See the file @ref SPIRIT_Config.h for more details. + * @{ + */ + + +/** @defgroup Configuration_Exported_Types Configuration Exported Types + * @{ + */ + +/** + * @} + */ + + +/** @defgroup Configuration_Exported_Constants Configuration Exported Constants + * @{ + */ +#define DOUBLE_XTAL_THR 30000000 + +/** + * @} + */ + + +/** @defgroup Configuration_Exported_Macros Configuration Exported Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup Configuration_Exported_Functions Configuration Exported Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Csma.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Csma.h new file mode 100644 index 000000000..88db8b353 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Csma.h @@ -0,0 +1,263 @@ +/** + ****************************************************************************** + * @file SPIRIT_Csma.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT CSMA. + * @details + * + * The Spirit CSMA feature, when configured and enabled, is transparent + * for the user. It means the user has only to call the @ref SpiritCsmaInit() + * function on a filled structure and then enable the CSMA policy using the @ref SpiritCsma() + * function. + * + * Example: + * @code + * + * CsmaInit csmaInit={ + * S_DISABLE, // persistent mode + * TBIT_TIME_64, // Tbit time + * TCCA_TIME_3, // Tcca time + * 5, // max number of backoffs + * 0xFA21, // BU counter seed + * 32 // CU prescaler + * }; + * + * ... + * + * SpiritCsmaInit(&csmaInit); + * SpiritCsma(S_ENABLE); + * + * + * @endcode + * + * @note The CS status depends of the RSSI threshold set. Please see the Spirit_Qi + * module for details. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_CSMA_H +#define __SPIRIT_CSMA_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Types.h" +#include "SPIRIT_Regs.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Csma CSMA + * @brief Configuration and management of SPIRIT CSMA. + * @details See the file @ref SPIRIT_Csma.h for more details. + * @{ + */ + +/** + * @defgroup Csma_Exported_Types CSMA Exported Types + * @{ + */ + + +/** + * @brief Multiplier for Tcca time enumeration (Tcca = Multiplier*Tbit). + */ +typedef enum +{ + TBIT_TIME_64 = CSMA_CCA_PERIOD_64TBIT, /*!< CSMA/CA: Sets CCA period to 64*TBIT */ + TBIT_TIME_128 = CSMA_CCA_PERIOD_128TBIT, /*!< CSMA/CA: Sets CCA period to 128*TBIT */ + TBIT_TIME_256 = CSMA_CCA_PERIOD_256TBIT, /*!< CSMA/CA: Sets CCA period to 256*TBIT */ + TBIT_TIME_512 = CSMA_CCA_PERIOD_512TBIT, /*!< CSMA/CA: Sets CCA period to 512*TBIT */ +}CcaPeriod; + +#define IS_CCA_PERIOD(PERIOD) (PERIOD == TBIT_TIME_64 || \ + PERIOD == TBIT_TIME_128 || \ + PERIOD == TBIT_TIME_256 || \ + PERIOD == TBIT_TIME_512) + + +/** + * @brief Multiplier of Tcca time enumeration to obtain Tlisten (Tlisten = [1...15]*Tcca). + */ +typedef enum +{ + TCCA_TIME_0 = 0x00, /*!< CSMA/CA: Sets CCA length to 0 */ + TCCA_TIME_1 = 0x10, /*!< CSMA/CA: Sets CCA length to 1*TLISTEN */ + TCCA_TIME_2 = 0x20, /*!< CSMA/CA: Sets CCA length to 2*TLISTEN */ + TCCA_TIME_3 = 0x30, /*!< CSMA/CA: Sets CCA length to 3*TLISTEN */ + TCCA_TIME_4 = 0x40, /*!< CSMA/CA: Sets CCA length to 4*TLISTEN */ + TCCA_TIME_5 = 0x50, /*!< CSMA/CA: Sets CCA length to 5*TLISTEN */ + TCCA_TIME_6 = 0x60, /*!< CSMA/CA: Sets CCA length to 6*TLISTEN */ + TCCA_TIME_7 = 0x70, /*!< CSMA/CA: Sets CCA length to 7*TLISTEN */ + TCCA_TIME_8 = 0x80, /*!< CSMA/CA: Sets CCA length to 8*TLISTEN */ + TCCA_TIME_9 = 0x90, /*!< CSMA/CA: Sets CCA length to 9*TLISTEN */ + TCCA_TIME_10 = 0xA0, /*!< CSMA/CA: Sets CCA length to 10*TLISTEN */ + TCCA_TIME_11 = 0xB0, /*!< CSMA/CA: Sets CCA length to 11*TLISTEN */ + TCCA_TIME_12 = 0xC0, /*!< CSMA/CA: Sets CCA length to 12*TLISTEN */ + TCCA_TIME_13 = 0xD0, /*!< CSMA/CA: Sets CCA length to 13*TLISTEN */ + TCCA_TIME_14 = 0xE0, /*!< CSMA/CA: Sets CCA length to 14*TLISTEN */ + TCCA_TIME_15 = 0xF0, /*!< CSMA/CA: Sets CCA length to 15*TLISTEN */ +}CsmaLength; + +#define IS_CSMA_LENGTH(LENGTH) (LENGTH == TCCA_TIME_0 || \ + LENGTH == TCCA_TIME_1 || \ + LENGTH == TCCA_TIME_2 || \ + LENGTH == TCCA_TIME_3 || \ + LENGTH == TCCA_TIME_4 || \ + LENGTH == TCCA_TIME_5 || \ + LENGTH == TCCA_TIME_6 || \ + LENGTH == TCCA_TIME_7 || \ + LENGTH == TCCA_TIME_8 || \ + LENGTH == TCCA_TIME_9 || \ + LENGTH == TCCA_TIME_10 || \ + LENGTH == TCCA_TIME_11 || \ + LENGTH == TCCA_TIME_12 || \ + LENGTH == TCCA_TIME_13 || \ + LENGTH == TCCA_TIME_14 || \ + LENGTH == TCCA_TIME_15) + + +/** + * @brief SPIRIT CSMA Init structure definition + */ +typedef struct +{ + SpiritFunctionalState xCsmaPersistentMode; /*!< Specifies if the CSMA persistent mode has to be on or off. + This parameter can be S_ENABLE or S_DISABLE */ + CcaPeriod xMultiplierTbit; /*!< Specifies the Tbit multiplier to obtain the Tcca. + This parameter can be a value of @ref CcaPeriod */ + CsmaLength xCcaLength; /*!< Specifies the Tcca multiplier to determinate the Tlisten. + This parameter can be a value of @ref CsmaLength. */ + uint8_t cMaxNb; /*!< Specifies the max number of backoff cycles. Not used in persistent mode. + This parameter is an uint8_t. */ + uint16_t nBuCounterSeed; /*!< Specifies the BU counter seed. Not used in persistent mode. + This parameter can be a value of 16 bits. */ + uint8_t cBuPrescaler; /*!< Specifies the BU prescaler. Not used in persistent mode. + This parameter can be a value of 6 bits. */ +}CsmaInit; + + +/** + *@} + */ + + +/** + * @defgroup Csma_Exported_Constants CSMA Exported Constants + * @{ + */ + +/** + * @defgroup Csma_Parameters CSMA Parameters + * @{ + */ + +#define IS_BU_COUNTER_SEED(SEED) (SEED!=0) +#define IS_BU_PRESCALER(PRESCALER) (PRESCALER<64) +#define IS_CMAX_NB(NB) (NB<8) + +/** + *@} + */ + +/** + *@} + */ + + +/** + * @defgroup Csma_Exported_Macros CSMA Exported Macros + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup Csma_Exported_Functions CSMA Exported Functions + * @{ + */ + +void SpiritCsmaInit(CsmaInit* pxCsmaInit); +void SpiritCsmaGetInfo(CsmaInit* pxCsmaInit); +void SpiritCsma(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritCsmaGetCsma(void); +void SpiritCsmaPersistentMode(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritCsmaGetPersistentMode(void); +void SpiritCsmaSeedReloadMode(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritCsmaGetSeedReloadMode(void); +void SpiritCsmaSetBuCounterSeed(uint16_t nBuCounterSeed); +uint16_t SpiritCsmaGetBuCounterSeed(void); +void SpiritCsmaSetBuPrescaler(uint8_t cBuPrescaler); +uint8_t SpiritCsmaGetBuPrescaler(void); +void SpiritCsmaSetCcaPeriod(CcaPeriod xMultiplierTbit); +CcaPeriod SpiritCsmaGetCcaPeriod(void); +void SpiritCsmaSetCcaLength(CsmaLength xCcaLength); +uint8_t SpiritCsmaGetCcaLength(void); +void SpiritCsmaSetMaxNumberBackoff(uint8_t cMaxNb); +uint8_t SpiritCsmaGetMaxNumberBackoff(void); + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_DirectRF.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_DirectRF.h new file mode 100644 index 000000000..f60090718 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_DirectRF.h @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file SPIRIT_DirectRF.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT direct transmission / receive modes. + * @details + * + * This module contains functions to manage the direct Tx/Rx mode. + * The user can choose the way to send data to Spirit through the + * enumerative types @ref DirectTx/@ref DirectRx. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT1_DIRECT_RF_H +#define __SPIRIT1_DIRECT_RF_H + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_DirectRf Direct RF + * @brief Configuration and management of SPIRIT direct transmission / receive modes. + * @details See the file @ref SPIRIT_DirectRF.h for more details. + * @{ + */ + +/** + * @defgroup DirectRf_Exported_Types Direct RF Exported Types + * @{ + */ + +/** + * @brief Direct transmission mode enumeration for SPIRIT. + */ +typedef enum +{ + NORMAL_TX_MODE = 0x00, /*!< Normal mode, no direct transmission is used */ + DIRECT_TX_FIFO_MODE = 0x04, /*!< Source is FIFO: payload bits are continuously read from the TX FIFO */ + DIRECT_TX_GPIO_MODE = 0x08, /*!< Source is GPIO: payload bits are continuously read from one of the GPIO ports and transmitted without any processing */ + PN9_TX_MODE = 0x0C /*!< A pseudorandom binary sequence is generated internally */ +}DirectTx; + +#define IS_DIRECT_TX(MODE) (((MODE) == NORMAL_TX_MODE) || \ + ((MODE) == DIRECT_TX_FIFO_MODE) || \ + ((MODE) == DIRECT_TX_GPIO_MODE) || \ + ((MODE) == PN9_TX_MODE)) + +/** + * @brief Direct receive mode enumeration for SPIRIT. + */ +typedef enum +{ + NORMAL_RX_MODE = 0x00, /*!< Normal mode, no direct reception is used */ + DIRECT_RX_FIFO_MODE = 0x10, /*!< Destination is FIFO: payload bits are continuously written to the RX FIFO and not subjected to any processing*/ + DIRECT_RX_GPIO_MODE = 0x20 /*!< Destination is GPIO: payload bits are continuously written to one of the GPIO ports and not subjected to any processing*/ +}DirectRx; + +#define IS_DIRECT_RX(MODE) (((MODE) == NORMAL_RX_MODE) || \ + ((MODE) == DIRECT_RX_FIFO_MODE) || \ + ((MODE) == DIRECT_RX_GPIO_MODE)) + + +/** + *@} + */ + + +/** + * @defgroup DirectRf_Exported_Constants Direct RF Exported Constants + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup DirectRf_Exported_Macros Direct RF Exported Macros + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup DirectRf_Exported_Functions Direct RF Exported Functions + * @{ + */ + +void SpiritDirectRfSetRxMode(DirectRx xDirectRx); +DirectRx SpiritDirectRfGetRxMode(void); +void SpiritDirectRfSetTxMode(DirectTx xDirectTx); +DirectTx SpiritDirectRfGetTxMode(void); + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_General.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_General.h new file mode 100644 index 000000000..0f723fb7e --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_General.h @@ -0,0 +1,227 @@ +/** + ****************************************************************************** + * @file SPIRIT_General.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT General functionalities. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_GENERAL_H +#define __SPIRIT_GENERAL_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_General General + * @brief Configuration and management of SPIRIT General functionalities. + * @details See the file @ref SPIRIT_General.h for more details. + * @{ + */ + +/** + * @defgroup General_Exported_Types General Exported Types + * @{ + */ + + +/** + * @brief SPIRIT ModeExtRef enumeration + */ + +typedef enum +{ + MODE_EXT_XO = 0, + MODE_EXT_XIN = !MODE_EXT_XO +} ModeExtRef; + +#define IS_MODE_EXT(MODE) (MODE == MODE_EXT_XO || \ + MODE == MODE_EXT_XIN) + + +/** + * @brief SPIRIT BatteryLevel enumeration + */ + +typedef enum +{ + BLD_LVL_2_7_V = 0, + BLD_LVL_2_5_V = 1, + BLD_LVL_2_3_V = 2, + BLD_LVL_2_1_V = 3 +} BatteryLevel; + +#define IS_BLD_LVL(MODE) (MODE == BLD_LVL_2_7_V || \ + MODE == BLD_LVL_2_5_V || \ + MODE == BLD_LVL_2_3_V || \ + MODE == BLD_LVL_2_1_V) + + +/** + * @brief SPIRIT GmConf enumeration + */ + +typedef enum +{ + GM_SU_13_2 = 0, + GM_SU_18_2, + GM_SU_21_5, + GM_SU_25_6, + GM_SU_28_8, + GM_SU_33_9, + GM_SU_38_5, + GM_SU_43_0 +} GmConf; + +#define IS_GM_CONF(MODE) (MODE == GM_SU_13_2 || \ + MODE == GM_SU_18_2 || \ + MODE == GM_SU_21_5 || \ + MODE == GM_SU_25_6 || \ + MODE == GM_SU_28_8 || \ + MODE == GM_SU_33_9 || \ + MODE == GM_SU_38_5 || \ + MODE == GM_SU_43_0) + + +/** + * @brief SPIRIT packet type enumeration + */ + +typedef enum +{ + PKT_BASIC = 0x00, + PKT_MBUS = 0x02, + PKT_STACK + +} PacketType; + +#define IS_PKT_TYPE(TYPE) (TYPE == PKT_BASIC || \ + TYPE == PKT_MBUS || \ + TYPE == PKT_STACK || \ + ) + + +/** + * @brief SPIRIT version type enumeration + */ + +typedef enum +{ + SPIRIT_VERSION_2_1 = 0x01, /* Deprecated */ + SPIRIT_VERSION_3_0, /* The only version of SPIRIT1 */ +} SpiritVersion; + + +/** + * @} + */ + + +/** + * @defgroup General_Exported_Constants General Exported Constants + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup General_Exported_Macros General Exported Macros + * @{ + */ +#define SpiritGeneralLibraryVersion() "Spirit1_Libraries_v.3.2.0" + + +/** + * @} + */ + + +/** + * @defgroup General_Exported_Functions General Exported Functions + * @{ + */ + + +void SpiritGeneralBatteryLevel(SpiritFunctionalState xNewState); +void SpiritGeneralSetBatteryLevel(BatteryLevel xBatteryLevel); +BatteryLevel SpiritGeneralGetBatteryLevel(void); +void SpiritGeneralBrownOut(SpiritFunctionalState xNewState); +void SpiritGeneralHighPwr(SpiritFunctionalState xNewState); +void SpiritGeneralSetExtRef(ModeExtRef xExtMode); +ModeExtRef SpiritGeneralGetExtRef(void); +void SpiritGeneralSetXoGm(GmConf xGm); +GmConf SpiritGeneralGetXoGm(void); +PacketType SpiritGeneralGetPktType(void); +uint16_t SpiritGeneralGetDevicePartNumber(void); +uint8_t SpiritGeneralGetSpiritVersion(void); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Gpio.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Gpio.h new file mode 100644 index 000000000..8ea32e004 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Gpio.h @@ -0,0 +1,405 @@ +/** + ****************************************************************************** + * @file SPIRIT_Gpio.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief This file provides all the low level API to manage SPIRIT GPIO. + * + * @details + * + * This module can be used to configure the Spirit GPIO pins to perform + * specific functions. + * The structure @ref gpioIRQ can be used to specify these features for + * one of the four Spirit Gpio pin. + * The following example shows how to configure a pin (GPIO 3) to be used as an IRQ source + * for a microcontroller using the @ref SpiritGpioInit() function. + * + * Example: + * @code + * + * SGpioInit gpioIRQ={ + * SPIRIT_GPIO_3, + * SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, + * SPIRIT_GPIO_DIG_OUT_IRQ + * }; + * + * ... + * + * SpiritGpioInit(&gpioIRQ); + * + * @endcode + * + * @note Please read the functions documentation for the other GPIO features. + * + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_GPIO_H +#define __SPIRIT_GPIO_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** @defgroup SPIRIT_Gpio GPIO + * @brief Configuration and management of SPIRIT GPIO. + * @details See the file @ref SPIRIT_Gpio.h for more details. + * @{ + */ + + + +/** @defgroup Gpio_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief SPIRIT GPIO pin enumeration. + */ +typedef enum +{ + SPIRIT_GPIO_0 = GPIO0_CONF_BASE, /*!< GPIO_0 selected */ + SPIRIT_GPIO_1 = GPIO1_CONF_BASE, /*!< GPIO_1 selected */ + SPIRIT_GPIO_2 = GPIO2_CONF_BASE, /*!< GPIO_2 selected */ + SPIRIT_GPIO_3 = GPIO3_CONF_BASE /*!< GPIO_3 selected */ +}SpiritGpioPin; + + +#define IS_SPIRIT_GPIO(PIN) ((PIN == SPIRIT_GPIO_0) || \ + (PIN == SPIRIT_GPIO_1) || \ + (PIN == SPIRIT_GPIO_2) || \ + (PIN == SPIRIT_GPIO_3)) + + +/** + * @brief SPIRIT GPIO mode enumeration. + */ +typedef enum +{ + SPIRIT_GPIO_MODE_DIGITAL_INPUT = 0x01, /*!< Digital Input on GPIO */ + SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP = 0x02, /*!< Digital Output on GPIO (low current) */ + SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP = 0x03 /*!< Digital Output on GPIO (high current) */ +}SpiritGpioMode; + +#define IS_SPIRIT_GPIO_MODE(MODE) ((MODE == SPIRIT_GPIO_MODE_DIGITAL_INPUT) || \ + (MODE == SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP) || \ + (MODE == SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP)) + + + +/** + * @brief SPIRIT I/O selection enumeration. + */ +typedef enum +{ + SPIRIT_GPIO_DIG_OUT_IRQ = 0x00, /*!< nIRQ (Interrupt Request, active low) , default configuration after POR */ + SPIRIT_GPIO_DIG_OUT_POR_INV = 0x08, /*!< POR inverted (active low) */ + SPIRIT_GPIO_DIG_OUT_WUT_EXP = 0x10, /*!< Wake-Up Timer expiration: "1" when WUT has expired */ + SPIRIT_GPIO_DIG_OUT_LBD = 0x18, /*!< Low battery detection: "1" when battery is below threshold setting */ + SPIRIT_GPIO_DIG_OUT_TX_DATA = 0x20, /*!< TX data internal clock output (TX data are sampled on the rising edge of it) */ + SPIRIT_GPIO_DIG_OUT_TX_STATE = 0x28, /*!< TX state indication: "1" when Spirit1 is passing in the TX state */ + SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_EMPTY = 0x30, /*!< TX FIFO Almost Empty Flag */ + SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_FULL = 0x38, /*!< TX FIFO Almost Full Flag */ + SPIRIT_GPIO_DIG_OUT_RX_DATA = 0x40, /*!< RX data output */ + SPIRIT_GPIO_DIG_OUT_RX_CLOCK = 0x48, /*!< RX clock output (recovered from received data) */ + SPIRIT_GPIO_DIG_OUT_RX_STATE = 0x50, /*!< RX state indication: "1" when Spirit1 is passing in the RX state */ + SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_FULL = 0x58, /*!< RX FIFO Almost Full Flag */ + SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_EMPTY = 0x60, /*!< RX FIFO Almost Empty Flag */ + SPIRIT_GPIO_DIG_OUT_ANTENNA_SWITCH = 0x68, /*!< Antenna switch used for antenna diversity */ + SPIRIT_GPIO_DIG_OUT_VALID_PREAMBLE = 0x70, /*!< Valid Preamble Detected Flag */ + SPIRIT_GPIO_DIG_OUT_SYNC_DETECTED = 0x78, /*!< Sync WordSync Word Detected Flag */ + SPIRIT_GPIO_DIG_OUT_RSSI_THRESHOLD = 0x80, /*!< RSSI above threshold */ + SPIRIT_GPIO_DIG_OUT_MCU_CLOCK = 0x88, /*!< MCU Clock */ + SPIRIT_GPIO_DIG_OUT_TX_RX_MODE = 0x90, /*!< TX or RX mode indicator (to enable an external range extender) */ + SPIRIT_GPIO_DIG_OUT_VDD = 0x98, /*!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) */ + SPIRIT_GPIO_DIG_OUT_GND = 0xA0, /*!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) */ + SPIRIT_GPIO_DIG_OUT_SMPS_EXT = 0xA8, /*!< External SMPS enable signal (active high) */ + SPIRIT_GPIO_DIG_OUT_SLEEP_OR_STANDBY = 0xB0, + SPIRIT_GPIO_DIG_OUT_READY = 0xB8, + SPIRIT_GPIO_DIG_OUT_LOCK = 0xC0, + SPIRIT_GPIO_DIG_OUT_WAIT_FOR_LOCK_SIG = 0xC8, + SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_LOCK = 0xD0, + SPIRIT_GPIO_DIG_OUT_WAIT_FOR_READY2_SIG = 0xD8, + SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_PM_SET = 0xE0, + SPIRIT_GPIO_DIG_OUT_WAIT_VCO_CALIBRATION = 0xE8, + SPIRIT_GPIO_DIG_OUT_ENABLE_SYNTH_FULL_CIRCUIT = 0xF0, + SPIRIT_GPIO_DIG_OUT_WAIT_FOR_RCCAL_OK_SIG = 0xFF, + + SPIRIT_GPIO_DIG_IN_TX_COMMAND = 0x00, + SPIRIT_GPIO_DIG_IN_RX_COMMAND = 0x08, + SPIRIT_GPIO_DIG_IN_TX_DATA_INPUT_FOR_DIRECTRF = 0x10, + SPIRIT_GPIO_DIG_IN_DATA_WAKEUP = 0x18, + SPIRIT_GPIO_DIG_IN_EXT_CLOCK_AT_34_7KHZ = 0x20 + +}SpiritGpioIO; + +#define IS_SPIRIT_GPIO_IO(IO_SEL) ((IO_SEL == SPIRIT_GPIO_DIG_OUT_IRQ) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_POR_INV) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_WUT_EXP) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_LBD) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_DATA) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_STATE) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_EMPTY) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_FULL) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_DATA) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_CLOCK) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_STATE) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_FULL) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_EMPTY) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_ANTENNA_SWITCH) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_VALID_PREAMBLE) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_SYNC_DETECTED) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_RSSI_THRESHOLD) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_MCU_CLOCK) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_RX_MODE) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_VDD) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_GND) || \ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_SMPS_EXT) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_SLEEP_OR_STANDBY) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_READY) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_LOCK) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_LOCK_SIG) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_LOCK) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_READY2_SIG) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_PM_SET) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_VCO_CALIBRATION) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_ENABLE_SYNTH_FULL_CIRCUIT) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_RCCAL_OK_SIG) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_IN_TX_COMMAND) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_IN_RX_COMMAND) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_IN_TX_DATA_INPUT_FOR_DIRECTRF) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_IN_DATA_WAKEUP) ||\ + (IO_SEL == SPIRIT_GPIO_DIG_IN_EXT_CLOCK_AT_34_7KHZ)) + +/** + * @brief SPIRIT OutputLevel enumeration. + */ + +typedef enum +{ + LOW = 0, + HIGH = !LOW +}OutputLevel; + +#define IS_SPIRIT_GPIO_LEVEL(LEVEL) ((LEVEL == LOW) || \ + (LEVEL == HIGH)) + + +/** + * @brief SPIRIT GPIO Init structure definition. + */ +typedef struct +{ + SpiritGpioPin xSpiritGpioPin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref SpiritGpioPin */ + + SpiritGpioMode xSpiritGpioMode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref SpiritGpioMode */ + + SpiritGpioIO xSpiritGpioIO; /*!< Specifies the I/O selection for the selected pins. + This parameter can be a value of @ref SpiritGpioIO */ + +}SGpioInit; + + + +/** + * @brief SPIRIT clock output XO prescaler enumeration. + */ + +typedef enum +{ + XO_RATIO_1 = 0x00, /*!< XO Clock signal available on the GPIO divided by 1 */ + XO_RATIO_2_3 = 0x02, /*!< XO Clock signal available on the GPIO divided by 2/3 */ + XO_RATIO_1_2 = 0x04, /*!< XO Clock signal available on the GPIO divided by 1/2 */ + XO_RATIO_1_3 = 0x06, /*!< XO Clock signal available on the GPIO divided by 1/3 */ + XO_RATIO_1_4 = 0x08, /*!< XO Clock signal available on the GPIO divided by 1/4 */ + XO_RATIO_1_6 = 0x0A, /*!< XO Clock signal available on the GPIO divided by 1/6 */ + XO_RATIO_1_8 = 0x0C, /*!< XO Clock signal available on the GPIO divided by 1/8 */ + XO_RATIO_1_12 = 0x0E, /*!< XO Clock signal available on the GPIO divided by 1/12 */ + XO_RATIO_1_16 = 0x10, /*!< XO Clock signal available on the GPIO divided by 1/16 */ + XO_RATIO_1_24 = 0x12, /*!< XO Clock signal available on the GPIO divided by 1/24 */ + XO_RATIO_1_36 = 0x14, /*!< XO Clock signal available on the GPIO divided by 1/36 */ + XO_RATIO_1_48 = 0x16, /*!< XO Clock signal available on the GPIO divided by 1/48 */ + XO_RATIO_1_64 = 0x18, /*!< XO Clock signal available on the GPIO divided by 1/64 */ + XO_RATIO_1_96 = 0x1A, /*!< XO Clock signal available on the GPIO divided by 1/96 */ + XO_RATIO_1_128 = 0x1C, /*!< XO Clock signal available on the GPIO divided by 1/128 */ + XO_RATIO_1_192 = 0x1E /*!< XO Clock signal available on the GPIO divided by 1/196 */ +}ClockOutputXOPrescaler; + +#define IS_SPIRIT_CLOCK_OUTPUT_XO(RATIO) ((RATIO == XO_RATIO_1) || \ + (RATIO == XO_RATIO_2_3) || \ + (RATIO == XO_RATIO_1_2) || \ + (RATIO == XO_RATIO_1_3) || \ + (RATIO == XO_RATIO_1_4) || \ + (RATIO == XO_RATIO_1_6) || \ + (RATIO == XO_RATIO_1_8) || \ + (RATIO == XO_RATIO_1_12) || \ + (RATIO == XO_RATIO_1_16) || \ + (RATIO == XO_RATIO_1_24) || \ + (RATIO == XO_RATIO_1_36) || \ + (RATIO == XO_RATIO_1_48) || \ + (RATIO == XO_RATIO_1_64) || \ + (RATIO == XO_RATIO_1_96) || \ + (RATIO == XO_RATIO_1_128) || \ + (RATIO == XO_RATIO_1_192)) + +/** + * @brief SPIRIT Clock Output RCO prescaler enumeration. + */ + +typedef enum +{ + RCO_RATIO_1 = 0x00, /*!< RCO Clock signal available on the GPIO divided by 1 */ + RCO_RATIO_1_128 = 0x01 /*!< RCO Clock signal available on the GPIO divided by 1/128 */ +}ClockOutputRCOPrescaler; + +#define IS_SPIRIT_CLOCK_OUTPUT_RCO(RATIO) ((RATIO == RCO_RATIO_1) || \ + (RATIO == RCO_RATIO_1_128)) + +/** + * @brief SPIRIT ExtraClockCycles enumeration. + */ + +typedef enum +{ +EXTRA_CLOCK_CYCLES_0 = 0x00, /*!< 0 extra clock cycles provided to the MCU before switching to STANDBY state */ +EXTRA_CLOCK_CYCLES_64 = 0x20, /*!< 64 extra clock cycles provided to the MCU before switching to STANDBY state */ +EXTRA_CLOCK_CYCLES_256 = 0x40, /*!< 256 extra clock cycles provided to the MCU before switching to STANDBY state */ +EXTRA_CLOCK_CYCLES_512 = 0x60 /*!< 512 extra clock cycles provided to the MCU before switching to STANDBY state */ +}ExtraClockCycles; + +#define IS_SPIRIT_CLOCK_OUTPUT_EXTRA_CYCLES(CYCLES) ((CYCLES == EXTRA_CLOCK_CYCLES_0) || \ + (CYCLES == EXTRA_CLOCK_CYCLES_64) || \ + (CYCLES == EXTRA_CLOCK_CYCLES_256) || \ + (CYCLES == EXTRA_CLOCK_CYCLES_512)) + + +/** + * @brief SPIRIT Clock Output initialization structure definition. + */ +typedef struct +{ + ClockOutputXOPrescaler xClockOutputXOPrescaler; /*!< Specifies the XO Ratio as clock output. + This parameter can be any value of @ref ClockOutputXOPrescaler */ + + ClockOutputRCOPrescaler xClockOutputRCOPrescaler; /*!< Specifies the RCO Ratio as clock output. + This parameter can be a value of @ref ClockOutputRCOPrescaler */ + + ExtraClockCycles xExtraClockCycles; /*!< Specifies the Extra Clock Cycles provided before entering in Standby State. + This parameter can be a value of @ref ExtraClockCycles */ + +}ClockOutputInit; + + + +/** + * @} + */ + + + +/** @defgroup Gpio_Exported_Constants GPIO Exported Constants + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Gpio_Exported_Macros GPIO Exported Macros + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Gpio_Exported_Functions GPIO Exported Functions + * @{ + */ + +void SpiritGpioInit(SGpioInit* pxGpioInitStruct); +void SpiritGpioTemperatureSensor(SpiritFunctionalState xNewState); +void SpiritGpioSetLevel(SpiritGpioPin xGpioX, OutputLevel xLevel); +OutputLevel SpiritGpioGetLevel(SpiritGpioPin xGpioX); +void SpiritGpioClockOutput(SpiritFunctionalState xNewState); +void SpiritGpioClockOutputInit(ClockOutputInit* pxClockOutputInitStruct); +void SpiritGpioSetXOPrescaler(ClockOutputXOPrescaler xXOPrescaler); +ClockOutputXOPrescaler SpiritGpioGetXOPrescaler(void); +void SpiritGpioSetRCOPrescaler(ClockOutputRCOPrescaler xRCOPrescaler); +ClockOutputRCOPrescaler SpiritGpioGetRCOPrescaler(void); +void SpiritGpioSetExtraClockCycles(ExtraClockCycles xExtraCycles); +ExtraClockCycles SpiritGpioGetExtraClockCycles(void); + + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Irq.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Irq.h new file mode 100644 index 000000000..07ef93981 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Irq.h @@ -0,0 +1,349 @@ +/** + ****************************************************************************** + * @file SPIRIT_Irq.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT IRQs. + * + * @details + * + * On the Spirit side specific IRQs can be enabled by setting a specific bitmask. + * The Spirit libraries allow the user to do this in two different ways: + *
    + * + *
  • The first enables the IRQs one by one, i.e. using an SPI transaction for each + * IRQ to enable. + * + * Example: + * @code + * + * SpiritIrqDeInit(NULL); // this call is used to reset the IRQ mask registers + * SpiritIrq(RX_DATA_READY , S_ENABLE); + * SpiritIrq(VALID_SYNC , S_ENABLE); + * SpiritIrq(RX_TIMEOUT , S_ENABLE); + * + * @endcode + * + *
    • + * + *
  • The second strategy is to set the IRQ bitfields structure. So, during the initialization the user + * has to fill the @ref SpiritIrqs structure setting to one the single field related to the IRQ he + * wants to enable, and to zero the single field related to all the IRQs he wants to disable. + * + * Example: + * @code + * + * SpiritIrqs irqMask; + * + * ... + * + * SpiritIrqDeInit(&irqMask); // this call is used to reset the IRQ mask registers + * // and to set to 0x00000000 the irq mask in order to disable + * // all IRQs (disabled by default on startup) + * irqMask.IRQ_RX_DATA_READY = 1; + * irqMask.IRQ_VALID_SYNC = 1; + * irqMask.IRQ_RX_TIMEOUT = 1; + * + * ... + * @endcode + *
    • + *
+ * + * The most applications will require a Spirit IRQ notification on an microcontroller EXTI line. + * Then, the user can check which IRQ has been raised using two different ways. + * + * On the ISR of the EXTI line phisically linked to the Spirit pin configured for IRQ: + * + *
    + *
  • Check only one Spirit IRQ (because the Spirit IRQ status register automatically blanks itself + * after an SPI reading) into the ISR. + * + * Example: + * @code + * + * if(SpiritIrqCheckFlag(RX_DATA_READY)) + * { + * // do something... + * } + * + * @endcode + *
    • + * + *
  • Check more than one Spirit IRQ status by storing the entire IRQ status registers into a bitfields @ref SpiritIrqs structure + * and then check the interested bits. + * + * Example: + * @code + * + * SpiritIrqGetStatus(&irqStatus); + * + * if(irqStatus.IRQ_RX_DATA_READY) + * { + * // do something... + * } + * if(irqStatus.IRQ_VALID_SYNC) + * { + * // do something... + * } + * if(irqStatus.RX_TIMEOUT) + * { + * // do something... + * } + * + * @endcode + *
    • + *
+ * + + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT1_IRQ_H +#define __SPIRIT1_IRQ_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Irq IRQ + * @brief Configuration and management of SPIRIT IRQs. + * @details See the file @ref SPIRIT_Irq.h for more details. + * @{ + */ + +/** + * @defgroup Irq_Exported_Types IRQ Exported Types + * @{ + */ + + +/** + * @brief IRQ bitfield structure for SPIRIT. This structure is used to read or write the single IRQ bit. + * During the initialization the user has to fill this structure setting to one the single field related + * to the IRQ he wants to enable, and to zero the single field related to all the IRQs he wants to disable. + * The same structure can be used to retrieve all the IRQ events from the IRQ registers IRQ_STATUS[3:0], + * and read if one or more specific IRQ raised. + * @note The fields order in the structure depends on used endianness (little or big + * endian). The actual definition is valid ONLY for LITTLE ENDIAN mode. Be sure to + * change opportunely the fields order when use a different endianness. + */ +typedef struct +{ + SpiritFlagStatus IRQ_RX_DATA_READY:1; /*!< IRQ: RX data ready */ + SpiritFlagStatus IRQ_RX_DATA_DISC:1; /*!< IRQ: RX data discarded (upon filtering) */ + SpiritFlagStatus IRQ_TX_DATA_SENT:1; /*!< IRQ: TX data sent */ + SpiritFlagStatus IRQ_MAX_RE_TX_REACH:1; /*!< IRQ: Max re-TX reached */ + SpiritFlagStatus IRQ_CRC_ERROR:1; /*!< IRQ: CRC error */ + SpiritFlagStatus IRQ_TX_FIFO_ERROR:1; /*!< IRQ: TX FIFO underflow/overflow error */ + SpiritFlagStatus IRQ_RX_FIFO_ERROR:1; /*!< IRQ: RX FIFO underflow/overflow error */ + SpiritFlagStatus IRQ_TX_FIFO_ALMOST_FULL:1; /*!< IRQ: TX FIFO almost full */ + + SpiritFlagStatus IRQ_TX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: TX FIFO almost empty */ + SpiritFlagStatus IRQ_RX_FIFO_ALMOST_FULL:1; /*!< IRQ: RX FIFO almost full */ + SpiritFlagStatus IRQ_RX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: RX FIFO almost empty */ + SpiritFlagStatus IRQ_MAX_BO_CCA_REACH:1; /*!< IRQ: Max number of back-off during CCA */ + SpiritFlagStatus IRQ_VALID_PREAMBLE:1; /*!< IRQ: Valid preamble detected */ + SpiritFlagStatus IRQ_VALID_SYNC:1; /*!< IRQ: Sync word detected */ + SpiritFlagStatus IRQ_RSSI_ABOVE_TH:1; /*!< IRQ: RSSI above threshold */ + SpiritFlagStatus IRQ_WKUP_TOUT_LDC:1; /*!< IRQ: Wake-up timeout in LDC mode */ + + SpiritFlagStatus IRQ_READY:1; /*!< IRQ: READY state */ + SpiritFlagStatus IRQ_STANDBY_DELAYED:1; /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ + SpiritFlagStatus IRQ_LOW_BATT_LVL:1; /*!< IRQ: Battery level below threshold*/ + SpiritFlagStatus IRQ_POR:1; /*!< IRQ: Power On Reset */ + SpiritFlagStatus IRQ_BOR:1; /*!< IRQ: Brown out event (both accurate and inaccurate)*/ + SpiritFlagStatus IRQ_LOCK:1; /*!< IRQ: LOCK state */ + SpiritFlagStatus IRQ_PM_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ + SpiritFlagStatus IRQ_XO_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ + + SpiritFlagStatus IRQ_SYNTH_LOCK_TIMEOUT:1; /*!< IRQ: only for debug; LOCK state timeout */ + SpiritFlagStatus IRQ_SYNTH_LOCK_STARTUP:1; /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ + SpiritFlagStatus IRQ_SYNTH_CAL_TIMEOUT:1; /*!< IRQ: only for debug; SYNTH calibration timeout */ + SpiritFlagStatus IRQ_TX_START_TIME:1; /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ + SpiritFlagStatus IRQ_RX_START_TIME:1; /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ + SpiritFlagStatus IRQ_RX_TIMEOUT:1; /*!< IRQ: RX operation timeout */ + SpiritFlagStatus IRQ_AES_END:1; /*!< IRQ: AES End of operation */ + SpiritFlagStatus :1; /*!< Reserved bit */ + +} SpiritIrqs; + + +/** + * @brief IRQ list enumeration for SPIRIT. This enumeration type can be used to address a + * specific IRQ. + */ +typedef enum +{ + RX_DATA_READY = 0x00000001, /*!< IRQ: RX data ready */ + RX_DATA_DISC = 0x00000002, /*!< IRQ: RX data discarded (upon filtering) */ + TX_DATA_SENT = 0x00000004, /*!< IRQ: TX data sent */ + MAX_RE_TX_REACH = 0x00000008, /*!< IRQ: Max re-TX reached */ + CRC_ERROR = 0x00000010, /*!< IRQ: CRC error */ + TX_FIFO_ERROR = 0x00000020, /*!< IRQ: TX FIFO underflow/overflow error */ + RX_FIFO_ERROR = 0x00000040, /*!< IRQ: RX FIFO underflow/overflow error */ + TX_FIFO_ALMOST_FULL = 0x00000080, /*!< IRQ: TX FIFO almost full */ + TX_FIFO_ALMOST_EMPTY = 0x00000100, /*!< IRQ: TX FIFO almost empty */ + RX_FIFO_ALMOST_FULL = 0x00000200, /*!< IRQ: RX FIFO almost full */ + RX_FIFO_ALMOST_EMPTY = 0x00000400, /*!< IRQ: RX FIFO almost empty */ + MAX_BO_CCA_REACH = 0x00000800, /*!< IRQ: Max number of back-off during CCA */ + VALID_PREAMBLE = 0x00001000, /*!< IRQ: Valid preamble detected */ + VALID_SYNC = 0x00002000, /*!< IRQ: Sync word detected */ + RSSI_ABOVE_TH = 0x00004000, /*!< IRQ: RSSI above threshold */ + WKUP_TOUT_LDC = 0x00008000, /*!< IRQ: Wake-up timeout in LDC mode */ + READY = 0x00010000, /*!< IRQ: READY state */ + STANDBY_DELAYED = 0x00020000, /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ + LOW_BATT_LVL = 0x00040000, /*!< IRQ: Battery level below threshold*/ + POR = 0x00080000, /*!< IRQ: Power On Reset */ + BOR = 0x00100000, /*!< IRQ: Brown out event (both accurate and inaccurate)*/ + LOCK = 0x00200000, /*!< IRQ: LOCK state */ + PM_COUNT_EXPIRED = 0x00400000, /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ + XO_COUNT_EXPIRED = 0x00800000, /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ + SYNTH_LOCK_TIMEOUT = 0x01000000, /*!< IRQ: only for debug; LOCK state timeout */ + SYNTH_LOCK_STARTUP = 0x02000000, /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ + SYNTH_CAL_TIMEOUT = 0x04000000, /*!< IRQ: only for debug; SYNTH calibration timeout */ + TX_START_TIME = 0x08000000, /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ + RX_START_TIME = 0x10000000, /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ + RX_TIMEOUT = 0x20000000, /*!< IRQ: RX operation timeout */ + AES_END = 0x40000000, /*!< IRQ: AES End of operation */ + ALL_IRQ = 0x7FFFFFFF /*!< All the above mentioned IRQs */ + +} IrqList; + +#define IS_SPIRIT_IRQ_LIST(VALUE) ((VALUE == RX_DATA_READY) || \ + (VALUE == RX_DATA_DISC) || \ + (VALUE == TX_DATA_SENT) || \ + (VALUE == MAX_RE_TX_REACH) || \ + (VALUE == CRC_ERROR) || \ + (VALUE == TX_FIFO_ERROR) || \ + (VALUE == RX_FIFO_ERROR) || \ + (VALUE == TX_FIFO_ALMOST_FULL) || \ + (VALUE == TX_FIFO_ALMOST_EMPTY) || \ + (VALUE == RX_FIFO_ALMOST_FULL) || \ + (VALUE == RX_FIFO_ALMOST_EMPTY) || \ + (VALUE == MAX_BO_CCA_REACH) || \ + (VALUE == VALID_PREAMBLE) || \ + (VALUE == VALID_SYNC) || \ + (VALUE == RSSI_ABOVE_TH) || \ + (VALUE == WKUP_TOUT_LDC) || \ + (VALUE == READY) || \ + (VALUE == STANDBY_DELAYED) || \ + (VALUE == LOW_BATT_LVL) || \ + (VALUE == POR) || \ + (VALUE == BOR) || \ + (VALUE == LOCK) || \ + (VALUE == PM_COUNT_EXPIRED) || \ + (VALUE == XO_COUNT_EXPIRED) || \ + (VALUE == SYNTH_LOCK_TIMEOUT) || \ + (VALUE == SYNTH_LOCK_STARTUP) || \ + (VALUE == SYNTH_CAL_TIMEOUT) || \ + (VALUE == TX_START_TIME) || \ + (VALUE == RX_START_TIME) || \ + (VALUE == RX_TIMEOUT) || \ + (VALUE == AES_END) || \ + (VALUE == ALL_IRQ )) + + +/** + * @} + */ + + +/** + * @defgroup Irq_Exported_Constants IRQ Exported Constants + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup Irq_Exported_Macros IRQ Exported Macros + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup Irq_Exported_Functions IRQ Exported Functions + * @{ + */ + +void SpiritIrqDeInit(SpiritIrqs* pxIrqInit); +void SpiritIrqInit(SpiritIrqs* pxIrqInit); +void SpiritIrq(IrqList xIrq, SpiritFunctionalState xNewState); +void SpiritIrqGetMask(SpiritIrqs* pxIrqMask); +void SpiritIrqGetStatus(SpiritIrqs* pxIrqStatus); +void SpiritIrqClearStatus(void); +SpiritBool SpiritIrqCheckFlag(IrqList xFlag); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_LinearFifo.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_LinearFifo.h new file mode 100644 index 000000000..f4e66a0ad --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_LinearFifo.h @@ -0,0 +1,136 @@ +/** + ****************************************************************************** + * @file SPIRIT_LinearFifo.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT Fifo. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_LINEAR_FIFO_H +#define __SPIRIT_LINEAR_FIFO_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_LinearFifo Linear FIFO + * @brief Configuration and management of SPIRIT FIFO. + * @details See the file @ref SPIRIT_LinearFifo.h for more details. + * @{ + */ + +/** + * @defgroup LinearFifo_Exported_Types Linear FIFO Exported Types + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup LinearFifo_Exported_Constants Linear FIFO Exported Constants + * @{ + */ +#define IS_FIFO_THR(VAL) (VAL<=96) + +/** + * @} + */ + + +/** + * @defgroup LinearFifo_Exported_Macros Linear FIFO Exported Macros + * @{ + */ + + +/** + * @} + */ + + +/** + * @defgroup LinearFifo_Exported_Functions Linear FIFO Exported Functions + * @{ + */ + +uint8_t SpiritLinearFifoReadNumElementsRxFifo(void); +uint8_t SpiritLinearFifoReadNumElementsTxFifo(void); +void SpiritLinearFifoSetAlmostFullThresholdRx(uint8_t cThrRxFifo); +uint8_t SpiritLinearFifoGetAlmostFullThresholdRx(void); +void SpiritLinearFifoSetAlmostEmptyThresholdRx(uint8_t cThrRxFifo); +uint8_t SpiritLinearFifoGetAlmostEmptyThresholdRx(void); +void SpiritLinearFifoSetAlmostFullThresholdTx(uint8_t cThrTxFifo); +uint8_t SpiritLinearFifoGetAlmostFullThresholdTx(void); +void SpiritLinearFifoSetAlmostEmptyThresholdTx(uint8_t cThrTxFifo); +uint8_t SpiritLinearFifoGetAlmostEmptyThresholdTx(void); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Management.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Management.h new file mode 100644 index 000000000..0f1bc49e2 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Management.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file SPIRIT_Management.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief The management layer for SPIRIT1 library. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef SPIRIT_MANAGEMENT_H_ +#define SPIRIT_MANAGEMENT_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Config.h" + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_MANAGEMENT Management + * @brief Workarounds for Spirit1. + * @details See the file @ref SPIRIT_Management.h for more details. + * @{ + */ + + +/** + * @addgroup SPIRIT_MANAGEMENT_FUNCTIONS + * @{ + */ + + + + +uint8_t SpiritManagementWaVcoCalibration(void); +void SpiritManagementWaCmdStrobeTx(void); +void SpiritManagementWaCmdStrobeRx(void); +void SpiritManagementWaTRxFcMem(uint32_t nDesiredFreq); +void SpiritManagementWaExtraCurrent(void); + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +#ifdef __cplusplus +} +#endif + + +#endif + + + /******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ + diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktBasic.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktBasic.h new file mode 100644 index 000000000..743cbb94e --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktBasic.h @@ -0,0 +1,696 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktBasic.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT Basic packets. + * + * @details + * + * This module can be used to manage the configuration of Spirit Basic + * packets. + * The user can obtain a packet configuration filling the structure + * @ref PktBasicInit, defining in it some general parameters + * for the Spirit Basic packet format. + * Another structure the user can fill is @ref PktBasicAddressesInit + * to define the addresses which will be used during the communication. + * Moreover, functions to set the payload length and the destination address + * are provided. + * + * Example: + * @code + * + * PktBasicInit basicInit={ + * PKT_PREAMBLE_LENGTH_08BYTES, // preamble length in bytes + * PKT_SYNC_LENGTH_4BYTES, // sync word length in bytes + * 0x1A2635A8, // sync word + * PKT_LENGTH_VAR, // variable or fixed payload length + * 7, // length field width in bits (used only for variable length) + * PKT_NO_CRC, // CRC mode + * PKT_CONTROL_LENGTH_0BYTES, // control field length + * S_ENABLE, // address field + * S_DISABLE, // FEC + * S_ENABLE // whitening + * }; + * + * PktBasicAddressesInit addressInit={ + * S_ENABLE, // enable/disable filtering on my address + * 0x34, // my address (address of the current node) + * S_DISABLE, // enable/disable filtering on multicast address + * 0xEE, // multicast address + * S_DISABLE, // enable/disable filtering on broadcast address + * 0xFF // broadcast address + * }; + * + * ... + * + * SpiritPktBasicInit(&basicInit); + * SpiritPktBasicAddressesInit(&addressInit); + * + * ... + * + * SpiritPktBasicSetPayloadLength(20); + * SpiritPktBasicSetDestinationAddress(0x44); + * + * ... + * + * @endcode + * + * The module provides some other functions that can be used to modify + * or read only some configuration parameters. + * + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_PKT_BASIC_H +#define __SPIRIT_PKT_BASIC_H + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" +#include "SPIRIT_PktCommon.h" + +#ifdef __cplusplus + extern "C" { +#endif + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_PktBasic Pkt Basic + * @brief Configuration and management of SPIRIT Basic packets. + * @details See the file @ref SPIRIT_PktBasic.h for more details. + * @{ + */ + +/** + * @defgroup PktBasic_Exported_Types Pkt Basic Exported Types + * @{ + */ + + +/** + * @brief Preamble length in bytes enumeration. + */ +typedef PktPreambleLength BasicPreambleLength; + +#define IS_BASIC_PREAMBLE_LENGTH IS_PKT_PREAMBLE_LENGTH + +/** + * @brief Sync length in bytes enumeration. + */ +typedef PktSyncLength BasicSyncLength; + +#define IS_BASIC_SYNC_LENGTH IS_PKT_SYNC_LENGTH + + + +/** + * @brief CRC length in bytes enumeration. + */ +typedef PktCrcMode BasicCrcMode; + +#define IS_BASIC_CRC_MODE IS_PKT_CRC_MODE + + +/** + * @brief Fixed or variable payload length enumeration. + */ +typedef PktFixVarLength BasicFixVarLength; + +#define IS_BASIC_FIX_VAR_LENGTH IS_PKT_FIX_VAR_LENGTH + +/** + * @brief Control length in bytes enumeration. + */ +typedef PktControlLength BasicControlLength; + +#define IS_BASIC_CONTROL_LENGTH IS_PKT_CONTROL_LENGTH + +/** + * @brief Sync words enumeration. + */ +typedef PktSyncX BasicSyncX; + +#define IS_BASIC_SYNCx IS_PKT_SYNCx + + +/** + * @brief SPIRIT Basic Packet Init structure definition. This structure allows users to set the main options + * for the Basic packet. + */ +typedef struct +{ + + BasicPreambleLength xPreambleLength; /*!< Specifies the preamble length. + This parameter can be any value of @ref BasicPreambleLength */ + BasicSyncLength xSyncLength; /*!< Specifies the sync word length. The 32bit word passed (lSyncWords) will be stored in the SYNCx registers from the MSb + until the number of bytes in xSyncLength has been stored. + This parameter can be any value of @ref BasicSyncLength */ + uint32_t lSyncWords; /*!< Specifies the sync words. + This parameter is a uint32_t word with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4| */ + BasicFixVarLength xFixVarLength; /*!< Specifies if a fixed length of packet has to be used. + This parameter can be any value of @ref BasicFixVarLength */ + uint8_t cPktLengthWidth; /*!< Specifies the size of the length of packet in bits. This field is useful only if + the field xFixVarLength is set to BASIC_LENGTH_VAR. For Basic packets the length width + is log2( max payload length + control length (0 to 4) + address length (0 or 1)). + This parameter is an uint8_t */ + BasicCrcMode xCrcMode; /*!< Specifies the CRC word length of packet. + This parameter can be any value of @ref BasicCrcMode */ + BasicControlLength xControlLength; /*!< Specifies the length of a control field to be sent. + This parameter can be any value of @ref BasicControlLength */ + SpiritFunctionalState xAddressField; /*!< Specifies if the destination address has to be sent. + This parameter can be S_ENABLE or S_DISABLE */ + SpiritFunctionalState xFec; /*!< Specifies if FEC has to be enabled. + This parameter can be S_ENABLE or S_DISABLE */ + SpiritFunctionalState xDataWhitening; /*!< Specifies if data whitening has to be enabled. + This parameter can be S_ENABLE or S_DISABLE */ +}PktBasicInit; + + +/** + * @brief SPIRIT Basic Packet address structure definition. This structure allows users to specify + * the node/multicast/broadcast addresses and the correspondent filtering options. + */ +typedef struct +{ + + SpiritFunctionalState xFilterOnMyAddress; /*!< If set RX packet is accepted if its destination address matches with cMyAddress. + This parameter can be S_ENABLE or S_DISABLE */ + uint8_t cMyAddress; /*!< Specifies the TX packet source address (address of this node). + This parameter is an uint8_t */ + SpiritFunctionalState xFilterOnMulticastAddress; /*!< If set RX packet is accepted if its destination address matches with cMulticastAddress. + This parameter can be S_ENABLE or S_DISABLE */ + uint8_t cMulticastAddress; /*!< Specifies the Multicast group address for this node. + This parameter is an uint8_t */ + SpiritFunctionalState xFilterOnBroadcastAddress; /*!< If set RX packet is accepted if its destination address matches with cBroadcastAddress. + This parameter can be S_ENABLE or S_DISABLE */ + uint8_t cBroadcastAddress; /*!< Specifies the Broadcast address for this node. + This parameter is an uint8_t */ +}PktBasicAddressesInit; + +/** + *@} + */ + + +/** + * @defgroup PktBasic_Exported_Constants Pkt Basic Exported Constants + * @{ + */ + +#define IS_BASIC_LENGTH_WIDTH_BITS IS_PKT_LENGTH_WIDTH_BITS + + +/** + *@} + */ + + +/** + * @defgroup PktBasic_Exported_Macros Pkt Basic Exported Macros + * @{ + */ + +/** + * @brief Macro used to compute per lower part of the packet length + * for Spirit Basic packets, to write in the PCKTLEN0 register. + * @param nLength Length of the packet payload. + * This parameter is an uint16_t. + * @retval None. + */ +#define BASIC_BUILD_PCKTLEN0(nLength) BUILD_PCKTLEN0(nLength) + + +/** + * @brief Macro used to compute per upper part of the packet length + * for Spirit Basic packets, to write the PCKTLEN1 register. + * @param nLengthLength of the packet payload. + * This parameter is an uint16_t. + * @retval None. + */ +#define BASIC_BUILD_PCKTLEN1(nLength) BUILD_PCKTLEN1(nLength) + +/** + * @brief Sets the CONTROL field length for SPIRIT Basic packets. + * @param xControlLength length of CONTROL field in bytes. + * This parameter can be any value of @ref PktControlLength. + * @retval None. + */ +#define SpiritPktBasicSetControlLength(xControlLength) SpiritPktCommonSetControlLength(xControlLength) + + +/** + * @brief Returns the CONTROL field length for SPIRIT Basic packets. + * @param None. + * @retval uint8_t Control field length. + */ +#define SpiritPktBasicGetControlLength() SpiritPktCommonGetControlLength() + + +/** + * @brief Sets the PREAMBLE field length for SPIRIT Basic packets. + * @param xPreambleLength length of PREAMBLE field in bytes. + * This parameter can be any value of @ref BasicPreambleLength. + * @retval None. + */ +#define SpiritPktBasicSetPreambleLength(xPreambleLength) SpiritPktCommonSetPreambleLength((PktPreambleLength)xPreambleLength) + + +/** + * @brief Returns the PREAMBLE field length mode for SPIRIT Basic packets. + * @param None. + * @retval uint8_t Preamble field length in bytes. + */ +#define SpiritPktBasicGetPreambleLength() SpiritPktCommonGetPreambleLength() + + +/** + * @brief Sets the SYNC field length for SPIRIT Basic packets. + * @param xSyncLength length of SYNC field in bytes. + * This parameter can be any value of @ref BasicSyncLength. + * @retval None. + */ +#define SpiritPktBasicSetSyncLength(xSyncLength) SpiritPktCommonSetSyncLength((PktSyncLength)xSyncLength) + + +/** + * @brief Returns the SYNC field length for SPIRIT Basic packets. + * @param None. + * @retval uint8_t SYNC field length in bytes. + */ +#define SpiritPktBasicGetSyncLength() SpiritPktCommonGetSyncLength() + + +/** + * @brief Sets fixed or variable payload length mode for SPIRIT packets. + * @param xFixVarLength variable or fixed length. + * BASIC_FIXED_LENGTH_VAR -> variable (the length is extracted from the received packet). + * BASIC_FIXED_LENGTH_FIX -> fix (the length is set by PCKTLEN0 and PCKTLEN1). + * @retval None. + */ +#define SpiritPktBasicSetFixVarLength(xFixVarLength) SpiritPktCommonSetFixVarLength((PktFixVarLength)xFixVarLength) + + +/** + * @brief Enables or Disables the CRC filtering. + * @param xNewState new state for CRC_CHECK. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktBasicFilterOnCrc(xNewState) SpiritPktCommonFilterOnCrc(xNewState) + + +/** + * @brief Returns the CRC filtering bit. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktBasicGetFilterOnCrc() SpiritPktCommonGetFilterOnCrc() + + +/** + * @brief Sets the CRC mode for SPIRIT Basic packets. + * @param xCrcMode CRC mode. + * This parameter can be any value of @ref BasicCrcMode. + * @retval None. + */ +#define SpiritPktBasicSetCrcMode(xCrcMode) SpiritPktCommonSetCrcMode((PktCrcMode)xCrcMode) + + +/** + * @brief Returns the CRC mode for SPIRIT Basic packets. + * @param None. + * @retval BasicCrcMode Crc mode. + */ +#define SpiritPktBasicGetCrcMode() (BasicCrcMode)SpiritPktCommonGetCrcMode() + + +/** + * @brief Enables or Disables WHITENING for SPIRIT packets. + * @param xNewState new state for WHITENING mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktBasicWhitening(xNewState) SpiritPktCommonWhitening(xNewState) + + +/** + * @brief Enables or Disables FEC for SPIRIT Basic packets. + * @param xNewState new state for FEC mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktBasicFec(xNewState) SpiritPktCommonFec(xNewState) + + +/** + * @brief Sets a specific SYNC word for SPIRIT Basic packets. + * @param xSyncX SYNC word number to be set. + * This parameter can be any value of @ref BasicSyncX. + * @param cSyncWord SYNC word. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktBasicSetSyncxWord(xSyncX, cSyncWord) SpiritPktCommonSetSyncxWord((PktSyncX)xSyncX, cSyncWord) + + +/** + * @brief Returns a specific SYNC words for SPIRIT Basic packets. + * @param xSyncX SYNC word number to be get. + * This parameter can be any value of @ref BasicSyncX. + * @retval uint8_t Sync word x. + */ +#define SpiritPktBasicGetSyncxWord(xSyncX) SpiritPktCommonGetSyncxWord(xSyncX) + + +/** + * @brief Sets multiple SYNC words for SPIRIT Basic packets. + * @param lSyncWords SYNC words to be set with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4|. + * This parameter is a uint32_t. + * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb + * until the number of bytes in xSyncLength has been stored. + * This parameter is a @ref BasicSyncLength. + * @retval None. + */ +#define SpiritPktBasicSetSyncWords(lSyncWords, xSyncLength) SpiritPktCommonSetSyncWords(lSyncWords, (PktSyncLength)xSyncLength) + + +/** + * @brief Returns multiple SYNC words for SPIRIT Basic packets. + * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb + * until the number of bytes in xSyncLength has been stored. + * This parameter is a pointer to @ref BasicSyncLength. + * @retval uint32_t Sync words. The format of the read 32 bit word is 0x|SYNC1|SYNC2|SYNC3|SYNC4|. + */ +#define SpiritPktBasicGetSyncWords(xSyncLength) SpiritPktCommonGetSyncWords((PktSyncLength)xSyncLength) + + +/** + * @brief Returns the SPIRIT variable length width (in number of bits). + * @param None. + * @retval Variable length width in bits. + */ +#define SpiritPktBasicGetVarLengthWidth() SpiritPktCommonGetVarLengthWidth() + + +/** + * @brief Sets the destination address for the Tx packet. + * @param cAddress destination address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktBasicSetDestinationAddress(cAddress) SpiritPktCommonSetDestinationAddress(cAddress) + + +/** + * @brief Returns the settled destination address. + * @param None. + * @retval uint8_t Transmitted destination address. + */ +#define SpiritPktBasicGetTransmittedDestAddress() SpiritPktCommonGetTransmittedDestAddress() + + +/** + * @brief Sets the node address. When the filtering on my address is on, if the destination address extracted from the received packet is equal to the content of the + * my address, then the packet is accepted (this is the address of the node). + * @param cAddress Address of the present node. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktBasicSetMyAddress(cAddress) SpiritPktCommonSetMyAddress(cAddress) + + +/** + * @brief Returns the address of the present node. + * @param None. + * @retval uint8_t My address (address of this node). + */ +#define SpiritPktBasicGetMyAddress() SpiritPktCommonGetMyAddress() + + +/** + * @brief Sets the broadcast address. When the broadcast filtering is on, if the destination address extracted from the received packet is equal to the content of the + * BROADCAST_ADDR register, then the packet is accepted. + * @param cAddress Broadcast address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktBasicSetBroadcastAddress(cAddress) SpiritPktCommonSetBroadcastAddress(cAddress) + + +/** + * @brief Returns the broadcast address. + * @param None. + * @retval uint8_t Broadcast address. + */ +#define SpiritPktBasicGetBroadcastAddress() SpiritPktCommonGetBroadcastAddress() + + +/** + * @brief Sets the multicast address. When the multicast filtering is on, if the destination address extracted from the received packet is equal to the content of the + * MULTICAST_ADDR register, then the packet is accepted. + * @param cAddress Multicast address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktBasicSetMulticastAddress(cAddress) SpiritPktCommonSetMulticastAddress(cAddress) + + +/** + * @brief Returns the multicast address. + * @param None. + * @retval uint8_t Multicast address. + */ +#define SpiritPktBasicGetMulticastAddress() SpiritPktCommonGetMulticastAddress() + + +/** + * @brief Sets the control mask. The 1 bits of the CONTROL_MASK indicate the + * bits to be used in filtering. (All 0s no filtering) + * @param lMask Control mask. + * This parameter is an uint32_t. + * @retval None. + */ +#define SpiritPktBasicSetCtrlMask(lMask) SpiritPktCommonSetCtrlMask(lMask) + + +/** + * @brief Returns the control mask. The 1 bits of the CONTROL_MASK indicate the + * bits to be used in filtering. (All 0s no filtering) + * @param None. + * @retval uint32_t Control mask. + */ +#define SpiritPktBasicGetCtrlMask() SpiritPktCommonGetCtrlMask() + + +/** + * @brief Sets the control field reference. If the bits enabled by the + * CONTROL_MASK match the ones of the control fields extracted from the received packet + * then the packet is accepted. + * @param lReference Control reference. + * This parameter is an uint32_t. + * @retval None. + */ +#define SpiritPktBasicSetCtrlReference(lReference) SpiritPktCommonSetCtrlReference(lReference) + + +/** + * @brief Returns the control field reference. + * @param None. + * @retval uint32_t Control reference. + */ +#define SpiritPktBasicGetCtrlReference() SpiritPktCommonGetCtrlReference() + + +/** + * @brief Sets the TX control field. + * @param lField Tx control field. + * This parameter is an uint32_t. + * @retval None. + */ +#define SpiritPktBasicSetTransmittedCtrlField(lField) SpiritPktCommonSetTransmittedCtrlField(lField) + + +/** + * @brief Returns the TX control field. + * @param None. + * @retval uint32_t Control field of the transmitted packet. + */ +#define SpiritPktBasicGetTransmittedCtrlField() SpiritPktCommonGetTransmittedCtrlField() + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with My address. + * @param xNewState new state for DEST_VS_SOURCE_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktBasicFilterOnMyAddress(xNewState) SpiritPktCommonFilterOnMyAddress(xNewState) + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with multicast address. + * @param xNewState new state for DEST_VS_MULTICAST_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktBasicFilterOnMulticastAddress(xNewState) SpiritPktCommonFilterOnMulticastAddress(xNewState) + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with broadcast address. + * @param xNewState new state for DEST_VS_BROADCAST_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktBasicFilterOnBroadcastAddress(xNewState) SpiritPktCommonFilterOnBroadcastAddress(xNewState) + + +/** + * @brief Returns the enable bit of the my address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktBasicGetFilterOnMyAddress() SpiritPktCommonGetFilterOnMyAddress(); + + +/** + * @brief Returns the enable bit of the multicast address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktBasicGetFilterOnMulticastAddress() SpiritPktCommonGetFilterOnMulticastAddress(); + + +/** + * @brief Returns the enable bit of the broadcast address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktBasicGetFilterOnBroadcastAddress() SpiritPktCommonGetFilterOnBroadcastAddress(); + + +/** + * @brief Returns the destination address of the received packet. + * @param None. + * @retval uint8_t Destination address of the received packet. + */ +#define SpiritPktBasicGetReceivedDestAddress() SpiritPktCommonGetReceivedDestAddress() + + +/** + * @brief Returns the control field of the received packet. + * @param None. + * @retval uint32_t Received control field. + */ +#define SpiritPktBasicGetReceivedCtrlField() SpiritPktCommonGetReceivedCtrlField() + + +/** + * @brief Returns the CRC field of the received packet. + * @param cCrcFieldVect array in which the CRC field has to be stored. + * This parameter is an uint8_t array of 3 elements. + * @retval None. + */ +#define SpiritPktBasicGetReceivedCrcField(cCrcFieldVect) SpiritPktCommonGetReceivedCrcField(cCrcFieldVect) + + +/** + * @brief If enabled RX packet is accepted only if the masked control field matches the + * masked control field reference (CONTROL_MASK & CONTROL_FIELD_REF == CONTROL_MASK & RX_CONTROL_FIELD). + * @param xNewState new state for Control filtering enable bit. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + * @note This filtering control is enabled by default but the control mask is by default set to 0. + * As a matter of fact the user has to enable the control filtering bit after the packet initialization + * because the PktInit routine disables it. + */ +#define SpiritPktBasicFilterOnControlField(xNewState) SpiritPktCommonFilterOnControlField(xNewState) + + +/** + * @brief Returns the enable bit of the control field filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktBasicGetFilterOnControlField() SpiritPktCommonGetFilterOnControlField(); + +/** + *@} + */ + + +/** + * @defgroup PktBasic_Exported_Functions Pkt Basic Exported Functions + * @{ + */ + +void SpiritPktBasicInit(PktBasicInit* pxPktBasicInit); +void SpiritPktBasicGetInfo(PktBasicInit* pxPktBasicInit); +void SpiritPktBasicAddressesInit(PktBasicAddressesInit* pxPktBasicAddresses); +void SpiritPktBasicGetAddressesInfo(PktBasicAddressesInit* pxPktBasicAddresses); +void SpiritPktBasicSetFormat(void); +void SpiritPktBasicAddressField(SpiritFunctionalState xAddressField); +SpiritFunctionalState SpiritPktBasicGetAddressField(void); +void SpiritPktBasicSetPayloadLength(uint16_t nPayloadLength); +uint16_t SpiritPktBasicGetPayloadLength(void); +uint16_t SpiritPktBasicGetReceivedPktLength(void); +void SpiritPktBasicSetVarLengthWidth(uint16_t nMaxPayloadLength,SpiritFunctionalState xAddressField, BasicControlLength xControlLength); + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktCommon.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktCommon.h new file mode 100644 index 000000000..ce81e8e4a --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktCommon.h @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktCommon.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of the common features of SPIRIT packets. + * + * @details + * + * This module provides all the common functions and definitions used by the + * packets modules. + * Here are also defined all the generic enumeration types that are redefined + * in the specific packets modules, but every enumeration value is referred + * to this module. So the user who wants to configure the preamble of a Basic, + * or a STack packet has to use the enumeration values defined here. + * + * Example: + * @code + * + * ... + * + * SpiritPktBasicSetPreambleLength(PKT_PREAMBLE_LENGTH_18BYTES); + * + * ... + * + * @endcode + * + * @note Is recommended for the user to not use these API directly + * importing this module in his application. + * + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_PKT_COMMON_H +#define __SPIRIT_PKT_COMMON_H + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_PktCommon Pkt Common + * @brief Configuration and management of the common features of SPIRIT packets. + * @details See the file @ref SPIRIT_PktCommon.h for more details. + * @{ + */ + +/** + * @defgroup PktCommon_Exported_Types Pkt Common Exported Types + * @{ + */ + + +/** + * @brief Preamble length in bytes enumeration. + */ +typedef enum +{ + PKT_PREAMBLE_LENGTH_01BYTE = 0x00, /*!< Preamble length 1 byte*/ + PKT_PREAMBLE_LENGTH_02BYTES = 0x08, /*!< Preamble length 2 bytes */ + PKT_PREAMBLE_LENGTH_03BYTES = 0x10, /*!< Preamble length 3 bytes */ + PKT_PREAMBLE_LENGTH_04BYTES = 0x18, /*!< Preamble length 4 bytes */ + PKT_PREAMBLE_LENGTH_05BYTES = 0x20, /*!< Preamble length 5 bytes */ + PKT_PREAMBLE_LENGTH_06BYTES = 0x28, /*!< Preamble length 6 bytes */ + PKT_PREAMBLE_LENGTH_07BYTES = 0x30, /*!< Preamble length 7 bytes */ + PKT_PREAMBLE_LENGTH_08BYTES = 0x38, /*!< Preamble length 8 bytes */ + PKT_PREAMBLE_LENGTH_09BYTES = 0x40, /*!< Preamble length 9 bytes */ + PKT_PREAMBLE_LENGTH_10BYTES = 0x48, /*!< Preamble length 10 bytes */ + PKT_PREAMBLE_LENGTH_11BYTES = 0x50, /*!< Preamble length 11 bytes */ + PKT_PREAMBLE_LENGTH_12BYTES = 0x58, /*!< Preamble length 12 bytes */ + PKT_PREAMBLE_LENGTH_13BYTES = 0x60, /*!< Preamble length 13 bytes */ + PKT_PREAMBLE_LENGTH_14BYTES = 0x68, /*!< Preamble length 14 bytes */ + PKT_PREAMBLE_LENGTH_15BYTES = 0x70, /*!< Preamble length 15 bytes */ + PKT_PREAMBLE_LENGTH_16BYTES = 0x78, /*!< Preamble length 16 bytes */ + PKT_PREAMBLE_LENGTH_17BYTES = 0x80, /*!< Preamble length 17 bytes */ + PKT_PREAMBLE_LENGTH_18BYTES = 0x88, /*!< Preamble length 18 bytes */ + PKT_PREAMBLE_LENGTH_19BYTES = 0x90, /*!< Preamble length 19 bytes */ + PKT_PREAMBLE_LENGTH_20BYTES = 0x98, /*!< Preamble length 20 bytes */ + PKT_PREAMBLE_LENGTH_21BYTES = 0xA0, /*!< Preamble length 21 bytes */ + PKT_PREAMBLE_LENGTH_22BYTES = 0xA8, /*!< Preamble length 22 bytes */ + PKT_PREAMBLE_LENGTH_23BYTES = 0xB0, /*!< Preamble length 23 bytes */ + PKT_PREAMBLE_LENGTH_24BYTES = 0xB8, /*!< Preamble length 24 bytes */ + PKT_PREAMBLE_LENGTH_25BYTES = 0xC0, /*!< Preamble length 25 bytes */ + PKT_PREAMBLE_LENGTH_26BYTES = 0xC8, /*!< Preamble length 26 bytes */ + PKT_PREAMBLE_LENGTH_27BYTES = 0xD0, /*!< Preamble length 27 bytes */ + PKT_PREAMBLE_LENGTH_28BYTES = 0xD8, /*!< Preamble length 28 bytes */ + PKT_PREAMBLE_LENGTH_29BYTES = 0xE0, /*!< Preamble length 29 bytes */ + PKT_PREAMBLE_LENGTH_30BYTES = 0xE8, /*!< Preamble length 30 bytes */ + PKT_PREAMBLE_LENGTH_31BYTES = 0xF0, /*!< Preamble length 31 bytes */ + PKT_PREAMBLE_LENGTH_32BYTES = 0xF8 /*!< Preamble length 32 bytes */ + +}PktPreambleLength; + +#define IS_PKT_PREAMBLE_LENGTH(LENGTH) ((LENGTH == PKT_PREAMBLE_LENGTH_01BYTE) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_02BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_03BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_04BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_05BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_06BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_07BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_08BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_09BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_10BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_11BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_12BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_13BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_14BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_15BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_16BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_17BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_18BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_19BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_20BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_21BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_22BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_23BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_24BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_25BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_26BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_27BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_28BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_29BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_30BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_31BYTES) || \ + (LENGTH == PKT_PREAMBLE_LENGTH_32BYTES)) + + + +/** + * @brief Sync length in bytes enumeration. + */ +typedef enum +{ + PKT_SYNC_LENGTH_1BYTE = 0x00, /*!< Sync length 1 byte*/ + PKT_SYNC_LENGTH_2BYTES = 0x02, /*!< Sync length 2 bytes*/ + PKT_SYNC_LENGTH_3BYTES = 0x04, /*!< Sync length 3 bytes */ + PKT_SYNC_LENGTH_4BYTES = 0x06 , /*!< Sync length 4 bytes */ + +}PktSyncLength; + +#define IS_PKT_SYNC_LENGTH(LENGTH) ((LENGTH == PKT_SYNC_LENGTH_1BYTE) || \ + (LENGTH == PKT_SYNC_LENGTH_2BYTES)|| \ + (LENGTH == PKT_SYNC_LENGTH_3BYTES)|| \ + (LENGTH == PKT_SYNC_LENGTH_4BYTES)) + + + +/** + * @brief CRC length in bytes enumeration. + */ +typedef enum +{ + PKT_NO_CRC = 0x00, /*!< No CRC */ + PKT_CRC_MODE_8BITS = 0x20, /*!< CRC length 8 bits - poly: 0x07 */ + PKT_CRC_MODE_16BITS_1 = 0x40, /*!< CRC length 16 bits - poly: 0x8005 */ + PKT_CRC_MODE_16BITS_2 = 0x60, /*!< CRC length 16 bits - poly: 0x1021 */ + PKT_CRC_MODE_24BITS = 0x80, /*!< CRC length 24 bits - poly: 0x864CFB */ + +}PktCrcMode; + +#define IS_PKT_CRC_MODE(MODE) ((MODE == PKT_NO_CRC) || \ + (MODE == PKT_CRC_MODE_8BITS) || \ + (MODE == PKT_CRC_MODE_16BITS_1) || \ + (MODE == PKT_CRC_MODE_16BITS_2) || \ + (MODE == PKT_CRC_MODE_24BITS)) + + + +/** + * @brief Fixed or variable payload length enumeration. + */ +typedef enum +{ + PKT_LENGTH_FIX = 0x00, /*!< Fixed payload length */ + PKT_LENGTH_VAR = 0x01 /*!< Variable payload length */ + +}PktFixVarLength; + +#define IS_PKT_FIX_VAR_LENGTH(LENGTH) ((LENGTH == PKT_LENGTH_FIX) || \ + (LENGTH == PKT_LENGTH_VAR)) + + +/** + * @brief Control length in bytes enumeration for SPIRIT packets. + */ +typedef enum +{ + PKT_CONTROL_LENGTH_0BYTES = 0x00, /*!< Control length 0 byte*/ + PKT_CONTROL_LENGTH_1BYTE, /*!< Control length 1 byte*/ + PKT_CONTROL_LENGTH_2BYTES, /*!< Control length 2 bytes*/ + PKT_CONTROL_LENGTH_3BYTES, /*!< Control length 3 bytes*/ + PKT_CONTROL_LENGTH_4BYTES /*!< Control length 4 bytes*/ + +}PktControlLength; + +#define IS_PKT_CONTROL_LENGTH(LENGTH) ((LENGTH == PKT_CONTROL_LENGTH_0BYTES) || \ + (LENGTH == PKT_CONTROL_LENGTH_1BYTE) || \ + (LENGTH == PKT_CONTROL_LENGTH_2BYTES) || \ + (LENGTH == PKT_CONTROL_LENGTH_3BYTES) || \ + (LENGTH == PKT_CONTROL_LENGTH_4BYTES)) + +/** + * @brief Sync words enumeration for SPIRIT packets. + */ +typedef enum +{ + PKT_SYNC_WORD_1=0x01, /*!< Index of the 1st sync word*/ + PKT_SYNC_WORD_2, /*!< Index of the 2nd sync word*/ + PKT_SYNC_WORD_3, /*!< Index of the 3rd sync word*/ + PKT_SYNC_WORD_4 /*!< Index of the 4th sync word*/ + +}PktSyncX; + +#define IS_PKT_SYNCx(WORD) ((WORD == PKT_SYNC_WORD_1) || \ + (WORD == PKT_SYNC_WORD_2) || \ + (WORD == PKT_SYNC_WORD_3) || \ + (WORD == PKT_SYNC_WORD_4)) + + + +/** + * @brief Max retransmissions number enumeration for SPIRIT packets. + */ +typedef enum +{ + PKT_DISABLE_RETX = 0x00, /*!< No retrasmissions*/ + PKT_N_RETX_1 = 0x10, /*!< Max retrasmissions 1*/ + PKT_N_RETX_2 = 0x20, /*!< Max retrasmissions 2*/ + PKT_N_RETX_3 = 0x30, /*!< Max retrasmissions 3*/ + PKT_N_RETX_4 = 0x40, /*!< Max retrasmissions 4*/ + PKT_N_RETX_5 = 0x50, /*!< Max retrasmissions 5*/ + PKT_N_RETX_6 = 0x60, /*!< Max retrasmissions 6*/ + PKT_N_RETX_7 = 0x70, /*!< Max retrasmissions 7*/ + PKT_N_RETX_8 = 0x80, /*!< Max retrasmissions 8*/ + PKT_N_RETX_9 = 0x90, /*!< Max retrasmissions 9*/ + PKT_N_RETX_10 = 0xA0, /*!< Max retrasmissions 10*/ + PKT_N_RETX_11 = 0xB0, /*!< Max retrasmissions 11*/ + PKT_N_RETX_12 = 0xC0, /*!< Max retrasmissions 12*/ + PKT_N_RETX_13 = 0xD0, /*!< Max retrasmissions 13*/ + PKT_N_RETX_14 = 0xE0, /*!< Max retrasmissions 14*/ + PKT_N_RETX_15 = 0xF0 /*!< Max retrasmissions 15*/ + +}PktNMaxReTx; + +#define IS_PKT_NMAX_RETX(N_RETX) ((N_RETX == PKT_DISABLE_RETX) || \ + (N_RETX == PKT_N_RETX_1) || \ + (N_RETX == PKT_N_RETX_2) || \ + (N_RETX == PKT_N_RETX_3) || \ + (N_RETX == PKT_N_RETX_4) || \ + (N_RETX == PKT_N_RETX_5) || \ + (N_RETX == PKT_N_RETX_6) || \ + (N_RETX == PKT_N_RETX_7) || \ + (N_RETX == PKT_N_RETX_8) || \ + (N_RETX == PKT_N_RETX_9) || \ + (N_RETX == PKT_N_RETX_10) || \ + (N_RETX == PKT_N_RETX_11) || \ + (N_RETX == PKT_N_RETX_12) || \ + (N_RETX == PKT_N_RETX_13) || \ + (N_RETX == PKT_N_RETX_14) || \ + (N_RETX == PKT_N_RETX_15)) + + +/** + *@} + */ + + +/** + * @defgroup PktCommon_Exported_Constants Pkt Common Exported Constants + * @{ + */ + +#define IS_PKT_LENGTH_WIDTH_BITS(BITS) (BITS<=16) +#define IS_PKT_SEQ_NUMBER_RELOAD(SEQN) (SEQN<=3) + +/** + *@} + */ + + +/** + * @defgroup PktCommon_Exported_Macros Pkt Common Exported Macros + * @{ + */ + + +/** + * @brief Macro used to compute the lower part of the packet length, to write in the PCKTLEN0 register + * @param nLength Length of the packet payload. + * This parameter is an uint16_t. + * @retval None. + */ +#define BUILD_PCKTLEN0(nLength) (nLength & 0xFF) + + +/** + * @brief Macro used to compute the upper part of the packet length, to write the PCKTLEN1 register + * @param nLength Length of the packet payload. + * This parameter is an uint16_t. + * @retval None. + */ +#define BUILD_PCKTLEN1(nLength) (nLength >> 8) + +/** + *@} + */ + + +/** + * @defgroup PktCommon_Exported_Functions Pkt Common Exported Functions + * @{ + */ + +void SpiritPktCommonSetControlLength(PktControlLength xControlLength); +uint8_t SpiritPktCommonGetControlLength(void); +void SpiritPktCommonSetPreambleLength(PktPreambleLength xPreambleLength); +uint8_t SpiritPktCommonGetPreambleLength(void); +void SpiritPktCommonSetSyncLength(PktSyncLength xSyncLength); +uint8_t SpiritPktCommonGetSyncLength(void); +void SpiritPktCommonSetFixVarLength(PktFixVarLength xFixVarLength); +void SpiritPktCommonFilterOnCrc(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritPktCommonGetFilterOnCrc(void); +void SpiritPktCommonSetCrcMode(PktCrcMode xCrcLength); +PktCrcMode SpiritPktCommonGetCrcMode(void); +void SpiritPktCommonWhitening(SpiritFunctionalState xNewState); +void SpiritPktCommonFec(SpiritFunctionalState xNewState); +void SpiritPktCommonSetSyncxWord(PktSyncX xSyncX, uint8_t cSyncWord); +uint8_t SpiritPktCommonGetSyncxWord(PktSyncX xSyncX); +void SpiritPktCommonSetSyncWords(uint32_t lSyncWords, PktSyncLength xSyncLength); +uint32_t SpiritPktCommonGetSyncWords(PktSyncLength xSyncLength); +uint8_t SpiritPktCommonGetVarLengthWidth(void); +void SpiritPktCommonSetDestinationAddress(uint8_t cAddress); +uint8_t SpiritPktCommonGetTransmittedDestAddress(void); +void SpiritPktCommonSetMyAddress(uint8_t cAddress); +uint8_t SpiritPktCommonGetMyAddress(void); +void SpiritPktCommonSetBroadcastAddress(uint8_t cAddress); +uint8_t SpiritPktCommonGetBroadcastAddress(void); +SpiritFunctionalState SpiritPktCommonGetTxAckRequest(void); +void SpiritPktCommonSetMulticastAddress(uint8_t cAddress); +uint8_t SpiritPktCommonGetMulticastAddress(void); +void SpiritPktCommonSetCtrlMask(uint32_t lMask); +uint32_t SpiritPktCommonGetCtrlMask(void); +void SpiritPktCommonSetCtrlReference(uint32_t lReference); +uint32_t SpiritPktCommonGetCtrlReference(void); +void SpiritPktCommonSetTransmittedCtrlField(uint32_t lField); +uint32_t SpiritPktCommonGetTransmittedCtrlField(void); +void SpiritPktCommonFilterOnMyAddress(SpiritFunctionalState xNewState); +void SpiritPktCommonFilterOnMulticastAddress(SpiritFunctionalState xNewState); +void SpiritPktCommonFilterOnBroadcastAddress(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritPktCommonGetFilterOnMyAddress(void); +SpiritFunctionalState SpiritPktCommonGetFilterOnMulticastAddress(void); +SpiritFunctionalState SpiritPktCommonGetFilterOnBroadcastAddress(void); +uint8_t SpiritPktCommonGetReceivedDestAddress(void); +uint32_t SpiritPktCommonGetReceivedCtrlField(void); +void SpiritPktCommonGetReceivedCrcField(uint8_t* cCrcFieldVect); +void SpiritPktCommonAutoAck(SpiritFunctionalState xAutoAck,SpiritFunctionalState xPiggybacking); +void SpiritPktCommonRequireAck(SpiritFunctionalState xRequireAck); +void SpiritPktCommonSetTransmittedSeqNumberReload(uint8_t cSeqNumberReload); +void SpiritPktCommonSetNMaxReTx(PktNMaxReTx xNMaxReTx); +uint8_t SpiritPktCommonGetNMaxReTx(void); +uint8_t SpiritPktCommonGetReceivedDestAddress(void); +uint8_t SpiritPktCommonGetReceivedSourceAddress(void); +uint8_t SpiritPktCommonGetReceivedSeqNumber(void); +uint8_t SpiritPktCommonGetReceivedNackRx(void); +uint8_t SpiritPktCommonGetTransmittedSeqNumber(void); +uint8_t SpiritPktCommonGetNReTx(void); +void SpiritPktCommonFilterOnControlField(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritPktCommonGetFilterOnControlField(void); + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktMbus.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktMbus.h new file mode 100644 index 000000000..2d524bf83 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktMbus.h @@ -0,0 +1,206 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktMbus.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT MBUS packets. + * + * @details + * + * This module can be used to manage the configuration of Spirit MBUS + * packets. + * The user can obtain a packet configuration filling the structure + * @ref PktMbusInit, defining in it some general parameters + * for the Spirit MBUS packet format. + * Since the MBUS protocol is a standard, the configuration of a MBUS + * packet is very simple to do. + * + * Example: + * @code + * + * PktMbusInit mbusInit={ + * MBUS_SUBMODE_S1_S2_LONG_HEADER, // MBUS submode selection + * 36, // added "01" chips on preamble + * 16 // postamble length in "01" chips + * }; + * + * ... + * + * SpiritPktMbusInit(&mbusInit); + * + * ... + * + * @endcode + * + * The module provides some other functions that can be used to modify + * or read only some configuration parameters. + * + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_PACKET_MBUS_H +#define __SPIRIT_PACKET_MBUS_H + + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" +#include "SPIRIT_PktCommon.h" + +#ifdef __cplusplus + extern "C" { +#endif + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_PktMbus Pkt MBUS + * @brief Configuration and management of SPIRIT MBUS packets. + * @details See the file @ref SPIRIT_PktMbus.h for more details. + * @{ + */ + +/** + * @defgroup PktMbus_Exported_Types Pkt MBUS Exported Types + * @{ + */ + + + +/** + * @brief MBUS submode enumeration. + */ + +typedef enum +{ + MBUS_SUBMODE_S1_S2_LONG_HEADER = MBUS_CTRL_MBUS_SUBMODE_S1_S2L, /*!< MBUS submode S1, S2 (long header) - Header length = mbus_prmbl_ctrl + 279 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits) */ + MBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER = MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER, /*!< MBUS submode S1-m, S2, T2 (other to meter) - Header length = mbus_prmbl_ctrl + 15 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits)*/ + MBUS_SUBMODE_T1_T2_METER_TO_OTHER = MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER, /*!< MBUS submode T1, T2 (meter to other) - Header length = mbus_prmbl_ctrl + 19 (in "01" bit pairs) , Sync word = 0x3D (length 10 bits)*/ + MBUS_SUBMODE_R2_SHORT_HEADER = MBUS_CTRL_MBUS_SUBMODE_R2, /*!< MBUS submode R2, short header - Header length = mbus_prmbl_ctrl + 39 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits)*/ + +}MbusSubmode; + +#define IS_MBUS_SUBMODE(MODE) (((MODE) == MBUS_SUBMODE_S1_S2_LONG_HEADER) || \ + ((MODE) == MBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER) || \ + ((MODE) == MBUS_SUBMODE_T1_T2_METER_TO_OTHER) || \ + ((MODE) == MBUS_SUBMODE_R2_SHORT_HEADER)) + + +/** + * @brief SPIRIT MBUS Packet Init structure definition + */ +typedef struct +{ + MbusSubmode xMbusSubmode; /*!< Specifies the SUBMODE to be configured. + This parameter can be a value of @ref MbusSubmode */ + + uint8_t cPreambleLength; /*!< Specifies the PREAMBLE length. + This parameter can be any value between 0 and 255 chip sequence '01' */ + + uint8_t cPostambleLength; /*!< Specifies the POSTAMBLE length. + This parameter can be any value between 0 and 255 chip sequence '01' */ + +}PktMbusInit; + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Exported_Constants Pkt MBUS Exported Constants + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Exported_Macros Pkt MBUS Exported Macros + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Exported_Functions Pkt MBUS Exported Functions + * @{ + */ +void SpiritPktMbusInit(PktMbusInit* pxPktMbusInit); +void SpiritPktMbusGetInfo(PktMbusInit* pxPktMbusInit); +void SpiritPktMbusSetFormat(void); +void SpiritPktMbusSetPreamble(uint8_t cPreamble); +uint8_t SpiritPktMbusGetPreamble(void); +void SpiritPktMbusSetPostamble(uint8_t cPostamble); +uint8_t SpiritPktMbusGetPostamble(void); +void SpiritPktMbusSetSubmode(MbusSubmode xMbusSubmode); +MbusSubmode SpiritPktMbusGetSubmode(void); +void SpiritPktMbusSetPayloadLength(uint16_t nPayloadLength); +uint16_t SpiritPktMbusGetPayloadLength(void); + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktStack.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktStack.h new file mode 100644 index 000000000..8255ac5dc --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktStack.h @@ -0,0 +1,849 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktStack.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT STack packets. + * + * @details + * + * This module can be used to manage the configuration of Spirit STack + * packets, and it is quite similar to the Basic packets one since the + * STack packets can be considered an extension of Basic. + * The user can obtain a packet configuration filling the structure + * @ref PktStackInit, defining in it some general parameters + * for the Spirit STack packet format. + * Another structure the user can fill is @ref PktStackAddressesInit + * to define the addresses which will be used during the communication. + * The structure @ref PktStackLlpInit is provided in order to configure + * the link layer protocol features like autoack, autoretransmission + * or piggybacking. + * Moreover, functions to set the payload length and the destination address + * are provided. + * + * Example: + * @code + * + * PktStackInit stackInit={ + * PKT_PREAMBLE_LENGTH_08BYTES, // preamble length in bytes + * PKT_SYNC_LENGTH_4BYTES, // sync word length in bytes + * 0x1A2635A8, // sync word + * PKT_LENGTH_VAR, // variable or fixed payload length + * 7, // length field width in bits (used only for variable length) + * PKT_NO_CRC, // CRC mode + * PKT_CONTROL_LENGTH_0BYTES, // control field length + * S_DISABLE, // FEC + * S_ENABLE // whitening + * }; + * + * PktStackAddressesInit addressInit={ + * S_ENABLE, // enable/disable filtering on my address + * 0x34, // my address (address of the current node) + * S_DISABLE, // enable/disable filtering on multicast address + * 0xEE, // multicast address + * S_DISABLE, // enable/disable filtering on broadcast address + * 0xFF // broadcast address + * }; + * + * PktStackLlpInit stackLLPInit ={ + * S_DISABLE, // enable/disable the autoack feature + * S_DISABLE, // enable/disable the piggybacking feature + * PKT_DISABLE_RETX // set the max number of retransmissions or disable them + * }; + * ... + * + * SpiritPktStackInit(&stackInit); + * SpiritPktStackAddressesInit(&addressInit); + * SpiritPktStackLlpInit(&stackLLPInit); + * + * ... + * + * SpiritPktStackSetPayloadLength(20); + * SpiritPktStackSetDestinationAddress(0x44); + * + * ... + * + * @endcode + * + * The module provides some other functions that can be used to modify + * or read only some configuration parameters. + * + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_PKT_STACK_H +#define __SPIRIT_PKT_STACK_H + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" +#include "SPIRIT_PktCommon.h" + +#ifdef __cplusplus + extern "C" { +#endif + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_PktStack Pkt STack + * @brief Configuration and management of SPIRIT STack packets. + * @details See the file @ref SPIRIT_PktStack.h for more details. + * @{ + */ + +/** + * @defgroup PktStack_Exported_Types Pkt STack Exported Types + * @{ + */ + +/** + * @brief Preamble length in bytes enumeration. + */ +typedef PktPreambleLength StackPreambleLength; + +#define IS_STACK_PREAMBLE_LENGTH IS_PKT_PREAMBLE_LENGTH + +/** + * @brief Sync length in bytes enumeration. + */ +typedef PktSyncLength StackSyncLength; + +#define IS_STACK_SYNC_LENGTH IS_PKT_SYNC_LENGTH + + + +/** + * @brief CRC length in bytes enumeration. + */ +typedef PktCrcMode StackCrcMode; + +#define IS_STACK_CRC_MODE IS_PKT_CRC_MODE + + +/** + * @brief Fixed or variable payload length enumeration. + */ +typedef PktFixVarLength StackFixVarLength; + +#define IS_STACK_FIX_VAR_LENGTH IS_PKT_FIX_VAR_LENGTH + +/** + * @brief Control length in bytes enumeration for SPIRIT. + */ +typedef PktControlLength StackControlLength; + +#define IS_STACK_CONTROL_LENGTH IS_PKT_CONTROL_LENGTH + +/** + * @brief Sync words enumeration for SPIRIT. + */ +typedef PktSyncX StackSyncX; + +#define IS_STACK_SYNCx IS_PKT_SYNCx + +/** + * @brief Max retransmission number enumeration for SPIRIT. + */ +typedef PktNMaxReTx StackNMaxReTx; + +#define IS_STACK_NMAX_RETX IS_PKT_NMAX_RETX + + +/** + * @brief SPIRIT STack Packet Init structure definition. This structure allows users to set the main options + * for the STack packet. + */ +typedef struct +{ + + StackPreambleLength xPreambleLength; /*!< Specifies the preamble length of packet. + This parameter can be any value of @ref StackPreambleLength */ + StackSyncLength xSyncLength; /*!< Specifies the sync word length of packet. + This parameter can be any value of @ref StackSyncLength */ + uint32_t lSyncWords; /*!< Specifies the sync words. + This parameter is a uint32_t word with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4| */ + StackFixVarLength xFixVarLength; /*!< Specifies if a fixed length of packet has to be used. + This parameter can be any value of @ref StackFixVarLength */ + uint8_t cPktLengthWidth; /*!< Specifies the size of the length of packet in bits. This field is useful only if + the field xFixVarLength is set to STACK_LENGTH_VAR. For STack packets the length width + is log2( max payload length + control length (0 to 4) + address length (always 2)). + This parameter is an uint8_t */ + StackCrcMode xCrcMode; /*!< Specifies the CRC word length of packet. + This parameter can be any value of @ref StackCrcMode */ + StackControlLength xControlLength; /*!< Specifies the length of a control field to be sent. + This parameter can be any value of @ref StackControlLength */ + SpiritFunctionalState xFec; /*!< Specifies if FEC has to be enabled. + This parameter can be any value of @ref SpiritFunctionalState */ + SpiritFunctionalState xDataWhitening; /*!< Specifies if data whitening has to be enabled. + This parameter can be any value of @ref SpiritFunctionalState */ + +}PktStackInit; + + +/** + * @brief SPIRIT STack packet address structure definition. This structure allows users to specify + * the node/multicast/broadcast addresses and the correspondent filtering options. + */ +typedef struct +{ + + SpiritFunctionalState xFilterOnMyAddress; /*!< If set RX packet is accepted if its destination address matches with cMyAddress. + This parameter can be S_ENABLE or S_DISABLE */ + uint8_t cMyAddress; /*!< Specifies the TX packet source address (address of this node). + This parameter is an uint8_t */ + SpiritFunctionalState xFilterOnMulticastAddress; /*!< If set RX packet is accepted if its destination address matches with cMulticastAddress. + This parameter can be S_ENABLE or S_DISABLE */ + uint8_t cMulticastAddress; /*!< Specifies the Multicast group address for this node. + This parameter is an uint8_t */ + SpiritFunctionalState xFilterOnBroadcastAddress; /*!< If set RX packet is accepted if its destination address matches with cBroadcastAddress. + This parameter can be S_ENABLE or S_DISABLE */ + uint8_t cBroadcastAddress; /*!< Specifies the Broadcast address for this node. + This parameter is an uint8_t */ +}PktStackAddressesInit; + + +/** + * @brief SPIRIT STack packet LLP structure definition. This structure allows users to configure + * all the LLP options for STack packets. + */ +typedef struct +{ + + SpiritFunctionalState xAutoAck; /*!< Specifies if the auto ACK feature is used or not. + This parameter can be a value of @ref SpiritFunctionalState */ + SpiritFunctionalState xPiggybacking; /*!< Specifies if the piggybacking feature is used or not. + This parameter can be a value of @ref SpiritFunctionalState */ + StackNMaxReTx xNMaxRetx; /*!< Specifies the number of MAX-Retransmissions. + This parameter can be a value of @ref StackNMaxReTx */ +}PktStackLlpInit; + + + +/** + *@} + */ + + +/** + * @defgroup PktStack_Exported_Constants Pkt STack Exported Constants + * @{ + */ + +#define IS_STACK_LENGTH_WIDTH_BITS IS_PKT_LENGTH_WIDTH_BITS + +/** + *@} + */ + + +/** + * @defgroup PktStack_Exported_Macros Pkt STack Exported Macros + * @{ + */ + +/** + * @brief Macro used to compute the lower part of the packet length + * for Spirit STack packets, to write in the PCKTLEN0 register. + * @param nLength length of the packet payload. + * This parameter is an uint16_t. + * @retval None. + */ +#define STACK_BUILD_PCKTLEN0(nLength) BUILD_PCKTLEN0(nLength) + + +/** + * @brief Macro used to compute the upper part of the packet length + * for Spirit STack packets, to write the PCKTLEN1 register. + * @param nLength length of the packet payload. + * This parameter is an uint16_t. + * @retval None. + */ +#define STACK_BUILD_PCKTLEN1(nLength) BUILD_PCKTLEN1(nLength) + + +/** + * @brief Sets the CONTROL length for SPIRIT STack packets. + * @param xControlLength length of CONTROL field in bytes. + * This parameter can be any value of @ref StackControlLength. + * @retval None. + */ +#define SpiritPktStackSetControlLength(xControlLength) SpiritPktCommonSetControlLength(xControlLength) + + +/** + * @brief Returns the CONTROL length for SPIRIT STack packets. + * @param None. + * @retval Control length. + */ +#define SpiritPktStackGetControlLength() SpiritPktCommonGetControlLength() + + +/** + * @brief Sets the PREAMBLE Length mode for SPIRIT STack packets. + * @param xPreambleLength length of PREAMBLE field in bytes. + * This parameter can be any value of @ref StackPreambleLength. + * @retval None. + */ +#define SpiritPktStackSetPreambleLength(xPreambleLength) SpiritPktCommonSetPreambleLength((PktPreambleLength)xPreambleLength) + + +/** + * @brief Returns the PREAMBLE Length mode for SPIRIT STack packets. + * @param None. + * @retval uint8_t Preamble length in bytes. + */ +#define SpiritPktStackGetPreambleLength() SpiritPktCommonGetPreambleLength() + + +/** + * @brief Sets the SYNC Length for SPIRIT STack packets. + * @param xSyncLength length of SYNC field in bytes. + * This parameter can be any value of @ref StackSyncLength. + * @retval None. + */ +#define SpiritPktStackSetSyncLength(xSyncLength) SpiritPktCommonSetSyncLength((PktSyncLength)xSyncLength) + + +/** + * @brief Returns the SYNC Length for SPIRIT STack packets. + * @param None. + * @retval uint8_t Sync length in bytes. + */ +#define SpiritPktStackGetSyncLength() SpiritPktCommonGetSyncLength() + + +/** + * @brief Sets fixed or variable payload length mode for SPIRIT STack packets. + * @param xFixVarLength variable or fixed length. + * PKT_FIXED_LENGTH_VAR -> variable (the length is extracted from the received packet). + * PKT_FIXED_LENGTH_FIX -> fix (the length is set by PCKTLEN0 and PCKTLEN1). + * @retval None. + */ +#define SpiritPktStackSetFixVarLength(xFixVarLength) SpiritPktCommonSetFixVarLength((PktFixVarLength)xFixVarLength) + + +/** + * @brief Enables or Disables the CRC filtering. + * @param xNewState new state for CRC_CHECK. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackFilterOnCrc(xNewState) SpiritPktCommonFilterOnCrc(xNewState) + + +/** + * @brief Returns the CRC filtering bit. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktStackGetFilterOnCrc() SpiritPktCommonGetFilterOnCrc() + + +/** + * @brief Sets the CRC mode for SPIRIT STack packets. + * @param xCrcMode CRC mode. + * This parameter can be any value of @ref StackCrcMode. + * @retval None. + */ +#define SpiritPktStackSetCrcMode(xCrcMode) SpiritPktCommonSetCrcMode((PktCrcMode)xCrcMode) + + +/** + * @brief Returns the CRC mode for SPIRIT packets. + * @param None. + * @retval StackCrcMode Crc mode. + */ +#define SpiritPktStackGetCrcMode() (StackCrcMode)SpiritPktCommonGetCrcMode() + + +/** + * @brief Enables or Disables WHITENING for SPIRIT STack packets. + * @param xNewState new state for WHITENING mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackWhitening(xNewState) SpiritPktCommonWhitening(xNewState) + + +/** + * @brief Enables or Disables FEC for SPIRIT STack packets. + * @param xNewState new state for FEC mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackFec(xNewState) SpiritPktCommonFec(xNewState) + + +/** + * @brief Sets a specific SYNC word for SPIRIT STack packets. + * @param xSyncX SYNC word number to be set. + * This parameter can be any value of @ref StackSyncX. + * @param cSyncWord SYNC word. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktStackSetSyncxWord(xSyncX, cSyncWord) SpiritPktCommonSetSyncxWord((PktSyncX)xSyncX,cSyncWord) + + +/** + * @brief Returns a specific SYNC word for SPIRIT STack packets. + * @param xSyncX SYNC word number to be get. + * This parameter can be any value of @ref StackSyncX. + * @retval uint8_t Sync word x. + */ +#define SpiritPktStackGetSyncxWord(xSyncX) SpiritPktCommonGetSyncxWord(xSyncX) + + +/** + * @brief Sets multiple SYNC words for SPIRIT STack packets. + * @param lSyncWords SYNC words to be set with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4|. + * This parameter is a uint32_t. + * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb + * until the number of bytes in xSyncLength has been stored. + * This parameter is a @ref StackSyncLength. + * @retval None. + */ +#define SpiritPktStackSetSyncWords(lSyncWords, xSyncLength) SpiritPktCommonSetSyncWords(lSyncWords,(PktSyncLength)xSyncLength) + + +/** + * @brief Returns multiple SYNC words for SPIRIT packets. + * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb + * until the number of bytes in xSyncLength has been stored. + * This parameter is a pointer to @ref StackSyncLength. + * @retval uint32_t Sync words. The format of the read 32 bit word is 0x|SYNC1|SYNC2|SYNC3|SYNC4|. + */ +#define SpiritPktStackGetSyncWords(xSyncLength) SpiritPktCommonGetSyncWords((PktSyncLength)xSyncLength) + + +/** + * @brief Returns the SPIRIT variable length width (in number of bits). + * @param None. + * @retval uint8_t Variable length width in bits. + */ +#define SpiritPktStackGetVarLengthWidth() SpiritPktCommonGetVarLengthWidth() + + +/** + * @brief Sets the destination address for the Tx packet. + * @param cAddress destination address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktStackSetDestinationAddress(cAddress) SpiritPktCommonSetDestinationAddress(cAddress) + + +/** + * @brief Sets the Rx packet reference source address. The source address extracted from the received packet is masked + * with the source reference mask and then compared to the masked reference value. + * @param cAddress Reference source address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktStackSetSourceReferenceAddress(cAddress) SpiritPktCommonSetDestinationAddress(cAddress) + + +/** + * @brief Returns the Rx packet reference source address. The source address extracted from the received packet is masked + * with the source reference mask and then compared to the masked reference value. + * @param cAddress Reference source address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktStackGetSourceReferenceAddress() SpiritPktCommonGetTransmittedDestAddress() + + +/** + * @brief Returns the settled destination address. + * @param None. + * @retval uint8_t Transmitted destination address. + */ +#define SpiritPktStackGetTransmittedDestAddress() SpiritPktCommonGetTransmittedDestAddress() + + +/** + * @brief Sets the node address. When the filtering on my address is on, if the destination address extracted from the received packet is equal to the content of the + * my address, then the packet is accepted (this is the address of the node). + * @param cAddress Address of the present node. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktStackSetMyAddress(cAddress) SpiritPktCommonSetMyAddress(cAddress) + + +/** + * @brief Returns the address of the present node. + * @param None. + * @retval uint8_t My address (address of this node). + */ +#define SpiritPktStackGetMyAddress() SpiritPktCommonGetMyAddress() + + +/** + * @brief Sets the broadcast address. When the broadcast filtering is on, if the destination address extracted from the received packet is equal to the content of the + * BROADCAST_ADDR register, then the packet is accepted. + * @param cAddress Broadcast address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktStackSetBroadcastAddress(cAddress) SpiritPktCommonSetBroadcastAddress(cAddress) + + +/** + * @brief Returns the broadcast address. + * @param None. + * @retval uint8_t Broadcast address. + */ +#define SpiritPktStackGetBroadcastAddress() SpiritPktCommonGetBroadcastAddress() + + +/** + * @brief Sets the multicast address. When the multicast filtering is on, if the destination address extracted from the received packet is equal to the content of the + * MULTICAST_ADDR register, then the packet is accepted. + * @param cAddress Multicast address. + * This parameter is an uint8_t. + * @retval None. + */ +#define SpiritPktStackSetMulticastAddress(cAddress) SpiritPktCommonSetMulticastAddress(cAddress) + + +/** + * @brief Returns the multicast address. + * @param None. + * @retval uint8_t Multicast address. + */ +#define SpiritPktStackGetMulticastAddress() SpiritPktCommonGetMulticastAddress() + + +/** + * @brief Sets the control mask. The 1 bits of the CONTROL_MASK indicate the + * bits to be used in filtering. (All 0s no filtering) + * @param lMask Control mask. + * This parameter is an uint32_t. + * @retval None. + */ +#define SpiritPktStackSetCtrlMask(lMask) SpiritPktCommonSetCtrlMask(lMask) + + +/** + * @brief Returns the control mask. The 1 bits of the CONTROL_MASK indicate the + * bits to be used in filtering. (All 0s no filtering) + * @param None. + * @retval uint32_t Control mask. + */ +#define SpiritPktStackGetCtrlMask() SpiritPktCommonGetCtrlMask() + + +/** + * @brief Sets the control field reference. If the bits enabled by the + * CONTROL_MASK match the ones of the control fields extracted from the received packet + * then the packet is accepted. + * @param lReference Control reference. + * This parameter is an uint32_t. + * @retval None. + */ +#define SpiritPktStackSetCtrlReference(lReference) SpiritPktCommonSetCtrlReference(lReference) + + +/** + * @brief Returns the control field reference. + * @param None. + * @retval uint32_t Control reference. + */ +#define SpiritPktStackGetCtrlReference() SpiritPktCommonGetCtrlReference() + + +/** + * @brief Sets the TX control field. + * @param lField TX CONTROL FIELD. + * This parameter is an uint32_t. + * @retval None. + */ +#define SpiritPktStackSetTransmittedCtrlField(lField) SpiritPktCommonSetTransmittedCtrlField(lField) + + +/** + * @brief Returns the TX control field. + * @param None. + * @retval uint32_t Control field of the transmitted packet. + */ +#define SpiritPktStackGetTransmittedCtrlField() SpiritPktCommonGetTransmittedCtrlField() + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with TX_SOURCE_ADDRESS. + * @param xNewState new state for DEST_VS_SOURCE_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackFilterOnMyAddress(xNewState) SpiritPktCommonFilterOnMyAddress(xNewState) + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with MULTICAST_ADDRESS. + * @param xNewState new state for DEST_VS_MULTICAST_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackFilterOnMulticastAddress(xNewState) SpiritPktCommonFilterOnMulticastAddress(xNewState) + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with BROADCAST_ADDRESS. + * @param xNewState new state for DEST_VS_BROADCAST_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackFilterOnBroadcastAddress(xNewState) SpiritPktCommonFilterOnBroadcastAddress(xNewState) + + +/** + * @brief Returns the enable bit of the my address filtering. + * @param None. + * @retval SpiritFunctionalStateThis parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktStackGetFilterOnMyAddress() SpiritPktCommonGetFilterOnMyAddress(); + + +/** + * @brief Returns the enable bit of the multicast address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktStackGetFilterOnMulticastAddress() SpiritPktCommonGetFilterOnMulticastAddress(); + + +/** + * @brief Returns the enable bit of the broadcast address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktStackGetFilterOnBroadcastAddress() SpiritPktCommonGetFilterOnBroadcastAddress(); + + +/** + * @brief Returns the control field of the received packet. + * @param None. + * @retval uint32_t Received control field. + */ +#define SpiritPktStackGetReceivedCtrlField() SpiritPktCommonGetReceivedCtrlField() + + +/** + * @brief Returns the CRC field of the received packet. + * @param cCrcFieldVect array in which the CRC field has to be stored. + * This parameter is an uint8_t array of 3 elements. + * @retval None. + */ +#define SpiritPktStackGetReceivedCrcField(cCrcFieldVect) SpiritPktCommonGetReceivedCrcField(cCrcFieldVect) + +/** + * @brief Sets the AUTO ACKNOLEDGEMENT mechanism on the receiver. When the feature is enabled and + * a data packet has been correctly received, then an acknowledgement packet is sent back to the originator of the received + * packet. If the PIGGYBACKING bit is also set, payload data will be read from the FIFO; otherwise an empty packet is sent + * only containing the source and destination addresses and the sequence number of the packet being acknowledged. + * @param xAutoAck new state for autoack. + * This parameter can be: S_ENABLE or S_DISABLE. + * @param xPiggybacking new state for autoack. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackAutoAck(xAutoAck, xPiggybacking) SpiritPktCommonAutoAck(xAutoAck, xPiggybacking) + + +/** + * @brief Sets the AUTO ACKNOLEDGEMENT mechanism on the transmitter. On the transmitter side, the NACK_TX field can be used to require or not an acknowledgment for each individual packet: if + * NACK_TX is set to "1" then acknowledgment will not be required; if NACK_TX is set to "0" then acknowledgment will be + * required. + * @param xNewState new state for TX_AUTOACK. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackRequireAck(xNewState) SpiritPktCommonRequireAck(xNewState) + + +/** + * @brief Sets the TX sequence number to be used to start counting. + * @param cSeqNumberReload new value for Tx seq number reload. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +#define SpiritPktStackSetTransmittedSeqNumberReload(cSeqNumberReload) SpiritPktCommonSetTransmittedSeqNumberReload(cSeqNumberReload) + + +/** + * @brief Sets the max number of automatic retransmission. + * @param xNMaxReTx max number of retransmission. + * This parameter can be any value of @ref PktNMaxReTx. + * @retval None. + */ +#define SpiritPktStackSetNMaxReTx(xNMaxReTx) SpiritPktCommonSetNMaxReTx((PktNMaxReTx)xNMaxReTx) + + +/** + * @brief Returns the max number of automatic retransmission. + * @param None. + * @retval uint8_t Max number of retransmissions. + */ +#define SpiritPktStackGetNMaxReTx() SpiritPktCommonGetNMaxReTx() + + +/** + * @brief Returns the TX ACK request. + * @param None. + * @retval SpiritFunctionalState. + */ +#define SpiritPktStackGetGetTxAckRequest() SpiritPktCommonGetTxAckRequest() + +/** + * @brief Returns the destination address of the received packet. + * @param None. + * @retval uint8_t Destination address of the received packet. + */ +#define SpiritPktStackGetReceivedDestAddress() SpiritPktCommonGetReceivedDestAddress() + + +/** + * @brief Returns the source address of the received packet. + * @param None. + * @retval uint8_t Source address of the received packet. + */ +#define SpiritPktStackGetReceivedSourceAddress() SpiritPktCommonGetReceivedSourceAddress() + + +/** + * @brief Returns the sequence number of the received packet. + * @param None. + * @retval uint8_t Received Sequence number. + */ +#define SpiritPktStackGetReceivedSeqNumber() SpiritPktCommonGetReceivedSeqNumber() + + +/** + * @brief Returns the Nack bit of the received packet + * @param None. + * @retval uint8_t Value of the NAck bit. + */ +#define SpiritPktStackGetReceivedNackRx() SpiritPktCommonGetReceivedNackRx() + + +/** + * @brief Returns the sequence number of the transmitted packet. + * @param None. + * @retval uint8_t Sequence number of the transmitted packet. + */ +#define SpiritPktStackGetTransmittedSeqNumber() SpiritPktCommonGetTransmittedSeqNumber() + + +/** + * @brief Returns the number of retransmission done on the transmitted packet. + * @param None. + * @retval uint8_t Number of retransmissions done until now. + */ +#define SpiritPktStackGetNReTx() SpiritPktCommonGetNReTx() + + +/** + * @brief If enabled RX packet is accepted only if the masked control field matches the + * masked control field reference (CONTROL_MASK & CONTROL_FIELD_REF == CONTROL_MASK & RX_CONTROL_FIELD). + * @param xNewState new state for Control filtering enable bit. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + * @note This filtering control is enabled by default but the control mask is by default set to 0. + * As a matter of fact the user has to enable the control filtering bit after the packet initialization + * because the PktInit routine disables it. + */ +#define SpiritPktStackFilterOnControlField(xNewState) SpiritPktCommonFilterOnControlField(xNewState) + + +/** + * @brief Returns the enable bit of the control field filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +#define SpiritPktStackGetFilterOnControlField() SpiritPktCommonGetFilterOnControlField(); + + +/** + *@} + */ + + +/** + * @defgroup PktStack_Exported_Functions Pkt STack Exported Functions + * @{ + */ + +void SpiritPktStackInit(PktStackInit* pxPktStackInit); +void SpiritPktStackGetInfo(PktStackInit* pxPktStackInit); +void SpiritPktStackAddressesInit(PktStackAddressesInit* pxPktStackAddresses); +void SpiritPktStackGetAddressesInfo(PktStackAddressesInit* pxPktStackAddresses); +void SpiritPktStackLlpInit(PktStackLlpInit* pxPktStackLlpInit); +void SpiritPktStackLlpGetInfo(PktStackLlpInit* pxPktStackLlpInit); +void SpiritPktStackSetFormat(void); +void SpiritPktStackSetPayloadLength(uint16_t nPayloadLength); +uint16_t SpiritPktStackGetPayloadLength(void); +void SpiritPktStackSetVarLengthWidth(uint16_t nMaxPayloadLength, StackControlLength xControlLength); +void SpiritPktStackSetRxSourceMask(uint8_t cMask); +uint8_t SpiritPktStackGetRxSourceMask(void); +uint16_t SpiritPktStackGetReceivedPktLength(void); +void SpiritPktStackFilterOnSourceAddress(SpiritFunctionalState xNewState); +void SpiritPktStackSetAddressLength(void); + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Qi.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Qi.h new file mode 100644 index 000000000..d7055d01a --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Qi.h @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file SPIRIT_Qi.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT QI. + * @details + * + * This module can be used to configure and read some quality indicators + * used by Spirit. + * API to set thresholds and to read values in raw mode or in dBm are + * provided. + * + * Example: + * @code + * + * float rssiValuedBm; + * uint8_t pqiValue, sqiValue; + * + * SpiritQiPqiCheck(S_ENABLE); + * SpiritQiSqiCheck(S_ENABLE); + * + * ... + * + * rssiValueDbm = SpiritQiGetRssidBm(); + * pqiValue = SpiritQiGetPqi(); + * sqiValue = SpiritQiGetSqi(); + * + * ... + * + * @endcode + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_QI_H +#define __SPIRIT_QI_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Qi QI + * @brief Configuration and management of SPIRIT QI. + * @details See the file @ref SPIRIT_Qi.h for more details. + * @{ + */ + +/** + * @defgroup Qi_Exported_Types QI Exported Types + * @{ + */ + + +/** + * @brief PQI threshold value enumeration. + */ +typedef enum +{ + PQI_TH_0=0x00, + PQI_TH_1=0x04, + PQI_TH_2=0x08, + PQI_TH_3=0x0C, + PQI_TH_4=0x10, + PQI_TH_5=0x14, + PQI_TH_6=0x18, + PQI_TH_7=0x1C, + PQI_TH_8=0x20, + PQI_TH_9=0x24, + PQI_TH_10=0x28, + PQI_TH_11=0x2C, + PQI_TH_12=0x30, + PQI_TH_13=0x34, + PQI_TH_14=0x38, + PQI_TH_15=0x3C + +} PqiThreshold; + +#define IS_PQI_THR(VALUE) (VALUE==PQI_TH_0 ||\ + VALUE==PQI_TH_1 ||\ + VALUE==PQI_TH_2 ||\ + VALUE==PQI_TH_3 ||\ + VALUE==PQI_TH_4 ||\ + VALUE==PQI_TH_5 ||\ + VALUE==PQI_TH_6 ||\ + VALUE==PQI_TH_7 ||\ + VALUE==PQI_TH_8 ||\ + VALUE==PQI_TH_9 ||\ + VALUE==PQI_TH_10 ||\ + VALUE==PQI_TH_11 ||\ + VALUE==PQI_TH_12 ||\ + VALUE==PQI_TH_13 ||\ + VALUE==PQI_TH_14 ||\ + VALUE==PQI_TH_15) + +/** + * @brief SQI threshold value enumeration. + */ +typedef enum +{ + SQI_TH_0=0x00, + SQI_TH_1=0x40, + SQI_TH_2=0x80, + SQI_TH_3=0xC0 + +} SqiThreshold; + +#define IS_SQI_THR(VALUE) (VALUE==SQI_TH_0 ||\ + VALUE==SQI_TH_1 ||\ + VALUE==SQI_TH_2 ||\ + VALUE==SQI_TH_3) + + +/** + * @brief RSSI filter gain value enumeration. + */ +typedef enum +{ + RSSI_FG_0=0x00, + RSSI_FG_1=0x10, + RSSI_FG_2=0x20, + RSSI_FG_3=0x30, + RSSI_FG_4=0x40, + RSSI_FG_5=0x50, + RSSI_FG_6=0x60, + RSSI_FG_7=0x70, + RSSI_FG_8=0x80, + RSSI_FG_9=0x90, + RSSI_FG_10=0xA0, + RSSI_FG_11=0xB0, + RSSI_FG_12=0xC0, + RSSI_FG_13=0xD0, + RSSI_FG_14=0xE0, /*=-130 && VALUE<=-2) + +/** + *@} + */ + + +/** + * @defgroup Qi_Exported_Macros QI Exported Macros + * @{ + */ + +/** + * @brief Macro to obtain the RSSI value in dBm + * @param None. + * @retval RSSI in dBm. + * This parameter is a float. + */ +#define SpiritQiGetRssidBm() (-120.0+((float)(SpiritQiGetRssi()-20))/2) + +/** + *@} + */ + + +/** + * @defgroup Qi_Exported_Functions QI Exported Functions + * @{ + */ + +void SpiritQiPqiCheck(SpiritFunctionalState xNewState); +void SpiritQiSqiCheck(SpiritFunctionalState xNewState); +void SpiritQiSetPqiThreshold(PqiThreshold xPqiThr); +PqiThreshold SpiritQiGetPqiThreshold(void); +void SpiritQiSetSqiThreshold(SqiThreshold xSqiThr); +SqiThreshold SpiritQiGetSqiThreshold(void); +void SpiritQiSetRssiThreshold(uint8_t cRssiThr); +uint8_t SpiritQiGetRssiThreshold(void); +uint8_t SpiritQiComputeRssiThreshold(int cDbmValue); +void SpiritQiSetRssiThresholddBm(int nDbmValue); +uint8_t SpiritQiGetPqi(void); +uint8_t SpiritQiGetSqi(void); +uint8_t SpiritQiGetLqi(void); +SpiritFlagStatus SpiritQiGetCs(void); +uint8_t SpiritQiGetRssi(void); +void SpiritQiSetRssiFilterGain(RssiFilterGain xRssiFg); +RssiFilterGain SpiritQiGetRssiFilterGain(void); +void SpiritQiSetCsMode(CSMode xCsMode); +CSMode SpiritQiGetCsMode(void); +void SpiritQiCsTimeoutMask(SpiritFunctionalState xNewState); +void SpiritQiPqiTimeoutMask(SpiritFunctionalState xNewState); +void SpiritQiSqiTimeoutMask(SpiritFunctionalState xNewState); + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Radio.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Radio.h new file mode 100644 index 000000000..020829194 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Radio.h @@ -0,0 +1,636 @@ +/** + ****************************************************************************** + * @file SPIRIT_Radio.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief This file provides all the low level API to manage Analog and Digital + * radio part of SPIRIT. + * @details + * + * In order to configure the Radio main parameters, the user can + * fit SRadioInit structure the and call the SpiritRadioInit() + * function passing its pointer as an argument. + * + * Example: + * @code + * + * SRadioInit radioInit = { + * 0, // Xtal offset in ppm + * 433.4e6, // base frequency + * 20e3, // channel space + * 0, // channel number + * FSK, // modulation select + * 38400, // datarate + * 20e3, // frequency deviation + * 100.5e3 // channel filter bandwidth + * }; + * + * ... + * + * SpiritRadioInit(&radioInit); + * @endcode + * + * Another important parameter for the radio configuration is the + * transmission power. + * The user is allowed to configure it using the function SpiritRadioSetPALeveldBm() + * which sets the PA LEVEL specified by the first argument to the + * power expressed in dBm by the second parameter. + * + * Example: + * @code + * + * SpiritRadioSetPALeveldBm(0 , 10.0); + * + * @endcode + * + * + * @note The effective power that is set can be a little different from the + * passed argument in dBm because the function performs an approximation. + * + + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_RADIO_H +#define __SPIRIT_RADIO_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" +#include "SPIRIT_Config.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** @defgroup SPIRIT_Radio Radio + * @brief Configuration and management of SPIRIT RF Analog and Digital part. + * @details See the file @ref SPIRIT_Radio.h for more details. + * @{ + */ + + + +/** @defgroup Radio_Exported_Types Radio Exported Types + * @{ + */ + + +/** + * @brief SPIRIT XTAL frequency enumeration + */ +typedef enum +{ + XTAL_FLAG_24_MHz = 0x00, /*!< 24 MHz Xtal selected */ + XTAL_FLAG_26_MHz = 0x01 /*!< 26 MHz Xtal selected */ + +}XtalFlag; + + +#define IS_XTAL_FLAG(FLAG) (((FLAG) == XTAL_FLAG_24_MHz) || \ + ((FLAG) == XTAL_FLAG_26_MHz)) + +/** + * @brief SPIRIT Band enumeration + */ +typedef enum +{ + HIGH_BAND = 0x00, /*!< High_Band selected: from 779 MHz to 915 MHz */ + MIDDLE_BAND = 0x01, /*!< Middle Band selected: from 387 MHz to 470 MHz */ + LOW_BAND = 0x02, /*!< Low Band selected: from 300 MHz to 348 MHz */ + VERY_LOW_BAND = 0x03 /*!< Vary low Band selected: from 150 MHz to 174 MHz */ +}BandSelect; + + +#define IS_BAND_SELECTED(BAND) ((BAND == HIGH_BAND) || \ + (BAND == MIDDLE_BAND) || \ + (BAND == LOW_BAND) || \ + (BAND == VERY_LOW_BAND)) + +/** + * @brief SPIRIT Modulation enumeration + */ +typedef enum +{ + FSK = 0x00, /*!< 2-FSK modulation selected */ + GFSK_BT05 = 0x50, /*!< GFSK modulation selected with BT=0.5 */ + GFSK_BT1 = 0x10, /*!< GFSK modulation selected with BT=1 */ + ASK_OOK = 0x20, /*!< ASK or OOK modulation selected. ASK will use power ramping */ + MSK = 0x30 /*!< MSK modulation selected */ + +}ModulationSelect; + + +#define IS_MODULATION_SELECTED(MOD) (((MOD) == FSK) || \ + ((MOD) == GFSK_BT05) || \ + ((MOD) == GFSK_BT1) || \ + ((MOD) == ASK_OOK) || \ + ((MOD) == MSK)) + + +/** + * @brief SPIRIT PA additional load capacitors bank enumeration + */ +typedef enum +{ + LOAD_0_PF = PA_POWER0_CWC_0, /*!< No additional PA load capacitor */ + LOAD_1_2_PF = PA_POWER0_CWC_1_2P, /*!< 1.2pF additional PA load capacitor */ + LOAD_2_4_PF = PA_POWER0_CWC_2_4P, /*!< 2.4pF additional PA load capacitor */ + LOAD_3_6_PF = PA_POWER0_CWC_3_6P /*!< 3.6pF additional PA load capacitor */ + +}PALoadCapacitor; + +#define IS_PA_LOAD_CAP(CWC) (((CWC) == LOAD_0_PF) || \ + ((CWC) == LOAD_1_2_PF) || \ + ((CWC) == LOAD_2_4_PF) || \ + ((CWC) == LOAD_3_6_PF)) + + +/** + * @brief SPIRIT AFC Mode selection + */ +typedef enum +{ + AFC_SLICER_CORRECTION = AFC2_AFC_MODE_SLICER, /*!< AFC loop closed on slicer */ + AFC_2ND_IF_CORRECTION = AFC2_AFC_MODE_MIXER /*!< AFC loop closed on 2nd conversion stage */ + +}AFCMode; + +#define IS_AFC_MODE(MODE) ((MODE) == AFC_SLICER_CORRECTION || (MODE) == AFC_2ND_IF_CORRECTION) + + +/** + * @brief SPIRIT AGC Mode selection + */ +typedef enum +{ + AGC_LINEAR_MODE = AGCCTRL0_AGC_MODE_LINEAR, /*!< AGC works in linear mode */ + AGC_BINARY_MODE = AGCCTRL0_AGC_MODE_BINARY /*!< AGC works in binary mode */ + +}AGCMode; + +#define IS_AGC_MODE(MODE) ((MODE) == AGC_LINEAR_MODE || (MODE) == AGC_BINARY_MODE) + + +/** + * @brief SPIRIT Clock Recovery Mode selection + */ +typedef enum +{ + CLK_REC_PLL = FDEV0_CLOCK_REG_ALGO_SEL_PLL, /*!< PLL alogrithm for clock recovery */ + CLK_REC_DLL = FDEV0_CLOCK_REG_ALGO_SEL_DLL /*!< DLL alogrithm for clock recovery */ + +}ClkRecMode; + +#define IS_CLK_REC_MODE(MODE) ((MODE) == CLK_REC_PLL || (MODE) == CLK_REC_DLL) + + +/** + * @brief SPIRIT Postfilter length + */ +typedef enum +{ + PSTFLT_LENGTH_8 = 0x00, /*!< Postfilter length is 8 symbols */ + PSTFLT_LENGTH_16 = 0x10 /*!< Postfilter length is 16 symbols */ + +}PstFltLength; + +#define IS_PST_FLT_LENGTH(LENGTH) ((LENGTH) == PSTFLT_LENGTH_8 || (LENGTH) == PSTFLT_LENGTH_16) + + +/** + * @brief SPIRIT OOK Peak Decay + */ +typedef enum +{ + FAST_DECAY = 0x00, /*!< Peak decay control for OOK: fast decay */ + MEDIUM_FAST_DECAY = 0x01, /*!< Peak decay control for OOK: medium_fast decay */ + MEDIUM_SLOW_DECAY = 0x02, /*!< Peak decay control for OOK: medium_fast decay */ + SLOW_DECAY = 0x03 /*!< Peak decay control for OOK: slow decay */ + +}OokPeakDecay; + +#define IS_OOK_PEAK_DECAY(DECAY) (((DECAY) == FAST_DECAY) ||\ + ((DECAY) == MEDIUM_FAST_DECAY) ||\ + ((DECAY) == MEDIUM_SLOW_DECAY) ||\ + ((DECAY) == SLOW_DECAY)) + + +/** + * @brief SPIRIT Radio Init structure definition + */ +typedef struct +{ + int16_t nXtalOffsetPpm; /*!< Specifies the offset frequency (in ppm) + to compensate crystal inaccuracy expressed + as signed value.*/ + + uint32_t lFrequencyBase; /*!< Specifies the base carrier frequency (in Hz), + i.e. the carrier frequency of channel #0. + This parameter can be in one of the following ranges: + High_Band: from 779 MHz to 915 MHz + Middle Band: from 387 MHz to 470 MHz + Low Band: from 300 MHz to 348 MHz */ + uint32_t nChannelSpace; /*!< Specifies the channel spacing expressed in Hz. + The channel spacing is expressed as: + NxFREQUENCY_STEPS, where FREQUENCY STEPS + is F_Xo/2^15. + This parameter can be in the range: [0, F_Xo/2^15*255] Hz */ + uint8_t cChannelNumber; /*!< Specifies the channel number. This value + is multiplied by the channel spacing and + added to synthesizer base frequency to + generate the actual RF carrier frequency */ + ModulationSelect xModulationSelect; /*!< Specifies the modulation. This + parameter can be any value of + @ref ModulationSelect */ + uint32_t lDatarate; /*!< Specifies the datarate expressed in bps. + This parameter can be in the range between + 100 bps and 500 kbps */ + uint32_t lFreqDev; /*!< Specifies the frequency deviation expressed in Hz. + This parameter can be in the range: [F_Xo*8/2^18, F_Xo*7680/2^18] Hz */ + uint32_t lBandwidth; /*!< Specifies the channel filter bandwidth + expressed in Hz. This parameter can be + in the range between 1100 and 800100 Hz */ + +}SRadioInit; + +/** + * @} + */ + + + +/** @defgroup Radio_Exported_Constants Radio Exported Constants + * @{ + */ + +/** @defgroup Radio_Band + * @{ + */ + +#define FBASE_DIVIDER 262144 /*!< 2^18 factor dividing fxo in fbase formula */ + +#define HIGH_BAND_FACTOR 6 /*!< Band select factor for high band. Factor B in the equation 2 */ +#define MIDDLE_BAND_FACTOR 12 /*!< Band select factor for middle band. Factor B in the equation 2 */ +#define LOW_BAND_FACTOR 16 /*!< Band select factor for low band. Factor B in the equation 2 */ +#define VERY_LOW_BAND_FACTOR 32 /*!< Band select factor for very low band. Factor B in the equation 2 */ + +#define HIGH_BAND_LOWER_LIMIT 778000000 /*!< Lower limit of the high band: 779 MHz */ +#define HIGH_BAND_UPPER_LIMIT 957100000 /*!< Upper limit of the high band: 956 MHz */ +#define MIDDLE_BAND_LOWER_LIMIT 386000000 /*!< Lower limit of the middle band: 387 MHz */ +#define MIDDLE_BAND_UPPER_LIMIT 471100000 /*!< Upper limit of the middle band: 470 MHz */ +#define LOW_BAND_LOWER_LIMIT 299000000 /*!< Lower limit of the low band: 300 MHz */ +#define LOW_BAND_UPPER_LIMIT 349100000 /*!< Upper limit of the low band: 348 MHz */ +#define VERY_LOW_BAND_LOWER_LIMIT 149000000 /*!< Lower limit of the very low band: 150 MHz */ +#define VERY_LOW_BAND_UPPER_LIMIT 175100000 /*!< Upper limit of the very low band: 174 MHz */ + +#define IS_FREQUENCY_BAND_HIGH(FREQUENCY) ((FREQUENCY)>=HIGH_BAND_LOWER_LIMIT && \ + (FREQUENCY)<=HIGH_BAND_UPPER_LIMIT) + +#define IS_FREQUENCY_BAND_MIDDLE(FREQUENCY) ((FREQUENCY)>=MIDDLE_BAND_LOWER_LIMIT && \ + (FREQUENCY)<=MIDDLE_BAND_UPPER_LIMIT) + +#define IS_FREQUENCY_BAND_LOW(FREQUENCY) ((FREQUENCY)>=LOW_BAND_LOWER_LIMIT && \ + (FREQUENCY)<=LOW_BAND_UPPER_LIMIT) + +#define IS_FREQUENCY_BAND_VERY_LOW(FREQUENCY) ((FREQUENCY)>=VERY_LOW_BAND_LOWER_LIMIT && \ + (FREQUENCY)<=VERY_LOW_BAND_UPPER_LIMIT) + +#define IS_FREQUENCY_BAND(FREQUENCY) (IS_FREQUENCY_BAND_HIGH(FREQUENCY)|| \ + IS_FREQUENCY_BAND_MIDDLE(FREQUENCY)|| \ + IS_FREQUENCY_BAND_LOW(FREQUENCY)|| \ + IS_FREQUENCY_BAND_VERY_LOW(FREQUENCY)) + +/** + * @} + */ + + +/** @defgroup Radio_IF_Offset Radio IF Offset + * @{ + */ +#define IF_OFFSET_ANA(F_Xo) (lroundf(480140.0/(F_Xo)*12288-64.0)) /*!< It represents the IF_OFFSET_ANA in order + to have an intermediate frequency of 480 kHz */ +/** + * @} + */ + + +/** @defgroup Radio_FC_Offset Radio FC Offset + * @{ + */ +#define F_OFFSET_DIVIDER 262144 /*!< 2^18 factor dividing fxo in foffset formula */ +#define PPM_FACTOR 1000000 /*!< 10^6 factor to use with Xtal_offset_ppm */ + + +#define F_OFFSET_LOWER_LIMIT(F_Xo) ((-(int32_t)F_Xo)/F_OFFSET_DIVIDER*2048) +#define F_OFFSET_UPPER_LIMIT(F_Xo) ((int32_t)(F_Xo/F_OFFSET_DIVIDER*2047)) + +#define IS_FREQUENCY_OFFSET(OFFSET, F_Xo) (OFFSET>=F_OFFSET_LOWER_LIMIT(F_Xo) && OFFSET<=F_OFFSET_UPPER_LIMIT(F_Xo)) + + +/** + * @} + */ + + +/** @defgroup Radio_Channel_Space Radio Channel Space + * @{ + */ + + +#define CHSPACE_DIVIDER 32768 /*!< 2^15 factor dividing fxo in channel space formula */ + +#define IS_CHANNEL_SPACE(CHANNELSPACE, F_Xo) (CHANNELSPACE<=(F_Xo/32768*255)) + + + + + +/** + * @} + */ + + +/** @defgroup Radio_Datarate Radio Datarate + * @{ + */ +#define MINIMUM_DATARATE 100 /*!< Minimum datarate supported by SPIRIT1 100 bps */ +#define MAXIMUM_DATARATE 510000 /*!< Maximum datarate supported by SPIRIT1 500 kbps */ + +#define IS_DATARATE(DATARATE) (DATARATE>=MINIMUM_DATARATE && DATARATE<=MAXIMUM_DATARATE) + +/** + * @} + */ + + +/** @defgroup Radio_Frequency_Deviation Radio Frequency Deviation + * @{ + */ +#define F_DEV_MANTISSA_UPPER_LIMIT 7 /*!< Maximum value for the mantissa in frequency deviation formula */ +#define F_DEV_EXPONENT_UPPER_LIMIT 9 /*!< Maximum value for the exponent in frequency deviation formula */ + +#define F_DEV_LOWER_LIMIT(F_Xo) (F_Xo>>16) +#define F_DEV_UPPER_LIMIT(F_Xo) ((F_Xo*15)>>10) + +#define IS_F_DEV(FDEV,F_Xo) (FDEV>=F_DEV_LOWER_LIMIT(F_Xo) && FDEV<=F_DEV_UPPER_LIMIT(F_Xo)) + + +/** + * @} + */ + + +/** @defgroup Radio_Channel_Bandwidth Radio Channel Bandwidth + * @{ + */ +#define CH_BW_LOWER_LIMIT(F_Xo) 1100*(F_Xo/1000000)/26 /*!< Minimum value of the channel filter bandwidth */ +#define CH_BW_UPPER_LIMIT(F_Xo) 800100*(F_Xo/1000000)/26 /*!< Maximum value of the channel filter bandwidth */ + +#define IS_CH_BW(BW,F_Xo) ((BW)>=CH_BW_LOWER_LIMIT(F_Xo) && (BW)<=CH_BW_UPPER_LIMIT(F_Xo)) + +/** + * @} + */ + + +/** @defgroup Radio_Power_Amplifier Radio Power Amplifier + * @{ + */ + +#define IS_PA_MAX_INDEX(INDEX) ((INDEX)<=7) +#define IS_PAPOWER_DBM(PATABLE) ((PATABLE)>= (-31) && (PATABLE)<=(12)) +#define IS_PAPOWER(PATABLE) ((PATABLE)<=90) +#define IS_PA_STEP_WIDTH(WIDTH) ((WIDTH)>=1 && (WIDTH)<=4) + +/** + * @} + */ + + +/** @defgroup Radio_Automatic_Frequency_Correction Radio Automatic Frequency Correction + * @{ + */ + +#define IS_AFC_FAST_GAIN(GAIN) ((GAIN)<=15) +#define IS_AFC_SLOW_GAIN(GAIN) ((GAIN)<=15) +#define IS_AFC_PD_LEAKAGE(LEAKAGE) ((LEAKAGE)<=31) + +/** + * @} + */ + +/** @defgroup Radio_Automatic_Gain_Control Radio Automatic Gain Control + * @{ + */ + +#define AGC_MEASURE_TIME_UPPER_LIMIT_US(F_Xo) (393216.0/F_Xo) + +#define IS_AGC_MEASURE_TIME_US(TIME, F_Xo) (TIME<=AGC_MEASURE_TIME_UPPER_LIMIT_US(F_Xo)) + +#define IS_AGC_MEASURE_TIME(TIME) (TIME<=15) + +#define AGC_HOLD_TIME_UPPER_LIMIT_US(F_Xo) (756.0/F_Xo) + +#define IS_AGC_HOLD_TIME_US(TIME,F_Xo) (TIME<=AGC_HOLD_TIME_UPPER_LIMIT_US(F_Xo)) + + +#define IS_AGC_HOLD_TIME(TIME) (TIME<=63) + +#define IS_AGC_THRESHOLD(THRESHOLD) (THRESHOLD<=15) + +/** + * @} + */ + + +/** @defgroup Radio_Clock_Recovery Radio Clock Recovery + * @{ + */ + +#define IS_CLK_REC_P_GAIN(GAIN) ((GAIN)<=7) +#define IS_CLK_REC_I_GAIN(GAIN) ((GAIN)<=15) + +/** + * @} + */ + +/** + * @} + */ + + + +/** @defgroup Radio_Exported_Macros Radio Exported Macros + * @{ + */ + + +/** + * @} + */ + +/** @defgroup Radio_Exported_Functions Radio Exported Functions + * @{ + */ + +uint8_t SpiritRadioInit(SRadioInit* pxSRadioInitStruct); +void SpiritRadioGetInfo(SRadioInit* pxSRadioInitStruct); +void SpiritRadioSetXtalFlag(XtalFlag xXtal); +XtalFlag SpiritRadioGetXtalFlag(void); +uint8_t SpiritRadioSearchWCP(uint32_t lFc); +void SpiritRadioSetSynthWord(uint32_t lSynthWord); +uint32_t SpiritRadioGetSynthWord(void); +void SpiritRadioSetBand(BandSelect xBand); +BandSelect SpiritRadioGetBand(void); +void SpiritRadioSetChannel(uint8_t cChannel); +uint8_t SpiritRadioGetChannel(void); +void SpiritRadioSetChannelSpace(uint32_t lChannelSpace); +uint32_t SpiritRadioGetChannelSpace(void); +void SpiritRadioSetFrequencyOffsetPpm(int16_t nXtalPpm); +void SpiritRadioSetFrequencyOffset(int32_t lFOffset); +int32_t SpiritRadioGetFrequencyOffset(void); +void SpiritRadioVcoCalibrationWAFB(SpiritFunctionalState xNewstate); +uint8_t SpiritRadioSetFrequencyBase(uint32_t lFBase); +uint32_t SpiritRadioGetFrequencyBase(void); +uint32_t SpiritRadioGetCenterFrequency(void); +void SpiritRadioSearchDatarateME(uint32_t lDatarate, uint8_t* pcM, uint8_t* pcE); +void SpiritRadioSearchFreqDevME(uint32_t lFDev, uint8_t* pcM, uint8_t* pcE); +void SpiritRadioSearchChannelBwME(uint32_t lBandwidth, uint8_t* pcM, uint8_t* pcE); +void SpiritRadioSetDatarate(uint32_t lDatarate); +uint32_t SpiritRadioGetDatarate(void); +void SpiritRadioSetFrequencyDev(uint32_t lFDev); +uint32_t SpiritRadioGetFrequencyDev(void); +void SpiritRadioSetChannelBW(uint32_t lBandwidth); +uint32_t SpiritRadioGetChannelBW(void); +void SpiritRadioSetModulation(ModulationSelect xModulation); +ModulationSelect SpiritRadioGetModulation(void); +void SpiritRadioCWTransmitMode(SpiritFunctionalState xNewState); +void SpiritRadioSetOokPeakDecay(OokPeakDecay xOokDecay); +OokPeakDecay SpiritRadioGetOokPeakDecay(void); +uint8_t SpiritRadioGetdBm2Reg(uint32_t lFBase, float fPowerdBm); +float SpiritRadioGetReg2dBm(uint32_t lFBase, uint8_t cPowerReg); +void SpiritRadioSetPATabledBm(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, float* pfPAtabledBm); +void SpiritRadioGetPATabledBm(uint8_t* pcPALevelMaxIndex, float* pfPAtabledBm); +void SpiritRadioSetPATable(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, uint8_t* pcPAtable); +void SpiritRadioGetPATable(uint8_t* pcPALevelMaxIndex, uint8_t* pcPAtable); +void SpiritRadioSetPALeveldBm(uint8_t cIndex, float fPowerdBm); +float SpiritRadioGetPALeveldBm(uint8_t cIndex); +void SpiritRadioSetPALevel(uint8_t cIndex, uint8_t cPower); +uint8_t SpiritRadioGetPALevel(uint8_t cIndex); +void SpiritRadioSetPACwc(PALoadCapacitor xCLoad); +PALoadCapacitor SpiritRadioGetPACwc(void); +void SpiritRadioSetPALevelMaxIndex(uint8_t cIndex); +uint8_t SpiritRadioGetPALevelMaxIndex(void); +void SpiritRadioSetPAStepWidth(uint8_t cWidth); +uint8_t SpiritRadioGetPAStepWidth(void); +void SpiritRadioPARamping(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritRadioGetPARamping(void); +void SpiritRadioAFC(SpiritFunctionalState xNewState); +void SpiritRadioAFCFreezeOnSync(SpiritFunctionalState xNewState); +void SpiritRadioSetAFCMode(AFCMode xMode); +AFCMode SpiritRadioGetAFCMode(void); +void SpiritRadioSetAFCPDLeakage(uint8_t cLeakage); +uint8_t SpiritRadioGetAFCPDLeakage(void); +void SpiritRadioSetAFCFastPeriod(uint8_t cLength); +uint8_t SpiritRadioGetAFCFastPeriod(void); +void SpiritRadioSetAFCFastGain(uint8_t cGain); +uint8_t SpiritRadioGetAFCFastGain(void); +void SpiritRadioSetAFCSlowGain(uint8_t cGain); +uint8_t SpiritRadioGetAFCSlowGain(void); +int8_t SpiritRadioGetAFCCorrectionReg(void); +int32_t SpiritRadioGetAFCCorrectionHz(void); +void SpiritRadioAGC(SpiritFunctionalState xNewState); +void SpiritRadioSetAGCMode(AGCMode xMode); +AGCMode SpiritRadioGetAGCMode(void); +void SpiritRadioAGCFreezeOnSteady(SpiritFunctionalState xNewState); +void SpiritRadioAGCFreezeOnSync(SpiritFunctionalState xNewState); +void SpiritRadioAGCStartMaxAttenuation(SpiritFunctionalState xNewState); +void SpiritRadioSetAGCMeasureTimeUs(uint16_t nTime); +uint16_t SpiritRadioGetAGCMeasureTimeUs(void); +void SpiritRadioSetAGCMeasureTime(uint8_t cTime); +uint8_t SpiritRadioGetAGCMeasureTime(void); +void SpiritRadioSetAGCHoldTimeUs(uint8_t cTime); +uint8_t SpiritRadioGetAGCHoldTimeUs(void); +void SpiritRadioSetAGCHoldTime(uint8_t cTime); +uint8_t SpiritRadioGetAGCHoldTime(void); +void SpiritRadioSetAGCHighThreshold(uint8_t cHighThreshold); +uint8_t SpiritRadioGetAGCHighThreshold(void); +void SpiritRadioSetAGCLowThreshold(uint8_t cLowThreshold); +uint8_t SpiritRadioGetAGCLowThreshold(void); +void SpiritRadioSetClkRecMode(ClkRecMode xMode); +ClkRecMode SpiritRadioGetClkRecMode(void); +void SpiritRadioSetClkRecPGain(uint8_t cPGain); +uint8_t SpiritRadioGetClkRecPGain(void); +void SpiritRadioSetClkRecIGain(uint8_t cIGain); +uint8_t SpiritRadioGetClkRecIGain(void); +void SpiritRadioSetClkRecPstFltLength(PstFltLength xLength); +PstFltLength SpiritRadioGetClkRecPstFltLength(void); +void SpiritRadioCsBlanking(SpiritFunctionalState xNewState); +void SpiritRadioPersistenRx(SpiritFunctionalState xNewState); +uint32_t SpiritRadioGetXtalFrequency(void); +void SpiritRadioSetXtalFrequency(uint32_t lXtalFrequency); +void SpiritRadioSetRefDiv(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritRadioGetRefDiv(void); +void SpiritRadioSetDigDiv(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritRadioGetDigDiv(void); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Regs.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Regs.h new file mode 100644 index 000000000..af742adca --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Regs.h @@ -0,0 +1,3244 @@ +/** + ****************************************************************************** + * @file SPIRIT_Regs.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief This file contains all the SPIRIT registers address and masks. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT1_REGS_H +#define __SPIRIT1_REGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @addtogroup SPIRIT_Registers SPIRIT Registers + * @brief Header file containing all the SPIRIT registers address and masks. + * @details See the file @ref SPIRIT_Regs.h for more details. + * @{ + */ + +/** @defgroup General_Configuration_Registers + * @{ + */ + +/** @defgroup ANA_FUNC_CONF_1_Register + * @{ + */ + +/** + * \brief ANA_FUNC_CONF register 1 + * \code + * Read Write + * Default value: 0x0C + * 7:5 NUM_EN_PIPES: Number of enabled pipes (starting from Data Pipe 0). + * 4:2 GM_CONF[2:0]: Sets the driver gm of the XO at start-up: + * GM_CONF2 | GM_CONF1 | GM_CONF0 | GM [mS] + * ------------------------------------------ + * 0 | 0 | 0 | 13.2 + * 0 | 0 | 1 | 18.2 + * 0 | 1 | 0 | 21.5 + * 0 | 1 | 1 | 25.6 + * 1 | 0 | 0 | 28.8 + * 1 | 0 | 1 | 33.9 + * 1 | 1 | 0 | 38.5 + * 1 | 1 | 1 | 43.0 + * 1:0 SET_BLD_LVL[1:0]: Sets the Battery Level Detector threshold: + * SET_BLD_LVL1 | SET_BLD_LVL0 | Threshold [V] + * ------------------------------------------ + * 0 | 0 | 2.7 + * 0 | 1 | 2.5 + * 1 | 0 | 2.3 + * 1 | 1 | 2.1 + * \endcode + */ + +#define ANA_FUNC_CONF1_BASE ((uint8_t)0x00) /*!< ANA_FUNC_CONF1 Address (R/W) */ + +#define ANA_FUNC_CONF1_NUM_PIPES_MASK ((uint8_t)0xE0) /*!< Mask for number of enabled pipes*/ + +#define ANA_FUNC_CONF1_GMCONF_MASK ((uint8_t)0x1C) /*!< Mask of the GmConf field of ANA_FUNC_CONF1 register (R/W) */ + +#define GM_13_2 ((uint8_t)0x00) /*!< Transconducatance Gm at start-up 13.2 mS */ +#define GM_18_2 ((uint8_t)0x04) /*!< Transconducatance Gm at start-up 18.2 mS */ +#define GM_21_5 ((uint8_t)0x08) /*!< Transconducatance Gm at start-up 21.5 mS */ +#define GM_25_6 ((uint8_t)0x0C) /*!< Transconducatance Gm at start-up 25.6 mS */ +#define GM_28_8 ((uint8_t)0x10) /*!< Transconducatance Gm at start-up 28.8 mS */ +#define GM_33_9 ((uint8_t)0x14) /*!< Transconducatance Gm at start-up 33.9 mS */ +#define GM_38_5 ((uint8_t)0x18) /*!< Transconducatance Gm at start-up 38.5 mS */ +#define GM_43_0 ((uint8_t)0x1C) /*!< Transconducatance Gm at start-up 43.0 mS */ + +#define ANA_FUNC_CONF1_SET_BLD_LVL_MASK ((uint8_t)0x03) /*!< Mask of the SET_BLD_LV field of ANA_FUNC_CONF1 register (R/W) */ + +#define BLD_LVL_2_7 ((uint8_t)0x00) /*!< Sets the Battery Level Detector threshold to 2.7V */ +#define BLD_LVL_2_5 ((uint8_t)0x01) /*!< Sets the Battery Level Detector threshold to 2.5V */ +#define BLD_LVL_2_3 ((uint8_t)0x02) /*!< Sets the Battery Level Detector threshold to 2.3V */ +#define BLD_LVL_2_1 ((uint8_t)0x03) /*!< Sets the Battery Level Detector threshold to 2.1V */ + +/** + * @} + */ + + +/** @defgroup ANA_FUNC_CONF_0_Register + * @{ + */ + +/** + * \brief ANA_FUNC_CONF register 0 + * \code + * Read Write + * Default value: 0xC0 + * 7 Reserved. + * 6 24_26_MHz_SELECT: 1 - 26 MHz configuration + * 0 - 24 MHz configuration + * 5 AES_ON: 1 - AES engine enabled + * 0 - AES engine disabled + * 4 EXT_REF: 1 - Reference signal from XIN pin + * 0 - Reference signal from XO circuit + * 3 HIGH_POWER_MODE: 1 - SET_SMPS_LEVEL word will be set to the value to + * PM_TEST register in RX state, while in TX state it + * will be fixed to 111 (which programs the SMPS output + * at max value 1.8V) + * 0 - SET_SMPS_LEVEL word will hold the value written in the + * PM_TEST register both in RX and TX state + * 2 BROWN_OUT: 1 - Brown_Out Detection enabled + * 0 - Brown_Out Detection disabled + * 1 BATTERY_LEVEL: 1 - Battery level detector enabled + * 0 - Battery level detector disabled + * 0 TS: 1 - Enable the "Temperature Sensor" function + * 0 - Disable the "Temperature Sensor" function + * \endcode + */ + + +#define ANA_FUNC_CONF0_BASE ((uint8_t)0x01) /*!< ANA_FUNC_CONF0 Address (R/W) */ + +#define SELECT_24_26_MHZ_MASK ((uint8_t)0x40) /*!< Configure the RCO if using 26 MHz or 24 MHz master clock/reference signal */ +#define AES_MASK ((uint8_t)0x20) /*!< AES engine on/off */ +#define EXT_REF_MASK ((uint8_t)0x10) /*!< Reference signal from XIN pin (oscillator external) or from XO circuit (oscillator internal)*/ +#define HIGH_POWER_MODE_MASK ((uint8_t)0x08) /*!< SET_SMPS_LEVEL word will be set to the value to PM_TEST register + in RX state, while in TX state it will be fixed to 111 + (which programs the SMPS output at max value, 1.8V) */ +#define BROWN_OUT_MASK ((uint8_t)0x04) /*!< Accurate Brown-Out detection on/off */ +#define BATTERY_LEVEL_MASK ((uint8_t)0x02) /*!< Battery level detector circuit on/off */ +#define TEMPERATURE_SENSOR_MASK ((uint8_t)0x01) /*!< The Temperature Sensor (available on GPIO0) on/off */ + +/** + * @} + */ + +/** @defgroup ANT_SELECT_CONF_Register + * @{ + */ + +/** + * \brief ANT_SELECT_CONF register + * \code + * Read Write + * Default value: 0x05 + * + * 7:5 Reserved. + * + * 4 CS_BLANKING: Blank received data if signal is below the CS threshold + * + * 3 AS_ENABLE: Enable antenna switching + * 1 - Enable + * 0 - Disable + * + * 2:0 AS_MEAS_TIME[2:0]: Measurement time according to the formula Tmeas = 24*2^(EchFlt)*2^AS_MEAS_TIME/fxo + * \endcode + */ +#define ANT_SELECT_CONF_BASE ((uint8_t)0x27) /*!< Antenna diversity (works only in static carrier sense mode) */ +#define ANT_SELECT_CS_BLANKING_MASK ((uint8_t)0x10) /*!< CS data blanking on/off */ +#define ANT_SELECT_CONF_AS_MASK ((uint8_t)0x08) /*!< Antenna diversity on/off */ + +/** + * @} + */ + +/** @defgroup DEVICE_INFO1_Register + * @{ + */ + +/** + * \brief DEVICE_INFO1[7:0] registers + * \code + * Default value: 0x01 + * Read + * + * 7:0 PARTNUM[7:0]: Device part number + * \endcode + */ +#define DEVICE_INFO1_PARTNUM ((uint8_t)(0xF0)) /*!< Device part number [7:0] */ + +/** + * @} + */ + +/** @defgroup DEVICE_INFO0_Register + * @{ + */ + +/** + * \brief DEVICE_INFO0[7:0] registers + * \code + * Read + * + * 7:0 VERSION[7:0]: Device version number + * \endcode + */ +#define DEVICE_INFO0_VERSION ((uint8_t)(0xF1)) /*!< Device version [7:0]; (0x55 in CUT1.0) */ + +/** + * @} + */ + + +/** + * @} + */ + + +/** @defgroup GPIO_Registers + * @{ + */ + +/** @defgroup GPIOx_CONF_Registers + * @{ + */ + +/** + * \brief GPIOx registers + * \code + * Read Write + * Default value: 0x03 + * 7:3 GPIO_SELECT[4:0]: Specify the I/O signal. + * GPIO_SELECT[4:0] | I/O | Signal + * ------------------------------------------------ + * 0 | Output | nIRQ + * 0 | Input | TX command + * 1 | Output | POR inverted + * 1 | Input | RX command + * 2 | Output | Wake-Up timer expiration + * 2 | Input | TX data for direct modulation + * 3 | Output | Low Battery Detection + * 3 | Input | Wake-up from external input + * 4 | Output | TX clock output + * 5 | Output | TX state + * 6 | Output | TX FIFO Almost Empty Flag + * 7 | Output | TX FIFO ALmost Full Flag + * 8 | Output | RX data output + * 9 | Output | RX clock output + * 10 | Output | RX state + * 11 | Output | RX FIFO Almost Full Flag + * 12 | Output | RX FIFO Almost Empty Flag + * 13 | Output | Antenna switch + * 14 | Output | Valid preamble detected + * 15 | Output | Sync word detected + * 16 | Output | RSSI above threshold + * 17 | Output | MCU clock + * 18 | Output | TX or RX mode indicator + * 19 | Output | VDD + * 20 | Output | GND + * 21 | Output | External SMPS enable signal + * 22-31 | Not Used | Not Used + * 2 Reserved + * 1:0 GpioMode[1:0]: Specify the mode: + * GPIO_MODE1 | GPIO_MODE0 | MODE + * ------------------------------------------------------------ + * 0 | 0 | Analog (valid only for GPIO_0) + * 0 | 1 | Digital Input + * 1 | 0 | Digital Output Low Power + * 1 | 1 | Digital Output High Power + * + * Note: The Analog mode is used only for temperature sensor indication. This is available only + * on GPIO_0 by setting the TS bit in the ANA_FUNC_CONF_0_Register. + * \endcode + */ + + +#define GPIO3_CONF_BASE ((uint8_t)0x02) /*!< GPIO_3 register address */ +#define GPIO2_CONF_BASE ((uint8_t)0x03) /*!< GPIO_3 register address */ +#define GPIO1_CONF_BASE ((uint8_t)0x04) /*!< GPIO_3 register address */ +#define GPIO0_CONF_BASE ((uint8_t)0x05) /*!< GPIO_3 register address */ + +#define CONF_GPIO_IN_TX_Command ((uint8_t)0x00) /*!< TX command direct from PIN (rising edge, width min=50ns) */ +#define CONF_GPIO_IN_RX_Command ((uint8_t)0x08) /*!< RX command direct from PIN (rising edge, width min=50ns)*/ +#define CONF_GPIO_IN_TX_Data ((uint8_t)0x10) /*!< TX data input for direct modulation */ +#define CONF_GPIO_IN_WKUP_Ext ((uint8_t)0x18) /*!< Wake up from external input */ + +#define CONF_GPIO_OUT_nIRQ ((uint8_t)0x00) /*!< nIRQ (Interrupt Request, active low) , default configuration after POR */ +#define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /*!< POR inverted (active low) */ +#define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /*!< Wake-Up Timer expiration: ‘1’ when WUT has expired */ +#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /*!< Low battery detection: ‘1’ when battery is below threshold setting */ +#define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /*!< TX data internal clock output (TX data are sampled on the rising edge of it) */ +#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /*!< TX state indication: ‘1’ when Spirit1 is transiting in the TX state */ +#define CONF_GPIO_OUT_TX_FIFO_Almost_Empty ((uint8_t)0x30) /*!< TX FIFO Almost Empty Flag */ +#define CONF_GPIO_OUT_TX_FIFO_Amost_Full ((uint8_t)0x38) /*!< TX FIFO Almost Full Flag */ +#define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /*!< RX data output */ +#define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /*!< RX clock output (recovered from received data) */ +#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /*!< RX state indication: ‘1’ when Spirit1 is transiting in the RX state */ +#define CONF_GPIO_OUT_RX_FIFO_Almost_Full ((uint8_t)0x58) /*!< RX FIFO Almost Full Flag */ +#define CONF_GPIO_OUT_RX_FIFO_Almost_Empty ((uint8_t)0x60) /*!< RX FIFO Almost Empty Flag */ +#define CONF_GPIO_OUT_Antenna_Switch ((uint8_t)0x68) /*!< Antenna switch used for antenna diversity */ +#define CONF_GPIO_OUT_Valid_Preamble ((uint8_t)0x70) /*!< Valid Preamble Detected Flag */ +#define CONF_GPIO_OUT_Sync_Detected ((uint8_t)0x78) /*!< Sync WordSync Word Detected Flag */ +#define CONF_GPIO_OUT_RSSI_Threshold ((uint8_t)0x80) /*!< CCA Assessment Flag */ +#define CONF_GPIO_OUT_MCU_Clock ((uint8_t)0x88) /*!< MCU Clock */ +#define CONF_GPIO_OUT_TX_RX_Mode ((uint8_t)0x90) /*!< TX or RX mode indicator (to enable an external range extender) */ +#define CONF_GPIO_OUT_VDD ((uint8_t)0x98) /*!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) */ +#define CONF_GPIO_OUT_GND ((uint8_t)0xA0) /*!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) */ +#define CONF_GPIO_OUT_SMPS_Ext ((uint8_t)0xA8) /*!< External SMPS enable signal (active high) */ + +#define CONF_GPIO_MODE_ANALOG ((uint8_t)0x00) /*!< Analog test BUS on GPIO; used only in test mode (except for temperature sensor) */ +#define CONF_GPIO_MODE_DIG_IN ((uint8_t)0x01) /*!< Digital Input on GPIO */ +#define CONF_GPIO_MODE_DIG_OUTL ((uint8_t)0x02) /*!< Digital Output on GPIO (low current) */ +#define CONF_GPIO_MODE_DIG_OUTH ((uint8_t)0x03) /*!< Digital Output on GPIO (high current) */ + +/** + * @} + */ + + +/** @defgroup MCU_CK_CONF_Register + * @{ + */ + +/** + * \brief MCU_CK_CONF register + * \code + * Read Write + * Default value: 0x00 + * 7 Reserved. + * 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided before entering in STANDBY state. + * CLOCK_TAIL1 | CLOCK_TAIL0 | Number of Extra Cycles + * ------------------------------------------------------------ + * 0 | 0 | 0 + * 0 | 1 | 64 + * 1 | 0 | 256 + * 1 | 1 | 512 + * 4:1 XO_RATIO[3:0]: Specifies the division ratio when XO oscillator is the clock source + * XO_RATIO[3:0] | Division Ratio + * ----------------------------------- + * 0 | 1 + * 1 | 2/3 + * 2 | 1/2 + * 3 | 1/3 + * 4 | 1/4 + * 5 | 1/6 + * 6 | 1/8 + * 7 | 1/12 + * 8 | 1/16 + * 9 | 1/24 + * 10 | 1/36 + * 11 | 1/48 + * 12 | 1/64 + * 13 | 1/96 + * 14 | 1/128 + * 15 | 1/256 + * 0 RCO_RATIO: Specifies the divsion ratio when RC oscillator is the clock source + * 0 - Division Ratio equal to 0 + * 1 - Division Ratio equal to 1/128 + * \endcode + */ + + +#define MCU_CK_CONF_BASE ((uint8_t)0x06) /*!< MCU Clock Config register address */ + +#define MCU_CK_ENABLE ((uint8_t)0x80) /*!< MCU clock enable bit */ + +#define MCU_CK_CONF_CLOCK_TAIL_0 ((uint8_t)0x00) /*!< 0 extra clock cycles provided to the MCU before switching to STANDBY state */ +#define MCU_CK_CONF_CLOCK_TAIL_64 ((uint8_t)0x20) /*!< 64 extra clock cycles provided to the MCU before switching to STANDBY state */ +#define MCU_CK_CONF_CLOCK_TAIL_256 ((uint8_t)0x40) /*!< 256 extra clock cycles provided to the MCU before switching to STANDBY state */ +#define MCU_CK_CONF_CLOCK_TAIL_512 ((uint8_t)0x60) /*!< 512 extra clock cycles provided to the MCU before switching to STANDBY state */ +#define MCU_CK_CONF_XO_RATIO_1 ((uint8_t)0x00) /*!< XO Clock signal available on the GPIO divided by 1 */ +#define MCU_CK_CONF_XO_RATIO_2_3 ((uint8_t)0x02) /*!< XO Clock signal available on the GPIO divided by 2/3 */ +#define MCU_CK_CONF_XO_RATIO_1_2 ((uint8_t)0x04) /*!< XO Clock signal available on the GPIO divided by 1/2 */ +#define MCU_CK_CONF_XO_RATIO_1_3 ((uint8_t)0x06) /*!< XO Clock signal available on the GPIO divided by 1/3 */ +#define MCU_CK_CONF_XO_RATIO_1_4 ((uint8_t)0x08) /*!< XO Clock signal available on the GPIO divided by 1/4 */ +#define MCU_CK_CONF_XO_RATIO_1_6 ((uint8_t)0x0A) /*!< XO Clock signal available on the GPIO divided by 1/6 */ +#define MCU_CK_CONF_XO_RATIO_1_8 ((uint8_t)0x0C) /*!< XO Clock signal available on the GPIO divided by 1/8 */ +#define MCU_CK_CONF_XO_RATIO_1_12 ((uint8_t)0x0E) /*!< XO Clock signal available on the GPIO divided by 1/12 */ +#define MCU_CK_CONF_XO_RATIO_1_16 ((uint8_t)0x10) /*!< XO Clock signal available on the GPIO divided by 1/16 */ +#define MCU_CK_CONF_XO_RATIO_1_24 ((uint8_t)0x12) /*!< XO Clock signal available on the GPIO divided by 1/24 */ +#define MCU_CK_CONF_XO_RATIO_1_36 ((uint8_t)0x14) /*!< XO Clock signal available on the GPIO divided by 1/36 */ +#define MCU_CK_CONF_XO_RATIO_1_48 ((uint8_t)0x16) /*!< XO Clock signal available on the GPIO divided by 1/48 */ +#define MCU_CK_CONF_XO_RATIO_1_64 ((uint8_t)0x18) /*!< XO Clock signal available on the GPIO divided by 1/64 */ +#define MCU_CK_CONF_XO_RATIO_1_96 ((uint8_t)0x1A) /*!< XO Clock signal available on the GPIO divided by 1/96 */ +#define MCU_CK_CONF_XO_RATIO_1_128 ((uint8_t)0x1C) /*!< XO Clock signal available on the GPIO divided by 1/128 */ +#define MCU_CK_CONF_XO_RATIO_1_192 ((uint8_t)0x1E) /*!< XO Clock signal available on the GPIO divided by 1/196 */ +#define MCU_CK_CONF_RCO_RATIO_1 ((uint8_t)0x00) /*!< RCO Clock signal available on the GPIO divided by 1 */ +#define MCU_CK_CONF_RCO_RATIO_1_128 ((uint8_t)0x01) /*!< RCO Clock signal available on the GPIO divided by 1/128*/ + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup Radio_Configuration_Registers + * @{ + */ + + + +/** @defgroup SYNT3_Register + * @{ + */ + +/** + * \brief SYNT3 register + * \code + * Read Write + * Default value: 0x0C + * + * 7:5 WCP[2:0]: Set the charge pump current according to the VCO frequency in RX mode. + * + * VCO Frequency | WCP2 | WCP1 | WCP0 | Charge Pump Current (uA) + * ------------------------------------------------------------------------------------------------------------ + * 4644-4678 | 0 | 0 | 0 | 378.4 + * 4708-4772 | 0 | 0 | 1 | 368.9 + * 4772-4836 | 0 | 1 | 0 | 359.5 + * 4836-4902 | 0 | 1 | 1 | 350 + * 4902-4966 | 1 | 0 | 0 | 340.5 + * 4966-5030 | 1 | 0 | 1 | 331.1 + * 5030-5095 | 1 | 1 | 0 | 321.6 + * 5095-5161 | 1 | 1 | 1 | 312.2 + * 5161-5232 | 0 | 0 | 0 | 378.4 + * 5232-5303 | 0 | 0 | 1 | 368.9 + * 5303-5375 | 0 | 1 | 0 | 359.5 + * 5375-5448 | 0 | 1 | 1 | 350 + * 5448-5519 | 1 | 0 | 0 | 340.5 + * 5519-5592 | 1 | 0 | 1 | 331.1 + * 5592-5663 | 1 | 1 | 0 | 321.6 + * 5663-5736 | 1 | 1 | 1 | 312.2 + * + * + * 4:0 SYNT[25:21]: highest 5 bits of the PLL programmable divider + * The valid range depends on fXO and REFDIV settings; for + * fXO=26MHz + * REFDIV = 0 - SYNT[25:21] = 11...13 + * REFDIV = 1 - SYNT[25:21] = 22…27 + * + * + * \endcode + */ +#define SYNT3_BASE ((uint8_t)0x08) /*!< [4:0] -> SYNT[25:21], highest 5 bits of the PLL programmable divider */ + +#define WCP_CONF_WCP_378UA ((uint8_t)0x00) /*!< Charge pump current nominal value = 378uA [VCO 4644-4708]&[VCO 5161-5232] */ +#define WCP_CONF_WCP_369UA ((uint8_t)0x01) /*!< Charge pump current nominal value = 369uA [VCO 4708-4772]&[VCO 5232-5303] */ +#define WCP_CONF_WCP_359UA ((uint8_t)0x02) /*!< Charge pump current nominal value = 359uA [VCO 4772-4836]&[VCO 5303-5375] */ +#define WCP_CONF_WCP_350UA ((uint8_t)0x03) /*!< Charge pump current nominal value = 350uA [VCO 4836-4902]&[VCO 5375-5448] */ +#define WCP_CONF_WCP_340UA ((uint8_t)0x04) /*!< Charge pump current nominal value = 340uA [VCO 4902-4966]&[VCO 5448-5519] */ +#define WCP_CONF_WCP_331UA ((uint8_t)0x05) /*!< Charge pump current nominal value = 331uA [VCO 4966-5030]&[VCO 5519-5592] */ +#define WCP_CONF_WCP_321UA ((uint8_t)0x06) /*!< Charge pump current nominal value = 321uA [VCO 5030-5095]&[VCO 5592-5563] */ +#define WCP_CONF_WCP_312UA ((uint8_t)0x07) /*!< Charge pump current nominal value = 312uA [VCO 5095-5160]&[VCO 5563-5736] */ + + +/** + * @} + */ + + +/** @defgroup SYNT2_Register + * @{ + */ + +/** + * \brief SYNT2 register + * \code + * Read Write + * Default value: 0x84 + * 7:0 SYNT[20:13]: intermediate bits of the PLL programmable divider. + * + * \endcode + */ + +#define SYNT2_BASE ((uint8_t)0x09) /*!< SYNT[20:13], intermediate bits of the PLL programmable divider */ + +/** + * @} + */ + +/** @defgroup SYNT1_Register + * @{ + */ + +/** + * \brief SYNT1 register + * \code + * Read Write + * Default value: 0xEC + * 7:0 SYNT[12:5]: intermediate bits of the PLL programmable divider. + * + * \endcode + */ + +#define SYNT1_BASE ((uint8_t)0x0A) /*!< SYNT[12:5], intermediate bits of the PLL programmable divider */ + +/** + * @} + */ + +/** @defgroup SYNT0_Register + * @{ + */ + +/** + * \brief SYNT0 register + * \code + * Read Write + * Default value: 0x51 + * 7:3 SYNT[4:0]: lowest bits of the PLL programmable divider. + * 2:0 BS[2:0]: Synthesizer band select. This parameter selects the out-of-loop divide factor of the synthesizer + * according to the formula fxo/(B/2)/D*SYNT/2^18 + * + * BS2 | BS1 | BS0 | value of B + * --------------------------------------------------------------------------- + * 0 | 0 | 1 | 6 + * 0 | 1 | 0 | 8 + * 0 | 1 | 1 | 12 + * 1 | 0 | 0 | 16 + * 1 | 0 | 1 | 32 + * + * \endcode + */ +#define SYNT0_BASE ((uint8_t)0x0B) /*!< [7:3] -> SYNT[4:0], lowest bits of the PLL programmable divider */ + +#define SYNT0_BS_6 ((uint8_t)0x01) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=6 (779-956MHz) */ +#define SYNT0_BS_8 ((uint8_t)0x02) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=8 (387-470MHz)*/ +#define SYNT0_BS_12 ((uint8_t)0x03) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=12 (387-470MHz)*/ +#define SYNT0_BS_16 ((uint8_t)0x04) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=16 (300-348MHz)*/ +#define SYNT0_BS_32 ((uint8_t)0x05) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=32 (150-174MHz)*/ + +/** + * @} + */ + +/** @defgroup CHSPACE_Register + * @{ + */ + +/** + * \brief CHSPACE register + * \code + * Read Write + * Default value: 0xFC + * 7:0 CH_SPACING[7:0]: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps + * (in general, frequency step is fXO/215=26MHz/215~793Hz). + * + * \endcode + */ + +#define CHSPACE_BASE ((uint8_t)0x0C) /*!< Channel spacing. From ~0.8KHz to ~200KHz in (fXO/2^15)Hz (793Hz for 26MHz XO) steps */ + +/** + * @} + */ + + + +/** @defgroup IF_OFFSET_DIG_Register + * @{ + */ + +/** + * \brief IF_OFFSET_DIG register + * \code + * Read Write + * Default value: 0xA3 + * 7:0 IF_OFFSET_DIG[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz. + * + * \endcode + */ +#define IF_OFFSET_DIG_BASE ((uint8_t)0x0D) /*!< Intermediate frequency fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz */ + +/** + * @} + */ + +/** @defgroup IF_OFFSET_ANA_Register + * @{ + */ + +/** + * \brief IF_OFFSET_ANA register + * \code + * Read Write + * Default value: 0xA3 + * 7:0 IF_OFFSET_ANA[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz. + * + * \endcode + */ +#define IF_OFFSET_ANA_BASE ((uint8_t)0x07) /*!< Intermediate frequency fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz */ + + +/** + * @} + */ + +/** @defgroup FC_OFFSET1_Register + * @{ + */ + +/** + * \brief FC_OFFSET1 registers + * \code + * Read Write + * Default value: 0xA3 + * 7:4 Reserved. + * 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a 12-bit 2’s complement integer + * representing an offset in 99Hz(2) units added/subtracted to the + * carrier frequency set by registers SYNT3…SYNT0. + * This register can be used to set a fixed correction value + * obtained e.g. from crystal measurements. + * + * \endcode + */ +#define FC_OFFSET1_BASE ((uint8_t)0x0E) /*!< [3:0] -> [11:8] Carrier offset (upper part) */ + +/** + * @} + */ + + +/** @defgroup FC_OFFSET0_Register + * @{ + */ + +/** + * \brief FC_OFFSET0 registers + * \code + * Default value: 0x00 + * Read Write + * 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a 12-bit 2’s complement integer + * representing an offset in 99Hz(2) units added/subtracted to the + * carrier frequency set by registers SYNT3…SYNT0. + * This register can be used to set a fixed correction value + * obtained e.g. from crystal measurements. + * + * \endcode + */ +#define FC_OFFSET0_BASE ((uint8_t)0x0F) /*!< [7:0] -> [7:0] Carrier offset (lower part). This value is a 12-bit 2’s complement integer + representing an offset in fXO/2^18 (99Hz for 26 MHz XO) units added/subtracted to the carrier frequency + set by registers SYNT3…SYNT0. Range is +/-200kHz with 26 MHz XO */ +/** + * @} + */ + + +/** @defgroup PA_LEVEL_x_Registers + * @{ + */ + +/** + * \brief PA_POWER_x[8:1] registers + * \code + * Default values from 8 to 1: [0x03, 0x0E, 0x1A, 0x25, 0x35, 0x40, 0x4E, 0x00] + * Read Write + * + * 7 Reserved. + * 6:0 PA_LEVEL_(x-1)[6:0]: Output power level for x-th slot. + * \endcode + */ + +#define PA_POWER8_BASE ((uint8_t)0x10) /*!< PA Power level for 8th slot of PA ramping or ASK modulation */ +#define PA_POWER7_BASE ((uint8_t)0x11) /*!< PA Power level for 7th slot of PA ramping or ASK modulation */ +#define PA_POWER6_BASE ((uint8_t)0x12) /*!< PA Power level for 6th slot of PA ramping or ASK modulation */ +#define PA_POWER5_BASE ((uint8_t)0x13) /*!< PA Power level for 5th slot of PA ramping or ASK modulation */ +#define PA_POWER4_BASE ((uint8_t)0x14) /*!< PA Power level for 4th slot of PA ramping or ASK modulation */ +#define PA_POWER3_BASE ((uint8_t)0x15) /*!< PA Power level for 3rd slot of PA ramping or ASK modulation */ +#define PA_POWER2_BASE ((uint8_t)0x16) /*!< PA Power level for 2nd slot of PA ramping or ASK modulation */ +#define PA_POWER1_BASE ((uint8_t)0x17) /*!< PA Power level for 1st slot of PA ramping or ASK modulation */ + +/** + * @} + */ + +/** @defgroup PA_POWER_CONF_Registers + * @{ + */ + +/** + * \brief PA_POWER_CONF_Registers + * \code + * Default value:0x07 + * Read Write + * + * 7:6 CWC[1:0]: Output stage additional load capacitors bank (to be used to + * optimize the PA for different sub-bands). + * + * CWC1 | CWC0 | Total capacity in pF + * --------------------------------------------------------- + * 0 | 0 | 0 + * 0 | 1 | 1.2 + * 1 | 0 | 2.4 + * 1 | 1 | 3.6 + * + * 5 PA_RAMP_ENABLE: + * 1 - Enable the power ramping + * 0 - Disable the power ramping + * 4:3 PA_RAMP_STEP_WIDTH[1:0]: Step width in bit period + * + * PA_RAMP_STEP_WIDTH1 | PA_RAMP_STEP_WIDTH0 | PA ramping time step + * ------------------------------------------------------------------------------------------- + * 0 | 0 | 1/8 Bit period + * 0 | 1 | 2/8 Bit period + * 1 | 0 | 3/8 Bit period + * 1 | 1 | 4/8 Bit period + * + * 2:0 PA_LEVEL_MAX_INDEX[2:0]: Fixes the MAX PA LEVEL in PA ramping or ASK modulation + * + * \endcode + */ +#define PA_POWER0_BASE ((uint8_t)0x18) /*!< PA ramping settings and additional load capacitor banks used + for PA optimization in different sub bands*/ +#define PA_POWER0_CWC_MASK ((uint8_t)0x20) /*!< Output stage additional load capacitors bank */ +#define PA_POWER0_CWC_0 ((uint8_t)0x00) /*!< No additional PA load capacitor */ +#define PA_POWER0_CWC_1_2P ((uint8_t)0x40) /*!< 1.2pF additional PA load capacitor */ +#define PA_POWER0_CWC_2_4P ((uint8_t)0x80) /*!< 2.4pF additional PA load capacitor */ +#define PA_POWER0_CWC_3_6P ((uint8_t)0xC0) /*!< 3.6pF additional PA load capacitor */ +#define PA_POWER0_PA_RAMP_MASK ((uint8_t)0x20) /*!< The PA power ramping */ +#define PA_POWER0_PA_RAMP_STEP_WIDTH_MASK ((uint8_t)0x20) /*!< The step width */ +#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_8 ((uint8_t)0x00) /*!< PA ramping time step = 1/8 Bit period*/ +#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_4 ((uint8_t)0x08) /*!< PA ramping time step = 2/8 Bit period*/ +#define PA_POWER0_PA_RAMP_STEP_WIDTH_3TB_8 ((uint8_t)0x10) /*!< PA ramping time step = 3/8 Bit period*/ +#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_2 ((uint8_t)0x18) /*!< PA ramping time step = 4/8 Bit period*/ +#define PA_POWER0_PA_LEVEL_MAX_INDEX ((uint8_t)0x20) /*!< Final level for power ramping */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_0 ((uint8_t)0x00) /*!< */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_1 ((uint8_t)0x01) /*!< Fixes the MAX PA LEVEL in PA ramping or ASK modulation */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_2 ((uint8_t)0x02) /*!< */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_3 ((uint8_t)0x03) /*!< _________ */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_4 ((uint8_t)0x04) /*!< PA_LVL2 _| <--| */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_5 ((uint8_t)0x05) /*!< _| | */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_6 ((uint8_t)0x06) /*!< PA_LVL1 _| | */ +#define PA_POWER0_PA_LEVEL_MAX_INDEX_7 ((uint8_t)0x07) /*!< PA_LVL0 _| MAX_INDEX- */ + + + +/** + * @} + */ + + +/** @defgroup MOD1_Register + * @{ + */ + +/** + * \brief MOD1 register + * \code + * Read Write + * Default value: 0x83 + * 7:0 DATARATE_M[7:0]: The Mantissa of the specified data rate + * + * \endcode + */ +#define MOD1_BASE ((uint8_t)0x1A) /*!< The Mantissa of the specified data rate */ + +/** + * @} + */ + +/** @defgroup MOD0_Register + * @{ + */ + +/** + * \brief MOD0 register + * \code + * Read Write + * Default value: 0x1A + * 7 CW: 1 - CW Mode enabled - enables the generation of a continous wave carrier without any modulation + * 0 - CW Mode disabled + * + * 6 BT_SEL: Select BT value for GFSK + * 1 - BT=0.5 + * 0 - BT=1 + * + * 5:4 MOD_TYPE[1:0]: Modulation type + * + * + * MOD_TYPE1 | MOD_TYPE0 | Modulation + * --------------------------------------------------------- + * 0 | 0 | 2-FSK,MSK + * 0 | 1 | GFSK,GMSK + * 1 | 0 | ASK/OOK + * + * 3:0 DATARATE_E[3:0]: The Exponent of the specified data rate + * + * \endcode + */ +#define MOD0_BASE ((uint8_t)0x1B) /*!< Modulation Settings, Exponent of the specified data rate, CW mode*/ + +#define MOD0_MOD_TYPE_2_FSK ((uint8_t)0x00) /*!< Modulation type 2-FSK (MSK if the frequency deviation is identical to a quarter of the data rate) */ +#define MOD0_MOD_TYPE_GFSK ((uint8_t)0x10) /*!< Modulation type GFSK (GMSK if the frequency deviation is identical to a quarter of the data rate) */ +#define MOD0_MOD_TYPE_ASK ((uint8_t)0x20) /*!< Modulation type ASK (OOK the PA is switched off for symbol "0") */ +#define MOD0_MOD_TYPE_MSK ((uint8_t)0x00) /*!< Modulation type MSK (the frequency deviation must be identical to a quarter of the data rate) */ +#define MOD0_MOD_TYPE_GMSK ((uint8_t)0x10) /*!< Modulation type GMSK (the frequency deviation must be identical to a quarter of the data rate) */ +#define MOD0_BT_SEL_BT_MASK ((uint8_t)0x00) /*!< Select the BT = 1 or BT = 0.5 valid only for GFSK or GMSK modulation*/ +#define MOD0_CW ((uint8_t)0x80) /*!< Set the Continous Wave (no modulation) transmit mode */ + +/** + * @} + */ + + +/** @defgroup FDEV0_Register + * @{ + */ + +/** + * \brief FDEV0 register + * \code + * Read Write + * Default value: 0x45 + * 7:4 FDEV_E[3:0]: Exponent of the frequency deviation (allowed values from 0 to 9) + * + * 3 CLOCK_REC_ALGO_SEL: Select PLL or DLL mode for clock recovery + * 1 - DLL mode + * 0 - PLL mode + * + * 2:0 FDEV_M[1:0]: Mantissa of the frequency deviation (allowed values from 0 to 7) + * + * + * \endcode + */ +#define FDEV0_BASE ((uint8_t)0x1C) /*!< Sets the Mantissa and exponent of frequency deviation (frequency separation/2) + and PLL or DLL alogrithm from clock recovery in RX digital demod*/ +#define FDEV0_CLOCK_REG_ALGO_SEL_MASK ((uint8_t)0x08) /*!< Can be DLL or PLL algorithm for clock recovery in RX digital demod (see CLOCKREC reg) */ +#define FDEV0_CLOCK_REG_ALGO_SEL_PLL ((uint8_t)0x00) /*!< Sets PLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) */ +#define FDEV0_CLOCK_REG_ALGO_SEL_DLL ((uint8_t)0x08) /*!< Sets DLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) */ + +/** + * @} + */ + +/** @defgroup CHFLT_Register + * @{ + */ + +/** + * \brief CHFLT register + * \code + * Read Write + * Default value: 0x23 + * 7:4 CHFLT_M[3:0]: Mantissa of the channel filter BW (allowed values from 0 to 8) + * + * 3:0 CHFLT_E[3:0]: Exponent of the channel filter BW (allowed values from 0 to 9) + * + * M\E | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | + * -----+-------+-------+-------+-------+------+------+------+-----+-----+-----+ + * 0 | 800.1 | 450.9 | 224.7 | 112.3 | 56.1 | 28.0 | 14.0 | 7.0 | 3.5 | 1.8 | + * 1 | 795.1 | 425.9 | 212.4 | 106.2 | 53.0 | 26.5 | 13.3 | 6.6 | 3.3 | 1.7 | + * 2 | 768.4 | 403.2 | 201.1 | 100.5 | 50.2 | 25.1 | 12.6 | 6.3 | 3.1 | 1.6 | + * 3 | 736.8 | 380.8 | 190.0 | 95.0 | 47.4 | 23.7 | 11.9 | 5.9 | 3.0 | 1.5 | + * 4 | 705.1 | 362.1 | 180.7 | 90.3 | 45.1 | 22.6 | 11.3 | 5.6 | 2.8 | 1.4 | + * 5 | 670.9 | 341.7 | 170.6 | 85.3 | 42.6 | 21.3 | 10.6 | 5.3 | 2.7 | 1.3 | + * 6 | 642.3 | 325.4 | 162.4 | 81.2 | 40.6 | 20.3 | 10.1 | 5.1 | 2.5 | 1.3 | + * 7 | 586.7 | 294.5 | 147.1 | 73.5 | 36.7 | 18.4 | 9.2 | 4.6 | 2.3 | 1.2 | + * 8 | 541.4 | 270.3 | 135.0 | 67.5 | 33.7 | 16.9 | 8.4 | 4.2 | 2.1 | 1.1 | + * + * \endcode + */ +#define CHFLT_BASE ((uint8_t)0x1D) /*!< RX Channel Filter Bandwidth */ + +#define CHFLT_800_1 ((uint8_t)0x00) /*!< RX Channel Filter Bandwidth = 800.1 kHz */ +#define CHFLT_795_1 ((uint8_t)0x10) /*!< RX Channel Filter Bandwidth = 795.1 kHz */ +#define CHFLT_768_4 ((uint8_t)0x20) /*!< RX Channel Filter Bandwidth = 768.4 kHz */ +#define CHFLT_736_8 ((uint8_t)0x30) /*!< RX Channel Filter Bandwidth = 736.8 kHz */ +#define CHFLT_705_1 ((uint8_t)0x40) /*!< RX Channel Filter Bandwidth = 705.1 kHz */ +#define CHFLT_670_9 ((uint8_t)0x50) /*!< RX Channel Filter Bandwidth = 670.9 kHz */ +#define CHFLT_642_3 ((uint8_t)0x60) /*!< RX Channel Filter Bandwidth = 642.3 kHz */ +#define CHFLT_586_7 ((uint8_t)0x70) /*!< RX Channel Filter Bandwidth = 586.7 kHz */ +#define CHFLT_541_4 ((uint8_t)0x80) /*!< RX Channel Filter Bandwidth = 541.4 kHz */ +#define CHFLT_450_9 ((uint8_t)0x01) /*!< RX Channel Filter Bandwidth = 450.9 kHz */ +#define CHFLT_425_9 ((uint8_t)0x11) /*!< RX Channel Filter Bandwidth = 425.9 kHz */ +#define CHFLT_403_2 ((uint8_t)0x21) /*!< RX Channel Filter Bandwidth = 403.2 kHz */ +#define CHFLT_380_8 ((uint8_t)0x31) /*!< RX Channel Filter Bandwidth = 380.8 kHz */ +#define CHFLT_362_1 ((uint8_t)0x41) /*!< RX Channel Filter Bandwidth = 362.1 kHz */ +#define CHFLT_341_7 ((uint8_t)0x51) /*!< RX Channel Filter Bandwidth = 341.7 kHz */ +#define CHFLT_325_4 ((uint8_t)0x61) /*!< RX Channel Filter Bandwidth = 325.4 kHz */ +#define CHFLT_294_5 ((uint8_t)0x71) /*!< RX Channel Filter Bandwidth = 294.5 kHz */ +#define CHFLT_270_3 ((uint8_t)0x81) /*!< RX Channel Filter Bandwidth = 270.3 kHz */ +#define CHFLT_224_7 ((uint8_t)0x02) /*!< RX Channel Filter Bandwidth = 224.7 kHz */ +#define CHFLT_212_4 ((uint8_t)0x12) /*!< RX Channel Filter Bandwidth = 212.4 kHz */ +#define CHFLT_201_1 ((uint8_t)0x22) /*!< RX Channel Filter Bandwidth = 201.1 kHz */ +#define CHFLT_190 ((uint8_t)0x32) /*!< RX Channel Filter Bandwidth = 190.0 kHz */ +#define CHFLT_180_7 ((uint8_t)0x42) /*!< RX Channel Filter Bandwidth = 180.7 kHz */ +#define CHFLT_170_6 ((uint8_t)0x52) /*!< RX Channel Filter Bandwidth = 170.6 kHz */ +#define CHFLT_162_4 ((uint8_t)0x62) /*!< RX Channel Filter Bandwidth = 162.4 kHz */ +#define CHFLT_147_1 ((uint8_t)0x72) /*!< RX Channel Filter Bandwidth = 147.1 kHz */ +#define CHFLT_135 ((uint8_t)0x82) /*!< RX Channel Filter Bandwidth = 135.0 kHz */ +#define CHFLT_112_3 ((uint8_t)0x03) /*!< RX Channel Filter Bandwidth = 112.3 kHz */ +#define CHFLT_106_2 ((uint8_t)0x13) /*!< RX Channel Filter Bandwidth = 106.2 kHz */ +#define CHFLT_100_5 ((uint8_t)0x23) /*!< RX Channel Filter Bandwidth = 100.5 kHz */ +#define CHFLT_95 ((uint8_t)0x33) /*!< RX Channel Filter Bandwidth = 95.0 kHz */ +#define CHFLT_90_3 ((uint8_t)0x43) /*!< RX Channel Filter Bandwidth = 90.3 kHz */ +#define CHFLT_85_3 ((uint8_t)0x53) /*!< RX Channel Filter Bandwidth = 85.3 kHz */ +#define CHFLT_81_2 ((uint8_t)0x63) /*!< RX Channel Filter Bandwidth = 81.2 kHz */ +#define CHFLT_73_5 ((uint8_t)0x73) /*!< RX Channel Filter Bandwidth = 73.5 kHz */ +#define CHFLT_67_5 ((uint8_t)0x83) /*!< RX Channel Filter Bandwidth = 67.5 kHz */ +#define CHFLT_56_1 ((uint8_t)0x04) /*!< RX Channel Filter Bandwidth = 56.1 kHz */ +#define CHFLT_53 ((uint8_t)0x14) /*!< RX Channel Filter Bandwidth = 53.0 kHz */ +#define CHFLT_50_2 ((uint8_t)0x24) /*!< RX Channel Filter Bandwidth = 50.2 kHz */ +#define CHFLT_47_4 ((uint8_t)0x34) /*!< RX Channel Filter Bandwidth = 47.4 kHz */ +#define CHFLT_45_1 ((uint8_t)0x44) /*!< RX Channel Filter Bandwidth = 45.1 kHz */ +#define CHFLT_42_6 ((uint8_t)0x54) /*!< RX Channel Filter Bandwidth = 42.6 kHz */ +#define CHFLT_40_6 ((uint8_t)0x64) /*!< RX Channel Filter Bandwidth = 40.6 kHz */ +#define CHFLT_36_7 ((uint8_t)0x74) /*!< RX Channel Filter Bandwidth = 36.7 kHz */ +#define CHFLT_33_7 ((uint8_t)0x84) /*!< RX Channel Filter Bandwidth = 33.7 kHz */ +#define CHFLT_28 ((uint8_t)0x05) /*!< RX Channel Filter Bandwidth = 28.0 kHz */ +#define CHFLT_26_5 ((uint8_t)0x15) /*!< RX Channel Filter Bandwidth = 26.5 kHz */ +#define CHFLT_25_1 ((uint8_t)0x25) /*!< RX Channel Filter Bandwidth = 25.1 kHz */ +#define CHFLT_23_7 ((uint8_t)0x35) /*!< RX Channel Filter Bandwidth = 23.7 kHz */ +#define CHFLT_22_6 ((uint8_t)0x45) /*!< RX Channel Filter Bandwidth = 22.6 kHz */ +#define CHFLT_21_3 ((uint8_t)0x55) /*!< RX Channel Filter Bandwidth = 21.3 kHz */ +#define CHFLT_20_3 ((uint8_t)0x65) /*!< RX Channel Filter Bandwidth = 20.3 kHz */ +#define CHFLT_18_4 ((uint8_t)0x75) /*!< RX Channel Filter Bandwidth = 18.4 kHz */ +#define CHFLT_16_9 ((uint8_t)0x85) /*!< RX Channel Filter Bandwidth = 16.9 kHz */ +#define CHFLT_14 ((uint8_t)0x06) /*!< RX Channel Filter Bandwidth = 14.0 kHz */ +#define CHFLT_13_3 ((uint8_t)0x16) /*!< RX Channel Filter Bandwidth = 13.3 kHz */ +#define CHFLT_12_6 ((uint8_t)0x26) /*!< RX Channel Filter Bandwidth = 12.6 kHz */ +#define CHFLT_11_9 ((uint8_t)0x36) /*!< RX Channel Filter Bandwidth = 11.9 kHz */ +#define CHFLT_11_3 ((uint8_t)0x46) /*!< RX Channel Filter Bandwidth = 11.3 kHz */ +#define CHFLT_10_6 ((uint8_t)0x56) /*!< RX Channel Filter Bandwidth = 10.6 kHz */ +#define CHFLT_10_1 ((uint8_t)0x66) /*!< RX Channel Filter Bandwidth = 10.1 kHz */ +#define CHFLT_9_2 ((uint8_t)0x76) /*!< RX Channel Filter Bandwidth = 9.2 kHz */ +#define CHFLT_8_4 ((uint8_t)0x86) /*!< RX Channel Filter Bandwidth = 8.4 kHz */ +#define CHFLT_7 ((uint8_t)0x07) /*!< RX Channel Filter Bandwidth = 7.0 kHz */ +#define CHFLT_6_6 ((uint8_t)0x17) /*!< RX Channel Filter Bandwidth = 6.6 kHz */ +#define CHFLT_6_3 ((uint8_t)0x27) /*!< RX Channel Filter Bandwidth = 6.3 kHz */ +#define CHFLT_5_9 ((uint8_t)0x37) /*!< RX Channel Filter Bandwidth = 5.9 kHz */ +#define CHFLT_5_6 ((uint8_t)0x47) /*!< RX Channel Filter Bandwidth = 5.6 kHz */ +#define CHFLT_5_3 ((uint8_t)0x57) /*!< RX Channel Filter Bandwidth = 5.3 kHz */ +#define CHFLT_5_1 ((uint8_t)0x67) /*!< RX Channel Filter Bandwidth = 5.1 kHz */ +#define CHFLT_4_6 ((uint8_t)0x77) /*!< RX Channel Filter Bandwidth = 4.6 kHz */ +#define CHFLT_4_2 ((uint8_t)0x87) /*!< RX Channel Filter Bandwidth = 4.2 kHz */ +#define CHFLT_3_5 ((uint8_t)0x08) /*!< RX Channel Filter Bandwidth = 3.5 kHz */ +#define CHFLT_3_3 ((uint8_t)0x18) /*!< RX Channel Filter Bandwidth = 3.3 kHz */ +#define CHFLT_3_1 ((uint8_t)0x28) /*!< RX Channel Filter Bandwidth = 3.1 kHz */ +#define CHFLT_3 ((uint8_t)0x38) /*!< RX Channel Filter Bandwidth = 3.0 kHz */ +#define CHFLT_2_8 ((uint8_t)0x48) /*!< RX Channel Filter Bandwidth = 2.8 kHz */ +#define CHFLT_2_7 ((uint8_t)0x58) /*!< RX Channel Filter Bandwidth = 2.7 kHz */ +#define CHFLT_2_5 ((uint8_t)0x68) /*!< RX Channel Filter Bandwidth = 2.5 kHz */ +#define CHFLT_2_3 ((uint8_t)0x78) /*!< RX Channel Filter Bandwidth = 2.3 kHz */ +#define CHFLT_2_1 ((uint8_t)0x88) /*!< RX Channel Filter Bandwidth = 2.1 kHz */ +#define CHFLT_1_8 ((uint8_t)0x09) /*!< RX Channel Filter Bandwidth = 1.8 kHz */ +#define CHFLT_1_7 ((uint8_t)0x19) /*!< RX Channel Filter Bandwidth = 1.7 kHz */ +#define CHFLT_1_6 ((uint8_t)0x29) /*!< RX Channel Filter Bandwidth = 1.6 kHz */ +#define CHFLT_1_5 ((uint8_t)0x39) /*!< RX Channel Filter Bandwidth = 1.5 kHz */ +#define CHFLT_1_4 ((uint8_t)0x49) /*!< RX Channel Filter Bandwidth = 1.4 kHz */ +#define CHFLT_1_3a ((uint8_t)0x59) /*!< RX Channel Filter Bandwidth = 1.3 kHz */ +#define CHFLT_1_3 ((uint8_t)0x69) /*!< RX Channel Filter Bandwidth = 1.3 kHz */ +#define CHFLT_1_2 ((uint8_t)0x79) /*!< RX Channel Filter Bandwidth = 1.2 kHz */ +#define CHFLT_1_1 ((uint8_t)0x89) /*!< RX Channel Filter Bandwidth = 1.1 kHz */ + +/** + * @} + */ + +/** @defgroup AFC2_Register + * @{ + */ + +/** + * \brief AFC2 register + * \code + * Read Write + * Default value: 0x48 + * 7 AFC Freeze on Sync: Freeze AFC correction upon sync word detection. + * 1 - AFC Freeze enabled + * 0 - AFC Freeze disabled + * + * 6 AFC Enabled: Enable AFC + * 1 - AFC enabled + * 0 - AFC disabled + * + * 5 AFC Mode: Select AFC mode + * 1 - AFC Loop closed on 2nd conversion stage. + * 0 - AFC Loop closed on slicer + * + * 4:0 AFC PD leakage[4:0]: Peak detector leakage. This parameter sets the decay speed of the min/max frequency peak detector (AFC2 register), + * the range allowed is 0..31 (0 - no leakage, 31 - high leakage). The recommended value for this parameter is 4. + * + * \endcode + */ +#define AFC2_BASE ((uint8_t)0x1E) /*!< Automatic frequency compensation algorithm parameters (FSK/GFSK/MSK)*/ + +#define AFC2_AFC_FREEZE_ON_SYNC_MASK ((uint8_t)0x80) /*!< The frequency correction value is frozen when SYNC word is detected */ +#define AFC2_AFC_MASK ((uint8_t)0x40) /*!< Mask of Automatic Frequency Correction */ +#define AFC2_AFC_MODE_MASK ((uint8_t)0x20) /*!< Automatic Frequency Correction can be in Main MODE or Auxiliary MODE*/ +#define AFC2_AFC_MODE_SLICER ((uint8_t)0x00) /*!< Automatic Frequency Correction Main MODE */ +#define AFC2_AFC_MODE_MIXER ((uint8_t)0x20) /*!< Automatic Frequency Correction Auxiliary MODE */ + +/** + * @} + */ + +/** @defgroup AFC1_Register + * @{ + */ + +/** + * \brief AFC1 register + * \code + * Read Write + * Default value: 0x18 + * 7:0 AFC_FAST_PERIOD: Length of the AFC fast period. this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed + * is 0..255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the + * algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble + * symbols. + * + * \endcode + */ +#define AFC1_BASE ((uint8_t)0x1F) /*!< Length of the AFC fast period */ + +/** + * @} + */ + +/** @defgroup AFC0_Register + * @{ + */ + +/** + * \brief AFC0 register + * \code + * Read Write + * Default value: 0x25 + * 7:4 AFC_FAST_GAIN_LOG2[3:0]: AFC loop gain in fast mode (2's log) + * + * 3:0 AFC_SLOW_GAIN_LOG2[3:0]: AFC loop gain in slow mode (2's log) + * + * \endcode + */ +#define AFC0_BASE ((uint8_t)0x20) /*!< AFC loop gain in fast and slow modes (2's log) */ + +/** + * @} + */ + +/** @defgroup CLOCKREC_Register + * @{ + */ + +/** + * \brief CLOCKREC register + * \code + * Read Write + * Default value: 0x58 + * + * 7:5 CLK_REC_P_GAIN [2:0]: Clock recovery loop gain (log2) + * + * 4 PSTFLT_LEN: Set Postfilter length + * 1 - 16 symbols + * 0 - 8 symbols + * + * 3:0 CLK_REC_I_GAIN[3:0]: Integral gain for the clock recovery loop + * \endcode + */ + +#define CLOCKREC_BASE ((uint8_t)0x23) /*!< Gain of clock recovery loop - Postfilter length 0-8 symbols, 1-16 symbols */ + +/** + * @} + */ + +/** @defgroup AGCCTRL2_Register + * @{ + */ + +/** + * \brief AGCCTRL2 register + * \code + * Read Write + * Default value: 0x22 + * + * 7 Reserved + * + * 6 FREEZE_ON_STEADY: Enable freezing on steady state + * 1 - Enable + * 0 - Disable + * + * 5 FREEZE_ON_SYNC: Enable freezing on sync detection + * 1 - Enable + * 0 - Disable + * + * 4 START_MAX_ATTENUATION: Start with max attenuation + * 1 - Enable + * 0 - Disable + * + * 3:0 MEAS_TIME[3:0]: Measure time during which the signal peak is detected (according to the formula 12/fxo*2^MEAS_TIME) + * \endcode + */ +#define AGCCTRL2_BASE ((uint8_t)0x24) /*!< AGC freeze strategy, AGC attenuation strategy, AGC measure time */ + +#define AGCCTRL2_FREEZE_ON_STEADY_MASK ((uint8_t)0x40) /*!< The attenuation settings will be frozen as soon as signal level + is betweeen min and max treshold (see AGCCTRL1) */ +#define AGCCTRL2_FREEZE_ON_SYNC_MASK ((uint8_t)0x20) /*!< The attenuation settings will be frozen as soon sync word is detected */ +#define AGCCTRL2_START_MAX_ATTENUATION_MASK ((uint8_t)0x10) /*!< The AGC algorithm can start with MAX attenuation or MIN attenuation */ + +/** + * @} + */ + +/** @defgroup AGCCTRL1_Register + * @{ + */ + +/** + * \brief AGCCTRL1 register + * \code + * Read Write + * Default value: 0x65 + * + * 7:4 THRESHOLD_HIGH[3:0]: High threshold for the AGC + * + * 3:0 THRESHOLD_LOW[3:0]: Low threshold for the AGC + * \endcode + */ +#define AGCCTRL1_BASE ((uint8_t)0x25) /*!< Sets low and high threshold for AGC */ + +/** + * @} + */ + +/** @defgroup AGCCTRL0_Register + * @{ + */ + +/** + * \brief AGCCTRL0 register + * \code + * Read Write + * Default value: 0x8A + * + * 7 AGC S_ENABLE: Enable AGC + * 1 - Enable + * 0 - Disable + * + * 6 AGC_MODE: Set linear-Binary AGC mode + * 1 - Enable + * 0 - Disable + * + * 5:0 HOLD_TIME[5:0]: Hold time after gain adjustment according to formula 12/fxo*HOLD_TIME + * \endcode + */ +#define AGCCTRL0_BASE ((uint8_t)0x26) /*!< Enables AGC, set AGC algo between linear/binary mode, set hold time + to account signal propagation through RX chain */ +#define AGCCTRL0_AGC_MASK ((uint8_t)0x80) /*!< AGC on/off */ +#define AGCCTRL0_AGC_MODE_MASK ((uint8_t)0x40) /*!< AGC search correct attenuation in binary mode or sequential mode */ +#define AGCCTRL0_AGC_MODE_LINEAR ((uint8_t)0x00) /*!< AGC search correct attenuation in sequential mode (recommended) */ +#define AGCCTRL0_AGC_MODE_BINARY ((uint8_t)0x40) /*!< AGC search correct attenuation in binary mode */ + +/** + * @} + */ + +/** @defgroup CHNUM_Register + * @{ + */ + +/** + * \brief CHNUM registers + * \code + * Default value: 0x00 + * Read Write + * 7:0 CH_NUM[7:0]: Channel number. This value is multiplied by the channel spacing and added to the + * synthesizer base frequency to generate the actual RF carrier frequency. + * \endcode + */ +#define CHNUM_BASE ((uint8_t)0x6C) /*!< Channel number. This value is multiplied by the channel + spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency */ +/** + * @} + */ + +/** @defgroup AFC_CORR_Register + * @{ + */ + +/** + * \brief AFC_CORR registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 AFC_CORR[7:0]: AFC word of the received packet + * \endcode + */ +#define AFC_CORR_BASE ((uint8_t)(0xC4)) /*!< AFC word of the received packet */ + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup Packet_Configuration_Registers + * @{ + */ + +/** @defgroup PCKTCTRL4_Register + * @{ + */ + +/** + * \brief PCKTCTRL4 register + * \code + * Read Write + * Default value: 0x00 + * + * 7:5 NOT_USED. + * + * 4:3 ADDRESS_LEN[1:0]: length of address field in bytes + * + * 2:0 control_len[2:0]: length of control field in bytes + * \endcode + */ +#define PCKTCTRL4_BASE ((uint8_t)0x30) /*!< lenghts of address and control field */ + +#define PCKTCTRL4_ADDRESS_LEN_MASK ((uint8_t)0x18) +#define PCKTCTRL4_CONTROL_LEN_MASK ((uint8_t)0x07) + +/** + * @} + */ + +/** @defgroup PCKTCTRL3_Register + * @{ + */ + +/** + * \brief PCKTCTRL3 register + * \code + * Read Write + * Default value: 0x07 + * + * 7:6 PCKT_FRMT[1:0]: format of packet + * + * PCKT_FRMT1 | PCKT_FRMT0 | Format + * ---------------------------------------------------------------------- + * 0 | 0 | BASIC + * 1 | 0 | MBUS + * 1 | 1 | STACK + * + * 5:4 RX_MODE[1:0]: length of address 0x30 field in bytes + * + * RX_MODE1 | RX_MODE0 | Rx Mode + * -------------------------------------------------------------------- + * 0 | 0 | normal + * 0 | 1 | direct through FIFO + * 1 | 0 | direct through GPIO + * + * 3:0 LEN_WID[3:0]: length of length field in bits + * \endcode + */ +#define PCKTCTRL3_BASE ((uint8_t)0x31) /*!< packet format, RX mode, lenght of length field */ + +#define PCKTCTRL3_PCKT_FRMT_BASIC ((uint8_t)0x00) /*!< Basic Packet Format */ +#define PCKTCTRL3_PCKT_FRMT_MBUS ((uint8_t)0x80) /*!< Wireless M-BUS Packet Format */ +#define PCKTCTRL3_PCKT_FRMT_STACK ((uint8_t)0xC0) /*!< STack Packet Format */ + +#define PCKTCTRL3_RX_MODE_NORMAL ((uint8_t)0x00) /*!< Normal RX Mode */ +#define PCKTCTRL3_RX_MODE_DIRECT_FIFO ((uint8_t)0x10) /*!< RX Direct Mode; data available through FIFO */ +#define PCKTCTRL3_RX_MODE_DIRECT_GPIO ((uint8_t)0x20) /*!< RX Direct Mode; data available through selected GPIO */ + +#define PCKTCTRL3_PKT_FRMT_MASK ((uint8_t)0xC0) +#define PCKTCTRL3_RX_MODE_MASK ((uint8_t)0x30) +#define PCKTCTRL3_LEN_WID_MASK ((uint8_t)0x0F) + +/** + * @} + */ + +/** @defgroup PCKTCTRL2_Register + * @{ + */ + +/** + * \brief PCKTCTRL2 register + * \code + * Read Write + * Default value: 0x1E + * + * 7:3 PREAMBLE_LENGTH[4:0]: length of preamble field in bytes (0..31) + * + * + * 2:1 SYNC_LENGTH[1:0]: length of sync field in bytes + * + * + * 0 FIX_VAR_LEN: fixed/variable packet length + * 1 - Variable + * 0 - Fixed + * \endcode + */ +#define PCKTCTRL2_BASE ((uint8_t)0x32) /*!< length of preamble and sync fields (in bytes), fix or variable packet length */ + +#define PCKTCTRL2_FIX_VAR_LEN_MASK ((uint8_t)0x01) /*!< Enable/disable the length mode */ +#define PCKTCTRL2_PREAMBLE_LENGTH_MASK ((uint8_t)0xF8) +#define PCKTCTRL2_SYNC_LENGTH_MASK ((uint8_t)0x06) + +/** + * @} + */ + +/** @defgroup PCKTCTRL1_Register + * @{ + */ + +/** + * \brief PCKTCTRL1 register + * \code + * Read Write + * Default value: 0x20 + * + * 7:5 CRC_MODE[2:0]: CRC type (0, 8, 16, 24 bits) + * + * CRC_MODE2 | CRC_MODE1 | CRC_MODE0 | CRC Mode (n. bits - poly) + * ------------------------------------------------------------------------------------------------- + * 0 | 0 | 1 | 8 - 0x07 + * 0 | 1 | 0 | 16 - 0x8005 + * 0 | 1 | 1 | 16 - 0x1021 + * 1 | 0 | 0 | 24 - 0x864CBF + * + * 4 WHIT_EN[0]: Enable Whitening + * 1 - Enable + * 0 - Disable + * + * 3:2 TX_SOURCE[1:0]: length of sync field in bytes + * + * TX_SOURCE1 | TX_SOURCE0 | Tx Mode + * -------------------------------------------------------------------- + * 0 | 0 | normal + * 0 | 1 | direct through FIFO + * 1 | 0 | direct through GPIO + * 1 | 1 | pn9 + * + * 1 NOT_USED + * + * 0 FEC_EN: enable FEC + * 1 - FEC in TX , Viterbi decoding in RX + * 0 - Disabled + * \endcode + */ +#define PCKTCTRL1_BASE ((uint8_t)0x33) /*!< CRC type, whitening enable, TX mode */ + +#define PCKTCTRL1_FEC_MASK ((uint8_t)0x01) /*!< Enable/disable the Forward Error Correction */ +#define PCKTCTRL1_TX_SOURCE_MASK ((uint8_t)0x0C) /*!< TX source mode */ +#define PCKTCTRL1_CRC_MODE_MASK ((uint8_t)0xE0) /*!< CRC type */ +#define PCKTCTRL1_WHIT_MASK ((uint8_t)0x10) /*!< Enable/disable the Whitening */ + +/** + * @} + */ + + + +/** @defgroup PCKTLEN1_Register + * @{ + */ + +/** + * \brief PCKTLEN1 register + * \code + * Read Write + * Default value: 0x00 + * + * 7:0 pktlen1[7:0]: lenght of packet in bytes (upper field) LENGHT/256 + * \endcode + */ +#define PCKTLEN1_BASE ((uint8_t)0x34) /*!< lenght of packet in bytes (upper field) */ + +/** + * @} + */ + +/** @defgroup PCKTLEN0_Register + * @{ + */ + +/** + * \brief PCKTLEN0 register + * \code + * Read Write + * Default value: 0x14 + * + * 7:0 pktlen0[7:0]: lenght of packet in bytes (lower field) LENGHT%256 + * \endcode + */ +#define PCKTLEN0_BASE ((uint8_t)0x35) /*!< lenght of packet in bytes (lower field) [PCKTLEN=PCKTLEN1x256+PCKTLEN0]*/ + +/** + * @} + */ + +/** @defgroup SYNCx_Registers + * @{ + */ +/** + * \brief SYNCx[4:1] Registers + * \code + * Read Write + * Default value: 0x88 + * + * 7:0 SYNCx[7:0]: xth sync word + * \endcode + */ +#define SYNC4_BASE ((uint8_t)0x36) /*!< Sync word 4 */ +#define SYNC3_BASE ((uint8_t)0x37) /*!< Sync word 3 */ +#define SYNC2_BASE ((uint8_t)0x38) /*!< Sync word 2 */ +#define SYNC1_BASE ((uint8_t)0x39) /*!< Sync word 1 */ + +/** + * @} + */ + + +/** @defgroup MBUS_PRMBL_Register + * @{ + */ + +/** + * \brief MBUS_PRMBL register + * \code + * Read Write + * Default value: 0x20 + * + * 7:0 MBUS_PRMBL[7:0]: MBUS preamble control + * \endcode + */ +#define MBUS_PRMBL_BASE ((uint8_t)0x3B) /*!< MBUS preamble lenght (in 01 bit pairs) */ + +/** + * @} + */ + + +/** @defgroup MBUS_PSTMBL_Register + * @{ + */ + +/** + * \brief MBUS_PSTMBL register + * \code + * Read Write + * Default value: 0x20 + * + * 7:0 MBUS_PSTMBL[7:0]: MBUS postamble control + * \endcode + */ +#define MBUS_PSTMBL_BASE ((uint8_t)0x3C) /*!< MBUS postamble length (in 01 bit pairs) */ + +/** + * @} + */ + +/** @defgroup MBUS_CTRL_Register + * @{ + */ + +/** + * \brief MBUS_CTRL register + * \code + * Read Write + * Default value: 0x00 + * + * 7:4 NOT_USED + * + * 3:1 MBUS_SUBMODE[2:0]: MBUS submode (allowed values are 0,1,3,5) + * + * 0 NOT_USED + * \endcode + */ +#define MBUS_CTRL_BASE ((uint8_t)0x3D) /*!< MBUS sub-modes (S1, S2 short/long header, T1, T2, R2) */ + +#define MBUS_CTRL_MBUS_SUBMODE_S1_S2L ((uint8_t)0x00) /*!< MBUS sub-modes S1 & S2L, header lenght min 279, sync 0x7696, Manchester */ +#define MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER ((uint8_t)0x02) /*!< MBUS sub-modes S2, S1-m, T2 (only other to meter) short header, header lenght min 15, sync 0x7696, Manchester */ +#define MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER ((uint8_t)0x06) /*!< MBUS sub-modes T1, T2 (only meter to other), header lenght min 19, sync 0x3D, 3 out of 6 */ +#define MBUS_CTRL_MBUS_SUBMODE_R2 ((uint8_t)0x0A) /*!< MBUS sub-mode R2, header lenght min 39, sync 0x7696, Manchester */ + +/** + * @} + */ + + + +/** @defgroup PCKT_FLT_GOALS_CONTROLx_MASK_Registers + * @{ + */ + +/** + * \brief PCKT_FLT_GOALS_CONTROLx_MASK registers + * \code + * Default value: 0x00 + * Read Write + * 7:0 CONTROLx_MASK[7:0]: All 0s - no filtering + * + * \endcode + */ +#define PCKT_FLT_GOALS_CONTROL0_MASK_BASE ((uint8_t)0x42) /*!< Packet control field #3 mask, all 0s -> no filtering */ + +#define PCKT_FLT_GOALS_CONTROL1_MASK_BASE ((uint8_t)0x43) /*!< Packet control field #2 mask, all 0s -> no filtering */ + +#define PCKT_FLT_GOALS_CONTROL2_MASK_BASE ((uint8_t)0x44) /*!< Packet control field #1 mask, all 0s -> no filtering */ + +#define PCKT_FLT_GOALS_CONTROL3_MASK_BASE ((uint8_t)0x45) /*!< Packet control field #0 mask, all 0s -> no filtering */ + +/** + * @} + */ + +/** @defgroup PCKT_FLT_GOALS_CONTROLx_FIELD_Registers + * @{ + */ + +/** + * \brief PCKT_FLT_GOALS_CONTROLx_FIELD registers + * \code + * Default value: 0x00 + * Read Write + * 7:0 CONTROLx_FIELD[7:0]: Control field (byte x) to be used as reference + * + * \endcode + */ +#define PCKT_FLT_GOALS_CONTROL0_FIELD_BASE ((uint8_t)0x46) /*!< Control field (byte #3) */ + +#define PCKT_FLT_GOALS_CONTROL1_FIELD_BASE ((uint8_t)0x47) /*!< Control field (byte #2) */ + +#define PCKT_FLT_GOALS_CONTROL2_FIELD_BASE ((uint8_t)0x48) /*!< Control field (byte #1) */ + +#define PCKT_FLT_GOALS_CONTROL3_FIELD_BASE ((uint8_t)0x49) /*!< Control field (byte #0) */ + +/** + * @} + */ + +/** @defgroup PCKT_FLT_GOALS_SOURCE_MASK_Register + * @{ + */ + +/** + * \brief PCKT_FLT_GOALS_SOURCE_MASK register + * \code + * Default value: 0x00 + * Read Write + * 7:0 RX_SOURCE_MASK[7:0]: For received packet only: all 0s - no filtering + * + * \endcode + */ +#define PCKT_FLT_GOALS_SOURCE_MASK_BASE ((uint8_t)0x4A) /*!< Source address mask, valid in RX mode */ + +/** + * @} + */ + +/** @defgroup PCKT_FLT_GOALS_SOURCE_ADDR_Register + * @{ + */ +/** + * \brief PCKT_FLT_GOALS_SOURCE_ADDR register + * \code + * Default value: 0x00 + * Read Write + * 7:0 RX_SOURCE_ADDR[7:0]: RX packet source / TX packet destination fields + * + * \endcode + */ +#define PCKT_FLT_GOALS_SOURCE_ADDR_BASE ((uint8_t)0x4B) /*!< Source address */ + +/** + * @} + */ + +/** @defgroup PCKT_FLT_GOALS_BROADCAST_Register + * @{ + */ + +/** + * \brief PCKT_FLT_GOALS_BROADCAST register + * \code + * Default value: 0x00 + * Read Write + * 7:0 BROADCAST[7:0]: Address shared for broadcast communication link + * + * \endcode + */ +#define PCKT_FLT_GOALS_BROADCAST_BASE ((uint8_t)0x4C) /*!< Address shared for broadcast communication links */ + +/** + * @} + */ + +/** @defgroup PCKT_FLT_GOALS_MULTICAST_Register + * @{ + */ + +/** + * \brief PCKT_FLT_GOALS_MULTICAST register + * \code + * Default value: 0x00 + * Read Write + * 7:0 MULTICAST[7:0]: Address shared for multicast communication links + * + * \endcode + */ +#define PCKT_FLT_GOALS_MULTICAST_BASE ((uint8_t)0x4D) /*!< Address shared for multicast communication links */ + +/** + * @} + */ + +/** @defgroup PCKT_FLT_GOALS_TX_SOURCE_ADDR_Register + * @{ + */ + +/** + * \brief PCKT_FLT_GOALS_TX_SOURCE_ADDR register + * \code + * Default value: 0x00 + * Read Write + * 7:0 TX_SOURCE_ADDR[7:0]: TX packet source / RX packet destination fields + * + * \endcode + */ +#define PCKT_FLT_GOALS_TX_ADDR_BASE ((uint8_t)0x4E) /*!< Address of the destination (also device own address) */ + +/** + * @} + */ + +/** @defgroup PCKT_FLT_OPTIONS_Register + * @{ + */ + +/** + * \brief PCKT_FLT_OPTIONS register + * \code + * Default value: 0x70 + * Read Write + * 7 Reserved. + * + * 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - ‘OR’ logical function applied to CS/SQI/PQI + * values (masked by 7:5 bits in PROTOCOL register) + * 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control fields matches + * with masked CONTROLx_FIELD registers. + * 4 SOURCE_FILTERING[0]: 1 - RX packet accepted if its source field + * matches w/ masked RX_SOURCE_ADDR register. + * 3 DEST_VS_ SOURCE _ADDR[0]: 1 - RX packet accepted if its destination + * address matches with TX_SOURCE_ADDR reg. + * 2 DEST_VS_MULTICAST_ADDR[0]: 1 - RX packet accepted if its destination + * address matches with MULTICAST register + * 1 DEST_VS_BROADCAST_ADDR[0]: 1 - RX packet accepted if its destination + * address matches with BROADCAST register. + * 0 CRC_CHECK[0]: 1 - packet discarded if CRC not valid. + * + * \endcode + */ +#define PCKT_FLT_OPTIONS_BASE ((uint8_t)0x4F) /*!< Options relative to packet filtering */ + +#define PCKT_FLT_OPTIONS_CRC_CHECK_MASK ((uint8_t)0x01) /*!< Enable/disable of CRC check: packet is discarded if CRC is not valid [RX] */ +#define PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK ((uint8_t)0x02) /*!< Packet discarded if destination address differs from BROADCAST register [RX] */ +#define PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK ((uint8_t)0x04) /*!< Packet discarded if destination address differs from MULTICAST register [RX] */ +#define PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK ((uint8_t)0x08) /*!< Packet discarded if destination address differs from TX_ADDR register [RX] */ +#define PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK ((uint8_t)0x10) /*!< Packet discarded if source address (masked by the SOURCE_MASK register) + differs from SOURCE_ADDR register [RX] */ +#define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20) /*!< Packet discarded if the x-byte (x=1¸4) control field (masked by the CONTROLx_MASK register) + differs from CONTROLx_FIELD register [RX] */ +#define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40) /*!< Logical function applied to CS/SQI/PQI values (masked by [7:5] bits in PROTOCOL[2] + register) */ + +/** + * @} + */ + +/** @defgroup TX_CTRL_FIELD_Registers + * @{ + */ + +/** + * \brief TX_CTRL_FIELDx registers + * \code + * Default value: 0x00 + * Read Write + * 7:0 TX_CTRLx[7:0]: Control field value to be used in TX packet as byte n.x + * \endcode + */ +#define TX_CTRL_FIELD3_BASE ((uint8_t)0x68) /*!< Control field value to be used in TX packet as byte n.3 */ + +#define TX_CTRL_FIELD2_BASE ((uint8_t)0x69) /*!< Control field value to be used in TX packet as byte n.2 */ + +#define TX_CTRL_FIELD1_BASE ((uint8_t)0x6A) /*!< Control field value to be used in TX packet as byte n.1 */ + +#define TX_CTRL_FIELD0_BASE ((uint8_t)0x6B) /*!< Control field value to be used in TX packet as byte n.0 */ + +/** + * @} + */ + + +/** @defgroup TX_PCKT_INFO_Register + * @{ + */ + +/** + * \brief TX_PCKT_INFO registers + * \code + * Default value: 0x00 + * Read + * + * 7:6 Not used. + * + * 5:4 TX_SEQ_NUM: Current TX packet sequence number + * + * 0 N_RETX[3:0]: Number of retransmissions done on the + * last TX packet + * \endcode + */ +#define TX_PCKT_INFO_BASE ((uint8_t)(0xC2)) /*!< Current TX packet sequence number [5:4]; + Number of retransmissions done on the last TX packet [3:0]*/ +/** + * @} + */ + +/** @defgroup RX_PCKT_INFO_Register + * @{ + */ + +/** + * \brief RX_PCKT_INFO registers + * \code + * Default value: 0x00 + * Read + * + * 7:3 Not used. + * + * 2 NACK_RX: NACK field of the received packet + * + * 1:0 RX_SEQ_NUM[1:0]: Sequence number of the received packet + * \endcode + */ +#define RX_PCKT_INFO_BASE ((uint8_t)(0xC3)) /*!< NO_ACK field of the received packet [2]; + sequence number of the received packet [1:0]*/ + +#define TX_PCKT_INFO_NACK_RX ((uint8_t)(0x04)) /*!< NACK field of the received packet */ + +/** + * @} + */ + +/** @defgroup RX_PCKT_LEN1 + * @{ + */ + +/** + * \brief RX_PCKT_LEN1 registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 + * This value is packet_length/256 + * \endcode + */ +#define RX_PCKT_LEN1_BASE ((uint8_t)(0xC9)) /*!< Length (number of bytes) of the received packet: */ + +/** + * @} + */ + +/** @defgroup RX_PCKT_LEN0 + * @{ + */ + +/** + * \brief RX_PCKT_LEN0 registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 + * This value is packet_length%256 + * \endcode + */ +#define RX_PCKT_LEN0_BASE ((uint8_t)(0xCA)) /*!< RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 */ + +/** + * @} + */ + + +/** @defgroup CRC_FIELD_Register + * @{ + */ + +/** + * \brief CRC_FIELD[2:0] registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 CRC_FIELDx[7:0]: upper(x=2), middle(x=1) and lower(x=0) part of the crc field of the received packet + * \endcode + */ +#define CRC_FIELD2_BASE ((uint8_t)(0xCB)) /*!< CRC2 field of the received packet */ + +#define CRC_FIELD1_BASE ((uint8_t)(0xCC)) /*!< CRC1 field of the received packet */ + +#define CRC_FIELD0_BASE ((uint8_t)(0xCD)) /*!< CRC0 field of the received packet */ + +/** + * @} + */ + +/** @defgroup RX_CTRL_FIELD_Register + * @{ + */ + +/** + * \brief RX_CTRL_FIELD[3:0] registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 RX_CTRL_FIELDx[7:0]: upper(x=3), middle(x=2), middle(x=1) and lower(x=0) part of the control field of the received packet + * \endcode + */ +#define RX_CTRL_FIELD0_BASE ((uint8_t)(0xCE)) /*!< CRTL3 Control field of the received packet */ + +#define RX_CTRL_FIELD1_BASE ((uint8_t)(0xCF)) /*!< CRTL2 Control field of the received packet */ + +#define RX_CTRL_FIELD2_BASE ((uint8_t)(0xD0)) /*!< CRTL1 Control field of the received packet */ + +#define RX_CTRL_FIELD3_BASE ((uint8_t)(0xD1)) /*!< CRTL0 Control field of the received packet */ + +/** + * @} + */ + +/** @defgroup RX_ADDR_FIELD_Register + * @{ + */ + +/** + * \brief RX_ADDR_FIELD[1:0] registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 RX_ADDR_FIELDx[7:0]: source(x=1) and destination(x=0) address field of the received packet + * \endcode + */ +#define RX_ADDR_FIELD1_BASE ((uint8_t)(0xD2)) /*!< ADDR1 Address field of the received packet */ + +#define RX_ADDR_FIELD0_BASE ((uint8_t)(0xD3)) /*!< ADDR0 Address field of the received packet */ + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup Protocol_Registers + * @{ + */ + +/** @defgroup PROTOCOL2_Register + * @{ + */ + +/** + * \brief PROTOCOL2 register + * \code + * Default value: 0x06 + * Read Write + * 7 CS_TIMEOUT_MASK: 1 - CS value contributes to timeout disabling + * + * 6 SQI_TIMEOUT_MASK: 1 - SQI value contributes to timeout disabling + * + * 5 PQI_TIMEOUT_MASK: 1 - PQI value contributes to timeout disabling + * + * 4:3 TX_SEQ_NUM_RELOAD[1:0]: TX sequence number to be used when counting reset is required using the related command. + * + * 2 RCO_CALIBRATION[0]: 1 - Enables the automatic RCO calibration + * + * 1 VCO_CALIBRATION[0]: 1 - Enables the automatic VCO calibration + * + * 0 LDCR_MODE[0]: 1 - LDCR mode enabled + * + * \endcode + */ +#define PROTOCOL2_BASE ((uint8_t)0x50) /*!< Protocol2 regisetr address */ + +#define PROTOCOL2_LDC_MODE_MASK ((uint8_t)0x01) /*!< Enable/disable Low duty Cycle mode */ +#define PROTOCOL2_VCO_CALIBRATION_MASK ((uint8_t)0x02) /*!< Enable/disable VCO automatic calibration */ +#define PROTOCOL2_RCO_CALIBRATION_MASK ((uint8_t)0x04) /*!< Enable/disable RCO automatic calibration */ +#define PROTOCOL2_PQI_TIMEOUT_MASK ((uint8_t)0x20) /*!< PQI value contributes to timeout disabling */ +#define PROTOCOL2_SQI_TIMEOUT_MASK ((uint8_t)0x40) /*!< SQI value contributes to timeout disabling */ +#define PROTOCOL2_CS_TIMEOUT_MASK ((uint8_t)0x80) /*!< CS value contributes to timeout disabling */ + +/** + * @} + */ + +/** @defgroup PROTOCOL1_Register + * @{ + */ + +/** + * \brief PROTOCOL1 register + * \code + * Default value: 0x00 + * Read Write + * 7 LDCR_RELOAD_ON_SYNC: 1 - LDCR timer will be reloaded with the value stored in the LDCR_RELOAD registers + * + * 6 PIGGYBACKING: 1 - PIGGYBACKING enabled + * + * 5:4 Reserved. + * + * 3 SEED_RELOAD[0]: 1 - Reload the back-off random generator + * seed using the value written in the + * BU_COUNTER_SEED_MSByte / LSByte registers + * + * 2 CSMA_ON [0]: 1 - CSMA channel access mode enabled + * + * 1 CSMA_PERS_ON[0]: 1 - CSMA persistent (no back-off) enabled + * + * 0 AUTO_PCKT_FLT[0]: 1 - automatic packet filtering mode enabled + * + * \endcode + */ +#define PROTOCOL1_BASE ((uint8_t)0x51) /*!< Protocol1 regisetr address */ + +#define PROTOCOL1_AUTO_PCKT_FLT_MASK ((uint8_t)0x01) /*!< Enable/disable automatic packet filtering mode */ +#define PROTOCOL1_CSMA_PERS_ON_MASK ((uint8_t)0x02) /*!< Enable/disable CSMA persistent (no back-off) */ +#define PROTOCOL1_CSMA_ON_MASK ((uint8_t)0x04) /*!< Enable/disable CSMA channel access mode */ +#define PROTOCOL1_SEED_RELOAD_MASK ((uint8_t)0x08) /*!< Reloads the seed of the PN generator for CSMA procedure */ +#define PROTOCOL1_PIGGYBACKING_MASK ((uint8_t)0x40) /*!< Enable/disable Piggybacking */ +#define PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK ((uint8_t)0x80) /*!< LDC timer will be reloaded with the value stored in the LDC_RELOAD registers */ + +/** + * @} + */ + +/** @defgroup PROTOCOL0_Register + * @{ + */ + +/** + * \brief PROTOCOL0 register + * \code + * Default value: 0x08 + * Read Write + * 7:4 NMAX_RETX[3:0]: Max number of re-TX. 0 - re-transmission is not performed + * + * 3 NACK_TX[0]: 1 - field NO_ACK=1 on transmitted packet + * + * 2 AUTO_ACK[0]: 1 - automatic ack after RX + * + * 1 PERS_RX[0]: 1 - persistent reception enabled + * + * 0 PERS_TX[0]: 1 - persistent transmission enabled + * + * \endcode + */ +#define PROTOCOL0_BASE ((uint8_t)0x52) /*!< Persistent RX/TX, autoack, Max number of retransmissions */ + +#define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /*!< Enables persistent transmission */ +#define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /*!< Enables persistent reception */ +#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /*!< Enables auto acknowlegment */ +#define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /*!< Writes field NO_ACK=1 on transmitted packet */ +#define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xF0) /*!< Retransmission mask */ + +/** + * @} + */ + +/** @defgroup TIMERS5_Register + * @{ + */ + +/** + * \brief TIMERS5 register + * \code + * Default value: 0x00 + * Read Write + * 7:0 RX_TIMEOUT_PRESCALER[7:0] : RX operation timeout: prescaler value + * \endcode + */ +#define TIMERS5_RX_TIMEOUT_PRESCALER_BASE ((uint8_t)0x53) /*!< RX operation timeout: prescaler value */ + +/** + * @} + */ + +/** @defgroup TIMERS4_Register + * @{ + */ + +/** + * \brief TIMERS4 register + * \code + * Default value: 0x00 + * Read Write + * 7:0 RX_TIMEOUT_COUNTER[7:0] : RX operation timeout: counter value + * \endcode + */ +#define TIMERS4_RX_TIMEOUT_COUNTER_BASE ((uint8_t)0x54) /*!< RX operation timeout: counter value */ + +/** + * @} + */ + +/** @defgroup TIMERS3_Register + * @{ + */ + +/** + * \brief TIMERS3 register + * \code + * Default value: 0x00 + * Read Write + * 7:0 LDCR_PRESCALER[7:0] : LDC Mode: Prescaler part of the wake-up value + * \endcode + */ +#define TIMERS3_LDC_PRESCALER_BASE ((uint8_t)0x55) /*!< LDC Mode: Prescaler of the wake-up timer */ + +/** + * @} + */ + +/** @defgroup TIMERS2_Register + * @{ + */ + +/** + * \brief TIMERS2 register + * \code + * Default value: 0x00 + * Read Write + * 7:0 LDCR_COUNTER[7:0] : LDC Mode: counter part of the wake-up value + * \endcode + */ +#define TIMERS2_LDC_COUNTER_BASE ((uint8_t)0x56) /*!< LDC Mode: counter of the wake-up timer */ + +/** + * @} + */ + +/** @defgroup TIMERS1_Register + * @{ + */ + +/** + * \brief TIMERS1 register + * \code + * Default value: 0x00 + * Read Write + * 7:0 LDCR_RELOAD_PRESCALER[7:0] : LDC Mode: Prescaler part of the reload value + * \endcode + */ +#define TIMERS1_LDC_RELOAD_PRESCALER_BASE ((uint8_t)0x57) /*!< LDC Mode: Prescaler part of the reload value */ + +/** + * @} + */ + +/** @defgroup TIMERS0_Register + * @{ + */ + +/** + * \brief TIMERS0 register + * \code + * Default value: 0x00 + * Read Write + * 7:0 LDCR_RELOAD_COUNTER[7:0] : LDC Mode: Counter part of the reload value + * \endcode + */ +#define TIMERS0_LDC_RELOAD_COUNTER_BASE ((uint8_t)0x58) /*!< LDC Mode: Counter part of the reload value */ + +/** + * @} + */ + + +/** @defgroup CSMA_CONFIG3_Register + * @{ + */ + +/** + * \brief CSMA_CONFIG3 registers + * \code + * Default value: 0xFF + * Read Write + * 7:0 BU_COUNTER_SEED_MSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) + * \endcode + */ +#define CSMA_CONFIG3_BASE ((uint8_t)0x64) /*!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) */ + +/** + * @} + */ + +/** @defgroup CSMA_CONFIG2_Register + * @{ + */ + +/** + * \brief CSMA_CONFIG2 registers + * \code + * Default value: 0x00 + * Read Write + * 7:0 BU_COUNTER_SEED_LSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) + * \endcode + */ +#define CSMA_CONFIG2_BASE ((uint8_t)0x65) /*!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) */ + +/** + * @} + */ + +/** @defgroup CSMA_CONFIG1_Register + * @{ + */ + +/** + * \brief CSMA_CONFIG1 registers + * \code + * Default value: 0x04 + * Read Write + * 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU + * + * 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time (64 / 128 /256 / 512 × Tbit. + * \endcode + */ +#define CSMA_CONFIG1_BASE ((uint8_t)0x66) /*!< CSMA/CA: Prescaler of the back-off time unit (BU); CCA period */ + +#define CSMA_CCA_PERIOD_64TBIT ((uint8_t)0x00) /*!< CSMA/CA: Sets CCA period to 64*TBIT */ +#define CSMA_CCA_PERIOD_128TBIT ((uint8_t)0x01) /*!< CSMA/CA: Sets CCA period to 128*TBIT */ +#define CSMA_CCA_PERIOD_256TBIT ((uint8_t)0x02) /*!< CSMA/CA: Sets CCA period to 256*TBIT */ +#define CSMA_CCA_PERIOD_512TBIT ((uint8_t)0x03) /*!< CSMA/CA: Sets CCA period to 512*TBIT */ + +/** + * @} + */ + +/** @defgroup CSMA_CONFIG0_Register + * @{ + */ + +/** + * \brief CSMA_CONFIG0 registers + * \code + * Default value: 0x00 + * Read Write + * 7:4 CCA_LENGTH[3:0]: Used to program the Tlisten time + * + * 3 Reserved. + * + * 2:0 NBACKOFF_MAX[2:0]: Max number of back-off cycles. + * \endcode + */ +#define CSMA_CONFIG0_BASE ((uint8_t)0x67) /*!< CSMA/CA: CCA lenght; Max number of backoff cycles */ + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup Link_Quality_Registers + * @{ + */ + +/** @defgroup QI_Register + * @{ + */ + +/** + * \brief QI register + * \code + * Read Write + * Default value: 0x02 + * + * 7:6 SQI_TH[1:0]: SQI threshold according to the formula: 8*SYNC_LEN - 2*SQI_TH + * + * 5:2 PQI_TH[3:0]: PQI threshold according to the formula: 4*PQI_THR + * + * + * 1 SQI_EN[0]: SQI enable + * 1 - Enable + * 0 - Disable + * + * 0 PQI_EN[0]: PQI enable + * 1 - Enable + * 0 - Disable + * \endcode + */ +#define QI_BASE ((uint8_t)0x3A) /*!< QI register */ + +#define QI_PQI_MASK ((uint8_t)0x01) /*!< PQI enable/disable */ +#define QI_SQI_MASK ((uint8_t)0x02) /*!< SQI enable/disable */ + +/** + * @} + */ + +/** @defgroup LINK_QUALIF2 + * @{ + */ + +/** + * \brief LINK_QUALIF2 registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 PQI[7:0]: PQI value of the received packet + * \endcode + */ +#define LINK_QUALIF2_BASE ((uint8_t)(0xC5)) /*!< PQI value of the received packet */ + +/** + * @} + */ + +/** @defgroup LINK_QUALIF1 + * @{ + */ + +/** + * \brief LINK_QUALIF1 registers + * \code + * Default value: 0x00 + * Read + * + * 7 CS: Carrier Sense indication + * + * 6:0 SQI[6:0]: SQI value of the received packet + * \endcode + */ +#define LINK_QUALIF1_BASE ((uint8_t)(0xC6)) /*!< Carrier sense indication [7]; SQI value of the received packet */ + +#define LINK_QUALIF1_CS ((uint8_t)(0x80)) /*!< Carrier sense indication [7] */ + +/** + * @} + */ + +/** @defgroup LINK_QUALIF0 + * @{ + */ + +/** + * \brief LINK_QUALIF0 registers + * \code + * Default value: 0x00 + * Read + * + * 7:4 LQI [3:0]: LQI value of the received packet + * + * 3:0 AGC_WORD[3:0]: AGC word of the received packet + * \endcode + */ +#define LINK_QUALIF0_BASE ((uint8_t)(0xC7)) /*!< LQI value of the received packet [7:4]; AGC word of the received packet [3:0] */ + +/** + * @} + */ + +/** @defgroup RSSI_LEVEL + * @{ + */ + +/** + * \brief RSSI_LEVEL registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 RSSI_LEVEL[7:0]: RSSI level of the received packet + * \endcode + */ +#define RSSI_LEVEL_BASE ((uint8_t)(0xC8)) /*!< RSSI level of the received packet */ + +/** + * @} + */ + +/** @defgroup RSSI_FLT_Register + * @{ + */ + +/** + * \brief RSSI register + * \code + * Read Write + * Default value: 0xF3 + * 7:4 RSSI_FLT[3:0]: Gain of the RSSI filter + * + * 3:2 CS_MODE[1:0]: AFC loop gain in slow mode (2's log) + * + * CS_MODE1 | CS_MODE0 | CS Mode + * ----------------------------------------------------------------------------------------- + * 0 | 0 | Static CS + * 0 | 1 | Dynamic CS with 6dB dynamic threshold + * 1 | 0 | Dynamic CS with 12dB dynamic threshold + * 1 | 1 | Dynamic CS with 18dB dynamic threshold + * + * 1:0 OOK_PEAK_DECAY[1:0]: Peak decay control for OOK: 3 slow decay; 0 fast decay + * + * \endcode + */ +#define RSSI_FLT_BASE ((uint8_t)0x21) /*!< Gain of the RSSI filter; lower value is fast but inaccurate, + higher value is slow and more accurate */ +#define RSSI_FLT_CS_MODE_MASK ((uint8_t)0x0C) /*!< Carrier sense mode mask */ +#define RSSI_FLT_CS_MODE_STATIC ((uint8_t)0x00) /*!< Carrier sense mode; static carrier sensing */ +#define RSSI_FLT_CS_MODE_DYNAMIC_6 ((uint8_t)0x04) /*!< Carrier sense mode; dynamic carrier sensing with 6dB threshold */ +#define RSSI_FLT_CS_MODE_DYNAMIC_12 ((uint8_t)0x08) /*!< Carrier sense mode; dynamic carrier sensing with 12dB threshold */ +#define RSSI_FLT_CS_MODE_DYNAMIC_18 ((uint8_t)0x0C) /*!< Carrier sense mode; dynamic carrier sensing with 18dB threshold */ +#define RSSI_FLT_OOK_PEAK_DECAY_MASK ((uint8_t)0x03) /*!< Peak decay control for OOK mask */ +#define RSSI_FLT_OOK_PEAK_DECAY_FAST ((uint8_t)0x00) /*!< Peak decay control for OOK: fast decay */ +#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_FAST ((uint8_t)0x01) /*!< Peak decay control for OOK: medium_fast decay */ +#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_SLOW ((uint8_t)0x02) /*!< Peak decay control for OOK: medium_fast decay */ +#define RSSI_FLT_OOK_PEAK_DECAY_SLOW ((uint8_t)0x03) /*!< Peak decay control for OOK: slow decay */ + +/** + * @} + */ + +/** @defgroup RSSI_TH_Register + * @{ + */ + +/** + * \brief RSSI_TH register + * \code + * Read Write + * Default value: 0x24 + * + * 7:0 RSSI_THRESHOLD [7:0]: Signal detect threshold in 0.5dB. -120dBm corresponds to 20 + * \endcode + */ +#define RSSI_TH_BASE ((uint8_t)0x22) /*!< Signal detect threshold in 0.5dB stp. 20 correspond to -120 dBm */ + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FIFO_Registers + * @{ + */ + +/** @defgroup FIFO_CONFIG3_Register + * @{ + */ + +/** + * \brief FIFO_CONFIG3 registers + * \code + * Default value: 0x30 + * Read Write + * 7 Reserved. + * + * 6:0 rxafthr [6:0]: FIFO Almost Full threshold for rx fifo. + * + * \endcode + */ +#define FIFO_CONFIG3_RXAFTHR_BASE ((uint8_t)0x3E) /*!< FIFO Almost Full threshold for rx fifo [6:0] */ + +/** + * @} + */ + +/** @defgroup FIFO_CONFIG2_Register + * @{ + */ + +/** + * \brief FIFO_CONFIG2 registers + * \code + * Default value: 0x30 + * Read Write + * 7 Reserved. + * + * 6:0 rxaethr [6:0]: FIFO Almost Empty threshold for rx fifo. + * + * \endcode + */ +#define FIFO_CONFIG2_RXAETHR_BASE ((uint8_t)0x3F) /*!< FIFO Almost Empty threshold for rx fifo [6:0] */ + +/** + * @} + */ + +/** @defgroup FIFO_CONFIG1_Register + * @{ + */ + +/** + * \brief FIFO_CONFIG1 registers + * \code + * Default value: 0x30 + * Read Write + * 7 Reserved. + * + * 6:0 txafthr [6:0]: FIFO Almost Full threshold for tx fifo. + * + * \endcode + */ +#define FIFO_CONFIG1_TXAFTHR_BASE ((uint8_t)0x40) /*!< FIFO Almost Full threshold for tx fifo [6:0] */ + +/** + * @} + */ + +/** @defgroup FIFO_CONFIG0_Register + * @{ + */ + +/** + * \brief FIFO_CONFIG0 registers + * \code + * Default value: 0x30 + * Read Write + * 7 Reserved. + * + * 6:0 txaethr [6:0]: FIFO Almost Empty threshold for tx fifo. + * + * \endcode + */ +#define FIFO_CONFIG0_TXAETHR_BASE ((uint8_t)0x41) /*!< FIFO Almost Empty threshold for tx fifo [6:0] */ + +/** + * @} + */ + +/** @defgroup LINEAR_FIFO_STATUS1_Register + * @{ + */ + +/** + * \brief LINEAR_FIFO_STATUS1 registers + * \code + * Default value: 0x00 + * Read + * + * 7 Reserved. + * + * 6:0 elem_txfifo[6:0]: Number of elements in the linear TXFIFO (<=96) + * \endcode + */ +#define LINEAR_FIFO_STATUS1_BASE ((uint8_t)(0xE6)) /*!< Number of elements in the linear TX FIFO [6:0] (<=96) */ + +/** + * @} + */ + +/** @defgroup LINEAR_FIFO_STATUS0_Register + * @{ + */ + +/** + * \brief LINEAR_FIFO_STATUS0 registers + * \code + * Default value: 0x00 + * Read + * + * 7 Reserved. + * + * 6:0 elem_rxfifo[6:0]: Number of elements in the linear RXFIFO (<=96) + * \endcode + */ +#define LINEAR_FIFO_STATUS0_BASE ((uint8_t)(0xE7)) /*!< Number of elements in the linear RX FIFO [6:0] (<=96) */ + +/** + * @} + */ + + +/** + * @} + */ + + +/** @defgroup Calibration_Registers + * @{ + */ + +/** @defgroup RCO_VCO_CALIBR_IN2_Register + * @{ + */ + +/** + * \brief RCO_VCO_CALIBR_IN2 registers + * \code + * Default value: 0x70 + * Read Write + * 7:4 RWT_IN[3:0]: RaWThermometric word value for the RCO [7:4] + * + * 3:0 RFB_IN[4:1]: ResistorFineBit word value for the RCO (first 4 bits) + * \endcode + */ +#define RCO_VCO_CALIBR_IN2_BASE ((uint8_t)0x6D) /*!< RaWThermometric word value for the RCO [7:4]; ResistorFineBit word value for the RCO [3:0] */ + +/** + * @} + */ + +/** @defgroup RCO_VCO_CALIBR_IN1_Register + * @{ + */ + +/** + * \brief RCO_VCO_CALIBR_IN1 registers + * \code + * Default value: 0x48 + * Read Write + * + * 7 RFB_IN[0]: ResistorFineBit word value for the RCO (LSb) + * + * 6:0 VCO_CALIBR_TX[6:0]: Word value for the VCO to be used in TX mode + * \endcode + */ +#define RCO_VCO_CALIBR_IN1_BASE ((uint8_t)0x6E) /*!< ResistorFineBit word value for the RCO [7]; Word value for the VCO to be used in TX mode [6:0]*/ + +/** + * @} + */ + +/** @defgroup RCO_VCO_CALIBR_IN0_Register + * @{ + */ + +/** + * \brief RCO_VCO_CALIBR_IN0 registers + * \code + * Default value: 0x48 + * Read Write + * + * 7 Reserved. + * + * 6:0 VCO_CALIBR_RX[6:0]: Word value for the VCO to be used in RX mode + * \endcode + */ +#define RCO_VCO_CALIBR_IN0_BASE ((uint8_t)0x6F) /*!< Word value for the VCO to be used in RX mode [6:0] */ + +/** + * @} + */ + +/** @defgroup RCO_VCO_CALIBR_OUT1_Register + * @{ + */ + +/** + * \brief RCO_VCO_CALIBR_OUT1 registers + * \code + * Default value: 0x00 + * Read + * + * 7:4 RWT_OUT[3:0]: RWT word from internal RCO calibrator + * + * 3:0 RFB_OUT[4:1]: RFB word from internal RCO calibrator (upper part) + * \endcode + */ +#define RCO_VCO_CALIBR_OUT1_BASE ((uint8_t)(0xE4)) /*!< RaWThermometric RWT word from internal RCO calibrator [7]; + ResistorFineBit RFB word from internal RCO oscillator [6:0] */ +/** + * @} + */ + +/** @defgroup RCO_VCO_CALIBR_OUT0_Register + * @{ + */ + +/** + * \brief RCO_VCO_CALIBR_OUT0 registers + * \code + * Default value: 0x00 + * Read + * + * 7 RFB_OUT[0]: RFB word from internal RCO calibrator (last bit LSB) + * + * 6:0 VCO_CALIBR_DATA[6:0]: Output word from internal VCO calibrator + * \endcode + */ +#define RCO_VCO_CALIBR_OUT0_BASE ((uint8_t)(0xE5)) /*!< ResistorFineBit RFB word from internal RCO oscillator [0]; + Output word from internal calibrator [6:0]; */ +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup AES_Registers + * @{ + */ + +/** @defgroup AES_KEY_IN_Register + * @{ + */ + +/** + * \brief AES_KEY_INx registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 AES_KEY_INx[7:0]: AES engine key input (total - 128 bits) + * \endcode + */ +#define AES_KEY_IN_15_BASE ((uint8_t)0x70) /*!< AES engine key input 15 */ + +#define AES_KEY_IN_14_BASE ((uint8_t)0x71) /*!< AES engine key input 14 */ + +#define AES_KEY_IN_13_BASE ((uint8_t)0x72) /*!< AES engine key input 13 */ + +#define AES_KEY_IN_12_BASE ((uint8_t)0x73) /*!< AES engine key input 12 */ + +#define AES_KEY_IN_11_BASE ((uint8_t)0x74) /*!< AES engine key input 11 */ + +#define AES_KEY_IN_10_BASE ((uint8_t)0x75) /*!< AES engine key input 10 */ + +#define AES_KEY_IN_9_BASE ((uint8_t)0x76) /*!< AES engine key input 9 */ + +#define AES_KEY_IN_8_BASE ((uint8_t)0x77) /*!< AES engine key input 8 */ + +#define AES_KEY_IN_7_BASE ((uint8_t)0x78) /*!< AES engine key input 7 */ + +#define AES_KEY_IN_6_BASE ((uint8_t)0x79) /*!< AES engine key input 6 */ + +#define AES_KEY_IN_5_BASE ((uint8_t)0x7A) /*!< AES engine key input 5 */ + +#define AES_KEY_IN_4_BASE ((uint8_t)0x7B) /*!< AES engine key input 4 */ + +#define AES_KEY_IN_3_BASE ((uint8_t)0x7C) /*!< AES engine key input 3 */ + +#define AES_KEY_IN_2_BASE ((uint8_t)0x7D) /*!< AES engine key input 2 */ + +#define AES_KEY_IN_1_BASE ((uint8_t)0x7E) /*!< AES engine key input 1 */ + +#define AES_KEY_IN_0_BASE ((uint8_t)0x7F) /*!< AES engine key input 0 */ + +/** + * @} + */ + +/** @defgroup AES_DATA_IN_Register + * @{ + */ + +/** + * \brief AES_DATA_INx registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 AES_DATA_INx[7:0]: AES engine data input (total - 128 bits) + * \endcode + */ +#define AES_DATA_IN_15_BASE ((uint8_t)0x80) /*!< AES engine data input 15 + Take care: Address is in reverse order respect data numbering; eg.: 0x81 -> AES_data14[7:0] */ +#define AES_DATA_IN_14_BASE ((uint8_t)0x81) /*!< AES engine data input 14 */ + +#define AES_DATA_IN_13_BASE ((uint8_t)0x82) /*!< AES engine data input 13 */ + +#define AES_DATA_IN_12_BASE ((uint8_t)0x83) /*!< AES engine data input 12 */ + +#define AES_DATA_IN_11_BASE ((uint8_t)0x84) /*!< AES engine data input 11 */ + +#define AES_DATA_IN_10_BASE ((uint8_t)0x85) /*!< AES engine data input 10 */ + +#define AES_DATA_IN_9_BASE ((uint8_t)0x86) /*!< AES engine data input 9 */ + +#define AES_DATA_IN_8_BASE ((uint8_t)0x87) /*!< AES engine data input 8 */ + +#define AES_DATA_IN_7_BASE ((uint8_t)0x88) /*!< AES engine data input 7 */ + +#define AES_DATA_IN_6_BASE ((uint8_t)0x89) /*!< AES engine data input 6 */ + +#define AES_DATA_IN_5_BASE ((uint8_t)0x8A) /*!< AES engine data input 5 */ + +#define AES_DATA_IN_4_BASE ((uint8_t)0x8B) /*!< AES engine data input 4 */ + +#define AES_DATA_IN_3_BASE ((uint8_t)0x8C) /*!< AES engine data input 3 */ + +#define AES_DATA_IN_2_BASE ((uint8_t)0x8D) /*!< AES engine data input 2 */ + +#define AES_DATA_IN_1_BASE ((uint8_t)0x8E) /*!< AES engine data input 1 */ + +#define AES_DATA_IN_0_BASE ((uint8_t)0x8F) /*!< AES engine data input 0 */ + +/** + * @} + */ + +/** @defgroup AES_DATA_OUT_Register + * @{ + */ + +/** + * \brief AES_DATA_OUT[15:0] registers + * \code + * Default value: 0x00 + * Read + * + * 7:0 AES_DATA_OUTx[7:0]: AES engine data output (128 bits) + * \endcode + */ +#define AES_DATA_OUT_15_BASE ((uint8_t)(0xD4)) /*!< AES engine data output 15 */ + +#define AES_DATA_OUT_14_BASE ((uint8_t)(0xD5)) /*!< AES engine data output 14 */ + +#define AES_DATA_OUT_13_BASE ((uint8_t)(0xD6)) /*!< AES engine data output 13 */ + +#define AES_DATA_OUT_12_BASE ((uint8_t)(0xD7)) /*!< AES engine data output 12 */ + +#define AES_DATA_OUT_11_BASE ((uint8_t)(0xD8)) /*!< AES engine data output 11 */ + +#define AES_DATA_OUT_10_BASE ((uint8_t)(0xD9)) /*!< AES engine data output 10 */ + +#define AES_DATA_OUT_9_BASE ((uint8_t)(0xDA)) /*!< AES engine data output 9 */ + +#define AES_DATA_OUT_8_BASE ((uint8_t)(0xDB)) /*!< AES engine data output 8 */ + +#define AES_DATA_OUT_7_BASE ((uint8_t)(0xDC)) /*!< AES engine data output 7 */ + +#define AES_DATA_OUT_6_BASE ((uint8_t)(0xDD)) /*!< AES engine data output 6 */ + +#define AES_DATA_OUT_5_BASE ((uint8_t)(0xDE)) /*!< AES engine data output 5 */ + +#define AES_DATA_OUT_4_BASE ((uint8_t)(0xDF)) /*!< AES engine data output 4 */ + +#define AES_DATA_OUT_3_BASE ((uint8_t)(0xE0)) /*!< AES engine data output 3 */ + +#define AES_DATA_OUT_2_BASE ((uint8_t)(0xE1)) /*!< AES engine data output 2 */ + +#define AES_DATA_OUT_1_BASE ((uint8_t)(0xE2)) /*!< AES engine data output 1 */ + +#define AES_DATA_OUT_0_BASE ((uint8_t)(0xE3)) /*!< AES engine data output 0 */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IRQ_Registers + * @{ + */ + +/** @defgroup IRQ_MASK0_Register + * @{ + */ + +/** + * \brief IRQ_MASK0 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_MASK0: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 0 | RX data ready + * 1 | RX data discarded (upon filtering) + * 2 | TX data sent + * 3 | Max re-TX reached + * 4 | CRC error + * 5 | TX FIFO underflow/overflow error + * 6 | RX FIFO underflow/overflow error + * 7 | TX FIFO almost full + * \endcode + */ + + +#define IRQ_MASK0_BASE ((uint8_t)0x93) /*!< IRQ_MASK is split into 4 registers*/ + +#define IRQ_MASK0_RX_DATA_READY ((uint8_t)0x01) /*!< IRQ: RX data ready */ +#define IRQ_MASK0_RX_DATA_DISC ((uint8_t)0x02) /*!< IRQ: RX data discarded (upon filtering) */ +#define IRQ_MASK0_TX_DATA_SENT ((uint8_t)0x04) /*!< IRQ: TX data sent */ +#define IRQ_MASK0_MAX_RE_TX_REACH ((uint8_t)0x08) /*!< IRQ: Max re-TX reached */ +#define IRQ_MASK0_CRC_ERROR ((uint8_t)0x10) /*!< IRQ: CRC error */ +#define IRQ_MASK0_TX_FIFO_ERROR ((uint8_t)0x20) /*!< IRQ: TX FIFO underflow/overflow error */ +#define IRQ_MASK0_RX_FIFO_ERROR ((uint8_t)0x40) /*!< IRQ: RX FIFO underflow/overflow error */ +#define IRQ_MASK0_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /*!< IRQ: TX FIFO almost full */ + +/** + * @} + */ + +/** @defgroup IRQ_MASK1_Register + * @{ + */ + +/** + * \brief IRQ_MASK1 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_MASK1: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 8 | TX FIFO almost empty + * 9 | RX FIFO almost full + * 10 | RX FIFO almost empty + * 11 | Max number of back-off during CCA + * 12 | Valid preamble detected + * 13 | Sync word detected + * 14 | RSSI above threshold (Carrier Sense) + * 15 | Wake-up timeout in LDCR mode13 + * \endcode + */ + +#define IRQ_MASK1_BASE ((uint8_t)0x92) /*!< IRQ_MASK is split into 4 registers*/ + +#define IRQ_MASK1_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /*!< IRQ: TX FIFO almost empty */ +#define IRQ_MASK1_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /*!< IRQ: RX FIFO almost full */ +#define IRQ_MASK1_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /*!< IRQ: RX FIFO almost empty */ +#define IRQ_MASK1_MAX_BO_CCA_REACH ((uint8_t)0x08) /*!< IRQ: Max number of back-off during CCA */ +#define IRQ_MASK1_VALID_PREAMBLE ((uint8_t)0x10) /*!< IRQ: Valid preamble detected */ +#define IRQ_MASK1_VALID_SYNC ((uint8_t)0x20) /*!< IRQ: Sync word detected */ +#define IRQ_MASK1_RSSI_ABOVE_TH ((uint8_t)0x40) /*!< IRQ: RSSI above threshold */ +#define IRQ_MASK1_WKUP_TOUT_LDC ((uint8_t)0x80) /*!< IRQ: Wake-up timeout in LDC mode */ + +/** + * @} + */ + +/** @defgroup IRQ_MASK2_Register + * @{ + */ + +/** + * \brief IRQ_MASK2 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_MASK2: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 16 | READY state in steady condition14 + * 17 | STANDBY state switching in progress + * 18 | Low battery level + * 19 | Power-On reset + * 20 | Brown-Out event + * 21 | LOCK state in steady condition + * 22 | PM start-up timer expiration + * 23 | XO settling timeout + * \endcode + */ +#define IRQ_MASK2_BASE ((uint8_t)0x91) /*!< IRQ_MASK is split into 4 registers*/ + +#define IRQ_MASK2_READY ((uint8_t)0x01) /*!< IRQ: READY state */ +#define IRQ_MASK2_STANDBY_DELAYED ((uint8_t)0x02) /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ +#define IRQ_MASK2_LOW_BATT_LVL ((uint8_t)0x04) /*!< IRQ: Battery level below threshold*/ +#define IRQ_MASK2_POR ((uint8_t)0x08) /*!< IRQ: Power On Reset */ +#define IRQ_MASK2_BOR ((uint8_t)0x10) /*!< IRQ: Brown out event (both accurate and inaccurate)*/ +#define IRQ_MASK2_LOCK ((uint8_t)0x20) /*!< IRQ: LOCK state */ +#define IRQ_MASK2_PM_COUNT_EXPIRED ((uint8_t)0x40) /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ +#define IRQ_MASK2_XO_COUNT_EXPIRED ((uint8_t)0x80) /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ + +/** + * @} + */ + +/** @defgroup IRQ_MASK3_Register + * @{ + */ + +/** + * \brief IRQ_MASK3 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_MASK3: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 24 | SYNTH locking timeout + * 25 | SYNTH calibration start-up time + * 26 | SYNTH calibration timeout + * 27 | TX circuitry start-up time + * 28 | RX circuitry start-up time + * 29 | RX operation timeout + * 30 | Others AES End–of –Operation + * 31 | Reserved + * \endcode + */ +#define IRQ_MASK3_BASE ((uint8_t)0x90) /*!< IRQ_MASK is split into 4 registers*/ + +#define IRQ_MASK3_SYNTH_LOCK_TIMEOUT ((uint8_t)0x01) /*!< IRQ: only for debug; LOCK state timeout */ +#define IRQ_MASK3_SYNTH_LOCK_STARTUP ((uint8_t)0x02) /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ +#define IRQ_MASK3_SYNTH_CAL_TIMEOUT ((uint8_t)0x04) /*!< IRQ: only for debug; SYNTH calibration timeout */ +#define IRQ_MASK3_TX_START_TIME ((uint8_t)0x08) /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ +#define IRQ_MASK3_RX_START_TIME ((uint8_t)0x10) /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ +#define IRQ_MASK3_RX_TIMEOUT ((uint8_t)0x20) /*!< IRQ: RX operation timeout */ +#define IRQ_MASK3_AES_END ((uint8_t)0x40) /*!< IRQ: AES End of operation */ + +/** + * @} + */ + + +/** @defgroup IRQ_STATUS0_Register + * @{ + */ + +/** + * \brief IRQ_STATUS0 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_STATUS0: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 0 | RX data ready + * 1 | RX data discarded (upon filtering) + * 2 | TX data sent + * 3 | Max re-TX reached + * 4 | CRC error + * 5 | TX FIFO underflow/overflow error + * 6 | RX FIFO underflow/overflow error + * 7 | TX FIFO almost full + * \endcode + */ + +#define IRQ_STATUS0_BASE ((uint8_t)(0xFD)) /*!< IRQ Events(RR, split into 4 registers) */ + +#define IRQ_STATUS0_SYNTH_LOCK_TIMEOUT ((uint8_t)(0x01)) /*!< IRQ: LOCK state timeout */ +#define IRQ_STATUS0_SYNTH_LOCK_STARTUP ((uint8_t)(0x02)) /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ +#define IRQ_STATUS0_SYNTH_CAL_TIMEOUT ((uint8_t)(0x04)) /*!< IRQ: SYNTH locking timeout */ +#define IRQ_STATUS0_TX_START_TIME ((uint8_t)(0x08)) /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ +#define IRQ_STATUS0_RX_START_TIME ((uint8_t)(0x10)) /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ +#define IRQ_STATUS0_RX_TIMEOUT ((uint8_t)(0x20)) /*!< IRQ: RX operation timeout expiration */ +#define IRQ_STATUS0_AES_END ((uint8_t)(0x40)) /*!< IRQ: AES End of operation */ + +/** + * @} + */ + +/** @defgroup IRQ_STATUS1_Register + * @{ + */ + +/** + * \brief IRQ_STATUS1 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_STATUS1: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 8 | TX FIFO almost empty + * 9 | RX FIFO almost full + * 10 | RX FIFO almost empty + * 11 | Max number of back-off during CCA + * 12 | Valid preamble detected + * 13 | Sync word detected + * 14 | RSSI above threshold (Carrier Sense) + * 15 | Wake-up timeout in LDCR mode13 + * \endcode + */ + +#define IRQ_STATUS1_BASE ((uint8_t)(0xFC)) /*!< IRQ Events(RR, split into 4 registers) */ + +#define IRQ_STATUS1_READY ((uint8_t)(0x01)) /*!< IRQ: READY state in steady condition*/ +#define IRQ_STATUS1_STANDBY_DELAYED ((uint8_t)(0x02)) /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ +#define IRQ_STATUS1_LOW_BATT_LVL ((uint8_t)(0x04)) /*!< IRQ: Battery level below threshold*/ +#define IRQ_STATUS1_POR ((uint8_t)(0x08)) /*!< IRQ: Power On Reset */ +#define IRQ_STATUS1_BOR ((uint8_t)(0x10)) /*!< IRQ: Brown out event (both accurate and inaccurate)*/ +#define IRQ_STATUS1_LOCK ((uint8_t)(0x20)) /*!< IRQ: LOCK state in steady condition */ +#define IRQ_STATUS1_PM_COUNT_EXPIRED ((uint8_t)(0x40)) /*!< IRQ: Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ +#define IRQ_STATUS1_XO_COUNT_EXPIRED ((uint8_t)(0x80)) /*!< IRQ: Crystal oscillator settling time counter expired */ + +/** + * @} + */ + +/** @defgroup IRQ_STATUS2_Register + * @{ + */ + +/** + * \brief IRQ_STATUS2 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_STATUS2: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 16 | READY state in steady condition14 + * 17 | STANDBY state switching in progress + * 18 | Low battery level + * 19 | Power-On reset + * 20 | Brown-Out event + * 21 | LOCK state in steady condition + * 22 | PM start-up timer expiration + * 23 | XO settling timeout + * \endcode + */ + +#define IRQ_STATUS2_BASE ((uint8_t)0xFB) /*!< IRQ Events(RR, split into 4 registers) */ + +#define IRQ_STATUS2_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /*!< IRQ: TX FIFO almost empty */ +#define IRQ_STATUS2_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /*!< IRQ: RX FIFO almost full */ +#define IRQ_STATUS2_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /*!< IRQ: RX FIFO almost empty */ +#define IRQ_STATUS2_MAX_BO_CCA_REACH ((uint8_t)0x08) /*!< IRQ: Max number of back-off during CCA */ +#define IRQ_STATUS2_VALID_PREAMBLE ((uint8_t)0x10) /*!< IRQ: Valid preamble detected */ +#define IRQ_STATUS2_VALID_SYNC ((uint8_t)0x20) /*!< IRQ: Sync word detected */ +#define IRQ_STATUS2_RSSI_ABOVE_TH ((uint8_t)(0x40)) /*!< IRQ: RSSI above threshold */ +#define IRQ_STATUS2_WKUP_TOUT_LDC ((uint8_t)(0x80)) /*!< IRQ: Wake-up timeout in LDC mode */ + +/** + * @} + */ + +/** @defgroup IRQ_STATUS3_Register + * @{ + */ + +/** + * \brief IRQ_STATUS3 registers + * \code + * Default value: 0x00 + * Read Write + * + * 7:0 INT_STATUS3: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) + * + * Bit | Events Group Interrupt Event + * ------------------------------------------------------- + * 24 | SYNTH locking timeout + * 25 | SYNTH calibration start-up time + * 26 | SYNTH calibration timeout + * 27 | TX circuitry start-up time + * 28 | RX circuitry start-up time + * 29 | RX operation timeout + * 30 | Others AES End–of –Operation + * 31 | Reserved + * \endcode + */ +#define IRQ_STATUS3_BASE ((uint8_t)0xFA) /*!< IRQ Events(RR, split into 4 registers) */ + +#define IRQ_STATUS3_RX_DATA_READY ((uint8_t)0x01) /*!< IRQ: RX data ready */ +#define IRQ_STATUS3_RX_DATA_DISC ((uint8_t)0x02) /*!< IRQ: RX data discarded (upon filtering) */ +#define IRQ_STATUS3_TX_DATA_SENT ((uint8_t)0x04) /*!< IRQ: TX data sent */ +#define IRQ_STATUS3_MAX_RE_TX_REACH ((uint8_t)0x08) /*!< IRQ: Max re-TX reached */ +#define IRQ_STATUS3_CRC_ERROR ((uint8_t)0x10) /*!< IRQ: CRC error */ +#define IRQ_STATUS3_TX_FIFO_ERROR ((uint8_t)0x20) /*!< IRQ: TX FIFO underflow/overflow error */ +#define IRQ_STATUS3_RX_FIFO_ERROR ((uint8_t)0x40) /*!< IRQ: RX FIFO underflow/overflow error */ +#define IRQ_STATUS3_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /*!< IRQ: TX FIFO almost full */ + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup MC_STATE_Registers + * @{ + */ + +/** @defgroup MC_STATE1_Register + * @{ + */ + +/** + * \brief MC_STATE1 registers + * \code + * Default value: 0x50 + * Read + * + * 7:4 Reserved. + * + * 3 ANT_SELECT: Currently selected antenna + * + * 2 TX_FIFO_Full: 1 - TX FIFO is full + * + * 1 RX_FIFO_Empty: 1 - RX FIFO is empty + * + * 0 ERROR_LOCK: 1 - RCO calibrator error + * \endcode + */ +#define MC_STATE1_BASE ((uint8_t)(0xC0)) /*!< MC_STATE1 register address (see the SpiritStatus struct */ + + +/** + * @} + */ + + +/** @defgroup MC_STATE0_Register + * @{ + */ + +/** + * \brief MC_STATE0 registers + * \code + * Default value: 0x00 + * Read + * + * 7:1 STATE[6:0]: Current MC state. + * + * REGISTER VALUE | STATE + * -------------------------------------------- + * 0x40 | STANDBY + * 0x36 | SLEEP + * 0x03 | READY + * 0x3B | PM setup + * 0x23 | XO settling + * 0x53 | SYNTH setup + * 0x1F | PROTOCOL + * 0x4F | SYNTH calibration + * 0x0F | LOCK + * 0x33 | RX + * 0x5F | TX + * + * 0 XO_ON: 1 - XO is operating + * \endcode + */ +#define MC_STATE0_BASE ((uint8_t)(0xC1)) /*!< MC_STATE0 register address. In this version ALL existing states have been inserted + and are still to be verified */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup Engineering-Test_Registers + * @{ + */ + +#define SYNTH_CONFIG1_BASE ((uint8_t)(0x9E)) /*!< Synthesizier registers: M, A, K data sync on positive/negative clock edges [4], + Enable Linearization of the charge pump [3], split time 1.75/3.45ns [2], VCO calibration window 16,32,64,128 clock cycles [1:0]*/ +#define SYNTH_CONFIG0_BASE ((uint8_t)(0x9F)) /*!< Enable DSM randomizer [7], Window width 1.2-7.5ns (Down-up) of lock detector*/ +#define VCOTH_BASE ((uint8_t)(0xA0)) /*!< Controls the threshold frequency between VCO low and VCO high [7:0] + VCOth frequency=2*fXO*(96+VCO_TH/16), fmin=4992 MHz, fmax=5820 MHz*/ +#define PM_CONFIG2_BASE ((uint8_t)(0xA4)) /*!< Enables high current buffer on Temperature sensor, sets SMPS options */ +#define PM_CONFIG1_BASE ((uint8_t)(0xA5)) /*!< Set SMPS options */ +#define PM_CONFIG0_BASE ((uint8_t)(0xA6)) /*!< Set SMPS options */ +#define VCO_CONFIG_BASE ((uint8_t)(0xA1)) /*!< Set VCO current [5:2]part and [1:0] part */ +#define XO_CONFIG_BASE ((uint8_t)(0xA7)) /*!< Clock management options from XO to digital part */ + +#define XO_RCO_TEST_BASE ((uint8_t)(0xB4)) /*!< Test of XO and RCO */ + +/** + * @} + */ + + +/** @addtogroup Commands + * @{ + */ + +#define COMMAND_TX ((uint8_t)(0x60)) /*!< Start to transmit; valid only from READY */ +#define COMMAND_RX ((uint8_t)(0x61)) /*!< Start to receive; valid only from READY */ +#define COMMAND_READY ((uint8_t)(0x62)) /*!< Go to READY; valid only from STANDBY or SLEEP or LOCK */ +#define COMMAND_STANDBY ((uint8_t)(0x63)) /*!< Go to STANDBY; valid only from READY */ +#define COMMAND_SLEEP ((uint8_t)(0x64)) /*!< Go to SLEEP; valid only from READY */ +#define COMMAND_LOCKRX ((uint8_t)(0x65)) /*!< Go to LOCK state by using the RX configuration of the synth; valid only from READY */ +#define COMMAND_LOCKTX ((uint8_t)(0x66)) /*!< Go to LOCK state by using the TX configuration of the synth; valid only from READY */ +#define COMMAND_SABORT ((uint8_t)(0x67)) /*!< Force exit form TX or RX states and go to READY state; valid only from TX or RX */ +#define COMMAND_LDC_RELOAD ((uint8_t)(0x68)) /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER + registers; valid from all states */ +#define COMMAND_SEQUENCE_UPDATE ((uint8_t)(0x69)) /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register + valid from all states */ +#define COMMAND_AES_ENC ((uint8_t)(0x6A)) /*!< AES: Start the encryption routine; valid from all states; valid from all states */ +#define COMMAND_AES_KEY ((uint8_t)(0x6B)) /*!< AES: Start the procedure to compute the key for the decryption; valid from all states */ +#define COMMAND_AES_DEC ((uint8_t)(0x6C)) /*!< AES: Start the decryption routine using the current key; valid from all states */ +#define COMMAND_AES_KEY_DEC ((uint8_t)(0x6D)) /*!< AES: Compute the key and start the decryption; valid from all states */ +#define COMMAND_SRES ((uint8_t)(0x70)) /*!< Reset of all digital part, except SPI registers */ +#define COMMAND_FLUSHRXFIFO ((uint8_t)(0x71)) /*!< Clean the RX FIFO; valid from all states */ +#define COMMAND_FLUSHTXFIFO ((uint8_t)(0x72)) /*!< Clean the TX FIFO; valid from all states */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Timer.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Timer.h new file mode 100644 index 000000000..d9e5e408f --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Timer.h @@ -0,0 +1,239 @@ +/** + ****************************************************************************** + * @file SPIRIT_Timer.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT timers. + * @details + * + * This module provides API to configure the Spirit timing mechanisms. + * They allow the user to set the timer registers using raw values or + * compute them since the desired timer value is expressed in ms. + * Moreover the management of the Spirit LDCR mode can be done using + * these API. + * + * Example: + * @code + * ... + * + * SpiritTimerSetRxTimeoutMs(50.0); + * SpiritTimerSetWakeUpTimerMs(150.0); + * + * // IRQ configuration for RX_TIMEOUT and WAKEUP_TIMEOUT + * ... + * + * SpiritTimerLdcrMode(S_ENABLE); + * + * ... + * + * @endcode + * + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT1_TIMER_H +#define __SPIRIT1_TIMER_H + + +/* Includes ------------------------------------------------------------------*/ + +#include "SPIRIT_Regs.h" +#include "SPIRIT_Types.h" + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Timer Timer + * @brief Configuration and management of SPIRIT Timers. + * @details See the file @ref SPIRIT_Timer.h for more details. + * @{ + */ + + +/** + * @defgroup Timer_Exported_Types Timer Exported Types + * @{ + */ + +/** + * @brief All the possible RX timeout stop conditions enumeration. + */ +typedef enum{ + + NO_TIMEOUT_STOP = 0x00, /*!< Timeout never stopped */ + TIMEOUT_ALWAYS_STOPPED = 0x08, /*!< Timeout always stopped (default) */ + RSSI_ABOVE_THRESHOLD = 0x04, /*!< Timeout stopped on RSSI above threshold */ + SQI_ABOVE_THRESHOLD = 0x02, /*!< Timeout stopped on SQI above threshold */ + PQI_ABOVE_THRESHOLD = 0x01, /*!< Timeout stopped on PQI above threshold */ + RSSI_AND_SQI_ABOVE_THRESHOLD = 0x06, /*!< Timeout stopped on both RSSI and SQI above threshold */ + RSSI_AND_PQI_ABOVE_THRESHOLD = 0x05, /*!< Timeout stopped on both RSSI and PQI above threshold */ + SQI_AND_PQI_ABOVE_THRESHOLD = 0x03, /*!< Timeout stopped on both SQI and PQI above threshold */ + ALL_ABOVE_THRESHOLD = 0x07, /*!< Timeout stopped only if RSSI, SQI and PQI are above threshold */ + RSSI_OR_SQI_ABOVE_THRESHOLD = 0x0E, /*!< Timeout stopped if one between RSSI or SQI are above threshold */ + RSSI_OR_PQI_ABOVE_THRESHOLD = 0x0D, /*!< Timeout stopped if one between RSSI or PQI are above threshold */ + SQI_OR_PQI_ABOVE_THRESHOLD = 0x0B, /*!< Timeout stopped if one between SQI or PQI are above threshold */ + ANY_ABOVE_THRESHOLD = 0x0F /*!< Timeout stopped if one among RSSI, SQI or SQI are above threshold */ + +} RxTimeoutStopCondition; + + +#define IS_RX_TIMEOUT_STOP_CONDITION(COND) ( COND == NO_TIMEOUT_STOP || \ + COND == TIMEOUT_ALWAYS_STOPPED || \ + COND == RSSI_ABOVE_THRESHOLD || \ + COND == SQI_ABOVE_THRESHOLD || \ + COND == PQI_ABOVE_THRESHOLD || \ + COND == RSSI_AND_SQI_ABOVE_THRESHOLD || \ + COND == RSSI_AND_PQI_ABOVE_THRESHOLD || \ + COND == SQI_AND_PQI_ABOVE_THRESHOLD || \ + COND == ALL_ABOVE_THRESHOLD || \ + COND == RSSI_OR_SQI_ABOVE_THRESHOLD || \ + COND == RSSI_OR_PQI_ABOVE_THRESHOLD || \ + COND == SQI_OR_PQI_ABOVE_THRESHOLD || \ + COND == ANY_ABOVE_THRESHOLD ) + + + +/** + * @} + */ + + +/** + * @defgroup Timer_Exported_Constants Timer Exported Constants + * @{ + */ + +/** + * @brief It represents the Time Step for RX_Timeout timer in case of 24 MHz Crystal, expressed in us. + * It is equal to 1210/(24*10^6). With this time step it is possible to fix the RX_Timeout to + * a minimum value of 50.417us to a maximum value of about 3.278 s. + * Remember that it is possible to have infinite RX_Timeout writing 0 in the RX_Timeout_Counter and/or RX_Timeout_Prescaler registers. + */ +#define RX_TCLK_24MHz 50.417f +#define IS_RX_TIMEOUT_24MHz(TIMEOUT) (TIMEOUT*1000)>=RX_TCLK_24MHz + +/** + * @brief It represents the Time Step for RX_Timeout timer in case of 26 MHz Crystal, expressed in us. + * It is equal to 1210/(26*10^6). With this time step it is possible to fix the RX_Timeout to + * a minimum value of 46.538us to a maximum value of about 3.026 s. + * Remember that it is possible to have infinite RX_Timeout writing 0 in the RX_Timeout_Counter register. + */ +#define RX_TCLK_26MHz 46.538f +#define IS_RX_TIMEOUT_26MHz(TIMEOUT) (TIMEOUT*1000)>=RX_TCLK_26MHz + +/** + * @brief It represents the Time Step for RX_Wakeup timer expressed in us. This timer is based on RCO (about 34.7 kHZ). + * With this time step it is possible to fix the Wakeup_Timeout to a minimum value of 28.818us to a maximum + * value of about 1.888 s. + */ +#define WAKEUP_TCLK 28.818f +#define IS_WKUP_TIMEOUT(TIMEOUT) (TIMEOUT*1000)>=WAKEUP_TCLK + + + +/** + * @} + */ + + +/** + * @defgroup Timer_Exported_Macros Timer Exported Macros + * @{ + */ + +#define SET_INFINITE_RX_TIMEOUT() SpiritTimerSetRxTimeoutCounter(0) + +/** + * @} + */ + + +/** + * @defgroup Timer_Exported_Functions Timer Exported Functions + * @{ + */ + +void SpiritTimerLdcrMode(SpiritFunctionalState xNewState); +void SpiritTimerLdcrAutoReload(SpiritFunctionalState xNewState); +SpiritFunctionalState SpiritTimerLdcrGetAutoReload(void); +void SpiritTimerSetRxTimeout(uint8_t cCounter , uint8_t cPrescaler); +void SpiritTimerSetRxTimeoutMs(float fDesiredMsec); +void SpiritTimerSetRxTimeoutCounter(uint8_t cCounter); +void SpiritTimerSetRxTimeoutPrescaler(uint8_t cPrescaler); +void SpiritTimerGetRxTimeout(float* pfTimeoutMsec, uint8_t* pcCounter , uint8_t* pcPrescaler); +void SpiritTimerSetWakeUpTimer(uint8_t cCounter , uint8_t cPrescaler); +void SpiritTimerSetWakeUpTimerMs(float fDesiredMsec); +void SpiritTimerSetWakeUpTimerCounter(uint8_t cCounter); +void SpiritTimerSetWakeUpTimerPrescaler(uint8_t cPrescaler); +void SpiritTimerSetWakeUpTimerReloadMs(float fDesiredMsec); +void SpiritTimerGetWakeUpTimer(float* pfWakeUpMsec, uint8_t* pcCounter , uint8_t* pcPrescaler); +void SpiritTimerSetWakeUpTimerReload(uint8_t cCounter , uint8_t cPrescaler); +void SpiritTimerSetWakeUpTimerReloadCounter(uint8_t cCounter); +void SpiritTimerSetWakeUpTimerReloadPrescaler(uint8_t cPrescaler); +void SpiritTimerGetWakeUpTimerReload(float* pfWakeUpReloadMsec, uint8_t* pcCounter , uint8_t* pcPrescaler); +void SpiritTimerComputeWakeUpValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler); +void SpiritTimerComputeRxTimeoutValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler); +void SpiritTimerSetRxTimeoutStopCondition(RxTimeoutStopCondition xStopCondition); +void SpiritTimerReloadStrobe(void); +uint16_t SpiritTimerGetRcoFrequency(void); + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ + diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Types.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Types.h new file mode 100644 index 000000000..ceba82b48 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Types.h @@ -0,0 +1,276 @@ +/** + ****************************************************************************** + * @file SPIRIT_Types.h + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Header file for SPIRIT types. + * @details + * + * This module provide some types definitions which will be used in + * all the modules of this library. Here is defined also the global + * variable @ref g_xStatus which contains the status of Spirit and + * is updated every time an SPI transaction occurs. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT_GENERICTYPES_H +#define __SPIRIT_GENERICTYPES_H + + +/* Includes ------------------------------------------------------------------*/ + +/* Include all integer types definitions */ +#include +#include +#include "SPIRIT_Regs.h" + + + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @defgroup SPIRIT_Types Types + * @brief Module for SPIRIT types definition. + * * @details See the file @ref SPIRIT_Types.h for more details. + * @{ + */ + +/** + * @defgroup Types_Exported_Types Types Exported Types + * @{ + */ + +/** + * @brief Spirit Functional state. Used to enable or disable a specific option. + */ +typedef enum +{ + S_DISABLE = 0, + S_ENABLE = !S_DISABLE + +} SpiritFunctionalState; + +#define IS_SPIRIT_FUNCTIONAL_STATE(STATE) (STATE == S_DISABLE || STATE == S_ENABLE) + +/** + * @brief Spirit Flag status. Used to control the state of a flag. + */ +typedef enum +{ + S_RESET = 0, + S_SET = !S_RESET + +} SpiritFlagStatus; + +#define IS_SPIRIT_FLAG_STATUS(STATUS) (STATUS == S_RESET || STATUS == S_SET) + + +/** + * @brief boolean type enumeration. + */ +typedef enum +{ + S_FALSE = 0, + S_TRUE = !S_FALSE + +} SpiritBool; + + +/** + * @brief SPIRIT States enumeration. + */ +typedef enum +{ + MC_STATE_STANDBY =0x40, /*!< STANDBY */ + MC_STATE_SLEEP =0x36, /*!< SLEEP */ + MC_STATE_READY =0x03, /*!< READY */ + MC_STATE_PM_SETUP =0x3D, /*!< PM_SETUP */ + MC_STATE_XO_SETTLING =0x23, /*!< XO_SETTLING */ + MC_STATE_SYNTH_SETUP =0x53, /*!< SYNT_SETUP */ + MC_STATE_PROTOCOL =0x1F, /*!< PROTOCOL */ + MC_STATE_SYNTH_CALIBRATION =0x4F, /*!< SYNTH */ + MC_STATE_LOCK =0x0F, /*!< LOCK */ + MC_STATE_RX =0x33, /*!< RX */ + MC_STATE_TX =0x5F /*!< TX */ + +} SpiritState; + + + +/** + * @brief SPIRIT Status. This definition represents the single field of the SPIRIT + * status returned on each SPI transaction, equal also to the MC_STATE registers. + * This field-oriented structure allows user to address in simple way the single + * field of the SPIRIT status. + * The user shall define a variable of SpiritStatus type to access on SPIRIT status fields. + * @note The fields order in the structure depends on used endianness (little or big + * endian). The actual definition is valid ONLY for LITTLE ENDIAN mode. Be sure to + * change opportunely the fields order when use a different endianness. + */ + +typedef struct +{ + uint8_t XO_ON:1; /*!< This one bit field notifies if XO is operating + (XO_ON is 1) or not (XO_On is 0) */ + SpiritState MC_STATE: 7; /*!< This 7 bits field indicates the state of the + Main Controller of SPIRIT. The possible states + and their corresponding values are defined in + @ref SpiritState */ + uint8_t ERROR_LOCK: 1; /*!< This one bit field notifies if there is an + error on RCO calibration (ERROR_LOCK is 1) or + not (ERROR_LOCK is 0) */ + uint8_t RX_FIFO_EMPTY: 1; /*!< This one bit field notifies if RX FIFO is empty + (RX_FIFO_EMPTY is 1) or not (RX_FIFO_EMPTY is 0) */ + uint8_t TX_FIFO_FULL: 1; /*!< This one bit field notifies if TX FIFO is full + (TX_FIFO_FULL is 1) or not (TX_FIFO_FULL is 0) */ + uint8_t ANT_SELECT: 1; /*!< This one bit field notifies the currently selected + antenna */ + uint8_t : 4; /*!< This 4 bits field are reserved and equal to 5 */ + +}SpiritStatus; + + + +/** + * @} + */ + + +/** + * @defgroup Types_Exported_Constants Types Exported Constants + * @{ + */ + + +/** + * @} + */ + +/** + * @defgroup Types_Exported_Variables Types Exported Variables + * @{ + */ + +extern volatile SpiritStatus g_xStatus; + +/** + * @} + */ + +/** + * @defgroup Types_Exported_Macros Types Exported Macros + * @{ + */ + +#ifdef SPIRIT_USE_FULL_ASSERT + /** + * @brief The s_assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define s_assert_param(expr) ((expr) ? (void)0 : s_assert_failed((uint8_t *)__FILE__, __LINE__)) + void s_assert_failed(uint8_t* file, uint32_t line); +#elif SPIRIT_USE_VCOM_ASSERT + /** + * @brief The s_assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define s_assert_param(expr) ((expr) ? (void)0 : s_assert_failed((uint8_t *)__FILE__, __LINE__,#expr)) + void s_assert_failed(uint8_t* file, uint32_t line, char* expression); + +#elif SPIRIT_USE_FRAME_ASSERT + /** + * @brief The s_assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ +#define s_assert_param(expr) ((expr) ? (void)0 : s_assert_failed(#expr)) + void s_assert_failed(char* expression); +#else +#define s_assert_param(expr) {} +#endif + +/** + * @brief Returns the absolute value. + */ +#define S_ABS(a) ((a)>0?(a):-(a)) + + +/** + * @} + */ + + +/** + * @defgroup Types_Exported_Functions Types Exported Functions + * @{ + */ + +void SpiritRefreshStatus(void); + +/** + *@} + */ + +/** + * @} + */ + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT1_Util.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT1_Util.c new file mode 100644 index 000000000..7ce878a93 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT1_Util.c @@ -0,0 +1,652 @@ +/** +* @file SPIRIT1_Util.c +* @author High End Analog & RF BU - AMS / ART Team IMS-Systems Lab +* @version V3.0.1 +* @date November 19, 2012 +* @brief Identification functions for SPIRIT DK. +* @details +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +* THIS SOURCE CODE IS PROTECTED BY A LICENSE. +* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED +* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. +* +*

© COPYRIGHT 2012 STMicroelectronics

+*/ + + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT1_Util.h" +#include "SPIRIT_Config.h" +#include "spirit1-config.h" +#if defined(P2P_DEMO) +#include "spirit1_appli.h" +#endif +/** +* @addtogroup ST_SPIRIT1 +* @{ +*/ + + +/** +* @addtogroup SPIRIT1_Util +* @{ +*/ + + +/** +* @defgroup SPIRIT1_Util_Private_TypesDefinitions SPIRIT1_Util Private Types Definitions +* @{ +*/ + +/** +* @} +*/ + + +/** +* @defgroup SPIRIT1_Util_Private_Defines SPIRIT1_Util Private Defines +* @{ +*/ + +/** +* @} +*/ + + +/** +* @defgroup SPIRIT1_Util_Private_Macros SPIRIT1_Util Private Macros +* @{ +*/ +#define SPIRIT_VERSION SPIRIT_VERSION_3_0 +#define RANGE_TYPE RANGE_EXT_NONE /*RANGE_EXT_SKYWORKS*/ +/** +* @} +*/ + + +/** +* @defgroup SPIRIT1_Util_Private_Variables SPIRIT1_Util Private Variables +* @{ +*/ + +/** +* @brief A map that contains the SPIRIT version +*/ +const SpiritVersionMap xSpiritVersionMap[] = +{ + /* The Control Board frame handler functions */ + {CUT_2_1v4, SPIRIT_VERSION_2_1}, + {CUT_2_1v3, SPIRIT_VERSION_2_1}, + {CUT_3_0, SPIRIT_VERSION_3_0}, +}; +static RangeExtType xRangeExtType = RANGE_EXT_NONE; + +static uint8_t s_RfModuleBand = 0; +static uint8_t s_eeprom = 0; +/** +* @} +*/ + + +/** +* @defgroup SPIRIT1_Util_Private_FunctionPrototypes SPIRIT1_Util Private Function Prototypes +* @{ +*/ + +/** +* @} +*/ + + +/** +* @defgroup SPIRIT1_Util_Private_Functions SPIRIT1_Util Private Functions +* @{ +*/ + +/** +* @brief Read the status register. +* @param None +* @retval Status +*/ +void Spirit1InterfaceInit(void) +{ + /* Initialize the SDN pin micro side */ + RadioGpioInit(RADIO_GPIO_SDN,RADIO_MODE_GPIO_OUT); + + SpiritSpiInit(); + +#if defined(SPIRIT1_HAS_EEPROM) + EepromSpiInitialization(); +#endif + + /* Board management */ + SpiritEnterShutdown(); + SpiritExitShutdown(); + + SpiritManagementIdentificationRFBoard(); + + /* Initialize the signals to drive the range extender application board */ + SpiritManagementRangeExtInit(); + + /* Micro EXTI config */ + RadioGpioInit(RADIO_GPIO_IRQ,RADIO_MODE_EXTI_IN); + RadioGpioInterruptCmd(RADIO_GPIO_IRQ,0x04,0x04,DISABLE); + RadioGpioInterruptCmd(RADIO_GPIO_IRQ,0x04,0x04,ENABLE); +} + +#if defined(SPIRIT1_HAS_EEPROM) +/** +* @brief Read the status register. +* @param None +* @retval Status +*/ +uint8_t EepromIdentification(void) +{ + uint8_t status; + status = EepromSetSrwd(); + status = EepromStatus(); + if((status&0xF0) == EEPROM_STATUS_SRWD) + { + /*0xF0 mask [SRWD 0 0 0]*/ + status = 1; + EepromResetSrwd(); + } + else + status = 0; + + return status; +} +#endif + +#if defined(SPIRIT1_HAS_EEPROM) + +/** +* @brief Identifies the SPIRIT1 Xtal frequency and version. +* @param None +* @retval Status +*/ +void SpiritManagementIdentificationRFBoard(void) +{ + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + }while(g_xStatus.MC_STATE!=MC_STATE_READY); + + SdkEvalSetHasEeprom(EepromIdentification()); + + if(!SdkEvalGetHasEeprom()) /* EEPROM is not present*/ + { + SpiritManagementComputeSpiritVersion(); + SpiritManagementComputeXtalFrequency(); + } + else /* EEPROM found*/ + { + /*read the memory and set the variable*/ + EepromRead(0x0000, 32, tmpBuffer); + uint32_t xtal; + if(tmpBuffer[0]==0 || tmpBuffer[0]==0xFF) { + SpiritManagementComputeSpiritVersion(); + SpiritManagementComputeXtalFrequency(); + return; + } + switch(tmpBuffer[1]) { + case 0: + xtal = 24000000; + SpiritRadioSetXtalFrequency(xtal); + break; + case 1: + xtal = 25000000; + SpiritRadioSetXtalFrequency(xtal); + break; + case 2: + xtal = 26000000; + SpiritRadioSetXtalFrequency(xtal); + break; + case 3: + xtal = 48000000; + SpiritRadioSetXtalFrequency(xtal); + break; + case 4: + xtal = 50000000; + SpiritRadioSetXtalFrequency(xtal); + break; + case 5: + xtal = 52000000; + SpiritRadioSetXtalFrequency(xtal); + break; + default: + SpiritManagementComputeXtalFrequency(); + break; + } + + SpiritVersion spiritVersion; + if(tmpBuffer[2]==0 || tmpBuffer[2]==1) { + spiritVersion = SPIRIT_VERSION_2_1; + //SpiritGeneralSetSpiritVersion(spiritVersion); + } + else if(tmpBuffer[2]==2) { + spiritVersion = SPIRIT_VERSION_3_0; + //SpiritGeneralSetSpiritVersion(spiritVersion); + } + else { + SpiritManagementComputeSpiritVersion(); + } + if(tmpBuffer[14]==1) { + spiritVersion = SPIRIT_VERSION_3_0_D1; + // SpiritGeneralSetSpiritVersion(spiritVersion); + } + + RangeExtType range; + if(tmpBuffer[5]==0) { + range = RANGE_EXT_NONE; + } + else if(tmpBuffer[5]==1) { + range = RANGE_EXT_SKYWORKS_169; + } + else if(tmpBuffer[5]==2) { + range = RANGE_EXT_SKYWORKS_868; + } + else { + range = RANGE_EXT_NONE; + } + SpiritManagementSetRangeExtender(range); + + SpiritManagementSetBand(tmpBuffer[3]); + + } +} +#endif + +#if defined(NO_EEPROM) +/** +* @brief Identifies the SPIRIT1 Xtal frequency and version. +* @param None +* @retval Status +*/ +void SpiritManagementIdentificationRFBoard(void) +{ + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + }while(g_xStatus.MC_STATE!=MC_STATE_READY); + + SpiritRadioSetXtalFrequency(XTAL_FREQUENCY); + //SpiritGeneralSetSpiritVersion(SPIRIT_VERSION); +} +#endif + + +/** +* @brief Sets the SPIRIT frequency band +* @param uint8_t value: RF FREQUENCY +* @retval None +*/ +void SpiritManagementSetBand(uint8_t value) +{ + s_RfModuleBand = value; +} + + +/** +* @brief returns the SPIRIT frequency band +* @param None +* @retval uint8_t value: RF FREQUENCY +*/ +uint8_t SpiritManagementGetBand(void) +{ + return s_RfModuleBand; +} + +/** +* @defgroup RANGE_EXT_MANAGEMENT_FUNCTIONS SDK SPIRIT Management Range Extender Functions +* @{ +*/ +void SpiritManagementRangeExtInit(void) +{ + RangeExtType range_type = SpiritManagementGetRangeExtender(); + + if(range_type==RANGE_EXT_SKYWORKS_169) { + /* TCXO optimization power consumption */ + SpiritGeneralSetExtRef(MODE_EXT_XIN); + uint8_t tmp = 0x01; SpiritSpiWriteRegisters(0xB6,1,&tmp); + + /* CSD control */ + SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_0, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_RX_MODE}); + + /* CTX/BYP control */ + SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_1, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_STATE}); + + /* Vcont control */ + SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_2, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_RX_STATE}); + } + else if(range_type==RANGE_EXT_SKYWORKS_868) { + /* CSD control */ + SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_0, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_RX_MODE}); + + /* CTX/BYP control */ + SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_1, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_RX_STATE}); + + /* Vcont control */ + SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_2, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_STATE}); + } +} + +/** +* @brief returns the spirit1 range extender type +* @param None +* @retval RangeExtType +*/ +RangeExtType SpiritManagementGetRangeExtender(void) +{ + return xRangeExtType; +} + +/** +* @brief Sets the spirit1 range extender type +* @param RangeExtType +* @retval None +*/ +void SpiritManagementSetRangeExtender(RangeExtType xRangeType) +{ + xRangeExtType = xRangeType; +} + +/** +* @brief this function returns the value to indicate that EEPROM is present or not +* @param None +* @retval uint8_t: 0 or 1 +*/ +uint8_t SdkEvalGetHasEeprom(void) +{ + return s_eeprom; +} + +/** +* @brief this function setc the value to indicate that EEPROM is present or not +* @param None +* @retval uint8_t: 0 or 1 +*/ +void SdkEvalSetHasEeprom(uint8_t eeprom) +{ + s_eeprom = eeprom; +} + +/** +* @brief this function intializes the spirit1 gpio irq for TX and Rx +* @param None +* @retval None +*/ +void Spirit1GpioIrqInit(SGpioInit *pGpioIRQ) +{ + /* Spirit IRQ config */ + SpiritGpioInit(pGpioIRQ); +} + +/** +* @brief this function used to receive RX packet +* @param None +* @retval None +*/ +void Spirit1RadioInit(SRadioInit *pRadioInit) +{ + /* Spirit Radio config */ + SpiritRadioInit(pRadioInit); + +} + +/** +* @brief this function sets the radio power +* @param uint8_t cIndex, float fPowerdBm +* @retval None +*/ +void Spirit1SetPower(uint8_t cIndex, float fPowerdBm) +{ + /* Spirit Radio set power */ + SpiritRadioSetPALeveldBm(cIndex,fPowerdBm); + SpiritRadioSetPALevelMaxIndex(cIndex); +} + +/** +* @brief this function sets the packet configuration according to the protocol used +* @param None +* @retval None +*/ +void Spirit1PacketConfig(void) +{ + BasicProtocolInit(); +} + +/** +* @brief this function sets the payload length +* @param uint8_t length +* @retval None +*/ +void Spirit1SetPayloadlength(uint8_t length) +{ +#if defined(USE_STack_PROTOCOL) + /* Payload length config */ + SpiritPktStackSetPayloadLength(length); + +#elif defined(USE_BASIC_PROTOCOL) + /* payload length config */ + SpiritPktBasicSetPayloadLength(length); +#endif +} + +/** +* @brief this function sets the destination address +* @param uint8_t adress +* @retval None +*/ +void Spirit1SetDestinationAddress(uint8_t address) +{ +#if defined(USE_STack_PROTOCOL) + /* Destination address */ + SpiritPktStackSetDestinationAddress(address); +#elif defined(USE_BASIC_PROTOCOL) + /* destination address */ + SpiritPktBasicSetDestinationAddress(address); +#endif +} + +/** +* @brief this function enables the Tx IRQ +* @param None +* @retval None +*/ +void Spirit1EnableTxIrq(void) +{ + /* Spirit IRQs enable */ + SpiritIrq(TX_DATA_SENT, S_ENABLE); +#if defined(USE_STack_PROTOCOL) + SpiritIrq(MAX_RE_TX_REACH, S_ENABLE); +#elif defined(USE_BASIC_PROTOCOL) //added inadr + SpiritIrq(VALID_SYNC,S_ENABLE); + SpiritIrq(TX_FIFO_ERROR, S_ENABLE); + +#endif +} + +/** +* @brief this function enables the Rx IRQ +* @param None +* @retval None +*/ +void Spirit1EnableRxIrq(void) +{ + /* Spirit IRQs enable */ + SpiritIrq(RX_DATA_READY, S_ENABLE); + SpiritIrq(RX_DATA_DISC, S_ENABLE); + SpiritIrq(RX_TIMEOUT, S_ENABLE); +#ifdef USE_BASIC_PROTOCOL //added inadr + SpiritIrq(RX_FIFO_ERROR, S_ENABLE); +#endif + +} + +/** +* @brief this function disable IRQs +* @param None +* @retval None +*/ +void Spirit1DisableIrq(void) +{ + /* Spirit IRQs enable */ + SpiritIrqDeInit(NULL); +} +/** +* @brief this function set the receive timeout period +* @param None +* @retval None +*/ +void Spirit1SetRxTimeout(float cRxTimeOut) +{ + if(cRxTimeOut == 0) + { + /* rx timeout config */ + SET_INFINITE_RX_TIMEOUT(); + SpiritTimerSetRxTimeoutStopCondition(ANY_ABOVE_THRESHOLD); + } + else + { + /* RX timeout config */ + SpiritTimerSetRxTimeoutMs(cRxTimeOut); + Spirit1EnableSQI(); + SpiritTimerSetRxTimeoutStopCondition(RSSI_AND_SQI_ABOVE_THRESHOLD); } +} + +/** +* @brief this function sets the RSSI threshold +* @param int dbmValue +* @retval None +*/ +void Spirit1SetRssiTH(int dbmValue) +{ + SpiritQiSetRssiThresholddBm(dbmValue); +} + +/** +* @brief this function sets the RSSI threshold +* @param int dbmValue +* @retval None +*/ +float Spirit1GetRssiTH(void) +{ + float dbmValue=0; + dbmValue = SpiritQiGetRssidBm(); + return dbmValue; +} + +/** +* @brief this function enables SQI check +* @param None +* @retval None +*/ +void Spirit1EnableSQI(void) +{ + /* enable SQI check */ + SpiritQiSetSqiThreshold(SQI_TH_0); + SpiritQiSqiCheck(S_ENABLE); +} + +/** +* @brief this function starts the RX process +* @param None +* @retval None +*/ +void Spirit1StartRx(void) +{ + /* RX command */ + SpiritCmdStrobeRx(); +#if 0 + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + } + while(g_xStatus.MC_STATE!=MC_STATE_RX); +#endif +} + +/** +* @brief this function receives the data +* @param None +* @retval None +*/ +void Spirit1GetRxPacket(uint8_t *buffer, uint8_t cRxData ) +{ + /* when rx data ready read the number of received bytes */ + cRxData=SpiritLinearFifoReadNumElementsRxFifo(); + + /* read the RX FIFO */ + SpiritSpiReadLinearFifo(cRxData, buffer); + + SpiritCmdStrobeFlushRxFifo(); +} + +/** +* @brief this function starts the TX process +* @param None +* @retval None +*/ +void Spirit1StartTx(uint8_t *buffer, uint8_t size ) +{ + /* fit the TX FIFO */ + SpiritCmdStrobeFlushTxFifo(); + + SpiritSpiWriteLinearFifo(size, buffer); + + /* send the TX command */ + SpiritCmdStrobeTx(); +#if 0 + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + } + while(g_xStatus.MC_STATE!=MC_STATE_TX); +#endif +#if defined(P2P_DEMO) + + /* wait for TX done */ + while(!xTxDoneFlag); + xTxDoneFlag = RESET; +#endif +} + +/** +* @brief this function clear the IRQ status +* @param None +* @retval None +*/ +void Spirit1ClearIRQ(void) +{ + SpiritIrqClearStatus(); +} +/** +* @} +*/ + +/** +* @} +*/ + + +/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Aes.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Aes.c new file mode 100644 index 000000000..469b3d399 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Aes.c @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file SPIRIT_Aes.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT AES Engine. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Aes.h" +#include "MCU_Interface.h" + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_Aes + * @{ + */ + + +/** + * @defgroup Aes_Private_TypesDefinitions AES Private Types Definitions + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Aes_Private_Defines AES Private Defines + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Aes_Private_Macros AES Private Macros + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Aes_Private_Variables AES Private Variables + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Aes_Private_FunctionPrototypes AES Private Function Prototypes + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Aes_Private_Functions AES Private Functions + * @{ + */ + + +/** + * @brief Enables or Disables the AES engine. + * @param xNewState new state for AES engine. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None + */ +void SpiritAesMode(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Modifies the register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= AES_MASK; + } + else + { + tempRegValue &= ~AES_MASK; + } + + /* Writes the ANA_FUNC_CONF0 register to enable or disable the AES engine */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Writes the data to encrypt or decrypt, or the encryption key for the + * derive decryption key operation into the AES_DATA_IN registers. + * @param pcBufferDataIn pointer to the user data buffer. The first byte of the array + * shall be the MSB byte and it will be put in the AES_DATA_IN[0] register, while + * the last one shall be the LSB and it will be put in the AES_DATA_IN[cDataLength-1] + * register. If data to write are less than 16 bytes the remaining AES_DATA_IN registers + * will be filled with bytes equal to 0. This parameter is an uint8_t*. + * @param cDataLength length of data in bytes. + * This parameter is an uint8_t. + * @retval None + */ +void SpiritAesWriteDataIn(uint8_t* pcBufferDataIn, uint8_t cDataLength) +{ + uint8_t i, dataInArray[16]; + + /* Verifies that there are no more than 16 bytes */ + (cDataLength>16) ? (cDataLength=16) : cDataLength; + + /* Fill the dataInArray with the data buffer, using padding */ + for(i=0;i<16;i++) + { + (i<(16 - cDataLength)) ? (dataInArray[i]=0):(dataInArray[i]=pcBufferDataIn[15-i]); + + } + + /* Writes the AES_DATA_IN registers */ + g_xStatus = SpiritSpiWriteRegisters(AES_DATA_IN_15_BASE, 16, dataInArray); + +} + + +/** + * @brief Returns the encrypted or decrypted data or the decription key from the AES_DATA_OUT register. + * @param pcBufferDataOut pointer to the user data buffer. The AES_DATA_OUT[0] + * register value will be put as first element of the buffer (MSB), while the + * AES_DAT_OUT[cDataLength-1] register value will be put as last element of the buffer (LSB). + * This parameter is a uint8_t*. + * @param cDataLength length of data to read in bytes. + * This parameter is a uint8_t. + * @retval None + */ +void SpiritAesReadDataOut(uint8_t* pcBufferDataOut, uint8_t cDataLength) +{ + uint8_t address, dataOutArray[16]; + + /* Verifies that there are no more than 16 bytes */ + (cDataLength>16) ? (cDataLength=16) : cDataLength; + + /* Evaluates the address of AES_DATA_OUT from which start to read */ + address = AES_DATA_OUT_15_BASE+16-cDataLength; + + /* Reads the exact number of AES_DATA_OUT registers */ + g_xStatus = (SpiritSpiReadRegisters(address, cDataLength, dataOutArray)); + + /* Copy in the user buffer the read values changing the order */ + for(int i = (cDataLength-1); i>=0; i--) + { + *pcBufferDataOut = dataOutArray[i]; + pcBufferDataOut++; + } + +} + + +/** + * @brief Writes the encryption key into the AES_KEY_IN register. + * @param pcKey pointer to the buffer of 4 words containing the AES key. + * The first byte of the buffer shall be the most significant byte AES_KEY_0 of the AES key. + * The last byte of the buffer shall be the less significant byte AES_KEY_15 of the AES key. + * This parameter is an uint8_t*. + * @retval None + */ +void SpiritAesWriteKey(uint8_t* pcKey) +{ + uint8_t pcTempKey[16]; + for (uint8_t i = 0; i < 16; i++) + { + pcTempKey[15-i] = pcKey[i]; + } + + /* Writes the AES_DATA_IN registers */ + g_xStatus = SpiritSpiWriteRegisters(AES_KEY_IN_15_BASE, 16, pcTempKey); + +} + +/** + * @brief Returns the encryption/decryption key from the AES_KEY_IN register. + * @param pcKey pointer to the buffer of 4 words (16 bytes) containing the AES key. + * The first byte of the buffer shall be the most significant byte AES_KEY_0 of the AES key. + * The last byte of the buffer shall be the less significant byte AES_KEY_15 of the AES key. + * This parameter is an uint8_t*. + * @retval None + */ +void SpiritAesReadKey(uint8_t* pcKey) +{ + uint8_t pcTempKey[16]; + + /* Reads the AES_DATA_IN registers */ + g_xStatus = SpiritSpiReadRegisters(AES_KEY_IN_15_BASE, 16, pcTempKey); + + + for (uint8_t i = 0; i < 16; i++) + pcKey[i] = pcTempKey[15-i]; + +} + + + +/** + * @brief Derives the decryption key from a given encryption key. + * @param None. + * @retval None. + */ +void SpiritAesDeriveDecKeyFromEnc(void) +{ + /* Sends the COMMAND_AES_KEY command */ + g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_KEY); + +} + + +/** + * @brief Executes the encryption operation. + * @param None. + * @retval None. + */ +void SpiritAesExecuteEncryption(void) +{ + /* Sends the COMMAND_AES_ENC command */ + g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_ENC); + +} + + +/** + * @brief Executes the decryption operation. + * @param None. + * @retval None. + */ +void SpiritAesExecuteDecryption(void) +{ + /* Sends the COMMAND_AES_DEC command */ + g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_DEC); + +} + + +/** + * @brief Executes the key derivation and the decryption operation. + * @param None. + * @retval None. + */ +void SpiritAesDeriveDecKeyExecuteDec(void) +{ + /* Sends the COMMAND_AES_KEY_DEC command */ + g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_KEY_DEC); + +} + + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Calibration.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Calibration.c new file mode 100644 index 000000000..698a9de47 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Calibration.c @@ -0,0 +1,491 @@ +/** + ****************************************************************************** + * @file SPIRIT_Calibration.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT VCO-RCO calibration. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Calibration.h" +#include "MCU_Interface.h" + + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_Calibration + * @{ + */ + + +/** + * @defgroup Calibration_Private_TypesDefinitions Calibration Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Calibration_Private_Defines Calibration Private Defines + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup Calibration_Private_Macros Calibration Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Calibration_Private_Variables Calibration Private Variables + * @{ + */ + +/** + *@} + */ + + + +/** + * @defgroup Calibration_Private_FunctionPrototypes Calibration Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Calibration_Private_Functions Calibration Private Functions + * @{ + */ + +/** + * @brief Enables or Disables the RCO calibration. + * @param xNewState new state for RCO calibration. + This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritCalibrationRco(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + + /* Build new value for the register */ + if(xNewState==S_ENABLE) + { + tempRegValue |= PROTOCOL2_RCO_CALIBRATION_MASK; + } + else + { + tempRegValue &= ~PROTOCOL2_RCO_CALIBRATION_MASK; + } + + /* Writes register to enable or disable the RCO calibration */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Enables or Disables the VCO calibration. + * @param xNewState new state for VCO calibration. + This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritCalibrationVco(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + + /* Build new value for the register */ + if(xNewState==S_ENABLE) + tempRegValue |= PROTOCOL2_VCO_CALIBRATION_MASK; + else + tempRegValue &= ~PROTOCOL2_VCO_CALIBRATION_MASK; + + /* Writes register to enable or disable the VCO calibration */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets the RCO calibration words. + * @param cRwt RWT word for RCO calibration. + * This parameter can be a value of uint8_t. + * @param cRfb RFB word for RCO calibration. + * This parameter can be a value of uint8_t. + * @retval None. + */ +void SpiritCalibrationSetRcoCalWords(uint8_t cRwt, uint8_t cRfb) +{ + uint8_t tempRegValue[2]; + + /* Build the value of RWT and the MSbits of the RFB word */ + tempRegValue[0] = (cRwt << 4) | (cRfb >> 1); + + /* Reads the register value to update the LSbit of RFB */ + g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue[1]); + + /* Build new value for the register */ + tempRegValue[1] = (tempRegValue[1] & 0x7F) | (cRfb<<7); + + /* Writes the new value for RCO calibration words */ + g_xStatus = SpiritSpiWriteRegisters(RCO_VCO_CALIBR_IN2_BASE, 2, tempRegValue); + +} + + +/** + * @brief Returns the RCO calibration words. + * @param pcRwt pointer to the variable in which the RWT word has to be stored. + * This parameter is a variable of uint8_t*. + * @param pcRfb pointer to the variable in which the RFB word has to be stored. + * This parameter is a variable of uint8_t*. + * @retval None. + */ +void SpiritCalibrationGetRcoCalWords(uint8_t* pcRwt, uint8_t* pcRfb) +{ + uint8_t tempRegValue[2]; + + /* Reads the registers values */ + g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_OUT1_BASE, 2, tempRegValue); + + /* Build the RWT value */ + (*pcRwt) = tempRegValue[0] >> 4; + /* Build the RFB value */ + (*pcRfb) = (tempRegValue[0] & 0x0F)<<1 | (tempRegValue[1]>>7); + +} + + +/** + * @brief Returns the VCO calibration data from internal VCO calibrator. + * @param None. + * @retval uint8_t VCO calibration data word. + */ +uint8_t SpiritCalibrationGetVcoCalData(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_OUT0_BASE, 1, &tempRegValue); + + /* Build and returns the VCO calibration data value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Sets the VCO calibration data to be used in TX mode. + * @param cVcoCalData calibration data word to be set. + * This parameter is a variable of uint8_t. + * @retval None. + */ +void SpiritCalibrationSetVcoCalDataTx(uint8_t cVcoCalData) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue); + + /* Build the value to be written */ + tempRegValue &= 0x80; + tempRegValue |= cVcoCalData; + + /* Writes the new value of calibration data in TX */ + g_xStatus = SpiritSpiWriteRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the actual VCO calibration data used in TX mode. + * @param None. + * @retval uint8_t Calibration data word used in TX mode. + */ +uint8_t SpiritCalibrationGetVcoCalDataTx(void) +{ + uint8_t tempRegValue; + + /* Reads the register containing the calibration data word used in TX mode */ + g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue); + + /* Mask the VCO_CALIBR_TX field and returns the value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Sets the VCO calibration data to be used in RX mode. + * @param cVcoCalData calibration data word to be set. + * This parameter is a variable of uint8_t. + * @retval None. + */ +void SpiritCalibrationSetVcoCalDataRx(uint8_t cVcoCalData) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN0_BASE, 1, &tempRegValue); + + /* Build the value to be written */ + tempRegValue &= 0x80; + tempRegValue |= cVcoCalData; + + /* Writes the new value of calibration data in RX */ + g_xStatus = SpiritSpiWriteRegisters(RCO_VCO_CALIBR_IN0_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the actual VCO calibration data used in RX mode. + * @param None. + * @retval uint8_t Calibration data word used in RX mode. + */ +uint8_t SpiritCalibrationGetVcoCalDataRx(void) +{ + uint8_t tempRegValue; + + /* Reads the register containing the calibration data word used in TX mode */ + g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN0_BASE, 1, &tempRegValue); + + /* Mask the VCO_CALIBR_RX field and returns the value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Sets the VCO calibration window. + * @param xRefWord value of REFWORD corresponding to the Ref_period according to the formula: CALIBRATION_WIN = 11*Ref_period/fxo. + This parameter can be a value of @ref VcoWin. + * @retval None. + */ +void SpiritCalibrationSetVcoWindow(VcoWin xRefWord) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_VCO_WIN(xRefWord)); + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + + /* Build the values to be written */ + tempRegValue &= 0xFC; + tempRegValue |= xRefWord; + + /* Writes the new value of VCO calibration window */ + g_xStatus = SpiritSpiWriteRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the VCO calibration window. + * @param None. + * @retval VcoWin Value of REFWORD corresponding to the Ref_period according to the formula: CALIBRATION_WIN = 11*Ref_period/fxo. + * This parameter can be a value of @ref VcoWin. + */ +VcoWin SpiritCalibrationGetVcoWindow(void) +{ + uint8_t tempRegValue1, tempRegValue2; + VcoWin refWord; + + /* Reads the register containing the REFWORD value */ + g_xStatus = SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue1); + + /* Reads the Xtal configuration */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue2); + + /* Mask the REFWORD field */ + tempRegValue1 &= 0x03; + + /* Mask the 24_26_MHz_SELECT field */ + tempRegValue2 = ((tempRegValue2 & 0x40)>>6); + + /* In case of 26 MHz crystal */ + if(tempRegValue2) + { + switch(tempRegValue1) + { + case 0: + refWord = CALIB_TIME_6_77_US_26MHZ; + break; + case 1: + refWord = CALIB_TIME_13_54_US_26MHZ; + break; + case 2: + refWord = CALIB_TIME_27_08_US_26MHZ; + break; + case 3: + refWord = CALIB_TIME_54_15_US_26MHZ; + break; + } + } + + /* In case of 24 MHz crystal */ + else + { + switch(tempRegValue1) + { + case 0: + refWord = CALIB_TIME_7_33_US_24MHZ; + break; + case 1: + refWord = CALIB_TIME_14_67_US_24MHZ; + break; + case 2: + refWord = CALIB_TIME_29_33_US_24MHZ; + break; + case 3: + refWord = CALIB_TIME_58_67_US_24MHZ; + break; + } + } + + return refWord; + +} + +/** + * @brief Selects a VCO. + * @param xVco can be VCO_H or VCO_L according to which VCO select. + * This parameter can be a value of @ref VcoSel. + * @retval None. + */ +void SpiritCalibrationSelectVco(VcoSel xVco) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_VCO_SEL(xVco)); + + SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + + tempRegValue &= 0xF9; + + if(xVco == VCO_H) + { + tempRegValue |= 0x02; + + } + else + { + tempRegValue |= 0x04; + } + SpiritSpiWriteRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + +} + + + +/** + * @brief Returns the VCO selected. + * @param void. + * @retval VCO_H or VCO_L according to which VCO selected. + * This parameter can be a value of @ref VcoSel. + */ +VcoSel SpiritCalibrationGetVcoSelecttion(void) +{ + uint8_t tempRegValue; + + SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + + tempRegValue = (tempRegValue>>1)&0x3; + + if(tempRegValue == 0x01) + { + return VCO_H; + + } + else + { + return VCO_L; + } + +} + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Commands.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Commands.c new file mode 100644 index 000000000..fe10f8022 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Commands.c @@ -0,0 +1,144 @@ +/** + ****************************************************************************** + * @file SPIRIT_Commands.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Management of SPIRIT Commands. + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Commands.h" +#include "MCU_Interface.h" + + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_Commands + * @{ + */ + + +/** + * @defgroup Commands_Private_TypesDefinitions Commands Private TypesDefinitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Commands_Private_Defines Commands Private Defines + * @{ + */ + +/** + *@} + */ + +/** + * @defgroup Commands_Private_Macros Commands Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Commands_Private_Variables Commands Private Variables + * @{ + */ + +/** + *@} + */ + + + +/** + * @defgroup Commands_Private_FunctionPrototypes Commands Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Commands_Private_Functions Commands Private Functions + * @{ + */ + +/** + * @brief Sends a specific command to SPIRIT. + * @param xCommandCode code of the command to send. + This parameter can be any value of @ref SpiritCmd. + * @retval None. + */ +void SpiritCmdStrobeCommand(SpiritCmd xCommandCode) +{ + /* Check the parameters */ + s_assert_param(IS_SPIRIT_CMD(xCommandCode)); + + g_xStatus = SpiritSpiCommandStrobes((uint8_t) xCommandCode); +} + + +/** + *@} + */ + + +/** + *@} + */ + + +/** + *@} + */ + + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Csma.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Csma.c new file mode 100644 index 000000000..c5f3b55f2 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Csma.c @@ -0,0 +1,600 @@ +/** + ****************************************************************************** + * @file SPIRIT_Csma.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT CSMA. + * @details + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Csma.h" +#include "MCU_Interface.h" + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_Csma + * @{ + */ + + +/** + * @defgroup Csma_Private_TypesDefinitions CSMA Private TypesDefinitions + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup Csma_Private_Defines CSMA Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Csma_Private_Macros CSMA Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Csma_Private_Variables CSMA Private Variables + * @{ + */ + +/** + *@} + */ + + + +/** + * @defgroup Csma_Private_FunctionPrototypes CSMA Private FunctionPrototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Csma_Private_Functions CSMA Private Functions + * @{ + */ + + +/** + * @brief Initializes the SPIRIT CSMA according to the specified parameters in the CsmaInit. + * @param pxCsmaInit Csma init structure. + * This parameter is a pointer to @ref CsmaInit. + * @retval None. + */ +void SpiritCsmaInit(CsmaInit* pxCsmaInit) +{ + uint8_t tempRegValue[5]; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxCsmaInit->xCsmaPersistentMode)); + s_assert_param(IS_CCA_PERIOD(pxCsmaInit->xMultiplierTbit)); + s_assert_param(IS_CSMA_LENGTH(pxCsmaInit->xCcaLength)); + s_assert_param(IS_BU_COUNTER_SEED(pxCsmaInit->nBuCounterSeed)); + s_assert_param(IS_BU_PRESCALER(pxCsmaInit->cBuPrescaler)); + s_assert_param(IS_CMAX_NB(pxCsmaInit->cMaxNb)); + + /* CSMA BU counter seed (MSB) config */ + tempRegValue[0] = (uint8_t)(pxCsmaInit->nBuCounterSeed >> 8); + + /* CSMA BU counter seed (LSB) config */ + tempRegValue[1] = (uint8_t) pxCsmaInit->nBuCounterSeed; + + /* CSMA BU prescaler config and CCA period config */ + tempRegValue[2] = (pxCsmaInit->cBuPrescaler << 2) | pxCsmaInit->xMultiplierTbit; + + /* CSMA CCA length config and max number of back-off */ + tempRegValue[3] = (pxCsmaInit->xCcaLength | pxCsmaInit->cMaxNb); + + /* Reads the PROTOCOL1_BASE register value, to write the SEED_RELOAD and CSMA_PERS_ON fields */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[4]); + + /* Writes the new value for persistent mode */ + if(pxCsmaInit->xCsmaPersistentMode==S_ENABLE) + { + tempRegValue[4] |= PROTOCOL1_CSMA_PERS_ON_MASK; + } + else + { + tempRegValue[4] &= ~PROTOCOL1_CSMA_PERS_ON_MASK; + } + + /* Writes PROTOCOL1_BASE register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue[4]); + + /* Writes CSMA_CONFIGx_BASE registers */ + g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG3_BASE, 4, tempRegValue); + +} + + + /** + * @brief Returns the fitted structure CsmaInit starting from the registers values. + * @param pxCsmaInit Csma structure to be fitted. + * This parameter is a pointer to @ref CsmaInit. + * @retval None. + */ +void SpiritCsmaGetInfo(CsmaInit* pxCsmaInit) +{ + uint8_t tempRegValue[5]; + + /* Reads PROTOCOL1_BASE register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[4]); + + /* Reads CSMA_CONFIGx_BASE registers */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG3_BASE, 4, tempRegValue); + + /* Reads the bu counter seed */ + pxCsmaInit->nBuCounterSeed = (uint16_t)tempRegValue[1] | ((uint16_t)(tempRegValue[0] << 8)); + + /* Reads the bu prescaler */ + pxCsmaInit->cBuPrescaler = tempRegValue[2]>>2; + + /* Reads the Cca period */ + pxCsmaInit->xMultiplierTbit = (CcaPeriod)(tempRegValue[2] & 0x03); + + /* Reads the Cca length */ + pxCsmaInit->xCcaLength = (CsmaLength)(tempRegValue[3]&0xF0); + + /* Reads the max number of back off */ + pxCsmaInit->cMaxNb = tempRegValue[3] & 0x07; + + /* Reads the persistent mode enable bit */ + pxCsmaInit->xCsmaPersistentMode = (SpiritFunctionalState)((tempRegValue[4]>>1) & 0x01); + +} + + +/** + * @brief Enables or Disables the CSMA. + * @param xNewState the state of the CSMA mode. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritCsma(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PROTOCOL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Sets or resets the CSMA enable bit */ + if(xNewState==S_ENABLE) + { + tempRegValue |= PROTOCOL1_CSMA_ON_MASK; + } + else + { + tempRegValue &= ~PROTOCOL1_CSMA_ON_MASK; + } + + /* Writes the new value on the PROTOCOL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + +} + +/** + * @brief Gets the CSMA mode. Says if it is enabled or disabled. + * @param None. + * @retval SpiritFunctionalState: CSMA mode. + */ +SpiritFunctionalState SpiritCsmaGetCsma(void) +{ + uint8_t tempRegValue; + + /* Reads the PROTOCOL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Return if set or reset */ + if(tempRegValue & PROTOCOL1_CSMA_ON_MASK) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + +/** + * @brief Enables or Disables the persistent CSMA mode. + * @param xNewState the state of the persistent CSMA mode. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritCsmaPersistentMode(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PROTOCOL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Enables/disables the CSMA persistent mode */ + if(xNewState==S_ENABLE) + { + tempRegValue |= PROTOCOL1_CSMA_PERS_ON_MASK; + } + else + { + tempRegValue &= ~PROTOCOL1_CSMA_PERS_ON_MASK; + } + + /* Writes the new vaue on the PROTOCOL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Gets the persistent CSMA mode. + * @param None. + * @retval SpiritFunctionalState: CSMA persistent mode. + */ +SpiritFunctionalState SpiritCsmaGetPersistentMode(void) +{ + uint8_t tempRegValue; + + /* Reads the PROTOCOL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Return if set or reset */ + if(tempRegValue & PROTOCOL1_CSMA_PERS_ON_MASK) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + + +/** + * @brief Enables or Disables the seed reload mode (if enabled it reloads the back-off generator seed using the value written in the BU_COUNTER_SEED register). + * @param xNewState the state of the seed reload mode. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritCsmaSeedReloadMode(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PROTOCOL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Enables/disables the seed reload mode */ + if(xNewState==S_ENABLE) + { + tempRegValue |= PROTOCOL1_SEED_RELOAD_MASK; + } + else + { + tempRegValue &= ~PROTOCOL1_SEED_RELOAD_MASK; + } + + /* Writes the new value on the PROTOCOL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Gets the seed reload mode. + * @param None. + * @retval SpiritFunctionalState: CSMA seed reload mode. + */ +SpiritFunctionalState SpiritCsmaGetSeedReloadMode(void) +{ + uint8_t tempRegValue; + + /* Reads the PROTOCOL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Return if set or reset */ + if(tempRegValue & PROTOCOL1_SEED_RELOAD_MASK) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } +} + + +/** + * @brief Sets the BU counter seed (BU_COUNTER_SEED register). The CSMA back off time is given by the formula: BO = rand(2^NB)*BU. + * @param nBuCounterSeed seed of the random number generator used to apply the BBE algorithm. + * This parameter is an uint16_t. + * @retval None. + */ +void SpiritCsmaSetBuCounterSeed(uint16_t nBuCounterSeed) +{ + uint8_t tempRegValue[2]; + + /* Check parameters */ + s_assert_param(IS_BU_COUNTER_SEED(nBuCounterSeed)); + + /* Build value (MSB)*/ + tempRegValue[0]=(uint8_t)(nBuCounterSeed>>8); + /* Build value (LSB) */ + tempRegValue[1]=(uint8_t)nBuCounterSeed; + + /* Writes the CSMA_CONFIG3 registers */ + g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG3_BASE, 2, tempRegValue); + +} + +/** + * @brief Returns the BU counter seed (BU_COUNTER_SEED register). + * @param None. + * @retval uint16_t Seed of the random number generator used to apply the BBE algorithm. + */ +uint16_t SpiritCsmaGetBuCounterSeed(void) +{ + uint8_t tempRegValue[2]; + + /* Reads the CSMA_CONFIGx registers value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG3_BASE, 2, tempRegValue); + + /* Build the counter seed and return it */ + return ((uint16_t)tempRegValue[1] + (((uint16_t)tempRegValue[0])<<8)); + +} + + +/** + * @brief Sets the BU prescaler. The CSMA back off time is given by the formula: BO = rand(2^NB)*BU. + * @param cBuPrescaler used to program the back-off unit BU. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritCsmaSetBuPrescaler(uint8_t cBuPrescaler) +{ + uint8_t tempRegValue; + + /* Check parameters */ + s_assert_param(IS_BU_PRESCALER(cBuPrescaler)); + + /* Reads the CSMA_CONFIG1 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); + + /* Build the new value for the BU prescaler */ + tempRegValue &= 0x03; + tempRegValue |= (cBuPrescaler<<2); + + /* Writes the new value on the CSMA_CONFIG1_BASE register */ + g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the BU prescaler. + * @param None. + * @retval uint8_t Value back-off unit (BU). + */ +uint8_t SpiritCsmaGetBuPrescaler(void) +{ + uint8_t tempRegValue; + + /* Reads the CSMA_CONFIG1 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); + + /* Build and return the BU prescaler value */ + return (tempRegValue >> 2); + +} + + +/** + * @brief Sets the CCA period. + * @param xMultiplierTbit value of CCA period to store. + * This parameter can be a value of @ref CcaPeriod. + * @retval None. + */ +void SpiritCsmaSetCcaPeriod(CcaPeriod xMultiplierTbit) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_CCA_PERIOD(xMultiplierTbit)); + + /* Reads the CSMA_CONFIG1 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); + + /* Build the new value setting the the CCA period */ + tempRegValue &= 0xFC; + tempRegValue |= xMultiplierTbit; + + /* Writes the new value on the CSMA_CONFIG1 register */ + g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the CCA period. + * @param None. + * @retval CcaPeriod CCA period. + */ +CcaPeriod SpiritCsmaGetCcaPeriod(void) +{ + uint8_t tempRegValue; + + /* Reads the CSMA_CONFIG1 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); + + /* Build and return the CCA period value */ + return (CcaPeriod)(tempRegValue & 0x03); + +} + + +/** + * @brief Sets the CCA length. + * @param xCcaLength the CCA length (a value between 1 and 15 that multiplies the CCA period). + * This parameter can be any value of @ref CsmaLength. + * @retval None. + */ +void SpiritCsmaSetCcaLength(CsmaLength xCcaLength) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_CSMA_LENGTH(xCcaLength)); + + /* Reads the CSMA_CONFIG0 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); + + /* Build the value of CCA length to be set */ + tempRegValue &= 0x0F; + tempRegValue |= xCcaLength; + + /* Writes the new value on the CSMA_CONFIG0 register */ + g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the CCA length. + * @param None. + * @retval uint8_t CCA length. + */ +uint8_t SpiritCsmaGetCcaLength(void) +{ + uint8_t tempRegValue; + + /* Reads the CSMA_CONFIG0 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); + + /* Build and return the CCA length */ + return tempRegValue >> 4; + +} + + +/** + * @brief Sets the max number of back-off. If reached Spirit stops the transmission. + * @param cMaxNb the max number of back-off. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritCsmaSetMaxNumberBackoff(uint8_t cMaxNb) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_CMAX_NB(cMaxNb)); + + /* Reads the CSMA_CONFIG0 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); + + /* Build the value of max back off to be set */ + tempRegValue &= 0xF8; + tempRegValue |= cMaxNb; + + /* Writes the new value on the CSMA_CONFIG0 register */ + g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); +} + +/** + * @brief Returns the max number of back-off. + * @param None. + * @retval uint8_t Max number of back-off. + */ +uint8_t SpiritCsmaGetMaxNumberBackoff(void) +{ + uint8_t tempRegValue; + + /* Reads the CSMA_CONFIG0 register value */ + g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); + + /* Build and return the max number of back-off */ + return (tempRegValue & 0x07); + +} + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_DirectRF.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_DirectRF.c new file mode 100644 index 000000000..38e7fcdbf --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_DirectRF.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file SPIRIT_DirectRF.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT direct transmission / receive modes. + * @details + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_DirectRF.h" +#include "MCU_Interface.h" + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_DirectRf + * @{ + */ + + +/** + * @defgroup DirectRf_Private_TypesDefinitions Direct RF Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup DirectRf_Private_Defines Direct RF Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup DirectRf_Private_Macros Direct RF Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup DirectRf_Private_Variables Direct RF Private Variables + * @{ + */ + +/** + *@} + */ + + + +/** + * @defgroup DirectRf_Private_FunctionPrototypes Direct RF Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup DirectRf_Private_Functions Direct RF Private Functions + * @{ + */ + +/** + * @brief Sets the DirectRF RX mode of SPIRIT. + * @param xDirectRx code of the desired mode. + * This parameter can be any value of @ref DirectRx. + * @retval None. + */ +void SpiritDirectRfSetRxMode(DirectRx xDirectRx) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_DIRECT_RX(xDirectRx)); + + /* Reads the register value */ + SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Build the value to be stored */ + tempRegValue &= ~PCKTCTRL3_RX_MODE_MASK; + tempRegValue |= (uint8_t)xDirectRx; + + /* Writes value on register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the DirectRF RX mode of SPIRIT. + * @param None. + * @retval DirectRx Direct Rx mode. + */ +DirectRx SpiritDirectRfGetRxMode(void) +{ + uint8_t tempRegValue; + + /* Reads the register value and mask the RX_Mode field */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Rebuild and return value */ + return (DirectRx)(tempRegValue & 0x30); + +} + + +/** + * @brief Sets the TX mode of SPIRIT. + * @param xDirectTx code of the desired source. + * This parameter can be any value of @ref DirectTx. + * @retval None. + */ +void SpiritDirectRfSetTxMode(DirectTx xDirectTx) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_DIRECT_TX(xDirectTx)); + + /* Reads the register value */ + SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Build the value to be stored */ + tempRegValue &= ~PCKTCTRL1_TX_SOURCE_MASK; + tempRegValue |= (uint8_t)xDirectTx; + + /* Writes value on register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the DirectRF TX mode of SPIRIT. + * @param None. + * @retval DirectTx Direct Tx mode. + */ +DirectTx SpiritDirectRfGetTxMode(void) +{ + uint8_t tempRegValue; + + /* Reads the register value and mask the RX_Mode field */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Returns value */ + return (DirectTx)(tempRegValue & 0x0C); + +} + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_General.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_General.c new file mode 100644 index 000000000..8bcb4337b --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_General.c @@ -0,0 +1,449 @@ +/** + ****************************************************************************** + * @file SPIRIT_General.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT General functionalities. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_General.h" +#include "MCU_Interface.h" + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_General + * @{ + */ + + +/** + * @defgroup General_Private_TypesDefinitions General Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup General_Private_Defines General Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup General_Private_Macros General Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup General_Private_Variables General Private Variables + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup General_Private_FunctionPrototypes General Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup General_Private_Functions General Private Functions + * @{ + */ + +/** + * @brief Enables or Disables the output of battery level detector. + * @param xNewState new state for battery level detector. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None + */ +void SpiritGeneralBatteryLevel(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the ANA_FUNC_CONF0_BASE register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + + /* Build the value to be stored */ + if(xNewState == S_ENABLE) + { + tempRegValue |= BATTERY_LEVEL_MASK; + } + else + { + tempRegValue &= ~BATTERY_LEVEL_MASK; + } + + /* Writes the new value */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets the battery level. + * @param xBatteryLevel new state for battery level. + * This parameter can be a value of @ref BatteryLevel. + * @retval None. + */ +void SpiritGeneralSetBatteryLevel(BatteryLevel xBatteryLevel) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_BLD_LVL(xBatteryLevel)); + + /* Reads the ANA_FUNC_CONF1_BASE register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); + + /* Build the value to be stored */ + tempRegValue &= ~ANA_FUNC_CONF1_SET_BLD_LVL_MASK; + switch(xBatteryLevel) + { + case BLD_LVL_2_7_V: + tempRegValue |= BLD_LVL_2_7; + break; + case BLD_LVL_2_5_V: + tempRegValue |= BLD_LVL_2_5; + break; + case BLD_LVL_2_3_V: + tempRegValue |= BLD_LVL_2_3; + break; + case BLD_LVL_2_1_V: + tempRegValue |= BLD_LVL_2_1; + break; + } + + /* Writes the new value */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the settled battery level. + * @param None. + * @retval BatteryLevel Settled battery level. This parameter can be a value of @ref BatteryLevel. + */ +BatteryLevel SpiritGeneralGetBatteryLevel(void) +{ + uint8_t tempRegValue; + + /* Reads the ANA_FUNC_CONF1_BASE register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); + + /* Mask the battery level field and returns the settled battery level */ + return ((BatteryLevel)(tempRegValue & ANA_FUNC_CONF1_SET_BLD_LVL_MASK)); + +} + + +/** + * @brief Enables or Disables the output of brown out detector. + * @param xNewState new state for brown out detector. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritGeneralBrownOut(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the ANA_FUNC_CONF0_BASE register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + + /* Build the value to be stored */ + if(xNewState == S_ENABLE) + { + tempRegValue |= BROWN_OUT_MASK; + } + else + { + tempRegValue &= ~BROWN_OUT_MASK; + } + + /* Writes value on register */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets High Power Mode. + * @param xNewState new state for High Power Mode. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritGeneralHighPwr(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the ANA_FUNC_CONF0_BASE register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + + /* Build the value to write */ + if(xNewState == S_ENABLE) + { + tempRegValue |= HIGH_POWER_MODE_MASK; + } + else + { + tempRegValue &= ~HIGH_POWER_MODE_MASK; + } + + /* Writes the new value on register */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets External Reference. + * @param xExtMode new state for the external reference. + * This parameter can be: MODE_EXT_XO or MODE_EXT_XIN. + * @retval None. + */ +void SpiritGeneralSetExtRef(ModeExtRef xExtMode) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_MODE_EXT(xExtMode)); + + /* Reads the ANA_FUNC_CONF0_BASE register value */ + SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + + /* Build the value to write */ + if(xExtMode == MODE_EXT_XO) + { + tempRegValue &= ~EXT_REF_MASK; + } + else + { + tempRegValue |= EXT_REF_MASK; + } + + /* Writes value on register */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns External Reference. + * @param None. + * @retval ModeExtRef Settled external reference. + * This parameter can be: MODE_EXT_XO or MODE_EXT_XIN. + */ +ModeExtRef SpiritGeneralGetExtRef(void) +{ + uint8_t tempRegValue; + + /* Reads the ANA_FUNC_CONF0_BASE register value and return the result */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + + /* Mask the EXT_REF field field and returns the settled reference signal */ + return ((ModeExtRef)((tempRegValue & 0x10)>>4)); + +} + + +/** + * @brief Sets XO gm at startup. + * @param xGm transconductance value of XO at startup. + * This parameter can be a value of @ref GmConf. + * @retval None. + */ +void SpiritGeneralSetXoGm(GmConf xGm) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_GM_CONF(xGm)); + + /* Reads the ANA_FUNC_CONF1_BASE register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); + + /* Build the value to write */ + tempRegValue &= ~ANA_FUNC_CONF1_GMCONF_MASK; + switch(xGm) + { + case GM_SU_13_2: + tempRegValue |= GM_13_2; + break; + case GM_SU_18_2: + tempRegValue |= GM_18_2; + break; + case GM_SU_21_5: + tempRegValue |= GM_21_5; + break; + case GM_SU_25_6: + tempRegValue |= GM_25_6; + break; + case GM_SU_28_8: + tempRegValue |= GM_28_8; + break; + case GM_SU_33_9: + tempRegValue |= GM_33_9; + break; + case GM_SU_38_5: + tempRegValue |= GM_38_5; + break; + case GM_SU_43_0: + tempRegValue |= GM_43_0; + break; + } + + /* Writes new value on register */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the configured XO gm at startup. + * @param None. + * @retval GmConf Settled XO gm. This parameter can be a value of @ref GmConf. + */ +GmConf SpiritGeneralGetXoGm(void) +{ + uint8_t tempRegValue; + + /* Reads the ANA_FUNC_CONF1_BASE register value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); + + /* Mask the GM_CONF field field and returns the settled transconductance of the XO at startup */ + return ((GmConf)((tempRegValue & 0x1C)>>2)); + +} + + +/** + * @brief Returns the settled packet format. + * @param None. + * @retval PacketType Settled packet type. This parameter can be a value of @ref PacketType. + */ +PacketType SpiritGeneralGetPktType(void) +{ + uint8_t tempRegValue; + + /* Reads the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* cast and return value */ + return (PacketType)(tempRegValue>>6); + +} + + + +/** + * @brief Returns device part number. + * @param None. + * @retval uint16_t Device part number. + */ +uint16_t SpiritGeneralGetDevicePartNumber(void) +{ + uint8_t tempRegValue[2]; + + /* Reads the register value containing the device part number */ + g_xStatus = SpiritSpiReadRegisters(DEVICE_INFO1_PARTNUM, 2, tempRegValue); + + return ((((uint16_t)tempRegValue[0])<<8) | ((uint16_t)tempRegValue[1])); + +} + +/** + * @brief Returns SPIRIT RF board version. + * @param None. + * @retval SPIRIT RF board version: 0x30 is the only admitted value + */ +uint8_t SpiritGeneralGetSpiritVersion(void) +{ + uint8_t ver; + SpiritSpiReadRegisters(DEVICE_INFO0_VERSION, 1, &ver); + return ver; +} + +/** + *@} + */ + + +/** + *@} + */ + + +/** + *@} + */ + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Gpio.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Gpio.c new file mode 100644 index 000000000..d2a15dd96 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Gpio.c @@ -0,0 +1,458 @@ +/** + ****************************************************************************** + * @file SPIRIT_Gpio.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief This file provides all the low level API to manage SPIRIT GPIO. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Gpio.h" +#include "MCU_Interface.h" + + +/** @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** @addtogroup SPIRIT_Gpio + * @{ + */ + + +/** @defgroup Gpio_Private_TypesDefinitions GPIO Private Types Definitions + * @{ + */ + + +/** + * @} + */ + + +/** @defgroup Gpio_Private_Defines GPIO Private Defines + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Gpio_Private_Macros GPIO Private Macros + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Gpio_Private_Variables GPIO Private Variables + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Gpio_Private_FunctionPrototypes GPIO Private Function Prototypes + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Gpio_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @brief Initializes the SPIRIT GPIOx according to the specified + * parameters in the pxGpioInitStruct. + * @param pxGpioInitStruct pointer to a SGpioInit structure that + * contains the configuration information for the specified SPIRIT GPIO. + * @retval None. + */ +void SpiritGpioInit(SGpioInit* pxGpioInitStruct) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_GPIO(pxGpioInitStruct->xSpiritGpioPin)); + s_assert_param(IS_SPIRIT_GPIO_MODE(pxGpioInitStruct->xSpiritGpioMode)); + s_assert_param(IS_SPIRIT_GPIO_IO(pxGpioInitStruct->xSpiritGpioIO)); + + tempRegValue = ((uint8_t)(pxGpioInitStruct->xSpiritGpioMode) | (uint8_t)(pxGpioInitStruct->xSpiritGpioIO)); + + g_xStatus = SpiritSpiWriteRegisters(pxGpioInitStruct->xSpiritGpioPin, 1, &tempRegValue); + +} + + +/** + * @brief Enables or Disables the output of temperature sensor on SPIRIT GPIO_0. + * @param xNewState new state for temperature sensor. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritGpioTemperatureSensor(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + uint8_t gpio0tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the ANA_FUNC_CONF0 register and mask the result to enable or disable the + temperature sensor */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= TEMPERATURE_SENSOR_MASK; + } + else + { + tempRegValue &= (~TEMPERATURE_SENSOR_MASK); + gpio0tempRegValue = 0x0A; /* Default value */ + } + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + + /* Sets the SPIRIT GPIO_0 according to input request */ + g_xStatus = SpiritSpiWriteRegisters(GPIO0_CONF_BASE, 1, &gpio0tempRegValue); + +} + + +/** + * @brief Forces SPIRIT GPIO_x configured as digital output, to VDD or GND. + * @param xGpioX Specifies the GPIO to be configured. + * This parameter can be one of following parameters: + * @arg SPIRIT_GPIO_0: SPIRIT GPIO_0 + * @arg SPIRIT_GPIO_1: SPIRIT GPIO_1 + * @arg SPIRIT_GPIO_2: SPIRIT GPIO_2 + * @arg SPIRIT_GPIO_3: SPIRIT GPIO_3 + * @param xLevel Specifies the level. + * This parameter can be: HIGH or LOW. + * @retval None. + */ +void SpiritGpioSetLevel(SpiritGpioPin xGpioX, OutputLevel xLevel) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_GPIO(xGpioX)); + s_assert_param(IS_SPIRIT_GPIO_LEVEL(xLevel)); + + /* Reads the SPIRIT_GPIOx register and mask the GPIO_SELECT field */ + g_xStatus = SpiritSpiReadRegisters(xGpioX, 1, &tempRegValue); + tempRegValue &= 0x04; + + /* Sets the value of the SPIRIT GPIO register according to the specified level */ + if(xLevel == HIGH) + { + tempRegValue |= (uint8_t)SPIRIT_GPIO_DIG_OUT_VDD | (uint8_t)SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP; + } + else + { + tempRegValue |= (uint8_t)SPIRIT_GPIO_DIG_OUT_GND | (uint8_t)SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP; + } + + /* Writes the SPIRIT GPIO register */ + g_xStatus = SpiritSpiWriteRegisters(xGpioX, 1, &tempRegValue); + +} + + +/** + * @brief Returns output value (VDD or GND) of SPIRIT GPIO_x, when it is configured as digital output. + * @param xGpioX Specifies the GPIO to be read. + * This parameter can be one of following parameters: + * @arg SPIRIT_GPIO_0: SPIRIT GPIO_0 + * @arg SPIRIT_GPIO_1: SPIRIT GPIO_1 + * @arg SPIRIT_GPIO_2: SPIRIT GPIO_2 + * @arg SPIRIT_GPIO_3: SPIRIT GPIO_3 + * @retval OutputLevel Logical level of selected GPIO configured as digital output. + * This parameter can be: HIGH or LOW. + */ +OutputLevel SpiritGpioGetLevel(SpiritGpioPin xGpioX) +{ + uint8_t tempRegValue = 0x00; + OutputLevel level; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_GPIO(xGpioX)); + + /* Reads the SPIRIT_GPIOx register */ + g_xStatus = SpiritSpiReadRegisters(xGpioX, 1, &tempRegValue); + + /* Mask the GPIO_SELECT field and returns the value according */ + tempRegValue &= 0xF8; + if(tempRegValue == SPIRIT_GPIO_DIG_OUT_VDD) + { + level = HIGH; + } + else + { + level = LOW; + } + + return level; + +} + + +/** + * @brief Enables or Disables the MCU clock output. + * @param xNewState new state for the MCU clock output. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritGpioClockOutput(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the MCU_CK_CONF register and mask the result to enable or disable the clock output */ + g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + + if(xNewState) + { + tempRegValue |= MCU_CK_ENABLE; + } + else + { + tempRegValue &= (~MCU_CK_ENABLE); + } + + /* Writes the MCU_CK_CONF register */ + g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Initializes the SPIRIT Clock Output according to the specified + * parameters in the xClockOutputInitStruct. + * @param pxClockOutputInitStruct pointer to a ClockOutputInit structure that + * contains the configuration information for the SPIRIT Clock Output. + * @retval None. + * @note The function SpiritGpioClockOutput() must be called in order to enable + * or disable the MCU clock dividers. + */ +void SpiritGpioClockOutputInit(ClockOutputInit* pxClockOutputInitStruct) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_XO(pxClockOutputInitStruct->xClockOutputXOPrescaler)); + s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_RCO(pxClockOutputInitStruct->xClockOutputRCOPrescaler)); + s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_EXTRA_CYCLES(pxClockOutputInitStruct->xExtraClockCycles)); + + /* Calculates the register value to write according to the specified configuration */ + tempRegValue = ((uint8_t)(pxClockOutputInitStruct->xClockOutputXOPrescaler) | (uint8_t)(pxClockOutputInitStruct->xClockOutputRCOPrescaler) | \ + (uint8_t)(pxClockOutputInitStruct->xExtraClockCycles)); + + /* Writes the MCU_CLOCK register */ + g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets the XO ratio as clock output. + * @param xXOPrescaler the XO prescaler to be used as clock output. + * This parameter can be any value of @ref ClockOutputXOPrescaler . + * @retval None + */ +void SpiritGpioSetXOPrescaler(ClockOutputXOPrescaler xXOPrescaler) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_XO(xXOPrescaler)); + + /* Reads the MCU_CLK_CONFIG register */ + g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + + /* Mask the XO_RATIO field and writes the new value */ + tempRegValue &= 0x61; + tempRegValue |= ((uint8_t)xXOPrescaler); + + /* Writes the new XO prescaler in the MCU_CLOCK register */ + g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the settled XO prescaler as clock output. + * @param None. + * @retval ClockOutputXOPrescaler Settled XO prescaler used for clock + * output. This parameter can be a value of @ref ClockOutputXOPrescaler . + */ +ClockOutputXOPrescaler SpiritGpioGetXOPrescaler(void) +{ + uint8_t tempRegValue = 0x00; + + /* Reads the MCU_CLK_CONFIG register */ + g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + + /* Mask the XO_RATIO field and return the value */ + return ((ClockOutputXOPrescaler)(tempRegValue & 0x1E)); + +} + + +/** + * @brief Sets the RCO ratio as clock output + * @param xRCOPrescaler the RCO prescaler to be used as clock output. + * This parameter can be any value of @ref ClockOutputRCOPrescaler . + * @retval None. + */ +void SpiritGpioSetRCOPrescaler(ClockOutputRCOPrescaler xRCOPrescaler) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_RCO(xRCOPrescaler)); + + /* Reads the MCU_CLK_CONFIG register */ + g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + + /* Mask the RCO_RATIO field and writes the new value */ + tempRegValue &= 0xFE; + tempRegValue |= ((uint8_t)xRCOPrescaler); + + /* Writes the new RCO prescaler in the MCU_CLOCK register */ + g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the settled RCO prescaler as clock output. + * @param None. + * @retval ClockOutputRCOPrescaler Settled RCO prescaler used for clock + * output. This parameter can be a value of @ref ClockOutputRCOPrescaler. + */ +ClockOutputRCOPrescaler SpiritGpioGetRCOPrescaler(void) +{ + uint8_t tempRegValue = 0x00; + + /* Reads the MCU_CLK_CONFIG register */ + g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + + /* Mask the RCO_RATIO field and returns the value */ + return ((ClockOutputRCOPrescaler)(tempRegValue & 0x01)); + +} + + +/** + * @brief Sets the RCO ratio as clock output. + * @param xExtraCycles the number of extra clock cycles provided before switching + * to STANDBY state. This parameter can be any value of @ref ExtraClockCycles . + * @retval None. + */ +void SpiritGpioSetExtraClockCycles(ExtraClockCycles xExtraCycles) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_EXTRA_CYCLES(xExtraCycles)); + + /* Reads the MCU_CLK_CONFIG register */ + g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + + /* Mask the CLOCK_TAIL field and writes the new value */ + tempRegValue &= 0x9F; + tempRegValue |= ((uint8_t)xExtraCycles); + + /* Writes the new number of extra clock cycles in the MCU_CLOCK register */ + g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the settled RCO prescaler as clock output. + * @param None. + * @retval ExtraClockCycles Settled number of extra clock cycles + * provided before switching to STANDBY state. This parameter can be + * any value of @ref ExtraClockCycles . + */ +ExtraClockCycles SpiritGpioGetExtraClockCycles(void) +{ + uint8_t tempRegValue = 0x00; + + /* Reads the MCU_CLK_CONFIG register */ + g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); + + /* Mask the CLOCK_TAIL field and returns the value */ + return ((ExtraClockCycles)(tempRegValue & 0x60)); + +} + + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Irq.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Irq.c new file mode 100644 index 000000000..8ef9d9061 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Irq.c @@ -0,0 +1,353 @@ +/** + ****************************************************************************** + * @file SPIRIT_Irq.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT IRQs. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Irq.h" +#include "MCU_Interface.h" + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_Irq + * @{ + */ + + +/** + * @defgroup Irq_Private_TypesDefinitions IRQ Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Irq_Private_Defines IRQ Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Irq_Private_Macros IRQ Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Irq_Private_Variables IRQ Private Variables + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup Irq_Private_FunctionPrototypes IRQ Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Irq_Private_Functions IRQ Private Functions + * @{ + */ + + +/** + * @brief De initializate the SpiritIrqs structure setting all the bitfield to 0. + * Moreover, it sets the IRQ mask registers to 0x00000000, disabling all IRQs. + * @param pxIrqInit pointer to a variable of type @ref SpiritIrqs, in which all the + * bitfields will be settled to zero. + * @retval None. + */ +void SpiritIrqDeInit(SpiritIrqs* pxIrqInit) +{ + uint8_t tempRegValue[4]={0x00,0x00,0x00,0x00}; + + if(pxIrqInit!=NULL) + { + uint32_t tempValue = 0x00000000; + + /* Sets the bitfields of passed structure to one */ + *pxIrqInit = (*(SpiritIrqs*)&tempValue); + } + + /* Writes the IRQ_MASK registers */ + g_xStatus = SpiritSpiWriteRegisters(IRQ_MASK3_BASE, 4, tempRegValue); +} + + +/** + * @brief Enables all the IRQs according to the user defined pxIrqInit structure. + * @param pxIrqInit pointer to a variable of type @ref SpiritIrqs, through which the + * user enable specific IRQs. This parameter is a pointer to a SpiritIrqs. + * For example suppose to enable only the two IRQ Low Battery Level and Tx Data Sent: + * @code + * SpiritIrqs myIrqInit = {0}; + * myIrqInit.IRQ_LOW_BATT_LVL = 1; + * myIrqInit.IRQ_TX_DATA_SENT = 1; + * SpiritIrqInit(&myIrqInit); + * @endcode + * @retval None. + */ +void SpiritIrqInit(SpiritIrqs* pxIrqInit) +{ + uint8_t tempRegValue[4]; + uint8_t* tmpPoint; + + /* Cast the bitfields structure in an array of char using */ + tmpPoint = (uint8_t*)(pxIrqInit); + for(char i=0; i<4; i++) + { + tempRegValue[3-i]= tmpPoint[i]; + } + + /* Writes the IRQ_MASK registers */ + g_xStatus = SpiritSpiWriteRegisters(IRQ_MASK3_BASE, 4, tempRegValue); + +} + + +/** + * @brief Enables or disables a specific IRQ. + * @param xIrq IRQ to enable or disable. + * This parameter can be any value of @ref IrqList. + * @param xNewState new state for the IRQ. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritIrq(IrqList xIrq, SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue[4]; + uint32_t tempValue = 0; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_IRQ_LIST(xIrq)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the IRQ_MASK registers */ + g_xStatus = SpiritSpiReadRegisters(IRQ_MASK3_BASE, 4, tempRegValue); + + /* Build the IRQ mask word */ + for(char i=0; i<4; i++) + { + tempValue += ((uint32_t)tempRegValue[i])<<(8*(3-i)); + } + + /* Rebuild the new mask according to user request */ + if(xNewState == S_DISABLE) + { + tempValue &= (~xIrq); + } + else + { + tempValue |= (xIrq); + } + + /* Build the array of bytes to write in the IRQ_MASK registers */ + for(char j=0; j<4; j++) + { + tempRegValue[j] = (uint8_t)(tempValue>>(8*(3-j))); + } + + /* Writes the new IRQ mask in the corresponding registers */ + g_xStatus = SpiritSpiWriteRegisters(IRQ_MASK3_BASE, 4, tempRegValue); + +} + + +/** + * @brief Fills a pointer to a structure of SpiritIrqs type reading the IRQ_MASK registers. + * @param pxIrqMask pointer to a variable of type @ref SpiritIrqs, through which the + * user can read which IRQs are enabled. All the bitfields equals to zero correspond + * to enabled IRQs, while all the bitfields equals to one correspond to disabled IRQs. + * This parameter is a pointer to a SpiritIrqs. + * For example suppose that the Power On Reset and RX Data ready are the only enabled IRQs. + * @code + * SpiritIrqs myIrqMask; + * SpiritIrqGetStatus(&myIrqMask); + * @endcode + * Then + * myIrqMask.IRQ_POR and myIrqMask.IRQ_RX_DATA_READY are equal to 0 + * while all the other bitfields are equal to one. + * @retval None. + */ +void SpiritIrqGetMask(SpiritIrqs* pxIrqMask) +{ + uint8_t tempRegValue[4]; + uint8_t* pIrqPointer = (uint8_t*)pxIrqMask; + + /* Reads IRQ_MASK registers */ + g_xStatus = SpiritSpiReadRegisters(IRQ_MASK3_BASE, 4, tempRegValue); + + /* Build the IRQ mask word */ + for(char i=0; i<4; i++) + { + *pIrqPointer = tempRegValue[3-i]; + pIrqPointer++; + } + +} + + +/** + * @brief Filla a pointer to a structure of SpiritIrqs type reading the IRQ_STATUS registers. + * @param pxIrqStatus pointer to a variable of type @ref SpiritIrqs, through which the + * user can read the status of all the IRQs. All the bitfields equals to one correspond + * to the raised interrupts. This parameter is a pointer to a SpiritIrqs. + * For example suppose that the XO settling timeout is raised as well as the Sync word + * detection. + * @code + * SpiritIrqs myIrqStatus; + * SpiritIrqGetStatus(&myIrqStatus); + * @endcode + * Then + * myIrqStatus.IRQ_XO_COUNT_EXPIRED and myIrqStatus.IRQ_VALID_SYNC are equals to 1 + * while all the other bitfields are equals to zero. + * @retval None. + */ +void SpiritIrqGetStatus(SpiritIrqs* pxIrqStatus) +{ + uint8_t tempRegValue[4]; + uint8_t* pIrqPointer = (uint8_t*)pxIrqStatus; + + /* Reads IRQ_STATUS registers */ + g_xStatus = SpiritSpiReadRegisters(IRQ_STATUS3_BASE, 4, tempRegValue); + + /* Build the IRQ Status word */ + for(uint8_t i=0; i<4; i++) + { + *pIrqPointer = tempRegValue[3-i]; + pIrqPointer++; + } +} + + +/** + * @brief Clear the IRQ status registers. + * @param None. + * @retval None. + */ +void SpiritIrqClearStatus(void) +{ + uint8_t tempRegValue[4]; + + /* Reads the IRQ_STATUS registers clearing all the flags */ + g_xStatus = SpiritSpiReadRegisters(IRQ_STATUS3_BASE, 4, tempRegValue); + +} + + +/** + * @brief Verifies if a specific IRQ has been generated. + * The call resets all the IRQ status, so it can't be used in case of multiple raising interrupts. + * @param xFlag IRQ flag to be checked. + * This parameter can be any value of @ref IrqList. + * @retval SpiritBool S_TRUE or S_FALSE. + */ +SpiritBool SpiritIrqCheckFlag(IrqList xFlag) +{ + uint8_t tempRegValue[4]; + uint32_t tempValue = 0; + SpiritBool flag; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_IRQ_LIST(xFlag)); + + /* Reads registers and build the status word */ + g_xStatus = SpiritSpiReadRegisters(IRQ_STATUS3_BASE, 4, tempRegValue); + for(uint8_t i=0; i<4; i++) + { + tempValue += ((uint32_t)tempRegValue[i])<<(8*(3-i)); + } + + if(tempValue & xFlag) + { + flag = S_TRUE; + } + else + { + flag = S_FALSE; + } + + return flag; + +} + + +/** + *@} + */ + + +/** + *@} + */ + + +/** + *@} + */ + + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_LinearFifo.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_LinearFifo.c new file mode 100644 index 000000000..755b76652 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_LinearFifo.c @@ -0,0 +1,338 @@ +/** + ****************************************************************************** + * @file SPIRIT_LinearFifo.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT Fifo. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_LinearFifo.h" +#include "MCU_Interface.h" + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_LinearFifo + * @{ + */ + + +/** + * @defgroup LinearFifo_Private_TypesDefinitions Linear FIFO Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup LinearFifo_Private_Defines Linear FIFO Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup LinearFifo_Private_Macros Linear FIFO Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup LinearFifo_Private_Variables Linear FIFO Private Variables + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup LinearFifo_Private_FunctionPrototypes Linear FIFO Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup LinearFifo_Private_Functions Linear FIFO Private Functions + * @{ + */ + +/** + * @brief Returns the number of elements in the Rx FIFO. + * @param None. + * @retval uint8_t Number of elements in the Rx FIFO. + */ +uint8_t SpiritLinearFifoReadNumElementsRxFifo(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(LINEAR_FIFO_STATUS0_BASE, 1, &tempRegValue); + + /* Build and return value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Returns the number of elements in the Tx FIFO. + * @param None. + * @retval uint8_t Number of elements in the Tx FIFO. + */ +uint8_t SpiritLinearFifoReadNumElementsTxFifo(void) +{ + uint8_t tempRegValue; + + /* Reads the number of elements in TX FIFO and return the value */ + g_xStatus = SpiritSpiReadRegisters(LINEAR_FIFO_STATUS1_BASE, 1, &tempRegValue); + + /* Build and return value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Sets the almost full threshold for the Rx FIFO. When the number of elements in RX FIFO reaches this value an interrupt can be generated to the MCU. + * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is set to 7 the almost + * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. + * @param cThrRxFifo almost full threshold. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritLinearFifoSetAlmostFullThresholdRx(uint8_t cThrRxFifo) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_FIFO_THR(cThrRxFifo)); + + /* Build the register value */ + tempRegValue = cThrRxFifo & 0x7F; + + /* Writes the Almost Full threshold for RX in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG3_RXAFTHR_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the almost full threshold for RX FIFO. + * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is 7 the almost + * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. + * @param None. + * @retval uint8_t Almost full threshold for Rx FIFO. + */ +uint8_t SpiritLinearFifoGetAlmostFullThresholdRx(void) +{ + uint8_t tempRegValue; + + /* Reads the almost full threshold for RX FIFO and return the value */ + g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG3_RXAFTHR_BASE, 1, &tempRegValue); + + /* Build and return value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Sets the almost empty threshold for the Rx FIFO. When the number of elements in RX FIFO reaches this value an interrupt can be generated to the MCU. + * @param cThrRxFifo almost empty threshold. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritLinearFifoSetAlmostEmptyThresholdRx(uint8_t cThrRxFifo) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_FIFO_THR(cThrRxFifo)); + + /* Build the register value */ + tempRegValue = cThrRxFifo & 0x7F; + + /* Writes the Almost Empty threshold for RX in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG2_RXAETHR_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the almost empty threshold for Rx FIFO. + * @param None. + * @retval uint8_t Almost empty threshold for Rx FIFO. + */ +uint8_t SpiritLinearFifoGetAlmostEmptyThresholdRx(void) +{ + uint8_t tempRegValue; + + /* Reads the almost empty threshold for RX FIFO and returns the value */ + g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG2_RXAETHR_BASE, 1, &tempRegValue); + + /* Build and return value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Sets the almost full threshold for the Tx FIFO. When the number of elements in TX FIFO reaches this value an interrupt can be generated to the MCU. + * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is set to 7 the almost + * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. + * @param cThrTxFifo almost full threshold. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritLinearFifoSetAlmostFullThresholdTx(uint8_t cThrTxFifo) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_FIFO_THR(cThrTxFifo)); + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG1_TXAFTHR_BASE, 1, &tempRegValue); + + /* Build the register value */ + tempRegValue &= 0x80; + tempRegValue |= cThrTxFifo; + + /* Writes the Almost Full threshold for Tx in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG1_TXAFTHR_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the almost full threshold for Tx FIFO. + * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is set to 7 the almost + * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. + * @param None. + * @retval uint8_t Almost full threshold for Tx FIFO. + */ +uint8_t SpiritLinearFifoGetAlmostFullThresholdTx(void) +{ + uint8_t tempRegValue; + + /* Reads the almost full threshold for Tx FIFO and returns the value */ + g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG1_TXAFTHR_BASE, 1, &tempRegValue); + + /* Build and returns value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Sets the almost empty threshold for the Tx FIFO. When the number of elements in Tx FIFO reaches this value an interrupt can can be generated to the MCU. + * @param cThrTxFifo: almost empty threshold. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritLinearFifoSetAlmostEmptyThresholdTx(uint8_t cThrTxFifo) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_FIFO_THR(cThrTxFifo)); + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG0_TXAETHR_BASE, 1, &tempRegValue); + + /* Build the register value */ + tempRegValue &= 0x80; + tempRegValue |= cThrTxFifo; + + /* Writes the Almost Empty threshold for Tx in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG0_TXAETHR_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the almost empty threshold for Tx FIFO. + * @param None. + * @retval uint8_t Almost empty threshold for Tx FIFO. + */ +uint8_t SpiritLinearFifoGetAlmostEmptyThresholdTx(void) +{ + uint8_t tempRegValue; + + /* Reads the almost empty threshold for TX FIFO and returns the value */ + g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG0_TXAETHR_BASE, 1, &tempRegValue); + + /* Build and return value */ + return (tempRegValue & 0x7F); + +} + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Management.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Management.c new file mode 100644 index 000000000..f851c1944 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Management.c @@ -0,0 +1,364 @@ +/** + ****************************************************************************** + * @file SPIRIT_Management.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief The management layer for SPIRIT1 library. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Management.h" + +/** +* @addtogroup SPIRIT_Libraries +* @{ +*/ + + +/** +* @defgroup SPIRIT_MANAGEMENT SPIRIT Management +* @{ +*/ + +/** +* @brief BS value to write in the SYNT0 register according to the selected band +*/ +static const uint8_t s_vectcBandRegValue[4]={SYNT0_BS_6, SYNT0_BS_12, SYNT0_BS_16, SYNT0_BS_32}; + +#define COMMUNICATION_STATE_TX 0 +#define COMMUNICATION_STATE_RX 1 +#define COMMUNICATION_STATE_NONE 2 + +static uint32_t s_nDesiredFrequency; + +volatile static uint8_t s_cCommunicationState = COMMUNICATION_STATE_NONE; + + +/** +* @brief Factor is: B/2 used in the formula for SYNTH word calculation +*/ +static const uint8_t s_vectcBHalfFactor[4]={(HIGH_BAND_FACTOR/2), (MIDDLE_BAND_FACTOR/2), (LOW_BAND_FACTOR/2), (VERY_LOW_BAND_FACTOR/2)}; + + +/** +* @defgroup SPIRIT_MANAGEMENT_FUNCTIONS SPIRIT Management Functions +* @{ +*/ + + +/** +* @defgroup WORKAROUND_FUNCTIONS SPIRIT Management Workaround Functions +* @{ +*/ + +/** +* @brief Private SpiritRadioSetFrequencyBase function only used in SpiritManagementWaVcoCalibration. +* @param lFBase the base carrier frequency expressed in Hz as unsigned word. +* @retval None. +*/ +void SpiritManagementSetFrequencyBase(uint32_t lFBase) +{ + uint32_t synthWord, Fc; + uint8_t band, anaRadioRegArray[4], wcp; + + /* Check the parameter */ + s_assert_param(IS_FREQUENCY_BAND(lFBase)); + + /* Search the operating band */ + if(IS_FREQUENCY_BAND_HIGH(lFBase)) + { + band = HIGH_BAND; + } + else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) + { + band = MIDDLE_BAND; + } + else if(IS_FREQUENCY_BAND_LOW(lFBase)) + { + band = LOW_BAND; + } + else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) + { + band = VERY_LOW_BAND; + } + + int32_t FOffset = SpiritRadioGetFrequencyOffset(); + uint32_t lChannelSpace = SpiritRadioGetChannelSpace(); + uint8_t cChannelNum = SpiritRadioGetChannel(); + + /* Calculates the channel center frequency */ + Fc = lFBase + FOffset + lChannelSpace*cChannelNum; + + /* Reads the reference divider */ + uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; + + switch(band) + { + case VERY_LOW_BAND: + if(Fc<161281250) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + break; + + case LOW_BAND: + if(Fc<322562500) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + break; + + case MIDDLE_BAND: + if(Fc<430083334) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + break; + + case HIGH_BAND: + if(Fc<860166667) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + } + + /* Search the VCO charge pump word and set the corresponding register */ + wcp = SpiritRadioSearchWCP(Fc); + + synthWord = (uint32_t)(lFBase*(((double)(FBASE_DIVIDER*cRefDiv*s_vectcBHalfFactor[band]))/SpiritRadioGetXtalFrequency())); + + /* Build the array of registers values for the analog part */ + anaRadioRegArray[0] = (uint8_t)(((synthWord>>21)&(0x0000001F))|(wcp<<5)); + anaRadioRegArray[1] = (uint8_t)((synthWord>>13)&(0x000000FF)); + anaRadioRegArray[2] = (uint8_t)((synthWord>>5)&(0x000000FF)); + anaRadioRegArray[3] = (uint8_t)(((synthWord&0x0000001F)<<3)| s_vectcBandRegValue[band]); + + /* Configures the needed Analog Radio registers */ + g_xStatus = SpiritSpiWriteRegisters(SYNT3_BASE, 4, anaRadioRegArray); +} + +uint8_t SpiritManagementWaVcoCalibration(void) +{ + uint8_t s_cVcoWordRx; + uint8_t s_cVcoWordTx; + uint32_t nFreq; + uint8_t cRestore = 0; + uint8_t cStandby = 0; + uint32_t xtal_frequency = SpiritRadioGetXtalFrequency(); + + /* Enable the reference divider if the XTAL is between 48 and 52 MHz */ + if(xtal_frequency>DOUBLE_XTAL_THR) + { + if(!SpiritRadioGetRefDiv()) + { + cRestore = 1; + nFreq = SpiritRadioGetFrequencyBase(); + SpiritRadioSetRefDiv(S_ENABLE); + SpiritManagementSetFrequencyBase(nFreq); + } + } + nFreq = SpiritRadioGetFrequencyBase(); + + /* Increase the VCO current */ + uint8_t tmp = 0x19; SpiritSpiWriteRegisters(0xA1,1,&tmp); + + SpiritCalibrationVco(S_ENABLE); + + SpiritRefreshStatus(); + if(g_xStatus.MC_STATE == MC_STATE_STANDBY) + { + cStandby = 1; + SpiritCmdStrobeReady(); + do{ + SpiritRefreshStatus(); + if(g_xStatus.MC_STATE == 0x13) + { + return 1; + } + }while(g_xStatus.MC_STATE != MC_STATE_READY); + } + + SpiritCmdStrobeLockTx(); + + do{ + SpiritRefreshStatus(); + if(g_xStatus.MC_STATE == 0x13) + { + return 1; + } + }while(g_xStatus.MC_STATE != MC_STATE_LOCK); + + s_cVcoWordTx = SpiritCalibrationGetVcoCalData(); + + SpiritCmdStrobeReady(); + + do{ + SpiritRefreshStatus(); + }while(g_xStatus.MC_STATE != MC_STATE_READY); + + + SpiritCmdStrobeLockRx(); + + do{ + SpiritRefreshStatus(); + if(g_xStatus.MC_STATE == 0x13) + { + return 1; + } + }while(g_xStatus.MC_STATE != MC_STATE_LOCK); + + s_cVcoWordRx = SpiritCalibrationGetVcoCalData(); + + SpiritCmdStrobeReady(); + + do{ + SpiritRefreshStatus(); + if(g_xStatus.MC_STATE == 0x13) + { + return 1; + } + }while(g_xStatus.MC_STATE != MC_STATE_READY); + + if(cStandby == 1) + { + SpiritCmdStrobeStandby(); + } + SpiritCalibrationVco(S_DISABLE); + + /* Disable the reference divider if the XTAL is between 48 and 52 MHz */ + if(cRestore) + { + SpiritRadioSetRefDiv(S_DISABLE); + SpiritManagementSetFrequencyBase(nFreq); + } + + /* Restore the VCO current */ + tmp = 0x11; SpiritSpiWriteRegisters(0xA1,1,&tmp); + + SpiritCalibrationSetVcoCalDataTx(s_cVcoWordTx); + SpiritCalibrationSetVcoCalDataRx(s_cVcoWordRx); + + return 0; +} + + +void SpiritManagementWaCmdStrobeTx(void) +{ + if(s_cCommunicationState != COMMUNICATION_STATE_TX) + { + uint32_t xtal_frequency = SpiritRadioGetXtalFrequency(); + + /* To achive the max output power */ + if(s_nDesiredFrequency>=150000000 && s_nDesiredFrequency<=470000000) + { + /* Optimal setting for Tx mode only */ + SpiritRadioSetPACwc(LOAD_3_6_PF); + } + else + { + /* Optimal setting for Tx mode only */ + SpiritRadioSetPACwc(LOAD_0_PF); + } + + uint8_t tmp = 0x11; SpiritSpiWriteRegisters(0xa9, 1, &tmp); /* Enable VCO_L buffer */ + tmp = 0x20; SpiritSpiWriteRegisters(PM_CONFIG1_BASE, 1, &tmp); /* Set SMPS switching frequency */ + + s_cCommunicationState = COMMUNICATION_STATE_TX; + } +} + + +void SpiritManagementWaCmdStrobeRx(void) +{ + if(s_cCommunicationState != COMMUNICATION_STATE_RX) + { + uint8_t tmp = 0x98; SpiritSpiWriteRegisters(PM_CONFIG1_BASE, 1, &tmp); /* Set SMPS switching frequency */ + SpiritRadioSetPACwc(LOAD_0_PF); /* Set the correct CWC parameter */ + + s_cCommunicationState = COMMUNICATION_STATE_RX; + } +} + +void SpiritManagementWaTRxFcMem(uint32_t nDesiredFreq) +{ + s_cCommunicationState = COMMUNICATION_STATE_NONE; + s_nDesiredFrequency = nDesiredFreq; +} + + +void SpiritManagementWaExtraCurrent(void) +{ + uint8_t tmp= 0xCA;SpiritSpiWriteRegisters(0xB2, 1, &tmp); + tmp= 0x04;SpiritSpiWriteRegisters(0xA8, 1, &tmp); + /* just a read to loose some microsecs more */ + SpiritSpiReadRegisters(0xA8, 1, &tmp); + tmp= 0x00;SpiritSpiWriteRegisters(0xA8, 1, &tmp); +} + +/** +* @} +*/ + + + +/** +* @} +*/ + + +/** +* @} +*/ + +/** +* @} +*/ + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktBasic.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktBasic.c new file mode 100644 index 000000000..d113f87f3 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktBasic.c @@ -0,0 +1,617 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktBasic.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT Basic packets. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_PktBasic.h" +#include "MCU_Interface.h" + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_PktBasic + * @{ + */ + + +/** + * @defgroup PktBasic_Private_TypesDefinitions Pkt Basic Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktBasic_Private_Defines Pkt Basic Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktBasic_Private_Macros Pkt Basic Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktBasic_Private_Variables Pkt Basic Private Variables + * @{ + */ + +/** + *@} + */ + + + +/** + * @defgroup PktBasic_Private_FunctionPrototypes Pkt Basic Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktBasic_Private_Functions Pkt Basic Private Functions + * @{ + */ + +/** + * @brief Initializes the SPIRIT Basic packet according to the specified parameters in the PktBasicInit struct. + * Notice that this function sets the autofiltering option on CRC if it is set to any value different from BASIC_NO_CRC. + * @param pxPktBasicInit Basic packet init structure. + * This parameter is a pointer to @ref PktBasicInit. + * @retval None. + */ +void SpiritPktBasicInit(PktBasicInit* pxPktBasicInit) +{ + uint8_t tempRegValue[4], i; + + /* Check the parameters */ + s_assert_param(IS_BASIC_PREAMBLE_LENGTH(pxPktBasicInit->xPreambleLength)); + s_assert_param(IS_BASIC_SYNC_LENGTH(pxPktBasicInit->xSyncLength)); + s_assert_param(IS_BASIC_CRC_MODE(pxPktBasicInit->xCrcMode)); + s_assert_param(IS_BASIC_LENGTH_WIDTH_BITS(pxPktBasicInit->cPktLengthWidth)); + s_assert_param(IS_BASIC_FIX_VAR_LENGTH(pxPktBasicInit->xFixVarLength)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicInit->xAddressField)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicInit->xFec)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicInit->xDataWhitening)); + s_assert_param(IS_BASIC_CONTROL_LENGTH(pxPktBasicInit->xControlLength)); + + /* Reads the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); + + /* Mask a reserved bit */ + tempRegValue[0] &= ~0x20; + + /* Always set the automatic packet filtering */ + tempRegValue[0] |= PROTOCOL1_AUTO_PCKT_FLT_MASK; + + /* Writes the value on register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); + + /* Reads the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Always reset the control and source filtering (also if it is not present in basic) */ + tempRegValue[0] &= ~(PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK | PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK); + + /* Writes the value on register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + if(pxPktBasicInit->xAddressField == S_ENABLE) + { + tempRegValue[0]=0x08; + } + else + { + tempRegValue[0]=0x00; + } + /* Address and control length setting */ + tempRegValue[0] |= ((uint8_t) pxPktBasicInit->xControlLength); + + /* Packet format and width length setting */ + pxPktBasicInit->cPktLengthWidth == 0 ? pxPktBasicInit->cPktLengthWidth=1 : pxPktBasicInit->cPktLengthWidth; + tempRegValue[1] = ((uint8_t) PCKTCTRL3_PCKT_FRMT_BASIC) | ((uint8_t)(pxPktBasicInit->cPktLengthWidth-1)); + + /* Preamble, sync and fixed or variable length setting */ + tempRegValue[2] = ((uint8_t) pxPktBasicInit->xPreambleLength) | ((uint8_t) pxPktBasicInit->xSyncLength) | + ((uint8_t) pxPktBasicInit->xFixVarLength); + + /* CRC length, whitening and FEC setting */ + tempRegValue[3] = (uint8_t) pxPktBasicInit->xCrcMode; + + if(pxPktBasicInit->xDataWhitening == S_ENABLE) + { + tempRegValue[3] |= PCKTCTRL1_WHIT_MASK; + } + + if(pxPktBasicInit->xFec == S_ENABLE) + { + tempRegValue[3] |= PCKTCTRL1_FEC_MASK; + } + + /* Writes registers */ + SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 4, tempRegValue); + + /* Sync words setting */ + for(i=0;i<4;i++) + { + if(i<3-(pxPktBasicInit->xSyncLength >>1)) + { + tempRegValue[i]=0; + } + else + { + tempRegValue[i] = (uint8_t)(pxPktBasicInit->lSyncWords>>(8*i)); + } + } + + /* Sets CRC check bit */ + if(pxPktBasicInit->xCrcMode == PKT_NO_CRC) + { + SpiritPktBasicFilterOnCrc(S_DISABLE); + } + else + { + SpiritPktBasicFilterOnCrc(S_ENABLE); + } + + + g_xStatus = SpiritSpiWriteRegisters(SYNC4_BASE, 4, tempRegValue); + +} + + +/** + * @brief Returns the SPIRIT Basic packet structure according to the specified parameters in the registers. + * @param pxPktBasicInit Basic packet init structure. + * This parameter is a pointer to @ref PktBasicInit. + * @retval None. + */ +void SpiritPktBasicGetInfo(PktBasicInit* pxPktBasicInit) +{ + uint8_t tempRegValue[10]; + + /* Reads registers */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 10, tempRegValue); + + /* Length width */ + pxPktBasicInit->cPktLengthWidth=(tempRegValue[1] & 0x0F)+1; + + /* Address field */ + pxPktBasicInit->xAddressField=(SpiritFunctionalState)((tempRegValue[0]>>3) & 0x01); + + /* Control length */ + pxPktBasicInit->xControlLength=(BasicControlLength)(tempRegValue[0] & 0x07); + + /* CRC mode */ + pxPktBasicInit->xCrcMode=(BasicCrcMode)(tempRegValue[3] & 0xE0); + + /* Whitening */ + pxPktBasicInit->xDataWhitening=(SpiritFunctionalState)((tempRegValue[3] >> 4) & 0x01); + + /* FEC */ + pxPktBasicInit->xFec=(SpiritFunctionalState)(tempRegValue[3] & 0x01); + + /* FIX or VAR bit */ + pxPktBasicInit->xFixVarLength=(BasicFixVarLength)(tempRegValue[2] & 0x01); + + /* Preamble length */ + pxPktBasicInit->xPreambleLength=(BasicPreambleLength)(tempRegValue[2] & 0xF8); + + /* Sync length */ + pxPktBasicInit->xSyncLength=(BasicSyncLength)(tempRegValue[2] & 0x06); + + /* sync Words */ + pxPktBasicInit->lSyncWords=0; + for(uint8_t i=0 ; i<4 ; i++) + { + if(i>2-(((uint8_t)pxPktBasicInit->xSyncLength) >>1)) + { + pxPktBasicInit->lSyncWords |= (uint32_t)(tempRegValue[i+6])<<(8*i); + } + } + +} + + +/** + * @brief Initializes the SPIRIT Basic packet addresses according to the specified + * parameters in the PktBasicAddressesInit struct. + * @param pxPktBasicAddresses Basic packet addresses init structure. + * This parameter is a pointer to @ref PktBasicAddresses. + * @retval None. + */ +void SpiritPktBasicAddressesInit(PktBasicAddressesInit* pxPktBasicAddresses) +{ + uint8_t tempRegValue[3]; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicAddresses->xFilterOnMyAddress)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicAddresses->xFilterOnMulticastAddress)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicAddresses->xFilterOnBroadcastAddress)); + + + /* Reads the PCKT_FLT_OPTIONS ragister */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Enables or disables filtering on my address */ + if(pxPktBasicAddresses->xFilterOnMyAddress == S_ENABLE) + { + tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; + } + else + { + tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; + } + + /* Enables or disables filtering on multicast address */ + if(pxPktBasicAddresses->xFilterOnMulticastAddress == S_ENABLE) + { + tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; + } + else + { + tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; + } + + /* Enables or disables filtering on broadcast address */ + if(pxPktBasicAddresses->xFilterOnBroadcastAddress == S_ENABLE) + { + tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; + } + else + { + tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; + } + + /* Writes the new value on the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Fills the array with the addresses passed in the structure */ + tempRegValue[0] = pxPktBasicAddresses->cBroadcastAddress; + tempRegValue[1] = pxPktBasicAddresses->cMulticastAddress; + tempRegValue[2] = pxPktBasicAddresses->cMyAddress; + + /* Writes values on the PCKT_FLT_GOALS registers */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); + + +} + + +/** + * @brief Returns the SPIRIT Basic packet addresses structure according to the specified + * parameters in the registers. + * @param pxPktBasicAddresses Basic packet addresses init structure. + * This parameter is a pointer to @ref PktBasicAddresses. + * @retval None. + */ +void SpiritPktBasicGetAddressesInfo(PktBasicAddressesInit* pxPktBasicAddresses) +{ + uint8_t tempRegValue[3]; + + /* Reads values on the PCKT_FLT_GOALS registers */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); + + /* Fit the structure with the read addresses */ + pxPktBasicAddresses->cBroadcastAddress = tempRegValue[0]; + pxPktBasicAddresses->cMulticastAddress = tempRegValue[1]; + pxPktBasicAddresses->cMyAddress = tempRegValue[2]; + + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Fit the structure with the read filtering bits */ + pxPktBasicAddresses->xFilterOnBroadcastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 1) & 0x01); + pxPktBasicAddresses->xFilterOnMulticastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 2) & 0x01); + pxPktBasicAddresses->xFilterOnMyAddress = (SpiritFunctionalState)((tempRegValue[0] >> 3) & 0x01); + +} + + +/** + * @brief Configures the Basic packet format as packet used by SPIRIT. + * @param None. + * @retval None. + */ +void SpiritPktBasicSetFormat(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Build the new value. Also set to 0 the direct RX mode bits */ + tempRegValue &= 0x0F; + tempRegValue |= (uint8_t)PCKTCTRL3_PCKT_FRMT_BASIC; + + /* Writes the value on the PCKTCTRL3 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Reads the PCKTCTRL1_BASE register */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Build the new value. Set to 0 the direct TX mode bits */ + tempRegValue &= 0xF3; + + /* Writes the value on the PCKTCTRL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Reads the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Mask a reserved bit */ + tempRegValue &= ~0x20; + + /* Writes the value on register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); +} + + +/** + * @brief Sets the address length for SPIRIT Basic packets. + * @param xAddressField length of ADDRESS in bytes. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritPktBasicAddressField(SpiritFunctionalState xAddressField) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xAddressField)); + + /* Reads the PCKTCTRL4 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + + /* Build the address length for the register */ + if(xAddressField==S_ENABLE) + { + tempRegValue |= 0x08; + } + else + { + tempRegValue &= 0x07; + } + + /* Writes the new value on the PCKTCTRL4 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Specifies if the Address field for SPIRIT Basic packets is enabled or disabled. + * @param None. + * @retval SpiritFunctionalState Notifies if the address field is enabled or disabled. + */ +SpiritFunctionalState SpiritPktBasicGetAddressField(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL4 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + + /* Returns the address field value */ + if(tempRegValue & PCKTCTRL4_ADDRESS_LEN_MASK) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + + +/** + * @brief Sets the payload length for SPIRIT Basic packets. Since the packet length + * depends from the address and the control field size, this + * function reads the correspondent registers in order to determine + * the correct packet length to be written. + * @param nPayloadLength payload length in bytes. + * This parameter is an uint16_t. + * @retval None. + */ +void SpiritPktBasicSetPayloadLength(uint16_t nPayloadLength) +{ + uint8_t tempRegValue[2]; + uint16_t overSize=0; + + /* Computes the oversize (address + control) size */ + if(SpiritPktBasicGetAddressField()) + { + overSize=1; + } + overSize += (uint16_t) SpiritPktBasicGetControlLength(); + + /* Computes PCKTLEN0 value from nPayloadLength */ + tempRegValue[1]=BASIC_BUILD_PCKTLEN0(nPayloadLength+overSize); + /* Computes PCKTLEN1 value from nPayloadLength */ + tempRegValue[0]=BASIC_BUILD_PCKTLEN1(nPayloadLength+overSize); + + /* Writes data on the PCKTLEN1/0 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTLEN1_BASE, 2, tempRegValue); + +} + + +/** + * @brief Returns the payload length for SPIRIT Basic packets. Since the + * packet length depends from the address and the control + * field size, this function reads the correspondent + * registers in order to determine the correct payload length + * to be returned. + * @param None. + * @retval uint16_t Payload length in bytes. + */ +uint16_t SpiritPktBasicGetPayloadLength(void) +{ + uint8_t tempRegValue[2]; + uint16_t overSize=0; + + /* Computes the oversize (address + control) size */ + if(SpiritPktBasicGetAddressField()) + { + overSize=1; + } + overSize += (uint16_t) SpiritPktBasicGetControlLength(); + + /* Reads the packet length registers */ + g_xStatus = SpiritSpiReadRegisters(PCKTLEN1_BASE, 2, tempRegValue); + + /* Returns the packet length */ + return ((((uint16_t)tempRegValue[0])<<8) + (uint16_t) tempRegValue[1]) - overSize; + +} + +/** + * @brief Returns the packet length field of the received packet. + * @param None. + * @retval uint16_t Packet length. + */ +uint16_t SpiritPktBasicGetReceivedPktLength(void) +{ + uint8_t tempRegValue[2]; + uint16_t overSize=0; + + /* Computes the oversize (address + control) size */ + if(SpiritPktBasicGetAddressField()) + { + overSize=1; + } + overSize += (uint16_t) SpiritPktBasicGetControlLength(); + + /* Reads the RX_PCKT_LENx registers value */ + g_xStatus = SpiritSpiReadRegisters(RX_PCKT_LEN1_BASE, 2, tempRegValue); + + /* Rebuild and return the the length field */ + return ((((uint16_t) tempRegValue[0]) << 8) + (uint16_t) tempRegValue[1] - overSize); + +} + +/** + * @brief Computes and sets the variable payload length for SPIRIT Basic packets. + * @param nMaxPayloadLength payload length in bytes. + * This parameter is an uint16_t. + * @param xAddressField Enable or Disable Address Field. + * This parameter can be S_ENABLE or S_DISABLE. + * @param xControlLength Control length in bytes. + * This parameter can be any value of @ref BasicControlLength. + * @retval None. + */ +void SpiritPktBasicSetVarLengthWidth(uint16_t nMaxPayloadLength, SpiritFunctionalState xAddressField, BasicControlLength xControlLength) +{ + uint8_t tempRegValue, + addressLength, + i; + uint32_t packetLength; + + /* Sets the address length according to xAddressField */ + if(xAddressField == S_ENABLE) + { + addressLength=1; + } + else + { + addressLength=0; + } + + /* packet length = payload length + address length + control length */ + packetLength=nMaxPayloadLength+addressLength+xControlLength; + + /* Computes the number of bits */ + for(i=0;i<16;i++) + { + if(packetLength == 0) break; + { + packetLength >>= 1; + } + } + i==0 ? i=1 : i; + + /* Reads the PCKTCTRL3 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Build value for the length width */ + tempRegValue &= ~PCKTCTRL3_LEN_WID_MASK; + tempRegValue |= (uint8_t)(i-1); + + /* Writes the PCKTCTRL3 register value */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + +} + + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktCommon.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktCommon.c new file mode 100644 index 000000000..b29084b78 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktCommon.c @@ -0,0 +1,1453 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktCommon.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of the common features of SPIRIT packets. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_PktCommon.h" +#include "MCU_Interface.h" + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_PktCommon + * @{ + */ + + +/** + * @defgroup PktCommon_Private_TypesDefinitions Pkt Common Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktCommon_Private_Defines Pkt Common Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktCommon_Private_Macros Pkt Common Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktCommon_Private_Variables Pkt Common Private Variables + * @{ + */ + +/** + *@} + */ + + + +/** + * @defgroup PktCommon_Private_FunctionPrototypes Pkt Common Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktCommon_Private_Functions Pkt Common Private Functions + * @{ + */ + +/** + * @brief Sets the CONTROL field length for SPIRIT packets. + * @param xControlLength length of CONTROL field in bytes. + * This parameter can be any value of @ref PktControlLength. + * @retval None. + */ +void SpiritPktCommonSetControlLength(PktControlLength xControlLength) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PKT_CONTROL_LENGTH(xControlLength)); + + /* Reads the PCKTCTRL4 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + + /* Set the control length */ + tempRegValue &= ~PCKTCTRL4_CONTROL_LEN_MASK; + tempRegValue |= (uint8_t)xControlLength; + + /* Writes the new value on the PCKTCTRL4 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the CONTROL field length for SPIRIT packets. + * @param None. + * @retval uint8_t Control field length. + */ +uint8_t SpiritPktCommonGetControlLength(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL4 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + + /* Rebuild and return value */ + return (tempRegValue & PCKTCTRL4_CONTROL_LEN_MASK); + +} + + +/** + * @brief Sets the PREAMBLE field Length mode for SPIRIT packets. + * @param xPreambleLength length of PREAMBLE field in bytes. + * This parameter can be any value of @ref PktPreambleLength. + * @retval None. + */ +void SpiritPktCommonSetPreambleLength(PktPreambleLength xPreambleLength) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PKT_PREAMBLE_LENGTH(xPreambleLength)); + + /* Reads the PCKTCTRL2 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); + + /* Set the preamble length */ + tempRegValue &= ~PCKTCTRL2_PREAMBLE_LENGTH_MASK; + tempRegValue |= (uint8_t)xPreambleLength; + + /* Writes the new value on the PCKTCTRL2 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the PREAMBLE field Length mode for SPIRIT packets. + * @param None. + * @retval uint8_t Preamble field length in bytes. + */ +uint8_t SpiritPktCommonGetPreambleLength(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL2 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); + + /* Rebuild and return value */ + return ((tempRegValue & PCKTCTRL2_PREAMBLE_LENGTH_MASK)>>3) + 1; + +} + + +/** + * @brief Sets the SYNC field Length for SPIRIT packets. + * @param xSyncLength length of SYNC field in bytes. + * This parameter can be any value of @ref PktSyncLength. + * @retval None. + */ +void SpiritPktCommonSetSyncLength(PktSyncLength xSyncLength) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PKT_SYNC_LENGTH(xSyncLength)); + + /* Reads the PCKTCTRL2 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); + + /* Set the sync length */ + tempRegValue &= ~PCKTCTRL2_SYNC_LENGTH_MASK; + tempRegValue |= (uint8_t)xSyncLength; + + /* Writes the new value on the PCKTCTRL2 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the SYNC field Length for SPIRIT packets. + * @param None. + * @retval uint8_t Sync field length in bytes. + */ +uint8_t SpiritPktCommonGetSyncLength(void) +{ + uint8_t tempRetValue; + + /* Reads the PCKTCTRL2 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRetValue); + + /* Rebuild and return value */ + return ((tempRetValue & PCKTCTRL2_SYNC_LENGTH_MASK)>>1) + 1; + +} + + +/** + * @brief Sets fixed or variable payload length mode for SPIRIT packets. + * @param xFixVarLength variable or fixed length. + * PKT_FIXED_LENGTH_VAR -> variable (the length is extracted from the received packet). + * PKT_FIXED_LENGTH_FIX -> fix (the length is set by PCKTLEN0 and PCKTLEN1). + * @retval None. + */ +void SpiritPktCommonSetFixVarLength(PktFixVarLength xFixVarLength) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PKT_FIX_VAR_LENGTH(xFixVarLength)); + + /* Reads the PCKTCTRL2 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); + + /* Set fixed or variable address mode */ + tempRegValue &= ~PCKTCTRL2_FIX_VAR_LEN_MASK; + tempRegValue |= (uint8_t)xFixVarLength; + + /* Writes the new value on the PCKTCTRL2 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Enables or Disables the filtering on CRC. + * @param xNewState new state for CRC_CHECK. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritPktCommonFilterOnCrc(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PCKT_FLT_OPTIONS register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Modify the register value: enable or disable the CRC filtering */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKT_FLT_OPTIONS_CRC_CHECK_MASK; + } + else + { + tempRegValue &= ~PCKT_FLT_OPTIONS_CRC_CHECK_MASK; + } + + /* Writes the PCKT_FLT_OPTIONS register value */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the CRC filtering enable bit. + * @param None. + * @retval SpiritFunctionalState CRC filtering. + */ +SpiritFunctionalState SpiritPktCommonGetFilterOnCrc(void) +{ + uint8_t tempRegValue; + + + /* Reads the PCKT_FLT_OPTIONS register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Check the CRC filtering bit */ + if(tempRegValue & PCKT_FLT_OPTIONS_CRC_CHECK_MASK) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + + +/** + * @brief Sets the CRC mode for SPIRIT packets. + * @param xCrcMode length of CRC field in bytes. + * This parameter can be any value of @ref PktCrcMode. + * @retval None. + */ +void SpiritPktCommonSetCrcMode(PktCrcMode xCrcMode) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PKT_CRC_MODE(xCrcMode)); + + /* Reads the PCKTCTRL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Build data to write setting the CRC mode */ + tempRegValue &= ~PCKTCTRL1_CRC_MODE_MASK; + tempRegValue |= (uint8_t)xCrcMode; + + /* Writes the new value on the PCKTCTRL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the CRC mode for SPIRIT packets. + * @param None. + * @retval PktCrcMode Crc mode. + */ +PktCrcMode SpiritPktCommonGetCrcMode(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL1 register */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Rebuild and return value */ + return (PktCrcMode)(tempRegValue & 0xE0); + +} + + +/** + * @brief Enables or Disables WHITENING for SPIRIT packets. + * @param xNewState new state for WHITENING mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritPktCommonWhitening(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PCKTCTRL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Build data to write: set or reset the whitening enable bit */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKTCTRL1_WHIT_MASK; + } + else + { + tempRegValue &= ~PCKTCTRL1_WHIT_MASK; + } + + /* Writes the new value on the PCKTCTRL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Enables or Disables FEC for SPIRIT packets. + * @param xNewState new state for FEC mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritPktCommonFec(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PCKTCTRL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Build data to write: set or reset the FEC enable bit */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKTCTRL1_FEC_MASK; + } + else + { + tempRegValue &= ~PCKTCTRL1_FEC_MASK; + } + + /* Writes data on the PCKTCTRL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets a specific SYNC word for SPIRIT packets. + * @param xSyncX SYNC word number to be set. + * This parameter can be any value of @ref PktSyncX. + * @param cSyncWord SYNC word. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktCommonSetSyncxWord(PktSyncX xSyncX , uint8_t cSyncWord) +{ + uint8_t tempRegAddress; + + /* Check the parameters */ + s_assert_param(IS_PKT_SYNCx(xSyncX)); + + /* Set the specified address */ + switch(xSyncX) + { + case PKT_SYNC_WORD_1: + tempRegAddress=SYNC1_BASE; + break; + case PKT_SYNC_WORD_2: + tempRegAddress=SYNC2_BASE; + break; + case PKT_SYNC_WORD_3: + tempRegAddress=SYNC3_BASE; + break; + case PKT_SYNC_WORD_4: + tempRegAddress=SYNC4_BASE; + break; + } + + /* Writes value on the selected register */ + g_xStatus = SpiritSpiWriteRegisters(tempRegAddress, 1, &cSyncWord); + +} + + +/** + * @brief Returns a specific SYNC word for SPIRIT packets. + * @param xSyncX SYNC word number to be get. + * This parameter can be any value of @ref PktSyncX. + * @retval uint8_t Sync word x. + */ +uint8_t SpiritPktCommonGetSyncxWord(PktSyncX xSyncX) +{ + uint8_t tempRegAddress, tempRegValue; + + /* Set the specified address */ + switch(xSyncX) + { + case PKT_SYNC_WORD_1: + tempRegAddress=SYNC1_BASE; + break; + case PKT_SYNC_WORD_2: + tempRegAddress=SYNC2_BASE; + break; + case PKT_SYNC_WORD_3: + tempRegAddress=SYNC3_BASE; + break; + case PKT_SYNC_WORD_4: + tempRegAddress=SYNC4_BASE; + break; + } + + /* Reads the selected register value */ + g_xStatus = SpiritSpiReadRegisters(tempRegAddress, 1, &tempRegValue); + + /* Returns the read value */ + return tempRegValue; + +} + + +/** + * @brief Sets multiple SYNC words for SPIRIT packets. + * @param lSyncWords SYNC words to be set with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4|. + * This parameter is a uint32_t. + * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb + * until the number of bytes in xSyncLength has been stored. + * This parameter is a @ref PktSyncLength. + * @retval None. + */ +void SpiritPktCommonSetSyncWords(uint32_t lSyncWords, PktSyncLength xSyncLength) +{ + uint8_t tempRegValue[4]; + + /* Split the 32-bit value in 4 8-bit values */ + for(uint8_t i=0 ; i<4 ; i++) + { + if(i<3-xSyncLength>>1) + { + tempRegValue[i]=0; + } + else + { + tempRegValue[i]=(uint8_t)(lSyncWords>>(8*i)); + } + } + + /* Writes SYNC value on the SYNCx registers */ + g_xStatus = SpiritSpiWriteRegisters(SYNC4_BASE, 4, tempRegValue); + +} + + +/** + * @brief Returns multiple SYNC words for SPIRIT packets. + * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb + * until the number of bytes in xSyncLength has been stored. + * This parameter is a pointer to @ref PktSyncLength. + * @retval uint32_t Sync words. The format of the read 32 bit word is 0x|SYNC1|SYNC2|SYNC3|SYNC4|. + */ +uint32_t SpiritPktCommonGetSyncWords(PktSyncLength xSyncLength) +{ + uint8_t tempRegValue[4]; + uint32_t tempRetValue=0; + + /* Reads the SYNCx registers value */ + g_xStatus = SpiritSpiReadRegisters(SYNC4_BASE, 4, tempRegValue); + + /* Rebuild the SYNC words */ + for(uint8_t i=0 ; i<4 ; i++) + { + if(i>2-(xSyncLength >>1)) + { + tempRetValue |= tempRegValue[i]<<(8*i); + } + } + + /* Return SYNC words */ + return tempRetValue; + +} + + +/** + * @brief Returns the variable length width (in number of bits). + * @param None. + * @retval uint8_t Variable length width in bits. + */ +uint8_t SpiritPktCommonGetVarLengthWidth(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL3 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Rebuild and return value */ + return (tempRegValue & PCKTCTRL3_LEN_WID_MASK)+1; + +} + + +/** + * @brief Sets the destination address for the Tx packet. + * @param cAddress Destination address. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktCommonSetDestinationAddress(uint8_t cAddress) +{ + /* Writes value on PCKT_FLT_GOALS_SOURCE_ADDR register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_SOURCE_ADDR_BASE, 1, &cAddress); + +} + + +/** + * @brief Returns the settled destination address. + * @param None. + * @retval uint8_t Transmitted destination address. + */ +uint8_t SpiritPktCommonGetTransmittedDestAddress(void) +{ + uint8_t tempRegValue; + + /* Reads value on the PCKT_FLT_GOALS_SOURCE_ADDR register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_SOURCE_ADDR_BASE, 1, &tempRegValue); + + /* Return value */ + return tempRegValue; + +} + + +/** + * @brief Sets the node my address. When the filtering on my address is on, if the destination address extracted from the received packet is equal to the content of the + * my address, then the packet is accepted (this is the address of the node). + * @param cAddress Address of the present node. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktCommonSetMyAddress(uint8_t cAddress) +{ + /* Writes value on the PCKT_FLT_GOALS_TX_ADDR register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_TX_ADDR_BASE, 1, &cAddress); + +} + + +/** + * @brief Returns the address of the present node. + * @param None. + * @retval uint8_t My address (address of this node). + */ +uint8_t SpiritPktCommonGetMyAddress(void) +{ + uint8_t tempRegValue; + + /* Reads value on the PCKT_FLT_GOALS_TX_ADDR register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_TX_ADDR_BASE, 1, &tempRegValue); + + /* Return value */ + return tempRegValue; + +} + + +/** + * @brief Sets the broadcast address. If the destination address extracted from the received packet is equal to the content of the + * BROADCAST_ADDR register, then the packet is accepted. + * @param cAddress Broadcast address. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktCommonSetBroadcastAddress(uint8_t cAddress) +{ + /* Writes value on the PCKT_FLT_GOALS_BROADCAST register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 1, &cAddress); + +} + + +/** + * @brief Returns the broadcast address. + * @param None. + * @retval uint8_t Broadcast address. + */ +uint8_t SpiritPktCommonGetBroadcastAddress(void) +{ + uint8_t tempRegValue; + + /* Reads value on the PCKT_FLT_GOALS_BROADCAST register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 1, &tempRegValue); + + /* Return value */ + return tempRegValue; + +} + + +/** + * @brief Sets the multicast address. When the multicast filtering is on, if the destination address extracted from the received packet is equal to the content of the + * MULTICAST_ADDR register, then the packet is accepted. + * @param cAddress Multicast address. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktCommonSetMulticastAddress(uint8_t cAddress) +{ + /* Writes value on the PCKT_FLT_GOALS_MULTICAST register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_MULTICAST_BASE, 1, &cAddress); + +} + + +/** + * @brief Returns the multicast address. + * @param None. + * @retval uint8_t Multicast address. + */ +uint8_t SpiritPktCommonGetMulticastAddress(void) +{ + uint8_t tempRegValue; + + /* Reads value on the PCKT_FLT_GOALS_MULTICAST register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_MULTICAST_BASE, 1, &tempRegValue); + + /* Return value */ + return tempRegValue; + +} + + +/** + * @brief Sets the control mask. The 1 bits of the CONTROL_MASK indicate the + * bits to be used in filtering. (All 0s no filtering) + * @param lMask Control mask. + * This parameter is an uint32_t. + * @retval None. + */ +void SpiritPktCommonSetCtrlMask(uint32_t lMask) +{ + uint8_t tempRegValue[4]; + + /* Split the 32-bit value in 4 8-bit values */ + tempRegValue[0] = (uint8_t) lMask; + tempRegValue[1] = (uint8_t)(lMask >> 8); + tempRegValue[2] = (uint8_t)(lMask >> 16); + tempRegValue[3] = (uint8_t)(lMask >> 24); + + /* Writes values on the CKT_FLT_GOALS_CONTROLx_MASK registers */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_CONTROL0_MASK_BASE, 4, tempRegValue); + +} + + +/** + * @brief Returns the control mask. The 1 bits of the CONTROL_MASK indicate the + * bits to be used in filtering. (All 0s no filtering) + * @param None. + * @retval uint32_t Control mask. + */ +uint32_t SpiritPktCommonGetCtrlMask(void) +{ + uint8_t tempRegValue[4]; + uint32_t tempRetValue=0; + + /* Reads the PCKT_FLT_GOALS_CONTROLx_MASK registers */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_CONTROL0_MASK_BASE, 4, tempRegValue); + + /* Rebuild the control mask value on a 32-bit integer variable */ + for(uint8_t i=0 ; i<4 ; i++) + { + tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*i); + } + + /* Return value */ + return tempRetValue; +} + +/** + * @brief Sets the control field reference. If the bits enabled by the CONTROL_MASK + * match the ones of the control fields extracted from the received packet + * then the packet is accepted. + * @param lReference Control reference. + * This parameter is an uint32_t. + * @retval None. + */ +void SpiritPktCommonSetCtrlReference(uint32_t lReference) +{ + uint8_t tempRegValue[4]; + + /* Split the 32-bit value in 4 8-bit values */ + tempRegValue[0] = (uint8_t) lReference; + tempRegValue[1] = (uint8_t)(lReference >> 8); + tempRegValue[2] = (uint8_t)(lReference >> 16); + tempRegValue[3] = (uint8_t)(lReference >> 24); + + /* Writes values on the CKT_FLT_GOALS_CONTROLx_FIELD registers */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_CONTROL0_FIELD_BASE, 4, tempRegValue); + +} + + +/** + * @brief Returns the control field reference. + * @param None. + * @retval uint32_t Control reference. + */ +uint32_t SpiritPktCommonGetCtrlReference(void) +{ + uint8_t tempRegValue[4]; + uint32_t tempRetValue=0; + + /* Reads the PCKT_FLT_GOALS_CONTROLx_FIELD registers */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_CONTROL0_FIELD_BASE, 4, tempRegValue); + + /* Rebuild the control mask value on a 32-bit integer variable */ + for(uint8_t i=0 ; i<4 ; i++) + { + tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*i); + } + + /* Return value */ + return tempRetValue; +} + + +/** + * @brief Sets the TX control field. + * @param lField Tx contro field. + * This parameter is an uint32_t. + * @retval None. + */ +void SpiritPktCommonSetTransmittedCtrlField(uint32_t lField) +{ + uint8_t tempRegValue[4]; + + /* Split the 32-bit value in 4 8-bit values */ + tempRegValue[3] = (uint8_t) lField; + tempRegValue[2] = (uint8_t)(lField >> 8); + tempRegValue[1] = (uint8_t)(lField >> 16); + tempRegValue[0] = (uint8_t)(lField >> 24); + + /* Writes value on the TX_CTRL_FIELDx register */ + g_xStatus = SpiritSpiWriteRegisters(TX_CTRL_FIELD3_BASE, 4, tempRegValue); + +} + + +/** + * @brief Returns the Tx control field. + * @param None. + * @retval uint32_t Control field of the transmitted packet. + */ +uint32_t SpiritPktCommonGetTransmittedCtrlField(void) +{ + uint8_t tempRegValue[4]; + uint32_t tempRetValue=0; + + /* Reads the TX_CTRL_FIELDx registers */ + g_xStatus = SpiritSpiReadRegisters(TX_CTRL_FIELD3_BASE, 4, tempRegValue); + + /* Rebuild value: build a 32-bit value from the read bytes */ + for(uint8_t i=0 ; i<4 ; i++) + { + tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*(3-i)); + } + + /* Return value */ + return tempRetValue; + +} + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with My address. + * @param xNewState new state for DEST_VS_SOURCE_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritPktCommonFilterOnMyAddress(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + + /* Modify the register value: set or reset the TX source address control */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Set or reset the DESTINATION vs TX enabling bit */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; + } + else + { + tempRegValue &= ~PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; + } + + /* Writes the new value on the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + +} + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with multicast address. + * @param xNewState new state for DEST_VS_MULTICAST_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritPktCommonFilterOnMulticastAddress(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PCKT_FLT_OPTIONS register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Enable or disable the filtering option */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; + } + else + { + tempRegValue &= ~PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; + } + + /* Writes the new value on the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + +} + + +/** + * @brief If enabled RX packet is accepted if its destination address matches with broadcast address. + * @param xNewState new state for DEST_VS_BROADCAST_ADDRESS. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritPktCommonFilterOnBroadcastAddress(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Enable or disable the filtering option */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; + } + else + { + tempRegValue &= ~PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; + } + + /* Writes the new value on the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the enable bit of the my address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +SpiritFunctionalState SpiritPktCommonGetFilterOnMyAddress(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Gets the enable/disable bit in form of SpiritFunctionalState type */ + if(tempRegValue & 0x08) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + +/** + * @brief Returns the enable bit of the multicast address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +SpiritFunctionalState SpiritPktCommonGetFilterOnMulticastAddress(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Get the enable/disable bit in form of SpiritFunctionalState type */ + if(tempRegValue & 0x04) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + +/** + * @brief Returns the enable bit of the broadcast address filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +SpiritFunctionalState SpiritPktCommonGetFilterOnBroadcastAddress(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Get the enable/disable bit in form of SpiritFunctionalState type */ + if(tempRegValue & 0x02) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + + +/** + * @brief Returns the destination address of the received packet. + * @param None. + * @retval uint8_t Destination address of the received address. + */ +uint8_t SpiritPktCommonGetReceivedDestAddress(void) +{ + uint8_t tempRegValue; + + /* Reads the RX_ADDR_FIELD0 register value */ + g_xStatus = SpiritSpiReadRegisters(RX_ADDR_FIELD0_BASE, 1, &tempRegValue); + + /* Return value */ + return tempRegValue; + +} + + +/** + * @brief Returns the control field of the received packet. + * @param None. + * @retval uint32_t Received control field. + */ +uint32_t SpiritPktCommonGetReceivedCtrlField(void) +{ + uint8_t tempRegValue[4]; + uint32_t tempRetValue=0; + + /* Reads the PCKT_FLT_GOALS_CONTROLx_MASK registers */ + g_xStatus = SpiritSpiReadRegisters(RX_CTRL_FIELD0_BASE, 4, tempRegValue); + + /* Rebuild the control mask value on a 32-bit integer variable */ + for(uint8_t i=0 ; i<4 ; i++) + { + tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*i); + } + + /* Returns value */ + return tempRetValue; +} + + +/** + * @brief Returns the CRC field of the received packet. + * @param cCrcFieldVect array in which the CRC field has to be stored. + * This parameter is an uint8_t array of 3 elements. + * @retval None. + */ +void SpiritPktCommonGetReceivedCrcField(uint8_t* cCrcFieldVect) +{ + uint8_t tempRegValue[3],crcLength; + PktCrcMode crcMode; + + /* Gets the CRC mode in PktCrcMode enum */ + crcMode=SpiritPktCommonGetCrcMode(); + + /* Cast to uint8_t */ + crcLength = (uint8_t)crcMode; + + /* Obtains the real length: see the @ref PktCrcMode enumeration */ + crcLength >>= 5; + if(crcLength>=3) crcLength--; + + /* Reads the CRC_FIELDx registers value */ + g_xStatus = SpiritSpiReadRegisters(CRC_FIELD2_BASE, 3,tempRegValue); + + /* Sets the array to be returned */ + for(uint8_t i=0 ; i<3 ; i++) + { + if(i>4); + +} + +/** + * @brief Returns the TX ACK request + * @param None. + * @retval uint8_t Max number of retransmissions. + * This parameter is an uint8_t. + */ +SpiritFunctionalState SpiritPktCommonGetTxAckRequest(void) +{ + uint8_t tempRegValue; + + /* Reads the PROTOCOL0 register value */ + g_xStatus = SpiritSpiReadRegisters(RX_PCKT_INFO_BASE, 1, &tempRegValue); + + /* Build the value to be written */ + return (SpiritFunctionalState)((tempRegValue & TX_PCKT_INFO_NACK_RX)>>2); + +} + + +/** + * @brief Returns the source address of the received packet. + * @param None. + * @retval uint8_t Source address of the received packet. + */ +uint8_t SpiritPktCommonGetReceivedSourceAddress(void) +{ + uint8_t tempRegValue; + + /* Reads the RX_ADDR_FIELD1 register value */ + g_xStatus = SpiritSpiReadRegisters(RX_ADDR_FIELD1_BASE, 1, &tempRegValue); + + /* Returns value */ + return tempRegValue; + +} + + +/** + * @brief Returns the sequence number of the received packet. + * @param None. + * @retval uint8_t Received Sequence number. + */ +uint8_t SpiritPktCommonGetReceivedSeqNumber(void) +{ + uint8_t tempRegValue; + + /* Reads the RX_PCKT_INFO register value */ + g_xStatus = SpiritSpiReadRegisters(RX_PCKT_INFO_BASE, 1, &tempRegValue); + + /* Obtains and returns the sequence number */ + return tempRegValue & 0x03; + +} + + +/** + * @brief Returns the Nack bit of the received packet + * @param None. + * @retval uint8_t Value of the Nack bit. + */ +uint8_t SpiritPktCommonGetReceivedNackRx(void) +{ + uint8_t tempRegValue; + + /* Reads the RX_PCKT_INFO register value */ + g_xStatus = SpiritSpiReadRegisters(RX_PCKT_INFO_BASE, 1, &tempRegValue); + + /* Obtains and returns the RX nack bit */ + return (tempRegValue >> 2) & 0x01; + +} + + +/** + * @brief Returns the sequence number of the transmitted packet. + * @param None. + * @retval uint8_t Sequence number of the transmitted packet. + */ +uint8_t SpiritPktCommonGetTransmittedSeqNumber(void) +{ + uint8_t tempRegValue; + + /* Reads the TX_PCKT_INFO register value */ + g_xStatus = SpiritSpiReadRegisters(TX_PCKT_INFO_BASE, 1, &tempRegValue); + + /* Obtains and returns the TX sequence number */ + return (tempRegValue >> 4) & 0x07; + +} + + +/** + * @brief Returns the number of retransmission done on the transmitted packet. + * @param None. + * @retval uint8_t Number of retransmissions done until now. + */ +uint8_t SpiritPktCommonGetNReTx(void) +{ + uint8_t tempRetValue; + + /* Reads the TX_PCKT_INFO register value */ + g_xStatus = SpiritSpiReadRegisters(TX_PCKT_INFO_BASE, 1, &tempRetValue); + + /* Obtains and returns the number of retransmission done */ + return (tempRetValue & 0x0F); + +} + + +/** + * @brief If enabled RX packet is accepted only if the masked control field matches the + * masked control field reference (CONTROL_MASK & CONTROL_FIELD_REF == CONTROL_MASK & RX_CONTROL_FIELD). + * @param xNewState new state for Control filtering enable bit. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + * @note This filtering control is enabled by default but the control mask is by default set to 0. + * As a matter of fact the user has to enable the control filtering bit after the packet initialization + * because the PktInit routine disables it. + */ +void SpiritPktCommonFilterOnControlField(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + + /* Modify the register value: set or reset the control bit filtering */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Set or reset the CONTROL filtering enabling bit */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK; + } + else + { + tempRegValue &= ~PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK; + } + + /* Writes the new value on the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the enable bit of the control field filtering. + * @param None. + * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. + */ +SpiritFunctionalState SpiritPktCommonGetFilterOnControlField(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Gets the enable/disable bit in form of SpiritFunctionalState type */ + if(tempRegValue & PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktMbus.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktMbus.c new file mode 100644 index 000000000..f1aa9d49a --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktMbus.c @@ -0,0 +1,354 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktMbus.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT MBUS packets. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_PktMbus.h" +#include "SPIRIT_Radio.h" +#include "MCU_Interface.h" + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_PktMbus + * @{ + */ + + +/** + * @defgroup PktMbus_Private_TypesDefinitions Pkt MBUS Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Private_Defines Pkt MBUS Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Private_Macros Pkt MBUS Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Private_Variables Pkt MBUS Private Variables + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Private_FunctionPrototypes Pkt MBUS Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktMbus_Private_Functions Pkt MBUS Private Functions + * @{ + */ + + +/** + * @brief Initializes the SPIRIT MBUS packet according to the specified parameters in the PktMbusInit struct. + * @param pxPktMbusInit pointer to a PktMbusInit structure that contains the configuration information for the specified SPIRIT MBUS PACKET FORMAT. + * This parameter is a pointer to @ref PktMbusInit. + * @retval None. + */ +void SpiritPktMbusInit(PktMbusInit* pxPktMbusInit) +{ + uint8_t tempRegValue[3]; + + /* Check the parameters */ + s_assert_param(IS_MBUS_SUBMODE(pxPktMbusInit->xMbusSubmode)); + + /* Packet format config */ + SpiritPktMbusSetFormat(); + SpiritPktCommonFilterOnCrc(S_DISABLE); + SpiritRadioCsBlanking(S_ENABLE); + + /* Preamble, postamble and submode config */ + tempRegValue[0] = pxPktMbusInit->cPreambleLength; + tempRegValue[1] = pxPktMbusInit->cPostambleLength; + tempRegValue[2] = (uint8_t) pxPktMbusInit->xMbusSubmode; + + /* Writes the new values on the MBUS_PRMBL registers */ + g_xStatus = SpiritSpiWriteRegisters(MBUS_PRMBL_BASE, 3, tempRegValue); + +} + +/** + * @brief Returns the SPIRIT MBUS packet structure according to the specified parameters in the registers. + * @param pxPktMbusInit MBUS packet init structure. + * This parameter is a pointer to @ref PktMbusInit. + * @retval None. + */ +void SpiritPktMbusGetInfo(PktMbusInit* pxPktMbusInit) +{ + uint8_t tempRegValue[3]; + + /* Reads the MBUS regs value */ + g_xStatus = SpiritSpiReadRegisters(MBUS_PRMBL_BASE, 3, tempRegValue); + + /* Fit the structure */ + pxPktMbusInit->cPreambleLength = tempRegValue[0]; + pxPktMbusInit->cPostambleLength = tempRegValue[1]; + pxPktMbusInit->xMbusSubmode = (MbusSubmode) (tempRegValue[2]&0x0E); + +} + + +/** + * @brief Configures the MBUS packet format as the one used by SPIRIT. + * @param None. + * @retval None. + */ +void SpiritPktMbusSetFormat(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL3 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Sets format bits. Also set to 0 the direct RX mode bits */ + tempRegValue &= 0x0F; + tempRegValue |= ((uint8_t)PCKTCTRL3_PCKT_FRMT_MBUS); + + /* Writes value on the PCKTCTRL3 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Reads the PCKTCTRL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Build the new value. Set to 0 the direct TX mode bits */ + tempRegValue &= 0xF3; + + /* Writes the value on the PCKTCTRL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Reads the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Mask a reserved bit */ + tempRegValue &= ~0x20; + + /* Writes the value on the PROTOCOL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets how many chip sequence “01” shall be added in the preamble + * respect to the minimum value as defined according to the specified sub-mode. + * @param cPreamble the number of chip sequence. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktMbusSetPreamble(uint8_t cPreamble) +{ + /* Modifies the MBUS_PRMBL register value */ + g_xStatus = SpiritSpiWriteRegisters(MBUS_PRMBL_BASE, 1, &cPreamble); + +} + + +/** + * @brief Returns how many chip sequence "01" are added in the preamble + * respect to the minimum value as defined according to the specified sub-mode. + * @param None. + * @retval uint8_t Preable in number of "01" chip sequences. + */ +uint8_t SpiritPktMbusGetPreamble(void) +{ + uint8_t tempRegValue; + + /* Modifies the MBUS_PRMBL register value */ + g_xStatus = SpiritSpiReadRegisters(MBUS_PRMBL_BASE, 1, &tempRegValue); + + /* Return value */ + return tempRegValue; + +} + + +/** + * @brief Sets how many chip sequence “01” will be used in postamble + * @param cPostamble the number of chip sequence. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktMbusSetPostamble(uint8_t cPostamble) +{ + /* Modifies the MBUS_PSTMBL register value */ + g_xStatus = SpiritSpiWriteRegisters(MBUS_PSTMBL_BASE, 1, &cPostamble); + +} + + +/** + * @brief Returns how many chip sequence "01" are used in the postamble + * @param None. + * @retval uint8_t Postamble in number of "01" chip sequences. + */ +uint8_t SpiritPktMbusGetPostamble(void) +{ + uint8_t tempRegValue; + + /* Reads the MBUS_PSTMBL register */ + g_xStatus = SpiritSpiReadRegisters(MBUS_PSTMBL_BASE, 1, &tempRegValue); + + /* Returns value */ + return tempRegValue; + +} + + +/** + * @brief Sets the MBUS submode used. + * @param xMbusSubmode the submode used. + * This parameter can be any value of @ref MbusSubmode. + * @retval None. + */ +void SpiritPktMbusSetSubmode(MbusSubmode xMbusSubmode) +{ + /* Modifies the MBUS_CTRL register value */ + g_xStatus = SpiritSpiWriteRegisters(MBUS_CTRL_BASE, 1, (uint8_t*)xMbusSubmode); + +} + + +/** + * @brief Returns the MBUS submode used. + * @param None. + * @retval MbusSubmode MBUS submode. + */ +MbusSubmode SpiritPktMbusGetSubmode(void) +{ + uint8_t tempRegValue; + + /* Reads the MBUS_CTRL register value */ + g_xStatus = SpiritSpiReadRegisters(MBUS_CTRL_BASE, 1, &tempRegValue); + + /* Returns value */ + return (MbusSubmode) tempRegValue; + +} + + +/** + * @brief Sets the payload length for SPIRIT MBUS packets. + * @param nPayloadLength payload length in bytes. + * This parameter is an uint16_t. + * @retval None. + */ +void SpiritPktMbusSetPayloadLength(uint16_t nPayloadLength) +{ + uint8_t tempRegValue[2]; + + /* Computes PCKTLEN0 value from nPayloadLength */ + tempRegValue[1]=BUILD_PCKTLEN0(nPayloadLength);//(uint8_t)nPayloadLength; + /* Computes PCKTLEN1 value from nPayloadLength */ + tempRegValue[0]=BUILD_PCKTLEN1(nPayloadLength);//(uint8_t)(nPayloadLength>>8); + + /* Writes data on the PCKTLEN1/0 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTLEN1_BASE, 2, tempRegValue); + +} + + +/** + * @brief Returns the payload length for SPIRIT MBUS packets. + * @param None. + * @retval uint16_t Payload length in bytes. + */ +uint16_t SpiritPktMbusGetPayloadLength(void) +{ + uint8_t tempRegValue[2]; + + /* Reads the packet length registers */ + g_xStatus = SpiritSpiReadRegisters(PCKTLEN1_BASE, 2, tempRegValue); + + /* Returns the packet length */ + return ((((uint16_t)tempRegValue[0])<<8) + (uint16_t) tempRegValue[1]); + +} + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktStack.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktStack.c new file mode 100644 index 000000000..55d11a6f6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktStack.c @@ -0,0 +1,687 @@ +/** + ****************************************************************************** + * @file SPIRIT_PktStack.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT STack packets. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_PktStack.h" +#include "MCU_Interface.h" + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_PktStack + * @{ + */ + + +/** + * @defgroup PktStack_Private_TypesDefinitions Pkt STack Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktStack_Private_Defines Pkt STack Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktStack_Private_Macros Pkt STack Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktStack_Private_Variables Pkt STack Private Variables + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktStack_Private_FunctionPrototypes Pkt STack Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup PktStack_Private_Functions Pkt STack Private Functions + * @{ + */ + + +/** + * @brief Initializes the SPIRIT STack packet according to the specified + * parameters in the PktStackInit. + * @param pxPktStackInit STack packet init structure. + * This parameter is a pointer to @ref PktStackInit. + * @retval None. + */ +void SpiritPktStackInit(PktStackInit* pxPktStackInit) +{ + uint8_t tempRegValue[4], i; + + /* Check the parameters */ + s_assert_param(IS_STACK_PREAMBLE_LENGTH(pxPktStackInit->xPreambleLength)); + s_assert_param(IS_STACK_SYNC_LENGTH(pxPktStackInit->xSyncLength)); + s_assert_param(IS_STACK_CRC_MODE(pxPktStackInit->xCrcMode)); + s_assert_param(IS_STACK_LENGTH_WIDTH_BITS(pxPktStackInit->cPktLengthWidth)); + s_assert_param(IS_STACK_FIX_VAR_LENGTH(pxPktStackInit->xFixVarLength)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackInit->xFec)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackInit->xDataWhitening)); + s_assert_param(IS_STACK_CONTROL_LENGTH(pxPktStackInit->xControlLength)); + + + /* Reads the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); + + /* Mask a reserved bit */ + tempRegValue[0] &= ~0x20; + + /* Always (!) set the automatic packet filtering */ + tempRegValue[0] |= PROTOCOL1_AUTO_PCKT_FLT_MASK; + + /* Writes the value on register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); + + /* Reads the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Always reset the control and source filtering */ + tempRegValue[0] &= ~(PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK | PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK); + + /* Writes the value on register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + + /* Address and control length setting: source and destination address are always present so ADDRESS_LENGTH=2 */ + tempRegValue[0] = 0x10 | ((uint8_t) pxPktStackInit->xControlLength); + + + /* Packet format and width length setting */ + pxPktStackInit->cPktLengthWidth == 0 ? pxPktStackInit->cPktLengthWidth=1 : pxPktStackInit->cPktLengthWidth; + tempRegValue[1] = ((uint8_t) PCKTCTRL3_PCKT_FRMT_STACK) | ((uint8_t)(pxPktStackInit->cPktLengthWidth-1)); + + /* Preamble, sync and fixed or variable length setting */ + tempRegValue[2] = ((uint8_t) pxPktStackInit->xPreambleLength) | ((uint8_t) pxPktStackInit->xSyncLength) | + ((uint8_t) pxPktStackInit->xFixVarLength); + + /* CRC length, whitening and FEC setting */ + tempRegValue[3] = (uint8_t) pxPktStackInit->xCrcMode; + + if(pxPktStackInit->xDataWhitening == S_ENABLE) + { + tempRegValue[3] |= PCKTCTRL1_WHIT_MASK; + } + + if(pxPktStackInit->xFec == S_ENABLE) + { + tempRegValue[3] |= PCKTCTRL1_FEC_MASK; + } + + /* Writes registers */ + SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 4, tempRegValue); + + /* Sync words setting */ + for(i=0;i<4;i++) + { + if(i<3-(pxPktStackInit->xSyncLength >>1)) + { + tempRegValue[i]=0; + } + else + { + tempRegValue[i] = (uint8_t)(pxPktStackInit->lSyncWords>>(8*i)); + } + } + + /* Enables or disables the CRC check */ + if(pxPktStackInit->xCrcMode == PKT_NO_CRC) + { + SpiritPktStackFilterOnCrc(S_DISABLE); + } + else + { + SpiritPktStackFilterOnCrc(S_ENABLE); + } + + /* Writes registers */ + g_xStatus = SpiritSpiWriteRegisters(SYNC4_BASE, 4, tempRegValue); + +} + + +/** + * @brief Returns the SPIRIT STack packet structure according to the specified parameters in the registers. + * @param pxPktStackInit STack packet init structure. + * This parameter is a pointer to @ref PktStackInit. + * @retval None. + */ +void SpiritPktStackGetInfo(PktStackInit* pxPktStackInit) +{ + uint8_t tempRegValue[10]; + + /* Reads registers */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 10, tempRegValue); + + /* Length width */ + pxPktStackInit->cPktLengthWidth=(tempRegValue[1] & 0x0F)+1; + + /* Control length */ + pxPktStackInit->xControlLength=(StackControlLength)(tempRegValue[0] & 0x07); + + /* CRC mode */ + pxPktStackInit->xCrcMode=(StackCrcMode)(tempRegValue[3] & 0xE0); + + /* Whitening */ + pxPktStackInit->xDataWhitening=(SpiritFunctionalState)((tempRegValue[3] >> 4) & 0x01); + + /* FEC */ + pxPktStackInit->xFec=(SpiritFunctionalState)(tempRegValue[3] & 0x01); + + /* FIX or VAR bit */ + pxPktStackInit->xFixVarLength=(StackFixVarLength)(tempRegValue[2] & 0x01); + + /* Preamble length */ + pxPktStackInit->xPreambleLength=(StackPreambleLength)(tempRegValue[2] & 0xF8); + + /* Sync length */ + pxPktStackInit->xSyncLength=(StackSyncLength)(tempRegValue[2] & 0x06); + + /* sync Words */ + pxPktStackInit->lSyncWords=0; + for(uint8_t i=0 ; i<4 ; i++) + { + if(i>2-(pxPktStackInit->xSyncLength >>1)) + { + pxPktStackInit->lSyncWords |= tempRegValue[i+6]<<(8*i); + } + } + +} + + +/** + * @brief Initializes the SPIRIT STack packet addresses according to the specified + * parameters in the PktStackAddresses struct. + * @param pxPktStackAddresses STack packet addresses init structure. + * This parameter is a pointer to @ref PktStackAddressesInit . + * @retval None. + */ +void SpiritPktStackAddressesInit(PktStackAddressesInit* pxPktStackAddresses) +{ + uint8_t tempRegValue[3]; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackAddresses->xFilterOnMyAddress)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackAddresses->xFilterOnMulticastAddress)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackAddresses->xFilterOnBroadcastAddress)); + + /* Reads the filtering options ragister */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Enables or disables filtering on my address */ + if(pxPktStackAddresses->xFilterOnMyAddress == S_ENABLE) + { + tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; + } + else + { + tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; + } + + /* Enables or disables filtering on multicast address */ + if(pxPktStackAddresses->xFilterOnMulticastAddress == S_ENABLE) + { + tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; + } + else + { + tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; + } + + /* Enables or disables filtering on broadcast address */ + if(pxPktStackAddresses->xFilterOnBroadcastAddress == S_ENABLE) + { + tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; + } + else + { + tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; + } + + /* Writes value on the register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Fills array with the addresses passed in the structure */ + tempRegValue[0] = pxPktStackAddresses->cBroadcastAddress; + tempRegValue[1] = pxPktStackAddresses->cMulticastAddress; + tempRegValue[2] = pxPktStackAddresses->cMyAddress; + + /* Writes them on the addresses registers */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); + +} + + +/** +* @brief Returns the SPIRIT STack packet addresses structure according to the specified +* parameters in the registers. +* @param pxPktStackAddresses STack packet addresses init structure. +* This parameter is a pointer to @ref PktStackAddresses. +* @retval None. +*/ +void SpiritPktStackGetAddressesInfo(PktStackAddressesInit* pxPktStackAddresses) +{ + uint8_t tempRegValue[3]; + + /* Reads values on the PCKT_FLT_GOALS registers */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); + + /* Fit the structure with the read addresses */ + pxPktStackAddresses->cBroadcastAddress = tempRegValue[0]; + pxPktStackAddresses->cMulticastAddress = tempRegValue[1]; + pxPktStackAddresses->cMyAddress = tempRegValue[2]; + + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); + + /* Fit the structure with the read filtering bits */ + pxPktStackAddresses->xFilterOnBroadcastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 1) & 0x01); + pxPktStackAddresses->xFilterOnMulticastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 2) & 0x01); + pxPktStackAddresses->xFilterOnMyAddress = (SpiritFunctionalState)((tempRegValue[0] >> 3) & 0x01); + +} + + +/** +* @brief Initializes the SPIRIT STack packet LLP options according to the specified +* parameters in the PktStackLlpInit struct. +* @param pxPktStackLlpInit STack packet LLP init structure. +* This parameter is a pointer to @ref PktStackLlpInit. +* @retval None. +*/ +void SpiritPktStackLlpInit(PktStackLlpInit* pxPktStackLlpInit) +{ + uint8_t tempRegValue[2]; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackLlpInit->xPiggybacking)); + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackLlpInit->xAutoAck)); + s_assert_param(IS_STACK_NMAX_RETX(pxPktStackLlpInit->xNMaxRetx)); + /* check if piggybacking is enabled and autoack is disabled */ + s_assert_param(!(pxPktStackLlpInit->xPiggybacking==S_ENABLE && pxPktStackLlpInit->xAutoAck==S_DISABLE)); + + /* Piggybacking mechanism setting on the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 2, tempRegValue); + if(pxPktStackLlpInit->xPiggybacking == S_ENABLE) + { + tempRegValue[0] |= PROTOCOL1_PIGGYBACKING_MASK; + } + else + { + tempRegValue[0] &= ~PROTOCOL1_PIGGYBACKING_MASK; + } + + /* RX and TX autoack mechanisms setting on the PROTOCOL0 register */ + if(pxPktStackLlpInit->xAutoAck == S_ENABLE) + { + tempRegValue[1] |= PROTOCOL0_AUTO_ACK_MASK; + } + else + { + tempRegValue[1] &= ~PROTOCOL0_AUTO_ACK_MASK; + } + + /* Max number of retransmission setting */ + tempRegValue[1] &= ~PROTOCOL0_NMAX_RETX_MASK; + tempRegValue[1] |= pxPktStackLlpInit->xNMaxRetx; + + /* Writes registers */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 2, tempRegValue); + +} + + +/** + * @brief Returns the SPIRIT STack packet LLP options according to the specified + * values in the registers. + * @param pxPktStackLlpInit STack packet LLP structure. + * This parameter is a pointer to @ref PktStackLlpInit. + * @retval None. + */ +void SpiritPktStackLlpGetInfo(PktStackLlpInit* pxPktStackLlpInit) +{ + uint8_t tempRegValue[2]; + + /* Piggybacking mechanism setting on the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 2, tempRegValue); + + /* Fit the structure with the read values */ + pxPktStackLlpInit->xPiggybacking = (SpiritFunctionalState)((tempRegValue[0] >> 6) & 0x01); + pxPktStackLlpInit->xAutoAck = (SpiritFunctionalState)((tempRegValue[1] >> 2) & 0x01); + pxPktStackLlpInit->xNMaxRetx = (StackNMaxReTx)(tempRegValue[1] & PROTOCOL0_NMAX_RETX_MASK); + +} + + +/** + * @brief Configures the STack packet format for SPIRIT. + * @param None. + * @retval None. + */ +void SpiritPktStackSetFormat(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL3 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Build value to be written. Also set to 0 the direct RX mode bits */ + tempRegValue &= 0x0F; + tempRegValue |= ((uint8_t)PCKTCTRL3_PCKT_FRMT_STACK); + + /* Writes the value on the PCKTCTRL3 register. */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Reads the PCKTCTRL1 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Build the new value. Set to 0 the direct TX mode bits */ + tempRegValue &= 0xF3; + + /* Writes the PCKTCTRL1 value on register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); + + /* Reads the PROTOCOL1 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Mask a reserved bit */ + tempRegValue &= ~0x20; + + /* Writes the value on the PROTOCOL1 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets the address length for SPIRIT STack packets (always 2). + * @param None. + * @retval None. + */ +void SpiritPktStackSetAddressLength(void) +{ + uint8_t tempRegValue; + + /* Reads the PCKTCTRL4 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + + /* Build the new value */ + tempRegValue &= ~PCKTCTRL4_ADDRESS_LEN_MASK; + tempRegValue |= ((uint8_t)0x10); + + /* Writes the value on the PCKTCTRL4 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets the payload length for SPIRIT STack packets. Since the packet length + * depends from the address (always 2 for this packet format) + * and the control field size, this function reads the control length register + * content in order to determine the correct packet length to be written. + * @param nPayloadLength payload length in bytes. + * This parameter can be any value of uint16_t. + * @retval None. + */ +void SpiritPktStackSetPayloadLength(uint16_t nPayloadLength) +{ + uint8_t tempRegValue[2]; + + /* Computes the oversize (address + control) size */ + uint16_t overSize = 2 + (uint16_t) SpiritPktStackGetControlLength(); + + /* Computes PCKTLEN0 value from lPayloadLength */ + tempRegValue[1]=STACK_BUILD_PCKTLEN0(nPayloadLength+overSize); + /* Computes PCKTLEN1 value from lPayloadLength */ + tempRegValue[0]=STACK_BUILD_PCKTLEN1(nPayloadLength+overSize); + + /* Writes the value on the PCKTLENx registers */ + g_xStatus = SpiritSpiWriteRegisters(PCKTLEN1_BASE, 2, tempRegValue); + +} + + +/** + * @brief Returns the payload length for SPIRIT STack packets. Since the + * packet length depends from the address and the control + * field size, this function reads the correspondent + * registers in order to determine the correct payload length + * to be returned. + * @param None. + * @retval uint16_t Payload length. + */ +uint16_t SpiritPktStackGetPayloadLength(void) +{ + uint8_t tempRegValue[2]; + /* Computes the oversize (address + control) size */ + uint16_t overSize = 2 + (uint16_t) SpiritPktStackGetControlLength(); + + /* Reads the PCKTLEN1 registers value */ + g_xStatus = SpiritSpiReadRegisters(PCKTLEN1_BASE, 2, tempRegValue); + + /* Rebuild and return the payload length value */ + return (((uint16_t) tempRegValue[1])<<8 + (uint16_t) tempRegValue[0] - overSize); + +} + + +/** + * @brief Computes and sets the variable payload length for SPIRIT STack packets. + * @param nMaxPayloadLength payload length in bytes. + * This parameter is an uint16_t. + * @param xControlLength control length in bytes. + * This parameter can be any value of @ref StackControlLength. + * @retval None. + */ +void SpiritPktStackSetVarLengthWidth(uint16_t nMaxPayloadLength, StackControlLength xControlLength) +{ + uint8_t tempRegValue, + i; + uint32_t packetLength; + + + /* packet length = payload length + address length (2) + control length */ + packetLength=nMaxPayloadLength+2+xControlLength; + + /* Computes the number of bits */ + for(i=0;i<16;i++) + { + if(packetLength == 0) + { + break; + } + packetLength >>= 1; + } + i==0 ? i=1 : i; + + /* Reads the PCKTCTRL3 register value */ + g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + + /* Build the register value */ + tempRegValue &= ~PCKTCTRL3_LEN_WID_MASK; + tempRegValue |= ((uint8_t)(i-1)); + + /* Writes the PCKTCTRL3 register value */ + g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Rx packet source mask. Used to mask the address of the accepted packets. If 0 -> no filtering. + * @param cMask Rx source mask. + * This parameter is an uint8_t. + * @retval None. + */ +void SpiritPktStackSetRxSourceMask(uint8_t cMask) +{ + /* Writes value on the register PCKT_FLT_GOALS_SOURCE_MASK */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_SOURCE_MASK_BASE, 1, &cMask); + +} + + +/** + * @brief Returns the Rx packet source mask. Used to mask the address of the accepted packets. If 0 -> no filtering. + * @param None. + * @retval uint8_t Rx source mask. + */ +uint8_t SpiritPktStackGetRxSourceMask(void) +{ + uint8_t tempRegValue; + + /* Writes value on the PCKT_FLT_GOALS_SOURCE_MASK register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_SOURCE_MASK_BASE, 1, &tempRegValue); + + /* Return the read value */ + return tempRegValue; + +} + +/** + * @brief Returns the packet length field of the received packet. + * @param None. + * @retval uint16_t Packet length. + */ +uint16_t SpiritPktStackGetReceivedPktLength(void) +{ + uint8_t tempRegValue[2]; + uint16_t tempLength; + + /* Reads the RX_PCKT_LENx registers value */ + g_xStatus = SpiritSpiReadRegisters(RX_PCKT_LEN1_BASE, 2, tempRegValue); + + /* Rebuild and return the the length field */ + tempLength = ((((uint16_t) tempRegValue[0]) << 8) + (uint16_t) tempRegValue[1]); + + /* Computes the oversize (address + control) size */ + tempLength -= 2 + (uint16_t) SpiritPktStackGetControlLength(); + + return tempLength; + +} + + +/** + * @brief If enabled RX packet is accepted only if the masked source address field matches the + * masked source address field reference (SOURCE_MASK & SOURCE_FIELD_REF == SOURCE_MASK & RX_SOURCE_FIELD). + * @param xNewState new state for Source address filtering enable bit. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + * @note This filtering control is enabled by default but the source address mask is by default set to 0. + * As a matter of fact the user has to enable the source filtering bit after the packet initialization + * because the PktInit routine disables it. + */ +void SpiritPktStackFilterOnSourceAddress(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + + /* Modify the register value: set or reset the source bit filtering */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + + /* Set or reset the SOURCE ADDRESS filtering enabling bit */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK; + } + else + { + tempRegValue &= ~PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK; + } + + /* Writes the new value on the PCKT_FLT_OPTIONS register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); + +} + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Qi.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Qi.c new file mode 100644 index 000000000..8d042675f --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Qi.c @@ -0,0 +1,636 @@ +/** + ****************************************************************************** + * @file SPIRIT_Qi.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT QI. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Qi.h" +#include "MCU_Interface.h" + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_Qi + * @{ + */ + + +/** + * @defgroup Qi_Private_TypesDefinitions QI Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Qi_Private_Defines QI Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Qi_Private_Macros QI Private Macros + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Qi_Private_Variables QI Private Variables + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Qi_Private_FunctionPrototypes QI Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Qi_Private_Functions QI Private Functions + * @{ + */ + +/** + * @brief Enables/Disables the PQI Preamble Quality Indicator check. The running peak PQI is + * compared to a threshold value and the preamble valid IRQ is asserted as soon as the threshold is passed. + * @param xNewState new state for PQI check. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritQiPqiCheck(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the QI register value */ + g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); + + /* Enables or disables the PQI Check bit on the QI_BASE register */ + if(xNewState == S_ENABLE) + { + tempRegValue |= QI_PQI_MASK; + } + else + { + tempRegValue &= ~QI_PQI_MASK; + } + + /* Writes value on the QI register */ + g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Enables/Disables the Synchronization Quality Indicator check. The running peak SQI is + * compared to a threshold value and the sync valid IRQ is asserted as soon as the threshold is passed. + * @param xNewState new state for SQI check. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritQiSqiCheck(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the QI register value */ + g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); + + /* Enables or disables the SQI Check bit on the QI_BASE register */ + if(xNewState == S_ENABLE) + { + tempRegValue |= QI_SQI_MASK; + } + else + { + tempRegValue &= ~QI_SQI_MASK; + } + + /* Writes value on the QI register */ + g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Sets the PQI threshold. The preamble quality threshold is 4*PQI_TH (PQI_TH = 0..15). + * @param xPqiThr parameter of the formula above. + * This variable is a @ref PqiThreshold. + * @retval None. + */ +void SpiritQiSetPqiThreshold(PqiThreshold xPqiThr) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PQI_THR(xPqiThr)); + + /* Reads the QI register value */ + g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); + + /* Build the PQI threshold value to be written */ + tempRegValue &= 0xC3; + tempRegValue |= ((uint8_t)xPqiThr); + + /* Writes value on the QI register */ + g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the PQI threshold. The preamble quality threshold is 4*PQI_TH (PQI_TH = 0..15). + * @param None. + * @retval PqiThreshold PQI threshold (PQI_TH of the formula above). + */ +PqiThreshold SpiritQiGetPqiThreshold(void) +{ + uint8_t tempRegValue; + + /* Reads the QI register value */ + g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); + + /* Rebuild and return the PQI threshold value */ + return (PqiThreshold)(tempRegValue & 0x3C); + +} + + +/** + * @brief Sets the SQI threshold. The synchronization quality + * threshold is equal to 8 * SYNC_LEN - 2 * SQI_TH with SQI_TH = 0..3. When SQI_TH is 0 perfect match is required; when + * SQI_TH = 1, 2, 3 then 1, 2, or 3 bit errors are respectively accepted. It is recommended that the SQI check is always + * enabled. + * @param xSqiThr parameter of the formula above. + * This parameter is a @ref SqiThreshold. + * @retval None. + */ +void SpiritQiSetSqiThreshold(SqiThreshold xSqiThr) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SQI_THR(xSqiThr)); + + /* Reads the QI register value */ + g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); + + /* Build the SQI threshold value to be written */ + tempRegValue &= 0x3F; + tempRegValue |= ((uint8_t)xSqiThr); + + /* Writes the new value on the QI register */ + g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the SQI threshold. The synchronization quality threshold is equal to 8 * SYNC_LEN - 2 * SQI_TH with SQI_TH = 0..3. + * @param None. + * @retval SqiThreshold SQI threshold (SQI_TH of the formula above). + */ +SqiThreshold SpiritQiGetSqiThreshold(void) +{ + uint8_t tempRegValue; + + /* Reads the QI register value */ + g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); + + /* Rebuild and return the SQI threshold value */ + return (SqiThreshold)(tempRegValue & 0xC0); + +} + + +/** + * @brief Returns the PQI value. + * @param None. + * @retval uint8_t PQI value. + */ +uint8_t SpiritQiGetPqi(void) +{ + uint8_t tempRegValue; + + /* Reads the LINK_QUALIF2 register value */ + g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF2_BASE, 1, &tempRegValue); + + /* Returns the PQI value */ + return tempRegValue; + +} + + +/** + * @brief Returns the SQI value. + * @param None. + * @retval uint8_t SQI value. + */ +uint8_t SpiritQiGetSqi(void) +{ + uint8_t tempRegValue; + + /* Reads the register LINK_QUALIF1 value */ + g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF1_BASE, 1, &tempRegValue); + + /* Rebuild and return the SQI value */ + return (tempRegValue & 0x7F); + +} + + +/** + * @brief Returns the LQI value. + * @param None. + * @retval uint8_t LQI value. + */ +uint8_t SpiritQiGetLqi(void) +{ + uint8_t tempRegValue; + + /* Reads the LINK_QUALIF0 register value */ + g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF0_BASE, 1, &tempRegValue); + + /* Rebuild and return the LQI value */ + return ((tempRegValue & 0xF0)>> 4); + +} + + +/** + * @brief Returns the CS status. + * @param None. + * @retval SpiritFlagStatus CS value (S_SET or S_RESET). + */ +SpiritFlagStatus SpiritQiGetCs(void) +{ + uint8_t tempRegValue; + + /* Reads the LINK_QUALIF1 register value */ + g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF1_BASE, 1, &tempRegValue); + + /* Rebuild and returns the CS status value */ + if((tempRegValue & 0x80) == 0) + { + return S_RESET; + } + else + { + return S_SET; + } + +} + + +/** + * @brief Returns the RSSI value. The measured power is reported in steps of half a dB from 0 to 255 and is offset in such a way that -120 dBm corresponds + * to 20. + * @param None. + * @retval uint8_t RSSI value. + */ +uint8_t SpiritQiGetRssi(void) +{ + uint8_t tempRegValue; + + /* Reads the RSSI_LEVEL register value */ + g_xStatus = SpiritSpiReadRegisters(RSSI_LEVEL_BASE, 1, &tempRegValue); + + /* Returns the RSSI value */ + return tempRegValue; + +} + + +/** + * @brief Sets the RSSI threshold. + * @param cRssiThr RSSI threshold reported in steps of half a dBm with a -130 dBm offset. + * This parameter must be a uint8_t. + * @retval None. + */ +void SpiritQiSetRssiThreshold(uint8_t cRssiThr) +{ + /* Writes the new value on the RSSI_TH register */ + g_xStatus = SpiritSpiWriteRegisters(RSSI_TH_BASE, 1, &cRssiThr); + +} + + +/** + * @brief Returns the RSSI threshold. + * @param None. + * @retval uint8_t RSSI threshold. + */ +uint8_t SpiritQiGetRssiThreshold(void) +{ + uint8_t tempRegValue; + + /* Reads the RSSI_TH register value */ + g_xStatus = SpiritSpiReadRegisters(RSSI_TH_BASE, 1, &tempRegValue); + + /* Returns RSSI threshold */ + return tempRegValue; + +} + + +/** + * @brief Computes the RSSI threshold from its dBm value according to the formula: (RSSI[Dbm] + 130)/0.5 + * @param nDbmValue RSSI threshold reported in dBm. + * This parameter must be a sint16_t. + * @retval uint8_t RSSI threshold corresponding to dBm value. + */ +uint8_t SpiritQiComputeRssiThreshold(int nDbmValue) +{ + /* Check the parameters */ + s_assert_param(IS_RSSI_THR_DBM(nDbmValue)); + + /* Computes the RSSI threshold for register */ + return 2*(nDbmValue+130); + +} + +/** + * @brief Sets the RSSI threshold from its dBm value according to the formula: (RSSI[Dbm] + 130)/0.5. + * @param nDbmValue RSSI threshold reported in dBm. + * This parameter must be a sint16_t. + * @retval None. + */ +void SpiritQiSetRssiThresholddBm(int nDbmValue) +{ + uint8_t tempRegValue=2*(nDbmValue+130); + + /* Check the parameters */ + s_assert_param(IS_RSSI_THR_DBM(nDbmValue)); + + /* Writes the new value on the RSSI_TH register */ + g_xStatus = SpiritSpiWriteRegisters(RSSI_TH_BASE, 1, &tempRegValue); + +} + +/** + * @brief Sets the RSSI filter gain. This parameter sets the bandwidth of a low pass IIR filter (RSSI_FLT register, allowed values 0..15), a + * lower values gives a faster settling of the measurements but lower precision. The recommended value for such parameter is 14. + * @param xRssiFg RSSI filter gain value. + * This parameter can be any value of @ref RssiFilterGain. + * @retval None. + */ +void SpiritQiSetRssiFilterGain(RssiFilterGain xRssiFg) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_RSSI_FILTER_GAIN(xRssiFg)); + + /* Reads the RSSI_FLT register */ + g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + + /* Sets the specified filter gain */ + tempRegValue &= 0x0F; + tempRegValue |= ((uint8_t)xRssiFg); + + /* Writes the new value on the RSSI_FLT register */ + g_xStatus = SpiritSpiWriteRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the RSSI filter gain. + * @param None. + * @retval RssiFilterGain RSSI filter gain. + */ +RssiFilterGain SpiritQiGetRssiFilterGain(void) +{ + uint8_t tempRegValue; + + /* Reads the RSSI_FLT register */ + g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + + /* Rebuild and returns the filter gain value */ + return (RssiFilterGain)(tempRegValue & 0xF0); + +} + + +/** + * @brief Sets the CS Mode. When static carrier sensing is used (cs_mode = 0), the carrier sense signal is asserted when the measured RSSI is above the + * value specified in the RSSI_TH register and is deasserted when the RSSI falls 3 dB below the same threshold. + * When dynamic carrier sense is used (cs_mode = 1, 2, 3), the carrier sense signal is asserted if the signal is above the + * threshold and a fast power increase of 6, 12 or 18 dB is detected; it is deasserted if a power fall of the same amplitude is + * detected. + * @param xCsMode CS mode selector. + * This parameter can be any value of @ref CSMode. + * @retval None. + */ +void SpiritQiSetCsMode(CSMode xCsMode) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_CS_MODE(xCsMode)); + + /* Reads the RSSI_FLT register */ + g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + + /* Sets bit to select the CS mode */ + tempRegValue &= ~0x0C; + tempRegValue |= ((uint8_t)xCsMode); + + /* Writes the new value on the RSSI_FLT register */ + g_xStatus = SpiritSpiWriteRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the CS Mode. + * @param None. + * @retval CSMode CS mode. + */ +CSMode SpiritQiGetCsMode(void) +{ + uint8_t tempRegValue; + + /* Reads the RSSI_FLT register */ + g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + + /* Rebuild and returns the CS mode value */ + return (CSMode)(tempRegValue & 0x0C); + +} + +/** + * @brief Enables/Disables the CS Timeout Mask. If enabled CS value contributes to timeout disabling. + * @param xNewState new state for CS Timeout Mask. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritQiCsTimeoutMask(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PROTOCOL2 register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + + /* Enables or disables the CS timeout mask */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PROTOCOL2_CS_TIMEOUT_MASK; + } + else + { + tempRegValue &= ~PROTOCOL2_CS_TIMEOUT_MASK; + } + + /* Writes the new value on the PROTOCOL2 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Enables/Disables the PQI Timeout Mask. If enabled PQI value contributes to timeout disabling. + * @param xNewState new state for PQI Timeout Mask. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritQiPqiTimeoutMask(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PROTOCOL2 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + + /* Enables or disables the PQI timeout mask */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PROTOCOL2_PQI_TIMEOUT_MASK; + } + else + { + tempRegValue &= ~PROTOCOL2_PQI_TIMEOUT_MASK; + } + + /* Writes the new value on the PROTOCOL2 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Enables/Disables the SQI Timeout Mask. If enabled SQI value contributes to timeout disabling. + * @param xNewState new state for SQI Timeout Mask. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritQiSqiTimeoutMask(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PROTOCOL2 register */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + + /* Enables or disables the SQI timeout mask */ + if(xNewState == S_ENABLE) + { + tempRegValue |= PROTOCOL2_SQI_TIMEOUT_MASK; + } + else + { + tempRegValue &= ~PROTOCOL2_SQI_TIMEOUT_MASK; + } + + /* Writes the new value on the PROTOCOL2 register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + +} + + +/** + *@} + */ + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Radio.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Radio.c new file mode 100644 index 000000000..8a129c003 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Radio.c @@ -0,0 +1,3144 @@ +/** + ****************************************************************************** + * @file SPIRIT_Radio.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief This file provides all the low level API to manage Analog and Digital + * radio part of SPIRIT. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Radio.h" +#include "MCU_Interface.h" +#include + +/** @addtogroup SPIRIT_Libraries +* @{ +*/ + + +/** @addtogroup SPIRIT_Radio +* @{ +*/ + + +/** @defgroup Radio_Private_TypesDefinitions Radio Private Types Definitions +* @{ +*/ + + +/** +* @} +*/ + + +/** @defgroup Radio_Private_Defines Radio Private Defines +* @{ +*/ + + + + +/** +* @} +*/ + + +/** @defgroup Radio_Private_Macros Radio Private Macros +* @{ +*/ +#define XTAL_FLAG(xtalFrequency) (xtalFrequency>=25e6) ? XTAL_FLAG_26_MHz:XTAL_FLAG_24_MHz + +#define ROUND(A) (((A-(uint32_t)A)> 0.5)? (uint32_t)A+1:(uint32_t)A) +/** +* @} +*/ + + +/** @defgroup Radio_Private_Variables Radio Private Variables +* @{ +*/ +/** +* @brief The Xtal frequency. To be set by the user (see SetXtalFreq() function) +*/ +static uint32_t s_lXtalFrequency; + +/** +* @brief Factor is: B/2 used in the formula for SYNTH word calculation +*/ +static const uint8_t s_vectcBHalfFactor[4]={(HIGH_BAND_FACTOR/2), (MIDDLE_BAND_FACTOR/2), (LOW_BAND_FACTOR/2), (VERY_LOW_BAND_FACTOR/2)}; + +/** +* @brief BS value to write in the SYNT0 register according to the selected band +*/ +static const uint8_t s_vectcBandRegValue[4]={SYNT0_BS_6, SYNT0_BS_12, SYNT0_BS_16, SYNT0_BS_32}; + + +/** +* @brief It represents the available channel bandwidth times 10 for 26 Mhz xtal. +* @note The channel bandwidth for others xtal frequencies can be computed since this table +* multiplying the current table by a factor xtal_frequency/26e6. +*/ +static const uint16_t s_vectnBandwidth26M[90]= +{ + 8001, 7951, 7684, 7368, 7051, 6709, 6423, 5867, 5414, \ + 4509, 4259, 4032, 3808, 3621, 3417, 3254, 2945, 2703, \ + 2247, 2124, 2015, 1900, 1807, 1706, 1624, 1471, 1350, \ + 1123, 1062, 1005, 950, 903, 853, 812, 735, 675, \ + 561, 530, 502, 474, 451, 426, 406, 367, 337, \ + 280, 265, 251, 237, 226, 213, 203, 184, 169, \ + 140, 133, 126, 119, 113, 106, 101, 92, 84, \ + 70, 66, 63, 59, 56, 53, 51, 46, 42, \ + 35, 33, 31, 30, 28, 27, 25, 23, 21, \ + 18, 17, 16, 15, 14, 13, 13, 12, 11 +}; + +/** +* @brief It represents the available VCO frequencies +*/ +static const uint16_t s_vectnVCOFreq[16]= +{ + 4644, 4708, 4772, 4836, 4902, 4966, 5030, 5095, \ + 5161, 5232, 5303, 5375, 5448, 5519, 5592, 5663 +}; + +/** +* @brief This variable is used to enable or disable +* the VCO calibration WA called at the end of the SpiritRadioSetFrequencyBase fcn. +* Default is enabled. +*/ +static SpiritFunctionalState xDoVcoCalibrationWA=S_ENABLE; + + +/** +* @brief These values are used to interpolate the power curves. +* Interpolation curves are linear in the following 3 regions: +* - reg value: 1 to 13 (up region) +* - reg value: 13 to 40 (mid region) +* - reg value: 41 to 90 (low region) +* power_reg = m*power_dBm + q +* For each band the order is: {m-up, q-up, m-mid, q-mid, m-low, q-low}. +* @note The power interpolation curves have been extracted +* by measurements done on the divisional evaluation boards. +*/ +static const float fPowerFactors[5][6]={ + {-2.11,25.66,-2.11,25.66,-2.00,31.28}, /* 915 */ + {-2.04,23.45,-2.04,23.45,-1.95,27.66}, /* 868 */ + {-3.48,38.45,-1.89,27.66,-1.92,30.23}, /* 433 */ + {-3.27,35.43,-1.80,26.31,-1.89,29.61}, /* 315 */ + {-4.18,50.66,-1.80,30.04,-1.86,32.22}, /* 169 */ +}; + +/** +* @} +*/ + + +/** @defgroup Radio_Private_FunctionPrototypes Radio Private Function Prototypes +* @{ +*/ + + +/** +* @} +*/ + + +/** @defgroup Radio_Private_Functions Radio Private Functions +* @{ +*/ + +/** +* @brief Initializes the SPIRIT analog and digital radio part according to the specified +* parameters in the pxSRadioInitStruct. +* @param pxSRadioInitStruct pointer to a SRadioInit structure that +* contains the configuration information for the analog radio part of SPIRIT. +* @retval Error code: 0=no error, 1=error during calibration of VCO. +*/ +uint8_t SpiritRadioInit(SRadioInit* pxSRadioInitStruct) +{ + int32_t FOffsetTmp; + uint8_t anaRadioRegArray[8], digRadioRegArray[4]; + int16_t xtalOffsetFactor; + uint8_t drM, drE, FdevM, FdevE, bwM, bwE; + + /* Workaround for Vtune */ + uint8_t value = 0xA0; SpiritSpiWriteRegisters(0x9F, 1, &value); + + /* Calculates the offset respect to RF frequency and according to xtal_ppm parameter: (xtal_ppm*FBase)/10^6 */ + FOffsetTmp = (int32_t)(((float)pxSRadioInitStruct->nXtalOffsetPpm*pxSRadioInitStruct->lFrequencyBase)/PPM_FACTOR); + + /* Check the parameters */ + s_assert_param(IS_FREQUENCY_BAND(pxSRadioInitStruct->lFrequencyBase)); + s_assert_param(IS_MODULATION_SELECTED(pxSRadioInitStruct->xModulationSelect)); + s_assert_param(IS_DATARATE(pxSRadioInitStruct->lDatarate)); + s_assert_param(IS_FREQUENCY_OFFSET(FOffsetTmp,s_lXtalFrequency)); + s_assert_param(IS_CHANNEL_SPACE(pxSRadioInitStruct->nChannelSpace,s_lXtalFrequency)); + s_assert_param(IS_F_DEV(pxSRadioInitStruct->lFreqDev,s_lXtalFrequency)); + + /* Disable the digital, ADC, SMPS reference clock divider if fXO>24MHz or fXO<26MHz */ + SpiritSpiCommandStrobes(COMMAND_STANDBY); + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + }while(g_xStatus.MC_STATE!=MC_STATE_STANDBY); + + if(s_lXtalFrequencylBandwidth,s_lXtalFrequency)); + } + else + { + SpiritRadioSetDigDiv(S_ENABLE); + s_assert_param(IS_CH_BW(pxSRadioInitStruct->lBandwidth,(s_lXtalFrequency>>1))); + } + + /* Goes in READY state */ + SpiritSpiCommandStrobes(COMMAND_READY); + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + }while(g_xStatus.MC_STATE!=MC_STATE_READY); + + /* Calculates the FC_OFFSET parameter and cast as signed int: FOffsetTmp = (Fxtal/2^18)*FC_OFFSET */ + xtalOffsetFactor = (int16_t)(((float)FOffsetTmp*FBASE_DIVIDER)/s_lXtalFrequency); + anaRadioRegArray[2] = (uint8_t)((((uint16_t)xtalOffsetFactor)>>8)&0x0F); + anaRadioRegArray[3] = (uint8_t)(xtalOffsetFactor); + + /* Calculates the channel space factor */ + anaRadioRegArray[0] =((uint32_t)pxSRadioInitStruct->nChannelSpace<<9)/(s_lXtalFrequency>>6)+1; + + SpiritManagementWaTRxFcMem(pxSRadioInitStruct->lFrequencyBase); + + /* 2nd order DEM algorithm enabling */ + uint8_t tmpreg; SpiritSpiReadRegisters(0xA3, 1, &tmpreg); + tmpreg &= ~0x02; SpiritSpiWriteRegisters(0xA3, 1, &tmpreg); + + /* Check the channel center frequency is in one of the possible range */ + s_assert_param(IS_FREQUENCY_BAND((pxSRadioInitStruct->lFrequencyBase + ((xtalOffsetFactor*s_lXtalFrequency)/FBASE_DIVIDER) + pxSRadioInitStruct->nChannelSpace * pxSRadioInitStruct->cChannelNumber))); + + /* Calculates the datarate mantissa and exponent */ + SpiritRadioSearchDatarateME(pxSRadioInitStruct->lDatarate, &drM, &drE); + digRadioRegArray[0] = (uint8_t)(drM); + digRadioRegArray[1] = (uint8_t)(0x00 | pxSRadioInitStruct->xModulationSelect |drE); + + /* Read the fdev register to preserve the clock recovery algo bit */ + SpiritSpiReadRegisters(0x1C, 1, &tmpreg); + + /* Calculates the frequency deviation mantissa and exponent */ + SpiritRadioSearchFreqDevME(pxSRadioInitStruct->lFreqDev, &FdevM, &FdevE); + digRadioRegArray[2] = (uint8_t)((FdevE<<4) | (tmpreg&0x08) | FdevM); + + /* Calculates the channel filter mantissa and exponent */ + SpiritRadioSearchChannelBwME(pxSRadioInitStruct->lBandwidth, &bwM, &bwE); + + digRadioRegArray[3] = (uint8_t)((bwM<<4) | bwE); + + float if_off=(3.0*480140)/(s_lXtalFrequency>>12)-64; + + uint8_t ifOffsetAna = ROUND(if_off); + + if(s_lXtalFrequency>13)-64; + + /* ... otherwise recompute it */ + anaRadioRegArray[1] = ROUND(if_off); + } +// if(s_lXtalFrequency==24000000) { +// ifOffsetAna = 0xB6; +// anaRadioRegArray[1] = 0xB6; +// } +// if(s_lXtalFrequency==25000000) { +// ifOffsetAna = 0xAC; +// anaRadioRegArray[1] = 0xAC; +// } +// if(s_lXtalFrequency==26000000) { +// ifOffsetAna = 0xA3; +// anaRadioRegArray[1] = 0xA3; +// } +// if(s_lXtalFrequency==48000000) { +// ifOffsetAna = 0x3B; +// anaRadioRegArray[1] = 0xB6; +// } +// if(s_lXtalFrequency==50000000) { +// ifOffsetAna = 0x36; +// anaRadioRegArray[1] = 0xAC; +// } +// if(s_lXtalFrequency==52000000) { +// ifOffsetAna = 0x31; +// anaRadioRegArray[1] = 0xA3; +// } + + g_xStatus = SpiritSpiWriteRegisters(IF_OFFSET_ANA_BASE, 1, &ifOffsetAna); + + + /* Sets Xtal configuration */ + if(s_lXtalFrequency>DOUBLE_XTAL_THR) + { + SpiritRadioSetXtalFlag(XTAL_FLAG((s_lXtalFrequency/2))); + } + else + { + SpiritRadioSetXtalFlag(XTAL_FLAG(s_lXtalFrequency)); + } + + /* Sets the channel number in the corresponding register */ + SpiritSpiWriteRegisters(CHNUM_BASE, 1, &pxSRadioInitStruct->cChannelNumber); + + /* Configures the Analog Radio registers */ + SpiritSpiWriteRegisters(CHSPACE_BASE, 4, anaRadioRegArray); + + /* Configures the Digital Radio registers */ + g_xStatus = SpiritSpiWriteRegisters(MOD1_BASE, 4, digRadioRegArray); + + /* Enable the freeze option of the AFC on the SYNC word */ + SpiritRadioAFCFreezeOnSync(S_ENABLE); + + /* Set the IQC correction optimal value */ + anaRadioRegArray[0]=0x80; + anaRadioRegArray[1]=0xE3; + g_xStatus = SpiritSpiWriteRegisters(0x99, 2, anaRadioRegArray); + + return SpiritRadioSetFrequencyBase(pxSRadioInitStruct->lFrequencyBase); + +} + + +/** +* @brief Returns the SPIRIT analog and digital radio structure according to the registers value. +* @param pxSRadioInitStruct pointer to a SRadioInit structure that +* contains the configuration information for the analog radio part of SPIRIT. +* @retval None. +*/ +void SpiritRadioGetInfo(SRadioInit* pxSRadioInitStruct) +{ + uint8_t anaRadioRegArray[8], digRadioRegArray[4]; + BandSelect band; + int16_t xtalOffsetFactor; + + /* Get the RF board version */ + //SpiritVersion xSpiritVersion = SpiritGeneralGetSpiritVersion(); + + /* Reads the Analog Radio registers */ + SpiritSpiReadRegisters(SYNT3_BASE, 8, anaRadioRegArray); + + /* Reads the Digital Radio registers */ + g_xStatus = SpiritSpiReadRegisters(MOD1_BASE, 4, digRadioRegArray); + + /* Reads the operating band masking the Band selected field */ + if((anaRadioRegArray[3] & 0x07) == SYNT0_BS_6) + { + band = HIGH_BAND; + } + else if ((anaRadioRegArray[3] & 0x07) == SYNT0_BS_12) + { + band = MIDDLE_BAND; + } + else if ((anaRadioRegArray[3] & 0x07) == SYNT0_BS_16) + { + band = LOW_BAND; + } + else if ((anaRadioRegArray[3] & 0x07) == SYNT0_BS_32) + { + band = VERY_LOW_BAND; + } + else + { + /* if it is another value, set it to a valid one in order to avoid access violation */ + uint8_t tmp=(anaRadioRegArray[3]&0xF8)|SYNT0_BS_6; + SpiritSpiWriteRegisters(SYNT0_BASE,1,&tmp); + band = HIGH_BAND; + } + + /* Computes the synth word */ + uint32_t synthWord = (uint32_t)((((uint32_t)(anaRadioRegArray[0]&0x1F))<<21)+(((uint32_t)(anaRadioRegArray[1]))<<13)+\ + (((uint32_t)(anaRadioRegArray[2]))<<5)+(((uint32_t)(anaRadioRegArray[3]))>>3)); + + /* Calculates the frequency base */ + uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; + pxSRadioInitStruct->lFrequencyBase = (uint32_t)round(synthWord*(((double)s_lXtalFrequency)/(FBASE_DIVIDER*cRefDiv*s_vectcBHalfFactor[band]))); + + /* Calculates the Offset Factor */ + uint16_t xtalOffTemp = ((((uint16_t)anaRadioRegArray[6])<<8)+((uint16_t)anaRadioRegArray[7])); + + /* If a negative number then convert the 12 bit 2-complement in a 16 bit number */ + if(xtalOffTemp & 0x0800) + { + xtalOffTemp = xtalOffTemp | 0xF000; + } + else + { + xtalOffTemp = xtalOffTemp & 0x0FFF; + } + + xtalOffsetFactor = *((int16_t*)(&xtalOffTemp)); + + /* Calculates the frequency offset in ppm */ + pxSRadioInitStruct->nXtalOffsetPpm =(int16_t)((uint32_t)xtalOffsetFactor*s_lXtalFrequency*PPM_FACTOR)/((uint32_t)FBASE_DIVIDER*pxSRadioInitStruct->lFrequencyBase); + + /* Channel space */ + pxSRadioInitStruct->nChannelSpace = anaRadioRegArray[4]*(s_lXtalFrequency>>15); + + /* Channel number */ + pxSRadioInitStruct->cChannelNumber = SpiritRadioGetChannel(); + + /* Modulation select */ + pxSRadioInitStruct->xModulationSelect = (ModulationSelect)(digRadioRegArray[1] & 0x70); + + /* Reads the frequency deviation for mantissa and exponent */ + uint8_t FDevM = digRadioRegArray[2]&0x07; + uint8_t FDevE = (digRadioRegArray[2]&0xF0)>>4; + + /* Reads the channel filter register for mantissa and exponent */ + uint8_t bwM = (digRadioRegArray[3]&0xF0)>>4; + uint8_t bwE = digRadioRegArray[3]&0x0F; + + uint8_t cDivider = 0; + cDivider = SpiritRadioGetDigDiv(); + + /* Calculates the datarate */ + pxSRadioInitStruct->lDatarate = ((s_lXtalFrequency>>(5+cDivider))*(256+digRadioRegArray[0]))>>(23-(digRadioRegArray[1]&0x0F)); + + /* Calculates the frequency deviation */ + // (((s_lXtalFrequency>>6)*(8+FDevM))>>(12-FDevE+cCorrection)); + pxSRadioInitStruct->lFreqDev =(uint32_t)((float)s_lXtalFrequency/(((uint32_t)1)<<18)*(uint32_t)((8.0+FDevM)/2*(1<lBandwidth = (uint32_t)(100.0*s_vectnBandwidth26M[bwM+(bwE*9)]*((s_lXtalFrequency>>cDivider)/26e6)); + +} + + +/** +* @brief Sets the Xtal configuration in the ANA_FUNC_CONF0 register. +* @param xXtal one of the possible value of the enum type XtalFrequency. +* @arg XTAL_FLAG_24_MHz: in case of 24 MHz crystal +* @arg XTAL_FLAG_26_MHz: in case of 26 MHz crystal +* @retval None. +*/ +void SpiritRadioSetXtalFlag(XtalFlag xXtal) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_XTAL_FLAG(xXtal)); + + /* Reads the ANA_FUNC_CONF_0 register */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + if(xXtal == XTAL_FLAG_26_MHz) + { + tempRegValue|=SELECT_24_26_MHZ_MASK; + } + else + { + tempRegValue &= (~SELECT_24_26_MHZ_MASK); + } + + /* Sets the 24_26MHz_SELECT field in the ANA_FUNC_CONF_0 register */ + g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the Xtal configuration in the ANA_FUNC_CONF0 register. +* @param None. +* @retval XtalFrequency Settled Xtal configuration. +*/ +XtalFlag SpiritRadioGetXtalFlag(void) +{ + uint8_t tempRegValue; + + /* Reads the Xtal configuration in the ANA_FUNC_CONF_0 register and return the value */ + g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); + + return (XtalFlag)((tempRegValue & 0x40)>>6); + +} + + +/** +* @brief Returns the charge pump word for a given VCO frequency. +* @param lFc channel center frequency expressed in Hz. +* This parameter can be a value in one of the following ranges:
    +*
  • High_Band: from 779 MHz to 915 MHz
    • +*
  • Middle Band: from 387 MHz to 470 MHz
    • +*
  • Low Band: from 300 MHz to 348 MHz
    • +*
  • Very low Band: from 150 MHz to 174 MHz
+* @retval uint8_t Charge pump word. +*/ +uint8_t SpiritRadioSearchWCP(uint32_t lFc) +{ + int8_t i; + uint32_t vcofreq; + uint8_t BFactor; + + /* Check the channel center frequency is in one of the possible range */ + s_assert_param(IS_FREQUENCY_BAND(lFc)); + + /* Search the operating band */ + if(IS_FREQUENCY_BAND_HIGH(lFc)) + { + BFactor = HIGH_BAND_FACTOR; + } + else if(IS_FREQUENCY_BAND_MIDDLE(lFc)) + { + BFactor = MIDDLE_BAND_FACTOR; + } + else if(IS_FREQUENCY_BAND_LOW(lFc)) + { + BFactor = LOW_BAND_FACTOR; + } + else if(IS_FREQUENCY_BAND_VERY_LOW(lFc)) + { + BFactor = VERY_LOW_BAND_FACTOR; + } + + /* Calculates the VCO frequency VCOFreq = lFc*B */ + vcofreq = (lFc/1000000)*BFactor; + + /* Search in the vco frequency array the charge pump word */ + if(vcofreq>=s_vectnVCOFreq[15]) + { + i=15; + } + else + { + /* Search the value */ + for(i=0 ; i<15 && vcofreq>s_vectnVCOFreq[i] ; i++); + + /* Be sure that it is the best approssimation */ + if (i!=0 && s_vectnVCOFreq[i]-vcofreq>vcofreq-s_vectnVCOFreq[i-1]) + i--; + } + + /* Return index */ + return (i%8); + +} + +/** +* @brief Returns the synth word. +* @param None. +* @retval uint32_t Synth word. +*/ +uint32_t SpiritRadioGetSynthWord(void) +{ + uint8_t regArray[4]; + + /* Reads the SYNTH registers, build the synth word and return it */ + g_xStatus = SpiritSpiReadRegisters(SYNT3_BASE, 4, regArray); + return ((((uint32_t)(regArray[0]&0x1F))<<21)+(((uint32_t)(regArray[1]))<<13)+\ + (((uint32_t)(regArray[2]))<<5)+(((uint32_t)(regArray[3]))>>3)); + +} + + +/** +* @brief Sets the SYNTH registers. +* @param lSynthWord the synth word to write in the SYNTH[3:0] registers. +* @retval None. +*/ +void SpiritRadioSetSynthWord(uint32_t lSynthWord) +{ + uint8_t tempArray[4]; + uint8_t tempRegValue; + + /* Reads the SYNT0 register */ + g_xStatus = SpiritSpiReadRegisters(SYNT0_BASE, 1, &tempRegValue); + + /* Mask the Band selected field */ + tempRegValue &= 0x07; + + /* Build the array for SYNTH registers */ + tempArray[0] = (uint8_t)((lSynthWord>>21)&(0x0000001F)); + tempArray[1] = (uint8_t)((lSynthWord>>13)&(0x000000FF)); + tempArray[2] = (uint8_t)((lSynthWord>>5)&(0x000000FF)); + tempArray[3] = (uint8_t)(((lSynthWord&0x0000001F)<<3)| tempRegValue); + + /* Writes the synth word in the SYNTH registers */ + g_xStatus = SpiritSpiWriteRegisters(SYNT3_BASE, 4, tempArray); + +} + + +/** +* @brief Sets the operating band. +* @param xBand the band to set. +* This parameter can be one of following parameters: +* @arg HIGH_BAND High_Band selected: from 779 MHz to 915 MHz +* @arg MIDDLE_BAND: Middle Band selected: from 387 MHz to 470 MHz +* @arg LOW_BAND: Low Band selected: from 300 MHz to 348 MHz +* @arg VERY_LOW_BAND: Very low Band selected: from 150 MHz to 174 MHz +* @retval None. +*/ +void SpiritRadioSetBand(BandSelect xBand) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_BAND_SELECTED(xBand)); + + /* Reads the SYNT0 register*/ + g_xStatus = SpiritSpiReadRegisters(SYNT0_BASE, 1, &tempRegValue); + + /* Mask the SYNTH[4;0] field and write the BS value */ + tempRegValue &= 0xF8; + tempRegValue |= s_vectcBandRegValue[xBand]; + + /* Configures the SYNT0 register setting the operating band */ + g_xStatus = SpiritSpiWriteRegisters(SYNT0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the operating band. +* @param None. +* @retval BandSelect Settled band. +* This returned value can be one of the following parameters: +* @arg HIGH_BAND High_Band selected: from 779 MHz to 915 MHz +* @arg MIDDLE_BAND: Middle Band selected: from 387 MHz to 470 MHz +* @arg LOW_BAND: Low Band selected: from 300 MHz to 348 MHz +* @arg VERY_LOW_BAND: Very low Band selected: from 150 MHz to 174 MHz +*/ +BandSelect SpiritRadioGetBand(void) +{ + uint8_t tempRegValue; + + /* Reads the SYNT0 register */ + g_xStatus = SpiritSpiReadRegisters(SYNT0_BASE, 1, &tempRegValue); + + /* Mask the Band selected field */ + if((tempRegValue & 0x07) == SYNT0_BS_6) + { + return HIGH_BAND; + } + else if ((tempRegValue & 0x07) == SYNT0_BS_12) + { + return MIDDLE_BAND; + } + else if ((tempRegValue & 0x07) == SYNT0_BS_16) + { + return LOW_BAND; + } + else + { + return VERY_LOW_BAND; + } + +} + + +/** +* @brief Sets the channel number. +* @param cChannel the channel number. +* @retval None. +*/ +void SpiritRadioSetChannel(uint8_t cChannel) +{ + /* Writes the CHNUM register */ + g_xStatus = SpiritSpiWriteRegisters(CHNUM_BASE, 1, &cChannel); + +} + + +/** +* @brief Returns the actual channel number. +* @param None. +* @retval uint8_t Actual channel number. +*/ +uint8_t SpiritRadioGetChannel(void) +{ + uint8_t tempRegValue; + + /* Reads the CHNUM register and return the value */ + g_xStatus = SpiritSpiReadRegisters(CHNUM_BASE, 1, &tempRegValue); + + return tempRegValue; + +} + + +/** +* @brief Sets the channel space factor in channel space register. +* The channel spacing step is computed as F_Xo/32768. +* @param fChannelSpace the channel space expressed in Hz. +* @retval None. +*/ +void SpiritRadioSetChannelSpace(uint32_t fChannelSpace) +{ + uint8_t cChannelSpaceFactor; + + /* Round to the nearest integer */ + cChannelSpaceFactor = ((uint32_t)fChannelSpace*CHSPACE_DIVIDER)/s_lXtalFrequency; + + /* Write value into the register */ + g_xStatus = SpiritSpiWriteRegisters(CHSPACE_BASE, 1, &cChannelSpaceFactor); + +} + + +/** +* @brief Returns the channel space register. +* @param None. +* @retval uint32_t Channel space. The channel space is: CS = channel_space_factor x XtalFrequency/2^15 +* where channel_space_factor is the CHSPACE register value. +*/ +uint32_t SpiritRadioGetChannelSpace(void) +{ + uint8_t channelSpaceFactor; + + /* Reads the CHSPACE register, calculate the channel space and return it */ + g_xStatus = SpiritSpiReadRegisters(CHSPACE_BASE, 1, &channelSpaceFactor); + + /* Compute the Hertz value and return it */ + return ((channelSpaceFactor*s_lXtalFrequency)/CHSPACE_DIVIDER); + +} + + +/** +* @brief Sets the FC OFFSET register starting from xtal ppm value. +* @param nXtalPpm the xtal offset expressed in ppm. +* @retval None. +*/ +void SpiritRadioSetFrequencyOffsetPpm(int16_t nXtalPpm) +{ + uint8_t tempArray[2]; + int16_t xtalOffsetFactor; + uint32_t synthWord, fBase; + int32_t FOffsetTmp; + BandSelect band; + + /* Reads the synth word */ + synthWord = SpiritRadioGetSynthWord(); + + /* Reads the operating band */ + band = SpiritRadioGetBand(); + + /* Calculates the frequency base */ + uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; + fBase = synthWord*(s_lXtalFrequency/(s_vectcBHalfFactor[band]*cRefDiv)/FBASE_DIVIDER); + + /* Calculates the offset respect to RF frequency and according to xtal_ppm parameter */ + FOffsetTmp = (int32_t)(((float)nXtalPpm*fBase)/PPM_FACTOR); + + /* Check the Offset is in the correct range */ + s_assert_param(IS_FREQUENCY_OFFSET(FOffsetTmp,s_lXtalFrequency)); + + /* Calculates the FC_OFFSET value to write in the corresponding register */ + xtalOffsetFactor = (int16_t)(((float)FOffsetTmp*FBASE_DIVIDER)/s_lXtalFrequency); + + /* Build the array related to the FC_OFFSET_1 and FC_OFFSET_0 register */ + tempArray[0]=(uint8_t)((((uint16_t)xtalOffsetFactor)>>8)&0x0F); + tempArray[1]=(uint8_t)(xtalOffsetFactor); + + /* Writes the FC_OFFSET registers */ + g_xStatus = SpiritSpiWriteRegisters(FC_OFFSET1_BASE, 2, tempArray); + +} + + +/** +* @brief Sets the FC OFFSET register starting from frequency offset expressed in Hz. +* @param lFOffset frequency offset expressed in Hz as signed word. +* @retval None. +*/ +void SpiritRadioSetFrequencyOffset(int32_t lFOffset) +{ + uint8_t tempArray[2]; + int16_t offset; + + /* Check that the Offset is in the correct range */ + s_assert_param(IS_FREQUENCY_OFFSET(lFOffset,s_lXtalFrequency)); + + /* Calculates the offset value to write in the FC_OFFSET register */ + offset = (int16_t)(((float)lFOffset*FBASE_DIVIDER)/s_lXtalFrequency); + + /* Build the array related to the FC_OFFSET_1 and FC_OFFSET_0 register */ + tempArray[0]=(uint8_t)((((uint16_t)offset)>>8)&0x0F); + tempArray[1]=(uint8_t)(offset); + + /* Writes the FC_OFFSET registers */ + g_xStatus = SpiritSpiWriteRegisters(FC_OFFSET1_BASE, 2, tempArray); + +} + + +/** +* @brief Returns the actual frequency offset. +* @param None. +* @retval int32_t Frequency offset expressed in Hz as signed word. +*/ +int32_t SpiritRadioGetFrequencyOffset(void) +{ + uint8_t tempArray[2]; + int16_t xtalOffsetFactor; + + /* Reads the FC_OFFSET registers */ + g_xStatus = SpiritSpiReadRegisters(FC_OFFSET1_BASE, 2, tempArray); + + /* Calculates the Offset Factor */ + uint16_t xtalOffTemp = ((((uint16_t)tempArray[0])<<8)+((uint16_t)tempArray[1])); + + if(xtalOffTemp & 0x0800) + { + xtalOffTemp = xtalOffTemp | 0xF000; + } + else + { + xtalOffTemp = xtalOffTemp & 0x0FFF; + } + + xtalOffsetFactor = *((int16_t*)(&xtalOffTemp)); + + /* Calculates the frequency offset and return it */ + return ((int32_t)(xtalOffsetFactor*s_lXtalFrequency)/FBASE_DIVIDER); + +} + + + +/** +* @brief Sets the Synth word and the Band Select register according to desired base carrier frequency. +* In this API the Xtal configuration is read out from +* the corresponding register. The user shall fix it before call this API. +* @param lFBase the base carrier frequency expressed in Hz as unsigned word. +* @retval Error code: 0=no error, 1=error during calibration of VCO. +*/ +uint8_t SpiritRadioSetFrequencyBase(uint32_t lFBase) +{ + uint32_t synthWord, Fc; + uint8_t band, anaRadioRegArray[4], wcp; + + /* Check the parameter */ + s_assert_param(IS_FREQUENCY_BAND(lFBase)); + + /* Search the operating band */ + if(IS_FREQUENCY_BAND_HIGH(lFBase)) + { + band = HIGH_BAND; + } + else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) + { + band = MIDDLE_BAND; + } + else if(IS_FREQUENCY_BAND_LOW(lFBase)) + { + band = LOW_BAND; + } + else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) + { + band = VERY_LOW_BAND; + } + + int32_t FOffset = SpiritRadioGetFrequencyOffset(); + uint32_t lChannelSpace = SpiritRadioGetChannelSpace(); + uint8_t cChannelNum = SpiritRadioGetChannel(); + + /* Calculates the channel center frequency */ + Fc = lFBase + FOffset + lChannelSpace*cChannelNum; + + /* Reads the reference divider */ + uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; + + /* Selects the VCO */ + switch(band) + { + case VERY_LOW_BAND: + if(Fc<161281250) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + break; + + case LOW_BAND: + if(Fc<322562500) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + break; + + case MIDDLE_BAND: + if(Fc<430083334) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + break; + + case HIGH_BAND: + if(Fc<860166667) + { + SpiritCalibrationSelectVco(VCO_L); + } + else + { + SpiritCalibrationSelectVco(VCO_H); + } + } + + /* Search the VCO charge pump word and set the corresponding register */ + wcp = SpiritRadioSearchWCP(Fc); + + synthWord = (uint32_t)(lFBase*s_vectcBHalfFactor[band]*(((double)(FBASE_DIVIDER*cRefDiv))/s_lXtalFrequency)); + + /* Build the array of registers values for the analog part */ + anaRadioRegArray[0] = (uint8_t)(((synthWord>>21)&(0x0000001F))|(wcp<<5)); + anaRadioRegArray[1] = (uint8_t)((synthWord>>13)&(0x000000FF)); + anaRadioRegArray[2] = (uint8_t)((synthWord>>5)&(0x000000FF)); + anaRadioRegArray[3] = (uint8_t)(((synthWord&0x0000001F)<<3)| s_vectcBandRegValue[band]); + + /* Configures the needed Analog Radio registers */ + g_xStatus = SpiritSpiWriteRegisters(SYNT3_BASE, 4, anaRadioRegArray); + + if(xDoVcoCalibrationWA==S_ENABLE) + return SpiritManagementWaVcoCalibration(); + + return 0; +} + +/** +* @brief To say to the set frequency base if do or not the VCO calibration WA. +* @param S_ENABLE or S_DISABLE the WA procedure. +* @retval None. +*/ +void SpiritRadioVcoCalibrationWAFB(SpiritFunctionalState xNewstate) +{ + xDoVcoCalibrationWA=xNewstate; +} + +/** +* @brief Returns the base carrier frequency. +* @param None. +* @retval uint32_t Base carrier frequency expressed in Hz as unsigned word. +*/ +uint32_t SpiritRadioGetFrequencyBase(void) +{ + uint32_t synthWord; + BandSelect band; + + /* Reads the synth word */ + synthWord = SpiritRadioGetSynthWord(); + + /* Reads the operating band */ + band = SpiritRadioGetBand(); + + uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv() + 1; + + /* Calculates the frequency base and return it */ + return (uint32_t)round(synthWord*(((double)s_lXtalFrequency)/(FBASE_DIVIDER*cRefDiv*s_vectcBHalfFactor[band]))); +} + + +/** +* @brief Returns the actual channel center frequency. +* @param None. +* @retval uint32_t Actual channel center frequency expressed in Hz. +*/ +uint32_t SpiritRadioGetCenterFrequency(void) +{ + int32_t offset; + uint8_t channel; + uint32_t fBase; + uint32_t channelSpace; + + /* Reads the frequency base */ + fBase = SpiritRadioGetFrequencyBase(); + + /* Reads the frequency offset */ + offset = SpiritRadioGetFrequencyOffset(); + + /* Reads the channel space */ + channelSpace = SpiritRadioGetChannelSpace(); + + /* Reads the channel number */ + channel = SpiritRadioGetChannel(); + + /* Calculates the channel center frequency and return it */ + return (uint32_t)(fBase + offset + (uint32_t)(channelSpace*channel)); + +} + + +/** +* @brief Returns the mantissa and exponent, whose value used in the datarate formula +* will give the datarate value closer to the given datarate. +* @param fDatarate datarate expressed in bps. This parameter ranging between 100 and 500000. +* @param pcM pointer to the returned mantissa value. +* @param pcE pointer to the returned exponent value. +* @retval None. +*/ +void SpiritRadioSearchDatarateME(uint32_t lDatarate, uint8_t* pcM, uint8_t* pcE) +{ + volatile SpiritBool find = S_FALSE; + int8_t i=15; + uint8_t cMantissaTmp; + uint8_t cDivider = 0; + + /* Check the parameters */ + s_assert_param(IS_DATARATE(lDatarate)); + + cDivider = (uint8_t)SpiritRadioGetDigDiv(); + + /* Search in the datarate array the exponent value */ + while(!find && i>=0) + { + if(lDatarate>=(s_lXtalFrequency>>(20-i+cDivider))) + { + find = S_TRUE; + } + else + { + i--; + } + } + i<0 ? i=0 : i; + *pcE = i; + + /* Calculates the mantissa value according to the datarate formula */ + cMantissaTmp = (lDatarate*((uint32_t)1<<(23-i)))/(s_lXtalFrequency>>(5+cDivider))-256; + + /* Finds the mantissa value with less approximation */ + int16_t mantissaCalculation[3]; + for(uint8_t j=0;j<3;j++) + { + if((cMantissaTmp+j-1)) + { + mantissaCalculation[j]=lDatarate-(((256+cMantissaTmp+j-1)*(s_lXtalFrequency>>(5+cDivider)))>>(23-i)); + } + else + { + mantissaCalculation[j]=0x7FFF; + } + } + uint16_t mantissaCalculationDelta = 0xFFFF; + for(uint8_t j=0;j<3;j++) + { + if(S_ABS(mantissaCalculation[j])=0) || ((i_tmp+j-1)<=89)) + { + chfltCalculation[j] = lBandwidth - (uint32_t)((s_vectnBandwidth26M[i_tmp+j-1]*lChfltFactor)/2600); + } + else + { + chfltCalculation[j] = 0x7FFF; + } + } + uint16_t chfltDelta = 0xFFFF; + + for(uint8_t j=0;j<3;j++) + { + if(S_ABS(chfltCalculation[j])>(5+cDivider))*(256+tempRegValue[0]))>>(23-(tempRegValue[1]&0x0F))); +} + + +/** +* @brief Sets the frequency deviation. +* @param fFDev frequency deviation expressed in Hz. Be sure that this value +* is in the correct range [F_Xo*8/2^18, F_Xo*7680/2^18] Hz. +* @retval None. +*/ +void SpiritRadioSetFrequencyDev(uint32_t lFDev) +{ + uint8_t FDevM, FDevE, tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_F_DEV(lFDev, s_lXtalFrequency)); + + /* Calculates the frequency deviation mantissa and exponent */ + SpiritRadioSearchFreqDevME(lFDev, &FDevM, &FDevE); + + /* Reads the FDEV0 register */ + SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); + + /* Mask the other fields and set the frequency deviation mantissa and exponent */ + tempRegValue &= 0x08; + tempRegValue |= ((FDevE<<4)|(FDevM)); + + /* Writes the Frequency deviation register */ + g_xStatus = SpiritSpiWriteRegisters(FDEV0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the frequency deviation. +* @param None. +* @retval uint32_t Frequency deviation value expressed in Hz. +* This value will be in the range [F_Xo*8/2^18, F_Xo*7680/2^18] Hz. +*/ +uint32_t SpiritRadioGetFrequencyDev(void) +{ + uint8_t tempRegValue, FDevM, FDevE; + + + /* Reads the frequency deviation register for mantissa and exponent */ + g_xStatus = SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); + FDevM = tempRegValue&0x07; + FDevE = (tempRegValue&0xF0)>>4; + + /* Calculates the frequency deviation and return it */ + //return (((s_lXtalFrequency>>6)*(8+FDevM))>>(13-FDevE)); + + return (uint32_t)((float)s_lXtalFrequency/(((uint32_t)1)<<18)*(uint32_t)((8.0+FDevM)/2*(1<>4; + bwE = tempRegValue&0x0F; + + /* Reads the channel filter bandwidth from the look-up table and return it */ + return (uint32_t)(100.0*s_vectnBandwidth26M[bwM+(bwE*9)]*s_lXtalFrequency/26e6); + +} + + +/** +* @brief Sets the modulation type. +* @param xModulation modulation to set. +* This parameter shall be of type @ref ModulationSelect . +* @retval None. +*/ +void SpiritRadioSetModulation(ModulationSelect xModulation) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_MODULATION_SELECTED(xModulation)); + + /* Reads the modulation register */ + SpiritSpiReadRegisters(MOD0_BASE, 1, &tempRegValue); + + /* Mask the other fields and set the modulation type */ + tempRegValue &=0x8F; + tempRegValue |= xModulation; + + /* Writes the modulation register */ + g_xStatus = SpiritSpiWriteRegisters(MOD0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the modulation type used. +* @param None. +* @retval ModulationSelect Settled modulation type. +*/ +ModulationSelect SpiritRadioGetModulation(void) +{ + uint8_t tempRegValue; + + /* Reads the modulation register MOD0*/ + g_xStatus = SpiritSpiReadRegisters(MOD0_BASE, 1, &tempRegValue); + + /* Return the modulation type */ + return (ModulationSelect)(tempRegValue&0x70); + +} + + +/** +* @brief Enables or Disables the Continuous Wave transmit mode. +* @param xNewState new state for power ramping. +* This parameter can be: S_ENABLE or S_DISABLE . +* @retval None. +*/ +void SpiritRadioCWTransmitMode(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the modulation register MOD0 and mask the CW field */ + SpiritSpiReadRegisters(MOD0_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |=MOD0_CW; + } + else + { + tempRegValue &= (~MOD0_CW); + } + + /* Writes the new value in the MOD0 register */ + g_xStatus = SpiritSpiWriteRegisters(MOD0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Sets the OOK Peak Decay. +* @param xOokDecay Peak decay control for OOK. +* This parameter shall be of type @ref OokPeakDecay . +* @retval None. +*/ +void SpiritRadioSetOokPeakDecay(OokPeakDecay xOokDecay) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_OOK_PEAK_DECAY(xOokDecay)); + + /* Reads the RSSI_FLT register */ + SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + + /* Mask the other fields and set OOK Peak Decay */ + tempRegValue &= 0xFC; + tempRegValue |= xOokDecay; + + /* Writes the RSSI_FLT register to set the new OOK peak dacay value */ + g_xStatus = SpiritSpiWriteRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the OOK Peak Decay. +* @param None +* @retval OokPeakDecay Ook peak decay value. +*/ +OokPeakDecay SpiritRadioGetOokPeakDecay(void) +{ + uint8_t tempRegValue; + + /* Reads the OOK peak decay register RSSI_FLT_BASE*/ + g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); + + /* Returns the OOK peak decay */ + return (OokPeakDecay) (tempRegValue & 0x03); + +} + +/** +* @brief Returns the PA register value that corresponds to the passed dBm power. +* @param lFbase Frequency base expressed in Hz. +* @param fPowerdBm Desired power in dBm. +* @retval Register value as byte. +* @note The power interpolation curves used by this function have been extracted +* by measurements done on the divisional evaluation boards. +*/ +uint8_t SpiritRadioGetdBm2Reg(uint32_t lFBase, float fPowerdBm) +{ + uint8_t i; + uint8_t j=0; + float fReg; + + if(IS_FREQUENCY_BAND_HIGH(lFBase)) + { + i=0; + if(lFBase<900000000) i=1;// 868 + } + else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) + { + i=2; + } + else if(IS_FREQUENCY_BAND_LOW(lFBase)) + { + i=3; + } + else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) + { + i=4; + } + + j=1; + if(fPowerdBm>0 && 13.0/fPowerFactors[i][2]-fPowerFactors[i][3]/fPowerFactors[i][2]fPowerdBm) + j=2; + + fReg=fPowerFactors[i][2*j]*fPowerdBm+fPowerFactors[i][2*j+1]; + + if(fReg<1) + fReg=1; + else if(fReg>90) + fReg=90; + + return ((uint8_t)fReg); +} + + +/** +* @brief Returns the dBm power that corresponds to the value of PA register. +* @param lFbase Frequency base expressed in Hz. +* @param cPowerReg Register value of the PA. +* @retval Power in dBm as float. +* @note The power interpolation curves used by this function have been extracted +* by measurements done on the divisional evaluation boards. +*/ +float SpiritRadioGetReg2dBm(uint32_t lFBase, uint8_t cPowerReg) +{ + uint8_t i; + uint8_t j=0; + float fPower; + + if(cPowerReg==0 || cPowerReg>90) + return (-130.0); + + if(IS_FREQUENCY_BAND_HIGH(lFBase)) + { + i=0; + if(lFBase<900000000) i=1;// 868 + } + else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) + { + i=2; + } + else if(IS_FREQUENCY_BAND_LOW(lFBase)) + { + i=3; + } + else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) + { + i=4; + } + + j=1; + if(cPowerReg<13) j=0; + else if(cPowerReg>40) j=2; + + fPower=(((float)cPowerReg)/fPowerFactors[i][2*j]-fPowerFactors[i][2*j+1]/fPowerFactors[i][2*j]); + + return fPower; +} + +/** +* @brief Configures the Power Amplifier Table and registers with value expressed in dBm. +* @param cPALevelMaxIndex number of levels to set. This parameter shall be in the range [0:7]. +* @param cWidth step width expressed in terms of bit period units Tb/8. +* This parameter shall be in the range [1:4]. +* @param xCLoad one of the possible value of the enum type PALoadCapacitor. +* @arg LOAD_0_PF No additional PA load capacitor +* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor +* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor +* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor +* @param pfPAtabledBm pointer to an array of PA values in dbm between [-PA_LOWER_LIMIT: PA_UPPER_LIMIT] dbm. +* The first element shall be the lower level (PA_LEVEL[0]) value and the last element +* the higher level one (PA_LEVEL[paLevelMaxIndex]). +* @retval None. +*/ +void SpiritRadioSetPATabledBm(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, float* pfPAtabledBm) +{ + uint8_t palevel[9], address, paLevelValue; + uint32_t lFBase=SpiritRadioGetFrequencyBase(); + + /* Check the parameters */ + s_assert_param(IS_PA_MAX_INDEX(cPALevelMaxIndex)); + s_assert_param(IS_PA_STEP_WIDTH(cWidth)); + s_assert_param(IS_PA_LOAD_CAP(xCLoad)); + + /* Check the PA level in dBm is in the range and calculate the PA_LEVEL value + to write in the corresponding register using the linearization formula */ + for(int i=0; i<=cPALevelMaxIndex; i++) + { + s_assert_param(IS_PAPOWER_DBM(*pfPAtabledBm)); + paLevelValue=SpiritRadioGetdBm2Reg(lFBase,(*pfPAtabledBm)); + palevel[cPALevelMaxIndex-i]=paLevelValue; + pfPAtabledBm++; + } + + /* Sets the PA_POWER[0] register */ + palevel[cPALevelMaxIndex+1]=xCLoad|(cWidth-1)<<3|cPALevelMaxIndex; + + /* Sets the base address */ + address=PA_POWER8_BASE+7-cPALevelMaxIndex; + + /* Configures the PA_POWER registers */ + g_xStatus = SpiritSpiWriteRegisters(address, cPALevelMaxIndex+2, palevel); + +} + + +/** +* @brief Returns the Power Amplifier Table and registers, returning values in dBm. +* @param pcPALevelMaxIndex pointer to the number of levels settled. +* This parameter will be in the range [0:7]. +* @param pfPAtabledBm pointer to an array of 8 elements containing the PA value in dbm. +* The first element will be the PA_LEVEL_0 and the last element +* will be PA_LEVEL_7. Any value higher than PA_UPPER_LIMIT implies no output +* power (output stage is in high impedance). +* @retval None. +*/ +void SpiritRadioGetPATabledBm(uint8_t* pcPALevelMaxIndex, float* pfPAtabledBm) +{ + uint8_t palevelvect[9]; + uint32_t lFBase=SpiritRadioGetFrequencyBase(); + + /* Reads the PA_LEVEL_x registers and the PA_POWER_0 register */ + g_xStatus = SpiritSpiReadRegisters(PA_POWER8_BASE, 9, palevelvect); + + /* Fill the PAtable */ + for(int i=7; i>=0; i--) + { + (*pfPAtabledBm)=SpiritRadioGetReg2dBm(lFBase,palevelvect[i]); + pfPAtabledBm++; + } + + /* Return the settled index */ + *pcPALevelMaxIndex = palevelvect[8]&0x07; + +} + + + + + + +/** +* @brief Sets a specific PA_LEVEL register, with a value given in dBm. +* @param cIndex PA_LEVEL to set. This parameter shall be in the range [0:7]. +* @param fPowerdBm PA value to write expressed in dBm . Be sure that this values is in the +* correct range [-PA_LOWER_LIMIT: PA_UPPER_LIMIT] dBm. +* @retval None. +* @note This function makes use of the @ref SpiritRadioGetdBm2Reg fcn to interpolate the +* power value. +*/ +void SpiritRadioSetPALeveldBm(uint8_t cIndex, float fPowerdBm) +{ + uint8_t address, paLevelValue; + + /* Check the parameters */ + s_assert_param(IS_PA_MAX_INDEX(cIndex)); + s_assert_param(IS_PAPOWER_DBM(fPowerdBm)); + + /* interpolate the power level */ + paLevelValue=SpiritRadioGetdBm2Reg(SpiritRadioGetFrequencyBase(),fPowerdBm); + + /* Sets the base address */ + address=PA_POWER8_BASE+7-cIndex; + + /* Configures the PA_LEVEL register */ + g_xStatus = SpiritSpiWriteRegisters(address, 1, &paLevelValue); + +} + + +/** +* @brief Returns a specific PA_LEVEL register, returning a value in dBm. +* @param cIndex PA_LEVEL to read. This parameter shall be in the range [0:7] +* @retval float Settled power level expressed in dBm. A value +* higher than PA_UPPER_LIMIT dBm implies no output power +* (output stage is in high impedance). +* @note This function makes use of the @ref SpiritRadioGetReg2dBm fcn to interpolate the +* power value. +*/ +float SpiritRadioGetPALeveldBm(uint8_t cIndex) +{ + uint8_t address, paLevelValue; + + /* Check the parameters */ + s_assert_param(IS_PA_MAX_INDEX(cIndex)); + + /* Sets the base address */ + address=PA_POWER8_BASE+7-cIndex; + + /* Reads the PA_LEVEL[cIndex] register */ + g_xStatus = SpiritSpiReadRegisters(address, 1, &paLevelValue); + + return SpiritRadioGetReg2dBm(SpiritRadioGetFrequencyBase(),paLevelValue); +} + + +/** +* @brief Configures the Power Amplifier Table and registers. +* @param cPALevelMaxIndex number of levels to set. This parameter shall be in the range [0:7]. +* @param cWidth step width expressed in terms of bit period units Tb/8. +* This parameter shall be in the range [1:4]. +* @param xCLoad one of the possible value of the enum type PALoadCapacitor. +* @arg LOAD_0_PF No additional PA load capacitor +* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor +* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor +* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor +* @param pcPAtable pointer to an array of PA values in the range [0: 90], where 0 implies no +* output power, 1 will be the maximum level and 90 the minimum one +* The first element shall be the lower level (PA_LEVEL[0]) value and the last element +* the higher level one (PA_LEVEL[paLevelMaxIndex]). +* @retval None. +*/ +void SpiritRadioSetPATable(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, uint8_t* pcPAtable) +{ + uint8_t palevel[9], address; + + /* Check the parameters */ + s_assert_param(IS_PA_MAX_INDEX(cPALevelMaxIndex)); + s_assert_param(IS_PA_STEP_WIDTH(cWidth)); + s_assert_param(IS_PA_LOAD_CAP(xCLoad)); + + /* Check the PA levels are in the range */ + for(int i=0; i<=cPALevelMaxIndex; i++) + { + s_assert_param(IS_PAPOWER(*pcPAtable)); + palevel[cPALevelMaxIndex-i]=*pcPAtable; + pcPAtable++; + } + + /* Sets the PA_POWER[0] register */ + palevel[cPALevelMaxIndex+1]=xCLoad|((cWidth-1)<<3)|cPALevelMaxIndex; + + /* Sets the base address */ + address=PA_POWER8_BASE+7-cPALevelMaxIndex; + + /* Configures the PA_POWER registers */ + g_xStatus = SpiritSpiWriteRegisters(address, cPALevelMaxIndex+2, palevel); + +} + + +/** +* @brief Returns the Power Amplifier Table and registers. +* @param pcPALevelMaxIndex pointer to the number of levels settled. +* This parameter shall be in the range [0:7]. +* @param pcPAtable pointer to an array of 8 elements containing the PA value. +* The first element will be the PA_LEVEL_0 and the last element +* will be PA_LEVEL_7. Any value equals to 0 implies that level has +* no output power (output stage is in high impedance). +* @retval None +*/ +void SpiritRadioGetPATable(uint8_t* pcPALevelMaxIndex, uint8_t* pcPAtable) +{ + uint8_t palevelvect[9]; + + /* Reads the PA_LEVEL_x registers and the PA_POWER_0 register */ + g_xStatus = SpiritSpiReadRegisters(PA_POWER8_BASE, 9, palevelvect); + + /* Fill the PAtable */ + for(int i=7; i>=0; i--) + { + *pcPAtable = palevelvect[i]; + pcPAtable++; + } + + /* Return the settled index */ + *pcPALevelMaxIndex = palevelvect[8]&0x07; + +} + + +/** +* @brief Sets a specific PA_LEVEL register. +* @param cIndex PA_LEVEL to set. This parameter shall be in the range [0:7]. +* @param cPower PA value to write in the register. Be sure that this values is in the +* correct range [0 : 90]. +* @retval None. +*/ +void SpiritRadioSetPALevel(uint8_t cIndex, uint8_t cPower) +{ + uint8_t address; + + /* Check the parameters */ + s_assert_param(IS_PA_MAX_INDEX(cIndex)); + s_assert_param(IS_PAPOWER(cPower)); + + /* Sets the base address */ + address=PA_POWER8_BASE+7-cIndex; + + /* Configures the PA_LEVEL register */ + g_xStatus = SpiritSpiWriteRegisters(address, 1, &cPower); + +} + + +/** +* @brief Returns a specific PA_LEVEL register. +* @param cIndex PA_LEVEL to read. This parameter shall be in the range [0:7]. +* @retval uint8_t PA_LEVEL value. A value equal to zero +* implies no output power (output stage is in high impedance). +*/ +uint8_t SpiritRadioGetPALevel(uint8_t cIndex) +{ + uint8_t address, tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PA_MAX_INDEX(cIndex)); + + /* Sets the base address */ + address=PA_POWER8_BASE+7-cIndex; + + /* Reads the PA_LEVEL[cIndex] register and return the value */ + g_xStatus = SpiritSpiReadRegisters(address, 1, &tempRegValue); + return tempRegValue; + +} + + +/** +* @brief Sets the output stage additional load capacitor bank. +* @param xCLoad one of the possible value of the enum type PALoadCapacitor. +* @arg LOAD_0_PF No additional PA load capacitor +* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor +* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor +* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor +* @retval None. +*/ +void SpiritRadioSetPACwc(PALoadCapacitor xCLoad) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PA_LOAD_CAP(xCLoad)); + + /* Reads the PA_POWER_0 register */ + SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + + /* Mask the CWC[1:0] field and write the new value */ + tempRegValue &= 0x3F; + tempRegValue |= xCLoad; + + /* Configures the PA_POWER_0 register */ + g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the output stage additional load capacitor bank. +* @param None. +* @retval PALoadCapacitor Output stage additional load capacitor bank. +* This parameter can be: +* @arg LOAD_0_PF No additional PA load capacitor +* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor +* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor +* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor +*/ +PALoadCapacitor SpiritRadioGetPACwc(void) +{ + uint8_t tempRegValue; + + /* Reads the PA_POWER_0 register */ + g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + + /* Mask the CWC[1:0] field and return the value*/ + return (PALoadCapacitor)(tempRegValue & 0xC0); + +} + + +/** +* @brief Sets a specific PA_LEVEL_MAX_INDEX. +* @param cIndex PA_LEVEL_MAX_INDEX to set. This parameter shall be in the range [0:7]. +* @retval None +*/ +void SpiritRadioSetPALevelMaxIndex(uint8_t cIndex) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PA_MAX_INDEX(cIndex)); + + /* Reads the PA_POWER_0 register */ + SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + + /* Mask the PA_LEVEL_MAX_INDEX[1:0] field and write the new value */ + tempRegValue &= 0xF8; + tempRegValue |= cIndex; + + /* Configures the PA_POWER_0 register */ + g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the actual PA_LEVEL_MAX_INDEX. +* @param None. +* @retval uint8_t Actual PA_LEVEL_MAX_INDEX. This parameter will be in the range [0:7]. +*/ +uint8_t SpiritRadioGetPALevelMaxIndex(void) +{ + uint8_t tempRegValue; + + /* Reads the PA_POWER_0 register */ + g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + + /* Mask the PA_LEVEL_MAX_INDEX[1:0] field and return the value */ + return (tempRegValue & 0x07); + +} + + +/** +* @brief Sets a specific PA_RAMP_STEP_WIDTH. +* @param cWidth step width expressed in terms of bit period units Tb/8. +* This parameter shall be in the range [1:4]. +* @retval None. +*/ +void SpiritRadioSetPAStepWidth(uint8_t cWidth) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_PA_STEP_WIDTH(cWidth)); + + /* Reads the PA_POWER_0 register */ + SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + + /* Mask the PA_RAMP_STEP_WIDTH[1:0] field and write the new value */ + tempRegValue &= 0xE7; + tempRegValue |= (cWidth-1)<<3; + + /* Configures the PA_POWER_0 register */ + g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the actual PA_RAMP_STEP_WIDTH. +* @param None. +* @retval uint8_t Step width value expressed in terms of bit period units Tb/8. +* This parameter will be in the range [1:4]. +*/ +uint8_t SpiritRadioGetPAStepWidth(void) +{ + uint8_t tempRegValue; + + /* Reads the PA_POWER_0 register */ + g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + + /* Mask the PA_RAMP_STEP_WIDTH[1:0] field and return the value */ + tempRegValue &= 0x18; + return ((tempRegValue>>3)+1); + +} + + +/** +* @brief Enables or Disables the Power Ramping. +* @param xNewState new state for power ramping. +* This parameter can be: S_ENABLE or S_DISABLE. +* @retval None. +*/ +void SpiritRadioPARamping(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PA_POWER_0 register and configure the PA_RAMP_ENABLE field */ + SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= PA_POWER0_PA_RAMP_MASK; + } + else + { + tempRegValue &= (~PA_POWER0_PA_RAMP_MASK); + } + + /* Sets the PA_POWER_0 register */ + g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); + +} + +/** +* @brief Returns the Power Ramping enable bit. +* @param xNewState new state for power ramping. +* This parameter can be: S_ENABLE or S_DISABLE. +* @retval None. +*/ +SpiritFunctionalState SpiritRadioGetPARamping(void) +{ + uint8_t tempRegValue; + + /* Reads the PA_POWER_0 register and configure the PA_RAMP_ENABLE field */ + g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); + + /* Mask and return data */ + return (SpiritFunctionalState)((tempRegValue>>5) & 0x01); + +} + + +/** +* @brief Enables or Disables the AFC. +* @param xNewState new state for AFC. +* This parameter can be: S_ENABLE or S_DISABLE. +* @retval None. +*/ +void SpiritRadioAFC(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the AFC_2 register and configure the AFC Enabled field */ + SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= AFC2_AFC_MASK; + } + else + { + tempRegValue &= (~AFC2_AFC_MASK); + } + + /* Sets the AFC_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Enables or Disables the AFC freeze on sync word detection. +* @param xNewState new state for AFC freeze on sync word detection. +* This parameter can be: S_ENABLE or S_DISABLE. +* @retval None. +*/ +void SpiritRadioAFCFreezeOnSync(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the AFC_2 register and configure the AFC Freeze on Sync field */ + SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= AFC2_AFC_FREEZE_ON_SYNC_MASK; + } + else + { + tempRegValue &= (~AFC2_AFC_FREEZE_ON_SYNC_MASK); + } + + /* Sets the AFC_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Sets the AFC working mode. +* @param xMode the AFC mode. This parameter can be one of the values defined in @ref AFCMode : +* @arg AFC_SLICER_CORRECTION AFC loop closed on slicer +* @arg AFC_2ND_IF_CORRECTION AFC loop closed on 2nd conversion stage +* @retval None. +*/ +void SpiritRadioSetAFCMode(AFCMode xMode) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_AFC_MODE(xMode)); + + /* Reads the AFC_2 register and configure the AFC Mode field */ + SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); + if(xMode == AFC_2ND_IF_CORRECTION) + { + tempRegValue |= AFC_2ND_IF_CORRECTION; + } + else + { + tempRegValue &= (~AFC_2ND_IF_CORRECTION); + } + + /* Sets the AFC_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AFC working mode. +* @param None. +* @retval AFCMode Settled AFC mode. This parameter will be one of the values defined in @ref AFCMode : +* @arg AFC_SLICER_CORRECTION AFC loop closed on slicer +* @arg AFC_2ND_IF_CORRECTION AFC loop closed on 2nd conversion stage +*/ +AFCMode SpiritRadioGetAFCMode(void) +{ + uint8_t tempRegValue; + + /* Reads the AFC_2 register */ + g_xStatus = SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); + + /* Mask the AFC Mode field and returns the value */ + return (AFCMode)(tempRegValue & 0x20); + +} + + +/** +* @brief Sets the AFC peak detector leakage. +* @param cLeakage the peak detector leakage. This parameter shall be in the range: +* [0:31]. +* @retval None. +*/ +void SpiritRadioSetAFCPDLeakage(uint8_t cLeakage) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_AFC_PD_LEAKAGE(cLeakage)); + + /* Reads the AFC_2 register and configure the AFC PD leakage field */ + SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); + tempRegValue &= 0xE0; + tempRegValue |= cLeakage; + + /* Sets the AFC_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AFC peak detector leakage. +* @param None. +* @retval uint8_t Peak detector leakage value. This parameter will be in the range: +* [0:31]. +*/ +uint8_t SpiritRadioGetAFCPDLeakage(void) +{ + uint8_t tempRegValue; + + /* Reads the AFC_2 register */ + g_xStatus = SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); + + /* Mask the AFC PD leakage field and return the value */ + return (tempRegValue & 0x1F); + +} + + +/** +* @brief Sets the length of the AFC fast period expressed as number of samples. +* @param cLength length of the fast period in number of samples. +* @retval None. +*/ +void SpiritRadioSetAFCFastPeriod(uint8_t cLength) +{ + /* Sets the AFC_1 register */ + g_xStatus = SpiritSpiWriteRegisters(AFC1_BASE, 1, &cLength); + +} + + +/** +* @brief Returns the AFC fast period expressed as number of samples. +* @param None. +* @retval uint8_t Length of the fast period in number of samples. +*/ +uint8_t SpiritRadioGetAFCFastPeriod(void) +{ + uint8_t tempRegValue; + + /* Reads the AFC 1 register and return the value */ + g_xStatus = SpiritSpiReadRegisters(AFC1_BASE, 1, &tempRegValue); + + return tempRegValue; + +} + + +/** +* @brief Sets the AFC loop gain in fast mode. +* @param cGain AFC loop gain in fast mode. This parameter shall be in the range: +* [0:15]. +* @retval None. +*/ +void SpiritRadioSetAFCFastGain(uint8_t cGain) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_AFC_FAST_GAIN(cGain)); + + /* Reads the AFC_0 register and configure the AFC Fast Gain field */ + SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); + tempRegValue &= 0x0F; + tempRegValue |= cGain<<4; + + /* Sets the AFC_0 register */ + g_xStatus = SpiritSpiWriteRegisters(AFC0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AFC loop gain in fast mode. +* @param None. +* @retval uint8_t AFC loop gain in fast mode. This parameter will be in the range: +* [0:15]. +*/ +uint8_t SpiritRadioGetAFCFastGain(void) +{ + uint8_t tempRegValue; + + /* Reads the AFC_0 register, mask the AFC Fast Gain field and return the value */ + g_xStatus = SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); + + return ((tempRegValue & 0xF0)>>4); + +} + + +/** +* @brief Sets the AFC loop gain in slow mode. +* @param cGain AFC loop gain in slow mode. This parameter shall be in the range: +* [0:15]. +* @retval None. +*/ +void SpiritRadioSetAFCSlowGain(uint8_t cGain) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_AFC_SLOW_GAIN(cGain)); + + /* Reads the AFC_0 register and configure the AFC Slow Gain field */ + SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); + tempRegValue &= 0xF0; + tempRegValue |= cGain; + + /* Sets the AFC_0 register */ + g_xStatus = SpiritSpiWriteRegisters(AFC0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AFC loop gain in slow mode. +* @param None. +* @retval uint8_t AFC loop gain in slow mode. This parameter will be in the range: +* [0:15]. +*/ +uint8_t SpiritRadioGetAFCSlowGain(void) +{ + uint8_t tempRegValue; + + /* Reads the AFC_0 register, mask the AFC Slow Gain field and return the value */ + g_xStatus = SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); + + return (tempRegValue & 0x0F); + +} + + +/** +* @brief Returns the AFC correction from the corresponding register. +* @param None. +* @retval int8_t AFC correction, read from the corresponding register. +* This parameter will be in the range [-128:127]. +*/ +int8_t SpiritRadioGetAFCCorrectionReg(void) +{ + uint8_t tempRegValue; + + /* Reads the AFC_CORR register, cast the read value as signed char and return it */ + g_xStatus = SpiritSpiReadRegisters(AFC_CORR_BASE, 1, &tempRegValue); + + return (int8_t)tempRegValue; + +} + + +/** +* @brief Returns the AFC correction expressed in Hz. +* @param None. +* @retval int32_t AFC correction expressed in Hz +* according to the following formula:
    +*
  • Fafc[Hz]= (Fdig/(12*2^10))*AFC_CORR where
    • +*
  • AFC_CORR is the value read in the AFC_CORR register
+*/ +int32_t SpiritRadioGetAFCCorrectionHz(void) +{ + int8_t correction; + uint32_t xtal = s_lXtalFrequency; + + /* Reads the AFC correction register */ + correction = SpiritRadioGetAFCCorrectionReg(); + + if(xtal>DOUBLE_XTAL_THR) + { + xtal /= 2; + } + + /* Calculates and return the Frequency Correction */ + return (int32_t)(xtal/(12*pow(2,10))*correction); + +} + + +/** +* @brief Enables or Disables the AGC. +* @param xNewState new state for AGC. +* This parameter can be: S_ENABLE or S_DISABLE +* @retval None. +*/ +void SpiritRadioAGC(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the AGCCTRL_0 register and configure the AGC Enabled field */ + SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= AGCCTRL0_AGC_MASK; + } + else + { + tempRegValue &= (~AGCCTRL0_AGC_MASK); + } + + /* Sets the AGCCTRL_0 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Sets the AGC working mode. +* @param xMode the AGC mode. This parameter can be one of the values defined in @ref AGCMode : +* @arg AGC_LINEAR_MODE AGC works in linear mode +* @arg AGC_BINARY_MODE AGC works in binary mode +* @retval None. +*/ +void SpiritRadioSetAGCMode(AGCMode xMode) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_AGC_MODE(xMode)); + + /* Reads the AGCCTRL_0 register and configure the AGC Mode field */ + SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + if(xMode == AGC_BINARY_MODE) + { + tempRegValue |= AGC_BINARY_MODE; + } + else + { + tempRegValue &= (~AGC_BINARY_MODE); + } + + /* Sets the AGCCTRL_0 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AGC working mode. +* @param None. +* @retval AGCMode Settled AGC mode. This parameter can be one of the values defined in @ref AGCMode : +* @arg AGC_LINEAR_MODE AGC works in linear mode +* @arg AGC_BINARY_MODE AGC works in binary mode +*/ +AGCMode SpiritRadioGetAGCMode(void) +{ + uint8_t tempRegValue; + + /* Reads the AGCCTRL_0 register, mask the AGC Mode field and return the value */ + g_xStatus = SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + + return (AGCMode)(tempRegValue & 0x40); + +} + + +/** +* @brief Enables or Disables the AGC freeze on steady state. +* @param xNewState new state for AGC freeze on steady state. +* This parameter can be: S_ENABLE or S_DISABLE. +* @retval None. +*/ +void SpiritRadioAGCFreezeOnSteady(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the AGCCTRL_2 register and configure the AGC Freeze On Steady field */ + SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= AGCCTRL2_FREEZE_ON_STEADY_MASK; + } + else + { + tempRegValue &= (~AGCCTRL2_FREEZE_ON_STEADY_MASK); + } + + /* Sets the AGCCTRL_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Enable or Disable the AGC freeze on sync detection. +* @param xNewState new state for AGC freeze on sync detection. +* This parameter can be: S_ENABLE or S_DISABLE. +* @retval None. +*/ +void SpiritRadioAGCFreezeOnSync(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the AGCCTRL_2 register and configure the AGC Freeze On Sync field */ + SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= AGCCTRL2_FREEZE_ON_SYNC_MASK; + } + else + { + tempRegValue &= (~AGCCTRL2_FREEZE_ON_SYNC_MASK); + } + + /* Sets the AGCCTRL_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Enable or Disable the AGC to start with max attenuation. +* @param xNewState new state for AGC start with max attenuation mode. +* This parameter can be: S_ENABLE or S_DISABLE. +* @retval None. +*/ +void SpiritRadioAGCStartMaxAttenuation(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue = 0x00; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the AGCCTRL_2 register and configure the AGC Start Max Attenuation field */ + SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + if(xNewState == S_ENABLE) + { + tempRegValue |= AGCCTRL2_START_MAX_ATTENUATION_MASK; + } + else + { + tempRegValue &= (~AGCCTRL2_START_MAX_ATTENUATION_MASK); + } + + /* Sets the AGCCTRL_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Sets the AGC measure time. +* @param nTime AGC measure time expressed in us. This parameter shall be in the range [0, 393216/F_Xo]. +* @retval None. +*/ +void SpiritRadioSetAGCMeasureTimeUs(uint16_t nTime) +{ + uint8_t tempRegValue, measure; + + /* Check the parameter */ + s_assert_param(IS_AGC_MEASURE_TIME_US(nTime,s_lXtalFrequency)); + + /* Reads the AGCCTRL_2 register */ + SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + + /* Calculates the measure time value to write in the register */ + measure = (uint8_t)lroundf(log2((float)nTime/1e6 * s_lXtalFrequency/12)); + (measure>15) ? (measure=15):(measure); + + /* Mask the MEAS_TIME field and write the new value */ + tempRegValue &= 0xF0; + tempRegValue |= measure; + + /* Sets the AGCCTRL_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AGC measure time. +* @param None. +* @retval uint16_t AGC measure time expressed in us. This parameter will be in the range [0, 393216/F_Xo]. +*/ +uint16_t SpiritRadioGetAGCMeasureTimeUs(void) +{ + uint8_t measure; + + /* Reads the AGCCTRL_2 register */ + g_xStatus = SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &measure); + + /* Mask the MEAS_TIME field */ + measure &= 0x0F; + + /* Calculates the measure time value to write in the register */ + return (uint16_t)((12.0/s_lXtalFrequency)*(float)pow(2,measure)*1e6); + +} + + +/** +* @brief Sets the AGC measure time. +* @param cTime AGC measure time to write in the MEAS_TIME field of AGCCTRL_2 register. +* This parameter shall be in the range [0:15]. +* @retval None. +*/ +void SpiritRadioSetAGCMeasureTime(uint8_t cTime) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_AGC_MEASURE_TIME(cTime)); + + /* Reads the AGCCTRL_2 register */ + SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + + /* Mask the MEAS_TIME field and write the new value */ + tempRegValue &= 0xF0; + tempRegValue |= cTime; + + /* Sets the AGCCTRL_2 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AGC measure time. +* @param None. +* @retval uint8_t AGC measure time read from the MEAS_TIME field of AGCCTRL_2 register. +* This parameter will be in the range [0:15]. +*/ +uint8_t SpiritRadioGetAGCMeasureTime(void) +{ + uint8_t tempRegValue; + + /* Reads the AGCCTRL_2 register, mask the MEAS_TIME field and return the value */ + g_xStatus = SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); + + return (tempRegValue & 0x0F); + +} + + +/** +* @brief Sets the AGC hold time. +* @param cTime AGC hold time expressed in us. This parameter shall be in the range[0, 756/F_Xo]. +* @retval None. +*/ +void SpiritRadioSetAGCHoldTimeUs(uint8_t cTime) +{ + uint8_t tempRegValue, hold; + + /* Check the parameter */ + s_assert_param(IS_AGC_HOLD_TIME_US(cTime,s_lXtalFrequency)); + + /* Reads the AGCCTRL_0 register */ + SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + + /* Calculates the hold time value to write in the register */ + hold = (uint8_t)lroundf(((float)cTime/1e6 * s_lXtalFrequency)/12); + (hold>63) ? (hold=63):(hold); + + /* Mask the HOLD_TIME field and write the new value */ + tempRegValue &= 0xC0; + tempRegValue |= hold; + + /* Sets the AGCCTRL_0 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AGC hold time. +* @param None. +* @retval uint8_t AGC hold time expressed in us. This parameter will be in the range: +* [0, 756/F_Xo]. +*/ +uint8_t SpiritRadioGetAGCHoldTimeUs(void) +{ + uint8_t tempRegValue; + + /* Reads the AGCCTRL_0 register */ + g_xStatus = SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + + /* Mask the HOLD_TIME field */ + tempRegValue &= 0x3F; + + /* Calculates the hold time value and return it */ + return (uint8_t)lroundf ((12.0/s_lXtalFrequency)*(tempRegValue*1e6)); + +} + + +/** +* @brief Sets the AGC hold time. +* @param cTime AGC hold time to write in the HOLD_TIME field of AGCCTRL_0 register. +* This parameter shall be in the range [0:63]. +* @retval None. +*/ +void SpiritRadioSetAGCHoldTime(uint8_t cTime) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_AGC_HOLD_TIME(cTime)); + + /* Reads the AGCCTRL_0 register */ + SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + + /* Mask the HOLD_TIME field and write the new value */ + tempRegValue &= 0xC0; + tempRegValue |= cTime; + + /* Sets the AGCCTRL_0 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AGC hold time. +* @param None. +* @retval uint8_t AGC hold time read from the HOLD_TIME field of AGCCTRL_0 register. +* This parameter will be in the range [0:63]. +*/ +uint8_t SpiritRadioGetAGCHoldTime(void) +{ + uint8_t tempRegValue; + + /* Reads the AGCCTRL_0 register, mask the MEAS_TIME field and return the value */ + g_xStatus = SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); + + return (tempRegValue & 0x3F); + +} + + +/** +* @brief Sets the AGC high threshold. +* @param cHighThreshold AGC high threshold to write in the THRESHOLD_HIGH field of AGCCTRL_1 register. +* This parameter shall be in the range [0:15]. +* @retval None. +*/ +void SpiritRadioSetAGCHighThreshold(uint8_t cHighThreshold) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_AGC_THRESHOLD(cHighThreshold)); + + /* Reads the AGCCTRL_1 register */ + SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); + + /* Mask the THRESHOLD_HIGH field and write the new value */ + tempRegValue &= 0x0F; + tempRegValue |= cHighThreshold<<4; + + /* Sets the AGCCTRL_1 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL1_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AGC high threshold. +* @param None. +* @retval uint8_t AGC high threshold read from the THRESHOLD_HIGH field of AGCCTRL_1 register. +* This parameter will be in the range [0:15]. +*/ +uint8_t SpiritRadioGetAGCHighThreshold(void) +{ + uint8_t tempRegValue; + + /* Reads the AGCCTRL_1 register, mask the THRESHOLD_HIGH field and return the value */ + g_xStatus = SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); + + return ((tempRegValue & 0xF0)>>4); + +} + + +/** +* @brief Sets the AGC low threshold. +* @param cLowThreshold AGC low threshold to write in the THRESHOLD_LOW field of AGCCTRL_1 register. +* This parameter shall be in the range [0:15]. +* @retval None. +*/ +void SpiritRadioSetAGCLowThreshold(uint8_t cLowThreshold) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_AGC_THRESHOLD(cLowThreshold)); + + /* Reads the AGCCTRL_1 register */ + SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); + + /* Mask the THRESHOLD_LOW field and write the new value */ + tempRegValue &= 0xF0; + tempRegValue |= cLowThreshold; + + /* Sets the AGCCTRL_1 register */ + g_xStatus = SpiritSpiWriteRegisters(AGCCTRL1_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the AGC low threshold. +* @param None. +* @retval uint8_t AGC low threshold read from the THRESHOLD_LOW field of AGCCTRL_1 register. +* This parameter will be in the range [0:15]. +*/ +uint8_t SpiritRadioGetAGCLowThreshold(void) +{ + uint8_t tempRegValue; + + /* Reads the AGCCTRL_1 register, mask the THRESHOLD_LOW field and return the value */ + g_xStatus = SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); + + return (tempRegValue & 0x0F); + +} + + +/** +* @brief Sets the clock recovery algorithm. +* @param xMode the Clock Recovery mode. This parameter can be one of the values defined in @ref ClkRecMode : +* @arg CLK_REC_PLL PLL alogrithm for clock recovery +* @arg CLK_REC_DLL DLL alogrithm for clock recovery +* @retval None. +*/ +void SpiritRadioSetClkRecMode(ClkRecMode xMode) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_CLK_REC_MODE(xMode)); + + /* Reads the FDEV_0 register */ + SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); + + /* Mask the CLOCK_REC_ALGO_SEL field and write the new value */ + tempRegValue &= 0xF7; + tempRegValue |= (uint8_t)xMode; + + /* Sets the FDEV_0 register */ + g_xStatus = SpiritSpiWriteRegisters(FDEV0_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the Clock Recovery working mode. +* @param None. +* @retval ClkRecMode Clock Recovery mode. This parameter can be one of the values defined in @ref ClkRecMode : +* @arg CLK_REC_PLL PLL alogrithm for clock recovery +* @arg CLK_REC_DLL DLL alogrithm for clock recovery +*/ +ClkRecMode SpiritRadioGetClkRecMode(void) +{ + uint8_t tempRegValue; + + /* Reads the FDEV_0 register, mask the CLOCK_REC_ALGO_SEL field and return the value */ + g_xStatus = SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); + + return (ClkRecMode)(tempRegValue & 0x08); + +} + + +/** +* @brief Sets the clock recovery proportional gain. +* @param cPGain the Clock Recovery proportional gain to write in the CLK_REC_P_GAIN field of CLOCKREC register. +* It represents is log2 value of the clock recovery proportional gain. +* This parameter shall be in the range [0:7]. +* @retval None. +*/ +void SpiritRadioSetClkRecPGain(uint8_t cPGain) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_CLK_REC_P_GAIN(cPGain)); + + /* Reads the CLOCKREC register */ + SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); + + /* Mask the CLK_REC_P_GAIN field and write the new value */ + tempRegValue &= 0x1F; + tempRegValue |= (cPGain<<5); + + /* Sets the CLOCKREC register */ + g_xStatus = SpiritSpiWriteRegisters(CLOCKREC_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the log2 of the clock recovery proportional gain. +* @param None. +* @retval uint8_t Clock Recovery proportional gain read from the CLK_REC_P_GAIN field of CLOCKREC register. +* This parameter will be in the range [0:7]. +*/ +uint8_t SpiritRadioGetClkRecPGain(void) +{ + uint8_t tempRegValue; + + /* Reads the CLOCKREC register, mask the CLK_REC_P_GAIN field and return the value */ + g_xStatus = SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); + + return ((tempRegValue & 0xEF)>>5); + +} + + +/** +* @brief Sets the clock recovery integral gain. +* @param cIGain the Clock Recovery integral gain to write in the CLK_REC_I_GAIN field of CLOCKREC register. +* This parameter shall be in the range [0:15]. +* @retval None. +*/ +void SpiritRadioSetClkRecIGain(uint8_t cIGain) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_CLK_REC_I_GAIN(cIGain)); + + /* Reads the CLOCKREC register */ + SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); + + /* Mask the CLK_REC_P_GAIN field and write the new value */ + tempRegValue &= 0xF0; + tempRegValue |= cIGain; + + /* Sets the CLOCKREC register */ + g_xStatus = SpiritSpiWriteRegisters(CLOCKREC_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the clock recovery integral gain. +* @param None. +* @retval uint8_t Clock Recovery integral gain read from the +* CLK_REC_I_GAIN field of CLOCKREC register. +* This parameter will be in the range [0:15]. +*/ +uint8_t SpiritRadioGetClkRecIGain(void) +{ + uint8_t tempRegValue; + + /* Reads the CLOCKREC register, mask the CLK_REC_I_GAIN field and return the value */ + g_xStatus = SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); + + return (tempRegValue & 0x0F); + +} + + +/** +* @brief Sets the postfilter length for clock recovery algorithm. +* @param xLength the postfilter length in symbols. This parameter can be one of the values defined in @ref PstFltLength : +* @arg PSTFLT_LENGTH_8 Postfilter length is 8 symbols +* @arg PSTFLT_LENGTH_16 Postfilter length is 16 symbols +* @retval None. +*/ +void SpiritRadioSetClkRecPstFltLength(PstFltLength xLength) +{ + uint8_t tempRegValue; + + /* Check the parameter */ + s_assert_param(IS_PST_FLT_LENGTH(xLength)); + + /* Reads the CLOCKREC register */ + SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); + + /* Mask the PSTFLT_LEN field and write the new value */ + tempRegValue &= 0xEF; + tempRegValue |= (uint8_t)xLength; + + /* Sets the CLOCKREC register */ + g_xStatus = SpiritSpiWriteRegisters(CLOCKREC_BASE, 1, &tempRegValue); + +} + + +/** +* @brief Returns the postfilter length for clock recovery algorithm. +* @param None. +* @retval PstFltLength Postfilter length in symbols. This parameter can be one of the values defined in @ref PstFltLength : +* @arg PSTFLT_LENGTH_8 Postfilter length is 8 symbols +* @arg PSTFLT_LENGTH_16 Postfilter length is 16 symbols +*/ +PstFltLength SpiritRadioGetClkRecPstFltLength(void) +{ + uint8_t tempRegValue; + + /* Reads the CLOCKREC register, mask the PSTFLT_LEN field and return the value */ + g_xStatus = SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); + + return (PstFltLength)(tempRegValue & 0x10); + +} + + +/** +* @brief Enables or Disables the received data blanking when the CS is under the threshold. +* @param xNewState new state of this mode. +* This parameter can be: S_ENABLE or S_DISABLE . +* @retval None. +*/ +void SpiritRadioCsBlanking(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the ANT_SELECT_CONF_BASE and mask the CS_BLANKING BIT field */ + SpiritSpiReadRegisters(ANT_SELECT_CONF_BASE, 1, &tempRegValue); + + if(xNewState == S_ENABLE) + { + tempRegValue |= ANT_SELECT_CS_BLANKING_MASK; + } + else + { + tempRegValue &= (~ANT_SELECT_CS_BLANKING_MASK); + } + + /* Writes the new value in the ANT_SELECT_CONF register */ + g_xStatus = SpiritSpiWriteRegisters(ANT_SELECT_CONF_BASE, 1, &tempRegValue); + + +} + +/** +* @brief Enables or Disables the persistent RX mode. +* @param xNewState new state of this mode. +* This parameter can be: S_ENABLE or S_DISABLE . +* @retval None. +*/ +void SpiritRadioPersistenRx(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the PROTOCOL0_BASE and mask the PROTOCOL0_PERS_RX_MASK bitfield */ + SpiritSpiReadRegisters(PROTOCOL0_BASE, 1, &tempRegValue); + + if(xNewState == S_ENABLE) + { + tempRegValue |= PROTOCOL0_PERS_RX_MASK; + } + else + { + tempRegValue &= (~PROTOCOL0_PERS_RX_MASK); + } + + /* Writes the new value in the PROTOCOL0_BASE register */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL0_BASE, 1, &tempRegValue); + +} + +/** +* @brief Enables or Disables the synthesizer reference divider. +* @param xNewState new state for synthesizer reference divider. +* This parameter can be: S_ENABLE or S_DISABLE . +* @retval None. +*/ +void SpiritRadioSetRefDiv(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the SYNTH_CONFIG1_BASE and mask the REFDIV bit field */ + SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + + if(xNewState == S_ENABLE) + { + tempRegValue |= 0x80; + } + else + { + tempRegValue &= 0x7F; + } + + /* Writes the new value in the SYNTH_CONFIG1_BASE register */ + g_xStatus = SpiritSpiWriteRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + +} + +/** +* @brief Get the the synthesizer reference divider state. +* @param void. +* @retval None. +*/ +SpiritFunctionalState SpiritRadioGetRefDiv(void) +{ + uint8_t tempRegValue; + + g_xStatus = SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); + + if(((tempRegValue>>7)&0x1)) + { + return S_ENABLE; + } + else + { + return S_DISABLE; + } + +} + +/** +* @brief Enables or Disables the synthesizer reference divider. +* @param xNewState new state for synthesizer reference divider. +* This parameter can be: S_ENABLE or S_DISABLE . +* @retval None. +*/ +void SpiritRadioSetDigDiv(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Check the parameters */ + s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); + + /* Reads the XO_RCO_TEST_BASE and mask the PD_CLKDIV bit field */ + SpiritSpiReadRegisters(XO_RCO_TEST_BASE, 1, &tempRegValue); + + if(xNewState == S_ENABLE) + { + tempRegValue &= 0xf7; + } + else + { + + tempRegValue |= 0x08; + } + + /* Writes the new value in the XO_RCO_TEST_BASE register */ + g_xStatus = SpiritSpiWriteRegisters(XO_RCO_TEST_BASE, 1, &tempRegValue); + +} + +/** +* @brief Get the the synthesizer reference divider state. +* @param void. +* @retval None. +*/ +SpiritFunctionalState SpiritRadioGetDigDiv(void) +{ + uint8_t tempRegValue; + + g_xStatus = SpiritSpiReadRegisters(XO_RCO_TEST_BASE, 1, &tempRegValue); + + if(((tempRegValue>>3)&0x1)) + { + return S_DISABLE; + } + else + { + return S_ENABLE; + } + +} + +/** +* @brief Returns the XTAL frequency. +* @param void. +* @retval uint32_t XTAL frequency. +*/ +uint32_t SpiritRadioGetXtalFrequency(void) +{ + return s_lXtalFrequency; +} + +/** +* @brief Sets the XTAL frequency. +* @param uint32_t XTAL frequency. +* @retval void. +*/ +void SpiritRadioSetXtalFrequency(uint32_t lXtalFrequency) +{ + s_lXtalFrequency = lXtalFrequency; +} + +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ + diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Timer.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Timer.c new file mode 100644 index 000000000..b51f2466d --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Timer.c @@ -0,0 +1,700 @@ +/** + ****************************************************************************** + * @file SPIRIT_Timer.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief Configuration and management of SPIRIT timers. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Timer.h" +#include "SPIRIT_Radio.h" +#include "MCU_Interface.h" + + + + +/** + * @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** + * @addtogroup SPIRIT_Timer + * @{ + */ + + +/** + * @defgroup Timer_Private_TypesDefinitions Timer Private Types Definitions + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Timer_Private_Defines Timer Private Defines + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Timer_Private_Macros Timer Private Macros + * @{ + */ + + +/** + *@} + */ + + +/** + * @defgroup Timer_Private_Variables Timer Private Variables + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Timer_Private_FunctionPrototypes Timer Private Function Prototypes + * @{ + */ + +/** + *@} + */ + + +/** + * @defgroup Timer_Private_Functions Timer Private Functions + * @{ + */ + +/** + * @brief Enables or Disables the LDCR mode. + * @param xNewState new state for LDCR mode. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritTimerLdcrMode(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + + /* Mask the read value to enable or disable the LDC mode */ + if(xNewState==S_ENABLE) + { + tempRegValue |= PROTOCOL2_LDC_MODE_MASK; + } + else + { + tempRegValue &= ~PROTOCOL2_LDC_MODE_MASK; + } + + /* Writes the register to Enable or Disable the LDCR mode */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Enables or Disables the LDCR timer reloading with the value stored in the LDCR_RELOAD registers. + * @param xNewState new state for LDCR reloading. + * This parameter can be: S_ENABLE or S_DISABLE. + * @retval None. + */ +void SpiritTimerLdcrAutoReload(SpiritFunctionalState xNewState) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + /* Mask te read value to enable or disable the reload on sync mode */ + if(xNewState==S_ENABLE) + { + tempRegValue |= PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK; + } + else + { + tempRegValue &= ~PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK; + } + + /* Writes the register to Enable or Disable the Auto Reload */ + g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + +} + + +/** + * @brief Returns the LDCR timer reload bit. + * @param None. + * @retval SpiritFunctionalState: value of the reload bit. + */ +SpiritFunctionalState SpiritTimerLdcrGetAutoReload(void) +{ + uint8_t tempRegValue; + + /* Reads the register value */ + g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); + + return (SpiritFunctionalState)(tempRegValue & 0x80); + +} + +/** + * @brief Sets the RX timeout timer initialization registers with the values of COUNTER and PRESCALER according to the formula: Trx=PRESCALER*COUNTER*Tck. + * Remember that it is possible to have infinite RX_Timeout writing 0 in the RX_Timeout_Counter and/or RX_Timeout_Prescaler registers. + * @param cCounter value for the timer counter. + * This parameter must be an uint8_t. + * @param cPrescaler value for the timer prescaler. + * This parameter must be an uint8_t. + * @retval None. + */ +void SpiritTimerSetRxTimeout(uint8_t cCounter , uint8_t cPrescaler) +{ + uint8_t tempRegValue[2]={cPrescaler,cCounter}; + + /* Writes the prescaler and counter value for RX timeout in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 2, tempRegValue); + +} + + +/** + * @brief Sets the RX timeout timer counter and prescaler from the desired value in ms. it is possible to fix the RX_Timeout to + * a minimum value of 50.417us to a maximum value of about 3.28 s. + * @param fDesiredMsec desired timer value. + * This parameter must be a float. + * @retval None + */ + +void SpiritTimerSetRxTimeoutMs(float fDesiredMsec) +{ + uint8_t tempRegValue[2]; + + /* Computes the counter and prescaler value */ + SpiritTimerComputeRxTimeoutValues(fDesiredMsec , &tempRegValue[1] , &tempRegValue[0]); + + /* Writes the prescaler and counter value for RX timeout in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 2, tempRegValue); + +} + + +/** + * @brief Sets the RX timeout timer counter. If it is equal to 0 the timeout is infinite. + * @param cCounter value for the timer counter. + * This parameter must be an uint8_t. + * @retval None. + */ +void SpiritTimerSetRxTimeoutCounter(uint8_t cCounter) +{ + /* Writes the counter value for RX timeout in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS4_RX_TIMEOUT_COUNTER_BASE, 1, &cCounter); + +} + + +/** + * @brief Sets the RX timeout timer prescaler. If it is equal to 0 the timeout is infinite. + * @param cPrescaler value for the timer prescaler. + * This parameter must be an uint8_t. + * @retval None + */ +void SpiritTimerSetRxTimeoutPrescaler(uint8_t cPrescaler) +{ + /* Writes the prescaler value for RX timeout in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 1, &cPrescaler); + +} + + +/** + * @brief Returns the RX timeout timer. + * @param pfTimeoutMsec pointer to the variable in which the timeout expressed in milliseconds has to be stored. + * If the returned value is 0, it means that the RX_Timeout is infinite. + * This parameter must be a float*. + * @param pcCounter pointer to the variable in which the timer counter has to be stored. + * This parameter must be an uint8_t*. + * @param pcPrescaler pointer to the variable in which the timer prescaler has to be stored. + * This parameter must be an uint8_t*. + * @retval None. + */ +void SpiritTimerGetRxTimeout(float* pfTimeoutMsec, uint8_t* pcCounter , uint8_t* pcPrescaler) +{ + uint8_t tempRegValue[2]; + + /* Reads the RX timeout registers value */ + g_xStatus = SpiritSpiReadRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 2, tempRegValue); + + /* Returns values */ + (*pcPrescaler) = tempRegValue[0]; + (*pcCounter) = tempRegValue[1]; + + float nXtalFrequency = (float)SpiritRadioGetXtalFrequency(); + if(nXtalFrequency>DOUBLE_XTAL_THR) { + nXtalFrequency /= 2.0; + } + nXtalFrequency /= 1000.0; + *pfTimeoutMsec = (float)((tempRegValue[0]+1)*tempRegValue[1]*(1210.0/nXtalFrequency)); + + +} + + +/** + * @brief Sets the LDCR wake up timer initialization registers with the values of + * COUNTER and PRESCALER according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where + * Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us (PRESCALER and + * COUNTER equals to 0) and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals + * to 255). + * @param cCounter value for the timer counter. + * This parameter must be an uint8_t. + * @param cPrescaler value for the timer prescaler. + * This parameter must be an uint8_t. + * @retval None. + */ +void SpiritTimerSetWakeUpTimer(uint8_t cCounter , uint8_t cPrescaler) +{ + uint8_t tempRegValue[2]={cPrescaler,cCounter}; + + /* Writes the counter and prescaler value of wake-up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS3_LDC_PRESCALER_BASE, 2, tempRegValue); + +} + + +/** + * @brief Sets the LDCR wake up timer counter and prescaler from the desired value in ms, + * according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. + * The minimum vale of the wakeup timeout is 28.818us (PRESCALER and COUNTER equals to 0) + * and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals to 255). + * @param fDesiredMsec desired timer value. + * This parameter must be a float. + * @retval None. + */ +void SpiritTimerSetWakeUpTimerMs(float fDesiredMsec) +{ + uint8_t tempRegValue[2]; + + /* Computes counter and prescaler */ + SpiritTimerComputeWakeUpValues(fDesiredMsec , &tempRegValue[1] , &tempRegValue[0]); + + /* Writes the counter and prescaler value of wake-up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS3_LDC_PRESCALER_BASE, 2, tempRegValue); + +} + + +/** + * @brief Sets the LDCR wake up timer counter. Remember that this value is incresead by one in the Twu calculation. + * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us + * @param cCounter value for the timer counter. + * This parameter must be an uint8_t. + * @retval None. + */ +void SpiritTimerSetWakeUpTimerCounter(uint8_t cCounter) +{ + /* Writes the counter value for Wake_Up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS2_LDC_COUNTER_BASE, 1, &cCounter); + +} + + +/** + * @brief Sets the LDCR wake up timer prescaler. Remember that this value is incresead by one in the Twu calculation. + * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us + * @param cPrescaler value for the timer prescaler. + * This parameter must be an uint8_t. + * @retval None. + */ +void SpiritTimerSetWakeUpTimerPrescaler(uint8_t cPrescaler) +{ + /* Writes the prescaler value for Wake_Up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS3_LDC_PRESCALER_BASE, 1, &cPrescaler); + +} + + +/** + * @brief Returns the LDCR wake up timer, according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. + * @param pfWakeUpMsec pointer to the variable in which the wake-up time expressed in milliseconds has to be stored. + * This parameter must be a float*. + * @param pcCounter pointer to the variable in which the timer counter has to be stored. + * This parameter must be an uint8_t*. + * @param pcPrescaler pointer to the variable in which the timer prescaler has to be stored. + * This parameter must be an uint8_t*. + * @retval None. + */ +void SpiritTimerGetWakeUpTimer(float* pfWakeUpMsec, uint8_t* pcCounter , uint8_t* pcPrescaler) +{ + uint8_t tempRegValue[2]; + uint32_t xtal=SpiritRadioGetXtalFrequency(); + float rco_freq; + + rco_freq=(float)SpiritTimerGetRcoFrequency(); + + /* Reads the Wake_Up timer registers value */ + g_xStatus = SpiritSpiReadRegisters(TIMERS3_LDC_PRESCALER_BASE, 2, tempRegValue); + + /* Returns values */ + (*pcPrescaler)=tempRegValue[0]; + (*pcCounter)=tempRegValue[1]; + *pfWakeUpMsec = (float)((((*pcPrescaler)+1)*((*pcCounter)+1)*(1000.0/rco_freq))); + +} + + +/** + * @brief Sets the LDCR wake up timer reloading registers with the values of + * COUNTER and PRESCALER according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where + * Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us (PRESCALER and + * COUNTER equals to 0) and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals + * to 255). + * @param cCounter reload value for the timer counter. + * This parameter must be an uint8_t. + * @param cPrescaler reload value for the timer prescaler. + * This parameter must be an uint8_t. + * @retval None. + */ +void SpiritTimerSetWakeUpTimerReload(uint8_t cCounter , uint8_t cPrescaler) +{ + uint8_t tempRegValue[2]={cPrescaler,cCounter}; + + /* Writes the counter and prescaler value of reload wake-up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 2, tempRegValue); + +} + + +/** + * @brief Sets the LDCR wake up reload timer counter and prescaler from the desired value in ms, + * according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. + * The minimum vale of the wakeup timeout is 28.818us (PRESCALER and COUNTER equals to 0) + * and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals to 255). + * @param fDesiredMsec desired timer value. + * This parameter must be a float. + * @retval None. + */ +void SpiritTimerSetWakeUpTimerReloadMs(float fDesiredMsec) +{ + uint8_t tempRegValue[2]; + + /* Computes counter and prescaler */ + SpiritTimerComputeWakeUpValues(fDesiredMsec , &tempRegValue[1] , &tempRegValue[0]); + + /* Writes the counter and prescaler value of reload wake-up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 2, tempRegValue); + +} + + +/** + * @brief Sets the LDCR wake up timer reload counter. Remember that this value is incresead by one in the Twu calculation. + * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us + * @param cCounter value for the timer counter. + * This parameter must be an uint8_t. + * @retval None + */ +void SpiritTimerSetWakeUpTimerReloadCounter(uint8_t cCounter) +{ + /* Writes the counter value for reload Wake_Up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS0_LDC_RELOAD_COUNTER_BASE, 1, &cCounter); + +} + + +/** + * @brief Sets the LDCR wake up timer reload prescaler. Remember that this value is incresead by one in the Twu calculation. + * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us + * @param cPrescaler value for the timer prescaler. + * This parameter must be an uint8_t. + * @retval None + */ +void SpiritTimerSetWakeUpTimerReloadPrescaler(uint8_t cPrescaler) +{ + /* Writes the prescaler value for reload Wake_Up timer in the corresponding register */ + g_xStatus = SpiritSpiWriteRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 1, &cPrescaler); + +} + + +/** + * @brief Returns the LDCR wake up reload timer, according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. + * @param pfWakeUpReloadMsec pointer to the variable in which the wake-up reload time expressed in milliseconds has to be stored. + * This parameter must be a float*. + * @param pcCounter pointer to the variable in which the timer counter has to be stored. + * This parameter must be an uint8_t*. + * @param pcPrescaler pointer to the variable in which the timer prescaler has to be stored. + * This parameter must be an uint8_t*. + * @retval None. + */ +void SpiritTimerGetWakeUpTimerReload(float* pfWakeUpReloadMsec, uint8_t* pcCounter , uint8_t* pcPrescaler) +{ + uint8_t tempRegValue[2]; + uint32_t xtal=SpiritRadioGetXtalFrequency(); + float rco_freq; + + rco_freq=(float)SpiritTimerGetRcoFrequency(); + + /* Reads the reload Wake_Up timer registers value */ + g_xStatus = SpiritSpiReadRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 2, tempRegValue); + + /* Returns values */ + (*pcPrescaler)=tempRegValue[0]; + (*pcCounter)=tempRegValue[1]; + *pfWakeUpReloadMsec = (float)((((*pcPrescaler)+1)*((*pcCounter)+1)*(1000.0/rco_freq))); + +} + +/** + * @brief Computes and returns the RCO frequency. + * This frequency depends on the xtal frequency and the XTAL bit in register 0x01. + * @retval RCO frequency in Hz as an uint16_t. + */ +uint16_t SpiritTimerGetRcoFrequency(void) +{ + uint16_t rco_freq=34700; + uint32_t xtal=SpiritRadioGetXtalFrequency(); + + if(xtal>30000000) xtal/=2; + + if(xtal==25000000) + { + uint8_t xtal_flag; + SpiritSpiReadRegisters(0x01, 1, &xtal_flag); + xtal_flag=(xtal_flag&0x40); + + if(xtal_flag==0) + { + rco_freq=36100; + } + else + { + rco_freq=33300; + } + } + + return rco_freq; +} + +/** + * @brief Computes the values of the wakeup timer counter and prescaler from the user time expressed in millisecond. + * The prescaler and the counter values are computed maintaining the prescaler value as + * small as possible in order to obtain the best resolution, and in the meantime minimizing the error. + * @param fDesiredMsec desired wakeup timeout in millisecs. + * This parameter must be a float. Since the counter and prescaler are 8 bit registers the maximum + * reachable value is maxTime = fTclk x 256 x 256. + * @param pcCounter pointer to the variable in which the value for the wakeup timer counter has to be stored. + * This parameter must be a uint8_t*. + * @param pcPrescaler pointer to the variable in which the value for the wakeup timer prescaler has to be stored. + * This parameter must be an uint8_t*. + * @retval None + */ +void SpiritTimerComputeWakeUpValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler) +{ + float rco_freq,err; + uint32_t n; + + rco_freq=((float)SpiritTimerGetRcoFrequency())/1000; + + /* N cycles in the time base of the timer: + - clock of the timer is RCO frequency + - divide times 1000 more because we have an input in ms (variable rco_freq is already this frequency divided by 1000) + */ + n=(uint32_t)(fDesiredMsec*rco_freq); + + /* check if it is possible to reach that target with prescaler and counter of spirit1 */ + if(n/0xFF>0xFD) + { + /* if not return the maximum possible value */ + (*pcCounter) = 0xFF; + (*pcPrescaler) = 0xFF; + return; + } + + /* prescaler is really 2 as min value */ + (*pcPrescaler)=(n/0xFF)+2; + (*pcCounter) = n / (*pcPrescaler); + + /* check if the error is minimum */ + err=S_ABS((float)(*pcCounter)*(*pcPrescaler)/rco_freq-fDesiredMsec); + + if((*pcCounter)<=254) + { + if(S_ABS((float)((*pcCounter)+1)*(*pcPrescaler)/rco_freq-fDesiredMsec)1) + (*pcCounter)--; + else + (*pcCounter)=1; +} + + +/** + * @brief Computes the values of the rx_timeout timer counter and prescaler from the user time expressed in millisecond. + * The prescaler and the counter values are computed maintaining the prescaler value as + * small as possible in order to obtain the best resolution, and in the meantime minimizing the error. + * @param fDesiredMsec desired rx_timeout in millisecs. + * This parameter must be a float. Since the counter and prescaler are 8 bit registers the maximum + * reachable value is maxTime = fTclk x 255 x 255. + * @param pcCounter pointer to the variable in which the value for the rx_timeout counter has to be stored. + * This parameter must be a uint8_t*. + * @param pcPrescaler pointer to the variable in which the value for the rx_timeout prescaler has to be stored. + * This parameter must be an uint8_t*. + * @retval None + */ +void SpiritTimerComputeRxTimeoutValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler) +{ + uint32_t nXtalFrequency = SpiritRadioGetXtalFrequency(); + uint32_t n; + float err; + + /* if xtal is doubled divide it by 2 */ + if(nXtalFrequency>DOUBLE_XTAL_THR) { + nXtalFrequency >>= 1; + } + + /* N cycles in the time base of the timer: + - clock of the timer is xtal/1210 + - divide times 1000 more because we have an input in ms + */ + n=(uint32_t)(fDesiredMsec*nXtalFrequency/1210000); + + /* check if it is possible to reach that target with prescaler and counter of spirit1 */ + if(n/0xFF>0xFD) + { + /* if not return the maximum possible value */ + (*pcCounter) = 0xFF; + (*pcPrescaler) = 0xFF; + return; + } + + /* prescaler is really 2 as min value */ + (*pcPrescaler)=(n/0xFF)+2; + (*pcCounter) = n / (*pcPrescaler); + + /* check if the error is minimum */ + err=S_ABS((float)(*pcCounter)*(*pcPrescaler)*1210000/nXtalFrequency-fDesiredMsec); + + if((*pcCounter)<=254) + { + if(S_ABS((float)((*pcCounter)+1)*(*pcPrescaler)*1210000/nXtalFrequency-fDesiredMsec)1) + (*pcCounter)--; + else + (*pcCounter)=1; +} + + +/** + * @brief Sets the RX timeout stop conditions. + * @param xStopCondition new stop condition. + * This parameter can be any value of @ref RxTimeoutStopCondition. + * @retval None + */ +void SpiritTimerSetRxTimeoutStopCondition(RxTimeoutStopCondition xStopCondition) +{ + uint8_t tempRegValue[2]; + + /* Check the parameters */ + s_assert_param(IS_RX_TIMEOUT_STOP_CONDITION(xStopCondition)); + + /* Reads value on the PKT_FLT_OPTIONS and PROTOCOL2 register */ + g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 2, tempRegValue); + + tempRegValue[0] &= 0xBF; + tempRegValue[0] |= ((xStopCondition & 0x08) << 3); + + tempRegValue[1] &= 0x1F; + tempRegValue[1] |= (xStopCondition << 5); + + /* Writes value on the PKT_FLT_OPTIONS and PROTOCOL2 register */ + g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 2, tempRegValue); + +} + +/** + * @brief Sends the LDC_RELOAD command to SPIRIT. Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER registers. + * @param None. + * @retval None + */ +void SpiritTimerReloadStrobe(void) +{ + /* Sends the CMD_LDC_RELOAD command */ + g_xStatus = SpiritSpiCommandStrobes(COMMAND_LDC_RELOAD); + +} + + +/** + *@} + */ + + +/** + *@} + */ + + +/** + *@} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Types.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Types.c new file mode 100644 index 000000000..66a9d9339 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Types.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file SPIRIT_Types.c + * @author VMA division - AMS + * @version 3.2.2 + * @date 08-July-2015 + * @brief File for SPIRIT types. + * @details + * + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "SPIRIT_Types.h" +#include "MCU_Interface.h" + + +/** @addtogroup SPIRIT_Libraries + * @{ + */ + + +/** @addtogroup SPIRIT_Types + * @{ + */ + + +/** @defgroup Types_Private_TypesDefinitions Types Private Types Definitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Types_Private_Defines Types Private Defines + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Types_Private_Macros Types Private Macros + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup Types_Private_Variables Types Private Variables + * @{ + */ + +/** + * @brief Spirit Status global variable. + * This global variable of @ref SpiritStatus type is updated on every SPI transaction + * to maintain memory of Spirit Status. + */ + +volatile SpiritStatus g_xStatus; + +/** + * @} + */ + + + +/** @defgroup Types_Private_FunctionPrototypes Types Private FunctionPrototypes + * @{ + */ + + + +/** + * @} + */ + + + +/** @defgroup Types_Private_Functions Types Private Functions + * @{ + */ + +#ifdef SPIRIT_USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file pointer to the source file name + * @param line assert_param error line source number + * @retval : None + */ +void s_assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number */ + printf("Wrong parameters value: file %s on line %d\r\n", file, line); + + /* Infinite loop */ + while (1) + { + } +} +#elif SPIRIT_USE_VCOM_ASSERT + +#include "SDK_EVAL_VC_General.h" + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file pointer to the source file name + * @param line assert_param error line source number + * @param expression: string representing the assert failed expression + * @retval : None + */ +void s_assert_failed(uint8_t* file, uint32_t line, char* expression) +{ + + printf("\n\rVCOM DEBUG: Incorrect parameter. Please reboot.\n\r"); + printf("%s:%d \n\r",file,line); + printf("The expression %s returned FALSE.\n\r", expression); + + /* Infinite loop */ + while (1) + { + } +} + +#elif SPIRIT_USE_FRAME_ASSERT + +#include "SdkUsbProtocol.h" + +/** + * @brief Sends a notify frame with a payload indicating the name + * of the assert failed. + * @param expression: string representing the assert failed expression + * @retval : None + */ +void s_assert_failed(char* expression) +{ + char pcPayload[100]; + uint16_t i; + + for(i = 0 ; expression[i]!='(' ; i++); + expression[i]='\0'; + + strcpy(pcPayload, &expression[3]); + + //sprintf(pcPayload, "The expression %s returned FALSE.\n\r", expression); + SpiritNotifyAssertFailed(pcPayload); + +} + +#endif + + +/** + * @brief Updates the gState (the global variable used to maintain memory of Spirit Status) + * reading the MC_STATE register of SPIRIT. + * @param None + * @retval None + */ +void SpiritRefreshStatus(void) +{ + uint8_t tempRegValue; + + /* Reads the MC_STATUS register to update the g_xStatus */ + g_xStatus = SpiritSpiReadRegisters(MC_STATE1_BASE, 1, &tempRegValue); + +} + + +/** + * @} + */ + + + +/** + * @} + */ + + + +/** + * @} + */ + + + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/Release_Notes.html new file mode 100644 index 000000000..402f5716d --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/Release_Notes.html @@ -0,0 +1,159 @@ + + + + + + + + +Release Notes for STM32L1xx-Nucleo Board Drivers + + +
+


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+

Release +Notes for STM32L1xx-Nucleo  Board Drivers

+

Copyright +2014 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

1.0.0 +/ 05-September-2014

Main +Changes

+
  • First +official release dedicated to STM32CubeL1 based development. Supported devices is STM32L152RE.
+ +

License

+
+
Redistribution +and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met:
+ +
    +
  1. Redistributions +of source code must retain the above copyright notice, this list of +conditions and the following disclaimer.
    2. +
  2. Redistributions +in binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution.
    3. +
  3. Neither the +name of STMicroelectronics nor the names of its contributors may be +used to endorse or promote products derived
    +
    4. +
+       +from this software without specific prior written permission.
+
+THIS +SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +THE POSSIBILITY OF SUCH DAMAGE.
+
+ + +
+
+

For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

+
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+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.c b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.c new file mode 100644 index 000000000..c51c045bb --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.c @@ -0,0 +1,844 @@ +/** + ****************************************************************************** + * @file stm32l1xx_nucleo.c + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file provides set of firmware functions to manage: + * - LEDs and push-button available on STM32L1XX-Nucleo Kit + * from STMicroelectronics + * - LCD, joystick and microSD available on Adafruit 1.8" TFT LCD + * shield (reference ID 802) + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_nucleo.h" + +/** @addtogroup BSP + * @{ + */ + +/** @defgroup STM32L1XX_NUCLEO STM32L152RE-Nucleo + * @brief This file provides set of firmware functions to manage Leds and push-button + * available on STM32L1XX-Nucleo Kit from STMicroelectronics. + * It provides also LCD, joystick and uSD functions to communicate with + * Adafruit 1.8" TFT LCD shield (reference ID 802) + * @{ + */ + + +/** @defgroup STM32L1XX_NUCLEO_Private_Defines Private Defines + * @{ + */ + +/** +* @brief STM32L152RE NUCLEO BSP Driver version +*/ +#define __STM32L1XX_NUCLEO_BSP_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1XX_NUCLEO_BSP_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32L1XX_NUCLEO_BSP_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1XX_NUCLEO_BSP_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1XX_NUCLEO_BSP_VERSION ((__STM32L1XX_NUCLEO_BSP_VERSION_MAIN << 24)\ + |(__STM32L1XX_NUCLEO_BSP_VERSION_SUB1 << 16)\ + |(__STM32L1XX_NUCLEO_BSP_VERSION_SUB2 << 8 )\ + |(__STM32L1XX_NUCLEO_BSP_VERSION_RC)) + +/** + * @brief LINK SD Card + */ +#define SD_DUMMY_BYTE 0xFF +#define SD_NO_RESPONSE_EXPECTED 0x80 + +/** + * @} + */ + + +/** @defgroup STM32L1XX_NUCLEO_Private_Variables Private Variables + * @{ + */ +//GPIO_TypeDef* GPIO_PORT[LEDn] = {LED2_GPIO_PORT}; +//const uint16_t GPIO_PIN[LEDn] = {LED2_PIN}; +GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, + LED4_GPIO_PORT, LED5_GPIO_PORT}; +const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, + LED4_PIN, LED5_PIN}; + + +GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT}; +const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN}; +const uint16_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn}; + +/** + * @brief BUS variables + */ + +#ifdef HAL_SPI_MODULE_ENABLED +uint32_t SpixTimeout = NUCLEO_SPIx_TIMEOUT_MAX; /* success, 1=> fail) + */ +uint8_t BSP_JOY_Init(void) +{ + ADCx_Init(); + + /* Select Channel 8 to be converted */ + sConfig.Channel = ADC_CHANNEL_8; + sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES; + sConfig.Rank = 1; + + /* Return Joystick initialization status */ + return HAL_ADC_ConfigChannel(&hnucleo_Adc, &sConfig); +} + +/** + * @brief Returns the Joystick key pressed. + * @note To know which Joystick key is pressed we need to detect the voltage + * level on each key output + * - None : 3.3 V / 4095 + * - SEL : 1.055 V / 1308 + * - DOWN : 0.71 V / 88 + * - LEFT : 3.0 V / 3720 + * - RIGHT : 0.595 V / 737 + * - UP : 1.65 V / 2046 + * @retval JOYState_TypeDef: Code of the Joystick key pressed. + */ +JOYState_TypeDef BSP_JOY_GetState(void) +{ + JOYState_TypeDef state = JOY_NONE; + uint16_t keyconvertedvalue = 0; + + /* Start the conversion process */ + HAL_ADC_Start(&hnucleo_Adc); + + /* Wait for the end of conversion */ + HAL_ADC_PollForConversion(&hnucleo_Adc, 10); + + /* Check if the continous conversion of regular channel is finished */ + if(HAL_ADC_GetState(&hnucleo_Adc) == HAL_ADC_STATE_EOC_REG) + { + /* Get the converted value of regular channel */ + keyconvertedvalue = HAL_ADC_GetValue(&hnucleo_Adc); + } + + if((keyconvertedvalue > 2010) && (keyconvertedvalue < 2090)) + { + state = JOY_UP; + } + else if((keyconvertedvalue > 680) && (keyconvertedvalue < 780)) + { + state = JOY_RIGHT; + } + else if((keyconvertedvalue > 1270) && (keyconvertedvalue < 1350)) + { + state = JOY_SEL; + } + else if((keyconvertedvalue > 50) && (keyconvertedvalue < 130)) + { + state = JOY_DOWN; + } + else if((keyconvertedvalue > 3680) && (keyconvertedvalue < 3760)) + { + state = JOY_LEFT; + } + else + { + state = JOY_NONE; + } + + /* Return the code of the Joystick key pressed*/ + return state; +} + +#endif /* HAL_ADC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup STM32L1XX_NUCLEO_Private_Functions + * @{ + */ + +#ifdef HAL_SPI_MODULE_ENABLED +/****************************************************************************** + BUS OPERATIONS +*******************************************************************************/ +/** + * @brief Initializes SPI MSP. + * @retval None + */ +static void SPIx_MspInit(void) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE(); + NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE(); + + /* Configure SPI SCK */ + gpioinitstruct.Pin = NUCLEO_SPIx_SCK_PIN; + gpioinitstruct.Mode = GPIO_MODE_AF_PP; + gpioinitstruct.Pull = GPIO_PULLUP; + gpioinitstruct.Speed = GPIO_SPEED_HIGH; + gpioinitstruct.Alternate = NUCLEO_SPIx_SCK_AF; + HAL_GPIO_Init(NUCLEO_SPIx_SCK_GPIO_PORT, &gpioinitstruct); + + /* Configure SPI MISO and MOSI */ + gpioinitstruct.Pin = NUCLEO_SPIx_MOSI_PIN; + gpioinitstruct.Alternate = NUCLEO_SPIx_MISO_MOSI_AF; + gpioinitstruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, &gpioinitstruct); + + gpioinitstruct.Pin = NUCLEO_SPIx_MISO_PIN; + HAL_GPIO_Init(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, &gpioinitstruct); + + /*** Configure the SPI peripheral ***/ + /* Enable SPI clock */ + NUCLEO_SPIx_CLK_ENABLE(); +} + +/** + * @brief Initializes SPI HAL. + * @retval None + */ +static void SPIx_Init(void) +{ + if(HAL_SPI_GetState(&hnucleo_Spi) == HAL_SPI_STATE_RESET) + { + /* SPI Config */ + hnucleo_Spi.Instance = NUCLEO_SPIx; + /* SPI baudrate is set to 8 MHz maximum (PCLK2/SPI_BaudRatePrescaler = 32/4 = 8 MHz) + to verify these constraints: + - ST7735 LCD SPI interface max baudrate is 15MHz for write and 6.66MHz for read + Since the provided driver doesn't use read capability from LCD, only constraint + on write baudrate is considered. + - SD card SPI interface max baudrate is 25MHz for write/read + - PCLK2 max frequency is 32 MHz + */ + hnucleo_Spi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; + hnucleo_Spi.Init.Direction = SPI_DIRECTION_2LINES; + hnucleo_Spi.Init.CLKPhase = SPI_PHASE_2EDGE; + hnucleo_Spi.Init.CLKPolarity = SPI_POLARITY_HIGH; + hnucleo_Spi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + hnucleo_Spi.Init.CRCPolynomial = 7; + hnucleo_Spi.Init.DataSize = SPI_DATASIZE_8BIT; + hnucleo_Spi.Init.FirstBit = SPI_FIRSTBIT_MSB; + hnucleo_Spi.Init.NSS = SPI_NSS_SOFT; + hnucleo_Spi.Init.TIMode = SPI_TIMODE_DISABLED; + hnucleo_Spi.Init.Mode = SPI_MODE_MASTER; + + SPIx_MspInit(); + HAL_SPI_Init(&hnucleo_Spi); + } +} + +/** + * @brief SPI Read 4 bytes from device + * @retval Read data +*/ +static uint32_t SPIx_Read(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t readvalue = 0; + uint32_t writevalue = 0xFFFFFFFF; + + status = HAL_SPI_TransmitReceive(&hnucleo_Spi, (uint8_t*) &writevalue, (uint8_t*) &readvalue, 1, SpixTimeout); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* Execute user timeout callback */ + SPIx_Error(); + } + + return readvalue; +} + +/** + * @brief SPI Write a byte to device + * @param Value: value to be written + * @retval None + */ +static void SPIx_Write(uint8_t Value) +{ + HAL_StatusTypeDef status = HAL_OK; + + status = HAL_SPI_Transmit(&hnucleo_Spi, (uint8_t*) &Value, 1, SpixTimeout); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* Execute user timeout callback */ + SPIx_Error(); + } +} + +/** + * @brief SPI error treatment function + * @retval None + */ +static void SPIx_Error (void) +{ + /* De-initialize the SPI communication BUS */ + HAL_SPI_DeInit(&hnucleo_Spi); + + /* Re-Initiaize the SPI communication BUS */ + SPIx_Init(); +} + +/****************************************************************************** + LINK OPERATIONS +*******************************************************************************/ + +/********************************* LINK SD ************************************/ +/** + * @brief Initializes the SD Card and put it into StandBy State (Ready for + * data transfer). + * @retval None + */ +void SD_IO_Init(void) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + uint8_t counter = 0; + + /* SD_CS_GPIO Periph clock enable */ + SD_CS_GPIO_CLK_ENABLE(); + + /* Configure SD_CS_PIN pin: SD Card CS pin */ + gpioinitstruct.Pin = SD_CS_PIN; + gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; + gpioinitstruct.Pull = GPIO_PULLUP; + gpioinitstruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(SD_CS_GPIO_PORT, &gpioinitstruct); + + /*------------Put SD in SPI mode--------------*/ + /* SD SPI Config */ + SPIx_Init(); + + /* SD chip select high */ + SD_CS_HIGH(); + + /* Send dummy byte 0xFF, 10 times with CS high */ + /* Rise CS and MOSI for 80 clocks cycles */ + for (counter = 0; counter <= 9; counter++) + { + /* Send dummy byte 0xFF */ + SD_IO_WriteByte(SD_DUMMY_BYTE); + } +} + +/** + * @brief Writes a byte on the SD. + * @param Data: byte to send. + * @retval None + */ +void SD_IO_WriteByte(uint8_t Data) +{ + /* Send the byte */ + SPIx_Write(Data); +} + +/** + * @brief Reads a byte from the SD. + * @retval The received byte. + */ +uint8_t SD_IO_ReadByte(void) + { + uint8_t data = 0; + + /* Get the received data */ + data = SPIx_Read(); + + /* Return the shifted data */ + return data; +} + +/** + * @brief Sends 5 bytes command to the SD card and get response + * @param Cmd: The user expected command to send to SD card. + * @param Arg: The command argument. + * @param Crc: The CRC. + * @param Response: Expected response from the SD card + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef SD_IO_WriteCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc, uint8_t Response) +{ + uint32_t counter = 0x00; + uint8_t frame[6] = {0}; + + /* Prepare Frame to send */ + frame[0] = (Cmd | 0x40); /* Construct byte 1 */ + frame[1] = (uint8_t)(Arg >> 24); /* Construct byte 2 */ + frame[2] = (uint8_t)(Arg >> 16); /* Construct byte 3 */ + frame[3] = (uint8_t)(Arg >> 8); /* Construct byte 4 */ + frame[4] = (uint8_t)(Arg); /* Construct byte 5 */ + frame[5] = (Crc); /* Construct byte 6 */ + + /* SD chip select low */ + SD_CS_LOW(); + + /* Send Frame */ + for (counter = 0; counter < 6; counter++) + { + SD_IO_WriteByte(frame[counter]); /* Send the Cmd bytes */ + } + + if(Response != SD_NO_RESPONSE_EXPECTED) + { + return SD_IO_WaitResponse(Response); + } + + return HAL_OK; +} + +/** + * @brief Waits response from the SD card + * @param Response: Expected response from the SD card + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef SD_IO_WaitResponse(uint8_t Response) +{ + uint32_t timeout = 0xFFFF; + + /* Check if response is got or a timeout is happen */ + while ((SD_IO_ReadByte() != Response) && timeout) + { + timeout--; + } + + if (timeout == 0) + { + /* After time out */ + return HAL_TIMEOUT; + } + else + { + /* Right response got */ + return HAL_OK; + } + } + +/** + * @brief Sends dummy byte with CS High + * @retval None + */ +void SD_IO_WriteDummy(void) +{ + /* SD chip select high */ + SD_CS_HIGH(); + + /* Send Dummy byte 0xFF */ + SD_IO_WriteByte(SD_DUMMY_BYTE); +} + +/********************************* LINK LCD ***********************************/ +/** + * @brief Initializes the LCD + * @retval None + */ +void LCD_IO_Init(void) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + + /* LCD_CS_GPIO and LCD_DC_GPIO Periph clock enable */ + LCD_CS_GPIO_CLK_ENABLE(); + LCD_DC_GPIO_CLK_ENABLE(); + + /* Configure LCD_CS_PIN pin: LCD Card CS pin */ + gpioinitstruct.Pin = LCD_CS_PIN; + gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; + gpioinitstruct.Pull = GPIO_NOPULL; + gpioinitstruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(SD_CS_GPIO_PORT, &gpioinitstruct); + + /* Configure LCD_DC_PIN pin: LCD Card DC pin */ + gpioinitstruct.Pin = LCD_DC_PIN; + HAL_GPIO_Init(LCD_DC_GPIO_PORT, &gpioinitstruct); + + /* LCD chip select high */ + LCD_CS_HIGH(); + + /* LCD SPI Config */ + SPIx_Init(); +} + +/** + * @brief Writes command to select the LCD register. + * @param LCDReg: Address of the selected register. + * @retval None + */ +void LCD_IO_WriteReg(uint8_t LCDReg) +{ + /* Reset LCD control line CS */ + LCD_CS_LOW(); + + /* Set LCD data/command line DC to Low */ + LCD_DC_LOW(); + + /* Send Command */ + SPIx_Write(LCDReg); + + /* Deselect : Chip Select high */ + LCD_CS_HIGH(); +} + +/** +* @brief Write register value. +* @param pData Pointer on the register value +* @param Size Size of byte to transmit to the register +* @retval None +*/ +void LCD_IO_WriteMultipleData(uint8_t *pData, uint32_t Size) +{ + uint32_t counter = 0; + + /* Reset LCD control line CS */ + LCD_CS_LOW(); + + /* Set LCD data/command line DC to High */ + LCD_DC_HIGH(); + + if (Size == 1) + { + /* Only 1 byte to be sent to LCD - general interface can be used */ + /* Send Data */ + SPIx_Write(*pData); + } + else + { + /* Several data should be sent in a raw */ + /* Direct SPI accesses for optimization */ + for (counter = Size; counter != 0; counter--) + { + while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE) + { + } + /* Need to invert bytes for LCD*/ + *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *(pData+1); + + while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE) + { + } + *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *pData; + counter--; + pData += 2; + } + + /* Wait until the bus is ready before releasing Chip select */ + while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_BSY) != RESET) + { + } + } + /* Deselect : Chip Select high */ + LCD_CS_HIGH(); +} + +/** + * @brief Wait for loop in ms. + * @param Delay in ms. + * @retval None + */ +void LCD_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +/******************************* LINK JOYSTICK ********************************/ +/** + * @brief Initializes ADC MSP. + * @retval None + */ +static void ADCx_MspInit(ADC_HandleTypeDef *hadc) +{ + GPIO_InitTypeDef gpioinitstruct = {0}; + + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + NUCLEO_ADCx_GPIO_CLK_ENABLE(); + + /* Configure ADC1 Channel8 as analog input */ + gpioinitstruct.Pin = NUCLEO_ADCx_GPIO_PIN ; + gpioinitstruct.Mode = GPIO_MODE_ANALOG; + gpioinitstruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(NUCLEO_ADCx_GPIO_PORT, &gpioinitstruct); + + /*** Configure the ADC peripheral ***/ + /* Enable ADC clock */ + NUCLEO_ADCx_CLK_ENABLE(); +} + +/** + * @brief Initializes ADC HAL. + * @retval None + */ +static void ADCx_Init(void) +{ + if(HAL_ADC_GetState(&hnucleo_Adc) == HAL_ADC_STATE_RESET) + { + /* ADC Config */ + hnucleo_Adc.Instance = NUCLEO_ADCx; + hnucleo_Adc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; /* (must not exceed 16MHz) */ + hnucleo_Adc.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_DISABLE; + hnucleo_Adc.Init.LowPowerAutoWait = ADC_AUTOWAIT_UNTIL_DATA_READ; + hnucleo_Adc.Init.Resolution = ADC_RESOLUTION12b; + hnucleo_Adc.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hnucleo_Adc.Init.ContinuousConvMode = DISABLE; + hnucleo_Adc.Init.ScanConvMode = DISABLE; + hnucleo_Adc.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hnucleo_Adc.Init.EOCSelection = EOC_SINGLE_CONV; + hnucleo_Adc.Init.DMAContinuousRequests = DISABLE; + + ADCx_MspInit(&hnucleo_Adc); + HAL_ADC_Init(&hnucleo_Adc); + } +} + +#endif /* HAL_ADC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.h b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.h new file mode 100644 index 000000000..ef185dc2d --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.h @@ -0,0 +1,301 @@ +/** + ****************************************************************************** + * @file stm32l1xx_nucleo.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains definitions for: + * - LEDs and push-button available on STM32L1XX-Nucleo Kit + * from STMicroelectronics + * - LCD, joystick and microSD available on Adafruit 1.8" TFT LCD + * shield (reference ID 802) + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32L1XX_NUCLEO + * @{ + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1XX_NUCLEO_H +#define __STM32L1XX_NUCLEO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + + +/** @defgroup STM32L1XX_NUCLEO_Exported_Types Exported Types + * @{ + */ + +typedef enum +{ + BUTTON_USER = 0, +} Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +} ButtonMode_TypeDef; + +typedef enum +{ + JOY_NONE = 0, + JOY_SEL = 1, + JOY_DOWN = 2, + JOY_LEFT = 3, + JOY_RIGHT = 4, + JOY_UP = 5 +} JOYState_TypeDef; + +/** + * @} + */ + +/** @defgroup STM32L1XX_NUCLEO_Exported_Constants Exported Constants + * @{ + */ + +/** + * @brief Define for STM32L1xx_NUCLEO board + */ +#if !defined (USE_STM32L1xx_NUCLEO) + #define USE_STM32L1xx_NUCLEO +#endif + +/** @defgroup STM32L1XX_NUCLEO_LED LED Constants + * @{ + */ + +typedef enum +{ + LED1 = 0, + LED2 = 1, + LED3 = 2, + LED4 = 3, + LED5 = 4 +} Led_TypeDef; + + + +#define LEDn 5 + +#define LED2_PIN GPIO_PIN_5 +#define LED2_GPIO_PORT GPIOA +#define LED2_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define LED2_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() + + +#define LED1_PIN GPIO_PIN_4 +#define LED1_GPIO_PORT GPIOB +#define LED1_GPIO_CLK RCC_AHBPeriph_GPIOB + +#define LED3_PIN GPIO_PIN_14 +#define LED3_GPIO_PORT GPIOB +#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOB + +#define LED4_PIN GPIO_PIN_14 +#define LED4_GPIO_PORT GPIOB +#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOB + +#define LED5_PIN GPIO_PIN_14 +#define LED5_GPIO_PORT GPIOB +#define LED5_GPIO_CLK RCC_AHBPeriph_GPIOB + +#define LEDx_GPIO_CLK_ENABLE(__INDEX__) (LED2_GPIO_CLK_ENABLE()) + +#define LEDx_GPIO_CLK_DISABLE(__INDEX__) (LED2_GPIO_CLK_DISABLE()) + +/** + * @} + */ + +/** @defgroup STM32L1XX_NUCLEO_BUTTON BUTTON Constants + * @{ + */ +#define BUTTONn 1 + +/** + * @brief Key push-button + */ +#define USER_BUTTON_PIN GPIO_PIN_13 +#define USER_BUTTON_GPIO_PORT GPIOC +#define USER_BUTTON_GPIO_CLK_ENABLE() __GPIOC_CLK_ENABLE() +#define USER_BUTTON_GPIO_CLK_DISABLE() __GPIOC_CLK_DISABLE() +#define USER_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) (USER_BUTTON_GPIO_CLK_ENABLE()) + +#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) (USER_BUTTON_GPIO_CLK_DISABLE()) +/** + * @} + */ + +/** @addtogroup STM32L1XX_NUCLEO_BUS BUS Constants + * @{ + */ +/*###################### SPI1 ###################################*/ +#define NUCLEO_SPIx SPI1 +#define NUCLEO_SPIx_CLK_ENABLE() __SPI1_CLK_ENABLE() + +#define NUCLEO_SPIx_SCK_AF GPIO_AF5_SPI1 +#define NUCLEO_SPIx_SCK_GPIO_PORT GPIOA +#define NUCLEO_SPIx_SCK_PIN GPIO_PIN_5 +#define NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define NUCLEO_SPIx_SCK_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() + +#define NUCLEO_SPIx_MISO_MOSI_AF GPIO_AF5_SPI1 +#define NUCLEO_SPIx_MISO_MOSI_GPIO_PORT GPIOA +#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() +#define NUCLEO_SPIx_MISO_PIN GPIO_PIN_6 +#define NUCLEO_SPIx_MOSI_PIN GPIO_PIN_7 +/* Maximum Timeout values for flags waiting loops. These timeouts are not based + on accurate values, they just guarantee that the application will not remain + stuck if the SPI communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...). */ +#define NUCLEO_SPIx_TIMEOUT_MAX 1000 + +#define NUCLEO_I2C_SHIELDS_EV_IRQn I2C1_EV_IRQn +/** + * @brief SD Control Lines management + */ +#define SD_CS_LOW() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_RESET) +#define SD_CS_HIGH() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_SET) + +/** + * @brief LCD Control Lines management + */ +#define LCD_CS_LOW() HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_RESET) +#define LCD_CS_HIGH() HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_SET) +#define LCD_DC_LOW() HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_RESET) +#define LCD_DC_HIGH() HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_SET) + +/** + * @brief SD Control Interface pins + */ +#define SD_CS_PIN GPIO_PIN_5 +#define SD_CS_GPIO_PORT GPIOB +#define SD_CS_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define SD_CS_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() + +/** + * @brief LCD Control Interface pins + */ +#define LCD_CS_PIN GPIO_PIN_6 +#define LCD_CS_GPIO_PORT GPIOB +#define LCD_CS_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define LCD_CS_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() + +/** + * @brief LCD Data/Command Interface pins + */ +#define LCD_DC_PIN GPIO_PIN_9 +#define LCD_DC_GPIO_PORT GPIOA +#define LCD_DC_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define LCD_DC_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() + +/*##################### ADC1 ###################################*/ +/** + * @brief ADC Interface pins + * used to detect motion of Joystick available on Adafruit 1.8" TFT shield + */ +#define NUCLEO_ADCx ADC1 +#define NUCLEO_ADCx_CLK_ENABLE() __ADC1_CLK_ENABLE() + +#define NUCLEO_ADCx_GPIO_PORT GPIOB +#define NUCLEO_ADCx_GPIO_PIN GPIO_PIN_0 +#define NUCLEO_ADCx_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define NUCLEO_ADCx_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() + + +/** @defgroup STM32L1XX_NUCLEO_Exported_Functions + * @{ + */ +uint32_t BSP_GetVersion(void); +/** @addtogroup STM32L1XX_NUCLEO_LED_Functions + * @{ + */ + +void BSP_LED_Init(Led_TypeDef Led); +void BSP_LED_On(Led_TypeDef Led); +void BSP_LED_Off(Led_TypeDef Led); +void BSP_LED_Toggle(Led_TypeDef Led); + +/** + * @} + */ + +/** @addtogroup STM32L1XX_NUCLEO_BUTTON_Functions + * @{ + */ + +void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); +uint32_t BSP_PB_GetState(Button_TypeDef Button); + +#ifdef HAL_ADC_MODULE_ENABLED +uint8_t BSP_JOY_Init(void); +JOYState_TypeDef BSP_JOY_GetState(void); +#endif /* HAL_ADC_MODULE_ENABLED */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1XX_NUCLEO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/Release_Notes.html new file mode 100644 index 000000000..25cf4ea92 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/Release_Notes.html @@ -0,0 +1,171 @@ + + + + + +Release Notes for X-NUCLEO-IDS02Ax(x=3,4,5) STM Shield + + + + + +
+


+

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+ + + + + + + + + +
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+
+

Release +Notes for X-NUCLEO-IDS02Ax(x=3,4,5) STM Shield

+

Copyright +2014 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+ +

V1.0.0/ 10-Oct-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • First +official release.
    • +
+ +

License
+

+
Redistribution +and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met:
+ +
    +
  1. Redistributions +of source code must retain the above copyright notice, this list of +conditions and the following disclaimer.
    2. +
  2. Redistributions +in binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution.
    3. +
  3. Neither the +name of STMicroelectronics nor the names of its contributors may be +used to endorse or promote products derived
    +
    4. +
+       +from this software without specific prior written permission.
+
+THIS +SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +THE POSSIBILITY OF SUCH DAMAGE.
+

+ +
+
+

For +complete documentation on SPIRIT1 Shields +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.c new file mode 100644 index 000000000..c499372c3 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.c @@ -0,0 +1,353 @@ +/** +****************************************************************************** +* @file radio_gpio.c +* @author System Lab - NOIDA +* @version V1.0.0 +* @date 15-May-2014 +* @brief This file provides code for the configuration of all used GPIO pins + for Radio inetrface. +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "radio_gpio.h" + +/** + * @addtogroup BSP + * @{ + */ + + +/** + * @addtogroup X-NUCLEO-IDS02Ax + * @{ + */ + + +/** + * @defgroup Radio_Gpio_Private_TypesDefinitions Radio_Gpio Private Types Definitions + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Radio_Gpio_Private_Defines Radio_Gpio Private Defines + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Radio_Gpio_Private_Macros Radio_Gpio Private Macros + * @{ + */ +#define POR_TIME ((uint16_t)0x1E00) + +/** + * @} + */ + + +/** + * @defgroup Radio_Gpio_Private_Variables Radio_Gpio Private Variables + * @{ + */ + +/** +* @brief Radio_Gpio Port array +*/ +GPIO_TypeDef* aRADIO_GPIO_PORT[RADIO_GPIO_NUMBER] = { + RADIO_GPIO_0_PORT, + RADIO_GPIO_1_PORT, + RADIO_GPIO_2_PORT, + RADIO_GPIO_3_PORT, + RADIO_GPIO_SDN_PORT +}; + + +/** +* @brief Radio_Gpio Pin array +*/ +static const uint16_t aRADIO_GPIO_PIN[RADIO_GPIO_NUMBER] = { + RADIO_GPIO_0_PIN, + RADIO_GPIO_1_PIN, + RADIO_GPIO_2_PIN, + RADIO_GPIO_3_PIN, + RADIO_GPIO_SDN_PIN +}; + + +/** +* @brief Radio_Gpio Speed array +*/ +static const uint32_t aRADIO_GPIO_SPEED[RADIO_GPIO_NUMBER] = { + RADIO_GPIO_0_SPEED, + RADIO_GPIO_1_SPEED, + RADIO_GPIO_2_SPEED, + RADIO_GPIO_3_SPEED, + RADIO_GPIO_SDN_SPEED +}; + + +/** +* @brief Radio_Gpio PuPd array +*/ +static const uint32_t aRADIO_GPIO_PUPD[RADIO_GPIO_NUMBER] = { + RADIO_GPIO_0_PUPD, + RADIO_GPIO_1_PUPD, + RADIO_GPIO_2_PUPD, + RADIO_GPIO_3_PUPD, + RADIO_GPIO_SDN_PUPD +}; + + +/** +* @brief Exti Mode array +*/ +static const uint32_t aRADIO_GPIO_EXTI_MODE[RADIO_GPIO_NUMBER-1] = { + RADIO_GPIO_0_EXTI_MODE, + RADIO_GPIO_1_EXTI_MODE, + RADIO_GPIO_2_EXTI_MODE, + RADIO_GPIO_3_EXTI_MODE +}; + + +/** +* @brief Exti IRQn array +*/ +static const uint8_t aRADIO_GPIO_IRQn[RADIO_GPIO_NUMBER-1] = { + RADIO_GPIO_0_EXTI_IRQN, + RADIO_GPIO_1_EXTI_IRQN, + RADIO_GPIO_2_EXTI_IRQN, + RADIO_GPIO_3_EXTI_IRQN +}; + + +/** + * @} + */ + + +/** + * @defgroup Radio_Gpio_Private_FunctionPrototypes Radio_Gpio Private Function Prototypes + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup Radio_Gpio_Private_Functions Radio_Gpio Private Functions + * @{ + */ + + +/** +* @brief Configures MCU GPIO and EXTI Line for GPIOs. +* @param xGpio Specifies the GPIO to be configured. +* This parameter can be one of following parameters: +* @arg GPIO_0 +* @arg GPIO_1 +* @arg GPIO_2 +* @arg GPIO_3 +* @param xGpioMode Specifies GPIO mode. +* This parameter can be one of following parameters: +* @arg RADIO_MODE_GPIO_IN: MCU GPIO will be used as simple input. +* @argRADIO_MODE_GPIO_OUT: MCU GPIO will be used as simple output. +* @arg RADIO_MODE_EXTI_IN: MCU GPIO will be connected to EXTI line with interrupt +* generation capability. +* @retval None. +*/ +void RadioGpioInit(RadioGpioPin xGpio, RadioGpioMode xGpioMode) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Check the parameters */ + assert_param(IS_RADIO_GPIO_PIN(xGpio)); + assert_param(IS_RADIO_GPIO_MODE(xGpioMode)); + + /* GPIO Ports Clock Enable */ + __GPIOA_CLK_ENABLE(); + __GPIOC_CLK_ENABLE(); + __GPIOB_CLK_ENABLE(); + + /* Configures MCU GPIO */ + if (xGpioMode == RADIO_MODE_GPIO_OUT) + { + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + } + else + { + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + } + + GPIO_InitStruct.Pin = aRADIO_GPIO_PIN[xGpio]; + GPIO_InitStruct.Pull = aRADIO_GPIO_PUPD[xGpio]; + GPIO_InitStruct.Speed = aRADIO_GPIO_SPEED[xGpio]; + HAL_GPIO_Init(aRADIO_GPIO_PORT[xGpio], &GPIO_InitStruct); + + if (xGpioMode == RADIO_MODE_EXTI_IN) + { + GPIO_InitStruct.Pin = aRADIO_GPIO_PIN[xGpio]; + GPIO_InitStruct.Pull = aRADIO_GPIO_PUPD[xGpio]; + GPIO_InitStruct.Speed = aRADIO_GPIO_SPEED[xGpio]; + GPIO_InitStruct.Mode = aRADIO_GPIO_EXTI_MODE[xGpio]; + HAL_GPIO_Init(aRADIO_GPIO_PORT[xGpio], &GPIO_InitStruct); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + /* NVIC_SetPriority((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio]), 0x02); */ + /* HAL_NVIC_EnableIRQ((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio])); */ + } +} + + +/** +* @brief Enables or disables the interrupt on GPIO . +* @param xGpio Specifies the GPIO whose priority shall be changed. +* This parameter can be one of following parameters: +* @arg GPIO_0 +* @arg GPIO_1 +* @arg GPIO_2 +* @arg GPIO_3 +* @param nPreemption Specifies Preemption Priority. +* @param nSubpriority Specifies Subgroup Priority. +* @param xNewState Specifies the State. +* This parameter can be one of following parameters: +* @arg ENABLE: Interrupt is enabled +* @arg DISABLE: Interrupt is disabled +* @retval None. +*/ +void RadioGpioInterruptCmd(RadioGpioPin xGpio, uint8_t nPreemption, uint8_t nSubpriority, FunctionalState xNewState) +{ + HAL_NVIC_SetPriority((IRQn_Type) (aRADIO_GPIO_IRQn[xGpio]), nPreemption, nSubpriority); + if (!xNewState) + { + HAL_NVIC_DisableIRQ((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio])); + } + else + { + HAL_NVIC_EnableIRQ((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio])); + } +} + + +/** +* @brief Returns the level of a specified GPIO. +* @param xGpio Specifies the GPIO to be read. +* This parameter can be one of following parameters: +* @arg GPIO_0 +* @arg GPIO_1 +* @arg GPIO_2 +* @arg GPIO_3 +* @retval FlagStatus Level of the GPIO. This parameter can be: +* SET or RESET. +*/ +FlagStatus RadioGpioGetLevel(RadioGpioPin xGpio) +{ + /* Gets the GPIO level */ + uint16_t nDataPort = HAL_GPIO_ReadPin(aRADIO_GPIO_PORT[xGpio], aRADIO_GPIO_PIN[xGpio]); + if (nDataPort & aRADIO_GPIO_PIN[xGpio]) + { + return SET; + } + else + { + return RESET; + } +} + + +/** +* @brief Sets the level of a specified GPIO. +* @param xGpio Specifies the GPIO to be set. +* This parameter can be one of following parameters: +* @arg GPIO_0 +* @arg GPIO_1 +* @arg GPIO_2 +* @arg GPIO_3 +* @param GPIO_PinState Level of the GPIO. This parameter can be: +* GPIO_PIN_SET or GPIO_PIN_RESET. +* @retval None. +*/ +void RadioGpioSetLevel(RadioGpioPin xGpio, GPIO_PinState xState) +{ + /* Sets the GPIO level */ + HAL_GPIO_WritePin(aRADIO_GPIO_PORT[xGpio], aRADIO_GPIO_PIN[xGpio], xState); +} + + +/** +* @brief Puts at logic 1 the SDN pin. +* @param None. +* @retval None. +*/ +void SdkEvalEnterShutdown(void) +{ + /* Puts high the GPIO connected to shutdown pin */ + /* Check the parameters */ + RadioGpioSetLevel(RADIO_GPIO_SDN, GPIO_PIN_SET); +} + + +/** +* @brief Put at logic 0 the SDN pin. +* @param None. +* @retval None. +*/ +void SdkEvalExitShutdown(void) +{ + /* Puts low the GPIO connected to shutdown pin */ + RadioGpioSetLevel(RADIO_GPIO_SDN, GPIO_PIN_RESET); + + /* Delay to allow the circuit POR, about 700 us */ + for (volatile uint32_t Index = 0; Index < POR_TIME; Index++); +} + + +/** +* @brief check the logic(0 or 1) at the SDN pin. +* @param None. +* @retval FlagStatus. +*/ +SpiritFlagStatus SdkEvalCheckShutdown(void) +{ + return RadioGpioGetLevel(RADIO_GPIO_SDN); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.h new file mode 100644 index 000000000..1af00edb7 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.h @@ -0,0 +1,218 @@ +/** +****************************************************************************** +* @file radio_gpio.h +* @author System Lab - NOIDA +* @version V1.0.0 +* @date 15-May-2014 +* @brief This file contains all the functions prototypes for the gpio +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported Variables ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_GPIO_H +#define __RADIO_GPIO_H +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" +#include "SPIRIT_Types.h" + +/** + * @addtogroup BSP + * @{ + */ + + +/* Exported types ------------------------------------------------------------*/ + /* MCU GPIO pin working mode for GPIO */ +typedef enum +{ + RADIO_MODE_GPIO_IN = 0x00, /*!< Work as GPIO input */ + RADIO_MODE_EXTI_IN, /*!< Work as EXTI */ + RADIO_MODE_GPIO_OUT, /*!< Work as GPIO output */ +}RadioGpioMode; + + /* MCU GPIO pin enumeration for GPIO */ +typedef enum +{ + RADIO_GPIO_0 = 0x00, /*!< GPIO_0 selected */ + RADIO_GPIO_1 = 0x01, /*!< GPIO_1 selected */ + RADIO_GPIO_2 = 0x02, /*!< GPIO_2 selected */ + RADIO_GPIO_3 = 0x03, /*!< GPIO_3 selected */ + RADIO_GPIO_SDN = 0x04, /*!< GPIO_SDN selected */ +} +RadioGpioPin; + + +/* Exported constants --------------------------------------------------------*/ + + +/* Exported macro ------------------------------------------------------------*/ + /* MCU GPIO pin working mode for GPIO */ +#define IS_RADIO_GPIO_MODE(MODE) (((MODE) == RADIO_MODE_GPIO_IN) || \ + ((MODE) == RADIO_MODE_EXTI_IN) || \ + ((MODE) == RADIO_MODE_GPIO_OUT)) + +/* Number of Arduino pins used for RADIO GPIO interface */ +#define RADIO_GPIO_NUMBER ((uint8_t)5) + +/* MCU GPIO pin enumeration for GPIO */ +#define IS_RADIO_GPIO_PIN(PIN) (((PIN) == RADIO_GPIO_0) || \ + ((PIN) == RADIO_GPIO_1) || \ + ((PIN) == RADIO_GPIO_2) || \ + ((PIN) == RADIO_GPIO_3) || \ + ((PIN) == RADIO_GPIO_SDN)) + +/* Define for RADIO board */ +#if !defined (USE_SPIRIT1_DEFAULT) + #define USE_SPIRIT1_DEFAULT +#endif + +/* @defgroup Radio_Gpio_config_Define */ +/*NOTE: GPIO0, GPIO1, GPIO2 of SPIRIT1 is not used in the shield*/ + +#define RADIO_GPIO_0_PORT GPIOC +#define RADIO_GPIO_0_PIN GPIO_PIN_1 +#define RADIO_GPIO_0_CLOCK_ENABLE() __GPIOC_CLK_ENABLE() +#define RADIO_GPIO_0_CLOCK_DISABLE() __GPIOC_CLK_ENABLE() +#define RADIO_GPIO_0_SPEED GPIO_SPEED_HIGH +#define RADIO_GPIO_0_PUPD GPIO_NOPULL +#define RADIO_GPIO_0_EXTI_LINE GPIO_PIN_1 +#define RADIO_GPIO_0_EXTI_MODE GPIO_MODE_IT_FALLING +#define RADIO_GPIO_0_EXTI_IRQN EXTI1_IRQn +#define RADIO_GPIO_0_EXTI_PREEMPTION_PRIORITY 2 +#define RADIO_GPIO_0_EXTI_SUB_PRIORITY 2 +#define RADIO_GPIO_0_EXTI_IRQ_HANDLER EXTI1_IRQHandler + +#define RADIO_GPIO_1_PORT GPIOB +#define RADIO_GPIO_1_PIN GPIO_PIN_0 +#define RADIO_GPIO_1_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() +#define RADIO_GPIO_1_CLOCK_DISABLE() __GPIOB_CLK_ENABLE() +#define RADIO_GPIO_1_SPEED GPIO_SPEED_HIGH +#define RADIO_GPIO_1_PUPD GPIO_NOPULL +#define RADIO_GPIO_1_EXTI_LINE GPIO_PIN_0 +#define RADIO_GPIO_1_EXTI_MODE GPIO_MODE_IT_FALLING +#define RADIO_GPIO_1_EXTI_IRQN EXTI0_IRQn +#define RADIO_GPIO_1_EXTI_PREEMPTION_PRIORITY 2 +#define RADIO_GPIO_1_EXTI_SUB_PRIORITY 2 +#define RADIO_GPIO_1_EXTI_IRQ_HANDLER EXTI0_IRQHandler + +#define RADIO_GPIO_2_PORT GPIOA +#define RADIO_GPIO_2_PIN GPIO_PIN_4 +#define RADIO_GPIO_2_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() +#define RADIO_GPIO_2_CLOCK_DISABLE() __GPIOA_CLK_ENABLE() +#define RADIO_GPIO_2_SPEED GPIO_SPEED_HIGH +#define RADIO_GPIO_2_PUPD GPIO_NOPULL +#define RADIO_GPIO_2_EXTI_LINE GPIO_PIN_4 +#define RADIO_GPIO_2_EXTI_MODE GPIO_MODE_IT_FALLING +#define RADIO_GPIO_2_EXTI_IRQN EXTI4_IRQn +#define RADIO_GPIO_2_EXTI_PREEMPTION_PRIORITY 2 +#define RADIO_GPIO_2_EXTI_SUB_PRIORITY 2 +#define RADIO_GPIO_2_EXTI_IRQ_HANDLER EXTI4_IRQHandler + + +#if defined (USE_SPIRIT1_DEFAULT) + + +#define RADIO_GPIO_3_PORT GPIOC +#define RADIO_GPIO_3_PIN GPIO_PIN_7 +#define RADIO_GPIO_3_CLOCK_ENABLE() __GPIOC_CLK_ENABLE() +#define RADIO_GPIO_3_CLOCK_DISABLE() __GPIOC_CLK_DISABLE() +#define RADIO_GPIO_3_SPEED GPIO_SPEED_HIGH +#define RADIO_GPIO_3_PUPD GPIO_NOPULL +#define RADIO_GPIO_3_EXTI_LINE GPIO_PIN_7 +#define RADIO_GPIO_3_EXTI_MODE GPIO_MODE_IT_FALLING +#define RADIO_GPIO_3_EXTI_IRQN EXTI9_5_IRQn +#define RADIO_GPIO_3_EXTI_PREEMPTION_PRIORITY 2 +#define RADIO_GPIO_3_EXTI_SUB_PRIORITY 2 +#define RADIO_GPIO_3_EXTI_IRQ_HANDLER EXTI9_5_IRQHandler + +#else + +#define RADIO_GPIO_3_PORT GPIOA +#define RADIO_GPIO_3_PIN GPIO_PIN_0 +#define RADIO_GPIO_3_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() +#define RADIO_GPIO_3_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() +#define RADIO_GPIO_3_SPEED GPIO_SPEED_HIGH +#define RADIO_GPIO_3_PUPD GPIO_NOPULL +#define RADIO_GPIO_3_EXTI_LINE GPIO_PIN_0 +#define RADIO_GPIO_3_EXTI_MODE GPIO_MODE_IT_FALLING +#define RADIO_GPIO_3_EXTI_IRQN EXTI0_IRQn +#define RADIO_GPIO_3_EXTI_PREEMPTION_PRIORITY 2 +#define RADIO_GPIO_3_EXTI_SUB_PRIORITY 2 +#define RADIO_GPIO_3_EXTI_IRQ_HANDLER EXTI0_IRQHandler + +#endif + +#define RADIO_GPIO_SDN_PORT GPIOA +#define RADIO_GPIO_SDN_PIN GPIO_PIN_10 +#define RADIO_GPIO_SDN_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() +#define RADIO_GPIO_SDN_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() +#define RADIO_GPIO_SDN_SPEED GPIO_SPEED_HIGH +#define RADIO_GPIO_SDN_PUPD GPIO_PULLUP + + +#define RADIO_GPIO_IRQ RADIO_GPIO_3 +#define SPIRIT_GPIO_IRQ SPIRIT_GPIO_3 + +/* Exported Variables ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ +FlagStatus RadioGpioGetLevel(RadioGpioPin xGpio); +void RadioGpioSetLevel(RadioGpioPin xGpio, GPIO_PinState xState); +void SdkEvalEnterShutdown(void); +void SdkEvalExitShutdown(void); +SpiritFlagStatus SdkEvalCheckShutdown(void); +void RadioGpioInit(RadioGpioPin xGpio, RadioGpioMode xGpioMode); +void RadioGpioInterruptCmd(RadioGpioPin xGpio, uint8_t nPreemption, uint8_t nSubpriority, FunctionalState xNewState); + + +#ifdef __cplusplus +} +#endif +#endif /*__RADIO_GPIO_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.c new file mode 100644 index 000000000..96d0983d1 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.c @@ -0,0 +1,139 @@ +/** +****************************************************************************** +* @file radio_shield_config.c +* @author System Lab - NOIDA +* @version V1.0.0 +* @date 15-May-2014 +* @brief This file provides set of firmware functions to manage: +* - LEDs and push-button available on radio Shield +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "radio_shield_config.h" + +/** @addtogroup BSP +* @{ +*/ + +/** @addtogroup RADIO_SHILED +* @{ +*/ + + +/** @addtogroup RADIO_SHILED_LOW_LEVEL +* @brief This file provides set of firmware functions to manage +* manage Leds and push-button available on Radio shield. +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +GPIO_TypeDef* aLED_GPIO_PORT[RADIO_SHIELD_LEDn] = {RADIO_SHIELD_LED_GPIO_PORT}; +const uint16_t aLED_GPIO_PIN[RADIO_SHIELD_LEDn] = {RADIO_SHIELD_LED_GPIO_PIN}; + +/* Private function prototypes -----------------------------------------------*/ +void RadioShieldLedOn(Led_t Led); +void Spirit1_LED_Toggle(Led_t Led); +void Spirit1_LED_Off(Led_t Led); +void RadioShieldLedInit(Led_t Led); +void RadioShieldLedOff(Led_t Led); +void RadioShieldLedToggle(Led_t Led); + +/* Private functions ---------------------------------------------------------*/ + + +/** +* @brief Configures LED GPIO. +* @param Led: LED to be configured. +* This parameter can be one of the following values: +* @arg Led_t Led +* @retval None +*/ +void RadioShieldLedInit(Led_t Led) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Enable the GPIO_LED Clock */ + __GPIOB_CLK_ENABLE(); + + /* Configure the GPIO_LED pin */ + GPIO_InitStruct.Pin = aLED_GPIO_PIN[Led]; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_MEDIUM; + + HAL_GPIO_Init(aLED_GPIO_PORT[Led], &GPIO_InitStruct); +} + + +/** +* @brief Turns selected LED On. +* @param Led: Specifies the Led to be set on. +* This parameter can be one of following parameters: +* @arg Led_t Led +* @retval None +*/ +void RadioShieldLedOn(Led_t Led) +{ + HAL_GPIO_WritePin(aLED_GPIO_PORT[Led], aLED_GPIO_PIN[Led], GPIO_PIN_SET); +} + + +/** +* @brief Turns selected LED Off. +* @param Led: Specifies the Led to be set off. +* This parameter can be one of following parameters: +* @arg Led_t Led +* @retval None +*/ +void RadioShieldLedOff(Led_t Led) +{ + HAL_GPIO_WritePin(aLED_GPIO_PORT[Led], aLED_GPIO_PIN[Led], GPIO_PIN_RESET); +} + + +/** +* @brief Toggles the selected LED. +* @param Led: Specifies the Led to be toggled. +* This parameter can be one of following parameters: +* @arg Led_t Led +* @retval None +*/ +void RadioShieldLedToggle(Led_t Led) +{ + HAL_GPIO_TogglePin(aLED_GPIO_PORT[Led], aLED_GPIO_PIN[Led]); +} + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.h new file mode 100644 index 000000000..7fd44474a --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.h @@ -0,0 +1,114 @@ +/** +****************************************************************************** +* @file radio_shield_config.h +* @author System Lab - NOIDA +* @version V1.0.0 +* @date 15-May-2014 +* @brief This file contains definitions for: +* - LEDs and push-button available on RF shields +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_SHIELD_CONFIG_H +#define __RADIO_SHIELD_CONFIG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X-NUCLEO-IDS02Ax + * @{ + */ + +/** @addtogroup RADIO_SHILED_LOW_LEVEL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +typedef enum +{ + RADIO_SHIELD_LED = 0 +} Led_t; + + + +/* Exported constants --------------------------------------------------------*/ + + +/* Exported macro ------------------------------------------------------------*/ + /** @addtogroup RF_SHIELD_CONFIG_LOW_LEVEL_LED + * @{ + */ +#define RADIO_SHIELD_LEDn ((uint8_t)1) + +#define RADIO_SHIELD_LED_GPIO_PIN GPIO_PIN_4 /*Rx Indicator LED*/ +#define RADIO_SHIELD_LED_GPIO_PORT GPIOB +#define RADIO_SHIELD_LED_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define RADIO_SHIELD_LED_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() + + +/* Exported Variables ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ +void RadioShieldLedInit(Led_t Led); +void RadioShieldLedOn(Led_t Led); +void RadioShieldLedOff(Led_t Led); +void RadioShieldLedToggle(Led_t Led); + + + +#ifdef __cplusplus +} +#endif + +#endif /* __RADIO_SHIELD_CONFIG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.c new file mode 100644 index 000000000..dd6c1f34b --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.c @@ -0,0 +1,482 @@ +/** +****************************************************************************** +* @file radio_spi.c +* @author System Lab - NOIDA +* @version V1.0.0 +* @date 15-May-2014 +* @brief This file provides code for the configuration of the SPI instances. +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + + +/* Includes ------------------------------------------------------------------*/ +#include "radio_spi.h" + +/** + * @addtogroup BSP + * @{ + */ + + +/** + * @addtogroup X-NUCLEO-IDS02Ax + * @{ + */ + + +/** + * @defgroup RADIO_SPI_Private_TypesDefinitions RADIO_SPI Private Types Definitions + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup RADIO_SPI_Private_Defines RADIO_SPI Private Defines + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup RADIO_SPI_Private_Macros RADIO_SPI Private Macros + * @{ + */ + +/** + * @} + */ + + +/** + * @defgroup RADIO_SPI_Private_Variables RADIO_SPI Private Variables + * @{ + */ +SPI_HandleTypeDef pSpiHandle; +uint32_t SpiTimeout = RADIO_SPI_TIMEOUT_MAX; /*Instance==RADIO_SPI) + { + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + RADIO_SPI_SCK_CLOCK_ENABLE(); + RADIO_SPI_MISO_CLOCK_ENABLE(); + RADIO_SPI_MOSI_CLOCK_ENABLE(); + + /**SPI1 GPIO Configuration */ + + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + + GPIO_InitStruct.Pin = RADIO_SPI_SCK_PIN; + HAL_GPIO_Init(RADIO_SPI_SCK_PORT, &GPIO_InitStruct); + + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + + GPIO_InitStruct.Pin = RADIO_SPI_MISO_PIN; + HAL_GPIO_Init(RADIO_SPI_MISO_PORT, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = RADIO_SPI_MOSI_PIN; + HAL_GPIO_Init(RADIO_SPI_MOSI_PORT, &GPIO_InitStruct); + + RADIO_SPI_CS_CLOCK_ENABLE(); + + /* Configure SPI pin: CS */ + GPIO_InitStruct.Pin = RADIO_SPI_CS_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(RADIO_SPI_CS_PORT, &GPIO_InitStruct); + + RADIO_SPI_CLK_ENABLE(); + } +} + +/** +* @} +*/ + + +/** + * @brief SPI Write a byte to device + * @param Value: value to be written + * @retval None + */ +static void SPI_Write(uint8_t Value) +{ + HAL_StatusTypeDef status = HAL_OK; + + while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); + status = HAL_SPI_Transmit(&pSpiHandle, (uint8_t*) &Value, 1, SpiTimeout); + + /* Check the communication status */ + if (status != HAL_OK) + { + /* Execute user timeout callback */ + SPI_Error(); + } +} + + +/** + * @brief SPI error treatment function + * @param None + * @retval None + */ +static void SPI_Error(void) +{ + /* De-initialize the SPI communication BUS */ + HAL_SPI_DeInit(&pSpiHandle); + + /* Re-Initiaize the SPI communication BUS */ + SdkEvalSpiInit(); +} + + +/** +* @brief Write single or multiple RF Transceivers register +* @param cRegAddress: base register's address to be write +* @param cNbBytes: number of registers and bytes to be write +* @param pcBuffer: pointer to the buffer of values have to be written into registers +* @retval StatusBytes +*/ +StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer) +{ + uint8_t aHeader[2] = {0}; + uint16_t tmpstatus = 0x0000; + StatusBytes *pStatus=(StatusBytes *)&tmpstatus; + + /* Built the aHeader bytes */ + aHeader[0] = WRITE_HEADER; + aHeader[1] = cRegAddress; + + SPI_ENTER_CRITICAL(); + + /* Puts the SPI chip select low to start the transaction */ + RadioSpiCSLow(); + + for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&(tmpstatus), 1, SpiTimeout); + tmpstatus = tmpstatus << 8; + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); + + /* Writes the registers according to the number of bytes */ + for (int index = 0; index < cNbBytes; index++) + { + SPI_Write(pcBuffer[index]); + } + + /* To be sure to don't rise the Chip Select before the end of last sending */ + while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); + /* Puts the SPI chip select high to end the transaction */ + RadioSpiCSHigh(); + + SPI_EXIT_CRITICAL(); + + return *pStatus; + + +} + + +/** +* @brief Read single or multiple SPIRIT1 register +* @param cRegAddress: base register's address to be read +* @param cNbBytes: number of registers and bytes to be read +* @param pcBuffer: pointer to the buffer of registers' values read +* @retval StatusBytes +*/ +StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer) +{ + uint16_t tmpstatus = 0x00; + StatusBytes *pStatus = (StatusBytes *)&tmpstatus; + + uint8_t aHeader[2] = {0}; + uint8_t dummy = 0xFF; + + /* Built the aHeader bytes */ + aHeader[0] = READ_HEADER; + aHeader[1] = cRegAddress; + + SPI_ENTER_CRITICAL(); + + /* Put the SPI chip select low to start the transaction */ + RadioSpiCSLow(); + + for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&(tmpstatus), 1, SpiTimeout); + tmpstatus = tmpstatus << 8; + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); + + for (int index = 0; index < cNbBytes; index++) + { + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&dummy, (uint8_t *)&(pcBuffer)[index], 1, SpiTimeout); + } + + /* To be sure to don't rise the Chip Select before the end of last sending */ + while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); + + /* Put the SPI chip select high to end the transaction */ + RadioSpiCSHigh(); + + SPI_EXIT_CRITICAL(); + + return *pStatus; + +} + + +/** +* @brief Send a command +* @param cCommandCode: command code to be sent +* @retval StatusBytes +*/ +StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode) +{ + uint8_t aHeader[2] = {0}; + uint16_t tmpstatus = 0x0000; + + StatusBytes *pStatus = (StatusBytes *)&tmpstatus; + + + /* Built the aHeader bytes */ + aHeader[0] = COMMAND_HEADER; + aHeader[1] = cCommandCode; + + SPI_ENTER_CRITICAL(); + + /* Puts the SPI chip select low to start the transaction */ + RadioSpiCSLow(); + + for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&tmpstatus, 1, SpiTimeout); + tmpstatus = tmpstatus<<8; + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); + + /* To be sure to don't rise the Chip Select before the end of last sending */ + while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); + + /* Puts the SPI chip select high to end the transaction */ + RadioSpiCSHigh(); + + SPI_EXIT_CRITICAL(); + + return *pStatus; + +} + + +/** +* @brief Write data into TX FIFO +* @param cNbBytes: number of bytes to be written into TX FIFO +* @param pcBuffer: pointer to data to write +* @retval StatusBytes +*/ +StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer) +{ + uint16_t tmpstatus = 0x0000; + StatusBytes *pStatus = (StatusBytes *)&tmpstatus; + + uint8_t aHeader[2] = {0}; + + /* Built the aHeader bytes */ + aHeader[0] = WRITE_HEADER; + aHeader[1] = LINEAR_FIFO_ADDRESS; + + SPI_ENTER_CRITICAL(); + + /* Put the SPI chip select low to start the transaction */ + RadioSpiCSLow(); + + for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&tmpstatus, 1, SpiTimeout); + tmpstatus = tmpstatus<<8; + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); + + /* Writes the registers according to the number of bytes */ + for (int index = 0; index < cNbBytes; index++) + { + SPI_Write(pcBuffer[index]); + } + + /* To be sure to don't rise the Chip Select before the end of last sending */ + while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); + + /* Put the SPI chip select high to end the transaction */ + RadioSpiCSHigh(); + + SPI_EXIT_CRITICAL(); + + return *pStatus; +} + +/** +* @brief Read data from RX FIFO +* @param cNbBytes: number of bytes to read from RX FIFO +* @param pcBuffer: pointer to data read from RX FIFO +* @retval StatusBytes +*/ +StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer) +{ + uint16_t tmpstatus = 0x0000; + StatusBytes *pStatus = (StatusBytes *)&tmpstatus; + + uint8_t aHeader[2]; + uint8_t dummy=0xFF; + + /* Built the aHeader bytes */ + aHeader[0]=READ_HEADER; + aHeader[1]=LINEAR_FIFO_ADDRESS; + + SPI_ENTER_CRITICAL(); + + /* Put the SPI chip select low to start the transaction */ + RadioSpiCSLow(); + + for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&tmpstatus, 1, SpiTimeout); + tmpstatus = tmpstatus<<8; + + /* Write the aHeader bytes and read the SPIRIT1 status bytes */ + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); + + for (int index = 0; index < cNbBytes; index++) + { + HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&dummy, (uint8_t *)&pcBuffer[index], 1, SpiTimeout); + } + + /* To be sure to don't rise the Chip Select before the end of last sending */ + while(__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); + + /* Put the SPI chip select high to end the transaction */ + RadioSpiCSHigh(); + + SPI_EXIT_CRITICAL(); + + return *pStatus; +} + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.h new file mode 100644 index 000000000..9073f50f6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.h @@ -0,0 +1,177 @@ +/** +****************************************************************************** +* @file radio_spi.h +* @author System Lab - NOIDA +* @version V1.0.0 +* @date 15-May-2014 +* @brief This file contains all the functions prototypes for SPI . +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RADIO_SPI_H +#define __RADIO_SPI_H +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" +#include "SPIRIT_Config.h" +#include "radio_spi.h" +/** + * @addtogroup BSP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + + +/* Exported constants --------------------------------------------------------*/ + + +/* Exported macro ------------------------------------------------------------*/ + /* Define for SPIRIT1 board */ + #if !defined (USE_SPIRIT1_DEFAULT) + #define USE_SPIRIT1_DEFAULT +#endif + +/* SPIRIT1_Spi_config */ +/* SPI1 */ +#define RADIO_SPI SPI1 +#define RADIO_SPI_CLK_ENABLE() __SPI1_CLK_ENABLE() +#define RADIO_SPI_CLK_DISABLE() __SPI1_CLK_DISABLE() + +#define RADIO_SPI_MISO_PORT GPIOA +#define RADIO_SPI_MISO_PIN GPIO_PIN_6 +#define RADIO_SPI_MISO_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() +#define RADIO_SPI_MISO_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() + +#define RADIO_SPI_MOSI_PORT GPIOA +#define RADIO_SPI_MOSI_PIN GPIO_PIN_7 +#define RADIO_SPI_MOSI_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() +#define RADIO_SPI_MOSI_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() + + + +#ifdef USE_SPIRIT1_DEFAULT + +#define RADIO_SPI_SCK_PORT GPIOB +#define RADIO_SPI_SCK_PIN GPIO_PIN_3 +#define RADIO_SPI_SCK_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() +#define RADIO_SPI_SCK_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() + + +#define RADIO_SPI_CS_PORT GPIOB +#define RADIO_SPI_CS_PIN GPIO_PIN_6 +#define RADIO_SPI_CS_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() +#define RADIO_SPI_CS_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() + +#else + +#define RADIO_SPI_SCK_PORT GPIOB +#define RADIO_SPI_SCK_PIN GPIO_PIN_3 +#define RADIO_SPI_SCK_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() +#define RADIO_SPI_SCK_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() + + +#define RADIO_SPI_CS_PORT GPIOB +#define RADIO_SPI_CS_PIN GPIO_PIN_6 +#define RADIO_SPI_CS_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() +#define RADIO_SPI_CS_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() + +#endif + +/* Maximum Timeout values for flags waiting loops. These timeouts are not based + on accurate values, they just guarantee that the application will not remain + stuck if the SPI communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...) */ +#define RADIO_SPI_TIMEOUT_MAX ((uint32_t)1000) + +/* SPIRIT1_Spi_config_Private_Defines */ +#define CS_TO_SCLK_DELAY 0x0100 +#define CLK_TO_CS_DELAY 0x0001 + +/* SPIRIT1_Spi_config_Headers */ +#define HEADER_WRITE_MASK 0x00 /*!< Write mask for header byte*/ +#define HEADER_READ_MASK 0x01 /*!< Read mask for header byte*/ +#define HEADER_ADDRESS_MASK 0x00 /*!< Address mask for header byte*/ +#define HEADER_COMMAND_MASK 0x80 /*!< Command mask for header byte*/ + +#define LINEAR_FIFO_ADDRESS 0xFF /*!< Linear FIFO address*/ + +/* SPIRIT1_Spi_config_Private_FunctionPrototypes */ +#define SPI_ENTER_CRITICAL() __disable_irq() +#define SPI_EXIT_CRITICAL() __enable_irq() + +/* SPIRIT1_Spi_config_Private_Functions */ +#define RadioSpiCSLow() HAL_GPIO_WritePin(RADIO_SPI_CS_PORT, RADIO_SPI_CS_PIN, GPIO_PIN_RESET) +#define RadioSpiCSHigh() HAL_GPIO_WritePin(RADIO_SPI_CS_PORT, RADIO_SPI_CS_PIN, GPIO_PIN_SET) + +/* SPIRIT1_Spi_config_Private_Macros */ +#define BUILT_HEADER(add_comm, w_r) (add_comm | w_r) /*!< macro to build the header byte*/ +#define WRITE_HEADER BUILT_HEADER(HEADER_ADDRESS_MASK, HEADER_WRITE_MASK) /*!< macro to build the write + header byte*/ +#define READ_HEADER BUILT_HEADER(HEADER_ADDRESS_MASK, HEADER_READ_MASK) /*!< macro to build the read + header byte*/ +#define COMMAND_HEADER BUILT_HEADER(HEADER_COMMAND_MASK, HEADER_WRITE_MASK) /*!< macro to build the command + header byte*/ + + + +/* Exported Variables --------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ +void SdkEvalSpiInit(void); +void SpiCSGpioSetLevel(GPIO_PinState xState); +StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); +StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); +StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode); +StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer); +StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer); + + +#ifdef __cplusplus +} +#endif +#endif /*__RADIO_SPI_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/readme.txt b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/readme.txt new file mode 100644 index 000000000..00b9b3591 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/readme.txt @@ -0,0 +1,50 @@ +/** + @verbatim + ******************** (C) COPYRIGHT 2014 STMicroelectronics ******************* + * @file readme.txt + * @author System LAB - NOIDA + * @version V1.0.0 + * @date 22-June-2014 + * @brief Description of the X-NUCLEO-IDS02Ax + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + * + ****************************************************************************** + @endverbatim + +@par Description + +This directory provides source files for SPIRIT1 nucleo shield BSP. + +This BSP supports: + + - X-NUCLEO-IDS02A3 (SPIRIT1-433MHz) + - X-NUCLEO-IDS02A4 (SPIRIT1-868MHz) + - X-NUCLEO-IDS02A5 (SPIRIT1-915MHz) + + + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/Release_Notes.html new file mode 100644 index 000000000..6d5847de6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/Release_Notes.html @@ -0,0 +1,221 @@ + + + + + +Release Notes for STM32 BlueEnergy Library + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
+

Back to Release page

+
+

Release Notes for X-NUCLEO-IKS01A1 STM32 Expansion Board

+

Copyright +2015 STMicroelectronics

+

+
+

 

+ + + + + + +
+ + +

Update History

+ + +

V1.3.0 +/ 28-May-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add support for NUCLEO-L152RE +
    • +
  • Add output data rate and full scale settings APIs for IMU 6-axis components +
    • +
  • Add BSP_IMU_6AXES_X_GetAxes, BSP_IMU_6AXES_G_GetAxes and BSP_MAGNETO_M_GetAxes APIs +
    • +
+ +

V1.2.0 +/ 11-February-2015

+

Main +Changes

+ + + + + + + + + +
    +
  • Add support for LPS25HB sensor via DIL24 interface +
    • +
  • Add auto-discovery of components attached via DIL24 interface +
    • +
  • Add extended features support for the components at BSP/driver level +
    • +
  • Add support for free fall detection feature for LSM6DS3 sensor +
    • +
+ +

V1.1.0 +/ 12-December-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • Add support for LSM6DS3 sensor via DIL24 interface +
    • +
  • Add error control in BSP and Components API +
    • +
+ +

V1.0.0 +/ 10-September-2014

+

Main +Changes

+ + + + + + + + + +
    +
  • First +official release
    • +
+ + +

License
+

+ + +Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

+ + +
+ http://www.st.com/software_license_agreement_liberty_v2


+ +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + + + + + +

+ +
+
+

For +complete documentation on STM32 STM BlueNRG +visit www.st.com/BlueNRG

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1.c new file mode 100644 index 000000000..7c4a873e1 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1.c @@ -0,0 +1,872 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1.c + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file provides X_NUCLEO_IKS01A1 MEMS shield board specific functions + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "x_nucleo_iks01a1.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @defgroup X_NUCLEO_IKS01A1_Private_Defines X_NUCLEO_IKS01A1_Private_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_Private_Variables X_NUCLEO_IKS01A1_Private_Variables + * @{ + */ + +uint32_t I2C_EXPBD_Timeout = NUCLEO_I2C_EXPBD_TIMEOUT_MAX; /*
© COPYRIGHT(c) 2015 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __X_NUCLEO_IKS01A1_H +#define __X_NUCLEO_IKS01A1_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#ifdef USE_STM32F4XX_NUCLEO +#include "stm32f4xx_hal.h" +#endif + +#ifdef USE_STM32L0XX_NUCLEO +#include "stm32l0xx_hal.h" +#endif + +#ifdef USE_STM32L1XX_NUCLEO +#include "stm32l1xx_hal.h" +#endif + +#include "hum_temp.h" +#include "imu_6axes.h" +#include "magneto.h" +#include "pressure.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @defgroup X_NUCLEO_IKS01A1_Exported_Types X_NUCLEO_IKS01A1_Exported_Types + * @{ + */ +/** + * @brief Axes raw structure definition + */ +typedef struct +{ + int16_t AXIS_X; + int16_t AXIS_Y; + int16_t AXIS_Z; +} AxesRaw_TypeDef; + +/** + * @brief Axes raw structure definition + */ +typedef struct +{ + int32_t AXIS_X; + int32_t AXIS_Y; + int32_t AXIS_Z; +} Axes_TypeDef; + +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_Exported_Defines X_NUCLEO_IKS01A1_Exported_Defines + * @{ + */ + +/* I2C clock speed configuration (in Hz) */ +#if (defined (USE_STM32F4XX_NUCLEO)) +#define NUCLEO_I2C_EXPBD_SPEED 400000 +#endif /* USE_STM32F4XX_NUCLEO */ + +/* Timing samples for L0 with SYSCLK 32MHz set in SystemClock_Config() */ +#if (defined (USE_STM32L0XX_NUCLEO)) +#define NUCLEO_I2C_EXPBD_TIMING_100KHZ 0x10A13E56 /* Analog Filter ON, Rise Time 400ns, Fall Time 100ns */ +#define NUCLEO_I2C_EXPBD_TIMING_400KHZ 0x00B1112E /* Analog Filter ON, Rise Time 250ns, Fall Time 100ns */ +#endif /* USE_STM32L0XX_NUCLEO */ + +#if (defined (USE_STM32L1XX_NUCLEO)) +#define NUCLEO_I2C_EXPBD_SPEED 100000 +#endif /* USE_STM32L1XX_NUCLEO */ + +/* I2C peripheral configuration defines */ +#define NUCLEO_I2C_EXPBD I2C1 +#define NUCLEO_I2C_EXPBD_CLK_ENABLE() __I2C1_CLK_ENABLE() +#define NUCLEO_I2C_EXPBD_SCL_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define NUCLEO_I2C_EXPBD_SCL_SDA_AF GPIO_AF4_I2C1 +#define NUCLEO_I2C_EXPBD_SCL_SDA_GPIO_PORT GPIOB +#define NUCLEO_I2C_EXPBD_SCL_PIN GPIO_PIN_8 +#define NUCLEO_I2C_EXPBD_SDA_PIN GPIO_PIN_9 + +#define NUCLEO_I2C_EXPBD_FORCE_RESET() __I2C1_FORCE_RESET() +#define NUCLEO_I2C_EXPBD_RELEASE_RESET() __I2C1_RELEASE_RESET() + +/* I2C interrupt requests */ +#if ((defined (USE_STM32F4XX_NUCLEO)) || (defined (USE_STM32L1XX_NUCLEO))) +#define NUCLEO_I2C_EXPBD_EV_IRQn I2C1_EV_IRQn +#define NUCLEO_I2C_EXPBD_ER_IRQn I2C1_ER_IRQn +#endif + +#if (defined (USE_STM32L0XX_NUCLEO)) +#define NUCLEO_I2C_EXPBD_EV_IRQn I2C1_IRQn +#endif + +/* Maximum Timeout values for flags waiting loops. These timeouts are not based + on accurate values, they just guarantee that the application will not remain + stuck if the SPI communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...). */ +#define NUCLEO_I2C_EXPBD_TIMEOUT_MAX 0x1000 /*
© COPYRIGHT(c) 2015 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "x_nucleo_iks01a1_hum_temp.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_HUM_TEMP + * @{ + */ + + +/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Private_Defines X_NUCLEO_IKS01A1_HUM_TEMP_Private_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif +/** + * @} + */ + + +/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Private_Variables X_NUCLEO_IKS01A1_HUM_TEMP_Private_Variables + * @{ + */ +static HUM_TEMP_DrvTypeDef *Hum_tempDrv = NULL; +static uint8_t HumTempInitialized = 0; +/** + * @} + */ + + +/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions + * @{ + */ + +/** + * @brief Initialize the humidity and temperature sensor + * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise + */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Init(void) +{ + uint8_t ht_id = 0; + HUM_TEMP_InitTypeDef InitStructure; + + if(!HumTempInitialized) + { + /* Initialize the hum_temp driver structure */ + Hum_tempDrv = &Hts221Drv; + + /* Configure sensor */ + InitStructure.OutputDataRate = HTS221_ODR_12_5Hz; + + /* Hts221 Init */ + if ( Hum_tempDrv->Init == NULL ) + { + Hum_tempDrv = NULL; + return HUM_TEMP_ERROR; + } + + if(Hum_tempDrv->Init(&InitStructure) != HUM_TEMP_OK) + { + Hum_tempDrv = NULL; + return HUM_TEMP_ERROR; + } + + if ( Hum_tempDrv->ReadID == NULL ) + { + Hum_tempDrv = NULL; + return HUM_TEMP_ERROR; + } + + if(Hum_tempDrv->ReadID(&ht_id) != HUM_TEMP_OK) + { + Hum_tempDrv = NULL; + return HUM_TEMP_ERROR; + } + + if(ht_id == I_AM_HTS221) + { + Hum_tempDrv->extData = (HUM_TEMP_DrvExtTypeDef *)&Hts221Drv_ext; + HumTempInitialized = 1; + } + } + + return HUM_TEMP_OK; +} + +/** + * @brief Check if the humidity and temperature sensor is initialized + * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized + */ +uint8_t BSP_HUM_TEMP_isInitialized(void) +{ + return HumTempInitialized; +} + +/** + * @brief Read the ID of the humidity and temperature component + * @param ht_id the pointer where the who_am_i of the device is stored + * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise + */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_ReadID(uint8_t *ht_id) +{ + if ( Hum_tempDrv->ReadID == NULL ) + { + return HUM_TEMP_ERROR; + } + + return Hum_tempDrv->ReadID(ht_id); +} + + +/** + * @brief Check the ID of the humidity and temperature sensor + * @retval HUM_TEMP_OK if the ID matches, HUM_TEMP_ERROR if the ID does not match or error occurs + */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_CheckID(void) +{ + uint8_t ht_id; + + if(BSP_HUM_TEMP_ReadID(&ht_id) != HUM_TEMP_OK) + { + return HUM_TEMP_ERROR; + } + + if(ht_id == I_AM_HTS221) + { + return HUM_TEMP_OK; + } + else + { + return HUM_TEMP_ERROR; + } +} + + +/** + * @brief Reboot memory content of humidity and temperature sensor + * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise + */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Reset(void) +{ + if ( Hum_tempDrv->Reset == NULL ) + { + return HUM_TEMP_ERROR; + } + + return Hum_tempDrv->Reset(); +} + + +/** + * @brief Power off the humidity and temperature sensor + * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise + */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_PowerOFF() +{ + if ( Hum_tempDrv->PowerOFF == NULL ) + { + return HUM_TEMP_ERROR; + } + + return Hum_tempDrv->PowerOFF(); +} + + +/** + * @brief Get the humidity value + * @param pfData the pointer to floating data + * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise + */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetHumidity(float* pfData) +{ + if ( Hum_tempDrv->GetHumidity == NULL ) + { + return HUM_TEMP_ERROR; + } + + return Hum_tempDrv->GetHumidity(pfData); +} + +/** + * @brief Get the temperature value + * @param pfData the pointer to floating data + * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise + */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetTemperature(float* pfData) +{ + if ( Hum_tempDrv->GetTemperature == NULL ) + { + return HUM_TEMP_ERROR; + } + + return Hum_tempDrv->GetTemperature(pfData); +} + +/** + * @brief Get component type currently used + * @retval HUM_TEMP_NONE_COMPONENT if none component is currently used, the component unique id otherwise + */ +HUM_TEMP_ComponentTypeDef BSP_HUM_TEMP_GetComponentType( void ) +{ + if( Hum_tempDrv == NULL ) + { + return HUM_TEMP_NONE_COMPONENT; + } + + if( Hum_tempDrv == &Hts221Drv ) + { + return HUM_TEMP_HTS221_COMPONENT; + } + + return HUM_TEMP_NONE_COMPONENT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_hum_temp.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_hum_temp.h new file mode 100644 index 000000000..311cde9d9 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_hum_temp.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1_hum_temp.h + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file contains definitions for x_nucleo_iks01a1_hum_temp.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __X_NUCLEO_IKS01A1_HUM_TEMP_H +#define __X_NUCLEO_IKS01A1_HUM_TEMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "x_nucleo_iks01a1.h" +/* Include HUM_TEMP sensor component driver */ +#include "hts221.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_HUM_TEMP + * @{ + */ + + +/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions + * @{ + */ +/* Sensor Configuration Functions */ +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Init(void); +uint8_t BSP_HUM_TEMP_isInitialized(void); +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_ReadID(uint8_t *); +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_CheckID(void); +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Reset(void); +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_PowerOFF(void); +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetHumidity(float* pfData); +HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetTemperature(float* pfData); +HUM_TEMP_ComponentTypeDef BSP_HUM_TEMP_GetComponentType(void); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __X_NUCLEO_IKS01A1_HUM_TEMP_H */ + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.c new file mode 100644 index 000000000..b6d711da4 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.c @@ -0,0 +1,599 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1_imu_6axes.c + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file provides a set of functions needed to manage the lsm6ds0 and lsm6ds3 sensors. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "x_nucleo_iks01a1_imu_6axes.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_IMU_6AXES + * @{ + */ + +/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Private_Defines X_NUCLEO_IKS01A1_IMU_6AXES_Private_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Private_Variables X_NUCLEO_IKS01A1_IMU_6AXES_Private_Variables + * @{ + */ +static IMU_6AXES_DrvTypeDef *Imu6AxesDrv = NULL; +static uint8_t Imu6AxesInitialized = 0; +static uint8_t imu_6axes_sensor_type = 1; /* 1 activates LSM6DS3, 0 activates LSM6DS0 */ + +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions + * @{ + */ + +/** + * @brief Initialize the IMU 6 axes sensor + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Init(void) +{ + IMU_6AXES_InitTypeDef InitStructure; + uint8_t xg_id = 0; + int done = 0; + + if(!Imu6AxesInitialized) + { + do + { + switch(imu_6axes_sensor_type) + { + case 1: /* Try to initialized LSM6DS3 */ + { + /* Initialize the six axes driver structure */ + Imu6AxesDrv = &LSM6DS3Drv; + + /* Configure sensor */ + InitStructure.G_FullScale = 2000.0f; /* 2000DPS */ + InitStructure.G_OutputDataRate = 104.0f; /* 104HZ */ + InitStructure.G_X_Axis = 1; /* Enable */ + InitStructure.G_Y_Axis = 1; /* Enable */ + InitStructure.G_Z_Axis = 1; /* Enable */ + + InitStructure.X_FullScale = 2.0f; /* 2G */ + InitStructure.X_OutputDataRate = 104.0f; /* 104HZ */ + InitStructure.X_X_Axis = 1; /* Enable */ + InitStructure.X_Y_Axis = 1; /* Enable */ + InitStructure.X_Z_Axis = 1; /* Enable */ + + if( Imu6AxesDrv->Init == NULL ) + { + Imu6AxesDrv = NULL; + imu_6axes_sensor_type--; + break; + } + + if( Imu6AxesDrv->Init(&InitStructure) != IMU_6AXES_OK) + { + Imu6AxesDrv = NULL; + imu_6axes_sensor_type--; + break; + } + + if ( Imu6AxesDrv->Read_XG_ID == NULL ) + { + Imu6AxesDrv = NULL; + imu_6axes_sensor_type--; + break; + } + + if(Imu6AxesDrv->Read_XG_ID(&xg_id) != IMU_6AXES_OK) + { + Imu6AxesDrv = NULL; + imu_6axes_sensor_type--; + break; + } + + if(xg_id == I_AM_LSM6DS3_XG) + { + Imu6AxesDrv->extData = (IMU_6AXES_DrvExtTypeDef *)&LSM6DS3Drv_ext; + Imu6AxesInitialized = 1; + done = 1; + break; + } + else + { + Imu6AxesDrv = NULL; + imu_6axes_sensor_type--; + break; + } + } + case 0: /* Try to initialized LSM6DS0 */ + default: + { + imu_6axes_sensor_type = 0; + /* Initialize the six axes driver structure */ + Imu6AxesDrv = &LSM6DS0Drv; + + /* Configure sensor */ + InitStructure.G_FullScale = 2000.0f; /* 2000DPS */ + InitStructure.G_OutputDataRate = 119.0f; /* 119HZ */ + InitStructure.G_X_Axis = 1; /* Enable */ + InitStructure.G_Y_Axis = 1; /* Enable */ + InitStructure.G_Z_Axis = 1; /* Enable */ + + InitStructure.X_FullScale = 2.0f; /* 2G */ + InitStructure.X_OutputDataRate = 119.0f; /* 119HZ */ + InitStructure.X_X_Axis = 1; /* Enable */ + InitStructure.X_Y_Axis = 1; /* Enable */ + InitStructure.X_Z_Axis = 1; /* Enable */ + + if( Imu6AxesDrv->Init == NULL ) + { + Imu6AxesDrv = NULL; + return IMU_6AXES_ERROR; + } + + if( Imu6AxesDrv->Init(&InitStructure) != IMU_6AXES_OK) + { + Imu6AxesDrv = NULL; + return IMU_6AXES_ERROR; + } + + if ( Imu6AxesDrv->Read_XG_ID == NULL ) + { + Imu6AxesDrv = NULL; + return IMU_6AXES_ERROR; + } + + if(Imu6AxesDrv->Read_XG_ID(&xg_id) != IMU_6AXES_OK) + { + Imu6AxesDrv = NULL; + return IMU_6AXES_ERROR; + } + + if(xg_id == I_AM_LSM6DS0_XG) + { + Imu6AxesDrv->extData = (IMU_6AXES_DrvExtTypeDef *)&LSM6DS0Drv_ext; + Imu6AxesInitialized = 1; + done = 1; + break; + } + } + } + } + while(!done); + } + + return IMU_6AXES_OK; +} + +/** + * @brief Check if the IMU 6 axes sensor is initialized + * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized + */ +uint8_t BSP_IMU_6AXES_isInitialized(void) +{ + return Imu6AxesInitialized; +} + + +/** + * @brief Read the ID of the IMU 6 axes sensor + * @param xg_id the pointer where the who_am_i of the device is stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Read_XG_ID(uint8_t *xg_id) +{ + if ( Imu6AxesDrv->Read_XG_ID == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Read_XG_ID(xg_id); +} + + +/** + * @brief Check the ID of the IMU 6 axes sensor + * @retval IMU_6AXES_OK if the ID matches, IMU_6AXES_ERROR if the ID does not match or error occurs + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Check_XG_ID(void) +{ + uint8_t xg_id; + + if(BSP_IMU_6AXES_Read_XG_ID(&xg_id) != IMU_6AXES_OK) + { + return IMU_6AXES_ERROR; + } + + switch(imu_6axes_sensor_type) + { + case 1: + { + if(xg_id == I_AM_LSM6DS3_XG) + { + return IMU_6AXES_OK; + } + else + { + return IMU_6AXES_ERROR; + } + } + case 0: + default: + { + if(xg_id == I_AM_LSM6DS0_XG) + { + return IMU_6AXES_OK; + } + else + { + return IMU_6AXES_ERROR; + } + } + } +} + +/** + * @brief Get the accelerometer axes of the IMU 6 axes sensor + * @param pData the pointer where the output data are stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxes(Axes_TypeDef *pData) +{ + if ( Imu6AxesDrv->Get_X_Axes == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_X_Axes((int32_t *)pData); +} + +/** + * @brief Get the accelerometer raw axes of the IMU 6 axes sensor + * @param pData the pointer where the output data are stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxesRaw(AxesRaw_TypeDef *pData) +{ + if ( Imu6AxesDrv->Get_X_AxesRaw == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_X_AxesRaw((int16_t *)pData); +} + +/** + * @brief Get the gyroscope axes of the IMU 6 axes sensor + * @param pData the pointer where the output data are stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxes(Axes_TypeDef *pData) +{ + if ( Imu6AxesDrv->Get_G_Axes == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_G_Axes((int32_t *)pData); +} + +/** + * @brief Get the gyroscope raw axes of the IMU 6 axes sensor + * @param pData the pointer where the output data are stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxesRaw(AxesRaw_TypeDef *pData) +{ + if ( Imu6AxesDrv->Get_G_AxesRaw == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_G_AxesRaw((int16_t *)pData); +} + +/** + * @brief Get the accelerometer output data rate + * @param odr the pointer where the accelerometer output data rate is stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_ODR(float *odr) +{ + if( Imu6AxesDrv->Get_X_ODR == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_X_ODR( odr ); +} + +/** + * @brief Set the accelerometer output data rate + * @param odr the accelerometer output data rate to be set + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_ODR(float odr) +{ + if( Imu6AxesDrv->Set_X_ODR == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Set_X_ODR( odr ); +} + +/** + * @brief Get accelerometer sensitivity + * @param pfData the pointer where accelerometer sensitivity is stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetSensitivity( float *pfData ) +{ + if( Imu6AxesDrv->Get_X_Sensitivity == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_X_Sensitivity( pfData ); +} + +/** + * @brief Get the accelerometer full scale + * @param fullScale the pointer where the accelerometer full scale is stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_FS(float *fullScale) +{ + if( Imu6AxesDrv->Get_X_FS == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_X_FS( fullScale ); +} + +/** + * @brief Set the accelerometer full scale + * @param fullScale the accelerometer full scale to be set + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_FS(float fullScale) +{ + if( Imu6AxesDrv->Set_X_FS == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Set_X_FS( fullScale ); +} + +/** + * @brief Get the gyroscope output data rate + * @param odr the pointer where the gyroscope output data rate is stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_ODR(float *odr) +{ + if( Imu6AxesDrv->Get_G_ODR == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_G_ODR( odr ); +} + +/** + * @brief Set the gyroscope output data rate + * @param odr the gyroscope output data rate to be set + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_ODR(float odr) +{ + if( Imu6AxesDrv->Set_G_ODR == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Set_G_ODR( odr ); +} + +/** + * @brief Get gyroscope sensitivity + * @param pfData the pointer where the gyroscope sensitivity is stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetSensitivity( float *pfData ) +{ + if( Imu6AxesDrv->Get_G_Sensitivity == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_G_Sensitivity( pfData ); +} + +/** + * @brief Get the gyroscope full scale + * @param fullScale the pointer where the gyroscope full scale is stored + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_FS(float *fullScale) +{ + if( Imu6AxesDrv->Get_G_FS == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Get_G_FS( fullScale ); +} + +/** + * @brief Set the gyroscope full scale + * @param fullScale the gyroscope full scale to be set + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_FS(float fullScale) +{ + if( Imu6AxesDrv->Set_G_FS == NULL ) + { + return IMU_6AXES_ERROR; + } + + return Imu6AxesDrv->Set_G_FS( fullScale ); +} + +/** + * @brief Get component type currently used + * @retval IMU_6AXES_NONE_COMPONENT if none component is currently used, the component unique id otherwise + */ +IMU_6AXES_ComponentTypeDef BSP_IMU_6AXES_GetComponentType( void ) +{ + if( Imu6AxesDrv == NULL ) + { + return IMU_6AXES_NONE_COMPONENT; + } + + if( Imu6AxesDrv == &LSM6DS0Drv ) + { + return IMU_6AXES_LSM6DS0_COMPONENT; + } + + if( Imu6AxesDrv == &LSM6DS3Drv ) + { + return IMU_6AXES_LSM6DS3_DIL24_COMPONENT; + } + + return IMU_6AXES_NONE_COMPONENT; +} + +/** + * @brief Enable free fall detection (available only for LSM6DS3 sensor) + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_NOT_IMPLEMENTED if the feature is not supported, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Enable_Free_Fall_Detection_Ext(void) +{ + /* At the moment this feature is only implemented for LSM6DS3 */ + if( Imu6AxesDrv->extData == NULL || Imu6AxesDrv->extData->id != IMU_6AXES_LSM6DS3_DIL24_COMPONENT + || Imu6AxesDrv->extData->pData == NULL) + { + return IMU_6AXES_NOT_IMPLEMENTED; + } + + if(((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Enable_Free_Fall_Detection == NULL) + { + return IMU_6AXES_NOT_IMPLEMENTED; + } + + return ((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Enable_Free_Fall_Detection(); +} + +/** + * @brief Disable free fall detection (available only for LSM6DS3 sensor) + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_NOT_IMPLEMENTED if the feature is not supported, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Disable_Free_Fall_Detection_Ext(void) +{ + /* At the moment this feature is only implemented for LSM6DS3 */ + if( Imu6AxesDrv->extData == NULL || Imu6AxesDrv->extData->id != IMU_6AXES_LSM6DS3_DIL24_COMPONENT + || Imu6AxesDrv->extData->pData == NULL) + { + return IMU_6AXES_NOT_IMPLEMENTED; + } + + if(((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Disable_Free_Fall_Detection == NULL) + { + return IMU_6AXES_NOT_IMPLEMENTED; + } + + return ((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Disable_Free_Fall_Detection(); +} + +/** + * @brief Get status of free fall detection (available only for LSM6DS3 sensor) + * @param status the pointer where the status of free fall detection is stored; 0 means no detection, 1 means detection happened + * @retval IMU_6AXES_OK in case of success, IMU_6AXES_NOT_IMPLEMENTED if the feature is not supported, IMU_6AXES_ERROR otherwise + */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Get_Status_Free_Fall_Detection_Ext(uint8_t *status) +{ + /* At the moment this feature is only implemented for LSM6DS3 */ + if( Imu6AxesDrv->extData == NULL || Imu6AxesDrv->extData->id != IMU_6AXES_LSM6DS3_DIL24_COMPONENT + || Imu6AxesDrv->extData->pData == NULL) + { + return IMU_6AXES_NOT_IMPLEMENTED; + } + + if(((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Get_Status_Free_Fall_Detection == NULL) + { + return IMU_6AXES_NOT_IMPLEMENTED; + } + + if(status == NULL) + { + return IMU_6AXES_ERROR; + } + + return ((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Get_Status_Free_Fall_Detection(status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.h new file mode 100644 index 000000000..d7a211da7 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.h @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1_imu_6axes.h + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file contains definitions for the x_nucleo_iks01a1_imu_6axes.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __X_NUCLEO_IKS01A1_IMU_6AXES_H +#define __X_NUCLEO_IKS01A1_IMU_6AXES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "x_nucleo_iks01a1.h" +/* Include nine axes sensor component driver */ +#include "lsm6ds3.h" +#include "lsm6ds0.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_IMU_6AXES + * @{ + */ + + +/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions + * @{ + */ + +/* Sensor Configuration Functions */ +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Init(void); +uint8_t BSP_IMU_6AXES_isInitialized(void); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Read_XG_ID(uint8_t *); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Check_XG_ID(void); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxes(Axes_TypeDef *pData); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxesRaw(AxesRaw_TypeDef *pData); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxes(Axes_TypeDef *pData); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxesRaw(AxesRaw_TypeDef *pData); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_ODR(float *odr); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_ODR(float odr); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetSensitivity(float *pfData); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_FS(float *fullScale); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_FS(float fullScale); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_ODR(float *odr); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_ODR(float odr); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetSensitivity(float *pfData); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_FS(float *fullScale); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_FS(float fullScale); +IMU_6AXES_ComponentTypeDef BSP_IMU_6AXES_GetComponentType(void); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Enable_Free_Fall_Detection_Ext(void); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Disable_Free_Fall_Detection_Ext(void); +IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Get_Status_Free_Fall_Detection_Ext(uint8_t *status); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __X_NUCLEO_IKS01A1_IMU_6AXES_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.c new file mode 100644 index 000000000..f6b7031e8 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.c @@ -0,0 +1,245 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1_magneto.c + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file provides a set of functions needed to manage the lis3mdl sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "x_nucleo_iks01a1_magneto.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_MAGNETO + * @{ + */ + +/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Private_Defines X_NUCLEO_IKS01A1_MAGNETO_Private_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Private_Variables X_NUCLEO_IKS01A1_MAGNETO_Private_Variables + * @{ + */ +static MAGNETO_DrvTypeDef *MagnetoDrv = NULL; +static uint8_t MagnetoInitialized = 0; + +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions + * @{ + */ + +/** + * @brief Initialize the magneto sensor + * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise + */ +MAGNETO_StatusTypeDef BSP_MAGNETO_Init(void) +{ + uint8_t m_id = 0; + MAGNETO_InitTypeDef InitStructure; + + if(!MagnetoInitialized) + { + /* Initialize the magneto driver structure */ + MagnetoDrv = &LIS3MDLDrv; + + /* Configure sensor */ + InitStructure.M_FullScale = LIS3MDL_M_FS_4; + InitStructure.M_OperatingMode = LIS3MDL_M_MD_CONTINUOUS; + InitStructure.M_XYOperativeMode = LIS3MDL_M_OM_HP; + InitStructure.M_OutputDataRate = LIS3MDL_M_DO_80; + + /* magneto sensor init */ + if ( MagnetoDrv->Init == NULL ) + { + MagnetoDrv = NULL; + return MAGNETO_ERROR; + } + + if(MagnetoDrv->Init(&InitStructure) != MAGNETO_OK) + { + MagnetoDrv = NULL; + return MAGNETO_ERROR; + } + + if ( MagnetoDrv->Read_M_ID == NULL ) + { + MagnetoDrv = NULL; + return MAGNETO_ERROR; + } + + if(MagnetoDrv->Read_M_ID(&m_id) != MAGNETO_OK) + { + MagnetoDrv = NULL; + return MAGNETO_ERROR; + } + + if(m_id == I_AM_LIS3MDL_M) + { + MagnetoDrv->extData = (MAGNETO_DrvExtTypeDef *)&LIS3MDLDrv_ext; + MagnetoInitialized = 1; + } + } + + return MAGNETO_OK; +} + +/** + * @brief Check if the magnetic sensor is initialized + * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized + */ +uint8_t BSP_MAGNETO_isInitialized(void) +{ + return MagnetoInitialized; +} + + +/** + * @brief Read the ID of the magnetic sensor + * @param m_id the pointer where the who_am_i of the device is stored + * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise + */ +MAGNETO_StatusTypeDef BSP_MAGNETO_Read_M_ID(uint8_t *m_id) +{ + if ( MagnetoDrv->Read_M_ID == NULL ) + { + return MAGNETO_ERROR; + } + + return MagnetoDrv->Read_M_ID(m_id); +} + + +/** + * @brief Check the ID of the magnetic sensor + * @retval MAGNETO_OK if the ID matches, MAGNETO_ERROR if the ID does not match or error occurs + */ +MAGNETO_StatusTypeDef BSP_MAGNETO_Check_M_ID(void) +{ + uint8_t m_id; + + if(BSP_MAGNETO_Read_M_ID(&m_id) != MAGNETO_OK) + { + return MAGNETO_ERROR; + } + + if(m_id == I_AM_LIS3MDL_M) + { + return MAGNETO_OK; + } + else + { + return MAGNETO_ERROR; + } +} + +/** + * @brief Get the magnetic sensor axes + * @param pData the pointer where the output data are stored + * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise + */ +MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxes(Axes_TypeDef *pData) +{ + if ( MagnetoDrv->Get_M_Axes == NULL ) + { + return MAGNETO_ERROR; + } + + return MagnetoDrv->Get_M_Axes((int32_t *)pData); +} + +/** + * @brief Get the magnetic sensor raw axes + * @param pData the pointer where the output data are stored + * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise + */ +MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxesRaw(AxesRaw_TypeDef *pData) +{ + if ( MagnetoDrv->Get_M_AxesRaw == NULL ) + { + return MAGNETO_ERROR; + } + + return MagnetoDrv->Get_M_AxesRaw((int16_t *)pData); +} + +/** + * @brief Get component type currently used + * @retval MAGNETO_NONE_COMPONENT if none component is currently used, the component unique id otherwise + */ +MAGNETO_ComponentTypeDef BSP_MAGNETO_GetComponentType( void ) +{ + if( MagnetoDrv == NULL ) + { + return MAGNETO_NONE_COMPONENT; + } + + if( MagnetoDrv == &LIS3MDLDrv ) + { + return MAGNETO_LIS3MDL_COMPONENT; + } + + return MAGNETO_NONE_COMPONENT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.h new file mode 100644 index 000000000..cfa7e3efe --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.h @@ -0,0 +1,97 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1_magneto.h + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file contains definitions for the x_nucleo_iks01a1_magneto.c + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __X_NUCLEO_IKS01A1_MAGNETO_H +#define __X_NUCLEO_IKS01A1_MAGNETO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "x_nucleo_iks01a1.h" +/* Include nine axes sensor component driver */ +#include "lis3mdl.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_MAGNETO + * @{ + */ + +/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions + * @{ + */ +/* Sensor Configuration Functions */ +MAGNETO_StatusTypeDef BSP_MAGNETO_Init(void); +uint8_t BSP_MAGNETO_isInitialized(void); +MAGNETO_StatusTypeDef BSP_MAGNETO_Read_M_ID(uint8_t *m_id); +MAGNETO_StatusTypeDef BSP_MAGNETO_Check_M_ID(void); +MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxes(Axes_TypeDef *pData); +MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxesRaw(AxesRaw_TypeDef *pData); +MAGNETO_ComponentTypeDef BSP_MAGNETO_GetComponentType(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __X_NUCLEO_IKS01A1_MAGNETO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.c new file mode 100644 index 000000000..44ff946af --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.c @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1_pressure.c + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file provides a set of functions needed to manage the lps25h and lps25hb sensors. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "x_nucleo_iks01a1_pressure.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_PRESSURE + * @{ + */ + + +/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Private_Defines X_NUCLEO_IKS01A1_PRESSURE_Private_Defines + * @{ + */ +#ifndef NULL +#define NULL (void *) 0 +#endif +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Private_Variables X_NUCLEO_IKS01A1_PRESSURE_Private_Variables + * @{ + */ +static PRESSURE_DrvTypeDef *PressureDrv = NULL; +static uint8_t PressureInitialized = 0; +static uint8_t pressure_sensor_type = 1; /* 1 activates LPS25HB, 0 activates LPS25H */ + +/** + * @} + */ + +/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions + * @{ + */ + +/** + * @brief Initialize the pressure sensor + * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise + */ +PRESSURE_StatusTypeDef BSP_PRESSURE_Init(void) +{ + uint8_t p_id = 0; + PRESSURE_InitTypeDef InitStructure; + int done = 0; + + if(!PressureInitialized) + { + do + { + switch(pressure_sensor_type) + { + case 1: + { + /* Initialize the pressure driver structure */ + PressureDrv = &LPS25HBDrv; + + /* Configure sensor */ + InitStructure.OutputDataRate = LPS25HB_ODR_1Hz; + InitStructure.BlockDataUpdate = LPS25HB_BDU_CONT; + InitStructure.DiffEnable = LPS25HB_DIFF_ENABLE; + InitStructure.SPIMode = LPS25HB_SPI_SIM_3W; + InitStructure.PressureResolution = LPS25HB_P_RES_AVG_32; + InitStructure.TemperatureResolution = LPS25HB_T_RES_AVG_16; + + /* Pressure sensor init */ + if ( PressureDrv->Init == NULL ) + { + PressureDrv = NULL; + pressure_sensor_type--; + break; + } + + if(PressureDrv->Init(&InitStructure) != PRESSURE_OK) + { + PressureDrv = NULL; + pressure_sensor_type--; + break; + } + + if ( PressureDrv->ReadID == NULL ) + { + PressureDrv = NULL; + pressure_sensor_type--; + break; + } + + if(PressureDrv->ReadID(&p_id) != PRESSURE_OK) + { + PressureDrv = NULL; + pressure_sensor_type--; + break; + } + + if(p_id == I_AM_LPS25HB) + { + PressureDrv->extData = (PRESSURE_DrvExtTypeDef *)&LPS25HBDrv_ext; + PressureInitialized = 1; + done = 1; + break; + } + else + { + PressureDrv = NULL; + pressure_sensor_type--; + break; + } + } + case 0: + default: + { + /* Initialize the pressure driver structure */ + PressureDrv = &LPS25HDrv; + + /* Configure sensor */ + InitStructure.OutputDataRate = LPS25H_ODR_1Hz; + InitStructure.BlockDataUpdate = LPS25H_BDU_CONT; + InitStructure.DiffEnable = LPS25H_DIFF_ENABLE; + InitStructure.SPIMode = LPS25H_SPI_SIM_3W; + InitStructure.PressureResolution = LPS25H_P_RES_AVG_32; + InitStructure.TemperatureResolution = LPS25H_T_RES_AVG_16; + + /* Pressure sensor init */ + if ( PressureDrv->Init == NULL ) + { + PressureDrv = NULL; + return PRESSURE_ERROR; + } + + if(PressureDrv->Init(&InitStructure) != PRESSURE_OK) + { + PressureDrv = NULL; + return PRESSURE_ERROR; + } + + if ( PressureDrv->ReadID == NULL ) + { + PressureDrv = NULL; + return PRESSURE_ERROR; + } + + if(PressureDrv->ReadID(&p_id) != PRESSURE_OK) + { + PressureDrv = NULL; + return PRESSURE_ERROR; + } + + if(p_id == I_AM_LPS25H) + { + PressureDrv->extData = (PRESSURE_DrvExtTypeDef *)&LPS25HDrv_ext; + PressureInitialized = 1; + done = 1; + break; + } + } + } + } + while(!done); + } + + return PRESSURE_OK; +} + +/** + * @brief Check if the pressure sensor is initialized + * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized + */ +uint8_t BSP_PRESSURE_isInitialized(void) +{ + return PressureInitialized; +} + +/** + * @brief Read the ID of the pressure sensor + * @param p_id the pointer where the who_am_i of the device is stored + * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise + */ +PRESSURE_StatusTypeDef BSP_PRESSURE_ReadID(uint8_t *p_id) +{ + if ( PressureDrv->ReadID == NULL ) + { + return PRESSURE_ERROR; + } + + return PressureDrv->ReadID(p_id); +} + + +/** + * @brief Check the ID of the pressure sensor + * @retval PRESSURE_OK if the ID matches, PRESSURE_ERROR if the ID does not match or error occurs + */ +PRESSURE_StatusTypeDef BSP_PRESSURE_CheckID(void) +{ + uint8_t p_id; + + if(BSP_PRESSURE_ReadID(&p_id) != PRESSURE_OK) + { + return PRESSURE_ERROR; + } + + switch(pressure_sensor_type) + { + case 1: + { + if(p_id == I_AM_LPS25HB) + { + return PRESSURE_OK; + } + else + { + return PRESSURE_ERROR; + } + } + case 0: + default: + { + if(p_id == I_AM_LPS25H) + { + return PRESSURE_OK; + } + else + { + return PRESSURE_ERROR; + } + } + } +} + + +/** + * @brief Reboot the memory content of the pressure sensor + * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise + */ +PRESSURE_StatusTypeDef BSP_PRESSURE_Reset(void) +{ + if ( PressureDrv->Reset == NULL ) + { + return PRESSURE_ERROR; + } + + return PressureDrv->Reset(); +} + + +/** + * @brief Get the pressure + * @param pfData the pointer where the output data are stored + * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise + */ +PRESSURE_StatusTypeDef BSP_PRESSURE_GetPressure(float* pfData) +{ + if ( PressureDrv->GetPressure == NULL ) + { + return PRESSURE_ERROR; + } + + return PressureDrv->GetPressure(pfData); +} + +/** + * @brief Get the temperature + * @param pfData the pointer where the output data are stored + * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise + */ +PRESSURE_StatusTypeDef BSP_PRESSURE_GetTemperature(float* pfData) +{ + if ( PressureDrv->GetTemperature == NULL ) + { + return PRESSURE_ERROR; + } + + return PressureDrv->GetTemperature(pfData); +} + +/** + * @brief Get component type currently used + * @retval PRESSURE_NONE_COMPONENT if none component is currently used, the component unique id otherwise + */ +PRESSURE_ComponentTypeDef BSP_PRESSURE_GetComponentType( void ) +{ + if( PressureDrv == NULL ) + { + return PRESSURE_NONE_COMPONENT; + } + + if( PressureDrv == &LPS25HDrv ) + { + return PRESSURE_LPS25H_COMPONENT; + } + + if( PressureDrv == &LPS25HBDrv ) + { + return PRESSURE_LPS25HB_DIL24_COMPONENT; + } + + return PRESSURE_NONE_COMPONENT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.h new file mode 100644 index 000000000..975020ea6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file x_nucleo_iks01a1_pressure.h + * @author CL + * @version V1.3.0 + * @date 28-May-2015 + * @brief This file contains definitions for x_nucleo_iks01a1_pressure.c + * firmware driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __X_NUCLEO_IKS01A1_PRESSURE_H +#define __X_NUCLEO_IKS01A1_PRESSURE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +//#include "x_nucleo_iks01a1.h" +/* Include Pressure sensor component driver */ +#include "lps25h.h" +#include "lps25hb.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1 + * @{ + */ + +/** @addtogroup X_NUCLEO_IKS01A1_PRESSURE + * @{ + */ + +/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions + * @{ + */ +/* Sensor Configuration Functions */ +PRESSURE_StatusTypeDef BSP_PRESSURE_Init(void); +uint8_t BSP_PRESSURE_isInitialized(void); +PRESSURE_StatusTypeDef BSP_PRESSURE_Reset(void); +PRESSURE_StatusTypeDef BSP_PRESSURE_ReadID(uint8_t *p_id); +PRESSURE_StatusTypeDef BSP_PRESSURE_CheckID(void); +PRESSURE_StatusTypeDef BSP_PRESSURE_GetPressure(float* pfData); +PRESSURE_StatusTypeDef BSP_PRESSURE_GetTemperature(float* pfData); +PRESSURE_ComponentTypeDef BSP_PRESSURE_GetComponentType(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __X_NUCLEO_IKS01A1_PRESSURE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/hw-config.h b/platform/stm32nucleo-spirit1/hw-config.h new file mode 100644 index 000000000..3a5d35243 --- /dev/null +++ b/platform/stm32nucleo-spirit1/hw-config.h @@ -0,0 +1,136 @@ + /** + ****************************************************************************** + * @file hw-config.h + * @author System LAB + * @version V1.0.0 + * @date 17-May-2015 + * @brief Header file for Hardware Configuration & Setup + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HW_CONFIG_H +#define __HW_CONFIG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l-spirit1-config.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported define -----------------------------------------------------------*/ +#define UART_RxBufferSize 512 + + +#define I2Cx I2C1 +#define I2Cx_CLK_ENABLE() __I2C1_CLK_ENABLE() +#define I2Cx_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define I2Cx_SCL_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() + +#define I2Cx_FORCE_RESET() __I2C1_FORCE_RESET() +#define I2Cx_RELEASE_RESET() __I2C1_RELEASE_RESET() + +/* Definition for I2Cx Pins */ +#define I2Cx_SCL_PIN GPIO_PIN_8 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SDA_PIN GPIO_PIN_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SCL_SDA_AF GPIO_AF4_I2C1 + +/* Definition for I2Cx's NVIC */ +#define I2Cx_EV_IRQn I2C1_EV_IRQn +#define I2Cx_ER_IRQn I2C1_ER_IRQn +#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler +#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler + + +#define I2Cx I2C1 +#define I2Cx_CLK_ENABLE() __I2C1_CLK_ENABLE() +#define I2Cx_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define I2Cx_SCL_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() + +#define I2Cx_FORCE_RESET() __I2C1_FORCE_RESET() +#define I2Cx_RELEASE_RESET() __I2C1_RELEASE_RESET() + +/* Definition for I2Cx Pins */ +#define I2Cx_SCL_PIN GPIO_PIN_8 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SDA_PIN GPIO_PIN_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SCL_SDA_AF GPIO_AF4_I2C1 + +/* Definition for I2Cx's NVIC */ +#define I2Cx_EV_IRQn I2C1_EV_IRQn +#define I2Cx_ER_IRQn I2C1_ER_IRQn +#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler +#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler + + + + +/* User can use this section to tailor USARTx/UARTx instance used and associated + resources */ +/* Definition for USARTx clock resources */ +#define USARTx USART2 +#define USARTx_CLK_ENABLE() __USART2_CLK_ENABLE(); +#define DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE() +#define USARTx_RX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define USARTx_TX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() + +#define USARTx_FORCE_RESET() __USART2_FORCE_RESET() +#define USARTx_RELEASE_RESET() __USART2_RELEASE_RESET() + +/* Definition for USARTx Pins */ +#define USARTx_TX_PIN GPIO_PIN_2 +#define USARTx_TX_GPIO_PORT GPIOA + +#define USARTx_RX_PIN GPIO_PIN_3 +#define USARTx_RX_GPIO_PORT GPIOA + +// /* Definition for USARTx's NVIC */ +#define USARTx_IRQn USART2_IRQn +#define USARTx_IRQHandler USART2_IRQHandler + +#define USARTx_TX_AF GPIO_AF7_USART2 +#define USARTx_RX_AF GPIO_AF7_USART2 + + + // Enalble sensor mask +#define PRESSURE_SENSOR 0x00000001 +#define TEMPERATURE_SENSOR 0x00000002 +#define HUMIDITY_SENSOR 0x00000004 +#define UV_SENSOR 0x00000008 +#define ACCELEROMETER_SENSOR 0x00000010 +#define GYROSCOPE_SENSOR 0x00000020 +#define MAGNETIC_SENSOR 0x00000040 +/* Exported functions ------------------------------------------------------- */ +/* External variables --------------------------------------------------------*/ + +#endif /*__HW_CONFIG_H*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/node-id.c b/platform/stm32nucleo-spirit1/node-id.c new file mode 100644 index 000000000..24b7d6af5 --- /dev/null +++ b/platform/stm32nucleo-spirit1/node-id.c @@ -0,0 +1,61 @@ +/** +****************************************************************************** +* @file node-id.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Source file for node Id +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include "node-id.h" +#include "contiki-conf.h" + +#include + +unsigned short node_id = 0; +unsigned char node_mac[8]; +volatile uint32_t device_id[3]; + +#define DEVICE_ID_REG0 (*((volatile uint32_t *) 0x1FF80050)) +#define DEVICE_ID_REG1 (*((volatile uint32_t *) 0x1FF80054)) +#define DEVICE_ID_REG2 (*((volatile uint32_t *) 0x1FF80064)) + +/*---------------------------------------------------------------------------*/ +void node_id_restore(void) +{ + device_id[0] = DEVICE_ID_REG0; + device_id[1] = DEVICE_ID_REG1; + device_id[2] = DEVICE_ID_REG2; + + (*(uint32_t*)node_mac)=DEVICE_ID_REG1; + (*(((uint32_t*)node_mac)+1))=DEVICE_ID_REG2+DEVICE_ID_REG0; + node_id = (unsigned short) DEVICE_ID_REG2; +} diff --git a/platform/stm32nucleo-spirit1/platform-conf.h b/platform/stm32nucleo-spirit1/platform-conf.h new file mode 100644 index 000000000..273f61fc8 --- /dev/null +++ b/platform/stm32nucleo-spirit1/platform-conf.h @@ -0,0 +1,96 @@ +/** +****************************************************************************** +* @file platform-conf.h +* @author System LAB +* @version V1.0.0 +* @date 17-May-2015 +* @brief Configuration parameters +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + +#ifndef __PLATFORM_CONF_H__ +#define __PLATFORM_CONF_H__ + +#include +#include + +#define PLATFORM_HAS_LEDS 1 +#define PLATFORM_HAS_BUTTON 1 + +#define LEDS_GREEN 1 /*Nucleo LED*/ +#define LEDS_RED 2 /*SPIRIT1 LED*/ + +#ifdef COMPILE_SENSORS +#define LEDS_CONF_ALL 1 /*Can't use SPIRIT1 LED in this case*/ +#else +#define LEDS_CONF_ALL 3 /*No sensors -> we can use SPIRIT1 LED in this case*/ +#endif /*COMPILE_SENSORS*/ + +#define F_CPU 32000000ul +#define RTIMER_ARCH_SECOND 32768 +#define PRESCALER ((F_CPU / (RTIMER_ARCH_SECOND*2))) + + +#define UART1_CONF_TX_WITH_INTERRUPT 0 +#define WITH_SERIAL_LINE_INPUT 1 +#define TELNETD_CONF_NUMLINES 6 +#define NETSTACK_CONF_RADIO spirit_radio_driver +#define NETSTACK_RADIO_MAX_PAYLOAD_LEN 96 /* spirit1-config.h */ + +/* define ticks/second for slow and fast clocks. Notice that these should be a + power of two, eg 64,128,256,512 etc, for efficiency as POT's can be optimized + well. */ + +#define CLOCK_CONF_SECOND 128 +// One tick: 62.5 ms + +#define RTIMER_CLOCK_LT(a,b) ((signed short)((a)-(b)) < 0) +typedef unsigned long clock_time_t; +typedef unsigned long long rtimer_clock_t; + +#define CC_CONF_REGISTER_ARGS 0 +#define CC_CONF_FUNCTION_POINTER_ARGS 1 +#define CC_CONF_FASTCALL +#define CC_CONF_VA_ARGS 1 +#define CC_CONF_INLINE inline + +#define CCIF +#define CLIF + +typedef uint8_t u8_t; +typedef uint16_t u16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +typedef unsigned short uip_stats_t; + +#define MULTICHAN_CONF_SET_CHANNEL(x) +#define MULTICHAN_CONF_READ_RSSI(x) 0 + +#endif /* __PLATFORM_CONF_H__ */ diff --git a/platform/stm32nucleo-spirit1/spirit1-arch.c b/platform/stm32nucleo-spirit1/spirit1-arch.c new file mode 100644 index 000000000..2d3a9218f --- /dev/null +++ b/platform/stm32nucleo-spirit1/spirit1-arch.c @@ -0,0 +1,85 @@ +/** +****************************************************************************** +* @file main.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Source file for SPIRIT1 +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" +#include "spirit1-arch.h" +#include "spirit1.h" + +extern void spirit1_interrupt_callback(void); +SpiritBool spiritdk_timer_expired = S_FALSE; +/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* use the SPI-port to acquire the status bytes from the radio. */ +#define CS_TO_SCLK_DELAY 0x0100 +extern SPI_HandleTypeDef pSpiHandle; +uint16_t +spirit1_arch_refresh_status(void) +{ + + volatile uint16_t mcstate = 0x0000; + uint8_t header[2]; + header[0]=0x01; + header[1]=MC_STATE1_BASE; + uint32_t SpiTimeout = ((uint32_t)1000); /*IDR & RADIO_SPI_CS_PIN)) +#define SPIRIT1_STATUS() (spirit1_arch_refresh_status() & SPIRIT1_STATE_STATEBITS) + +uint16_t spirit1_arch_refresh_status(void); + + + +#endif /* __SPIRIT1_ARCH_H__ */ diff --git a/platform/stm32nucleo-spirit1/spirit1-config.h b/platform/stm32nucleo-spirit1/spirit1-config.h new file mode 100644 index 000000000..a4e93f3d2 --- /dev/null +++ b/platform/stm32nucleo-spirit1/spirit1-config.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + */ +/* + * \file + * spirit1-config.h + * \author + * Marcus Lunden > + * \desc + * configuration for the Spirit1 radio transceiver + * + */ + +#ifndef __SPIRIT1_CONFIG_H__ +#define __SPIRIT1_CONFIG_H__ + +#include "radio.h" +#include "SPIRIT_Config.h" +#include "spirit1-const.h" + +#define CCA_THRESHOLD -98.0 /* dBm */ +#define XTAL_FREQUENCY 50000000 /* Hz */ +#define SPIRIT_MAX_FIFO_LEN 96 + + + +/** + * The MAX_PACKET_LEN is an arbitrary value used to define the two array + * spirit_txbuf and spirit_rxbuf. + * The SPIRIT1 supports with its packet handler a length of 65,535 bytes, + * and in direct mode (without packet handler) there is no limit of data. + */ +#define MAX_PACKET_LEN SPIRIT_MAX_FIFO_LEN + +/** + * Spirit1 IC version + */ +#define SPIRIT1_VERSION SPIRIT_VERSION_3_0 + + +#endif /* __SPIRIT1_CONFIG_H__ */ + diff --git a/platform/stm32nucleo-spirit1/spirit1-const.h b/platform/stm32nucleo-spirit1/spirit1-const.h new file mode 100644 index 000000000..a6555097c --- /dev/null +++ b/platform/stm32nucleo-spirit1/spirit1-const.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2012, Thingsquare, http://www.thingsquare.com/. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * \file + * spirit1-const.h + * \author + * Marcus Lunden > + * \desc + * Spirit1 constants + * + * + */ + +#ifndef __SPIRIT1_CONST_H__ +#define __SPIRIT1_CONST_H__ + + +/* The state bitfield and values for different states, as read from MC_STATE[1:0] registers, +which are returned on any SPI read or write operation. */ +#define SPIRIT1_STATE_STATEBITS (0x00FE) + +#define SPIRIT1_STATE_STANDBY ((0x0040)<<1) +#define SPIRIT1_STATE_SLEEP ((0x0036)<<1) +#define SPIRIT1_STATE_READY ((0x0003)<<1) +#define SPIRIT1_STATE_LOCK ((0x000F)<<1) +#define SPIRIT1_STATE_RX ((0x0033)<<1) +#define SPIRIT1_STATE_TX ((0x005F)<<1) +/* NB the below states were extracted from ST drivers, but are not specified in the datasheet */ +#define SPIRIT1_STATE_PM_SETUP ((0x003D)<<1) +#define SPIRIT1_STATE_XO_SETTLING ((0x0023)<<1) +#define SPIRIT1_STATE_SYNTH_SETUP ((0x0053)<<1) +#define SPIRIT1_STATE_PROTOCOL ((0x001F)<<1) +#define SPIRIT1_STATE_SYNTH_CALIBRATION ((0x004F)<<1) + + +/* strobe commands */ +#define SPIRIT1_STROBE_TX 0x60 +#define SPIRIT1_STROBE_RX 0x61 +#define SPIRIT1_STROBE_READY 0x62 +#define SPIRIT1_STROBE_STANDBY 0x63 +#define SPIRIT1_STROBE_SLEEP 0x64 +#define SPIRIT1_STROBE_SABORT 0x67 +#define SPIRIT1_STROBE_SRES 0x70 +#define SPIRIT1_STROBE_FRX 0x71 +#define SPIRIT1_STROBE_FTX 0x72 + + +#endif /* __SPIRIT1_CONST_H__ */ + diff --git a/platform/stm32nucleo-spirit1/spirit1.c b/platform/stm32nucleo-spirit1/spirit1.c new file mode 100644 index 000000000..e8c9abed5 --- /dev/null +++ b/platform/stm32nucleo-spirit1/spirit1.c @@ -0,0 +1,740 @@ +/** +****************************************************************************** +* @file spirit1.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Source file for SPIRIT1 +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#include "spirit1.h" +#include "spirit1-arch.h" +#include "stm32l1xx.h" +#include "contiki.h" +#include "net/mac/frame802154.h" +#include "net/netstack.h" +#include "net/packetbuf.h" +#include "net/rime/rimestats.h" +#include "spirit1-arch.h" +#include + +extern SpiritIrqs xIrqStatus; +extern volatile FlagStatus rx_timeout; +#define XXX_ACK_WORKAROUND 1 +/*---------------------------------------------------------------------------*/ +#define DEBUG 0 +#if DEBUG +#include +#define PRINTF(...) printf(__VA_ARGS__) +#else +#define PRINTF(...) +#endif + +#define BUSYWAIT_UNTIL(cond, max_time) \ + do { \ + rtimer_clock_t t0; \ + t0 = RTIMER_NOW(); \ + while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ + } while(0) + +/*---------------------------------------------------------------------------*/ +#define CLEAR_TXBUF() (spirit_txbuf[0] = 0) +#define CLEAR_RXBUF() (spirit_rxbuf[0] = 0) +#define IS_TXBUF_EMPTY() (spirit_txbuf[0] == 0) +#define IS_RXBUF_EMPTY() (spirit_rxbuf[0] == 0) +#define IS_RXBUF_FULL() (spirit_rxbuf[0] != 0) + +/* transceiver state. */ +#define ON 0 +#define OFF 1 + + +/*---------------------------------------------------------------------------*/ +static volatile unsigned int spirit_on = OFF; +static volatile uint8_t receiving_packet = 0; +/* +* The buffers which hold incoming data. +* The +1 because of the first byte, +* which will contain the length of the packet. +*/ +static uint8_t spirit_rxbuf[MAX_PACKET_LEN+1]; +static uint8_t spirit_txbuf[MAX_PACKET_LEN+1-SPIRIT_MAX_FIFO_LEN]; +void SpiritManagementSetFrequencyBase(uint32_t lFBase); + +static int just_got_an_ack = 0; /* Interrupt callback just detected an ack */ +#if NULLRDC_CONF_802154_AUTOACK +#define ACK_LEN 3 +static int wants_an_ack = 0; /* The packet sent expects an ack */ +//static int just_got_an_ack = 0; /* Interrupt callback just detected an ack */ +//#define ACKPRINTF printf +#define ACKPRINTF(...) +#endif /* NULLRDC_CONF_802154_AUTOACK */ + +/*---------------------------------------------------------------------------*/ + +static int packet_is_prepared = 0; +/*---------------------------------------------------------------------------*/ +PROCESS(spirit_radio_process, "SPIRIT radio driver"); +/*---------------------------------------------------------------------------*/ +static int spirit_radio_init(void); +static int spirit_radio_prepare(const void *payload, unsigned short payload_len); +static int spirit_radio_transmit(unsigned short payload_len); +static int spirit_radio_send(const void *data, unsigned short len); +static int spirit_radio_read(void *buf, unsigned short bufsize); +static int spirit_radio_channel_clear(void); +static int spirit_radio_receiving_packet(void); +static int spirit_radio_pending_packet(void); +static int spirit_radio_on(void); +static int spirit_radio_off(void); +/*---------------------------------------------------------------------------*/ +const struct radio_driver spirit_radio_driver = +{ + spirit_radio_init, + spirit_radio_prepare, + spirit_radio_transmit, + spirit_radio_send, + spirit_radio_read, + spirit_radio_channel_clear, + spirit_radio_receiving_packet, + spirit_radio_pending_packet, + spirit_radio_on, + spirit_radio_off, +}; +/*---------------------------------------------------------------------------*/ +/* convienience macro for reading the MC_STATE[1] register from Spirit1, to be used like eg + if(SPIRIT1_STATUS() == SPIRIT1_STATE_READY) { + } + or + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, RTIMER_SECOND/1000); +*/ + +/*---------------------------------------------------------------------------*/ +void +spirit1_printstatus(void) +{ + int s = SPIRIT1_STATUS(); + if(s == SPIRIT1_STATE_STANDBY) { + printf("spirit1: SPIRIT1_STATE_STANDBY\n"); + } else if(s == SPIRIT1_STATE_READY) { + printf("spirit1: SPIRIT1_STATE_READY\n"); + } else if(s == SPIRIT1_STATE_TX) { + printf("spirit1: SPIRIT1_STATE_TX\n"); + } else if(s == SPIRIT1_STATE_RX) { + printf("spirit1: SPIRIT1_STATE_RX\n"); + } else { + printf("spirit1: status: %d\n", s); + } +} +/*---------------------------------------------------------------------------*/ +/* Strobe a command. The rationale for this is to clean up the messy legacy code. */ +static void +spirit1_strobe(uint8_t s) +{ + SpiritCmdStrobeCommand(s); +} +/*---------------------------------------------------------------------------*/ +/** +* @brief Puts the SPIRIT1 in READY state. +* @param None +* @retval None +*/ +void SpiritSetReadyState(void) +{ + PRINTF("READY IN\n"); + + SpiritIrqClearStatus(); + IRQ_DISABLE(); + + if(SPIRIT1_STATUS() == SPIRIT1_STATE_STANDBY) { + spirit1_strobe(SPIRIT1_STROBE_READY); +/* SpiritCmdStrobeReady();*/ + } else if(SPIRIT1_STATUS() == SPIRIT1_STATE_RX) { + spirit1_strobe(SPIRIT1_STROBE_SABORT); +/* SpiritCmdStrobeSabort();*/ + SpiritIrqClearStatus(); + } + + IRQ_ENABLE(); + + PRINTF("READY OUT\n"); +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_init(void) +{ + + PRINTF("RADIO INIT IN\n"); + + SpiritSpiInit(); + + /* Configure radio shut-down (SDN) pin and activate radio */ + RadioGpioInit(RADIO_GPIO_SDN, RADIO_MODE_GPIO_OUT); + + /* Configures the SPIRIT1 library */ + SpiritRadioSetXtalFrequency(XTAL_FREQUENCY); + SpiritManagementSetFrequencyBase(XTAL_FREQUENCY); + + /* wake up to READY state */ + /* weirdly enough, this *should* actually *set* the pin, not clear it! The pins is declared as GPIO_pin13 == 0x2000 */ + RADIO_GPIO_SDN_PORT->BSRR = RADIO_GPIO_SDN_PIN; + HAL_GPIO_WritePin(RADIO_GPIO_SDN_PORT, RADIO_GPIO_SDN_PIN,GPIO_PIN_RESET); + + /* wait minimum 1.5 ms to allow SPIRIT1 a proper boot-up sequence */ + BUSYWAIT_UNTIL(0, 3 * RTIMER_SECOND/2000); + + /* Soft reset of core */ + spirit1_strobe(SPIRIT1_STROBE_SRES); + + /* Configures the SPIRIT1 radio part */ + SRadioInit xRadioInit = { + // XTAL_FREQUENCY, + XTAL_OFFSET_PPM, + BASE_FREQUENCY, + CHANNEL_SPACE, + CHANNEL_NUMBER, + MODULATION_SELECT, + DATARATE, + FREQ_DEVIATION, + BANDWIDTH + }; + SpiritRadioInit(&xRadioInit); + SpiritRadioSetXtalFrequency(XTAL_FREQUENCY); + SpiritRadioSetPALeveldBm(0,POWER_DBM); + SpiritRadioSetPALevelMaxIndex(0); + + /* Configures the SPIRIT1 packet handler part*/ + PktBasicInit xBasicInit = { + PREAMBLE_LENGTH, + SYNC_LENGTH, + SYNC_WORD, + LENGTH_TYPE, + LENGTH_WIDTH, + CRC_MODE, + CONTROL_LENGTH, + EN_ADDRESS, + EN_FEC, + EN_WHITENING + }; + SpiritPktBasicInit(&xBasicInit); + + /* Enable the following interrupt sources, routed to GPIO */ + SpiritIrqDeInit(NULL); + SpiritIrqClearStatus(); + SpiritIrq(TX_DATA_SENT, S_ENABLE); + SpiritIrq(RX_DATA_READY,S_ENABLE); + SpiritIrq(VALID_SYNC,S_ENABLE); + SpiritIrq(RX_DATA_DISC, S_ENABLE); + SpiritIrq(TX_FIFO_ERROR, S_ENABLE); + SpiritIrq(RX_FIFO_ERROR, S_ENABLE); + + /* Configure Spirit1 */ + SpiritRadioPersistenRx(S_ENABLE); + SpiritQiSetSqiThreshold(SQI_TH_0); + SpiritQiSqiCheck(S_ENABLE); + SpiritQiSetRssiThresholddBm(CCA_THRESHOLD); + SpiritTimerSetRxTimeoutStopCondition(SQI_ABOVE_THRESHOLD); + SET_INFINITE_RX_TIMEOUT(); + SpiritRadioAFCFreezeOnSync(S_ENABLE); + + /* Puts the SPIRIT1 in STANDBY mode (125us -> rx/tx) */ + spirit1_strobe(SPIRIT1_STROBE_STANDBY); + spirit_on = OFF; + CLEAR_RXBUF(); + CLEAR_TXBUF(); + + /* Initializes the mcu pin as input, used for IRQ */ + RadioGpioInit(RADIO_GPIO_IRQ, RADIO_MODE_EXTI_IN); + + /* Configure the radio to route the IRQ signal to its GPIO 3 */ + SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_IRQ, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, SPIRIT_GPIO_DIG_OUT_IRQ}); + + process_start(&spirit_radio_process, NULL); + + PRINTF("Spirit1 init done\n"); + return 0; +} + + +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_prepare(const void *payload, unsigned short payload_len) +{ + PRINTF("Spirit1: prep %u\n", payload_len); + packet_is_prepared = 0; + + /* Checks if the payload length is supported */ + if(payload_len > MAX_PACKET_LEN) { + return RADIO_TX_ERR; + } + + /* Should we delay for an ack? */ +#if NULLRDC_CONF_802154_AUTOACK + frame802154_t info154; + wants_an_ack = 0; + if(payload_len > ACK_LEN + && frame802154_parse((char*)payload, payload_len, &info154) != 0) { + if(info154.fcf.frame_type == FRAME802154_DATAFRAME + && info154.fcf.ack_required != 0) { + wants_an_ack = 1; + } + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + /* Sets the length of the packet to send */ + IRQ_DISABLE(); + spirit1_strobe(SPIRIT1_STROBE_FTX); + SpiritPktBasicSetPayloadLength(payload_len); + SpiritSpiWriteLinearFifo(payload_len, (uint8_t *)payload); + IRQ_ENABLE(); + + PRINTF("PREPARE OUT\n"); + + packet_is_prepared = 1; + return RADIO_TX_OK; +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_transmit(unsigned short payload_len) +{ + /* This function blocks until the packet has been transmitted */ + rtimer_clock_t rtimer_txdone, rtimer_rxack; + + PRINTF("TRANSMIT IN\n"); + if(!packet_is_prepared) { + return RADIO_TX_ERR; + } + + /* Stores the length of the packet to send */ + /* Others spirit_radio_prepare will be in hold */ + spirit_txbuf[0] = payload_len; + + /* Puts the SPIRIT1 in TX state */ + receiving_packet = 0; + SpiritSetReadyState(); + spirit1_strobe(SPIRIT1_STROBE_TX); + just_got_an_ack = 0; + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); + //BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 4 * RTIMER_SECOND/1000); //For GFSK with high data rate + BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 50 * RTIMER_SECOND/1000); //For FSK with low data rate + + /* Reset radio - needed for immediate RX of ack */ + CLEAR_TXBUF(); + CLEAR_RXBUF(); + IRQ_DISABLE(); + SpiritIrqClearStatus(); + spirit1_strobe(SPIRIT1_STROBE_SABORT); + BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); + spirit1_strobe(SPIRIT1_STROBE_READY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 1 * RTIMER_SECOND/1000); + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND/1000); + IRQ_ENABLE(); + +#if XXX_ACK_WORKAROUND + just_got_an_ack = 1; +#endif /* XXX_ACK_WORKAROUND */ + +#if NULLRDC_CONF_802154_AUTOACK + if (wants_an_ack) { + rtimer_txdone = RTIMER_NOW(); + BUSYWAIT_UNTIL(just_got_an_ack, 2 * RTIMER_SECOND/1000); + rtimer_rxack = RTIMER_NOW(); + + if(just_got_an_ack) { + ACKPRINTF("debug_ack: ack received after %u/%u ticks\n", + (uint32_t)(rtimer_rxack - rtimer_txdone), 2 * RTIMER_SECOND/1000); + } else { + ACKPRINTF("debug_ack: no ack received\n"); + } + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + PRINTF("TRANSMIT OUT\n"); + + CLEAR_TXBUF(); + + packet_is_prepared = 0; + + clock_wait(1); + + return RADIO_TX_OK; +} +/*---------------------------------------------------------------------------*/ +static int spirit_radio_send(const void *payload, unsigned short payload_len) +{ + if(spirit_radio_prepare(payload, payload_len) == RADIO_TX_ERR) { + return RADIO_TX_ERR; + } + return spirit_radio_transmit(payload_len); + +} +/*---------------------------------------------------------------------------*/ +static int spirit_radio_read(void *buf, unsigned short bufsize) +{ + PRINTF("READ IN\n"); + + /* Checks if the RX buffer is empty */ + if(IS_RXBUF_EMPTY()) { + IRQ_DISABLE(); + CLEAR_RXBUF(); + spirit1_strobe(SPIRIT1_STROBE_SABORT); + BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); + spirit1_strobe(SPIRIT1_STROBE_READY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 1 * RTIMER_SECOND/1000); + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND/1000); + PRINTF("READ OUT RX BUF EMPTY\n"); + IRQ_ENABLE(); + return 0; + } + + if(bufsize < spirit_rxbuf[0]) { + /* If buf has the correct size */ + PRINTF("TOO SMALL BUF\n"); + return 0; + } else { + /* Copies the packet received */ + memcpy(buf, spirit_rxbuf + 1, spirit_rxbuf[0]); + + bufsize = spirit_rxbuf[0]; + CLEAR_RXBUF(); + + PRINTF("READ OUT\n"); + + return bufsize; + } + +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_channel_clear(void) +{ + float rssi_value; + /* Local variable used to memorize the SPIRIT1 state */ + uint8_t spirit_state = ON; + + PRINTF("CHANNEL CLEAR IN\n"); + + if(spirit_on == OFF) { + /* Wakes up the SPIRIT1 */ + spirit_radio_on(); + spirit_state = OFF; + } + + /* */ + IRQ_DISABLE(); + spirit1_strobe(SPIRIT1_STROBE_SABORT); +/* SpiritCmdStrobeSabort();*/ + SpiritIrqClearStatus(); + IRQ_ENABLE(); + { + rtimer_clock_t timeout = RTIMER_NOW() + 5 * RTIMER_SECOND/1000; + do { + SpiritRefreshStatus(); + } while((g_xStatus.MC_STATE != MC_STATE_READY) && (RTIMER_NOW() < timeout)); + if(RTIMER_NOW() < timeout) { + return 1; + } + } + + /* Stores the RSSI value */ + rssi_value = SpiritQiGetRssidBm(); + + /* Puts the SPIRIT1 in its previous state */ + if(spirit_state==OFF) { + spirit_radio_off(); + } else { + spirit1_strobe(SPIRIT1_STROBE_RX); +/* SpiritCmdStrobeRx();*/ + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 5 * RTIMER_SECOND/1000); + } + + PRINTF("CHANNEL CLEAR OUT\n"); + + /* Checks the RSSI value with the threshold */ + if(rssi_valueoff\n"); + if(spirit_on == ON) { + /* Disables the mcu to get IRQ from the SPIRIT1 */ + IRQ_DISABLE(); + + /* first stop rx/tx */ + spirit1_strobe(SPIRIT1_STROBE_SABORT); + + /* Clear any pending irqs */ + SpiritIrqClearStatus(); + + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND/1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) { + PRINTF("Spirit1: failed off->ready\n"); + return 1; + } + + /* Puts the SPIRIT1 in STANDBY */ + spirit1_strobe(SPIRIT1_STROBE_STANDBY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_STANDBY, 5 * RTIMER_SECOND/1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_STANDBY) { + PRINTF("Spirit1: failed off->stdby\n"); + return 1; + } + + spirit_on = OFF; + CLEAR_TXBUF(); + CLEAR_RXBUF(); + } + PRINTF("Spirit1: off.\n"); + return 0; +} +/*---------------------------------------------------------------------------*/ + +static int spirit_radio_on(void) +{ + + PRINTF("Spirit1: on\n"); + spirit1_strobe(SPIRIT1_STROBE_SABORT); + BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); + if(spirit_on == OFF) + { + IRQ_DISABLE(); + /* ensure we are in READY state as we go from there to Rx */ + spirit1_strobe(SPIRIT1_STROBE_READY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND/1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) + { + PRINTF("Spirit1: failed to turn on\n"); + while(1); + //return 1; + } + + /* now we go to Rx */ + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 5 * RTIMER_SECOND/1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_RX) + { + PRINTF("Spirit1: failed to enter rx\n"); + while(1); + //return 1; + } + + /* Enables the mcu to get IRQ from the SPIRIT1 */ + IRQ_ENABLE(); + spirit_on = ON; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +static int interrupt_callback_in_progress = 0; +static int interrupt_callback_wants_poll = 0; +PROCESS_THREAD(spirit_radio_process, ev, data) +{ + PROCESS_BEGIN(); + PRINTF("Spirit1: process started\n"); + + while(1) { + int len; + + PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL); + PRINTF("Spirit1: polled\n"); + + packetbuf_clear(); + len = spirit_radio_read(packetbuf_dataptr(), PACKETBUF_SIZE); + + if(len > 0) { + +#if NULLRDC_CONF_802154_AUTOACK + /* Check if the packet has an ACK request */ + frame802154_t info154; + if(len > ACK_LEN && + frame802154_parse((char*)packetbuf_dataptr(), len, &info154) != 0) { + if(info154.fcf.frame_type == FRAME802154_DATAFRAME && + info154.fcf.ack_required != 0 && + linkaddr_cmp((linkaddr_t *)&info154.dest_addr, + &linkaddr_node_addr)) { + + +#if !XXX_ACK_WORKAROUND + /* Send an ACK packet */ + uint8_t ack_frame[ACK_LEN] = { + FRAME802154_ACKFRAME, + 0x00, + info154.seq + }; + IRQ_DISABLE(); + spirit1_strobe(SPIRIT1_STROBE_FTX); + SpiritPktBasicSetPayloadLength((uint16_t) ACK_LEN); + SpiritSpiWriteLinearFifo((uint16_t) ACK_LEN, (uint8_t *) ack_frame); + + SpiritSetReadyState(); + IRQ_ENABLE(); + spirit1_strobe(SPIRIT1_STROBE_TX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); + ACKPRINTF("debug_ack: sent ack %d\n", ack_frame[2]); +#endif /* !XXX_ACK_WORKAROUND */ + } + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + packetbuf_set_datalen(len); + NETSTACK_RDC.input(); + } + if(!IS_RXBUF_EMPTY()){ + process_poll(&spirit_radio_process); + } + + if(interrupt_callback_wants_poll) { + spirit1_interrupt_callback(); + + if(SPIRIT1_STATUS() == SPIRIT1_STATE_READY) { + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND/1000); + } + + } + } + + PROCESS_END(); +} +/*---------------------------------------------------------------------------*/ +void +spirit1_interrupt_callback(void) +{ +#define INTPRINTF(...) // PRINTF + SpiritIrqs xIrqStatus; + if (SpiritSPIBusy() || interrupt_callback_in_progress) + { + process_poll(&spirit_radio_process); + interrupt_callback_wants_poll = 1; + return; + } + + interrupt_callback_wants_poll = 0; + interrupt_callback_in_progress = 1; + + /* get interrupt source from radio */ + SpiritIrqGetStatus(&xIrqStatus); + SpiritIrqClearStatus(); + + if(xIrqStatus.IRQ_RX_FIFO_ERROR) + { + receiving_packet = 0; + interrupt_callback_in_progress = 0; + spirit1_strobe(SPIRIT1_STROBE_FRX); + return; + } + if(xIrqStatus.IRQ_TX_FIFO_ERROR) + { + receiving_packet = 0; + interrupt_callback_in_progress = 0; + spirit1_strobe(SPIRIT1_STROBE_FTX); + return; + } + + /* The IRQ_VALID_SYNC is used to notify a new packet is coming */ + if(xIrqStatus.IRQ_VALID_SYNC) + { + INTPRINTF("SYNC\n"); + receiving_packet = 1; + } + + /* The IRQ_TX_DATA_SENT notifies the packet received. Puts the SPIRIT1 in RX */ + if(xIrqStatus.IRQ_TX_DATA_SENT) + { + spirit1_strobe(SPIRIT1_STROBE_RX); +/* SpiritCmdStrobeRx();*/ + INTPRINTF("SENT\n"); + CLEAR_TXBUF(); + interrupt_callback_in_progress = 0; + return; + } + + /* The IRQ_RX_DATA_READY notifies a new packet arrived */ + if(xIrqStatus.IRQ_RX_DATA_READY) { + SpiritSpiReadLinearFifo(SpiritLinearFifoReadNumElementsRxFifo(), &spirit_rxbuf[1]); + spirit_rxbuf[0] = SpiritPktBasicGetReceivedPktLength(); + spirit1_strobe(SPIRIT1_STROBE_FRX); + + INTPRINTF("RECEIVED\n"); + + process_poll(&spirit_radio_process); + + receiving_packet = 0; + +#if NULLRDC_CONF_802154_AUTOACK + if (spirit_rxbuf[0] == ACK_LEN) { + /* For debugging purposes we assume this is an ack for us */ + just_got_an_ack = 1; + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + interrupt_callback_in_progress = 0; + return; + } + + if(xIrqStatus.IRQ_RX_DATA_DISC) + { + /* RX command - to ensure the device will be ready for the next reception */ + if(xIrqStatus.IRQ_RX_TIMEOUT) + { + SpiritCmdStrobeFlushRxFifo(); + rx_timeout = SET; + } + + } + + interrupt_callback_in_progress = 0; +} + +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/spirit1.h b/platform/stm32nucleo-spirit1/spirit1.h new file mode 100644 index 000000000..3c29abbf7 --- /dev/null +++ b/platform/stm32nucleo-spirit1/spirit1.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + */ + +/* + * \file + * spirit1.h + * \author + * Marcus Lunden > + * \desc + * Spirit1 radio driver + * + * + */ + + + +#ifndef __SPIRIT_H__ +#define __SPIRIT_H__ + +#include "radio.h" +#include "SPIRIT_Config.h" +#include "spirit1-config.h" +#include "spirit1_appli.h" +#include "spirit1-const.h" + +extern const struct radio_driver spirit_radio_driver; +void spirit1_interrupt_callback(void); + +#endif /* __SPIRIT_H__ */ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/spirit1_appli.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/spirit1_appli.h new file mode 100644 index 000000000..1d392e59b --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/spirit1_appli.h @@ -0,0 +1,233 @@ +/** + ****************************************************************************** + * @file spirit1_appli.h + * @author System Lab - NOIDA + * @version V1.1.0 + * @date 14-Aug-2014 + * @brief Header for spirit1_appli.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPIRIT1_APPLI_H +#define __SPIRIT1_APPLI_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" +#include "radio_shield_config.h" +#include "MCU_Interface.h" +#include "SPIRIT_Config.h" +#include "stm32l1xx_nucleo.h" + + +/* Exported macro ------------------------------------------------------------*/ + +#if defined(X_NUCLEO_IDS01A3) + #define USE_SPIRIT1_433MHz +#elif defined(X_NUCLEO_IDS01A4) + #define USE_SPIRIT1_868MHz +#elif defined(X_NUCLEO_IDS01A5) + #define USE_SPIRIT1_915MHz +#else +#error SPIRIT1 Nucleo Shield undefined or unsupported +#endif + +/* Uncomment the Link Layer features to be used */ +// #define USE_AUTO_ACK +// #define USE_AUTO_ACK_PIGGYBACKING +// #define USE_AUTO_RETRANSMISSION + +#if defined(USE_AUTO_ACK)&& defined(USE_AUTO_ACK_PIGGYBACKING)&& defined(USE_AUTO_RETRANSMISSION) +#define USE_STack_PROTOCOL + +/* LLP configuration parameters */ +#define EN_AUTOACK S_ENABLE +#define EN_PIGGYBACKING S_ENABLE +#define MAX_RETRANSMISSIONS PKT_N_RETX_2 + +#else +#define USE_BASIC_PROTOCOL + +#endif + +/* Uncomment the system Operating mode */ +//#define USE_LOW_POWER_MODE + +#if defined (USE_LOW_POWER_MODE) +#define LPM_ENABLE +#define MCU_STOP_MODE +//#define MCU_SLEEP_MODE +//#define RF_STANDBY +#endif + + +/* Exported constants --------------------------------------------------------*/ + +/* Radio configuration parameters */ +#define XTAL_OFFSET_PPM 0 +#define INFINITE_TIMEOUT 0.0 + +#ifdef USE_SPIRIT1_433MHz +#define BASE_FREQUENCY 433.0e6 +#endif + +#ifdef USE_SPIRIT1_868MHz +#define BASE_FREQUENCY 868.0e6 +#endif + +#ifdef USE_SPIRIT1_915MHz +//#define BASE_FREQUENCY 915.0e6 +#define BASE_FREQUENCY 902.0e6 +#endif + + +/* Addresses configuration parameters */ +#define EN_FILT_MY_ADDRESS S_DISABLE +#define MY_ADDRESS 0x34 +#define EN_FILT_MULTICAST_ADDRESS S_DISABLE +#define MULTICAST_ADDRESS 0xEE +#define EN_FILT_BROADCAST_ADDRESS S_DISABLE +#define BROADCAST_ADDRESS 0xFF +#define DESTINATION_ADDRESS 0x44 +#define EN_FILT_SOURCE_ADDRESS S_DISABLE +#define SOURCE_ADDR_MASK 0xf0 +#define SOURCE_ADDR_REF 0x37 + +#define APPLI_CMD 0x11 +#define NWK_CMD 0x22 +#define LED_TOGGLE 0xff +#define ACK_OK 0x01 +#define MAX_BUFFER_LEN 96 +#define TIME_TO_EXIT_RX 3000 +#define DELAY_RX_LED_TOGGLE 200 +#define DELAY_TX_LED_GLOW 1000 +#define LPM_WAKEUP_TIME 100 +#define DATA_SEND_TIME 30 + +#define PREAMBLE_LENGTH PKT_PREAMBLE_LENGTH_04BYTES +#define SYNC_LENGTH PKT_SYNC_LENGTH_4BYTES +#define CONTROL_LENGTH PKT_CONTROL_LENGTH_0BYTES +#define EN_ADDRESS S_DISABLE +#define EN_FEC S_DISABLE +#define CHANNEL_NUMBER 0 +#define LENGTH_TYPE PKT_LENGTH_VAR +#define POWER_INDEX 7 +#define RECEIVE_TIMEOUT 2000.0 /*change the value for required timeout period*/ +#define RSSI_THRESHOLD -120 + + + +#define POWER_DBM 11.6 +#define CHANNEL_SPACE 100e3 +#define FREQ_DEVIATION 127e3 +#define BANDWIDTH 540.0e3 +#define MODULATION_SELECT GFSK_BT1 +#define DATARATE 250000 +#define XTAL_OFFSET_PPM 0 +#define SYNC_WORD 0x88888888 +#define LENGTH_WIDTH 8 +#define CRC_MODE PKT_CRC_MODE_16BITS_2 +#define EN_WHITENING S_DISABLE +#define INFINITE_TIMEOUT 0.0 + + +/* Exported types ------------------------------------------------------------*/ +//extern LPTIM_HandleTypeDef LptimHandle; +extern volatile FlagStatus xRxDoneFlag, xTxDoneFlag; +extern volatile FlagStatus PushButtonStatusWakeup; +extern uint16_t wakeupCounter; +extern uint16_t dataSendCounter ; +extern volatile FlagStatus PushButtonStatusData, datasendFlag; + +typedef struct sRadioDriver +{ + void ( *Init )( void ); + void ( *GpioIrq )( SGpioInit *pGpioIRQ ); + void ( *RadioInit )( SRadioInit *pRadioInit ); + void ( *SetRadioPower )( uint8_t cIndex, float fPowerdBm ); + void ( *PacketConfig )( void ); + void ( *SetPayloadLen )( uint8_t length); + void ( *SetDestinationAddress )( uint8_t address); + void ( *EnableTxIrq )( void ); + void ( *EnableRxIrq )( void ); + void ( *DisableIrq )(void); + void ( *SetRxTimeout )( float cRxTimeout ); + void ( *EnableSQI )(void); + void ( *SetRssiThreshold)(int dbmValue); + void ( *ClearIrqStatus )(void); + void ( *StartRx )( void ); + void ( *StartTx )( uint8_t *buffer, uint8_t size ); + void ( *GetRxPacket )( uint8_t *buffer, uint8_t size ); +}RadioDriver_t; + +typedef struct sMCULowPowerMode +{ + void ( *McuStopMode )( void ); + void ( *McuStandbyMode )( void ); + void ( *McuSleepMode )( void ); +}MCULowPowerMode_t; + +typedef struct sRadioLowPowerMode +{ + void ( *RadioShutDown )( void ); + void ( *RadioStandBy )( void ); + void ( *RadioSleep ) ( void ); + void ( *RadioPowerON )( void ); +}RadioLowPowerMode_t; + +typedef struct +{ + uint8_t Cmdtag; + uint8_t CmdType; + uint8_t CmdLen; + uint8_t Cmd; + uint8_t DataLen; + uint8_t* DataBuff; +}AppliFrame_t; + + +/* Exported functions ------------------------------------------------------- */ +void HAL_Spirit1_Init(void); +void Enter_LP_mode(void); +void Exit_LP_mode(void); +void MCU_Enter_StopMode(void); +void MCU_Enter_StandbyMode(void); +void MCU_Enter_SleepMode(void); +void RadioPowerON(void); +void RadioPowerOFF(void); +void RadioStandBy(void); +void RadioSleep(void); +void SPIRIT1_Init(void); +void BasicProtocolInit(void); +void Set_KeyStatus(FlagStatus val); + +#endif /* __SPIRIT1_APPLI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32cube_hal_init.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32cube_hal_init.h new file mode 100644 index 000000000..e6aefade6 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32cube_hal_init.h @@ -0,0 +1,87 @@ +/** +****************************************************************************** +* @file stm32cube_hal_init.h +* @author MCD Application Team +* @version V1.0.0 +* @date 18-February-2014 +* @brief This file contains all the functions prototypes for the +* stm32cube_hal_init.c file. +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +* You may not use this file except in compliance with the License. +* You may obtain a copy of the License at: +* +* http://www.st.com/software_license_agreement_liberty_v2 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32CUBE_HAL_INIT_H +#define __STM32CUBE_HAL_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + + /* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" +#include "stm32l1xx_nucleo.h" +#include "platform-conf.h" + +#if COMPILE_SENSORS +#include "x_nucleo_iks01a1_pressure.h" +#include "x_nucleo_iks01a1_imu_6axes.h" +#include "x_nucleo_iks01a1_magneto.h" +#include "x_nucleo_iks01a1_hum_temp.h" +#endif /*COMPILE_SENSORS*/ + + + /* Exported types ------------------------------------------------------------*/ + /* Exported constants --------------------------------------------------------*/ + + /* Uncomment to enable the adaquate RTC Clock Source */ + +#define RTC_CLOCK_SOURCE_LSI + + +#ifdef RTC_CLOCK_SOURCE_LSI + #define RTC_ASYNCH_PREDIV 0x7F + #define RTC_SYNCH_PREDIV 0x0130 +#endif + +#ifdef RTC_CLOCK_SOURCE_LSE + #define RTC_ASYNCH_PREDIV 0x7F + #define RTC_SYNCH_PREDIV 0x00FF +#endif + + + + /* Exported macro ------------------------------------------------------------*/ + + /* Exported functions ------------------------------------------------------- */ + +void stm32cube_hal_init(); +void RTC_TimeRegulate(uint8_t hh, uint8_t mm, uint8_t ss); + +#ifdef __cplusplus +} +#endif + + + +#endif /* __STM32CUBE_HAL_INIT */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_hal_conf.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_hal_conf.h new file mode 100644 index 000000000..a1ad11636 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_hal_conf.h @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_conf.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CONF_H +#define __STM32L1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LCD_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +//#define HAL_OPAMP_MODULE_ENABLED +//#define HAL_PCD_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/*#define USE_FULL_ASSERT 1*/ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l1xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l1xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l1xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32l1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l1xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l1xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l1xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_it.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_it.h new file mode 100644 index 000000000..47c911392 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_it.h @@ -0,0 +1,72 @@ +/** + ****************************************************************************** + * @file Templates/Inc/stm32l1xx_it.h + * @author MCD Application Team + * @version V1.0.0 + * @date 5-September-2014 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_IT_H +#define __STM32L1xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI0_IRQHandler(void); +void EXTI1_IRQHandler(void); +void I2Cx_EV_IRQHandler(void); +void I2Cx_ER_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/spirit1_appli.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/spirit1_appli.c new file mode 100644 index 000000000..c71c19105 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/spirit1_appli.c @@ -0,0 +1,649 @@ +/** +****************************************************************************** +* @file spirit1_appli.c +* @author System Lab - NOIDA +* @version V1.1.0 +* @date 14-Aug-2014 +* @brief user file to configure Spirit1 transceiver. +* +@verbatim +=============================================================================== +##### How to use this driver ##### +=============================================================================== +[..] +This file is generated automatically by STM32CubeMX and eventually modified +by the user + +@endverbatim +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l152xe.h" +#include "spirit1_appli.h" +#include "MCU_Interface.h" +#include "SPIRIT1_Util.h" + +#include "lib/sensors.h" +extern const struct sensors_sensor button_sensor; + +/** @addtogroup USER +* @{ +*/ + +/** @defgroup SPIRIT1_APPLI +* @brief User file to configure spirit1 tranceiver for desired frequency and +* @feature. +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ + +/** +* @brief RadioDriver_t structure fitting +*/ +RadioDriver_t spirit_cb = +{ + .Init = Spirit1InterfaceInit, + .GpioIrq = Spirit1GpioIrqInit, + .RadioInit = Spirit1RadioInit, + .SetRadioPower = Spirit1SetPower, + .PacketConfig = Spirit1PacketConfig, + .SetPayloadLen = Spirit1SetPayloadlength, + .SetDestinationAddress = Spirit1SetDestinationAddress, + .EnableTxIrq = Spirit1EnableTxIrq, + .EnableRxIrq = Spirit1EnableRxIrq, + .DisableIrq = Spirit1DisableIrq, + .SetRxTimeout = Spirit1SetRxTimeout, + .EnableSQI = Spirit1EnableSQI, + .SetRssiThreshold = Spirit1SetRssiTH, + .ClearIrqStatus = Spirit1ClearIRQ, + .StartRx = Spirit1StartRx, + .StartTx = Spirit1StartTx, + .GetRxPacket = Spirit1GetRxPacket +}; + +/** +* @brief MCULowPowerMode_t structure fitting +*/ +MCULowPowerMode_t MCU_LPM_cb = +{ + .McuStopMode = MCU_Enter_StopMode, + .McuStandbyMode = MCU_Enter_StandbyMode, + .McuSleepMode = MCU_Enter_SleepMode +}; + +/** +* @brief RadioLowPowerMode_t structure fitting +*/ +RadioLowPowerMode_t Radio_LPM_cb = +{ + .RadioShutDown = RadioPowerOFF, + .RadioStandBy = RadioStandBy, + .RadioSleep = RadioSleep, + .RadioPowerON = RadioPowerON +}; + +/** +* @brief GPIO structure fitting +*/ +SGpioInit xGpioIRQ={ + SPIRIT_GPIO_IRQ, + SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, + SPIRIT_GPIO_DIG_OUT_IRQ +}; + +/** +* @brief Radio structure fitting +*/ +SRadioInit xRadioInit = { + XTAL_OFFSET_PPM, + BASE_FREQUENCY, + CHANNEL_SPACE, + CHANNEL_NUMBER, + MODULATION_SELECT, + DATARATE, + FREQ_DEVIATION, + BANDWIDTH +}; + + +#if defined(USE_STack_PROTOCOL) +/** +* @brief Packet Basic structure fitting +*/ +PktStackInit xStackInit={ + PREAMBLE_LENGTH, + SYNC_LENGTH, + SYNC_WORD, + LENGTH_TYPE, + LENGTH_WIDTH, + CRC_MODE, + CONTROL_LENGTH, + EN_FEC, + EN_WHITENING +}; + +/* LLP structure fitting */ +PktStackLlpInit xStackLLPInit ={ + EN_AUTOACK, + EN_PIGGYBACKING, + MAX_RETRANSMISSIONS +}; + +/** +* @brief Address structure fitting +*/ +PktStackAddressesInit xAddressInit={ + EN_FILT_MY_ADDRESS, + MY_ADDRESS, + EN_FILT_MULTICAST_ADDRESS, + MULTICAST_ADDRESS, + EN_FILT_BROADCAST_ADDRESS, + BROADCAST_ADDRESS +}; + +#elif defined(USE_BASIC_PROTOCOL) + +/** +* @brief Packet Basic structure fitting +*/ +PktBasicInit xBasicInit={ + PREAMBLE_LENGTH, + SYNC_LENGTH, + SYNC_WORD, + LENGTH_TYPE, + LENGTH_WIDTH, + CRC_MODE, + CONTROL_LENGTH, + EN_ADDRESS, + EN_FEC, + EN_WHITENING +}; + + +/** +* @brief Address structure fitting +*/ +PktBasicAddressesInit xAddressInit={ + EN_FILT_MY_ADDRESS, + MY_ADDRESS, + EN_FILT_MULTICAST_ADDRESS, + MULTICAST_ADDRESS, + EN_FILT_BROADCAST_ADDRESS, + BROADCAST_ADDRESS +}; +#endif + + +/* Private define ------------------------------------------------------------*/ +#define TIME_UP 0x01 + +/* Private macro -------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ +RadioDriver_t *pRadioDriver; +MCULowPowerMode_t *pMCU_LPM_Comm; +RadioLowPowerMode_t *pRadio_LPM_Comm; +/*Flags declarations*/ +volatile FlagStatus xRxDoneFlag = RESET, xTxDoneFlag=RESET, cmdFlag=RESET; +volatile FlagStatus xStartRx=RESET, rx_timeout=RESET, exitTime=RESET; +volatile FlagStatus datasendFlag=RESET, wakeupFlag=RESET; +volatile FlagStatus PushButtonStatusWakeup=RESET; +volatile FlagStatus PushButtonStatusData=RESET; +/*IRQ status struct declaration*/ +SpiritIrqs xIrqStatus; +static __IO uint32_t KEYStatusData = 0x00; +AppliFrame_t xTxFrame, xRxFrame; +uint8_t TxFrameBuff[MAX_BUFFER_LEN] = {0x00}; +uint16_t exitCounter = 0; +uint16_t txCounter = 0; +uint16_t wakeupCounter = 0; +uint16_t dataSendCounter = 0x00; + +/* Private function prototypes -----------------------------------------------*/ + +void HAL_Spirit1_Init(void); +void Data_Comm_On(uint8_t *pTxBuff, uint8_t cTxlen, uint8_t* pRxBuff, uint8_t cRxlen); +void Enter_LP_mode(void); +void Exit_LP_mode(void); +void MCU_Enter_StopMode(void); +void MCU_Enter_StandbyMode(void); +void MCU_Enter_SleepMode(void); +void RadioPowerON(void); +void RadioPowerOFF(void); +void RadioStandBy(void); +void RadioSleep(void); +void SPIRIT1_Init(void); +void STackProtocolInit(void); +void BasicProtocolInit(void); +void P2PInterruptHandler(void); +void Set_KeyStatus(FlagStatus val); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); +void HAL_SYSTICK_Callback(void); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SPIRIT1_APPLI_Private_Functions +* @{ +*/ + +/** +* @brief Initializes RF Transceiver's HAL. +* @param None +* @retval None. +*/ +void HAL_Spirit1_Init(void) +{ + pRadioDriver = &spirit_cb; + pRadioDriver->Init( ); +} + + + +/** +* @brief This function initializes the protocol for point-to-point +* communication +* @param None +* @retval None +*/ +void SPIRIT1_Init(void) +{ + pRadioDriver = &spirit_cb; + + /* Spirit IRQ config */ + pRadioDriver->GpioIrq(&xGpioIRQ); + + /* Spirit Radio config */ + pRadioDriver->RadioInit(&xRadioInit); + + /* Spirit Radio set power */ + pRadioDriver->SetRadioPower(POWER_INDEX, POWER_DBM); + + /* Spirit Packet config */ + pRadioDriver->PacketConfig(); + + pRadioDriver->EnableSQI(); + + pRadioDriver->SetRssiThreshold(RSSI_THRESHOLD); +} + + +/** +* @brief This function initializes the BASIC Packet handler of spirit1 +* @param None +* @retval None +*/ +void BasicProtocolInit(void) +{ +#if defined(USE_BASIC_PROTOCOL) + /* Spirit Packet config */ + SpiritPktBasicInit(&xBasicInit); + SpiritPktBasicAddressesInit(&xAddressInit); +#endif +} + +/** +* @brief This routine will put the radio and mcu in LPM +* @param None +* @retval None +*/ +void Enter_LP_mode(void) +{ + + pMCU_LPM_Comm = &MCU_LPM_cb; + pRadio_LPM_Comm = &Radio_LPM_cb; + +#if defined(MCU_STOP_MODE)&&defined(RF_SHUTDOWN) + { + pRadio_LPM_Comm->RadioShutDown(); + pMCU_LPM_Comm->McuStopMode(); + } +#elif defined(MCU_STOP_MODE)&&defined(RF_STANDBY) + { + pRadio_LPM_Comm->RadioStandBy(); + pMCU_LPM_Comm->McuStopMode(); + } +#elif defined(MCU_STOP_MODE)&&defined(RF_SLEEP) + { + pRadio_LPM_Comm->RadioSleep(); + pMCU_LPM_Comm->McuStopMode(); + } +#elif defined(MCU_STANDBY_MODE)&&defined(RF_SHUTDOWN) + { + pRadio_LPM_Comm->RadioShutDown(); + pMCU_LPM_Comm->McuStandbyMode(); + } +#elif defined(MCU_STANDBY_MODE)&&defined(RF_STANDBY) + { + pRadio_LPM_Comm->RadioStandBy(); + pMCU_LPM_Comm->McuStandbyMode(); + } +#elif defined(MCU_STANDBY_MODE)&&defined(RF_SLEEP) + { + pRadio_LPM_Comm->RadioSleep(); + pMCU_LPM_Comm->McuStandbyMode(); + } +#elif defined(MCU_SLEEP_MODE)&&defined(RF_SHUTDOWN) + { + pRadio_LPM_Comm->RadioShutDown(); + pMCU_LPM_Comm->McuSleepMode(); + } +#elif defined(MCU_SLEEP_MODE)&&defined(RF_STANDBY) + { + pRadio_LPM_Comm->RadioStandBy(); + pMCU_LPM_Comm->McuSleepMode(); + } +#elif defined(MCU_SLEEP_MODE)&&defined(RF_SLEEP) + { + pRadio_LPM_Comm->RadioSleep(); + pMCU_LPM_Comm->McuSleepMode(); + } +#elif defined(MCU_STOP_MODE) + pMCU_LPM_Comm->McuStopMode(); + +#elif defined(MCU_STANDBY_MODE) + pMCU_LPM_Comm->McuStandbyMode(); + +#else + pMCU_LPM_Comm->McuSleepMode(); +#endif +} + +/** +* @brief This routine wake-up the mcu and radio from LPM +* @param None +* @retval None +*/ +void Exit_LP_mode(void) +{ + pRadio_LPM_Comm = &Radio_LPM_cb; + pRadio_LPM_Comm->RadioPowerON(); +} + +/** +* @brief This routine puts the MCU in stop mode +* @param None +* @retval None +*/ +void MCU_Enter_StopMode(void) +{ + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); /* Infinite loop */ +} + +/** +* @brief This routine puts the MCU in standby mode +* @param None +* @retval None +*/ +void MCU_Enter_StandbyMode(void) +{ + HAL_PWR_EnterSTANDBYMode(); /* Infinite loop */ +} + +/** +* @brief This routine puts the MCU in sleep mode +* @param None +* @retval None +*/ +void MCU_Enter_SleepMode(void) +{ + /*Suspend Tick increment to prevent wakeup by Systick interrupt. + Otherwise the Systick interrupt will wake up the device within 1ms (HAL time base)*/ + HAL_SuspendTick(); + HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); /* Infinite loop */ +} + +/** +* @brief This function will turn on the radio and waits till it enters the Ready state. +* @param Param:None. +* @retval None +* +*/ +void RadioPowerON(void) +{ + SpiritCmdStrobeReady(); + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + } + while(g_xStatus.MC_STATE!=MC_STATE_READY); +} + + +/** +* @brief This function will Shut Down the radio. +* @param Param:None. +* @retval None +* +*/ +void RadioPowerOFF(void) +{ + SpiritEnterShutdown(); +} + + +/** +* @brief This function will put the radio in standby state. +* @param None. +* @retval None +* +*/ +void RadioStandBy(void) +{ + SpiritCmdStrobeStandby(); +#if 0 + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + } + while(g_xStatus.MC_STATE!=MC_STATE_STANDBY); +#endif +} + +/** +* @brief This function will put the radio in sleep state. +* @param None. +* @retval None +* +*/ +void RadioSleep(void) +{ + SpiritCmdStrobeSleep(); +#if 0 + do{ + /* Delay for state transition */ + for(volatile uint8_t i=0; i!=0xFF; i++); + + /* Reads the MC_STATUS register */ + SpiritRefreshStatus(); + } + while(g_xStatus.MC_STATE!=MC_STATE_SLEEP); +#endif +} + +/** +* @brief This routine updates the respective status for key press. +* @param None +* @retval None +*/ +void Set_KeyStatus(FlagStatus val) +{ + if(val==SET) + { + KEYStatusData = 1; + } + else + KEYStatusData = 0; +} + + +/** + * @brief SYSTICK callback. + * @param None + * @retval None + */ +void HAL_SYSTICK_Callback(void) +{ + if(exitTime) + { + /*Decreament the counter to check when 3 seconds has been elapsed*/ + exitCounter--; + /*3 seconds has been elapsed*/ + if(exitCounter <= TIME_UP) + { + exitTime = RESET; + } + } + +#if defined(RF_STANDBY) + /*Check if Push Button pressed for wakeup or to send data*/ + if(PushButtonStatusWakeup) + { + /*Decreament the counter to check when 5 seconds has been elapsed*/ + wakeupCounter--; + + /*5seconds has been elapsed*/ + if(wakeupCounter<=TIME_UP) + { + /*Perform wakeup opeartion*/ + wakeupFlag = SET; + Exit_LP_mode(); + BSP_LED_Toggle(LED2); + PushButtonStatusWakeup = RESET; + PushButtonStatusData = SET; + } + } + else if(PushButtonStatusData) + { + dataSendCounter--; + if(dataSendCounter<=TIME_UP) + { + datasendFlag = SET; + PushButtonStatusWakeup = RESET; + PushButtonStatusData = RESET; + } + } +#endif +} +/** +* @} +*/ +/** + * @brief GPIO EXTI callback + * @param uint16_t GPIO_Pin + * @retval None + */ +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ +#if defined(MCU_STOP_MODE)/*if MCU is in stop mode*/ + + /* Clear Wake Up Flag */ + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); + + /* Configures system clock after wake-up from STOP: enable HSE, PLL and select + PLL as system clock source (HSE and PLL are disabled in STOP mode) */ + SystemClockConfig_STOP(); +#endif +#if defined(MCU_SLEEP_MODE) + /* Resume Tick interrupt if disabled prior to sleep mode entry*/ + HAL_ResumeTick(); +#endif + + /* Initialize LEDs*/ + RadioShieldLedInit(RADIO_SHIELD_LED); + //BSP_LED_Init(LED2); + + if (GPIO_Pin == USER_BUTTON_PIN) + { + sensors_changed(&button_sensor); + } + +} +/** +* @} +*/ +/** + * @brief Configures system clock after wake-up from STOP: enable HSI, PLL + * and select PLL as system clock source. + * @param None + * @retval None + */ +#if defined(MCU_STOP_MODE)/*if MCU is in stop mode*/ + +static void SystemClockConfig_STOP(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable Power Control clock */ + __PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Get the Oscillators configuration according to the internal RCC registers */ + HAL_RCC_GetOscConfig(&RCC_OscInitStruct); + + /* After wake-up from STOP reconfigure the system clock: Enable HSI and PLL */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; + RCC_OscInitStruct.HSICalibrationValue = 0x10; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1); +} +#endif +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32cube_hal_init.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32cube_hal_init.c new file mode 100644 index 000000000..3dc4ea8b8 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32cube_hal_init.c @@ -0,0 +1,334 @@ +/** +****************************************************************************** +* @file stm32cube_hal_init.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief STM32 Cube HAL Init Source file +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#include "stdio.h" +#include "string.h" +#include "stdlib.h" +#include "stm32cube_hal_init.h" +#include "stm32l1xx_nucleo.h" +#include "radio_shield_config.h" +#include "spirit1_appli.h" + + +extern UART_HandleTypeDef UartHandle; +FlagStatus TamperStatus = RESET; +volatile uint8_t scheduler_started=0; +RTC_HandleTypeDef RtcHandle; +int dec_precision = 2; +volatile float UVI_Value; + +static void RTC_Config(void); +static void RTC_TimeStampConfig(void); +static void SystemClock_Config(void); +static void MX_GPIO_Init(void); + +void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); +void BSP_LED_Init(Led_TypeDef Led); +void BSP_LED_Off(Led_TypeDef Led); +void BSP_LED_On(Led_TypeDef Led); +void BSP_LED_Toggle(Led_TypeDef Led); +void USARTConfig(void); +void Stack_6LoWPAN_Init(void); + +static void Error_Handler(); + +I2C_HandleTypeDef I2cHandle; +#define I2C_ADDRESS 0x30F + +/* I2C SPEEDCLOCK define to max value: 400 KHz on STM32L1xx*/ +#define I2C_SPEEDCLOCK 400000 +#define I2C_DUTYCYCLE I2C_DUTYCYCLE_2 + + +/** + * @brief stm32cube_hal_init() + * @param None + * @retval None + */ +void stm32cube_hal_init() +{ + HAL_Init(); + /* Configure the system clock */ + SystemClock_Config(); + + HAL_EnableDBGStopMode(); + + MX_GPIO_Init(); + HAL_Spirit1_Init(); + SPIRIT1_Init(); + + USARTConfig(); + /* Initialize RTC */ + + RTC_Config(); + RTC_TimeStampConfig(); +} + + + +/** + * @brief Configure the RTC peripheral by selecting the clock source. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + /*##-1- Configure the RTC peripheral #######################################*/ + RtcHandle.Instance = RTC; + + /* Configure RTC prescaler and RTC data registers */ + /* RTC configured as follow: + - Hour Format = Format 12 + - Asynch Prediv = Value according to source clock + - Synch Prediv = Value according to source clock + - OutPut = Output Disable + - OutPutPolarity = High Polarity + - OutPutType = Open Drain */ + RtcHandle.Init.HourFormat = RTC_HOURFORMAT_12; + RtcHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; + RtcHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV; + RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; + RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + + if(HAL_RTC_Init(&RtcHandle) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } +} + + +/** + * @brief Configures the current time and date. + * @param None + * @retval None + */ +static void RTC_TimeStampConfig(void) +{ + RTC_DateTypeDef sdatestructure; + RTC_TimeTypeDef stimestructure; + + /*##-3- Configure the Date #################################################*/ + /* Set Date: Tuesday February 18th 2014 */ + sdatestructure.Year = 0x14; + sdatestructure.Month = RTC_MONTH_FEBRUARY; + sdatestructure.Date = 0x18; + sdatestructure.WeekDay = RTC_WEEKDAY_TUESDAY; + + if(HAL_RTC_SetDate(&RtcHandle,&sdatestructure,FORMAT_BCD) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } + + /*##-4- Configure the Time #################################################*/ + /* Set Time: 08:10:00 */ + stimestructure.Hours = 0x08; + stimestructure.Minutes = 0x10; + stimestructure.Seconds = 0x00; + stimestructure.TimeFormat = RTC_HOURFORMAT12_AM; + stimestructure.DayLightSaving = RTC_DAYLIGHTSAVING_NONE ; + stimestructure.StoreOperation = RTC_STOREOPERATION_RESET; + + if(HAL_RTC_SetTime(&RtcHandle,&stimestructure,FORMAT_BCD) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } +} + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (HSI) + * SYSCLK(Hz) = 32000000 + * HCLK(Hz) = 32000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 1 + * HSI Frequency(Hz) = 16000000 + * PLL_MUL = 4 + * PLL_DIV = 2 + * Flash Latency(WS) = 1 + * Main regulator output voltage = Scale1 mode + * @param None + * @retval None + */ + +void SystemClock_Config(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + /* Enable HSE Oscillator and Activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + + /* Set Voltage scale1 as MCU will run at 32MHz */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ + while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } +} + + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +static void Error_Handler(void) +{ + /* User may add here some code to deal with this error */ + while(1) + { + } +} + +/** + * @brief RTC MSP Initialization + * This function configures the hardware resources used in this example + * @param hrtc: RTC handle pointer + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval None + */ +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /*##-1- Configue LSE as RTC clock soucre ###################################*/ +#ifdef RTC_CLOCK_SOURCE_LSE + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_OFF; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } +#elif defined (RTC_CLOCK_SOURCE_LSI) + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } +#else +#error Please select the RTC Clock source inside the stm32cube_hal_init.h file +#endif /*RTC_CLOCK_SOURCE_LSE*/ + + /*##-2- Enable RTC peripheral Clocks #######################################*/ + /* Enable RTC Clock */ + __HAL_RCC_RTC_ENABLE(); + + /*##-3- Configure the NVIC for RTC TimeStamp ###################################*/ + HAL_NVIC_SetPriority(/*TAMP_STAMP_IRQn*/2, 0x0F, 0); + HAL_NVIC_EnableIRQ(/*TAMP_STAMP_IRQn*/2); +} + + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + + /* GPIO Ports Clock Enable */ + __GPIOA_CLK_ENABLE(); + __GPIOC_CLK_ENABLE(); + __GPIOD_CLK_ENABLE(); +} + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_hal_msp.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_hal_msp.c new file mode 100644 index 000000000..71f9f6753 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_hal_msp.c @@ -0,0 +1,319 @@ +/** +****************************************************************************** +* @file stm32l1xx_hal_msp.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief HAL MSP file +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include "stm32cube_hal_init.h" +#include "stm32l1xx_hal.h" +#include "hw-config.h" +/** @addtogroup STM32L1xx_HAL_Examples + * @{ + */ + +/** @addtogroup Templates + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +volatile uint8_t UART_RxBuffer[UART_RxBufferSize]; +volatile uint32_t Usart_BaudRate = 115200; + +UART_HandleTypeDef UartHandle; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_MSP_Private_Functions + * @{ + */ + +/** + * @brief Initializes the Global MSP. + * @param None + * @retval None + */ +void HAL_MspInit(void) +{ + /* NOTE : This function is generated automatically by MicroXplorer and eventually + modified by the user + */ + + GPIO_InitTypeDef GPIO_InitStruct; + + /*##-2- Enable peripherals and GPIO Clocks #################################*/ + /* Enable GPIO TX/RX clock */ + /* GPIO Ports Clock Enable */ + __GPIOA_CLK_ENABLE(); + __GPIOC_CLK_ENABLE(); + __GPIOD_CLK_ENABLE(); + I2Cx_SCL_GPIO_CLK_ENABLE(); + I2Cx_SDA_GPIO_CLK_ENABLE(); + /* Enable I2Cx clock */ + I2Cx_CLK_ENABLE(); + + /*##-3- Configure peripheral GPIO ##########################################*/ + /* I2C TX GPIO pin configuration */ + GPIO_InitStruct.Pin = I2Cx_SCL_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Alternate = I2Cx_SCL_SDA_AF; + + HAL_GPIO_Init(I2Cx_SCL_GPIO_PORT, &GPIO_InitStruct); + + /* I2C RX GPIO pin configuration */ + GPIO_InitStruct.Pin = I2Cx_SDA_PIN; + GPIO_InitStruct.Alternate = I2Cx_SCL_SDA_AF; + + HAL_GPIO_Init(I2Cx_SDA_GPIO_PORT, &GPIO_InitStruct); + + /*##-4- Configure the NVIC for I2C ########################################*/ + /* NVIC for I2Cx */ + HAL_NVIC_SetPriority(I2Cx_ER_IRQn, 0, 1); + HAL_NVIC_EnableIRQ(I2Cx_ER_IRQn); + HAL_NVIC_SetPriority(I2Cx_EV_IRQn, 0, 2); + HAL_NVIC_EnableIRQ(I2Cx_EV_IRQn); + +} + +/** + * @brief DeInitializes the Global MSP. + * @param None + * @retval None + */ +void HAL_MspDeInit(void) +{ + /* NOTE : This function is generated automatically by MicroXplorer and eventually + modified by the user + */ + /*##-1- Reset peripherals ##################################################*/ + I2Cx_FORCE_RESET(); + I2Cx_RELEASE_RESET(); + + /*##-2- Disable peripherals and GPIO Clocks #################################*/ + /* Configure I2C Tx as alternate function */ + HAL_GPIO_DeInit(I2Cx_SCL_GPIO_PORT, I2Cx_SCL_PIN); + /* Configure I2C Rx as alternate function */ + HAL_GPIO_DeInit(I2Cx_SDA_GPIO_PORT, I2Cx_SDA_PIN); + + /*##-3- Disable the NVIC for I2C ##########################################*/ + HAL_NVIC_DisableIRQ(I2Cx_ER_IRQn); + HAL_NVIC_DisableIRQ(I2Cx_EV_IRQn); +} + + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* Peripheral clock enable */ + __TIM2_CLK_ENABLE(); + + /**TIM2 GPIO Configuration + PA0-WKUP ------> TIM2_CH1 + */ + /* Peripheral interrupt init*/ + + HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM2_IRQn); + } + +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM2) + { + /* Peripheral clock disable */ + __TIM2_CLK_DISABLE(); + + /**TIM2 GPIO Configuration + PA0-WKUP ------> TIM2_CH1 + */ + /* Peripheral interrupt Deinit*/ + HAL_NVIC_DisableIRQ(TIM2_IRQn); + } + +} + + +/** + * @brief UART MSP Initialization + * This function configures the hardware resources used in this example: + * - Peripheral's clock enable + * - Peripheral's GPIO Configuration + * - NVIC configuration for UART interrupt request enable + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /*##-1- Enable peripherals and GPIO Clocks #################################*/ + /* Enable GPIO TX/RX clock */ + USARTx_TX_GPIO_CLK_ENABLE(); + USARTx_RX_GPIO_CLK_ENABLE(); + + + /* Enable USARTx clock */ + USARTx_CLK_ENABLE(); + + /*##-2- Configure peripheral GPIO ##########################################*/ + /* UART TX GPIO pin configuration */ + GPIO_InitStruct.Pin = USARTx_TX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Alternate = USARTx_TX_AF; + + HAL_GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStruct); + + /* UART RX GPIO pin configuration */ + GPIO_InitStruct.Pin = USARTx_RX_PIN; + GPIO_InitStruct.Alternate = USARTx_RX_AF; + + + + + HAL_GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStruct); + + /*##-3- Configure the NVIC for UART ########################################*/ + /* NVIC for USART */ + HAL_NVIC_SetPriority(USARTx_IRQn, 0, 1); + HAL_NVIC_EnableIRQ(USARTx_IRQn); + +} + +/** + * @brief UART MSP De-Initialization + * This function frees the hardware resources used in this example: + * - Disable the Peripheral's clock + * - Revert GPIO and NVIC configuration to their default state + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /*##-1- Reset peripherals ##################################################*/ + USARTx_FORCE_RESET(); + USARTx_RELEASE_RESET(); + + /*##-2- Disable peripherals and GPIO Clocks #################################*/ + /* Configure UART Tx as alternate function */ + HAL_GPIO_DeInit(USARTx_TX_GPIO_PORT, USARTx_TX_PIN); + /* Configure UART Rx as alternate function */ + HAL_GPIO_DeInit(USARTx_RX_GPIO_PORT, USARTx_RX_PIN); + + /*##-3- Disable the NVIC for UART ##########################################*/ + HAL_NVIC_DisableIRQ(USARTx_IRQn); +} + + +/** + * @brief Configure the USART + * @param None + * @retval None + */ +void USARTConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /*##-1- Enable peripherals and GPIO Clocks #################################*/ + /* Enable GPIO TX/RX clock */ + USARTx_TX_GPIO_CLK_ENABLE(); + USARTx_RX_GPIO_CLK_ENABLE(); + /* Enable USART2 clock */ + USARTx_CLK_ENABLE(); + /* Enable DMA1 clock */ + DMAx_CLK_ENABLE(); + + /*##-2- Configure peripheral GPIO ##########################################*/ + /* UART TX GPIO pin configuration */ + GPIO_InitStruct.Pin = USARTx_TX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Alternate = USARTx_TX_AF; + + HAL_GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStruct); + + /* UART RX GPIO pin configuration */ + GPIO_InitStruct.Pin = USARTx_RX_PIN; + GPIO_InitStruct.Alternate = USARTx_RX_AF; + + HAL_GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStruct); + + + /*##-1- Configure the UART peripheral ######################################*/ + /* Put the USART peripheral in the Asynchronous mode (UART Mode) */ + UartHandle.Instance = USARTx; + UartHandle.Init.BaudRate = Usart_BaudRate; + UartHandle.Init.WordLength = UART_WORDLENGTH_8B; + UartHandle.Init.StopBits = UART_STOPBITS_1; + UartHandle.Init.Parity = UART_PARITY_NONE; + UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + UartHandle.Init.Mode = UART_MODE_TX_RX; + + if(HAL_UART_Init(&UartHandle) != HAL_OK) + { + // Error_Handler(); + while(1); + } + + UartHandle.pRxBuffPtr = (uint8_t*)UART_RxBuffer; + UartHandle.RxXferSize = UART_RxBufferSize; + UartHandle.ErrorCode = HAL_UART_ERROR_NONE; + //HAL_UART_Receive_IT(&UartHandle, (uint8_t*)UART_RxBuffer, UART_RxBufferSize); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c new file mode 100644 index 000000000..915263370 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c @@ -0,0 +1,363 @@ +/** +****************************************************************************** +* @file stm32l1xx_it.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +* @brief Main Interrupt Service Routines +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include "stm32cube_hal_init.h" +#include "stm32l1xx_it.h" +#include "stm32l1xx_nucleo.h" +#include "radio_gpio.h" +#include "spirit1.h" + +extern UART_HandleTypeDef UartHandle; +/** @addtogroup STM32L1xx_HAL_Examples +* @{ +*/ + +/** @addtogroup Templates +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ +extern I2C_HandleTypeDef I2cHandle; +/** +* @brief This function handles NMI exception. +* @param None +* @retval None +*/ +void NMI_Handler(void) +{ +} +void WWDG_IRQHandler(void) +{ + while(1); +} +/** +* @brief This function handles Hard Fault exception. +* @param None +* @retval None +*/ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** +* @brief This function handles Memory Manage exception. +* @param None +* @retval None +*/ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** +* @brief This function handles Bus Fault exception. +* @param None +* @retval None +*/ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** +* @brief This function handles Usage Fault exception. +* @param None +* @retval None +*/ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** +* @brief This function handles SVCall exception. +* @param None +* @retval None +*/ +void SVC_Handler(void) +{ +} + +/** +* @brief This function handles Debug Monitor exception. +* @param None +* @retval None +*/ +void DebugMon_Handler(void) +{ +} + +/** +* @brief This function handles PendSVC exception. +* @param None +* @retval None +*/ +void PendSV_Handler(void) +{ +} + + +/******************************************************************************/ +/* STM32L1xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32l1xx.s). */ +/******************************************************************************/ +/** +* @brief This function handles I2C event interrupt request. +* @param None +* @retval None +* @Note This function is redefined in "stm32cube_hal_init.h" and related to I2C data transmission +*/ +void I2Cx_EV_IRQHandler(void) +{ + HAL_I2C_EV_IRQHandler(& I2cHandle); +} + +/** +* @brief This function handles I2C error interrupt request. +* @param None +* @retval None +* @Note This function is redefined in "stm32cube_hal_init.h" and related to I2C error +*/ +void I2Cx_ER_IRQHandler(void) +{ + HAL_I2C_ER_IRQHandler(& I2cHandle); +} + + +/** +* @brief This function handles External lines 15 to 4 interrupt request. +* @param None +* @retval None +*/ +void EXTI0_IRQHandler(void) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_0) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0); + } + while(1); +} + +void EXTI1_IRQHandler(void) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_1) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_1); + } + while(1); +} + +void EXTI2_IRQHandler(void) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_2) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_2); + } + while(1); +} + +void EXTI3_IRQHandler(void) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_3) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_3); + } + while(1); +} + + +/** +* @brief This function handles External lines 15 to 4 interrupt request. +* @param None +* @retval None +*/ +void EXTI9_5_IRQHandler(void) +{ + /* EXTI line 7 interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(RADIO_GPIO_3_EXTI_LINE)) + { + __HAL_GPIO_EXTI_CLEAR_IT(RADIO_GPIO_3_EXTI_LINE); + + HAL_GPIO_EXTI_Callback(RADIO_GPIO_3_EXTI_LINE); + + spirit1_interrupt_callback(); + } + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_9); + + + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8); + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_7); + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_6); + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_5); + +#ifndef LPM_ENABLE + + // if(__HAL_GPIO_EXTI_GET_IT(KEY_BUTTON_EXTI_LINE) != RESET) + // { + // __HAL_GPIO_EXTI_CLEAR_IT(KEY_BUTTON_EXTI_LINE); + // + // Set_KeyStatus(SET); + // } + // +#else /*Low Power mode enabled*/ + +#if defined(RF_STANDBY)/*if spirit1 is in standby*/ + + if(EXTI->PR & KEY_BUTTON_EXTI_LINE) + { + HAL_GPIO_EXTI_Callback(KEY_BUTTON_EXTI_LINE); + /* EXTI line 13 interrupt detected */ + if(HAL_GPIO_ReadPin(KEY_BUTTON_GPIO_PORT, KEY_BUTTON_PIN) == 0x01) //0x00 + { + HAL_GPIO_EXTI_Callback(KEY_BUTTON_EXTI_LINE); + + PushButtonStatusWakeup = SET; + PushButtonStatusData = RESET; + wakeupCounter = LPM_WAKEUP_TIME; + dataSendCounter = DATA_SEND_TIME; + dataSendCounter++; + } + __HAL_GPIO_EXTI_CLEAR_IT(KEY_BUTTON_EXTI_LINE); + } +#else /*if spirit1 is not in standby or sleep mode but MCU is in LPM*/ + + if(__HAL_GPIO_EXTI_GET_IT(KEY_BUTTON_EXTI_LINE) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(KEY_BUTTON_EXTI_LINE); + + HAL_GPIO_EXTI_Callback(KEY_BUTTON_EXTI_LINE); + + Set_KeyStatus(SET); + } +#endif +#endif +} + + + +/** +* @brief This function handles EXTI15_10_IRQHandler +* @param None +* @retval None +*/ +void EXTI15_10_IRQHandler(void) +{ + HAL_GPIO_EXTI_IRQHandler(USER_BUTTON_PIN); +} + + +/** +* @brief This function handles UART interrupt request. +* @param None +* @retval None +* @Note This function is redefined in "stm32cube_hal_init.h" and related to DMA +* used for USART data transmission +*/ + +void USART2_IRQHandler() +{ + slip_input_byte(UartHandle.Instance->DR); + return; + + //HAL_UART_IRQHandler(&UartHandle); +} + +/** +* @brief UART error callbacks +* @param UartHandle: UART handle +* @note This example shows a simple way to report transfer error, and you can +* add your own implementation. +* @retval None +*/ +void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle) +{ + // Error_Handler(); +} + + +/** +* @brief Tx Transfer completed callback +* @param UartHandle: UART handle. +* @note This example shows a simple way to report end of IT Tx transfer, and +* you can add your own implementation. +* @retval None +*/ +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *UartHandle) +{ + + +} + + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h b/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h new file mode 100644 index 000000000..de5f97558 --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file platform_config.h + * @author MCD Application Team + * @version V3.4.0 + * @date 29-June-2012 + * @brief Evaluation board specific configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PLATFORM_CONFIG_H +#define __PLATFORM_CONFIG_H + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Define the STM32F10x hardware depending on the used evaluation board */ +#ifdef USE_STM3210B_EVAL + #define USB_DISCONNECT GPIOD + #define USB_DISCONNECT_PIN GPIO_PIN_9 + #define RCC_APB2Periph_GPIO_DISCONNECT RCC_APB2Periph_GPIOD + #define EVAL_COM1_IRQHandler USART1_IRQHandler + +#elif defined (USE_STM3210E_EVAL) + #define USB_DISCONNECT GPIOB + #define USB_DISCONNECT_PIN GPIO_PIN_14 + #define RCC_APB2Periph_GPIO_DISCONNECT RCC_APB2Periph_GPIOB + #define EVAL_COM1_IRQHandler USART1_IRQHandler + +#elif defined (USE_STM3210C_EVAL) + #define USB_DISCONNECT 0 + #define USB_DISCONNECT_PIN 0 + #define RCC_APB2Periph_GPIO_DISCONNECT 0 + #define EVAL_COM1_IRQHandler USART2_IRQHandler + +#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL) + /* + For STM32L15xx devices it is possible to use the internal USB pullup + controlled by register SYSCFG_PMC (refer to RM0038 reference manual for + more details). + It is also possible to use external pullup (and disable the internal pullup) + by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h + and configuring the right pin to be used for the external pull up configuration. + To have more details on how to use an external pull up, please refer to + STM3210E-EVAL evaluation board manuals. + */ + /* Uncomment the following define to use an external pull up instead of the + integrated STM32L15xx internal pull up. In this case make sure to set up + correctly the external required hardware and the GPIO defines below.*/ +/* #define USB_USE_EXTERNAL_PULLUP */ + + #if !defined(USB_USE_EXTERNAL_PULLUP) + #define STM32L15_USB_CONNECT SYSCFG_USBPuCmd(ENABLE) + #define STM32L15_USB_DISCONNECT SYSCFG_USBPuCmd(DISABLE) + + #elif defined(USB_USE_EXTERNAL_PULLUP) + /* PA0 is chosen just as illustrating example, you should modify the defines + below according to your hardware configuration. */ + #define USB_DISCONNECT GPIOA + #define USB_DISCONNECT_PIN GPIO_PIN_0 + #define RCC_AHBPeriph_GPIO_DISCONNECT RCC_AHBPeriph_GPIOA + #define STM32L15_USB_CONNECT GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN) + #define STM32L15_USB_DISCONNECT GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN) + #endif /* USB_USE_EXTERNAL_PULLUP */ + +#ifdef USE_STM32L152_EVAL + #define EVAL_COM1_IRQHandler USART2_IRQHandler +#elif defined (USE_STM32L152D_EVAL) + #define EVAL_COM1_IRQHandler USART1_IRQHandler +#endif + +#endif /* USE_STM3210B_EVAL */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __PLATFORM_CONFIG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/uart-msg.c b/platform/stm32nucleo-spirit1/uart-msg.c new file mode 100644 index 000000000..831bd2079 --- /dev/null +++ b/platform/stm32nucleo-spirit1/uart-msg.c @@ -0,0 +1,95 @@ +/** +****************************************************************************** +* @file uart-msg.c +* @author System LAB +* @version V1.0.0 +* @date 17-June-2015 +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ + +#include "contiki.h" +#include "dev/leds.h" +#include "stm32l1xx_nucleo.h" +#include "platform-conf.h" +#include +#include "dev/slip.h" +#include "hw-config.h" +#include "stm32l1xx_hal.h" + +void UART_SendMsg(char *Msg); +extern UART_HandleTypeDef UartHandle; + +/** +* @brief Rx Transfer completed callbacks. +* @param huart: Pointer to a UART_HandleTypeDef structure that contains +* the configuration information for the specified UART module. +* @retval None +*/ + +static unsigned char databyte[1] = {0}; +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + slip_input_byte(databyte[0]); + HAL_UART_Receive_IT(&UartHandle, databyte, 1); +} + +/*---------------------------------------------------------------------------*/ +void +uart1_set_input(int (*input) (unsigned char c)) +{ + HAL_UART_Receive_IT(&UartHandle, databyte, 1); +} + +/*--------------------------------------------------------------------------*/ +void +slip_arch_init(unsigned long ubr) +{ + __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); + //uart1_set_input(slip_input_byte); +} +/*--------------------------------------------------------------------------*/ +void +slip_arch_writeb(unsigned char c) +{ + UART_SendMsg(&c); +} +/*--------------------------------------------------------------------------*/ + +/** + * @brief Send a message via UART + * @param Msg the pointer to the message to be sent + * @retval None + */ +void UART_SendMsg(char *Msg) +{ + HAL_UART_Transmit(&UartHandle, (uint8_t*)Msg, 1, 5000); +} +/*--------------------------------------------------------------------------*/ From 1116bcca2acc67f91fba9ee65ae730d881dd6169 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 24 Jul 2015 16:44:19 +0200 Subject: [PATCH 03/23] Updated README.md --- platform/stm32nucleo-spirit1/README.md | 33 +++++++++++++++----------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index ab4498f05..ab543c8bb 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -1,7 +1,7 @@ Getting Started with Contiki for STM32 Nucleo equipped with sub-1GHz SPIRIT1 expansion boards ============================================================================================= -This guide explains how get started with the STM32 Nucleo and expansion boards port to Contiki. +This guide explains how to get started with the STM32 Nucleo and expansion boards port to Contiki. Port Feature ============ @@ -47,8 +47,7 @@ http://www.st.com/web/catalog/sense_power/FM2185/SC1845/PF253167 >The X-NUCLEO-IKS01A1 is a motion MEMS and environmental sensor evaluation board. The use of this board is optional in the stm32nucleo-spirit1 Contiki platform. -Drivers are currently included in the platform folder but the sensors APIs are not -yet integrated with Contiki APIs. This feature will be provided soon. + Detailed information on the X-NUCLEO-IKS01A1 expansion board can be found at: http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261191 @@ -67,7 +66,7 @@ The platform name is: stm32nucleo-spirit1 * A toolchain to build the firmware: The port has been developed and tested with GNU Tools for ARM Embedded Processors. >The toolchain can be found at: https://launchpad.net/gcc-arm-embedded -The port was developed and tested using this version: gcc-arm-none-eabi v4.83 +The port was developed and tested using this version: gcc-arm-none-eabi v4.8.3 Examples @@ -75,7 +74,8 @@ Examples The following examples have been successfully tested: -* Examples located in: examples/ipv6/simple-udp-rpl +* examples/stm32nucleo-spirit1/sensor-demo +* examples/ipv6/simple-udp-rpl (multicast, rpl-border-router, simple-udp-rpl) Build an example @@ -101,6 +101,13 @@ This will create executables for UDP sender and receiver nodes. These executables can be programmed on the nodes using the procedure described hereafter. + +In case you need to build an example that uses the additional sensors expansion board +(for example, considering a system made of NUCLEO-L152RE, X-NUCLEO-IDS01A4 and X-NUCLEO-IKS01A1) +then the command to be run would be: + + make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 USE_SENSOR_BOARD=1 + System setup ============ @@ -109,20 +116,18 @@ This jumper provides the required voltage to the devices on the board. 2. Connect the X-NUCLEO-IDS01Ax board to the STM32 Nucleo board (NUCLEO-L152RE) from the top. -3. Power the STM32 Nucleo board using the Mini-B USB cable connected to the PC. +3. If the optional X-NUCLEO-IKS01A1 board is used, connect it on top of the X-NUCLEO-IDS01Ax board. -4. Program the firmware on the STM32 Nucleo board. +4. Power the STM32 Nucleo board using the Mini-B USB cable connected to the PC. + +5. Program the firmware on the STM32 Nucleo board. This can be done by copying the binary file on the USB mass storage that is automatically created when plugging the STM32 Nucleo board to the PC. On Linux machines the serial port device is located in /dev/ttyACMx (x depends on the PC). -5. Reset the MCU by using the reset button on the STM32 Nucleo board - - -Know Limitations -================ - -* The border router functionality is not yet fully supported. +6. Reset the MCU by using the reset button on the STM32 Nucleo board + + From ceff03ab2f7e439dffa7e2a5e1fcb4cb6b9a2138 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 24 Jul 2015 16:57:34 +0200 Subject: [PATCH 04/23] Updated README.md --- platform/stm32nucleo-spirit1/README.md | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index ab543c8bb..4b7c54b80 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -16,7 +16,7 @@ The following drivers are included: - LEDs and buttons (user, reset) - USB - SPIRIT1 sub-1GHz transceiver -- HTS221, LIS3MDL, LPS25H, LSM6DS0 sensors +- HTS221, LIS3MDL, LPS25HB, LSM6DS0 sensors Hardware Requirements @@ -34,13 +34,16 @@ http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002 >The X-NUCLEO-IDS01A4 and X-NUCLEO-IDS01A5 are STM32 Nucleo expansion boards that use the module SPSGRF-868 or SPSGRF-915 based on SPIRIT1 low data rate, low power sub-1 GHz transceiver. -The user can select the X-NUCLEO-IDS01A4 board to operate the SPIRIT1 transceiver at 868MHz -or the X-NUCLEO-IDS01A5 board to operate the SPIRIT1 transceiver at 915MHz. -Detailed information on the X-NUCLEO-IDS01A4 expansion board can be found at: + +>The user can select the X-NUCLEO-IDS01A4 board to operate the SPIRIT1 transceiver at 868MHz or the X-NUCLEO-IDS01A5 board to operate the SPIRIT1 transceiver at 915MHz. + +>Detailed information on the X-NUCLEO-IDS01A4 expansion board can be found at: http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261982 -Detailed information on the X-NUCLEO-IDS01A5 expansion board can be found at: + +>Detailed information on the X-NUCLEO-IDS01A5 expansion board can be found at: http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261983 -Detailed information on the SPIRIT1 sub-1GHz transceiver can be found at: + +>Detailed information on the SPIRIT1 sub-1GHz transceiver can be found at: http://www.st.com/web/catalog/sense_power/FM2185/SC1845/PF253167 * X-NUCLEO-IKS01A1, motion MEMS and environmental sensors expansion board (OPTIONAL) @@ -48,7 +51,7 @@ http://www.st.com/web/catalog/sense_power/FM2185/SC1845/PF253167 >The X-NUCLEO-IKS01A1 is a motion MEMS and environmental sensor evaluation board. The use of this board is optional in the stm32nucleo-spirit1 Contiki platform. -Detailed information on the X-NUCLEO-IKS01A1 expansion board can be found at: +>Detailed information on the X-NUCLEO-IKS01A1 expansion board can be found at: http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261191 From b271a4a3c32746d40d8043de1121d94df0964af7 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 24 Jul 2015 17:00:32 +0200 Subject: [PATCH 05/23] Updated README.md --- platform/stm32nucleo-spirit1/README.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index 4b7c54b80..6d574010d 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -35,15 +35,15 @@ http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002 >The X-NUCLEO-IDS01A4 and X-NUCLEO-IDS01A5 are STM32 Nucleo expansion boards that use the module SPSGRF-868 or SPSGRF-915 based on SPIRIT1 low data rate, low power sub-1 GHz transceiver. ->The user can select the X-NUCLEO-IDS01A4 board to operate the SPIRIT1 transceiver at 868MHz or the X-NUCLEO-IDS01A5 board to operate the SPIRIT1 transceiver at 915MHz. + >The user can select the X-NUCLEO-IDS01A4 board to operate the SPIRIT1 transceiver at 868MHz or the X-NUCLEO-IDS01A5 board to operate the SPIRIT1 transceiver at 915MHz. ->Detailed information on the X-NUCLEO-IDS01A4 expansion board can be found at: + >Detailed information on the X-NUCLEO-IDS01A4 expansion board can be found at: http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261982 ->Detailed information on the X-NUCLEO-IDS01A5 expansion board can be found at: + >Detailed information on the X-NUCLEO-IDS01A5 expansion board can be found at: http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261983 ->Detailed information on the SPIRIT1 sub-1GHz transceiver can be found at: + >Detailed information on the SPIRIT1 sub-1GHz transceiver can be found at: http://www.st.com/web/catalog/sense_power/FM2185/SC1845/PF253167 * X-NUCLEO-IKS01A1, motion MEMS and environmental sensors expansion board (OPTIONAL) @@ -51,7 +51,7 @@ http://www.st.com/web/catalog/sense_power/FM2185/SC1845/PF253167 >The X-NUCLEO-IKS01A1 is a motion MEMS and environmental sensor evaluation board. The use of this board is optional in the stm32nucleo-spirit1 Contiki platform. ->Detailed information on the X-NUCLEO-IKS01A1 expansion board can be found at: + >Detailed information on the X-NUCLEO-IKS01A1 expansion board can be found at: http://www.st.com/web/catalog/tools/FM146/CL2167/SC2006/PF261191 @@ -63,12 +63,12 @@ Software Requirements The following software are needed: * ST port of Contiki for STM32 Nucleo and expansion boards. ->The port is installed automatically when the Contiki repository is cloned. + >The port is installed automatically when the Contiki repository is cloned. The platform name is: stm32nucleo-spirit1 * A toolchain to build the firmware: The port has been developed and tested with GNU Tools for ARM Embedded Processors. ->The toolchain can be found at: https://launchpad.net/gcc-arm-embedded + >The toolchain can be found at: https://launchpad.net/gcc-arm-embedded The port was developed and tested using this version: gcc-arm-none-eabi v4.8.3 From 211d410d86c9b1bdd2c1cacbc087ea7985a296b4 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 24 Jul 2015 18:19:46 +0200 Subject: [PATCH 06/23] USE_SUBGHZ_BOARD fix in Makefile.compile-test --- regression-tests/Makefile.compile-test | 1 + 1 file changed, 1 insertion(+) diff --git a/regression-tests/Makefile.compile-test b/regression-tests/Makefile.compile-test index 4ca4e3fd7..c32705434 100644 --- a/regression-tests/Makefile.compile-test +++ b/regression-tests/Makefile.compile-test @@ -41,6 +41,7 @@ define dooneexample @echo Building example $(3): $(1) for target $(2) @((cd $(EXAMPLESDIR)/$(1); \ export STM32W_CPUREV=CC; \ + export USE_SUBGHZ_BOARD=IDS01A5; \ make TARGET=$(2) clean && make TARGET=$(2)) > \ $(3)-$(subst /,-,$(1))$(2).report 2>&1 && \ (echo $(1) $(2): OK | tee $(3)-$(subst /,-,$(1))$(2).summary) || \ From b61152bfa1dc40417b3bea4e5876b3b79601c850 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 24 Jul 2015 19:54:05 +0200 Subject: [PATCH 07/23] I/O libraries --- .gitignore | 1 - cpu/arm/stm32l152/e_stdio_intonly_thumb2.a | Bin 0 -> 38442 bytes cpu/arm/stm32l152/e_stdio_thumb2.a | Bin 0 -> 39964 bytes cpu/arm/stm32l152/smallprintf_thumb2.a | Bin 0 -> 8048 bytes 4 files changed, 1 deletion(-) create mode 100644 cpu/arm/stm32l152/e_stdio_intonly_thumb2.a create mode 100644 cpu/arm/stm32l152/e_stdio_thumb2.a create mode 100644 cpu/arm/stm32l152/smallprintf_thumb2.a diff --git a/.gitignore b/.gitignore index ca86d3acd..4899b754e 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,3 @@ -*.a *.bin *.map *.png diff --git a/cpu/arm/stm32l152/e_stdio_intonly_thumb2.a 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zA(mlH&ubgu{B#l43Ep|54i?O7*FeF1i0SeYjQ2=@e^o-|5?8Ab0O2{QBNS}kAF$ZLNPe7kB?@oi9Yc_dz zE$BV3TGk$D4+%N@29y^;!rc#zcy>;Og5QhZk1>Jw#^?jcDUZY?&5l8gRoQ#6;eVBP zzY}vzfFDXit{P;_%d2qWRARHNNtl;U&EqX<9-pae$5#u}w-U_TkuWA4tSpyaXEOFN zGEG@Y7(YDC#K{CVo+Th+jBst^Ily=?i#9jL)zxc>xIuI L1n-OTVAK2u{|0W_ literal 0 HcmV?d00001 From bb08369b0187321e0d858f2a5b4426d054d70f9e Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Mon, 27 Jul 2015 14:08:07 +0200 Subject: [PATCH 08/23] Regression tests fixes and Readme update. --- platform/stm32nucleo-spirit1/README.md | 5 +++++ regression-tests/01-compile-base/Makefile | 4 +--- regression-tests/15-compile-arm-apcs-ports/Makefile | 1 - 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index 6d574010d..313a8d3c0 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -102,6 +102,11 @@ If the X-NUCLEO-IDS01A5 sub-1GHz RF expansion board is used, the following must This will create executables for UDP sender and receiver nodes. +In order to generate binary files that can be flashed on the STM32 Nucleo the following command must be run: + + arm-none-eabi-objcopy -O binary unicast-sender.stm32nucleo-spirit1 unicast-sender.bin + arm-none-eabi-objcopy -O binary unicast-receiver.stm32nucleo-spirit1 unicast-receiver.bin + These executables can be programmed on the nodes using the procedure described hereafter. diff --git a/regression-tests/01-compile-base/Makefile b/regression-tests/01-compile-base/Makefile index 878d4324a..b6410c780 100644 --- a/regression-tests/01-compile-base/Makefile +++ b/regression-tests/01-compile-base/Makefile @@ -2,7 +2,6 @@ EXAMPLESDIR=../../examples TOOLSDIR=../../tools EXAMPLES = \ -hello-world/stm32nucleo-spirit1 \ hello-world/avr-raven \ hello-world/exp5438 \ hello-world/eval-adf7xxxmb4z \ @@ -15,7 +14,6 @@ hello-world/z1 \ eeprom-test/native \ collect/sky \ er-rest-example/sky \ -er-rest-example/stm32nucleo-spirit1 \ example-shell/native \ netperf/sky \ powertrace/sky \ @@ -36,7 +34,7 @@ wget/minimal-net \ z1/z1 \ settings-example/avr-raven \ ipv6/multicast/sky \ -ipv6/multicast/stm32nucleo-spirit1 \ + TOOLS= diff --git a/regression-tests/15-compile-arm-apcs-ports/Makefile b/regression-tests/15-compile-arm-apcs-ports/Makefile index 61f37d47e..e73a9a39f 100644 --- a/regression-tests/15-compile-arm-apcs-ports/Makefile +++ b/regression-tests/15-compile-arm-apcs-ports/Makefile @@ -4,7 +4,6 @@ TOOLSDIR=../../tools EXAMPLES = \ hello-world/econotag \ hello-world/mbxxx \ -hello-world/stm32nucleo-spirit1 \ ipv6/rpl-border-router/econotag \ er-rest-example/econotag \ webserver-ipv6/econotag \ From 711dd02a9c85a4be28b2dc82422b8d474f1e16c8 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Wed, 29 Jul 2015 12:55:30 +0200 Subject: [PATCH 09/23] Improve UART IRQ management. --- .../stm32cube-hal/Src/stm32l1xx_it.c | 25 ++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c index 915263370..4ad2038c0 100644 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c +++ b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c @@ -41,6 +41,7 @@ #include "radio_gpio.h" #include "spirit1.h" + extern UART_HandleTypeDef UartHandle; /** @addtogroup STM32L1xx_HAL_Examples * @{ @@ -319,10 +320,28 @@ void EXTI15_10_IRQHandler(void) void USART2_IRQHandler() { - slip_input_byte(UartHandle.Instance->DR); - return; + UART_HandleTypeDef *huart = &UartHandle; - //HAL_UART_IRQHandler(&UartHandle); + if(__HAL_UART_GET_FLAG(huart, UART_FLAG_PE)){ + __HAL_UART_CLEAR_PEFLAG(huart); + } + + if(__HAL_UART_GET_FLAG(huart, UART_FLAG_FE)){ + __HAL_UART_CLEAR_FEFLAG(huart); + } + + if(__HAL_UART_GET_FLAG(huart, UART_FLAG_NE)){ + __HAL_UART_CLEAR_NEFLAG(huart); + } + + if(__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE)){ + __HAL_UART_CLEAR_OREFLAG(&UartHandle); + } + + if(__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)){ + slip_input_byte(UartHandle.Instance->DR); + __HAL_UART_GET_IT_SOURCE(&UartHandle, UART_IT_RXNE); + } } /** From 62c33260bd109b771426d517713ed360baffd5ab Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 31 Jul 2015 17:11:27 +0200 Subject: [PATCH 10/23] Modified structure to use a sub-module for platform APIs --- .gitmodules | 3 + .../CMSIS END USER LICENCE AGREEMENT.pdf | Bin 24914 -> 0 bytes cpu/arm/stm32l152/CMSIS/README.txt | 37 - cpu/arm/stm32l152/CMSIS/index.html | 14 - cpu/arm/stm32l152/CMSIS/stm32l152xb.h | 5300 -------------- cpu/arm/stm32l152/CMSIS/stm32l152xba.h | 5312 -------------- cpu/arm/stm32l152/CMSIS/stm32l152xc.h | 5793 --------------- cpu/arm/stm32l152/CMSIS/stm32l152xca.h | 5981 ---------------- cpu/arm/stm32l152/CMSIS/stm32l152xd.h | 6355 ----------------- cpu/arm/stm32l152/CMSIS/stm32l152xe.h | 6016 ---------------- cpu/arm/stm32l152/CMSIS/stm32l1xx.h | 247 - cpu/arm/stm32l152/CMSIS/system_stm32l1xx.c | 416 -- cpu/arm/stm32l152/CMSIS/system_stm32l1xx.h | 121 - cpu/arm/stm32l152/Makefile.stm32l152 | 70 +- cpu/arm/stm32l152/Makefile.stm32l152.gnu | 4 +- cpu/arm/stm32l152/Makefile.stm32l152.iar | 6 +- cpu/arm/stm32l152/STM32L152RETx_FLASH.ld | 169 - .../STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h | 955 --- .../Inc/stm32l1xx_hal_adc.h | 1107 --- .../Inc/stm32l1xx_hal_adc_ex.h | 693 -- .../Inc/stm32l1xx_hal_comp.h | 520 -- .../Inc/stm32l1xx_hal_comp_ex.h | 336 - .../Inc/stm32l1xx_hal_conf_template.h | 291 - .../Inc/stm32l1xx_hal_cortex.h | 220 - .../Inc/stm32l1xx_hal_crc.h | 192 - .../Inc/stm32l1xx_hal_cryp.h | 411 -- .../Inc/stm32l1xx_hal_cryp_ex.h | 98 - .../Inc/stm32l1xx_hal_dac.h | 385 - .../Inc/stm32l1xx_hal_dac_ex.h | 205 - .../Inc/stm32l1xx_hal_def.h | 195 - .../Inc/stm32l1xx_hal_dma.h | 444 -- .../Inc/stm32l1xx_hal_dma_ex.h | 248 - .../Inc/stm32l1xx_hal_flash.h | 385 - .../Inc/stm32l1xx_hal_flash_ex.h | 975 --- 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CMSIS Documentation. - - - diff --git a/cpu/arm/stm32l152/CMSIS/stm32l152xb.h b/cpu/arm/stm32l152/CMSIS/stm32l152xb.h deleted file mode 100644 index 8e0f9327b..000000000 --- a/cpu/arm/stm32l152/CMSIS/stm32l152xb.h +++ /dev/null @@ -1,5300 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152xb.h - * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l152xb - * @{ - */ - -#ifndef __STM32L152xB_H -#define __STM32L152xB_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l152xba - * @{ - */ - -#ifndef __STM32L152xBA_H -#define __STM32L152xBA_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l152xc - * @{ - */ - -#ifndef __STM32L152xC_H -#define __STM32L152xC_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ - TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ - DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ - COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l152xca - * @{ - */ - -#ifndef __STM32L152xCA_H -#define __STM32L152xCA_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ - TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ - DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ - COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l152xd - * @{ - */ - -#ifndef __STM32L152xD_H -#define __STM32L152xD_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ - SDIO_IRQn = 45, /*!< SDIO global Interrupt */ - TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ - UART4_IRQn = 48, /*!< UART4 global Interrupt */ - UART5_IRQn = 49, /*!< UART5 global Interrupt */ - DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ - COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l152xe - * @{ - */ - -#ifndef __STM32L152xE_H -#define __STM32L152xE_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ - TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ - UART4_IRQn = 48, /*!< UART4 global Interrupt */ - UART5_IRQn = 49, /*!< UART5 global Interrupt */ - DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ - COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! 0x7C */ - __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */ - __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */ -} OB_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -/** - * @brief General Purpose IO - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ -} GPIO_TypeDef; - -/** - * @brief SysTem Configuration - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ - __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief LCD - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ - __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ - __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ - __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ -} LCD_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ - __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ - __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ - __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ -} RCC_TypeDef; - -/** - * @brief Routing Interface - */ - -typedef struct -{ - __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ - __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ -} RI_TypeDef; - -/** - * @brief Real-Time Clock - */ -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ - __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ - __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ - __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ - __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ - __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ - __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ - __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ - __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ - __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ - __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ - __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ - __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ -} RTC_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ - __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - uint32_t RESERVED12; /*!< Reserved, 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - uint32_t RESERVED17; /*!< Reserved, 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -} TIM_TypeDef; -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Device - */ - -typedef struct -{ - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ - __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ - __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ - __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ - __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ - __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ - __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ - __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ - __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ - __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ - __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ - __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ -} USB_TypeDef; - -/** - * @brief Window WATCHDOG - */ -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Device - */ -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define FLASH_BANK2_BASE ((uint32_t)0x08040000) /*!< FLASH BANK2 base address in the alias region */ -#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH BANK1 address */ -#define FLASH_BANK2_END ((uint32_t)0x0807FFFF) /*!< Program end FLASH BANK2 address */ -#define FLASH_EEPROM_END ((uint32_t)0x08083FFF) /*!< FLASH EEPROM end address (16KB) */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) -#define LCD_BASE (APB1PERIPH_BASE + 0x00002400) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800) -#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x00005000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) - -/* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ - -/* USB device FS SRAM */ -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000) -#define DAC_BASE (APB1PERIPH_BASE + 0x00007400) -#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00) -#define RI_BASE (APB1PERIPH_BASE + 0x00007C04) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C) - -/*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) -#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800) -#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00) -#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400) -#define ADC_BASE (APB2PERIPH_BASE + 0x00002700) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800) - -/*!< AHB peripherals */ -#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400) -#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800) -#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000) -#define RCC_BASE (AHBPERIPH_BASE + 0x00003800) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */ -#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ -#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058) -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -/* USB device FS */ -#define USB ((USB_TypeDef *) USB_BASE) -/* USB device FS SRAM */ -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define COMP ((COMP_TypeDef *) COMP_BASE) -#define COMP1 ((COMP_TypeDef *) COMP_BASE) -#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001)) -#define RI ((RI_TypeDef *) RI_BASE) -#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001)) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - - /** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ -#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ -#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ -#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ -#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ -#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ - -#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ -#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ -#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ -#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ -#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ -#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ -#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ -#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ -#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ -#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ -#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ -#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ -#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR3 register *******************/ -#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ -#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ -#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ -#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ -#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ -#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ -#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ -#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ -#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ -#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ -#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR4 register *******************/ -#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR5 register *******************/ -#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ - -/****************** Bit definition for ADC_SMPR0 register *******************/ -#define ADC_SMPR0_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */ -#define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR0_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */ -#define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -/******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ -#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ - -/******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/******************************************************************************/ -/* */ -/* Analog Comparators (COMP) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for COMP_CSR register ********************/ -#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ -#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ -#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ -#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ -#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ -#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */ -#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ - -#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ -#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ -#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ -#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ -#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ -#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ -#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ -#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ -#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ - -#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ -#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ -#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ - -/******************************************************************************/ -/* */ -/* Operational Amplifier (OPAMP) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for OPAMP_CSR register ******************/ -#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ -#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ -#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ -#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ -#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ -#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ -#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ -#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ -#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ -#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ -#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ -#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ -#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ -#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ -#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ -#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ -#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ -#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ -#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ -#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ - -/******************* Bit definition for OPAMP_OTR register ******************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ -#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ - -/******************* Bit definition for OPAMP_LPOTR register ****************/ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ -#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ -#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter (DAC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE) - /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ - /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ - /* #define STM32L100xC */ /*!< STM32L100RC Devices */ - /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ - /* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ - /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ - /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ - /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ - /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ - /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ - /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ - /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ - /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ - /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ - /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ - /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ - /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ - /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ - /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V2.0.0 - */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ - |(__CMSIS_DEVICE_HAL_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L100xB) - #include "stm32l100xb.h" -#elif defined(STM32L100xBA) - #include "stm32l100xba.h" -#elif defined(STM32L100xC) - #include "stm32l100xc.h" -#elif defined(STM32L151xB) - #include "stm32l151xb.h" -#elif defined(STM32L151xBA) - #include "stm32l151xba.h" -#elif defined(STM32L151xC) - #include "stm32l151xc.h" -#elif defined(STM32L151xCA) - #include "stm32l151xca.h" -#elif defined(STM32L151xD) - #include "stm32l151xd.h" -#elif defined(STM32L151xE) - #include "stm32l151xe.h" -#elif defined(STM32L152xB) - #include "stm32l152xb.h" -#elif defined(STM32L152xBA) - #include "stm32l152xba.h" -#elif defined(STM32L152xC) - #include "stm32l152xc.h" -#elif defined(STM32L152xCA) - #include "stm32l152xca.h" -#elif defined(STM32L152xD) - #include "stm32l152xd.h" -#elif defined(STM32L152xE) - #include "stm32l152xe.h" -#elif defined(STM32L162xC) - #include "stm32l162xc.h" -#elif defined(STM32L162xCA) - #include "stm32l162xca.h" -#elif defined(STM32L162xD) - #include "stm32l162xd.h" -#elif defined(STM32L162xE) - #include "stm32l162xe.h" -#else - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.c b/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.c deleted file mode 100644 index 4bd19a874..000000000 --- a/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.c +++ /dev/null @@ -1,416 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l1xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** @addtogroup STM32L1xx_System_Private_Includes - * @{ - */ - -#include "stm32l1xx.h" - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Defines - * @{ - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM32L152D_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -uint32_t SystemCoreClock = 32000000; -__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; -__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI - * value as defined by the MSI range. - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - case 0x04: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x08: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x0C: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; - - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - - if (pllsource == 0x00) - { - /* HSI oscillator clock selected as PLL clock entry */ - SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); - } - else - { - /* HSE selected as PLL clock entry */ - SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); - } - break; - default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in SystemInit() function before jump to main. - * This function configures the external SRAM mounted on STM32L152D_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ - | PD15 <-> FSMC_D1 |--------------------+ - +-------------------+ -*/ - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHBENR = 0x000080D8; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00CC00CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A0A; - /* Configure PDx pins speed to 40 MHz */ - GPIOD->OSPEEDR = 0xFFFF0F0F; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 40 MHz */ - GPIOE->OSPEEDR = 0xFFFFC00F; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 40 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x00000C00; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00200AAA; - /* Configure PGx pins speed to 40 MHz */ - GPIOG->OSPEEDR = 0x00300FFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHBENR = 0x400080D8; - - /* Configure and enable Bank1_SRAM3 */ - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000300; - FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; -/* - Bank1_SRAM3 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 3; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); -*/ - -} -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.h b/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.h deleted file mode 100644 index 3ad18770d..000000000 --- a/cpu/arm/stm32l152/CMSIS/system_stm32l1xx.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.h - * @author MCD Application Team - * @version V2.0.0 - * @date 5-September-2014 - * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L1XX_H -#define __SYSTEM_STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L1xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L1XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/Makefile.stm32l152 b/cpu/arm/stm32l152/Makefile.stm32l152 index a6011749d..c0ac54a43 100644 --- a/cpu/arm/stm32l152/Makefile.stm32l152 +++ b/cpu/arm/stm32l152/Makefile.stm32l152 @@ -1,17 +1,12 @@ -# Makefile for the STM32L152VB Cortex M3 medium-density microcontroller -# author Marcus Lunden +# Makefile for the STM32L152 Cortex M3 medium-density microcontroller .SUFFIXES: # CPU folder CONTIKI_CPU=$(CONTIKI)/cpu/arm/stm32l152 -# Source folders for ST HAL libraries, ARM CMSIS and IAR conf files -CONTIKI_CPU_DIRS = . \ - STM32L1xx_HAL_Driver \ - STM32L1xx_HAL_Driver/Src \ - CMSIS \ - STM32L1xx_HAL_Driver/Inc +# Source folders for contiki cpu files +CONTIKI_CPU_DIRS = . # source files: proprietary sources for startup. Refer to CMSIS docs. PROP_SYS_ARCH_C = system_stm32l1xx.c @@ -31,7 +26,7 @@ CONTIKI_CPU_ARCH= watchdog.c \ ifdef GCC CONTIKI_CPU_PORT= sysmem.c \ - console.c \ + console.c \ crt.c \ uart.c else @@ -46,61 +41,16 @@ UIPDRIVERS= ELFLOADER= -STM32L1XX_HAL =\ - stm32l1xx_hal.c\ - stm32l1xx_hal_adc_ex.c\ - stm32l1xx_hal_adc.c\ - stm32l1xx_hal_comp.c\ - stm32l1xx_hal_cortex.c\ - stm32l1xx_hal_crc.c\ - stm32l1xx_hal_cryp_ex.c\ - stm32l1xx_hal_cryp.c\ - stm32l1xx_hal_dac_ex.c\ - stm32l1xx_hal_dac.c\ - stm32l1xx_hal_dma.c\ - stm32l1xx_hal_flash_ex.c\ - stm32l1xx_hal_flash.c\ - stm32l1xx_hal_flash_ramfunc.c\ - stm32l1xx_hal_gpio.c\ - stm32l1xx_hal_i2c.c\ - stm32l1xx_hal_i2s.c\ - stm32l1xx_hal_irda.c\ - stm32l1xx_hal_iwdg.c\ - stm32l1xx_hal_lcd.c\ - stm32l1xx_hal_nor.c\ - stm32l1xx_hal_opamp_ex.c\ - stm32l1xx_hal_opamp.c\ - stm32l1xx_hal_pcd_ex.c\ - stm32l1xx_hal_pcd.c\ - stm32l1xx_hal_pwr_ex.c\ - stm32l1xx_hal_pwr.c\ - stm32l1xx_hal_rcc_ex.c\ - stm32l1xx_hal_rcc.c\ - stm32l1xx_hal_rtc_ex.c\ - stm32l1xx_hal_rtc.c\ - stm32l1xx_hal_sd.c\ - stm32l1xx_hal_smartcard.c\ - stm32l1xx_hal_spi_ex.c\ - stm32l1xx_hal_spi.c\ - stm32l1xx_hal_sram.c\ - stm32l1xx_hal_tim_ex.c\ - stm32l1xx_hal_tim.c\ - stm32l1xx_hal_uart.c\ - stm32l1xx_hal_usart.c\ - stm32l1xx_hal_wwdg.c\ - stm32l1xx_ll_fsmc.c\ - stm32l1xx_ll_sdmmc.c - - - # add CPU folder to search path for .s (assembler) files -vpath %.s $(CONTIKI_CPU) - - +ifdef GCC +vpath %.s $(CONTIKI)/platform/$(TARGET)/stm32cube-lib/stm32cube-prj/startup_files/gcc +else +vpath %.s $(CONTIKI)/platform/$(TARGET)/stm32cube-lib/stm32cube-prj/startup_files/iar +endif # include all files above ssubst = ${patsubst %.s,%.o,${patsubst %.s79,%.o,$(1)}} -CONTIKI_TARGET_SOURCEFILES += $(PROP_SYS_ARCH_C) $(PROP_USB_ARCH) $(CONTIKI_CPU_ARCH) $(CONTIKI_CPU_PORT) $(ELFLOADER) $(UIPDRIVERS) $(STM32L1XX_HAL) +CONTIKI_TARGET_SOURCEFILES += $(PROP_SYS_ARCH_C) $(PROP_USB_ARCH) $(CONTIKI_CPU_ARCH) $(CONTIKI_CPU_PORT) $(ELFLOADER) $(UIPDRIVERS) CONTIKI_SOURCEFILES += $(CONTIKI_TARGET_SOURCEFILES) PROJECT_OBJECTFILES += ${addprefix $(OBJECTDIR)/,$(CONTIKI_TARGET_MAIN:.c=.o)} PROJECT_OBJECTFILES += ${addprefix $(OBJECTDIR)/,${call ssubst, $(PROP_SYS_ARCH_S)}} diff --git a/cpu/arm/stm32l152/Makefile.stm32l152.gnu b/cpu/arm/stm32l152/Makefile.stm32l152.gnu index bb72d88f8..a6c62e7c6 100644 --- a/cpu/arm/stm32l152/Makefile.stm32l152.gnu +++ b/cpu/arm/stm32l152/Makefile.stm32l152.gnu @@ -20,7 +20,7 @@ STRIP = arm-none-eabi-strip ifndef LDSCRIPT -LDSCRIPT = $(CONTIKI_CPU)/STM32L152RETx_FLASH.ld +LDSCRIPT = $(CONTIKI)/platform/$(TARGET)/stm32cube-lib/stm32cube-prj/linker/gcc/STM32L152RETx_FLASH.ld endif #ASFLAGS += -mcpu=cortex-m3 -mthumb @@ -44,7 +44,7 @@ CFLAGS+=\ LDFLAGS += -Wl,-Map=contiki-$(TARGET).map,--cref,--no-warn-mismatch -LDLIBS += $(CONTIKI_CPU)/smallprintf_thumb2.a +LDLIBS += $(CONTIKI_CPU)/lib/smallprintf_thumb2.a diff --git a/cpu/arm/stm32l152/Makefile.stm32l152.iar b/cpu/arm/stm32l152/Makefile.stm32l152.iar index 17165b748..5e6758313 100644 --- a/cpu/arm/stm32l152/Makefile.stm32l152.iar +++ b/cpu/arm/stm32l152/Makefile.stm32l152.iar @@ -1,5 +1,4 @@ -PROP_SYS_ARCH_S = \ - startup_stm32l152xe-IAR.s +PROP_SYS_ARCH_S = startup_stm32l152xe.s # Compiler definitions @@ -56,8 +55,7 @@ AROPTS= --create --output # ----------linker flags # this will also generate log and symbol map files -#MGR: check which -ICF_FILE="$(CONTIKI_CPU)/stm32l1xx_flash.icf" +ICF_FILE="$(CONTIKI)/platform/$(TARGET)/stm32cube-lib/stm32cube-prj/linker/iar/stm32l1xx_flash.icf" LDFLAGS+= \ --config $(ICF_FILE) \ --entry __iar_program_start \ diff --git a/cpu/arm/stm32l152/STM32L152RETx_FLASH.ld b/cpu/arm/stm32l152/STM32L152RETx_FLASH.ld deleted file mode 100644 index 7de0e5c58..000000000 --- a/cpu/arm/stm32l152/STM32L152RETx_FLASH.ld +++ /dev/null @@ -1,169 +0,0 @@ -/* -***************************************************************************** -** - -** File : LinkerScript.ld -** -** Abstract : Linker script for STM32L152RETx Device with -** 512KByte FLASH, 80KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Ac6. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Ac6 permit registered System Workbench for MCU users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the System Workbench for MCU toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20014000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h deleted file mode 100644 index f6f71d969..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h +++ /dev/null @@ -1,955 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_H -#define __STM32L1xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_conf.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - -/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG - * @{ - */ - -/** @defgroup SYSCFG_BootMode Boot Mode - * @{ - */ - -#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) -#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0) -#if defined(FSMC_R_BASE) -#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1) -#endif /* FSMC_R_BASE */ -#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RI_Constants RI: Routing Interface - * @{ - */ - -/** @defgroup RI_InputCapture Input Capture - * @{ - */ - -#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ -#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ -#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ -#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ - -/** - * @} - */ - -/** @defgroup TIM_Select TIM Select - * @{ - */ - -#define TIM_SELECT_NONE ((uint32_t)0x00000000) /*!< None selected */ -#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */ -#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */ -#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */ - -#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \ - ((__TIM__) == TIM_SELECT_TIM2) || \ - ((__TIM__) == TIM_SELECT_TIM3) || \ - ((__TIM__) == TIM_SELECT_TIM4)) - -/** - * @} - */ - -/** @defgroup RI_InputCaptureRouting Input Capture Routing - * @{ - */ - /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ -#define RI_INPUTCAPTUREROUTING_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */ -#define RI_INPUTCAPTUREROUTING_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */ -#define RI_INPUTCAPTUREROUTING_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */ -#define RI_INPUTCAPTUREROUTING_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */ -#define RI_INPUTCAPTUREROUTING_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */ -#define RI_INPUTCAPTUREROUTING_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */ -#define RI_INPUTCAPTUREROUTING_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */ -#define RI_INPUTCAPTUREROUTING_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */ -#define RI_INPUTCAPTUREROUTING_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */ -#define RI_INPUTCAPTUREROUTING_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */ -#define RI_INPUTCAPTUREROUTING_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */ -#define RI_INPUTCAPTUREROUTING_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */ -#define RI_INPUTCAPTUREROUTING_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */ -#define RI_INPUTCAPTUREROUTING_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */ -#define RI_INPUTCAPTUREROUTING_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */ -#define RI_INPUTCAPTUREROUTING_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */ - -#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15)) - -/** - * @} - */ - -/** @defgroup RI_IOSwitch IO Switch - * @{ - */ -#define RI_ASCR1_REGISTER ((uint32_t)0x80000000) -/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ -#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0) -#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1) -#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2) -#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3) -#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4) -#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5) -#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6) -#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7) -#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8) -#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9) -#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10) -#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11) -#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12) -#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13) -#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14) -#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15) -#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18) -#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19) -#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20) -#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21) -#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22) -#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23) -#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24) -#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25) -#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */ -#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ -#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27) -#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28) -#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29) -#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30) -#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31) -#endif /* RI_ASCR2_CH1b */ - -/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ -#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1) -#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2) -#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3) -#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4) -#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1) -#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2) -#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1) -#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2) -#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3) -#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1) -#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2) -#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3) -#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */ -#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b) -#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ -#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b) -#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b) -#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b) -#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b) -#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b) -#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b) -#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b) -#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b) -#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b) -#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b) -#endif /* RI_ASCR2_CH1b */ -#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3) -#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4) -#endif /* RI_ASCR2_CH0b */ - - -#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ - -#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ - ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12b)) - -#else /* !RI_ASCR2_CH1b */ - -#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */ - -#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ - ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b)) - -#else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */ - -#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ - ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)) - -#endif /* RI_ASCR2_CH0b */ -#endif /* RI_ASCR2_CH1b */ - -/** - * @} - */ - -/** @defgroup RI_Pin PIN define - * @{ - */ -#define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU - * @{ - */ - -/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode - * @brief Freeze/Unfreeze Peripherals in Debug mode - * @{ - */ - -/** - * @brief TIM2 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_FREEZE_TIM2_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_UNFREEZE_TIM2_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#endif - -/** - * @brief TIM3 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_FREEZE_TIM3_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_UNFREEZE_TIM3_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#endif - -/** - * @brief TIM4 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#define __HAL_FREEZE_TIM4_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#define __HAL_UNFREEZE_TIM4_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#endif - -/** - * @brief TIM5 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#define __HAL_FREEZE_TIM5_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#define __HAL_UNFREEZE_TIM5_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#endif - -/** - * @brief TIM6 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_FREEZE_TIM6_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_UNFREEZE_TIM6_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#endif - -/** - * @brief TIM7 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_FREEZE_TIM7_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_UNFREEZE_TIM7_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#endif - -/** - * @brief RTC Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_FREEZE_RTC_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_UNFREEZE_RTC_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) -#endif - -/** - * @brief WWDG Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_FREEZE_WWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_UNFREEZE_WWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#endif - -/** - * @brief IWDG Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_FREEZE_IWDG_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_UNFREEZE_IWDG_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#endif - -/** - * @brief I2C1 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#endif - -/** - * @brief I2C2 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#endif - -/** - * @brief TIM9 Peripherals Debug mode - */ -#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#define __HAL_FREEZE_TIM9_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#define __HAL_UNFREEZE_TIM9_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#endif - -/** - * @brief TIM10 Peripherals Debug mode - */ -#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#define __HAL_FREEZE_TIM10_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#define __HAL_UNFREEZE_TIM10_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#endif - -/** - * @brief TIM11 Peripherals Debug mode - */ -#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#define __HAL_FREEZE_TIM11_DBGMCU() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#define __HAL_UNFREEZE_TIM11_DBGMCU() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#endif - -/** - * @brief Enables or disables the output of internal reference voltage - * (VREFINT) on I/O pin. - * The VREFINT output can be routed to any I/O in group 3: - * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). - * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). - * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), - * CH1b (PF11) or CH2b (PF12). - * Note: Comparator peripheral clock must be preliminarility enabled, - * either in COMP user function "HAL_COMP_MspInit()" (should be - * done if comparators are used) or by direct clock enable: - * Refer to macro "__COMP_CLK_ENABLE()". - * Note: In addition with this macro, Vrefint output buffer must be - * connected to the selected I/O pin. Refer to macro - * "__HAL_RI_IOSWITCH_CLOSE()". - * @note ENABLE: Internal reference voltage connected to I/O group 3 - * @note DISABLE: Internal reference voltage disconnected from I/O group 3 - * @retval None - */ -#define __HAL_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) -#define __HAL_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG - * @{ - */ - -/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration - * @{ - */ - -/** - * @brief Main Flash memory mapped at 0x00000000 - */ -#define __HAL_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) - -/** @brief System Flash memory mapped at 0x00000000 - */ -#define __HAL_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) - -/** @brief Embedded SRAM mapped at 0x00000000 - */ -#define __HAL_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) - -#if defined(FSMC_R_BASE) -/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 - */ -#define __HAL_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) - -#endif /* FSMC_R_BASE */ - -/** - * @brief Returns the boot mode as configured by user. - * @retval The boot mode as configured by user. The returned value can be one - * of the following values: - * @arg SYSCFG_BOOT_MAINFLASH - * @arg SYSCFG_BOOT_SYSTEMFLASH - * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD) - * @arg SYSCFG_BOOT_SRAM - */ -#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE) - -/** - * @} - */ - -/** @defgroup SYSCFG_USBConfig USB DP line Configuration - * @{ - */ - -/** - * @brief Control the internal pull-up on USB DP line. - */ -#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) - -#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RI_Macris RI: Routing Interface - * @{ - */ - -/** @defgroup RI_InputCaputureConfig Input Capture configuration - * @{ - */ - -/** - * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin. - * @param __TIMSELECT__: Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__: selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * e.g. - * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1) - * allows routing of Input capture IC1 of TIM2 to PA4. - * For details about correspondence between RI_INPUTCAPTUREROUTING_x - * and I/O pins refer to the parameters' description in the header file - * or refer to the product reference manual. - * @note Input capture selection bits are not reset by this function. - * To reset input capture selection bits, use SYSCFG_RIDeInit() function. - * @note The I/O should be configured in alternate function mode (AF14) using - * GPIO_PinAFConfig() function. - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \ - MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \ - }while(0) - -/** - * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin. - * @param __TIMSELECT__: Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__: selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \ - MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \ - }while(0) - -/** - * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin. - * @param __TIMSELECT__: Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__: selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \ - MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \ - }while(0) - -/** - * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin. - * @param __TIMSELECT__: Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__: selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \ - MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \ - }while(0) - -/** - * @} - */ - -/** @defgroup RI_SwitchControlConfig Switch Control configuration - * @{ - */ - -/** - * @brief Enable or disable the switch control mode. - * @note ENABLE: ADC analog switches closed if the corresponding - * I/O switch is also closed. - * When using COMP1, switch control mode must be enabled. - * @note DISABLE: ADC analog switches open or controlled by the ADC interface. - * When using the ADC for acquisition, switch control mode - * must be disabled. - * @note COMP1 comparator and ADC cannot be used at the same time since - * they share the ADC switch matrix. - * @retval None - */ -#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM) - -#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM) - -/* - * @brief Close or Open the routing interface Input Output switches. - * @param __IOSWITCH__: selects the I/O analog switch number. - * This parameter must be a value of @ref RI_IOSwitch - * @retval None - */ -#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ - if ((__IOSWITCH__) >> 31 != 0 ) \ - { \ - SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ - } \ - else \ - { \ - SET_BIT(RI->ASCR2, (__IOSWITCH__)); \ - } \ - }while(0) - -#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ - if ((__IOSWITCH__) >> 31 != 0 ) \ - { \ - CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ - } \ - else \ - { \ - CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \ - } \ - }while(0) - -#if defined (COMP_CSR_SW1) -/** - * @brief Close or open the internal switch COMP1_SW1. - * This switch connects I/O pin PC3 (can be used as ADC channel 13) - * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel - * 26) and COMP1 non-inverting input. - * Pin PC3 connection depends on another switch setting, refer to - * macro "__HAL_ADC_CHANNEL_SPEED_FAST()". - * @retval None. - */ -#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1) - -#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1) -#endif /* COMP_CSR_SW1 */ - -/** - * @} - */ - -/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation - * @{ - */ - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR1, (__IOPIN__)); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR2, (__IOPIN__)); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ - } while(0) - -#if defined (GPIOE_BASE) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR3, (__IOPIN__)); \ - } while(0) - -#endif /* GPIOE_BASE */ - -#if defined(GPIOF_BASE) || defined(GPIOG_BASE) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR4, (__IOPIN__)); \ - } while(0) - -#endif /* GPIOF_BASE || GPIOG_BASE */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HAL_Exported_Functions - * @{ - */ - -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -void HAL_EnableDBGSleepMode(void); -void HAL_DisableDBGSleepMode(void); -void HAL_EnableDBGStopMode(void); -void HAL_DisableDBGStopMode(void); -void HAL_EnableDBGStandbyMode(void); -void HAL_DisableDBGStandbyMode(void); - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h deleted file mode 100644 index e4f548339..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h +++ /dev/null @@ -1,1107 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_adc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file containing functions prototypes of ADC HAL library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_ADC_H -#define __STM32L1xx_HAL_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Types ADC Exported Types - * @{ - */ - -/** - * @brief Structure definition of ADC and regular group initialization - * @note Parameters of this structure are shared within 2 scopes: - * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. - * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. - * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled - * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. - * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler. - This parameter can be a value of @ref ADC_ClockPrescaler - Note: In case of usage of channels on injected group, ADC frequency should be low than AHB clock frequency /4 for resolution 12 or 10 bits, - AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. - Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */ - uint32_t Resolution; /*!< Configures the ADC resolution. - This parameter can be a value of @ref ADC_Resolution */ - uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) - or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). - This parameter can be a value of @ref ADC_Data_align */ - uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. - This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). - Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). - If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). - Scan direction is upward: from rank1 to rank 'n'. - This parameter can be a value of @ref ADC_Scan_mode */ - uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. - This parameter can be a value of @ref ADC_EOCSelection. - Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. - Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) - or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. - Note: If overrun feature is intending to be used in ADC mode 'interruption' (function HAL_ADC_Start_IT() ), parameter EOCSelection must be set to each conversion (this is not needed for ADC mode 'transfer by DMA', with function HAL_ADC_Start_DMA()) */ - uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous - conversion (for regular group) or previous sequence (for injected group) has been treated by user software. - This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. - This parameter can be a value of @ref ADC_LowPowerAutoWait. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed - and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. - Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */ - uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). - This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). - This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */ - uint32_t ChannelsBank; /*!< Selects the ADC channels bank. - This parameter can be a value of @ref ADC_ChannelsBank. - Note: Banks availability depends on devices categories. - Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */ - uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, - after the selected trigger occurred (software start or external trigger). - This parameter can be set to ENABLE or DISABLE. */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. - To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 28. */ -#else - uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. - To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 27. */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. - If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. - This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ - uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. - If set to ADC_SOFTWARE_START, external triggers are disabled. - If set to external trigger source, triggering is on event rising edge. - This parameter can be a value of @ref ADC_External_trigger_source_Regular */ - uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. - If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. - This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ - uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) - or in Continuous mode (DMA transfer unlimited, whatever number of conversions). - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */ -}ADC_InitTypeDef; - -/** - * @brief Structure definition of ADC channel for regular group - * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. - * ADC can be either disabled or enabled without conversion on going on regular group. - */ -typedef struct -{ - uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_channels - Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. - Maximum number of channels by device category (without taking in account each device package constraints): - STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26. - STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. - STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. - Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '. - Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */ - uint32_t Rank; /*!< Specifies the rank in the regular group sequencer - This parameter can be a value of @ref ADC_regular_rank - Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ - uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times - Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. - If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ -}ADC_ChannelConfTypeDef; - -/** - * @brief ADC Configuration analog watchdog definition - * @note The setting of these parameters with function is conditioned to ADC state. - * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. - */ -typedef struct -{ - uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. - This parameter can be a value of @ref ADC_analog_watchdog_mode. */ - uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. - This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) - This parameter can be a value of @ref ADC_channels. */ - uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. - This parameter can be set to ENABLE or DISABLE */ - uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ -}ADC_AnalogWDGConfTypeDef; - -/** - * @brief HAL ADC state machine: ADC States structure definition - */ -typedef enum -{ - HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ - HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ - HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ - HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ - HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ - HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ - HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ - HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ - HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ - HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ - HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ - HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32L1xx devices (kept for compatibility with other devices featuring several AWD) */ - HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32l1xx devices (kept for compatibility with other devices featuring several AWD) */ -}HAL_ADC_StateTypeDef; - -/** - * @brief ADC handle Structure definition - */ -typedef struct -{ - ADC_TypeDef *Instance; /*!< Register base address */ - - ADC_InitTypeDef Init; /*!< ADC required parameters */ - - __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - - HAL_LockTypeDef Lock; /*!< ADC locking object */ - - __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ - - __IO uint32_t ErrorCode; /*!< ADC Error code */ -}ADC_HandleTypeDef; -/** - * @} - */ - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_Error_Code ADC Error Code - * @{ - */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, - enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ - -/** - * @} - */ - -/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler - * @{ - */ -#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */ -#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */ -#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */ - -#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) ) -/** - * @} - */ - -/** @defgroup ADC_Resolution ADC Resolution - * @{ - */ -#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ -#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */ -#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */ -#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */ - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ - ((RESOLUTION) == ADC_RESOLUTION10b) || \ - ((RESOLUTION) == ADC_RESOLUTION8b) || \ - ((RESOLUTION) == ADC_RESOLUTION6b) ) - -#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \ - ((RESOLUTION) == ADC_RESOLUTION6b) ) -/** - * @} - */ - -/** @defgroup ADC_Data_align ADC Data_align - * @{ - */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) -#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ - ((ALIGN) == ADC_DATAALIGN_LEFT) ) -/** - * @} - */ - -/** @defgroup ADC_Scan_mode ADC Scan mode - * @{ - */ -#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) -#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) - -#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ - ((SCAN_MODE) == ADC_SCAN_ENABLE) ) -/** - * @} - */ - -/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular - * @{ - */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) -#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) -#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) - -#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) -/** - * @} - */ - -/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular - * @{ - */ -/* List of external triggers with generic trigger name, sorted by trigger */ -/* name: */ - -/* External triggers of regular group for ADC1 */ -#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3 -#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2 -#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO -#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1 -#define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3 -#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO -#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4 -#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO -#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO -#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2 -#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO -#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 - -#define ADC_SOFTWARE_START ((uint32_t)0x00000010) - -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - ((REGTRIG) == ADC_SOFTWARE_START) ) -/** - * @} - */ - -/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular - * @{ - */ - -/* List of external triggers of regular group for ADC1: */ -/* (used internally by HAL driver. To not use into HAL structure parameters) */ - -/* External triggers of regular group for ADC1 */ -#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000) -#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) -#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 )) -#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) -#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 )) -#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 )) -#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) - -/** - * @} - */ - -/** @defgroup ADC_EOCSelection ADC EOCSelection - * @{ - */ -#define EOC_SEQ_CONV ((uint32_t)0x00000000) -#define EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS) - -#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == EOC_SEQ_CONV) ) -/** - * @} - */ - -/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait - * @{ - */ -/*!< Note : For compatibility with other STM32 devices with ADC autowait */ -/* feature limited to enable or disable settings: */ -/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */ - -#define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000) -#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */ -#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */ -#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */ -#define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */ -#define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */ -#define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */ -#define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */ - -#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \ - ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) ) -/** - * @} - */ - -/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff - * @{ - */ -#define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000) -#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */ -#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */ -#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */ - -#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \ - ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \ - ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \ - ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) ) -/** - * @} - */ - - -/** @defgroup ADC_ChannelsBank ADC ChannelsBank - * @{ - */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) -#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) - -#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ - ((BANK) == ADC_CHANNELS_BANK_B) ) -#else -#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000) - -#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup ADC_channels ADC channels - * @{ - */ -/* Note: Depending on devices, some channels may not be available on package */ -/* pins. Refer to device datasheet for channels availability. */ -#define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */ -#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ -#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */ -#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */ -#define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ -#define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */ -#define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ -#define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ -#define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ -#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ -#define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */ -#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) -#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_16) || \ - ((CHANNEL) == ADC_CHANNEL_17) || \ - ((CHANNEL) == ADC_CHANNEL_18) || \ - ((CHANNEL) == ADC_CHANNEL_19) || \ - ((CHANNEL) == ADC_CHANNEL_20) || \ - ((CHANNEL) == ADC_CHANNEL_21) || \ - ((CHANNEL) == ADC_CHANNEL_22) || \ - ((CHANNEL) == ADC_CHANNEL_23) || \ - ((CHANNEL) == ADC_CHANNEL_24) || \ - ((CHANNEL) == ADC_CHANNEL_25) || \ - ((CHANNEL) == ADC_CHANNEL_26) ) -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_16) || \ - ((CHANNEL) == ADC_CHANNEL_17) || \ - ((CHANNEL) == ADC_CHANNEL_18) || \ - ((CHANNEL) == ADC_CHANNEL_19) || \ - ((CHANNEL) == ADC_CHANNEL_20) || \ - ((CHANNEL) == ADC_CHANNEL_21) || \ - ((CHANNEL) == ADC_CHANNEL_22) || \ - ((CHANNEL) == ADC_CHANNEL_23) || \ - ((CHANNEL) == ADC_CHANNEL_24) || \ - ((CHANNEL) == ADC_CHANNEL_25) || \ - ((CHANNEL) == ADC_CHANNEL_26) || \ - ((CHANNEL) == ADC_CHANNEL_27) || \ - ((CHANNEL) == ADC_CHANNEL_28) || \ - ((CHANNEL) == ADC_CHANNEL_29) || \ - ((CHANNEL) == ADC_CHANNEL_30) || \ - ((CHANNEL) == ADC_CHANNEL_31) ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup ADC_sampling_times ADC sampling times - * @{ - */ -#define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /*!< Sampling time 4 ADC clock cycles */ -#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */ -#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */ -#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */ -#define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */ -#define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */ -#define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */ -#define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */ - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_9CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_16CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_24CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_48CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_96CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_192CYCLES) || \ - ((TIME) == ADC_SAMPLETIME_384CYCLES) ) -/** - * @} - */ - -/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels - * @{ - */ -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \ - (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \ - ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \ - ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ - (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \ - ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \ - ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2) -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ - (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \ - ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ - (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \ - ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \ - ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \ - (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \ - (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \ - ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \ - ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ - (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \ - ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \ - ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1) -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ - (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \ - ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ - (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \ - ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \ - ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \ - (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \ - (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \ - ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \ - ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ - (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \ - ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \ - ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0) -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ - (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \ - ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ - (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \ - ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \ - ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) -#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \ - (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup ADC_regular_rank ADC regular rank - * @{ - */ -#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) -#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) -#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) -#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) -#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) -#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) -#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) -#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) -#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) -#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) -#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) -#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) -#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) -#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) -#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) -#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) -#define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011) -#define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012) -#define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013) -#define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014) -#define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015) -#define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016) -#define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017) -#define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018) -#define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019) -#define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A) -#define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B) -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C) - -#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_10) || \ - ((CHANNEL) == ADC_REGULAR_RANK_11) || \ - ((CHANNEL) == ADC_REGULAR_RANK_12) || \ - ((CHANNEL) == ADC_REGULAR_RANK_13) || \ - ((CHANNEL) == ADC_REGULAR_RANK_14) || \ - ((CHANNEL) == ADC_REGULAR_RANK_15) || \ - ((CHANNEL) == ADC_REGULAR_RANK_16) || \ - ((CHANNEL) == ADC_REGULAR_RANK_17) || \ - ((CHANNEL) == ADC_REGULAR_RANK_18) || \ - ((CHANNEL) == ADC_REGULAR_RANK_19) || \ - ((CHANNEL) == ADC_REGULAR_RANK_20) || \ - ((CHANNEL) == ADC_REGULAR_RANK_21) || \ - ((CHANNEL) == ADC_REGULAR_RANK_22) || \ - ((CHANNEL) == ADC_REGULAR_RANK_23) || \ - ((CHANNEL) == ADC_REGULAR_RANK_24) || \ - ((CHANNEL) == ADC_REGULAR_RANK_25) || \ - ((CHANNEL) == ADC_REGULAR_RANK_26) || \ - ((CHANNEL) == ADC_REGULAR_RANK_27) || \ - ((CHANNEL) == ADC_REGULAR_RANK_28) ) -#else - -#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ - ((CHANNEL) == ADC_REGULAR_RANK_10) || \ - ((CHANNEL) == ADC_REGULAR_RANK_11) || \ - ((CHANNEL) == ADC_REGULAR_RANK_12) || \ - ((CHANNEL) == ADC_REGULAR_RANK_13) || \ - ((CHANNEL) == ADC_REGULAR_RANK_14) || \ - ((CHANNEL) == ADC_REGULAR_RANK_15) || \ - ((CHANNEL) == ADC_REGULAR_RANK_16) || \ - ((CHANNEL) == ADC_REGULAR_RANK_17) || \ - ((CHANNEL) == ADC_REGULAR_RANK_18) || \ - ((CHANNEL) == ADC_REGULAR_RANK_19) || \ - ((CHANNEL) == ADC_REGULAR_RANK_20) || \ - ((CHANNEL) == ADC_REGULAR_RANK_21) || \ - ((CHANNEL) == ADC_REGULAR_RANK_22) || \ - ((CHANNEL) == ADC_REGULAR_RANK_23) || \ - ((CHANNEL) == ADC_REGULAR_RANK_24) || \ - ((CHANNEL) == ADC_REGULAR_RANK_25) || \ - ((CHANNEL) == ADC_REGULAR_RANK_26) || \ - ((CHANNEL) == ADC_REGULAR_RANK_27) ) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode - * @{ - */ -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) -#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) -#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) -#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) -#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) - -#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) -/** - * @} - */ - -/** @defgroup ADC_conversion_group ADC conversion group - * @{ - */ -#define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) -#define INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) -#define REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) - -#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP) || \ - ((CONVERSION) == INJECTED_GROUP) || \ - ((CONVERSION) == REGULAR_INJECTED_GROUP) ) -/** - * @} - */ - -/** @defgroup ADC_Event_type ADC Event type - * @{ - */ -#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ -#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ - -#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ - ((EVENT) == ADC_FLAG_OVR) ) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition ADC interrupts definition - * @{ - */ -#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ -#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ -#define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */ -/** - * @} - */ - -/** @defgroup ADC_flags_definition ADC flags definition - * @{ - */ -#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ -#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ -#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ -#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ -#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ -#define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */ -#define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */ -#define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Regular group ready status flag */ - -/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \ - ADC_FLAG_OVR) -/** - * @} - */ - -/** @defgroup ADC_range_verification ADC range verification - * For a unique ADC resolution: 12 bits - * @{ - */ -#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF)) -/** - * @} - */ - -/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification - * @{ - */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28))) -#else -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27))) -#endif -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification - * @{ - */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Macros ADC Exported Macros - * @{ - */ -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ - -/** - * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle - * @retval SET (ADC enabled) or RESET (ADC disabled) - */ -#define __HAL_ADC_IS_ENABLED(__HANDLE__) \ - ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ - ) ? SET : RESET) - -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__: ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - -/** - * @brief Test if conversion trigger of injected group is software start - * or external trigger. - * @param __HANDLE__: ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) - -/** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC interrupt source to check - * @retval State of interruption (SET or RESET) - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (( ((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__) \ - )? SET : RESET \ - ) - -/** - * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt - * @retval None - */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) - -/** - * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) - -/** - * @brief Get the selected ADC's flag status. - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag - * @retval None - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the ADC's pending flags - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag - * @retval None - */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) - -/** - * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) \ - ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) - -/** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) - -/** - * @} - */ - -/* Include ADC HAL Extension module */ -#include "stm32l1xx_hal_adc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_Exported_Functions_Group1 - * @{ - */ - - -/* Initialization and de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); -/** - * @} - */ - -/* IO operation functions *****************************************************/ - -/** @addtogroup ADC_Exported_Functions_Group2 - * @{ - */ - - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); - -/* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); -/** - * @} - */ - - -/* Peripheral Control functions ***********************************************/ -/** @addtogroup ADC_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); -/** - * @} - */ - - -/* Peripheral State functions *************************************************/ -/** @addtogroup ADC_Exported_Functions_Group4 - * @{ - */ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); -/** - * @} - */ - - -/** - * @} - */ - - -/* Internal HAL driver functions **********************************************/ -/** @addtogroup ADC_Private_Functions - * @{ - */ - -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h deleted file mode 100644 index 255a1051d..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h +++ /dev/null @@ -1,693 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_adc_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of ADC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_ADC_EX_H -#define __STM32L1xx_HAL_ADC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Types ADCEx Exported Types - * @{ - */ - -/** - * @brief ADC Configuration injected Channel structure definition - * @note Parameters of this structure are shared within 2 scopes: - * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset - * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, - * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. - * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled - * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. - * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. - */ -typedef struct -{ - uint32_t InjectedChannel; /*!< Selection of ADC channel to configure - This parameter can be a value of @ref ADC_channels - Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ - uint32_t InjectedRank; /*!< Rank in the injected group sequencer - This parameter must be a value of @ref ADCEx_injected_rank - Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ - uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times - Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. - If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ - uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). - Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), - this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ - uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. - To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. - Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one - This parameter can be set to ENABLE or DISABLE. - Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) - Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) - Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. - To maintain JAUTO always enabled, DMA must be configured in circular mode. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. - If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. - If set to external trigger source, triggering is on event rising edge. - This parameter can be a value of @ref ADCEx_External_trigger_source_Injected - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. - This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. - If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ -}ADC_InjectionConfTypeDef; -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants - * @{ - */ - -/** @defgroup ADCEx_injected_rank ADCEx injected rank - * @{ - */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) - -#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ - ((CHANNEL) == ADC_INJECTED_RANK_2) || \ - ((CHANNEL) == ADC_INJECTED_RANK_3) || \ - ((CHANNEL) == ADC_INJECTED_RANK_4) ) -/** - * @} - */ - -/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx External trigger edge Injected - * @{ - */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) - -#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) -/** - * @} - */ - -/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected - * @{ - */ -/* External triggers for injected groups of ADC1 */ -#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 -#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO -#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 -#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO -#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1 -#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2 -#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3 -#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO -#define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1 -#define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO -#define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 -#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 - -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000010) - -#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ - ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - ((REGTRIG) == ADC_SOFTWARE_START) ) -/** - * @} - */ - -/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected - * @{ - */ - -/* List of external triggers of injected group for ADC1: */ -/* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC_EXTERNALTRIGINJEC_T9_CC1 ((uint32_t) 0x00000000) -#define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) -#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 )) -#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) -#define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 )) -#define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) -#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) - -/** - * @} - */ - - -/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification - * @{ - */ -#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros - * @{ - */ -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ - -/** - * @brief Selection of channels bank. - * Note: Banks availability depends on devices categories. - * This macro is intended to change bank selection quickly on the fly, - * without going through ADC init structure update and execution of function - * 'HAL_ADC_Init()'. - * @param __HANDLE__: ADC handle - * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank. - * @retval None - */ -#define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ - MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Configures the ADC channels speed. - * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. - * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is - * in power down mode. - * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is - * in power down mode. - * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in - * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and - * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. - * (Note: OPAMP3 is available on STM32L1 Cat.4 only). - * @param __CHANNEL__: ADC channel - * This parameter can be one of the following values: - * @arg ADC_CHANNEL_3: Channel 3 is selected. - * @arg ADC_CHANNEL_8: Channel 8 is selected. - * @arg ADC_CHANNEL_13: Channel 13 is selected. - * @retval None - */ -#define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \ - ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ - )? \ - (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \ - : \ - ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ - )? \ - (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \ - : \ - ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ - )? \ - (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \ - : \ - (SET_BIT(COMP->CSR, 0x00000000)) \ - ) \ - ) \ - ) - -#define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \ - ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ - )? \ - (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \ - : \ - ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ - )? \ - (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \ - : \ - ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ - )? \ - (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \ - : \ - (SET_BIT(COMP->CSR, 0x00000000)) \ - ) \ - ) \ - ) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -/* Private macro ------------------------------------------------------------*/ - -/** @defgroup ADCEx_Private_Macro ADCEx Private Macro - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - -/** - * @brief Set ADC number of ranks into regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length - * @retval None - */ -#define __ADC_SQR1_L(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) - -/** - * @brief Set ADC ranks available in register SQR1. - * Register SQR1 bits availability depends on device category. - * @param _NbrOfConversion_: Regular channel sequence length - * @retval None - */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SQR1_SQXX ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25 -#else -#define __ADC_SQR1_SQXX ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25 -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Set the ADC's sample time for channel numbers between 30 and 31. - * Register SMPR0 availability depends on device category. If register is not - * available on the current device, this macro does nothing. - * @retval None - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) -#else -#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((uint32_t)0x00000000) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Set the ADC's sample time for channel numbers between 20 and 29. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) -#else -/** - * @brief Set the ADC's sample time for channel numbers between 20 and 26. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Defines the highest channel available in register SMPR1. Channels - * availability depends on device category: - * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3 - * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5 - * @param None - * @retval None - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 -#else -#define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define __ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) - -/** - * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. - * @retval None - */ -#define __ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) - -/** - * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) - -/** - * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) - -/** - * @brief Set the selected regular channel rank for rank between 13 and 18. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) - -/** - * @brief Set the selected regular channel rank for rank between 19 and 24. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19))) - -/** - * @brief Set the selected regular channel rank for rank between 25 and 28. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @retval None - */ -#define __ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25))) - -/** - * @brief Set the injected sequence length. - * @param _JSQR_JL_: Sequence length. - * @retval None - */ -#define __ADC_JSQR_JL(_JSQR_JL_) (((_JSQR_JL_) -1) << 20) - -/** - * @brief Set the selected injected Channel rank (channels sequence starting from 4-JL) - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @param _JSQR_JL_: Sequence length. - * @retval None - */ -#define __ADC_JSQR_RK(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ - ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) - - -/** - * @brief Enable the ADC DMA continuous request. - * @param _DMACONTREQ_MODE_: DMA continuous request mode. - * @retval None - */ -#define __ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS)) - -/** - * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. - * @retval None - */ -#define __ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) - -/** - * @brief Define mask of configuration bits of ADC and regular group in - * register CR2 (bits of ADC enable, conversion start and injected group are - * excluded of this mask). - * @retval None - */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_CR2_MASK_ADCINIT() \ - (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) -#else -#define __ADC_CR2_MASK_ADCINIT() \ - (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) -#endif - -/** - * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. - * @retval None - */ -#define __ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) - -/** - * @brief Enable ADC scan mode to convert multiple ranks with sequencer. - * @param _SCAN_MODE_: Scan conversion mode. - * @retval None - */ -#define __ADC_CR1_SCAN(_SCAN_MODE_) \ - ( ( (_SCAN_MODE_) == (ADC_SCAN_ENABLE) \ - )? (ADC_CR1_SCAN) : (0x00000000) \ - ) - -/** - * @brief Get the maximum ADC conversion cycles on all channels. - * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) - * Approximation of sampling time within 2 ranges, returns the higher value: - * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} - * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} - * Unit: ADC clock cycles - * @param __HANDLE__: ADC handle - * @retval ADC conversion cycles on all channels - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ - (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ - (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ - (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ - (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \ - \ - ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ - ) -#else -#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ - (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ - (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ - (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ - \ - ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ - ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Get the ADC clock prescaler from ADC common control register - * and convert it to its decimal number setting (refer to reference manual) - * @retval None - */ -#define __ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ - ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) - -/** - * @brief Clear register SMPR0. - * Register SMPR0 availability depends on device category. If register is not - * available on the current device, this macro performs no action. - * @param __HANDLE__: ADC handle - * @retval None - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SMPR0_CLEAR(__HANDLE__) \ - (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) -#else -#define __ADC_SMPR0_CLEAR(__HANDLE__) __NOP() -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Clear register CR2. - * @param __HANDLE__: ADC handle - * @retval None - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_CR2_CLEAR(__HANDLE__) \ - (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ - ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ - ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ - ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \ - ADC_CR2_CONT | ADC_CR2_ADON )) \ - ) -#else -#define __ADC_CR2_CLEAR(__HANDLE__) \ - (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ - ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ - ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ - ADC_CR2_DMA | ADC_CR2_DELS | \ - ADC_CR2_CONT | ADC_CR2_ADON )) \ - ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Set the sampling time of selected channel on register SMPR0 - * Register SMPR0 availability depends on device category. If register is not - * available on the current device, this macro performs no action. - * @param __HANDLE__: ADC handle - * @param _SAMPLETIME_: Sample time parameter. - * @param __CHANNEL__: Channel number. - * @retval None - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ - MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ - __ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ - __ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) -#else -#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - -/** - * @brief Enable the ADC peripheral - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __ADC_ENABLE(__HANDLE__) \ - (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON - -/** - * @brief Disable the ADC peripheral - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __ADC_DISABLE(__HANDLE__) \ - (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADCEx_Exported_Functions - * @{ - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup ADCEx_Exported_Functions_Group1 - * @{ - */ - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); -/** - * @} - */ - - -/* Peripheral Control functions ***********************************************/ -/** @addtogroup ADCEx_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_ADC_EX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h deleted file mode 100644 index 39eb773aa..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h +++ /dev/null @@ -1,520 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_comp.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of COMP HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_COMP_H -#define __STM32L1xx_HAL_COMP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup COMP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup COMP_Exported_Types COMP Exported Types - * @{ - */ - -/** - * @brief COMP Init structure definition - */ -typedef struct -{ - - uint32_t InvertingInput; /*!< Selects the inverting input of the comparator. - This parameter can be a value of @ref COMP_InvertingInput - Note: Inverting input can be changed on the fly, while comparator is running. - Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded (On COMP1, inverting input is fixed to Vrefint). */ - - uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator. - This parameter can be a value of @ref COMPEx_NonInvertingInput */ - - uint32_t Output; /*!< Selects the output redirection of the comparator. - This parameter can be a value of @ref COMP_Output - Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */ - - uint32_t Mode; /*!< Selects the operating consumption mode of the comparator - to adjust the speed/consumption. - This parameter can be a value of @ref COMP_Mode - Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */ - - uint32_t WindowMode; /*!< Selects the window mode of the 2 comparators. - If enabled, non-inverting inputs of the 2 comparators are connected together and are using inputs of COMP2 only (COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP). - This parameter can be a value of @ref COMP_WindowMode - Note: This feature must be enabled from COMP2 instance. If COMP1 is selected, this parameter is discarded. */ - - uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator when using interruption on EXTI line (interrupt mode). - This parameter can be a value of @ref COMP_TriggerMode - Note: This feature is used with function "HAL_COMP_Start_IT()". In all other functions, this parameter is discarded. */ - - uint32_t NonInvertingInputPull; /*!< Selects the internal pulling resistor connected on non inverting input. - This parameter can be a value of @ref COMP_NonInvertingInputPull - Note: To avoid extra power consumption, only one resistor should be enabled at a time. - Note: This feature is available on COMP1 only. If COMP2 is selected, this parameter is discarded. */ - -}COMP_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */ - HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */ - HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */ - HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ - HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */ -}HAL_COMP_StateTypeDef; - -/** - * @brief COMP Handle Structure definition - */ -typedef struct -{ - COMP_TypeDef *Instance; /*!< Register base address */ - COMP_InitTypeDef Init; /*!< COMP required parameters */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ -} COMP_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup COMP_Exported_Constants COMP Exported Constants - * @{ - */ - -/** @defgroup COMP_Output COMP Output - * @{ - */ -#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00000000) /*!< COMP2 output connected to TIM2 Input Capture 4 */ -#define COMP_OUTPUT_TIM2OCREFCLR ( COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM3IC4 ( COMP_CSR_OUTSEL_1 ) /*!< COMP2 output connected to TIM3 Input Capture 4 */ -#define COMP_OUTPUT_TIM3OCREFCLR ( COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM3 OCREF Clear */ -#define COMP_OUTPUT_TIM4IC4 (COMP_CSR_OUTSEL_2 ) /*!< COMP2 output connected to TIM4 Input Capture 4 */ -#define COMP_OUTPUT_TIM4OCREFCLR (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM4 OCREF Clear */ -#define COMP_OUTPUT_TIM10IC1 (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 ) /*!< COMP2 output connected to TIM10 Input Capture 1 */ -#define COMP_OUTPUT_NONE (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output is not connected to other peripherals */ - -#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \ - ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \ - ((OUTPUT) == COMP_OUTPUT_TIM3IC4) || \ - ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \ - ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \ - ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \ - ((OUTPUT) == COMP_OUTPUT_TIM10IC1) || \ - ((OUTPUT) == COMP_OUTPUT_NONE) ) -/** - * @} - */ - -/** @defgroup COMP_InvertingInput COMP InvertingInput - * @{ - */ -/* Inverting Input specific to COMP2 */ -#define COMP_INVERTINGINPUT_IO ( COMP_CSR_INSEL_0) /*!< External I/O (COMP2_INM connected to pin PB3) connected to comparator 2 inverting input */ -#define COMP_INVERTINGINPUT_VREFINT ( COMP_CSR_INSEL_1 ) /*!< VREFINT connected to comparator 2 inverting input */ -#define COMP_INVERTINGINPUT_3_4VREFINT ( COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< 3/4 VREFINT connected to comparator 2 inverting input */ -#define COMP_INVERTINGINPUT_1_2VREFINT (COMP_CSR_INSEL_2 ) /*!< 1/2 VREFINT connected to comparator 2 inverting input */ -#define COMP_INVERTINGINPUT_1_4VREFINT (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_0) /*!< 1/4 VREFINT connected to comparator 2 inverting input */ -#define COMP_INVERTINGINPUT_DAC1 (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1 ) /*!< DAC_OUT1 (PA4) connected to comparator 2 inverting input */ -#define COMP_INVERTINGINPUT_DAC2 (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< DAC2_OUT (PA5) connected to comparator 2 inverting input */ - -#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_IO) || \ - ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \ - ((INPUT) == COMP_INVERTINGINPUT_DAC2) ) -/** - * @} - */ - -/** @defgroup COMP_Mode COMP Mode - * @{ - */ -/* Please refer to the electrical characteristics in the device datasheet for - the power consumption values */ -#define COMP_MODE_LOWSPEED ((uint32_t)0x00000000) /*!< Low Speed */ -#define COMP_MODE_HIGHSPEED COMP_CSR_SPEED /*!< High Speed */ - -#define IS_COMP_MODE(SPEED) (((SPEED) == COMP_MODE_LOWSPEED) || \ - ((SPEED) == COMP_MODE_HIGHSPEED)) -/** - * @} - */ - -/** @defgroup COMP_WindowMode COMP WindowMode - * @{ - */ -#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled: COMP1 non-inverting input is independant */ -#define COMP_WINDOWMODE_ENABLED COMP_CSR_WNDWE /*!< Window mode enabled: COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP) (connected to COMP2 non-inverting input) */ - -#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \ - ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED)) -/** - * @} - */ - -/** @defgroup COMP_OutputLevel COMP OutputLevel - * @{ - */ -/* Comparator output is low when the non-inverting input is at a lower */ -/* voltage than the inverting input. */ -#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) - -/* Comparator output is high when the non-inverting input is at a higher */ -/* voltage than the inverting input. */ -#define COMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) -/** - * @} - */ - -/** @defgroup COMP_TriggerMode COMP TriggerMode - * @{ - */ -#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */ -#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \ - ((MODE) == COMP_TRIGGERMODE_IT_RISING) || \ - ((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \ - ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING) ) -/** - * @} - */ - -/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent - * @{ - */ -#define COMP_EXTI_LINE_COMP1_EVENT EXTI_RTSR_TR21 /*!< External interrupt line 21 Connected to COMP1 */ -#define COMP_EXTI_LINE_COMP2_EVENT EXTI_RTSR_TR22 /*!< External interrupt line 22 Connected to COMP2 */ - -/** - * @} - */ - -/** @defgroup COMP_NonInvertingInputPull COMP NonInvertingInputPull - * @{ - */ -#define COMP_NONINVERTINGINPUT_NOPULL ((uint32_t)0x00000000) /*!< No internal pull-up or pull-down resistor connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_10KPU COMP_CSR_10KPU /*!< Internal 10kOhm pull-up resistor connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_10KPD COMP_CSR_10KPD /*!< Internal 10kOhm pull-down resistor connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_400KPU COMP_CSR_400KPU /*!< Internal 400kOhm pull-up resistor connected to comparator non inverting input */ -#define COMP_NONINVERTINGINPUT_400KPD COMP_CSR_400KPD /*!< Internal 400kOhm pull-down resistor connected to comparator non inverting input */ - -#define IS_COMP_NONINVERTINGINPUTPULL(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_NOPULL) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_10KPU) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_10KPD) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_400KPU) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_400KPD) ) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup COMP_Exported_Macro COMP Exported Macro - * @{ - */ - -/** @brief Reset COMP handle state - * @param __HANDLE__: COMP handle. - * @retval None - */ -#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) - -/** - * @brief Enables the specified comparator - * @param __HANDLE__: COMP handle. - * @retval None. - */ -#define __HAL_COMP_ENABLE(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == COMP1) \ - )? \ - SET_BIT(COMP->CSR, COMP_CSR_CMP1EN) \ - : \ - MODIFY_REG(COMP->CSR, COMP_CSR_INSEL, (__HANDLE__)->Init.InvertingInput ) \ - ) - -/** - * @brief Disables the specified comparator - * @param __HANDLE__: COMP handle. - * @retval None. - */ -#define __HAL_COMP_DISABLE(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == COMP1) \ - )? \ - CLEAR_BIT(COMP->CSR, COMP_CSR_CMP1EN) \ - : \ - CLEAR_BIT(COMP->CSR, COMP_CSR_INSEL) \ - ) - - -/** @brief Checks whether the specified COMP flag is set or not. - * @param __HANDLE__: specifies the COMP Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg COMP_FLAG_LOCK: lock flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->CSR, (__FLAG__)) == (__FLAG__)) - - -/** - * @brief Enable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->RTSR, (__EXTILINE__))) - -/** - * @brief Disable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))) - -/** - * @brief Enable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->FTSR, (__EXTILINE__))) - -/** - * @brief Disable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))) - -/** - * @brief Get the specified EXTI line for a comparator instance - * @param __INSTANCE__: specifies the COMP instance. - * @retval value of @ref COMP_ExtiLineEvent - */ -#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) \ - ( ( ((__INSTANCE__) == COMP1) \ - )? \ - (COMP_EXTI_LINE_COMP1_EVENT) \ - : \ - (COMP_EXTI_LINE_COMP2_EVENT) \ - ) - -/** - * @brief Enable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (SET_BIT(EXTI->IMR, (__EXTILINE__))) - -/** - * @brief Disable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (CLEAR_BIT(EXTI->IMR, (__EXTILINE__))) - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __FLAG__: specifies the COMP Exti sources to be checked. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval The state of __FLAG__ (SET or RESET). - */ -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (READ_BIT(EXTI->PR, (__FLAG__))) - -/** - * @brief Clear the COMP Exti flags. - * @param __FLAG__: specifies the COMP Exti sources to be cleared. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTILINE__: specifies the COMP Exti sources to trig. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None - */ -#define __HAL_COMP_EXTI_GENERATE_SWIT(__EXTILINE__) (SET_BIT(EXTI->SWIER, (__EXTILINE__))) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup COMP_Private_Macro COMP Private Macro - * @{ - */ - -/** - * @brief Select the COMP register CSR bit CMPxOUT corresponding to the - * selected COMP instance. - * @param __HANDLE__: COMP handle - * @retval Comparator register CSR bit COMP_CSR_CMP1OUT or COMP_CSR_CMP2OUT - */ -#define __COMP_CSR_CMPXOUT(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == COMP1) \ - )? \ - (COMP_CSR_CMP1OUT) \ - : \ - (COMP_CSR_CMP2OUT) \ - ) - -/** - * @brief Verification of COMP state: enabled or disabled - * @param __HANDLE__: COMP handle - * @retval SET (COMP enabled) or RESET (COMP disabled) - */ -#define __COMP_IS_ENABLED(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == COMP1) \ - )? \ - (((READ_BIT(COMP->CSR , COMP_CSR_CMP1EN) == COMP_CSR_CMP1EN) \ - ) ? SET : RESET) \ - : \ - (((READ_BIT(COMP->CSR , COMP_CSR_INSEL) != RESET) \ - ) ? SET : RESET) \ - ) - -/** - * @} - */ - - -/* Include COMP HAL Extension module */ -#include "stm32l1xx_hal_comp_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup COMP_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -/** @addtogroup COMP_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); -void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); -void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); -/** - * @} - */ - -/* I/O operation functions *****************************************************/ -/** @addtogroup COMP_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp); -void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ -/** @addtogroup COMP_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); - -/* Callback in Interrupt mode */ -void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); -/** - * @} - */ - -/* Peripheral State functions **************************************************/ -/** @addtogroup COMP_Exported_Functions_Group4 - * @{ - */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_COMP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h deleted file mode 100644 index 731c9e45d..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_comp_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of COMP HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_COMP_EX_H -#define __STM32L1xx_HAL_COMP_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup COMPEx COMPEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup COMPEx_Exported_Constants COMPEx Exported Constants - * @{ - */ - -/** @defgroup COMPEx_NonInvertingInput COMPEx NonInvertingInput - * @{ - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/* Non-inverting inputs specific to COMP2 */ -#define COMP_NONINVERTINGINPUT_PB4 RI_IOSWITCH_GR6_1 /*!< I/O pin PB4 connection to COMP2 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB6 RI_IOSWITCH_GR6_3 /*!< I/O pin PB6 connection to COMP2 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB7 RI_IOSWITCH_GR6_4 /*!< I/O pin PB7 connection to COMP2 non-inverting input */ - -/* Non-inverting inputs specific to COMP1 */ -#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */ -#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA3 RI_IOSWITCH_CH3 /*!< I/O pin PA3 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA4 RI_IOSWITCH_CH4 /*!< I/O pin PA4 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA5 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA6 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA7 RI_IOSWITCH_CH7 /*!< I/O pin PA7 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB0 RI_IOSWITCH_CH8 /*!< I/O pin PB0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB1 RI_IOSWITCH_CH9 /*!< I/O pin PB1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC0 RI_IOSWITCH_CH10 /*!< I/O pin PC0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC1 RI_IOSWITCH_CH11 /*!< I/O pin PC1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC2 RI_IOSWITCH_CH12 /*!< I/O pin PC2 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC3 RI_IOSWITCH_CH13 /*!< I/O pin PC3 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC4 RI_IOSWITCH_CH14 /*!< I/O pin PC4 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC5 RI_IOSWITCH_CH15 /*!< I/O pin PC5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB12 RI_IOSWITCH_CH18 /*!< I/O pin PB12 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB13 RI_IOSWITCH_CH19 /*!< I/O pin PB13 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB14 RI_IOSWITCH_CH20 /*!< I/O pin PB14 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB15 RI_IOSWITCH_CH21 /*!< I/O pin PB15 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE7 RI_IOSWITCH_CH22 /*!< I/O pin PE7 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE8 RI_IOSWITCH_CH23 /*!< I/O pin PE8 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE9 RI_IOSWITCH_CH24 /*!< I/O pin PE9 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE10 RI_IOSWITCH_CH25 /*!< I/O pin PE10 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PF6 RI_IOSWITCH_CH27 /*!< I/O pin PF6 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PF7 RI_IOSWITCH_CH28 /*!< I/O pin PF7 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PF8 RI_IOSWITCH_CH29 /*!< I/O pin PF8 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PF9 RI_IOSWITCH_CH30 /*!< I/O pin PF9 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PF10 RI_IOSWITCH_CH31 /*!< I/O pin PF10 connection to COMP1 non-inverting input */ - -#define COMP_NONINVERTINGINPUT_OPAMP1 COMP_NONINVERTINGINPUT_PA3 /*!< OPAMP1 output connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_OPAMP2 COMP_NONINVERTINGINPUT_PB0 /*!< OPAMP2 output connection to COMP1 non-inverting input */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) -#define COMP_NONINVERTINGINPUT_OPAMP3 COMP_NONINVERTINGINPUT_PC3 /*!< OPAMP3 output connection to COMP1 non-inverting input */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -/* Non-inverting inputs specific to COMP2 */ -#define COMP_NONINVERTINGINPUT_PB4 RI_IOSWITCH_GR6_1 /*!< I/O pin PB4 connection to COMP2 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB6 RI_IOSWITCH_GR6_3 /*!< I/O pin PB6 connection to COMP2 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB7 RI_IOSWITCH_GR6_4 /*!< I/O pin PB7 connection to COMP2 non-inverting input */ - -/* Non-inverting inputs specific to COMP1 */ -#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */ -#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA3 RI_IOSWITCH_CH3 /*!< I/O pin PA3 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA4 RI_IOSWITCH_CH4 /*!< I/O pin PA4 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA5 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA6 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA7 RI_IOSWITCH_CH7 /*!< I/O pin PA7 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB0 RI_IOSWITCH_CH8 /*!< I/O pin PB0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB1 RI_IOSWITCH_CH9 /*!< I/O pin PB1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC0 RI_IOSWITCH_CH10 /*!< I/O pin PC0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC1 RI_IOSWITCH_CH11 /*!< I/O pin PC1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC2 RI_IOSWITCH_CH12 /*!< I/O pin PC2 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC3 RI_IOSWITCH_CH13 /*!< I/O pin PC3 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC4 RI_IOSWITCH_CH14 /*!< I/O pin PC4 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC5 RI_IOSWITCH_CH15 /*!< I/O pin PC5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB12 RI_IOSWITCH_CH18 /*!< I/O pin PB12 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB13 RI_IOSWITCH_CH19 /*!< I/O pin PB13 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB14 RI_IOSWITCH_CH20 /*!< I/O pin PB14 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB15 RI_IOSWITCH_CH21 /*!< I/O pin PB15 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE7 RI_IOSWITCH_CH22 /*!< I/O pin PE7 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE8 RI_IOSWITCH_CH23 /*!< I/O pin PE8 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE9 RI_IOSWITCH_CH24 /*!< I/O pin PE9 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE10 RI_IOSWITCH_CH25 /*!< I/O pin PE10 connection to COMP1 non-inverting input */ - -#define COMP_NONINVERTINGINPUT_OPAMP1 COMP_NONINVERTINGINPUT_PA3 /*!< OPAMP1 output connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_OPAMP2 COMP_NONINVERTINGINPUT_PB0 /*!< OPAMP2 output connection to COMP1 non-inverting input */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) -/* Non-inverting inputs specific to COMP2 */ -#define COMP_NONINVERTINGINPUT_PB4 RI_IOSWITCH_GR6_1 /*!< I/O pin PB4 connection to COMP2 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB5 RI_IOSWITCH_GR6_2 /*!< I/O pin PB5 connection to COMP2 non-inverting input */ - -/* Non-inverting inputs specific to COMP1 */ -#define COMP_NONINVERTINGINPUT_NONE ((uint32_t)0x00000000) /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */ -#define COMP_NONINVERTINGINPUT_PA0 RI_IOSWITCH_CH0 /*!< I/O pin PA0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA1 RI_IOSWITCH_CH1 /*!< I/O pin PA1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA2 RI_IOSWITCH_CH2 /*!< I/O pin PA2 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA3 RI_IOSWITCH_CH3 /*!< I/O pin PA3 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA4 RI_IOSWITCH_CH4 /*!< I/O pin PA4 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA5 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA6 RI_IOSWITCH_CH5 /*!< I/O pin PA5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PA7 RI_IOSWITCH_CH7 /*!< I/O pin PA7 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB0 RI_IOSWITCH_CH8 /*!< I/O pin PB0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB1 RI_IOSWITCH_CH9 /*!< I/O pin PB1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC0 RI_IOSWITCH_CH10 /*!< I/O pin PC0 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC1 RI_IOSWITCH_CH11 /*!< I/O pin PC1 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC2 RI_IOSWITCH_CH12 /*!< I/O pin PC2 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC3 RI_IOSWITCH_CH13 /*!< I/O pin PC3 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC4 RI_IOSWITCH_CH14 /*!< I/O pin PC4 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PC5 RI_IOSWITCH_CH15 /*!< I/O pin PC5 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB12 RI_IOSWITCH_CH18 /*!< I/O pin PB12 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB13 RI_IOSWITCH_CH19 /*!< I/O pin PB13 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB14 RI_IOSWITCH_CH20 /*!< I/O pin PB14 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PB15 RI_IOSWITCH_CH21 /*!< I/O pin PB15 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE7 RI_IOSWITCH_CH22 /*!< I/O pin PE7 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE8 RI_IOSWITCH_CH23 /*!< I/O pin PE8 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE9 RI_IOSWITCH_CH24 /*!< I/O pin PE9 connection to COMP1 non-inverting input */ -#define COMP_NONINVERTINGINPUT_PE10 RI_IOSWITCH_CH25 /*!< I/O pin PE10 connection to COMP1 non-inverting input */ - -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB6) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_NONE) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA2) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA3) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA6) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC2) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC3) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB12) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB13) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB14) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB15) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE8) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE9) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE10) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PF6) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PF7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PF8) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PF9) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PF10) ) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB6) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_NONE) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA2) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA3) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA6) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC2) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC3) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB12) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB13) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB14) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB15) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE8) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE9) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE10) ) -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) -#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_NONE) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA2) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA3) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA6) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PA7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC0) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC2) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC3) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC4) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PC5) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB12) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB13) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB14) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PB15) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE7) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE8) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE9) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_PE10) ) -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup COMPEx_Private_Macro COMP Private Macro - * @{ - */ - -/** - * @brief Specifies whether Routing Interface (RI) needs to be configured for - * switches of comparator non-inverting input. - * @param __HANDLE__: COMP handle. - * @retval None. - */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__) \ - (((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) && \ - (READ_BIT(COMP->CSR, COMP_CSR_SW1) == RESET) ) -#else -#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__) \ - ((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_COMP_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h deleted file mode 100644 index c6d0dd67e..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h +++ /dev/null @@ -1,291 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_conf_template.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32l1xx_hal_conf.h. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CONF_H -#define __STM32L1xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -#define HAL_COMP_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_CRC_MODULE_ENABLED -#define HAL_CRYP_MODULE_ENABLED -#define HAL_DAC_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_I2S_MODULE_ENABLED -#define HAL_IRDA_MODULE_ENABLED -#define HAL_IWDG_MODULE_ENABLED -#define HAL_LCD_MODULE_ENABLED -#define HAL_NOR_MODULE_ENABLED -#define HAL_OPAMP_MODULE_ENABLED -#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -#define HAL_SD_MODULE_ENABLED -#define HAL_SMARTCARD_MODULE_ENABLED -#define HAL_SPI_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED -#define HAL_TIM_MODULE_ENABLED -#define HAL_UART_MODULE_ENABLED -#define HAL_USART_MODULE_ENABLED -#define HAL_WWDG_MODULE_ENABLED - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 -#define INSTRUCTION_CACHE_ENABLE 0 -#define DATA_CACHE_ENABLE 0 - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/*#define USE_FULL_ASSERT 1*/ - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l1xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l1xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l1xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l1xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l1xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l1xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l1xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l1xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l1xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l1xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l1xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l1xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l1xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32l1xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l1xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l1xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32l1xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l1xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l1xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l1xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l1xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l1xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l1xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l1xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l1xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l1xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l1xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l1xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h deleted file mode 100644 index 8323d6bde..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cortex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CORTEX_H -#define __STM32L1xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ - -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported Macros -----------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source_Macro_Exported CORTEX SysTick clock source - * @{ - */ - -/** @brief Configures the SysTick clock source. - * @param __CLKSRC__: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \ - do { \ - if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \ - { \ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \ - } \ - else \ - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \ - } while(0) -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ - -/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source - * @{ - */ -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h deleted file mode 100644 index a3c807d40..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h +++ /dev/null @@ -1,192 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_crc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of CRC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CRC_H -#define __STM32L1xx_HAL_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Types CRC Exported Types - * @{ - */ - -/** - * @brief CRC HAL State Structure definition - */ -typedef enum -{ - HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ - HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ - -}HAL_CRC_StateTypeDef; - -/** - * @brief CRC handle Structure definition - */ -typedef struct -{ - CRC_TypeDef *Instance; /*!< Register base address */ - - HAL_LockTypeDef Lock; /*!< CRC locking object */ - - __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ - -}CRC_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Macros CRC Exported Macros - * @{ - */ - -/** @brief Reset CRC handle state - * @param __HANDLE__: CRC handle - * @retval None - */ -#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) - -/** - * @brief Resets CRC Data Register. - * @param __HANDLE__: CRC handle - * @retval None - */ -#define __HAL_CRC_DR_RESET(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET)) - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register - * @retval None - */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)) - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @retval 8-bit value of the ID register - */ -#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CRC_Exported_Functions - * @{ - */ - -/** @addtogroup CRC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); -HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc); -void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); -void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); - -/** - * @} - */ - -/** @addtogroup CRC_Exported_Functions_Group2 - * @{ - */ - -/** @addtogroup CRC_Exported_Functions_Group3 - ** @{ - */ -/* Peripheral Control functions ************************************************/ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); - -/* Peripheral State functions **************************************************/ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h deleted file mode 100644 index 2b0405a6e..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h +++ /dev/null @@ -1,411 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cryp.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of CRYP HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CRYP_H -#define __STM32L1xx_HAL_CRYP_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup CRYP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Types CRYP Exported Types - * @{ - */ - -/** - * @brief CRYP Configuration Structure definition - */ -typedef struct -{ - uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. - This parameter can be a value of @ref CRYP_Data_Type */ - - uint8_t* pKey; /*!< The key used for encryption/decryption */ - - uint8_t* pInitVect; /*!< The initialization vector used also as initialization - counter in CTR mode */ - -}CRYP_InitTypeDef; - -/** - * @brief HAL CRYP State structures definition - */ -typedef enum -{ - HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */ - HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */ - HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */ - HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */ - HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */ - -}HAL_CRYP_STATETypeDef; - -/** - * @brief HAL CRYP phase structures definition - */ -typedef enum -{ - HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ - HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */ -}HAL_PhaseTypeDef; - -/** - * @brief CRYP handle Structure definition - */ -typedef struct -{ - CRYP_InitTypeDef Init; /*!< CRYP required parameters */ - - uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - - uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - - __IO uint16_t CrypInCount; /*!< Counter of inputed data */ - - __IO uint16_t CrypOutCount; /*!< Counter of outputed data */ - - HAL_StatusTypeDef Status; /*!< CRYP peripheral status */ - - HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */ - - DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ - - DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< CRYP locking object */ - - __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - -}CRYP_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Constants CRYP Exported Constants - * @{ - */ - -/** @defgroup CRYP_Data_Type CRYP Data Type - * @{ - */ -#define CRYP_DATATYPE_32B ((uint32_t)0x00000000) -#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 -#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 -#define CRYP_DATATYPE_1B AES_CR_DATATYPE - -#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \ - ((DATATYPE) == CRYP_DATATYPE_16B) || \ - ((DATATYPE) == CRYP_DATATYPE_8B) || \ - ((DATATYPE) == CRYP_DATATYPE_1B)) -/** - * @} - */ - -/** @defgroup CRYP_AlgoModeDirection CRYP Algo Mode Direction - * @{ - */ -#define CRYP_CR_ALGOMODE_DIRECTION (uint32_t)(AES_CR_MODE|AES_CR_CHMOD) - -#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000) -#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT (AES_CR_MODE) -#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT (AES_CR_CHMOD_0) -#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE)) -#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT (AES_CR_CHMOD_1) -#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)(AES_CR_CHMOD_1 | AES_CR_MODE_1)) -/** - * @} - */ - -/** @defgroup CRYP_AES_Interrupts AES Interrupts - * @{ - */ -#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */ -#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */ - -/** - * @} - */ - - -/** @defgroup CRYP_AES_Flags AES Flags - * @{ - */ -#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */ -#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */ -#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */ - -/** - * @} - */ - -/** @defgroup CRYP_AES_Clear_Flags AES Clear Flags - * @{ - */ -#define AES_CLEARFLAG_CCF AES_CR_CCFC /*!< Computation Complete Flag Clear */ -#define AES_CLEARFLAG_RDERR AES_CR_ERRC /*!< Read Error Clear */ -#define AES_CLEARFLAG_WRERR AES_CR_ERRC /*!< Write Error Clear */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Macros CRYP Exported Macros - * @{ - */ - -/** @brief Reset CRYP handle state - * @param __HANDLE__: specifies the CRYP Handle. - * @retval None - */ -#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) - -/** - * @brief Enable/Disable the CRYP peripheral. - * @retval None - */ -#define __HAL_CRYP_ENABLE() SET_BIT(AES->CR, AES_CR_EN) -#define __HAL_CRYP_DISABLE() CLEAR_BIT(AES->CR, AES_CR_EN) - -/** - * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,... - * @param __MODE__: The algorithm mode. - * @retval None - */ -#define __HAL_CRYP_SET_MODE(__MODE__) SET_BIT(AES->CR, (__MODE__)) - - -/** @brief Check whether the specified CRYP flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg AES_FLAG_CCF : Computation Complete Flag - * @arg AES_FLAG_RDERR : Read Error Flag - * @arg AES_FLAG_WRERR : Write Error Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the CRYP pending flag. - * @param __HANDLE__: specifies the CRYP handle. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg AES_CLEARFLAG_CCF : Computation Complete Clear Flag - * @arg AES_CLEARFLAG_RDERR : Read Error Clear - * @arg AES_CLEARFLAG_WRERR : Write Error Clear - * @retval None - */ -#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(AES->CR, (__FLAG__)) - -/** - * @brief Enable the CRYP interrupt. - * @param __INTERRUPT__: CRYP Interrupt. - * @retval None - */ -#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__)) - -/** - * @brief Disable the CRYP interrupt. - * @param __INTERRUPT__: CRYP interrupt. - * @retval None - */ -#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(AES->CR, (__INTERRUPT__)) - -/** @brief Checks if the specified CRYP interrupt source is enabled or disabled. - * @param __HANDLE__: CRYP handle - * @param __INTERRUPT__: CRYP interrupt source to check - * This parameter can be one of the following values: - * @arg AES_IT_CC : Computation Complete interrupt - * @arg AES_IT_ERR : Error interrupt (used for RDERR and WRERR) - * @retval State of interruption (SET or RESET) - */ -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (( (AES->CR & (__INTERRUPT__)) == (__INTERRUPT__) \ - )? SET : RESET \ - ) - -/** @brief Clear the CRYP pending IT. - * @param __HANDLE__: specifies the CRYP handle. - * @param __IT__: specifies the IT to clear. - * This parameter can be one of the following values: - * @arg AES_CLEARFLAG_CCF : Computation Complete Clear Flag - * @arg AES_CLEARFLAG_RDERR : Read Error Clear - * @arg AES_CLEARFLAG_WRERR : Write Error Clear - * @retval None - */ -#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT(AES->CR, (__IT__)) - -/** - * @} - */ - -/* Include CRYP HAL Extension module */ -#include "stm32l1xx_hal_cryp_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CRYP_Exported_Functions - * @{ - */ - -/** @addtogroup CRYP_Exported_Functions_Group1 - * @{ - */ - -/* Initialization/de-initialization functions *********************************/ -HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); -HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); - -/* MSP functions *************************************************************/ -void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); - -/** - * @} - */ - -/** @addtogroup CRYP_Exported_Functions_Group2 - * @{ - */ - -/* AES encryption/decryption using polling ***********************************/ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); - -/* AES encryption/decryption using interrupt *********************************/ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); - -/* AES encryption/decryption using DMA ***************************************/ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); - -/** - * @} - */ - -/** @addtogroup CRYP_Exported_Functions_Group3 - * @{ - */ - -/* CallBack functions ********************************************************/ -void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); - -/** - * @} - */ - -/** @addtogroup CRYP_Exported_Functions_Group4 - * @{ - */ - -/* Processing functions ********************************************************/ -void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); - -/** - * @} - */ - -/** @addtogroup CRYP_Exported_Functions_Group5 - * @{ - */ - -/* Peripheral State functions **************************************************/ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CRYP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h deleted file mode 100644 index 26a989e56..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cryp_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of CRYPEx HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CRYP_EX_H -#define __STM32L1xx_HAL_CRYP_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup CRYPEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CRYPEx_Exported_Functions - * @{ - */ - -/** @addtogroup CRYPEx_Exported_Functions_Group1 - * @{ - */ - -/* CallBack functions ********************************************************/ -void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CRYP_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h deleted file mode 100644 index e86b57236..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dac.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of DAC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_DAC_H -#define __STM32L1xx_HAL_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Types DAC Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ - -}HAL_DAC_StateTypeDef; - -/** - * @brief DAC handle Structure definition - */ -typedef struct -{ - DAC_TypeDef *Instance; /*!< Register base address */ - - __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ - - HAL_LockTypeDef Lock; /*!< DAC locking object */ - - DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ - - DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ - - __IO uint32_t ErrorCode; /*!< DAC Error code */ - -}DAC_HandleTypeDef; - -/** - * @brief DAC Configuration regular Channel structure definition - */ -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ - -}DAC_ChannelConfTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants DAC Exported Constants - * @{ - */ - -/** @defgroup DAC_Error_Code DAC Error Code - * @{ - */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ -/** - * @} - */ - -/** @defgroup DAC_trigger_selection DAC trigger selection - * @{ - */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T9_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ - ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T9_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer DAC output buffer - * @{ - */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) -#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) - -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ - ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection DAC Channel selection - * @{ - */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) - -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ - ((CHANNEL) == DAC_CHANNEL_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement DAC data alignement - * @{ - */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) - -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ - ((ALIGN) == DAC_ALIGN_12B_L) || \ - ((ALIGN) == DAC_ALIGN_8B_R)) -/** - * @} - */ - -/** @defgroup DAC_data DAC data - * @{ - */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_flags_definition DAC flags definition - * @{ - */ -#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) - -/** - * @} - */ - -/** @defgroup DAC_IT_definition DAC IT definition - * @{ - */ -#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Macros DAC Exported Macros - * @{ - */ - -/** @brief Reset DAC handle state - * @param __HANDLE__: specifies the DAC handle. - * @retval None - */ -#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) - -/** @brief Enable the DAC channel - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_Channel__: specifies the DAC channel - * @retval None - */ -#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) - -/** @brief Disable the DAC channel - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_Channel__: specifies the DAC channel. - * @retval None - */ -#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) - -/** @brief Set DHR12R1 alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) - -/** @brief Set DHR12R2 alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) - -/** @brief Set DHR12RD alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) - -/** @brief Enable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. - * @retval None - */ -#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) - -/** @brief Disable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. - * @retval None - */ -#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) - -/** @brief Get the selected DAC's flag status. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the FLAG. - * @retval None - */ -#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the DAC's flag. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the FLAG. - * @retval None - */ -#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) - -/** - * @} - */ - - -/* Include DAC HAL Extension module */ -#include "stm32l1xx_hal_dac_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DAC_Exported_Functions - * @{ - */ - -/** @addtogroup DAC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); -void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); -void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); - -/** - * @} - */ - -/** @addtogroup DAC_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup DAC_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup DAC_Exported_Functions_Group2 - * @{ - */ -/* Peripheral State functions ***************************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); - -void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); -void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); -void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); -void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_HAL_DAC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h deleted file mode 100644 index 9c3032ee8..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dac_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of DAC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_DAC_EX_H -#define __STM32L1xx_HAL_DAC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup DACEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DACEx_Exported_Constants DACEx Exported Constants - * @{ - */ - -/** @defgroup DACEx_wave_generation DACEx wave generation - * @{ - */ -#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000) -#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) - -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \ - ((WAVE) == DAC_WAVEGENERATION_NOISE) || \ - ((WAVE) == DAC_WAVEGENERATION_TRIANGLE)) -/** - * @} - */ - -/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude - * @{ - */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ -#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ -#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ -#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ -#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ -#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ -#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ -#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ -#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) -/** - * @} - */ - -/** @defgroup DACEx_wave_generation DACEx wave generation - * @{ - */ -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \ - ((WAVE) == DAC_WAVE_TRIANGLE)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DACEx_Exported_Functions - * @{ - */ - -/** @addtogroup DACEx_Exported_Functions_Group1 - * @{ - */ -/* Extension features functions ***********************************************/ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); - -void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); - -/** - * @} - */ - -/** - * @} - */ -/** @addtogroup DACEx_Private_Functions - * @{ - */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_HAL_DAC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h deleted file mode 100644 index a8ad77943..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_def.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_DEF -#define __STM32L1xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ -#ifndef NULL - #define NULL (void *) 0 -#endif - -#define HAL_MAX_DELAY 0xFFFFFFFF - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ - (__DMA_HANDLE_).Parent = (__HANDLE__); \ - } while(0) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) - -#if (USE_RTOS == 1) - #error " USE_RTOS should be 0 in the current HAL release " -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32L1xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h deleted file mode 100644 index 366d973a0..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h +++ /dev/null @@ -1,444 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dma.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_DMA_H -#define __STM32L1xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Types DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ - -} DMA_InitTypeDef; - -/** - * @brief DMA Configuration enumeration values definition - */ -typedef enum -{ - DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ - DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ - -} DMA_ControlTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ - HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ - -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ - -}HAL_DMA_LevelCompleteTypeDef; - - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - -} DMA_HandleTypeDef; -/** - * @} - */ - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA_Error_Code - * @{ - */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -/** - * @} - */ - - -/** @defgroup DMA_Data_transfer_direction DMA_Data_transfer_direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) -/** - * @} - */ - -/** @defgroup DMA_Data_buffer_size DMA_Data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA_Peripheral_incremented_mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA_Memory_incremented_mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA_Peripheral_data_size - * @{ - */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) -/** - * @} - */ - - -/** @defgroup DMA_Memory_data_size DMA_Memory_data_size - * @{ - */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) -/** - * @} - */ - -/** @defgroup DMA_mode DMA_mode - * @{ - */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA_Priority_level - * @{ - */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions DMA_interrupt_enable_definitions - * @{ - */ - -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) - -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA_flag_definitions - * @{ - */ - -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DMA_Exported_macros DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state - * @param __HANDLE__: DMA handle. - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None. - */ -#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None. - */ -#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) - - -/* Interrupt & Flag management */ - -/** - * @brief Enables the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) - -/** - * @brief Disables the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) - -/** - * @brief Checks whether the specified DMA Channel interrupt has occurred or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** - * @} - */ - - -/* Include DMA HAL Extension module */ -#include "stm32l1xx_hal_dma_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions - * @{ - */ - - -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); - -/* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h deleted file mode 100644 index c1feb45bc..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h +++ /dev/null @@ -1,248 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dma_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of DMA HAL extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_DMA_EX_H -#define __STM32L1xx_HAL_DMA_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMAEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros - * @{ - */ - -/* Interrupt & Flag management */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer complete flag index. - */ - -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - DMA_FLAG_TC5) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - DMA_FLAG_HT5) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - DMA_FLAG_TE5) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ - (DMA1->ISR & (__FLAG__))) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 or 1_5 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ - (DMA1->IFCR = (__FLAG__))) - -#else -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_DMA_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h deleted file mode 100644 index 5bbe8c878..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of Flash HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_FLASH_H -#define __STM32L1xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Error structure definition - */ -typedef enum -{ - FLASH_ERROR_SIZE = 0x01, - FLASH_ERROR_OPTV = 0x02, - FLASH_ERROR_OPTVUSR = 0x04, - FLASH_ERROR_PGA = 0x08, - FLASH_ERROR_WRP = 0x10, - FLASH_ERROR_RD = 0x20, - FLASH_ERROR_OPERATION = 0x40 -}FLASH_ErrorTypeDef; - - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0, - FLASH_PROC_PAGEERASE, - FLASH_PROC_PROGRAM -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ - - __IO uint32_t NbPagesToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ - - __IO uint32_t Page; /*Internal variable to define the current sector which is erasing*/ - - __IO uint32_t Address; /*Internal variable to save address selected for program*/ - - HAL_LockTypeDef Lock; /* FLASH locking object */ - - __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */ - -}FLASH_ProcessTypeDef; - -/** - * @} - */ - -/** @addtogroup FLASH_Internal_Variables - * @{ - */ - -/** - * @brief Variable used for Program/Erase sectors under interruption. - * Put as extern as used also in flash_ex.c. - */ -extern FLASH_ProcessTypeDef ProcFlash; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000) /* 50 s */ - -#define FLASH_PAGE_SIZE ((uint32_t)256) - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */ - -#define IS_TYPEPROGRAMFLASH(_VALUE_) (((_VALUE_) == TYPEPROGRAM_WORD)) - -/** - * @} - */ - -/** @defgroup FLASH_Latency FLASH Latency - * @{ - */ -#define FLASH_LATENCY_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */ -#define FLASH_LATENCY_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */ - -#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ - ((__LATENCY__) == FLASH_LATENCY_1)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts FLASH Interrupts - * @{ - */ - -#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */ -#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */ -/** - * @} - */ - -/** @defgroup FLASH_Flags FLASH Flags - * @{ - */ - -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ -#define FLASH_FLAG_ENDHV FLASH_SR_ENDHV /*!< FLASH End of High Voltage flag */ -#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ -#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */ - -/** - * @} - */ - -/** @defgroup FLASH_Keys FLASH Keys - * @{ - */ - -#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */ -#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 - to unlock the RUN_PD bit in FLASH_ACR */ - -#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */ -#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2 - to unlock the write access to the FLASH_PECR register and - data EEPROM */ - -#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */ -#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2 - to unlock the program memory */ - -#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */ -#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to - unlock the write access to the option byte block */ -/** - * @} - */ - - - -#if defined ( __ICCARM__ ) -#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk -#endif - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @{ - */ - -/** @defgroup FLASH_Interrupt FLASH Interrupts - * @brief macros to handle FLASH interrupts - * @{ - */ - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) ((FLASH->PECR) |= (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) ((FLASH->PECR) &= ~(uint32_t)(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY : FLASH Busy flag - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_ENDHV : FLASH End of High Voltage flag - * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error error flag - * @arg FLASH_FLAG_OPTVERRUSR : FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) - * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_BSY : FLASH Busy flag - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_ENDHV : FLASH End of High Voltage flag - * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error error flag - * @arg FLASH_FLAG_OPTVERRUSR : FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices) - * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Include FLASH HAL Extension module */ -#include "stm32l1xx_hal_flash_ex.h" -#include "stm32l1xx_hal_flash_ramfunc.h" - -/* Exported functions ------------------------------------------------------- */ - -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ - -/** - * @brief FLASH memory functions that can be executed from FLASH. - */ -/* Program operation functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); - -/* FLASH IRQ handler function */ -void HAL_FLASH_IRQHandler(void); - -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ - -/* FLASH Memory Programming functions *****************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); - -/* Option Bytes Programming functions *****************************************/ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral State methods **************************************************/ -FLASH_ErrorTypeDef HAL_FLASH_GetError(void); - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH_Internal_Functions - * @{ - */ - -/** - * @brief Function used internally by HAL FLASH driver. - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h deleted file mode 100644 index 50b5fc7f3..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h +++ /dev/null @@ -1,975 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of Flash HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_FLASH_EX_H -#define __STM32L1xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< TypeErase: Page Erase only. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - - uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased - This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ - - uint32_t NbPages; /*!< NbPages: Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes PROGRAM structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASHEx_Option_Type */ - - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_WRP_State */ - - uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ - - uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. - This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - - uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ - - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ -} FLASH_OBProgramInitTypeDef; - -/** - * @brief FLASH Advanced Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . - This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. - This parameter can be a value of @ref FLASHEx_PCROP_State */ - - uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */ - -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ -#endif /* STM32L151xC || STM32L152xC || STM32L162xC */ -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config - This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ -} FLASH_AdvOBProgramInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase - * @{ - */ -#define TYPEERASE_PAGES ((uint32_t)0x00) /*!= 256KB*/ -#define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */ -#define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */ -#define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */ -#define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */ -#define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */ -#define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */ -#define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */ -#define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */ -#define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */ -#define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */ -#define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */ -#define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */ -#define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */ -#define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */ -#define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */ -#define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */ -#define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */ -#define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */ -#define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */ -#define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */ -#define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */ -#define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */ -#define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */ -#define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */ -#define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */ -#define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */ -#define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */ -#define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */ -#define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */ -#define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */ -#define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */ -#define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */ - -#define OB_WRP3_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ - -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4 - * @{ - */ - -/* Pages for Cat5 devices*/ -#define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/ -#define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/ -#define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/ -#define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/ -#define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/ -#define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/ -#define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/ -#define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/ -#define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/ -#define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/ -#define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/ -#define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/ -#define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/ -#define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/ -#define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/ -#define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/ -#define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/ -#define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/ -#define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/ -#define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/ -#define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/ -#define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/ -#define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/ -#define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/ -#define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/ -#define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/ -#define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/ -#define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/ -#define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/ -#define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/ -#define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/ -#define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000) /* Write protection of Sector127*/ - -#define OB_WRP4_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ - -/** - * @} - */ - -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ - -/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection - * @{ - */ -#define OB_RDP_LEVEL0 ((uint8_t)0xAA) -#define OB_RDP_LEVEL1 ((uint8_t)0xBB) -/*#define OB_RDP_LEVEL2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ - -#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL0)||\ - ((__LEVEL__) == OB_RDP_LEVEL1))/*||\ - ((__LEVEL__) == OB_RDP_LEVEL2))*/ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level - * @{ - */ - -#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD - power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ -#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ -#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ -#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ -#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ - -#define IS_OB_BOR_LEVEL(__LEVEL__) ( ((__LEVEL__) == OB_BOR_OFF) || \ - ((__LEVEL__) == OB_BOR_LEVEL1) || \ - ((__LEVEL__) == OB_BOR_LEVEL2) || \ - ((__LEVEL__) == OB_BOR_LEVEL3) || \ - ((__LEVEL__) == OB_BOR_LEVEL4) || \ - ((__LEVEL__) == OB_BOR_LEVEL5)) - -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */ - -#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP - * @{ - */ - -#define OB_STOP_NORST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY - * @{ - */ - -#define OB_STDBY_NORST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) - -/** - * @} - */ - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - -/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type - * @{ - */ - -#define OBEX_PCROP ((uint32_t)0x01) /*!= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END)) - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || \ - defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined (STM32L151xCA) || defined (STM32L152xCA) || defined (STM32L162xCA) - -#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) - -#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) -#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) -#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) - -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L152xCA || STM32L162xCA */ - -#define IS_NBPAGES(_PAGES_) (((_PAGES_) >= 1) && ((_PAGES_) <= FLASH_NBPAGES_MAX)) - -/** - * @} - */ - -/** @defgroup FLASHEx_Flags FLASHEx Flags - * @{ - */ - -/* Cat2 & Cat3*/ -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - -#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */ - -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -/* Cat3, Cat4 & Cat5*/ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */ - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/* Cat1*/ -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined (STM32L100xBA) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR) - -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA */ - -/* RDERR only for STM32L151xBA & STM32L152xBA (Cat2)*/ -#if defined (STM32L151xBA) || defined (STM32L152xBA) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_RDERR) - -#endif /* STM32L151xBA || STM32L152xBA */ - -/* FLASH_FLAG_OPTVERRUSR & RDERR only for STM32L151xC, STM32L152xC & STM32L152xBA (Cat3) */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC */ - -/* FLASH_FLAG_OPTVERRUSR only for STM32L100xC (Cat3) */ -#if defined (STM32L100xC) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR) - -#endif /* STM32L100xC */ - -/* Cat4 & Cat5 */ -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT - * @{ - */ - -#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank 2 - or Bank 1, depending on the activation of the bank */ -#define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank1(Default) */ -#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) - -/** - * @} - */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros - * @{ - */ - -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle - * @arg FLASH_LATENCY_1: FLASH One Latency cycle - * @retval none - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \ - if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \ - MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \ - } while(0) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle - * @arg FLASH_LATENCY_1: FLASH One Latency cycle - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - - /** - * @brief Enable the FLASH 64-bit access. - * @note Read access 64 bit is used. - * @note This bit cannot be written at the same time as the LATENCY and - * PRFTEN bits. - * @retval none - */ -#define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64)) - - /** - * @brief Disable the FLASH 64-bit access. - * @note Read access 32 bit is used - * @note To reset this bit, the LATENCY should be zero wait state and the - * prefetch off. - * @retval none - */ -#define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64)) - - /** - * @brief Enable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \ - SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \ - } while(0) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) - -/** - * @brief Enable the FLASH power down during Sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @brief Disable the FLASH power down during Sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @brief Macro to enable or disable the Flash Run power down mode. - * @note Writing this bit to 0 this bit, automatically the keys are - * loss and a new unlock sequence is necessary to re-write it to 1. - */ - -#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ - FLASH->PDKEYR = FLASH_PDKEY2; \ - SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ - } while (0) - -#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ - FLASH->PDKEYR = FLASH_PDKEY2; \ - CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ - } while (0) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); - -/** - * @} - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); -void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); - -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - -HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); -HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); - -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -/** - * @} - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group3 - * @{ - */ - -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); - -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address); -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); -void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); -void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_FLASH_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h deleted file mode 100644 index a4b2f3242..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash_ramfunc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of FLASH RAMFUNC driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_FLASH_RAMFUNC_H -#define __STM32L1xx_FLASH_RAMFUNC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHRamfunc - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup FLASHRamfunc_Exported_Functions - * @{ - */ - -/* - * @brief FLASH memory functions that should be executed from internal SRAM. - * These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c" - * file. - */ - -/** @addtogroup FLASHRamfunc_Exported_Functions_Group1 - * @{ - */ - -__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); -__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); - -/** - * @} - */ - -/** @addtogroup FLASHRamfunc_Exported_Functions_Group2 - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); -__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); - -/** - * @} - */ - -/** @addtogroup FLASHRamfunc_Exported_Functions_Group3 - * @{ - */ - -__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address); -__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_FLASH_RAMFUNC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h deleted file mode 100644 index fab2e3fd0..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h +++ /dev/null @@ -1,331 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_gpio.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_GPIO_H -#define __STM32L1xx_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode_define */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull_define */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed_define */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins - This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ -}GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0, - GPIO_PIN_SET -}GPIO_PinState; - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_pins_define GPIO pins define - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ -/** - * @} - */ - - -/** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) - * @{ - */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ - -/** - * @} - */ - - -/** @defgroup GPIO_speed_define GPIO speed define - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_VERY_LOW ((uint32_t)0x00000000) /*!< Very Low speed */ -#define GPIO_SPEED_LOW ((uint32_t)0x00000001) /*!< Low speed */ -#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000002) /*!< Medium speed */ -#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ - -/** - * @} - */ - - - /** @defgroup GPIO_pull_define GPIO pull define - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ - -/** - * @} - */ - -/** - * @} - */ - - -/* Private macros --------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Macros - * @{ - */ - -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) - -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_VERY_LOW) || ((SPEED) == GPIO_SPEED_LOW) || \ - ((SPEED) == GPIO_SPEED_MEDIUM) || ((SPEED) == GPIO_SPEED_HIGH)) - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) - -/* Include GPIO HAL Extension module */ -#include "stm32l1xx_hal_gpio_ex.h" -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *******************************/ -/** @addtogroup GPIO_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * - * @{ - */ - -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -/** - * @} - */ - -/* IO operation functions *******************************************************/ -/** @addtogroup GPIO_Exported_Functions_Group2 - * @brief Initialization and Configuration functions - * - * @{ - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h deleted file mode 100644 index ba82ea56c..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h +++ /dev/null @@ -1,260 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_gpio_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of GPIO HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_GPIO_EX_H -#define __STM32L1xx_HAL_GPIO_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants - * @{ - */ - -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ - -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_OUT Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) ||\ - defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) - -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ - -#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE */ - - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#if defined (STM32L151xD) || defined (STM32L151xE) ||\ - defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xD) || defined (STM32L162xE) - -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ - -#endif /* STM32L151xD || STM32L151xE || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE */ - - -/** - * @brief AF 9 selection - */ - -/** - * @brief AF 10 selection - */ - -/** - * @brief AF 11 selection - */ -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) - -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ - -#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE */ - -/** - * @brief AF 12 selection - */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -/** - * @brief AF 13 selection - */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /* TIMER INPUT CAPTURE Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros - * @{ - */ - - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) -#endif - -#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) -#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) -#endif - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) -#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) -#endif - - - -/** - * @} - */ - - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h deleted file mode 100644 index cabf29d17..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h +++ /dev/null @@ -1,538 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_i2c.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_I2C_H -#define __STM32L1xx_HAL_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** - * @brief I2C Configuration Structure definition - */ -typedef struct -{ - uint32_t ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_addressing_mode */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_dual_addressing_mode */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_general_call_addressing_mode */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_nostretch_mode */ - -}I2C_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ - HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */ - HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */ - HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */ - HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */ - -}HAL_I2C_StateTypeDef; - -/** - * @brief HAL I2C Error Code structure definition - */ -typedef enum -{ - HAL_I2C_ERROR_NONE = 0x00, /*!< No error */ - HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */ - HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */ - HAL_I2C_ERROR_AF = 0x04, /*!< AF error */ - HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */ - HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */ - -}HAL_I2C_ErrorTypeDef; - -/** - * @brief I2C handle Structure definition - */ -typedef struct -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */ - -}I2C_HandleTypeDef; -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode I2C_duty_cycle_in_fast_mode - * @{ - */ -#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000) -#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY - -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ - ((CYCLE) == I2C_DUTYCYCLE_16_9)) -/** - * @} - */ - -/** @defgroup I2C_addressing_mode I2C_addressing_mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000) -#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000)) - -#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ - ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) -/** - * @} - */ - -/** @defgroup I2C_dual_addressing_mode I2C_dual_addressing_mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000) -#define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLED)) -/** - * @} - */ - -/** @defgroup I2C_general_call_addressing_mode I2C_general_call_addressing_mode - * @{ - */ -#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000) -#define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \ - ((CALL) == I2C_GENERALCALL_ENABLED)) -/** - * @} - */ - -/** @defgroup I2C_nostretch_mode I2C_nostretch_mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000) -#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLED)) -/** - * @} - */ - -/** @defgroup I2C_Memory_Address_Size I2C_Memory_Address_Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C_Interrupt_configuration_definition - * @{ - */ -#define I2C_IT_BUF I2C_CR2_ITBUFEN -#define I2C_IT_EVT I2C_CR2_ITEVTEN -#define I2C_IT_ERR I2C_CR2_ITERREN -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C_Flag_definition - * @{ - */ -#define I2C_FLAG_OVR ((uint32_t)(1 << 16 | I2C_SR1_OVR)) -#define I2C_FLAG_AF ((uint32_t)(1 << 16 | I2C_SR1_AF)) -#define I2C_FLAG_ARLO ((uint32_t)(1 << 16 | I2C_SR1_ARLO)) -#define I2C_FLAG_BERR ((uint32_t)(1 << 16 | I2C_SR1_BERR)) -#define I2C_FLAG_TXE ((uint32_t)(1 << 16 | I2C_SR1_TXE)) -#define I2C_FLAG_RXNE ((uint32_t)(1 << 16 | I2C_SR1_RXNE)) -#define I2C_FLAG_STOPF ((uint32_t)(1 << 16 | I2C_SR1_STOPF)) -#define I2C_FLAG_ADD10 ((uint32_t)(1 << 16 | I2C_SR1_ADD10)) -#define I2C_FLAG_BTF ((uint32_t)(1 << 16 | I2C_SR1_BTF)) -#define I2C_FLAG_ADDR ((uint32_t)(1 << 16 | I2C_SR1_ADDR)) -#define I2C_FLAG_SB ((uint32_t)(1 << 16 | I2C_SR1_SB)) -#define I2C_FLAG_DUALF ((uint32_t)(2 << 16 | I2C_SR2_DUALF)) -#define I2C_FLAG_GENCALL ((uint32_t)(2 << 16 | I2C_SR2_GENCALL)) -#define I2C_FLAG_TRA ((uint32_t)(2 << 16 | I2C_SR2_TRA)) -#define I2C_FLAG_BUSY ((uint32_t)(2 << 16 | I2C_SR2_BUSY)) -#define I2C_FLAG_MSL ((uint32_t)(2 << 16 | I2C_SR2_MSL)) - - -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF) - -/** - * @} - */ - -/** @defgroup I2C_Clock_Speed_definition I2C_Clock_Speed_definition - * @{ - */ -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** @defgroup I2C_Own_Address1_definition I2C_Own_Address1_definition - * @{ - */ -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0) -/** - * @} - */ - -/** @defgroup I2C_Own_Address2_definition I2C_Own_Address2_definition - * @{ - */ -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) - -/** @brief Enable or disable the specified I2C interrupts. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg I2C_IT_BUF: Buffer interrupt enable - * @arg I2C_IT_EVT: Event interrupt enable - * @arg I2C_IT_ERR: Error interrupt enable - * @retval None - */ - -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) - -/** @brief Checks if the specified I2C interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_BUF: Buffer interrupt enable - * @arg I2C_IT_EVT: Event interrupt enable - * @arg I2C_IT_ERR: Error interrupt enable - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks whether the specified I2C flag is set or not. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_OVR: Overrun/Underrun flag - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag - * @arg I2C_FLAG_RXNE: Data register not empty flag - * @arg I2C_FLAG_STOPF: Stop detection flag - * @arg I2C_FLAG_ADD10: 10-bit header sent flag - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag - * Address matched flag - * @arg I2C_FLAG_SB: Start bit flag - * @arg I2C_FLAG_DUALF: Dual flag - * @arg I2C_FLAG_GENCALL: General call header flag - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ - ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) - -/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) - -/** @brief Clears the I2C ADDR pending flag. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @retval None - */ - -#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\ - (__HANDLE__)->Instance->SR2;}while(0) - -/** @brief Clears the I2C STOPF pending flag. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\ - SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);}while(0) - -/** @brief Enable the I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) - -/** @brief Disable the I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) - -/** - * @} - */ - -/** @defgroup I2C_Private_Macros I2C Private Macros - * @{ - */ - -#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000) -#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1)) -#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1))) -#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9)) -#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) - -#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) -#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) - -#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) -#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) -#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -/** @addtogroup I2C_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - - -/* I/O operation functions *****************************************************/ -/** @addtogroup I2C_Exported_Functions_Group2 - * @{ - */ - -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - - -/* Peripheral Control and State functions **************************************/ -/** @addtogroup I2C_Exported_Functions_Group3 - * @{ - */ - -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** - * @} - */ - - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h deleted file mode 100644 index 63704acbb..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h +++ /dev/null @@ -1,454 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_i2s.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of I2S HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_I2S_H -#define __STM32L1xx_HAL_I2S_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L100xC) || \ - defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \ - defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L151xE) || \ - defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2S - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2S_Exported_Types I2S Exported Types - * @{ - */ - -/** - * @brief I2S Init structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint32_t Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ - -}I2S_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S pause state: used in case of DMA */ - HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ -}HAL_I2S_StateTypeDef; - -/** - * @brief HAL I2S Error Code structure definition - */ -typedef enum -{ - HAL_I2S_ERROR_NONE = 0x00, /*!< No error */ - HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */ - HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */ - HAL_I2S_ERROR_FRE = 0x04, /*!< I2S Frame format error */ - HAL_I2S_ERROR_DMA = 0x08 /*!< DMA transfer error */ -}HAL_I2S_ErrorTypeDef; - -/** - * @brief I2S handle Structure definition - */ -typedef struct -{ - SPI_TypeDef *Instance; /* I2S registers base address */ - - I2S_InitTypeDef Init; /* I2S communication parameters */ - - uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */ - - __IO uint16_t TxXferSize; /* I2S Tx transfer size */ - - __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ - - uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */ - - __IO uint16_t RxXferSize; /* I2S Rx transfer size */ - - __IO uint16_t RxXferCount; /* I2S Rx transfer counter - (This field is initialized at the - same value as transfer size at the - beginning of the transfer and - decremented when a sample is received. - NbSamplesReceived = RxBufferSize-RxBufferCount) */ - - DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ - - __IO HAL_LockTypeDef Lock; /* I2S locking object */ - - __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ - - __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */ - -}I2S_HandleTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2S_Exported_Constants I2S Exported Constants - * @{ - */ - -/** @defgroup I2S_Mode I2S Mode - * @{ - */ -#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) -#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) -#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) -#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) - -#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ - ((MODE) == I2S_MODE_SLAVE_RX) || \ - ((MODE) == I2S_MODE_MASTER_TX) || \ - ((MODE) == I2S_MODE_MASTER_RX)) -/** - * @} - */ - -/** @defgroup I2S_Standard I2S Standard - * @{ - */ -#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) -#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0) -#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1) -#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ - SPI_I2SCFGR_I2SSTD_1)) -#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ - SPI_I2SCFGR_I2SSTD_1 |\ - SPI_I2SCFGR_PCMSYNC)) - -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ - ((STANDARD) == I2S_STANDARD_MSB) || \ - ((STANDARD) == I2S_STANDARD_LSB) || \ - ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ - ((STANDARD) == I2S_STANDARD_PCM_LONG)) -/** @defgroup I2S_Legacy I2S Legacy - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2S_Data_Format I2S Data Format - * @{ - */ -#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) -#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN) -#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) -#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) - -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ - ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ - ((FORMAT) == I2S_DATAFORMAT_24B) || \ - ((FORMAT) == I2S_DATAFORMAT_32B)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output I2S MCLK Output - * @{ - */ -#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) - -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ - ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency I2S Audio Frequency - * @{ - */ -#define I2S_AUDIOFREQ_192K ((uint32_t)192000) -#define I2S_AUDIOFREQ_96K ((uint32_t)96000) -#define I2S_AUDIOFREQ_48K ((uint32_t)48000) -#define I2S_AUDIOFREQ_44K ((uint32_t)44100) -#define I2S_AUDIOFREQ_32K ((uint32_t)32000) -#define I2S_AUDIOFREQ_22K ((uint32_t)22050) -#define I2S_AUDIOFREQ_16K ((uint32_t)16000) -#define I2S_AUDIOFREQ_11K ((uint32_t)11025) -#define I2S_AUDIOFREQ_8K ((uint32_t)8000) -#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ - ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ - ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity I2S Clock Polarity - * @{ - */ -#define I2S_CPOL_LOW ((uint32_t)0x00000000) -#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) - -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ - ((CPOL) == I2S_CPOL_HIGH)) -/** - * @} - */ - -/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition - * @{ - */ -#define I2S_IT_TXE SPI_CR2_TXEIE -#define I2S_IT_RXNE SPI_CR2_RXNEIE -#define I2S_IT_ERR SPI_CR2_ERRIE -/** - * @} - */ - -/** @defgroup I2S_Flag_definition I2S Flag definition - * @{ - */ -#define I2S_FLAG_TXE SPI_SR_TXE -#define I2S_FLAG_RXNE SPI_SR_RXNE - -#define I2S_FLAG_UDR SPI_SR_UDR -#define I2S_FLAG_OVR SPI_SR_OVR -#define I2S_FLAG_FRE SPI_SR_FRE - -#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE -#define I2S_FLAG_BSY SPI_SR_BSY -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2S_Exported_macros I2S Exported Macros - * @{ - */ - -/** @brief Reset I2S handle state - * @param __HANDLE__: specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) - -/** @brief Enable or disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__: specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) -#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - -/** @brief Enable or disable the specified I2S interrupts. - * @param __HANDLE__: specifies the I2S Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) -#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) - -/** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2S Handle. - * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__: specifies the I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__: specifies the I2S Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2S_FLAG_RXNE: Receive buffer not empty flag - * @arg I2S_FLAG_TXE: Transmit buffer empty flag - * @arg I2S_FLAG_UDR: Underrun flag - * @arg I2S_FLAG_OVR: Overrun flag - * @arg I2S_FLAG_FRE: Frame error flag - * @arg I2S_FLAG_CHSIDE: Channel Side flag - * @arg I2S_FLAG_BSY: Busy flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__: specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\ - tmpreg = (__HANDLE__)->Instance->SR;\ - }while(0) -/** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__: specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2S_Exported_Functions - * @{ - */ - -/** @addtogroup I2S_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s); -void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); -void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); -/** - * @} - */ - -/** @addtogroup I2S_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ***************************************************/ - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); - - /* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); - -/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ -void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); -/** - * @} - */ - -/** @addtogroup I2S_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32L100xC || - STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\ - STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L151xE ||\\ - STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_I2S_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h deleted file mode 100644 index ca1264730..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h +++ /dev/null @@ -1,535 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_irda.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains all the functions prototypes for the IRDA - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_IRDA_H -#define __STM32L1xx_HAL_IRDA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup IRDA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Types IRDA Exported Types - * @{ - */ - -/** - * @brief IRDA Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref IRDA_Word_Length */ - - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref IRDA_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref IRDA_Transfer_Mode */ - - uint8_t Prescaler; /*!< Specifies the Prescaler */ - - uint32_t IrDAMode; /*!< Specifies the IrDA mode - This parameter can be a value of @ref IRDA_Low_Power */ -}IRDA_InitTypeDef; - -/** - * @brief HAL IRDA State structures definition - */ -typedef enum -{ - HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ -}HAL_IRDA_StateTypeDef; - -/** - * @brief HAL IRDA Error Code structure definition - */ -typedef enum -{ - HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */ - HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */ - HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */ - HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */ - HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_IRDA_ErrorTypeDef; - -/** - * @brief IRDA handle Structure definition - */ -typedef struct -{ - USART_TypeDef *Instance; /* USART registers base address */ - - IRDA_InitTypeDef Init; /* IRDA communication parameters */ - - uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */ - - uint16_t TxXferSize; /* IRDA Tx Transfer size */ - - uint16_t TxXferCount; /* IRDA Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */ - - uint16_t RxXferSize; /* IRDA Rx Transfer size */ - - uint16_t RxXferCount; /* IRDA Rx Transfer Counter */ - - DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /* Locking object */ - - __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */ - - __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */ - -}IRDA_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Constants IRDA Exported constants - * @{ - */ - -/** @defgroup IRDA_Word_Length IRDA Word Length - * @{ - */ -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) -#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ - ((LENGTH) == IRDA_WORDLENGTH_9B)) -/** - * @} - */ - - -/** @defgroup IRDA_Parity IRDA Parity - * @{ - */ -#define IRDA_PARITY_NONE ((uint32_t)0x00000000) -#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ - ((PARITY) == IRDA_PARITY_EVEN) || \ - ((PARITY) == IRDA_PARITY_ODD)) -/** - * @} - */ - - -/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode - * @{ - */ -#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) -#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) -#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000)) -/** - * @} - */ - -/** @defgroup IRDA_Low_Power IRDA Low Power - * @{ - */ -#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) -#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) -#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ - ((MODE) == IRDA_POWERMODE_NORMAL)) -/** - * @} - */ - -/** @defgroup IRDA_Flags IRDA Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the SR register - * @{ - */ -#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC) -#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE) -#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE) -#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE) -/** - * @} - */ - -/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions - * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register - * - Y : Interrupt source register (4 bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - * @{ - */ - -#define IRDA_IT_PE ((uint32_t)0x10000100) -#define IRDA_IT_TXE ((uint32_t)0x10000080) -#define IRDA_IT_TC ((uint32_t)0x10000040) -#define IRDA_IT_RXNE ((uint32_t)0x10000020) -#define IRDA_IT_IDLE ((uint32_t)0x10000010) - -#define IRDA_IT_LBD ((uint32_t)0x20000040) - -#define IRDA_IT_CTS ((uint32_t)0x30000400) -#define IRDA_IT_ERR ((uint32_t)0x30000001) - -/** - * @} - */ - -/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask - * @{ - */ -#define IRDA_IT_MASK ((uint32_t)0x0000FFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Macros IRDA Exported Macros - * @{ - */ - -/** @brief Reset IRDA handle state - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) - -/** @brief Flushs the IRDA DR register - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - */ -#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) - -/** @brief Checks whether the specified IRDA flag is set or not. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IRDA_FLAG_TXE: Transmit data register empty flag - * @arg IRDA_FLAG_TC: Transmission Complete flag - * @arg IRDA_FLAG_RXNE: Receive data register not empty flag - * @arg IRDA_FLAG_IDLE: Idle Line detection flag - * @arg IRDA_FLAG_ORE: OverRun Error flag - * @arg IRDA_FLAG_NE: Noise Error flag - * @arg IRDA_FLAG_FE: Framing Error flag - * @arg IRDA_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified IRDA pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __FLAG__: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg IRDA_FLAG_TC: Transmission Complete flag. - * @arg IRDA_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register followed by a read - * operation to USART_DR register. - * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. - * - * @retval None - */ -#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) -/** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Enables the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. - * This parameter can be one of the following values: - * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt - * @arg IRDA_IT_TC: Transmission complete interrupt - * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt - * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg IRDA_IT_PE: Parity Error interrupt - * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK))) - -/** @brief Disables the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. - * This parameter can be one of the following values: - * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt - * @arg IRDA_IT_TC: Transmission complete interrupt - * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt - * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg IRDA_IT_PE: Parity Error interrupt - * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK))) - -/** @brief Checks whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __IT__: specifies the IRDA interrupt source to check. - * This parameter can be one of the following values: - * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt - * @arg IRDA_IT_TC: Transmission complete interrupt - * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt - * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ERR: Error interrupt - * @arg IRDA_IT_PE: Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK)) - -/** @brief Enable UART/USART associated to IRDA Handle - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) - -/** @brief Disable UART/USART associated to IRDA Handle - * @param __HANDLE__: specifies the IRDA Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup IRDA_Private_Macros IRDA Private Macros - * @{ - */ - -#define IRDA_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) -#define IRDA_DIVMANT(__PCLK__, __BAUD__) (IRDA_DIV((__PCLK__), (__BAUD__))/100) -#define IRDA_DIVFRAQ(__PCLK__, __BAUD__) (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -#define IRDA_BRR(__PCLK__, __BAUD__) ((IRDA_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(IRDA_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) - -/** @brief Ensure that IRDA Baud rate is less or equal to maximum value - * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. - * @retval True or False - */ -#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions - * @{ - */ - -/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); - -/** - * @} - */ - -/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); - -/** - * @} - */ - -/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ - -/* Peripheral State and Error functions ***************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_IRDA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h deleted file mode 100644 index 6c7842d73..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h +++ /dev/null @@ -1,291 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_iwdg.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of IWDG HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_IWDG_H -#define __STM32L1xx_HAL_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Types IWDG Exported Types - * @{ - */ - -/** - * @brief IWDG HAL State Structure definition - */ -typedef enum -{ - HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ - HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ - HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ - HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ - HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ - -}HAL_IWDG_StateTypeDef; - -/** - * @brief IWDG Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Select the prescaler of the IWDG. - This parameter can be a value of @ref IWDG_Prescaler */ - - uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ - -}IWDG_InitTypeDef; - -/** - * @brief IWDG Handle Structure definition - */ -typedef struct -{ - IWDG_TypeDef *Instance; /*!< Register base address */ - - IWDG_InitTypeDef Init; /*!< IWDG required parameters */ - - HAL_LockTypeDef Lock; /*!< IWDG Locking object */ - - __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ - -}IWDG_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants IWDG Exported Constants - * @{ - */ - -/** @defgroup IWDG_Registers_BitMask IWDG_Registers_BitMask - * @brief IWDG registers bit mask - * @{ - */ -/* --- KR Register ---*/ -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ -#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ -#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ -#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ - -#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \ - ((__KR__) == KR_KEY_ENABLE))|| \ - ((__KR__) == KR_KEY_EWA)) || \ - ((__KR__) == KR_KEY_DWA)) -/** - * @} - */ - -/** @defgroup IWDG_Flag_definition IWDG_Flag_definition - * @{ - */ -#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */ -#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */ - -/** - * @} - */ - -/** @defgroup IWDG_Prescaler IWDG_Prescaler - * @{ - */ -#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ - -#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ - ((__PRESCALER__) == IWDG_PRESCALER_8) || \ - ((__PRESCALER__) == IWDG_PRESCALER_16) || \ - ((__PRESCALER__) == IWDG_PRESCALER_32) || \ - ((__PRESCALER__) == IWDG_PRESCALER_64) || \ - ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ - ((__PRESCALER__) == IWDG_PRESCALER_256)) - -/** - * @} - */ - -/** @defgroup IWDG_Reload_Value IWDG_Reload_Value - * @{ - */ -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Macros IWDG Exported Macros - * @{ - */ - -/** @brief Reset IWDG handle state - * @param __HANDLE__: IWDG handle. - * @retval None - */ -#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) - -/** - * @brief Enables the IWDG peripheral. - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE) - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD) - -/** - * @brief Enables write access to IWDG_PR and IWDG_RLR registers. - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA) - -/** - * @brief Disables write access to IWDG_PR and IWDG_RLR registers. - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA) - -/** - * @brief Gets the selected IWDG's flag status. - * @param __HANDLE__: IWDG handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag - * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup IWDG_Exported_Functions - * @{ - */ - -/** @addtogroup IWDG_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); -void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); - -/** - * @} - */ - -/** @addtogroup IWDG_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); - -/** - * @} - */ - -/** @addtogroup IWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h deleted file mode 100644 index e65ec99ce..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h +++ /dev/null @@ -1,763 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_lcd.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of LCD Controller HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_LCD_H -#define __STM32L1xx_HAL_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup LCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup LCD_Exported_Types LCD Exported Types - * @{ - */ - -/** - * @brief LCD Init structure definition - */ - -typedef struct -{ - uint32_t Prescaler; /*!< Configures the LCD Prescaler. - This parameter can be one value of @ref LCD_Prescaler */ - uint32_t Divider; /*!< Configures the LCD Divider. - This parameter can be one value of @ref LCD_Divider */ - uint32_t Duty; /*!< Configures the LCD Duty. - This parameter can be one value of @ref LCD_Duty */ - uint32_t Bias; /*!< Configures the LCD Bias. - This parameter can be one value of @ref LCD_Bias */ - uint32_t VoltageSource; /*!< Selects the LCD Voltage source. - This parameter can be one value of @ref LCD_Voltage_Source */ - uint32_t Contrast; /*!< Configures the LCD Contrast. - This parameter can be one value of @ref LCD_Contrast */ - uint32_t DeadTime; /*!< Configures the LCD Dead Time. - This parameter can be one value of @ref LCD_DeadTime */ - uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration. - This parameter can be one value of @ref LCD_PulseOnDuration */ - uint32_t BlinkMode; /*!< Configures the LCD Blink Mode. - This parameter can be one value of @ref LCD_BlinkMode */ - uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency. - This parameter can be one value of @ref LCD_BlinkFrequency */ - uint32_t MuxSegment; /*!< Enable or disable mux segment. - This parameter can be set to ENABLE or DISABLE. */ -}LCD_InitTypeDef; - -/** - * @brief HAL LCD State structures definition - */ -typedef enum -{ - HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_LCD_STATE_ERROR = 0x04 /*!< Error */ -}HAL_LCD_StateTypeDef; - -/** - * @brief HAL LCD Error Code structure definition - */ -typedef enum -{ - HAL_LCD_ERROR_NONE = 0x00, /*!< No error */ - HAL_LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag timeout error */ - HAL_LCD_ERROR_UDR = 0x02, /*!< Update display request flag timeout error */ - HAL_LCD_ERROR_UDD = 0x04, /*!< Update display done flag timeout error */ - HAL_LCD_ERROR_ENS = 0x08, /*!< LCD enabled status flag timeout error */ - HAL_LCD_ERROR_RDY = 0x10 /*!< LCD Booster ready timeout error */ -}HAL_LCD_ErrorTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct -{ - LCD_TypeDef *Instance; /* LCD registers base address */ - - LCD_InitTypeDef Init; /* LCD communication parameters */ - - HAL_LockTypeDef Lock; /* Locking object */ - - __IO HAL_LCD_StateTypeDef State; /* LCD communication state */ - - __IO HAL_LCD_ErrorTypeDef ErrorCode; /* LCD Error code */ - -}LCD_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup LCD_Exported_Constants LCD Exported Constants - * @{ - */ - -/** @defgroup LCD_Prescaler LCD Prescaler - * @{ - */ - -#define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */ -#define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */ -#define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */ -#define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */ -#define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */ -#define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */ -#define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */ -#define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */ -#define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */ -#define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */ -#define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */ -#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */ -#define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ -#define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ -#define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ -#define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */ - -#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \ - ((__PRESCALER__) == LCD_PRESCALER_2) || \ - ((__PRESCALER__) == LCD_PRESCALER_4) || \ - ((__PRESCALER__) == LCD_PRESCALER_8) || \ - ((__PRESCALER__) == LCD_PRESCALER_16) || \ - ((__PRESCALER__) == LCD_PRESCALER_32) || \ - ((__PRESCALER__) == LCD_PRESCALER_64) || \ - ((__PRESCALER__) == LCD_PRESCALER_128) || \ - ((__PRESCALER__) == LCD_PRESCALER_256) || \ - ((__PRESCALER__) == LCD_PRESCALER_512) || \ - ((__PRESCALER__) == LCD_PRESCALER_1024) || \ - ((__PRESCALER__) == LCD_PRESCALER_2048) || \ - ((__PRESCALER__) == LCD_PRESCALER_4096) || \ - ((__PRESCALER__) == LCD_PRESCALER_8192) || \ - ((__PRESCALER__) == LCD_PRESCALER_16384) || \ - ((__PRESCALER__) == LCD_PRESCALER_32768)) - -/** - * @} - */ - -/** @defgroup LCD_Divider LCD Divider - * @{ - */ - -#define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */ -#define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */ -#define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */ -#define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */ -#define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */ -#define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */ -#define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */ -#define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */ -#define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */ -#define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */ -#define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */ -#define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */ -#define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ -#define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ -#define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ -#define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */ - -#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \ - ((__DIVIDER__) == LCD_DIVIDER_17) || \ - ((__DIVIDER__) == LCD_DIVIDER_18) || \ - ((__DIVIDER__) == LCD_DIVIDER_19) || \ - ((__DIVIDER__) == LCD_DIVIDER_20) || \ - ((__DIVIDER__) == LCD_DIVIDER_21) || \ - ((__DIVIDER__) == LCD_DIVIDER_22) || \ - ((__DIVIDER__) == LCD_DIVIDER_23) || \ - ((__DIVIDER__) == LCD_DIVIDER_24) || \ - ((__DIVIDER__) == LCD_DIVIDER_25) || \ - ((__DIVIDER__) == LCD_DIVIDER_26) || \ - ((__DIVIDER__) == LCD_DIVIDER_27) || \ - ((__DIVIDER__) == LCD_DIVIDER_28) || \ - ((__DIVIDER__) == LCD_DIVIDER_29) || \ - ((__DIVIDER__) == LCD_DIVIDER_30) || \ - ((__DIVIDER__) == LCD_DIVIDER_31)) - -/** - * @} - */ - - -/** @defgroup LCD_Duty LCD Duty - * @{ - */ - -#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */ -#define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */ -#define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */ -#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */ -#define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */ - -#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \ - ((__DUTY__) == LCD_DUTY_1_2) || \ - ((__DUTY__) == LCD_DUTY_1_3) || \ - ((__DUTY__) == LCD_DUTY_1_4) || \ - ((__DUTY__) == LCD_DUTY_1_8)) - -/** - * @} - */ - - -/** @defgroup LCD_Bias LCD Bias - * @{ - */ - -#define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */ -#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ -#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ - -#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \ - ((__BIAS__) == LCD_BIAS_1_2) || \ - ((__BIAS__) == LCD_BIAS_1_3)) -/** - * @} - */ - -/** @defgroup LCD_Voltage_Source LCD Voltage Source - * @{ - */ - -#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */ -#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */ - -#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \ - ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL)) - -/** - * @} - */ - -/** @defgroup LCD_Interrupts LCD Interrupts - * @{ - */ -#define LCD_IT_SOF LCD_FCR_SOFIE -#define LCD_IT_UDD LCD_FCR_UDDIE - -/** - * @} - */ - -/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration - * @{ - */ - -#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ -#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */ -#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */ -#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */ -#define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */ -#define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */ -#define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */ -#define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */ - -#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \ - ((__DURATION__) == LCD_PULSEONDURATION_1) || \ - ((__DURATION__) == LCD_PULSEONDURATION_2) || \ - ((__DURATION__) == LCD_PULSEONDURATION_3) || \ - ((__DURATION__) == LCD_PULSEONDURATION_4) || \ - ((__DURATION__) == LCD_PULSEONDURATION_5) || \ - ((__DURATION__) == LCD_PULSEONDURATION_6) || \ - ((__DURATION__) == LCD_PULSEONDURATION_7)) -/** - * @} - */ - - -/** @defgroup LCD_DeadTime LCD Dead Time - * @{ - */ - -#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */ -#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */ -#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */ -#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */ -#define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */ -#define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */ -#define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */ -#define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */ - -#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \ - ((__TIME__) == LCD_DEADTIME_1) || \ - ((__TIME__) == LCD_DEADTIME_2) || \ - ((__TIME__) == LCD_DEADTIME_3) || \ - ((__TIME__) == LCD_DEADTIME_4) || \ - ((__TIME__) == LCD_DEADTIME_5) || \ - ((__TIME__) == LCD_DEADTIME_6) || \ - ((__TIME__) == LCD_DEADTIME_7)) -/** - * @} - */ - -/** @defgroup LCD_BlinkMode LCD Blink Mode - * @{ - */ - -#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */ -#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ -#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to - 8 pixels according to the programmed duty) */ -#define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */ - -#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \ - ((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \ - ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \ - ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM)) -/** - * @} - */ - -/** @defgroup LCD_BlinkFrequency LCD Blink Frequency - * @{ - */ - -#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ -#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */ -#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */ -#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */ -#define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */ -#define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */ -#define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */ -#define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */ - -#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \ - ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \ - ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \ - ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \ - ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \ - ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \ - ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \ - ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024)) -/** - * @} - */ - -/** @defgroup LCD_Contrast LCD Contrast - * @{ - */ - -#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ -#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */ -#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */ -#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */ -#define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */ -#define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V */ -#define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V */ -#define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.51V */ - -#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \ - ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \ - ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \ - ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \ - ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \ - ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \ - ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \ - ((__CONTRAST__) == LCD_CONTRASTLEVEL_7)) -/** - * @} - */ - -/** @defgroup LCD_MuxSegment LCD Mux Segment - * @{ - */ - -#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */ -#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */ - -#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \ - ((__VALUE__) == LCD_MUXSEGMENT_DISABLE)) -/** - * @} - */ - -/** @defgroup LCD_Flag LCD Flag - * @{ - */ - -#define LCD_FLAG_ENS LCD_SR_ENS -#define LCD_FLAG_SOF LCD_SR_SOF -#define LCD_FLAG_UDR LCD_SR_UDR -#define LCD_FLAG_UDD LCD_SR_UDD -#define LCD_FLAG_RDY LCD_SR_RDY -#define LCD_FLAG_FCRSF LCD_SR_FCRSR - -/** - * @} - */ - -/** @defgroup LCD_RAMRegister LCD RAMRegister - * @{ - */ - -#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */ -#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */ -#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */ -#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */ -#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */ -#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */ -#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */ -#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */ -#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */ -#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */ -#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */ -#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */ -#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */ -#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */ -#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ -#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ - -#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \ - ((__REGISTER__) == LCD_RAM_REGISTER1) || \ - ((__REGISTER__) == LCD_RAM_REGISTER2) || \ - ((__REGISTER__) == LCD_RAM_REGISTER3) || \ - ((__REGISTER__) == LCD_RAM_REGISTER4) || \ - ((__REGISTER__) == LCD_RAM_REGISTER5) || \ - ((__REGISTER__) == LCD_RAM_REGISTER6) || \ - ((__REGISTER__) == LCD_RAM_REGISTER7) || \ - ((__REGISTER__) == LCD_RAM_REGISTER8) || \ - ((__REGISTER__) == LCD_RAM_REGISTER9) || \ - ((__REGISTER__) == LCD_RAM_REGISTER10) || \ - ((__REGISTER__) == LCD_RAM_REGISTER11) || \ - ((__REGISTER__) == LCD_RAM_REGISTER12) || \ - ((__REGISTER__) == LCD_RAM_REGISTER13) || \ - ((__REGISTER__) == LCD_RAM_REGISTER14) || \ - ((__REGISTER__) == LCD_RAM_REGISTER15)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup LCD_Exported_Macros LCD Exported Macros - * @{ - */ - -/** @brief Reset LCD handle state - * @param __HANDLE__: specifies the LCD Handle. - * @retval None - */ -#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET) - -/** @brief macros to enables or disables the LCD - * @param __HANDLE__: specifies the LCD Handle. - * @retval None - */ -#define __HAL_LCD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) -#define __HAL_LCD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) - -/** @brief Macros to enable or disable the low resistance divider. Displays with high - * internal resistance may need a longer drive time to achieve - * satisfactory contrast. This function is useful in this case if some - * additional power consumption can be tolerated. - * @param __HANDLE__: specifies the LCD Handle. - * @note When this mode is enabled, the PulseOn Duration (PON) have to be - * programmed to 1/CK_PS (LCD_PULSEONDURATION_1). - * @retval None - */ -#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) - -#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) - -/** - * @brief Macro to configure the LCD pulses on duration. - * @param __HANDLE__: specifies the LCD Handle. - * @param __DURATION__: specifies the LCD pulse on duration in terms of - * CK_PS (prescaled LCD clock period) pulses. - * This parameter can be one of the following values: - * @arg LCD_PULSEONDURATION_0: 0 pulse - * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS - * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS - * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS - * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS - * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS - * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS - * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS - * @retval None - */ -#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__) \ - do{ \ - MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) - -/** - * @brief Macro to configure the LCD dead time. - * @param __HANDLE__: specifies the LCD Handle. - * @param __DEADTIME__: specifies the LCD dead time. - * This parameter can be one of the following values: - * @arg LCD_DEADTIME_0: No dead Time - * @arg LCD_DEADTIME_1: One Phase between different couple of Frame - * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame - * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame - * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame - * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame - * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame - * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame - * @retval None - */ -#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__) \ - do{ \ - MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) - -/** - * @brief Macro to configure the LCD Contrast. - * @param __HANDLE__: specifies the LCD Handle. - * @param __CONTRAST__: specifies the LCD Contrast. - * This parameter can be one of the following values: - * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V - * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V - * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V - * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V - * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V - * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V - * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V - * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V - * @retval None - */ -#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__) \ - do{ \ - MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \ - LCD_WaitForSynchro(__HANDLE__); \ - } while(0) - -/** - * @brief Macro to configure the LCD Blink mode and Blink frequency. - * @param __HANDLE__: specifies the LCD Handle. - * @param __BLINKMODE__: specifies the LCD blink mode. - * This parameter can be one of the following values: - * @arg LCD_BLINKMODE_OFF: Blink disabled - * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel) - * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 - * pixels according to the programmed duty) - * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM - * (all pixels) - * @param __BLINKFREQUENCY__: specifies the LCD blink frequency. - * @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8 - * @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16 - * @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32 - * @arg LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64 - * @arg LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128 - * @arg LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256 - * @arg LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512 - * @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024 - * @retval None - */ -#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__) \ - do{ \ - MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) - -/** @brief Enables or disables the specified LCD interrupt. - * @param __HANDLE__: specifies the LCD Handle. - * @param __INTERRUPT__: specifies the LCD interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg LCD_IT_SOF: Start of Frame Interrupt - * @arg LCD_IT_UDD: Update Display Done Interrupt - * @retval None - */ -#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) -#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) - -/** @brief Checks whether the specified LCD interrupt is enabled or not. - * @param __HANDLE__: specifies the LCD Handle. - * @param __IT__: specifies the LCD interrupt source to check. - * This parameter can be one of the following values: - * @arg LCD_IT_SOF: Start of Frame Interrupt - * @arg LCD_IT_UDD: Update Display Done Interrupt. - * @note If the device is in STOP mode (PCLK not provided) UDD will not - * generate an interrupt even if UDDIE = 1. - * If the display is not enabled the UDD interrupt will never occur. - * @retval The state of __IT__ (TRUE or FALSE). - */ -#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__)) - -/** @brief Checks whether the specified LCD flag is set or not. - * @param __HANDLE__: specifies the LCD Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. - * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR - * goes from 0 to 1. On deactivation it reflects the real status of - * LCD so it becomes 0 at the end of the last displayed frame. - * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at - * the beginning of a new frame, at the same time as the display data is - * updated. - * @arg LCD_FLAG_UDR: Update Display Request flag. - * @arg LCD_FLAG_UDD: Update Display Done flag. - * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status - * of the step-up converter. - * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. - * This flag is set by hardware each time the LCD_FCR register is updated - * in the LCDCLK domain. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified LCD pending flag. - * @param __HANDLE__: specifies the LCD Handle. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg LCD_FLAG_SOF: Start of Frame Interrupt - * @arg LCD_FLAG_UDD: Update Display Done Interrupt - * @retval None - */ -#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLR = (__FLAG__)) - -/** - * @} - */ - -/* Exported functions ------------------------------------------------------- */ - -/** @addtogroup LCD_Exported_Functions - * @{ - */ - -/** @addtogroup LCD_Exported_Functions_Group1 - * @{ - */ - -/* Initialization/de-initialization methods **********************************/ -HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd); -HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd); -void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd); -void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd); - -/** - * @} - */ - -/** @addtogroup LCD_Exported_Functions_Group2 - * @{ - */ - -/* IO operation methods *******************************************************/ -HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data); -HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd); -HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd); - -/** - * @} - */ - -/** @addtogroup LCD_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral State methods **************************************************/ -HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd); -uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd); - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup LCD_Private_Functions - * @{ - */ - -/* Private functions ---------------------------------------------------------*/ -HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_LCD_H */ - -/******************* (C) COPYRIGHT 2014 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h deleted file mode 100644 index 1401fc2e3..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h +++ /dev/null @@ -1,307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_nor.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of NOR HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_NOR_H -#define __STM32L1xx_HAL_NOR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_ll_fsmc.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup NOR - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup NOR_Exported_typedef NOR Exported typedef - * @{ - */ - -/** - * @brief HAL SRAM State structures definition - */ -typedef enum -{ - HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ - HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ - HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ - HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ - -}HAL_NOR_StateTypeDef; - -/** - * @brief FSMC NOR Status typedef - */ -typedef enum -{ - NOR_SUCCESS = 0, - NOR_ONGOING, - NOR_ERROR, - NOR_TIMEOUT - -}NOR_StatusTypedef; - -/** - * @brief FSMC NOR ID typedef - */ -typedef struct -{ - uint16_t ManufacturerCode; /*!< Defines the device's manufacturer code used to identify the memory */ - - uint16_t DeviceCode1; - - uint16_t DeviceCode2; - - uint16_t DeviceCode3; /*!< Defines the devices' codes used to identify the memory. - These codes can be accessed by performing read operations with specific - control signals and addresses set.They can also be accessed by issuing - an Auto Select command */ - -}NOR_IDTypeDef; - - -/** - * @brief FSMC NOR CFI typedef - */ -typedef struct -{ - /*!< Defines the information stored in the memory's Common flash interface - which contains a description of various electrical and timing parameters, - density information and functions supported by the memory */ - - uint16_t CFI1; - - uint16_t CFI2; - - uint16_t CFI3; - - uint16_t CFI4; - -}NOR_CFITypeDef; - -/** - * @brief NOR handle Structure definition - */ -typedef struct -{ - FSMC_NORSRAM_TYPEDEF *Instance; /*!< Register base address */ - - FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended; /*!< Extended mode register base address */ - - FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ - - HAL_LockTypeDef Lock; /*!< NOR locking object */ - - __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ - -}NOR_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup NOR_Exported_Constants NOR Exported Constants - * @{ - */ - -/* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) - -/* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x10) -#define CFI2_ADDRESS ((uint16_t)0x11) -#define CFI3_ADDRESS ((uint16_t)0x12) -#define CFI4_ADDRESS ((uint16_t)0x13) - -/* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFF) - -/* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) - -/* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup NOR_Exported_macro NOR Exported macro - * @{ - */ - -/** @brief Reset NOR handle state - * @param __HANDLE__: NOR handle - * @retval None - */ -#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) - - -/** - * @brief NOR memory address shifting. - * @param __NOR_ADDRESS: NOR base address - * @param __NOR_MEMORY_WIDTH_: NOR memory width - * @param __ADDRESS__: NOR memory address - * @retval NOR shifted address value - */ -#define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ - ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ - ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) - -/** - * @brief NOR memory write data to specified address. - * @param __ADDRESS__: NOR memory address - * @param __DATA__: Data to write - * @retval None - */ -#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup NOR_Exported_Functions - * @{ - */ - -/** @addtogroup NOR_Exported_Functions_Group1 - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); - -/** - * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group2 - * @{ - */ - -/* I/O operation functions *****************************************************/ -HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); -HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); -HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); - -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); - -HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); -HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); -HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); - -/** - * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group3 - * @{ - */ - -/* NOR Control functions *******************************************************/ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); -HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); - -/** - * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group4 - * @{ - */ - -/* NOR State functions **********************************************************/ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); -NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_NOR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h deleted file mode 100644 index dc6726f76..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h +++ /dev/null @@ -1,533 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_opamp.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of OPAMP HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_OPAMP_H -#define __STM32L1xx_HAL_OPAMP_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup OPAMP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup OPAMP_Exported_Types OPAMP Exported Types - * @{ - */ -/** - * @brief OPAMP Init structure definition - */ - -typedef struct -{ - uint32_t PowerSupplyRange; /*!< Specifies the power supply range: above or under 2.4V. - This parameter must be a value of @ref OPAMP_PowerSupplyRange - Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */ - - uint32_t UserTrimming; /*!< Specifies the trimming mode - This parameter must be a value of @ref OPAMP_UserTrimming - UserTrimming is either factory or user trimming. - Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */ - - uint32_t Mode; /*!< Specifies the OPAMP mode - This parameter must be a value of @ref OPAMP_Mode - mode is either Standalone or Follower */ - - uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone mode - - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE - This parameter must be a value of @ref OPAMP_InvertingInput - InvertingInput is either VM0 or VM1 - - In Follower mode: i.e when mode is OPAMP_FOLLOWER_MODE - This parameter is Not Applicable */ - - uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: - This parameter must be a value of @ref OPAMP_NonInvertingInput - NonInvertingInput is either VP0, VP1 or VP2 */ - - uint32_t PowerMode; /*!< Specifies the power mode Normal or Low-Power. - This parameter must be a value of @ref OPAMP_PowerMode */ - - uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ - - uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ - - uint32_t TrimmingValuePLowPower; /*!< Specifies the offset trimming value (PMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ - - uint32_t TrimmingValueNLowPower; /*!< Specifies the offset trimming value (NMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */ - -}OPAMP_InitTypeDef; - -/** - * @brief HAL State structures definition - */ - -typedef enum -{ - HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPMAP is not yet Initialized */ - - HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */ - HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */ - - HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */ - HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005, /*!< OPAMP is locked - only system reset allows reconfiguring the opamp. */ - -}HAL_OPAMP_StateTypeDef; - -/** - * @brief OPAMP Handle Structure definition - */ -typedef struct -{ - OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */ - OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */ - HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */ - -} OPAMP_HandleTypeDef; - -/** - * @brief OPAMP_TrimmingValueTypeDef @brief definition - */ - -typedef uint32_t OPAMP_TrimmingValueTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants - * @{ - */ - -/** - * OTR register Mask - */ -#define OPAMP_TRIM_VALUE_MASK OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW - -/** - * CSR register Mask - */ -#define OPAMP_CSR_INSTANCE_OFFSET ((uint32_t) 8) /* Offset of each OPAMP instance into register CSR */ -#define OPAMP_OTR_INSTANCE_OFFSET ((uint32_t) 10) /* Offset of each OPAMP instance into register OTR */ - - -/** @defgroup OPAMP_Mode OPAMP Mode - * @{ - */ -#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< OPAMP standalone mode */ -#define OPAMP_FOLLOWER_MODE ((uint32_t)0x00000001) /*!< OPAMP follower mode */ - -#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \ - ((INPUT) == OPAMP_FOLLOWER_MODE)) -/** - * @} - */ - -/** @defgroup OPAMP_NonInvertingInput OPAMP NonInvertingInput - * @{ - */ -#define OPAMP_NONINVERTINGINPUT_VP0 ((uint32_t)0x00000000) /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */ -#define OPAMP_NONINVERTINGINPUT_DAC_CH1 ((uint32_t)0x00000001) /*!< Comparator non-inverting input connected internally to DAC channel 1 */ -#define OPAMP_NONINVERTINGINPUT_DAC_CH2 ((uint32_t)0x00000002) /*!< Comparator non-inverting input connected internally to DAC channel 2. Available on OPAMP2 only. */ - -#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_VP0) || \ - ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) || \ - ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2) ) -/** - * @} - */ - -/** @defgroup OPAMP_InvertingInput OPAMP InvertingInput - * @{ - */ -#define OPAMP_INVERTINGINPUT_VM0 ((uint32_t)0x00000000) /*!< Comparator inverting input connected to dedicated IO pin low-leakage */ -#define OPAMP_INVERTINGINPUT_VM1 ((uint32_t)0x00000001) /*!< Comparator inverting input connected to alternative IO pin available on some device packages */ - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_INVERTINGINPUT_VM1 /*!< Alternate name for comparator inverting input connected to alternative IO pin available on some device packages */ - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_VM0 /* For compatibility with other STM32 devices */ -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_VM1 /* For compatibility with other STM32 devices */ - -#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_VM0) || \ - ((INPUT) == OPAMP_INVERTINGINPUT_VM1) ) -/** - * @} - */ - -/** @defgroup OPAMP_PowerMode OPAMP PowerMode - * @{ - */ -#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000) -#define OPAMP_POWERMODE_LOWPOWER ((uint32_t)0x00000001) - -#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \ - ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) ) -/** - * @} - */ - -/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange - * @{ - */ -#define OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000) /*!< Power supply range low (VDDA lower than 2.4V) */ -#define OPAMP_POWERSUPPLY_HIGH OPAMP_CSR_AOP_RANGE /*!< Power supply range high (VDDA higher than 2.4V) */ - -#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \ - ((RANGE) == OPAMP_POWERSUPPLY_HIGH) ) -/** - * @} - */ - -/** @defgroup OPAMP_UserTrimming OPAMP UserTrimming - * @{ - */ -#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ -#define OPAMP_TRIMMING_USER OPAMP_OTR_OT_USER /*!< User trimming */ - -#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \ - ((TRIMMING) == OPAMP_TRIMMING_USER)) -/** - * @} - */ - -/** @defgroup OPAMP_FactoryTrimming OPAMP FactoryTrimming - * @{ - */ -#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy value if trimming value could not be retrieved */ - -#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000000) /*!< Offset trimming P */ -#define OPAMP_FACTORYTRIMMING_N POSITION_VAL(OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH) /*!< Offset trimming N */ - -#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \ - ((TRIMMING) == OPAMP_FACTORYTRIMMING_P) ) -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup OPAMP_Private_Constants OPAMP Private Constants - * @{ - */ - -/* Offset trimming time: during calibration, minimum time needed between two */ -/* steps to have 1 mV accuracy. */ -/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/ -/* Unit: ms. */ -#define OPAMP_TRIMMING_DELAY ((uint32_t) 1) - -/** - * @} - */ - - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup OPAMP_Private_Macro OPAMP Private Macro - * @{ - */ - -/** @brief Reset OPAMP handle state - * @param __HANDLE__: OPAMP handle. - * @retval None - */ -#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET) - -/** - * @} - */ - - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup OPAMP_Private_Macro OPAMP Private Macro - * @{ - */ - -/** - * @brief Select the OPAMP bit OPAxPD (power-down) corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_OPAXPD(__HANDLE__) \ - (OPAMP_CSR_OPA1PD << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bit S3SELx (switch 3) corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_S3SELX(__HANDLE__) \ - (OPAMP_CSR_S3SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bit S4SELx (switch 4) corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_S4SELX(__HANDLE__) \ - (OPAMP_CSR_S4SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bit S5SELx (switch 5) corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_S5SELX(__HANDLE__) \ - (OPAMP_CSR_S5SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bit S3SELx (switch 6) corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_S6SELX(__HANDLE__) \ - (OPAMP_CSR_S6SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bit OPAxCAL_L (offset calibration for differential - * pair P) corresponding to the selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_OPAXCAL_L(__HANDLE__) \ - (OPAMP_CSR_OPA1CAL_L << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bit OPAxCAL_H (offset calibration for differential - * pair N) corresponding to the selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_OPAXCAL_H(__HANDLE__) \ - (OPAMP_CSR_OPA1CAL_H << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bit OPAxLPM (low power mode) corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_OPAXLPM(__HANDLE__) \ - (OPAMP_CSR_OPA1LPM << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) - -/** - * @brief Select the OPAMP bits of all switches corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_ALL_SWITCHES(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance != OPAMP2) \ - )? \ - ( \ - ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ - | \ - (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) \ - ) \ - : \ - ( \ - ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET)) \ - | \ - (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) \ - | \ - (OPAMP_CSR_S7SEL2) \ - ) \ - ) - -/** - * @brief Select the OPAMP bit ANAWSELx (switch SanA) corresponding to the - * selected OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_ANAWSELX(__HANDLE__) \ - (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) - -/** - * @brief Select the OPAMP bit OPAxCALOUT in function of the selected - * OPAMP instance. - * @param __HANDLE__: OPAMP handle - * @retval None - */ -#define __OPAMP_CSR_OPAXCALOUT(__HANDLE__) \ - (OPAMP_CSR_OPA1CALOUT << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__))) - -/** - * @brief Select the OPAMP trimming bits position value (position of LSB) - * in register OPAMP_OTR or register OPAMP_LPOTR in function of the selected - * OPAMP instance and the transistors differential pair high (PMOS) or - * low (NMOS). - * @param __HANDLE__: OPAMP handle - * @param __TRIM_HIGH_LOW__: transistors differential pair high or low. - * Must be a value of @ref OPAMP_FactoryTrimming. - * @retval None - */ -#define __OPAMP_OFFSET_TRIM_BITSPOSITION(__HANDLE__, __TRIM_HIGH_LOW__) \ - ((__OPAMP_INSTANCE_DECIMAL__((__HANDLE__)) * OPAMP_OTR_INSTANCE_OFFSET) + (__TRIM_HIGH_LOW__)) - -/** - * @brief Shift the OPAMP trimming bits to register OPAMP_OTR or register - * OPAMP_LPOTR in function of the selected OPAMP instance and the transistors - * differential pair high (PMOS) or low (NMOS). - * @param __HANDLE__: OPAMP handle - * @param __TRIM_HIGH_LOW__: transistors differential pair high or low. - * Must be a value of @ref OPAMP_FactoryTrimming. - * @param __TRIMMING_VALUE__: Trimming value - * @retval None - */ -#define __OPAMP_OFFSET_TRIM_SET(__HANDLE__, __TRIM_HIGH_LOW__, __TRIMMING_VALUE__) \ - ((__TRIMMING_VALUE__) << (__OPAMP_OFFSET_TRIM_BITSPOSITION((__HANDLE__), (__TRIM_HIGH_LOW__)))) - -/** - * @brief Check that trimming value is within correct range - * @param TRIMMINGVALUE: OPAMP trimming value - * @retval None - */ -#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1E) - -/** - * @} - */ - - -/* Include OPAMP HAL Extension module */ -#include "stm32l1xx_hal_opamp_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup OPAMP_Exported_Functions - * @{ - */ - -/** @addtogroup OPAMP_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp); -HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp); -void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp); -void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp); -/** - * @} - */ - -/** @addtogroup OPAMP_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions *****************************************************/ -HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp); -HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp); -HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); -OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); -/** - * @} - */ - -/** @addtogroup OPAMP_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); -/** - * @} - */ - -/** @addtogroup OPAMP_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); -/** - * @} - */ - -/** - * @} - */ - - - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_OPAMP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h deleted file mode 100644 index d3a34ca17..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h +++ /dev/null @@ -1,225 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_opamp_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of OPAMP HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_OPAMP_EX_H -#define __STM32L1xx_HAL_OPAMP_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup OPAMPEx - * @{ - */ - - - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants ---------------------------------------------------------*/ -/** @defgroup OPAMPEx_Exported_Constants OPAMPEx Exported Constants - * @{ - */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -#define OPAMP_CSR_OPAXPD_ALL \ - (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD | OPAMP_CSR_OPA3PD) - -#define OPAMP_CSR_OPAXCAL_L_ALL \ - (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA3CAL_L) - -#define OPAMP_CSR_OPAXCAL_H_ALL \ - (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H | OPAMP_CSR_OPA3CAL_H) - -#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS \ - (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \ - OPAMP_CSR_ANAWSEL1 | \ - OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \ - OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2 | \ - OPAMP_CSR_S3SEL3 | OPAMP_CSR_S4SEL3 | OPAMP_CSR_S5SEL3 | OPAMP_CSR_S6SEL3 | \ - OPAMP_CSR_ANAWSEL3 ) -#else -#define OPAMP_CSR_OPAXPD_ALL \ - (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD) - -#define OPAMP_CSR_OPAXCAL_L_ALL \ - (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L) - -#define OPAMP_CSR_OPAXCAL_H_ALL \ - (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H) - -#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS \ - (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \ - OPAMP_CSR_ANAWSEL1 | \ - OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \ - OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2 ) -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup OPAMPEx_Exported_Macro OPAMPEx Exported Macro - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -/** - * @brief Enable internal analog switch SW1 to connect OPAMP3 ouput to ADC - * switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting input - * (OPAMP3 available on STM32L1 devices Cat.4 only). - * @retval None - */ -#define __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() __HAL_RI_SWITCH_COMP1_SW1_CLOSE() - -/** - * @brief Disable internal analog switch SW1 to disconnect OPAMP3 ouput from - * ADC switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting - * input. - * @retval None - */ -#define __HAL_OPAMP_OPAMP3OUT_DISCONNECT_ADC_COMP1() __HAL_RI_SWITCH_COMP1_SW1_OPEN() -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup OPAMPEx_Private_Macro OPAMPEx Private Macro - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -/** - * @brief Get the OPAMP instance in decimal number for further - * processing needs by HAL OPAMP driver functions. - * @param __HANDLE__: OPAMP handle - * @retval "0" for OPAMP1, "1" for OPAMP2, "2" for OPAMP3 - */ -#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == OPAMP1) \ - )? \ - ((uint32_t)0) \ - : \ - ( ( ((__HANDLE__)->Instance == OPAMP2) \ - )? \ - ((uint32_t)1) \ - : \ - ((uint32_t)2) \ - ) \ - ) -#else -/** - * @brief Get the OPAMP instance in decimal number for further - * processing needs by HAL OPAMP driver functions. - * @param __HANDLE__: OPAMP handle - * @retval "0" for OPAMP1, "1" for OPAMP2 - */ -#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == OPAMP1) \ - )? \ - ((uint32_t)0) \ - : \ - ((uint32_t)1) \ - ) -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup OPAMPEx_Exported_Functions - * @{ - */ - -/* I/O operation functions *****************************************************/ -/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended IO operation functions - * @{ - */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3); -#else -HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -/** - * @} - */ -/* Peripheral Control functions ************************************************/ -/** @addtogroup OPAMPEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_OPAMP_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h deleted file mode 100644 index 5d373423f..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h +++ /dev/null @@ -1,833 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pcd.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_PCD_H -#define __STM32L1xx_HAL_PCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup PCD_Exported_Types PCD Exported Types - * @{ - */ - - /** - * @brief PCD State structures definition - */ -typedef enum -{ - PCD_READY = 0x00, - PCD_ERROR = 0x01, - PCD_BUSY = 0x02, - PCD_TIMEOUT = 0x03 -} PCD_StateTypeDef; - -typedef enum -{ - /* double buffered endpoint direction */ - PCD_EP_DBUF_OUT, - PCD_EP_DBUF_IN, - PCD_EP_DBUF_ERR, -}PCD_EP_DBUF_DIR; - -/* endpoint buffer number */ -typedef enum -{ - PCD_EP_NOBUF, - PCD_EP_BUF0, - PCD_EP_BUF1 -}PCD_EP_BUF_NUM; - -/** - * @brief PCD Initialization Structure definition - */ -typedef struct -{ - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - -}PCD_InitTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type */ - - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - - uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - - uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - -}PCD_EPTypeDef; - -typedef USB_TypeDef PCD_TypeDef; - -/** - * @brief PCD Handle Structure definition - */ -typedef struct -{ - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - void *pData; /*!< Pointer to upper stack Handler */ - -} PCD_HandleTypeDef; - -/** - * @} - */ - -#include "stm32l1xx_hal_pcd_ex.h" -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -/** @defgroup USB_Exti_Line_Wakeup USB_Exti_Line_Wakeup - * @{ - */ - -#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ -/** - * @} - */ - - -/** @defgroup USB_Core_Speed USB Core Speed - * @{ - */ -#define PCD_SPEED_HIGH 0 /* Not Supported */ -#define PCD_SPEED_FULL 2 -/** - * @} - */ - - /** @defgroup USB_Core_PHY USB Core PHY - * @{ - */ -#define PCD_PHY_EMBEDDED 2 -/** - * @} - */ - -/** @defgroup USB_EP0_MPS USB EP0 MPS - * @{ - */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 - -#define PCD_EP0MPS_64 DEP0CTL_MPS_64 -#define PCD_EP0MPS_32 DEP0CTL_MPS_32 -#define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 -/** - * @} - */ - -/** @defgroup USB_EP_Type USB EP Type - * @{ - */ -#define PCD_EP_TYPE_CTRL 0 -#define PCD_EP_TYPE_ISOC 1 -#define PCD_EP_TYPE_BULK 2 -#define PCD_EP_TYPE_INTR 3 -/** - * @} - */ - -/** @defgroup USB_ENDP_Type USB_ENDP_Type - * @{ - */ - -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) - -/* Endpoint Kind */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 - -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE - -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) - -#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP -#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP) -#define __HAL_USB_EXTI_GET_FLAG() EXTI->PR & (USB_EXTI_LINE_WAKEUP) -#define __HAL_USB_EXTI_CLEAR_FLAG() EXTI->PR = USB_EXTI_LINE_WAKEUP - -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\ - EXTI->RTSR |= USB_EXTI_LINE_WAKEUP - - -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (USB_EXTI_LINE_WAKEUP);\ - EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP) - - -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\ - EXTI->RTSR |= USB_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= USB_EXTI_LINE_WAKEUP - -/** - * @} - */ - -/* Internal macros -----------------------------------------------------------*/ - -/** @defgroup PCD_Private_Macros PCD Private Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) - -/* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) - - - -/** - * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wType: Endpoint Type. - * @retval None - */ -#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) - -/** - * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval Endpoint Type - */ -#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) - - -/** - * @brief free buffer used from the application realizing it to the line - toggles bit SW_BUF in the double buffered endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: Direction - * @retval None - */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ -{\ - if ((bDir) == PCD_EP_DBUF_OUT)\ - { /* OUT double buffered endpoint */\ - PCD_TX_DTOG((USBx), (bEpNum));\ - }\ - else if ((bDir) == PCD_EP_DBUF_IN)\ - { /* IN double buffered endpoint */\ - PCD_RX_DTOG((USBx), (bEpNum));\ - }\ -} - -/** - * @brief gets direction of the double buffered endpoint - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval EP_DBUF_OUT, EP_DBUF_IN, - * EP_DBUF_ERR if the endpoint counter not yet programmed. - */ -#define PCD_GET_DB_DIR(USBx, bEpNum)\ -{\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ - return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ - return(PCD_EP_DBUF_IN);\ - else\ - return(PCD_EP_DBUF_ERR);\ -} - -/** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state - * @retval None - */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ - } /* PCD_SET_EP_TX_STATUS */ - -/** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state - * @retval None - */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ - register uint16_t _wRegVal; \ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ - } /* PCD_SET_EP_RX_STATUS */ - -/** - * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wStaterx: new state. - * @param wStatetx: new state. - * @retval None - */ -#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ - register uint32_t _wRegVal; \ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ - } /* PCD_SET_EP_TXRX_STATUS */ - -/** - * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] - * /STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval status - */ -#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) - -#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) - -/** - * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) - -#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) - -/** - * @brief checks stall condition in an endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval TRUE = endpoint in stall condition. - */ -#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ - == USB_EP_TX_STALL) -#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ - == USB_EP_RX_STALL) - -/** - * @brief set & clear EP_KIND bit. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) - -/** - * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) - -/** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) -#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) - -/** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ - { \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ - { \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } - -/** - * @brief Sets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bAddr: Address. - * @retval None - */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) - -#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) - -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400))) - -#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } - -/** - * @brief sets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wAddr: address to be set (must be word aligned). - * @retval None - */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) - -/** - * @brief Gets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval address of the buffer. - */ -#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg: Register - * @param wCount: Counter. - * @param wNBlocks: no. of Blocks. - * @retval None - */ -#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5;\ - if(((wCount) & 0x1f) == 0)\ - { \ - (wNBlocks)--;\ - } \ - *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ - }/* PCD_CALC_BLK32 */ - -#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1;\ - if(((wCount) & 0x1) != 0)\ - { \ - (wNBlocks)++;\ - } \ - *pdwReg = (uint16_t)((wNBlocks) << 10);\ - }/* PCD_CALC_BLK2 */ - -#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ - uint16_t wNBlocks;\ - if((wCount) > 62) \ - { \ - PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ - } \ - else \ - { \ - PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \ - } \ - }/* PCD_SET_EP_CNT_RX_REG */ - -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } -/** - * @brief sets counter for the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wCount: Counter value. - * @retval None - */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) - - -/** - * @brief gets counter of the tx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval Counter value - */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) - -/** - * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @retval Counter value - */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} - -/** - * @brief Sets addresses in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @param wBuf1Addr = buffer 1 address. - * @retval None - */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ - PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ - PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ - } /* PCD_SET_EP_DBUF_ADDR */ - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value - * @retval None - */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ - else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } /* SetEPDblBuf0Count*/ - -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - {/* OUT endpoint */ \ - PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \ - } \ - else if((bDir) == PCD_EP_DBUF_IN)\ - {/* IN endpoint */ \ - *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } \ - } /* SetEPDblBuf1Count */ - -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ - PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } /* PCD_SET_EP_DBUF_CNT */ - -/** - * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PCD_Exported_Functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ - - -/** @addtogroup PCD_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); - -/** - * @} - */ - -/* I/O operation functions *****************************************************/ -/* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); - -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ -/** @addtogroup PCD_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - - -/* Peripheral State functions **************************************************/ -/** @addtogroup PCD_Exported_Functions_Group4 - * @{ - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h deleted file mode 100644 index 092fca04a..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pcd.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_PCD_EX_H -#define __STM32L1xx_HAL_PCD_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCDEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Internal macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions - * @{ - */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress); -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h deleted file mode 100644 index 5732776b8..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h +++ /dev/null @@ -1,431 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_PWR_H -#define __STM32L1xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ -}PWR_PVDTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_register_alias_address PWR Register alias address - * @{ - */ -/* ------------- PWR registers bit address in the alias region ---------------*/ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) -#define PWR_CR_OFFSET 0x00 -#define PWR_CSR_OFFSET 0x04 -#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) -#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) -/** - * @} - */ - -/** @defgroup PWR_CR_register_alias PWR CR Register alias address - * @{ - */ -/* --- CR Register ---*/ -/* Alias word address of LPSDSR bit */ -#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) -#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) - -/* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) -#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) - -/* Alias word address of LPRUN bit */ -#define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) -#define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) - -/* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) -#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) - -/* Alias word address of FWU bit */ -#define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) -#define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) - -/* Alias word address of ULP bit */ -#define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) -#define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) -/** - * @} - */ - -/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address - * @{ - */ - -/* --- CSR Register ---*/ -/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ -#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) -/** - * @} - */ - -/** @defgroup PWR_PVD_detection_level PWR PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage - (Compare internally to VREFINT) */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ - -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) -/** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) -#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) -/** - * @} - */ - -/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale - * @{ - */ - -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 -#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS - -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) -/** - * @} - */ - -/** @defgroup PWR_Flag PWR Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#define PWR_FLAG_VOS PWR_CSR_VOSF -#define PWR_FLAG_REGLP PWR_CSR_REGLPF - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro PWR Exported Macro - * @{ - */ - -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, - * System frequency up to 32 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, - * System frequency up to 16 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, - * System frequency up to 4.2 MHz - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) - -/** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm B), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. - * This bit indicates the state of the internal voltage reference, VREFINT. - * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for - * the internal regulator to be ready after the voltage range is changed. - * The VOSF bit indicates that the regulator has reached the voltage level - * defined with bits VOS of PWR_CR register. - * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run - * mode, this bit stays at 1 until the regulator is ready in main mode. - * A polling on this bit is recommended to wait for the regulator main mode. - * This bit is reset by hardware when the regulator is ready. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2) - -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ - -/** - * @brief Enable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief PVD EXTI line configuration: clear falling edge trigger and set rising edge. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \ - EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD) - -/** - * @brief PVD EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) - -/** - * @brief PVD EXTI line configuration: set rising edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) - -/** - * @brief Check whether the specified PVD EXTI interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD EXTI flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) -/** - * @} - */ - -/* Include PWR HAL Extension module */ -#include "stm32l1xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *******************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); - -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - -/* WakeUp pins configuration functions ****************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes configuration functions ************************************/ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h deleted file mode 100644 index cfd35938c..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of PWR HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_PWR_EX_H -#define __STM32L1xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ - - -/** @defgroup PWR_WakeUp_Pins PWREx Wakeup Pins - * @{ - */ - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) - -#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 -#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 -#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3)) -#else -#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 -#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2)) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 - * @{ - */ - -/* Peripheral Control methods ************************************************/ -void HAL_PWREx_EnableFastWakeUp(void); -void HAL_PWREx_DisableFastWakeUp(void); -void HAL_PWREx_EnableUltraLowPower(void); -void HAL_PWREx_DisableUltraLowPower(void); -void HAL_PWREx_EnableLowPowerRunMode(void); -void HAL_PWREx_DisableLowPowerRunMode(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h deleted file mode 100644 index b093b03fd..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h +++ /dev/null @@ -1,1227 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RCC_H -#define __STM32L1xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ - - uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Division_Factor*/ -} RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - uint32_t MSIState; /*!< The new state of the MSI. - This parameter can be a value of @ref RCC_MSI_Config */ - - uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t MSIClockRange; /*!< The MSI frequency range. - This parameter can be a value of @ref RCC_MSI_Clock_Range */ - - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ - -} RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - -} RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ -#define DBP_TIMEOUT_VALUE ((uint32_t)100) -#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT - -/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion - * @brief RCC registers bit address in the alias region - * @{ - */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00 -#define RCC_CFGR_OFFSET 0x08 -#define RCC_CIR_OFFSET 0x0C -#define RCC_CSR_OFFSET 0x34 -#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) -#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) -#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) -#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) - -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION) -#define CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4))) -/* Alias word address of MSION bit */ -#define MSION_BITNUMBER POSITION_VAL(RCC_CR_MSION) -#define CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4))) -/* Alias word address of HSEON bit */ -#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON) -#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4))) -/* Alias word address of CSSON bit */ -#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON) -#define CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4))) -/* Alias word address of PLLON bit */ -#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON) -#define CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4))) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION) -#define CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4))) - -/* Alias word address of LSEON bit */ -#define LSEON_BITNUMBER POSITION_VAL(RCC_CSR_LSEON) -#define CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4))) - -/* Alias word address of LSEON bit */ -#define LSEBYP_BITNUMBER POSITION_VAL(RCC_CSR_LSEBYP) -#define CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4))) - -/* Alias word address of RTCEN bit */ -#define RTCEN_BITNUMBER POSITION_VAL(RCC_CSR_RTCEN) -#define CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4))) - -/* Alias word address of RTCRST bit */ -#define RTCRST_BITNUMBER POSITION_VAL(RCC_CSR_RTCRST) -#define CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4))) - -/* CR register byte 2 (Bits[23:16]) base address */ -#define CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) - -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source - * @{ - */ - -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI -#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE - -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSE)) -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type RCC Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) -#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) - -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) -/** - * @} - */ - -/** @defgroup RCC_HSE_Config RCC HSE Config - * @{ - */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00000001) -#define RCC_HSE_BYPASS ((uint32_t)0x00000005) - -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Config RCC LSE Config - * @{ - */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) -#define RCC_LSE_ON ((uint32_t)0x00000001) -#define RCC_LSE_BYPASS ((uint32_t)0x00000005) - -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) -/** - * @} - */ - -/** @defgroup RCC_HSI_Config RCC HSI Config - * @{ - */ -#define RCC_HSI_OFF ((uint32_t)0x00000000) -#define RCC_HSI_ON ((uint32_t)0x00000001) - -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) - -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ - -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) -/** - * @} - */ - -/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range - * @{ - */ - -#define RCC_MSIRANGE_0 ((uint32_t)RCC_ICSCR_MSIRANGE_0) /*!< MSI = 65.536 KHz */ -#define RCC_MSIRANGE_1 ((uint32_t)RCC_ICSCR_MSIRANGE_1) /*!< MSI = 131.072 KHz */ -#define RCC_MSIRANGE_2 ((uint32_t)RCC_ICSCR_MSIRANGE_2) /*!< MSI = 262.144 KHz */ -#define RCC_MSIRANGE_3 ((uint32_t)RCC_ICSCR_MSIRANGE_3) /*!< MSI = 524.288 KHz */ -#define RCC_MSIRANGE_4 ((uint32_t)RCC_ICSCR_MSIRANGE_4) /*!< MSI = 1.048 MHz */ -#define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /*!< MSI = 2.097 MHz */ -#define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /*!< MSI = 4.194 MHz */ - -#define IS_RCC_MSIRANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ - ((__RANGE__) == RCC_MSIRANGE_1) || \ - ((__RANGE__) == RCC_MSIRANGE_2) || \ - ((__RANGE__) == RCC_MSIRANGE_3) || \ - ((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6)) -/** - * @} - */ - -/** @defgroup RCC_LSI_Config RCC LSI Config - * @{ - */ -#define RCC_LSI_OFF ((uint32_t)0x00000000) -#define RCC_LSI_ON ((uint32_t)0x00000001) - -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) -/** - * @} - */ - - -/** @defgroup RCC_MSI_Config RCC MSI Config - * @{ - */ -#define RCC_MSI_OFF ((uint32_t)0x00000000) -#define RCC_MSI_ON ((uint32_t)0x00000001) - -#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) - -#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */ - -/** - * @} - */ - -/** @defgroup RCC_PLL_Config RCC PLL Config - * @{ - */ -#define RCC_PLL_NONE ((uint32_t)0x00000000) -#define RCC_PLL_OFF ((uint32_t)0x00000001) -#define RCC_PLL_ON ((uint32_t)0x00000002) - -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor - * @{ - */ - -#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 -#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 -#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 - -#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ - ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) - -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor - * @{ - */ - -#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 -#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 -#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 -#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 -#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 -#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 -#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 -#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 -#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 - -#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ - ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ - ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ - ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ - ((__MUL__) == RCC_PLL_MUL48)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type RCC System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) - -#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source RCC System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_MSI ((uint32_t)RCC_CFGR_SW_MSI) -#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) -#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) -#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) - -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1) -#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2) -#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4) -#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8) -#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16) -#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64) -#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128) -#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256) -#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512) - -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 ((uint32_t)RCC_CFGR_PPRE1_DIV1) -#define RCC_HCLK_DIV2 ((uint32_t)RCC_CFGR_PPRE1_DIV2) -#define RCC_HCLK_DIV4 ((uint32_t)RCC_CFGR_PPRE1_DIV4) -#define RCC_HCLK_DIV8 ((uint32_t)RCC_CFGR_PPRE1_DIV8) -#define RCC_HCLK_DIV16 ((uint32_t)RCC_CFGR_PPRE1_DIV16) - -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) -/** - * @} - */ - -/** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_CSR_RTCSEL_LSE) -#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_CSR_RTCSEL_LSI) -#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)RCC_CSR_RTCSEL_HSE) -#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)(RCC_CR_RTCPRE_0 | RCC_CSR_RTCSEL_HSE)) -#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)(RCC_CR_RTCPRE_1 | RCC_CSR_RTCSEL_HSE)) -#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)(RCC_CR_RTCPRE | RCC_CSR_RTCSEL_HSE)) -/** - * @} - */ - -/** @defgroup RCC_MCO_Index RCC MCO Index - * @{ - */ -#define RCC_MCO1 ((uint32_t)0x00000000) -#define RCC_MCO RCC_MCO1 - -#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO)) -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1) -#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2) -#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4) -#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8) -#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16) - -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ - ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ - ((__DIV__) == RCC_MCODIV_16)) -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) -#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) -#define RCC_MCO1SOURCE_MSI ((uint32_t)RCC_CFGR_MCO_MSI) -#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) -#define RCC_MCO1SOURCE_LSE ((uint32_t)RCC_CFGR_MCO_LSE) -#define RCC_MCO1SOURCE_LSI ((uint32_t)RCC_CFGR_MCO_LSI) -#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) -#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL) - -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt RCC Interrupt - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) -#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) -#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) -#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) -#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) -#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) -#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSS) -#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) -/** - * @} - */ - -/** @defgroup RCC_Flag RCC Flag - * Elements values convention: 0XXYYYYYb - * - YYYYY : Flag position in the register - * - XX : Register index - * - 01: CR register - * - 11: CSR register - * @{ - */ -#define CR_REG_INDEX ((uint8_t)1) -#define CSR_REG_INDEX ((uint8_t)3) - -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) -#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) -#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) -#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) -#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_RMVF))) -#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) - -#define RCC_FLAG_MASK ((uint8_t)0x1F) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) -#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) -#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) -#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) -#define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN)) - -#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) -#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) -#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) - -#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) -#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) -#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) -#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) -#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) - -#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) -#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) -#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) - -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) -#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) -#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN)) -#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) -#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) -#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) -#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) -#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) -#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) -#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) -#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) -#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) -#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) -#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) -#define __COMP_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_COMPEN)) - -#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) -#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN)) - -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) -#define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN)) -#define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN)) -#define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN)) -#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) -#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) -#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) - -#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) -#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) -#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) - -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release - * @brief Force or release AHB peripheral reset. - * @{ - */ -#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) -#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) -#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) -#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) -#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) -#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) - -#define __CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) -#define __FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST)) -#define __DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) - -#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) -#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) -#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) -#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) -#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) -#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) - -#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST)) -#define __FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST)) -#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST)) - -/** @brief Force or release APB1 peripheral reset. - */ -#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) -#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) -#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST)) - -#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) -#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) -#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST)) - -/** @brief Force or release APB2 peripheral reset. - */ -#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) -#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -#define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) -#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) -#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) - -#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) -#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) -#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) -#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) -#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) - -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN)) -#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN)) -#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN)) -#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN)) -#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN)) - -#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN)) -#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN)) -#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN)) - -#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN)) -#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN)) -#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN)) -#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN)) -#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN)) - -#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN)) -#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN)) -#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN)) - -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) -#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) -#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) -#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) -#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) -#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN)) -#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) -#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN)) - -#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) -#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) -#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) -#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) -#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) -#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN)) -#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) -#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN)) - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) -#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) -#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) -#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) -#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) -#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) -#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) - -#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) -#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) -#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) -#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) -#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) -#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) - -/** - * @} - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE) -#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE) - -/** @brief Macros to enable or disable the External High Speed oscillator (HSE). - * @param __HSE_STATE__: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock - */ -#define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__HSE_STATE__)) - -/** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). - * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note MSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the MSI. - * @note After enabling the MSI, the application software should wait on MSIRDY - * flag to be set indicating that MSI clock is stable and can be used as - * system clock source. - * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator - * clock cycles. - */ -#define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) CR_MSION_BB = ENABLE) -#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) CR_MSION_BB = DISABLE) - -/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ - (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM))) - -/** @brief macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal MSI RC. - * @param _MSICALIBRATIONVALUE_: specifies the calibration trimming value. - * (default is RCC_MSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ - (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM))) - -/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. - * @note After restart from Reset or wakeup from STANDBY, the MSI clock is - * around 2.097 MHz. The MSI clock does not change after wake-up from - * STOP mode. - * @note The MSI clock range can be modified on the fly. - * @param _MSIRANGEVALUE_: specifies the MSI Clock range. - * This parameter must be one of the following values: - * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz - * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz - * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz - * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz - * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz - * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) - * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz - */ -#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) - - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE) -#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE) - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE). - */ -#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \ - do{ \ - if ((__LSE_STATE__) == RCC_LSE_OFF) \ - { \ - *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \ - *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \ - } \ - else if ((__LSE_STATE__) == RCC_LSE_ON) \ - { \ - *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \ - *(__IO uint32_t *) CSR_LSEON_BB = ENABLE; \ - } \ - else \ - { \ - *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \ - *(__IO uint32_t *) CSR_LSEBYP_BB = ENABLE; \ - } \ - }while(0) - -/** @brief Macros to enable or disable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = ENABLE) -#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) CSR_RTCEN_BB = DISABLE) - -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) CSR_RTCRST_BB = ENABLE) -#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) CSR_RTCRST_BB = DISABLE) - - -/** @brief Macro to configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). - * - * @param __RTC_CLKSOURCE__: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \ - if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \ - { \ - MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \ - } \ - } while (0) - -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \ - __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ - RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ - } while (0) - -/** @brief macros to get the RTC clock source. - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) - -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE) -#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE) - -/** @brief macros to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock - * This parameter can be one of the following values: - * @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 - * @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4 - * @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6 - * @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8 - * @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 - * @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 - * @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24 - * @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32 - * @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48 - * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in - * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is - * in Range 3. - * - * @param __PLLDIV__: specifies the division factor for PLL VCO input clock - * This parameter can be one of the following values: - * @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2 - * @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3 - * @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4 - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * @arg RCC_CFGR_SWS_MSI: MSI used as system clock - * @arg RCC_CFGR_SWS_HSI: HSI used as system clock - * @arg RCC_CFGR_SWS_HSE: HSE used as system clock - * @arg RCC_CFGR_SWS_PLL: PLL used as system clock - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) - -/** @brief macros to manage the specified RCC Flags and interrupts. - */ - -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts.). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) - -/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_MSIRDY: MSI ready interrupt. - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - * @arg RCC_IT_CSS: Clock Security System interrupt - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_MSIRDY: MSI ready interrupt. - * @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device) - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. - * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready. - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. - * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. - * @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*) - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. - * @arg RCC_FLAG_PINRST: Pin reset. - * @arg RCC_FLAG_PORRST: POR/PDR reset. - * @arg RCC_FLAG_SFTRST: Software reset. - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. - * @arg RCC_FLAG_LPWRRST: Low Power reset. - * @note (*) This bit is available in high and medium+ density devices only. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) - - -/** @brief Get oscillator clock selected as PLL input clock - * @retval The clock source used for PLL entry. The returned value can be one - * of the following: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC)) - -/** - * @} - */ - -/* Include RCC HAL Extension module */ -#include "stm32l1xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Private_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); - -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CCSCallback(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h deleted file mode 100644 index 94d9d7c06..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h +++ /dev/null @@ -1,573 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RCC_EX_H -#define __STM32L1xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< specifies the RTC clock source. - This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - - uint32_t LCDClockSelection; /*!< specifies the LCD clock source. - This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ -} RCC_PeriphCLKInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001) - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - -#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - -#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) - -#else /* Not LCD LINE */ - -#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -/* Alias word address of LSECSSON bit */ -#define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON) -#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4))) - -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined (STM32L151xB) || defined (STM32L152xB) || \ - defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) -#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) -#define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN)) - -#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) -#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) -#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -#define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_AESEN)) -#define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define __FSMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FSMCEN)) -#define __FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - -#define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN)) -#define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - -/** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN)) -#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) -#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) -#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) - -#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - -#define __OPAMP_CLK_ENABLE() __COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ -#define __OPAMP_CLK_DISABLE() __COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -/** @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN)) -#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - - -/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset - * @brief Forces or releases AHB peripheral reset. - * @{ - */ -#if defined (STM32L151xB) || defined (STM32L152xB) || \ - defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) -#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) -#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) - -#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) -#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) -#define __DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -#define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) -#define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define __FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) -#define __FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - -#define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) -#define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - -/** @brief Forces or releases APB1 peripheral reset. - */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) - -#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - -#define __OPAMP_FORCE_RESET() __COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ -#define __OPAMP_RELEASE_RESET() __COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -/** @brief Forces or releases APB2 peripheral reset. - */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#if defined (STM32L151xB) || defined (STM32L152xB) || \ - defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) -#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) -#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) - -#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) -#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) -#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) -#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) -#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - -#define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) -#define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - -/** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) -#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) - -#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - - -/** @brief Macro to configures LCD clock (LCDCLK). - * @note LCD and RTC use the same configuration - * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the - * LCD clock source. - * - * @param __LCD_CLKSOURCE__: specifies the LCD clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock - */ -#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) - -/** @brief macros to get the LCD clock source. - */ -#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -void HAL_RCCEx_EnableLSECSS(void); -void HAL_RCCEx_DisableLSECSS(void); - -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h deleted file mode 100644 index 2d0d7a23f..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of RTC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RTC_H -#define __STM32L1xx_HAL_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTC_Exported_Types RTC Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ - -}HAL_RTCStateTypeDef; - -/** - * @brief RTC Configuration Structure definition - */ -typedef struct -{ - uint32_t HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ - - uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ - - uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. - This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ - - uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. - This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ - - uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. - This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -}RTC_InitTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t Date; /*!< Specifies the RTC Date. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - - uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ - -}RTC_DateTypeDef; - -/** - * @brief Time Handle Structure definition - */ -typedef struct -{ - RTC_TypeDef *Instance; /*!< Register base address */ - - RTC_InitTypeDef Init; /*!< RTC required parameters */ - - HAL_LockTypeDef Lock; /*!< RTC locking object */ - - __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ - -}RTC_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Constants RTC Exported Constants - * @{ - */ - -/** @defgroup RTC_Timeout_Value Default Timeout Value - * @{ - */ -#define RTC_TIMEOUT_VALUE 1000 -/** - * @} - */ - -/** @defgroup RTC_Hour_Formats Hour Formats - * @{ - */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) - -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ - ((FORMAT) == RTC_HOURFORMAT_24)) -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions Outpout Polarity - * @{ - */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) - -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((POL) == RTC_OUTPUT_POLARITY_LOW)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT Alarm Output Type - * @{ - */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) -#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000) - -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ - ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) - -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions Time Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions AM PM Definitions - * @{ - */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) - -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions DayLightSaving - * @{ - */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) - -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) -/** - * @} - */ - -/** @defgroup RTC_StoreOperation_Definitions StoreOperation - * @{ - */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) - -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ - ((OPERATION) == RTC_STOREOPERATION_SET)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format - * @{ - */ -#define FORMAT_BIN ((uint32_t)0x000000000) -#define FORMAT_BCD ((uint32_t)0x000000001) - -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD)) -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions Year Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions Month Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) - -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions - * @{ - */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) - -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Definitions Alarm Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions AlarmDateWeekDay Definitions - * @{ - */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ - ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions Alarm Mask Definitions - * @{ - */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) - -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions Alarms Definitions - * @{ - */ -#define RTC_ALARM_A RTC_CR_ALRAE -#define RTC_ALARM_B RTC_CR_ALRBE - -#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTC_Exported_macros RTC Exported Macros - * @{ - */ - -/** @brief Reset RTC handle state - * @param __HANDLE__: RTC handle. - * @retval None - */ -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) - -/** - * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) - -/** - * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) - -/** - * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) - -/** - * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) - -/** - * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) - -/** - * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) - -/** - * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF - * @retval None - */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @retval None - */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - - -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ - -/** - * @brief Enable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None - */ -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) - -/* alias define maintained for legacy */ -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -/** - * @brief Disable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None - */ -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) - -/* alias define maintained for legacy */ -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None - */ -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) - -/** - * @brief Clear the RTC Exti flags. - * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None - */ -#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) - -/* alias define maintained for legacy */ -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG - -/** - * @} - */ - -/* Include RTC HAL Extension module */ -#include "stm32l1xx_hal_rtc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_Exported_Functions - * @{ - */ - - -/* Initialization and de-initialization functions ****************************/ -/** @addtogroup RTC_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* RTC Time and Date functions ************************************************/ -/** @addtogroup RTC_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -/** - * @} - */ - -/* RTC Alarm functions ********************************************************/ -/** @addtogroup RTC_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* Peripheral Control functions ***********************************************/ -/** @addtogroup RTC_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); -/** - * @} - */ - -/* Peripheral State functions *************************************************/ -/** @addtogroup RTC_Exported_Functions_Group5 - * @{ - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** - * @} - */ -/* Private functions **********************************************************/ -/** @addtogroup RTC_Internal_Functions - * @{ - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); -uint8_t RTC_ByteToBcd2(uint8_t Value); -uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h deleted file mode 100644 index 1b93cc6ec..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h +++ /dev/null @@ -1,973 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of RTC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RTC_EX_H -#define __STM32L1xx_HAL_RTC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Types RTCEx Exported Types - * @{ - */ - -/** - * @brief RTC Tamper structure definition - */ -typedef struct -{ - uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ - - uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t Filter; /*!< Specifies the RTC Filter Tamper. - This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ - - uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. - This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ - - uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . - This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ - - uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */ - - uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. - This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -}RTC_TamperTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ - - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ - - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ - - uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. - This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint32_t Alarm; /*!< Specifies the alarm . - This parameter can be a value of @ref RTC_Alarms_Definitions */ -}RTC_AlarmTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants - * @{ - */ - -/** @defgroup RTC_Masks_Definitions Masks Definitions - * @{ - */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \ - RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \ - RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \ - RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ - RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \ - RTC_FLAG_RECALPF)) -#else -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \ - RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \ - RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \ - RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ - RTC_FLAG_TAMP1F | \ - RTC_FLAG_RECALPF)) - -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup RTC_Synchronous_Predivider Synchronous Predivider - * @{ - */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) -#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x1FFF) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) -#define RTC_IT_TAMP3 ((uint32_t)0x00080000) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions Flags Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) -#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_FLAG_SHPF ((uint32_t)0x00000008) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -/** - * @} - */ - -/** @defgroup RTCEx_Output_selection_Definitions Output selection Definitions - * @{ - */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) -#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) -#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) -/** - * @} - */ - -/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions - * @{ - */ -#if RTC_BKP_NUMBER > 0 -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#endif /* RTC_BKP_NUMBER > 0 */ - -#if RTC_BKP_NUMBER > 5 -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#endif /* RTC_BKP_NUMBER > 5 */ - -#if RTC_BKP_NUMBER > 20 -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) -#endif /* RTC_BKP_NUMBER > 20 */ - -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) -/** - * @} - */ - -/** @defgroup RTCEx_Time_Stamp_Edges_Definitions Time Stamp Edges Definitions - * @{ - */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) - -#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ - ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions - * @{ - */ -#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E -#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_TAMPER(TAMPER) (((~(RTC_TAMPER_1|RTC_TAMPER_2|RTC_TAMPER_3) & (TAMPER)) == (uint32_t)RESET) && ((TAMPER) != (uint32_t)RESET)) -#else -#define IS_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions - * @{ - */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE -#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) -#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) -#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** @defgroup RTCEx_Tamper_Filter_Definitions Tamper Filter Definitions - * @{ - */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active level. */ - -#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions Tamper Sampling Frequencies - * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ - -#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions Tamper Pin Precharge Duration - * @{ - */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions TimeStampOnTamperDetection Definitions - * @{ - */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ - -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pull_Up_Definitions Tamper Pull-Up Definitions - * @{ - */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ - -#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) -/** - * @} - */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** @defgroup RTCEx_Wakeup_Timer_Definitions Wakeup Timer Definitions - * @{ - */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) - -#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) - -#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTCEx_Digital_Calibration_Definitions Digital Calibration Definitions - * @{ - */ -#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000) -#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080) - -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \ - ((SIGN) == RTC_CALIBSIGN_NEGATIVE)) - -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_Calib_Period_Definitions Smooth Calib Period Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ - -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_Calib_Plus_Pulses_Definitions Smooth Calib Plus Pulses Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ - -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ - ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_Calib_Minus_Pulses_Definitions Smooth Calib Minus Pulses Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) -/** - * @} - */ - -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions Add 1 Second Parameter Definitions - * @{ - */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) - -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) -/** - * @} - */ - -/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value Substract Fraction Of Second Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) -/** - * @} - */ - -/** @defgroup RTCEx_Calib_Output_Selection_Definitions Calib Output Selection Definitions - * @{ - */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) - -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ - ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) -/** - * @} - */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** @defgroup RTC_Alarm_Sub_Seconds_Value Alarm Sub Seconds Value - * @{ - */ -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions Alarm Sub Seconds Masks Definitions - * @{ - */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) -/** - * @} - */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros - * @{ - */ - -/** - * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) - -/** - * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) - -/** - * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) - -/** - * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) - -/** - * @brief Enable the Coarse calibration process. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE)) - -/** - * @brief Disable the Coarse calibration process. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE)) - -/** - * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) - -/** - * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) - -/** - * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) - -/** - * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) - -/** - * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TAMP1 - * @arg RTC_IT_TAMP2 - * @arg RTC_IT_TAMP3 - * @retval None - */ -#else -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TAMP1 - * @retval None - */ -#endif -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) - -/** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) - -/** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_SHPF - * @retval None - */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTCEx_Exported_Functions - * @{ - */ - -/* RTC TimeStamp and Tamper functions *****************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group4 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge); -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); - -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); - -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -/** - * @} - */ - -/* RTC Wake-up functions ******************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group5 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/* Extension Control functions ************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group7 - * @{ - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); - -HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value); -HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); -#else -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* Extension RTC features functions *******************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group8 - * @{ - */ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h deleted file mode 100644 index b3aec3dfe..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h +++ /dev/null @@ -1,705 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_sd.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of SD HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_SD_H -#define __STM32L1xx_HAL_SD_H - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_ll_sdmmc.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup SD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SD_Exported_Types SD Exported Types - * @{ - */ - -#define SD_InitTypeDef SDIO_InitTypeDef -#define SD_TypeDef SDIO_TypeDef - -/** - * @brief SDIO Handle Structure definition - */ -typedef struct -{ - SD_TypeDef *Instance; /*!< SDIO register base address */ - - SD_InitTypeDef Init; /*!< SD required parameters */ - - HAL_LockTypeDef Lock; /*!< SD locking object */ - - uint32_t CardType; /*!< SD card type */ - - uint32_t RCA; /*!< SD relative card address */ - - uint32_t CSD[4]; /*!< SD card specific data table */ - - uint32_t CID[4]; /*!< SD card identification number table */ - - __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */ - - __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */ - - __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */ - - __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */ - - DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ - - DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ - -}SD_HandleTypeDef; - -/** - * @brief Card Specific Data: CSD Register - */ -typedef struct -{ - __IO uint8_t CSDStruct; /*!< CSD structure */ - __IO uint8_t SysSpecVersion; /*!< System specification version */ - __IO uint8_t Reserved1; /*!< Reserved */ - __IO uint8_t TAAC; /*!< Data read access time 1 */ - __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ - __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - __IO uint16_t CardComdClasses; /*!< Card command classes */ - __IO uint8_t RdBlockLen; /*!< Max. read data block length */ - __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ - __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ - __IO uint8_t DSRImpl; /*!< DSR implemented */ - __IO uint8_t Reserved2; /*!< Reserved */ - __IO uint32_t DeviceSize; /*!< Device Size */ - __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ - __IO uint8_t EraseGrSize; /*!< Erase group size */ - __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ - __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ - __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - __IO uint8_t WrSpeedFact; /*!< Write speed factor */ - __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - __IO uint8_t Reserved3; /*!< Reserved */ - __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ - __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ - __IO uint8_t PermWrProtect; /*!< Permanent write protection */ - __IO uint8_t TempWrProtect; /*!< Temporary write protection */ - __IO uint8_t FileFormat; /*!< File format */ - __IO uint8_t ECC; /*!< ECC code */ - __IO uint8_t CSD_CRC; /*!< CSD CRC */ - __IO uint8_t Reserved4; /*!< Always 1 */ - -}HAL_SD_CSDTypedef; - -/** - * @brief Card Identification Data: CID Register - */ -typedef struct -{ - __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ - __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ - __IO uint32_t ProdName1; /*!< Product Name part1 */ - __IO uint8_t ProdName2; /*!< Product Name part2 */ - __IO uint8_t ProdRev; /*!< Product Revision */ - __IO uint32_t ProdSN; /*!< Product Serial Number */ - __IO uint8_t Reserved1; /*!< Reserved1 */ - __IO uint16_t ManufactDate; /*!< Manufacturing Date */ - __IO uint8_t CID_CRC; /*!< CID CRC */ - __IO uint8_t Reserved2; /*!< Always 1 */ - -}HAL_SD_CIDTypedef; - -/** - * @brief SD Card Status returned by ACMD13 - */ -typedef struct -{ - __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */ - __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */ - __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */ - __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */ - __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */ - __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */ - __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */ - __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */ - __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */ - __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */ - -}HAL_SD_CardStatusTypedef; - -/** - * @brief SD Card information structure - */ -typedef struct -{ - HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */ - HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */ - uint64_t CardCapacity; /*!< Card capacity */ - uint32_t CardBlockSize; /*!< Card block size */ - uint16_t RCA; /*!< SD relative card address */ - uint8_t CardType; /*!< SD card type */ - -}HAL_SD_CardInfoTypedef; - -/** - * @brief SD Error status enumeration Structure definition - */ -typedef enum -{ -/** - * @brief SD specific error defines - */ - SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ - SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */ - SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ - SD_DATA_TIMEOUT = (4), /*!< Data timeout */ - SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */ - SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */ - SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */ - SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */ - SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ - SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ - SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */ - SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */ - SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ - SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ - SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ - SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ - SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ - SD_CC_ERROR = (18), /*!< Internal card controller error */ - SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */ - SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ - SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ - SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ - SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */ - SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ - SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ - SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ - SD_INVALID_VOLTRANGE = (27), - SD_ADDR_OUT_OF_RANGE = (28), - SD_SWITCH_ERROR = (29), - SD_SDIO_DISABLED = (30), - SD_SDIO_FUNCTION_BUSY = (31), - SD_SDIO_FUNCTION_FAILED = (32), - SD_SDIO_UNKNOWN_FUNCTION = (33), - -/** - * @brief Standard error defines - */ - SD_INTERNAL_ERROR = (34), - SD_NOT_CONFIGURED = (35), - SD_REQUEST_PENDING = (36), - SD_REQUEST_NOT_APPLICABLE = (37), - SD_INVALID_PARAMETER = (38), - SD_UNSUPPORTED_FEATURE = (39), - SD_UNSUPPORTED_HW = (40), - SD_ERROR = (41), - SD_OK = (0) - -}HAL_SD_ErrorTypedef; - -/** - * @brief SD Transfer state enumeration structure - */ -typedef enum -{ - SD_TRANSFER_OK = 0, /*!< Transfer success */ - SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */ - SD_TRANSFER_ERROR = 2 /*!< Transfer failed */ - -}HAL_SD_TransferStateTypedef; - -/** - * @brief SD Card State enumeration structure - */ -typedef enum -{ - SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */ - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */ - SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */ - SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */ - SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */ - SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */ - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */ - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */ - SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */ - -}HAL_SD_CardStateTypedef; - -/** - * @brief SD Operation enumeration structure - */ -typedef enum -{ - SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */ - SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */ - SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */ - SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */ - -}HAL_SD_OperationTypedef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants SD Exported Constants - * @{ - */ - -/** - * @brief SD Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ -#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ -#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ -#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ -#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ -#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective - for SDHS and SDXC. */ -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by - STOP_TRANSMISSION command. */ -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ -#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command - system set by switch function command (CMD6). */ -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. - Reserved for each command system set by switch function command (CMD6). */ -#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by - the SET_BLOCK_LEN command. */ -#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather - than a standard command. */ -#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card - for general purpose/application specific commands. */ -#define SD_CMD_NO_CMD ((uint8_t)64) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus - widths are given in SCR register. */ -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with - 32bit+CRC data block. */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to - send its operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SD_CMD_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */ - -/** - * @brief Supported SD Memory Cards - */ -#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SD_Exported_macros SD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/** - * @brief Enable the SD device. - * @retval None - */ -#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE() - -/** - * @brief Disable the SD device. - * @retval None - */ -#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE() - -/** - * @brief Enable the SDIO DMA transfer. - * @retval None - */ -#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE() - -/** - * @brief Disable the SDIO DMA transfer. - * @retval None - */ -#define __HAL_SD_SDIO_DMA_DISABLE() __SDIO_DMA_DISABLE() - -/** - * @brief Enable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval None - */ -#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Disable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval None - */ -#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SD FLAG (SET or RESET). - */ -#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) - -/** - * @brief Clear the SD's pending flags. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) - -/** - * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SD IT (SET or RESET). - */ -#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__) - -/** - * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__ : SD Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SD_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions **********************************/ -/** @addtogroup SD_Exported_Functions_Group1 - * @{ - */ -HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo); -HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); -void HAL_SD_MspInit(SD_HandleTypeDef *hsd); -void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); -/** - * @} - */ - -/* I/O operation functions *****************************************************/ -/** @addtogroup SD_Exported_Functions_Group2 - * @{ - */ -/* Blocking mode: Polling */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr); - -/* Non-Blocking mode: Interrupt */ -void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); - -/* Callback in non blocking modes (DMA) */ -void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd); -void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd); - -/* Non-Blocking mode: DMA */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); -HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ -/** @addtogroup SD_Exported_Functions_Group3 - * @{ - */ -HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo); -HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode); -HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd); -HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd); -/** - * @} - */ - -/* Peripheral State functions **************************************************/ -/** @addtogroup SD_Exported_Functions_Group4 - * @{ - */ -HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus); -HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#endif /* __STM32L1xx_HAL_SD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h deleted file mode 100644 index f24169fbe..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h +++ /dev/null @@ -1,587 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_smartcard.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains all the functions prototypes for the SMARTCARD - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_SMARTCARD_H -#define __STM32L1xx_HAL_SMARTCARD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup SMARTCARD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types - * @{ - */ - - -/** - * @brief SMARTCARD Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (hsc->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref SMARTCARD_Word_Length */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref SMARTCARD_Stop_Bits */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref SMARTCARD_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits).*/ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref SMARTCARD_Mode */ - - uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ - - uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SMARTCARD_Clock_Phase */ - - uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref SMARTCARD_Last_Bit */ - - uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler - This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ - - uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time - This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ - - uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state - This parameter can be a value of @ref SMARTCARD_NACK_State */ -}SMARTCARD_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ -}HAL_SMARTCARD_StateTypeDef; - -/** - * @brief HAL SMARTCARD Error Code structure definition - */ -typedef enum -{ - HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ - HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ - HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ - HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ - HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_SMARTCARD_ErrorTypeDef; - -/** - * @brief SMARTCARD handle Structure definition - */ -typedef struct -{ - USART_TypeDef *Instance; /* USART registers base address */ - - SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */ - - uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */ - - uint16_t TxXferSize; /* SmartCard Tx Transfer size */ - - uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */ - - uint16_t RxXferSize; /* SmartCard Rx Transfer size */ - - uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */ - - DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /* Locking object */ - - __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */ - - __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SmartCard Error code */ -}SMARTCARD_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants - * @{ - */ - -/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length - * @{ - */ -#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000) -#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) -/** - * @} - */ - -/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits - * @{ - */ -#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000) -#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) -#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) -#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \ - ((STOPBITS) == SMARTCARD_STOPBITS_1_5)) -/** - * @} - */ - -/** @defgroup SMARTCARD_Parity SMARTCARD Parity - * @{ - */ -#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000) -#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ - ((PARITY) == SMARTCARD_PARITY_ODD)) -/** - * @} - */ - -/** @defgroup SMARTCARD_Mode SMARTCARD Mode - * @{ - */ -#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) -#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) -#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) -/** - * @} - */ - -/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity - * @{ - */ -#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) -#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) -#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) -/** - * @} - */ - -/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase - * @{ - */ -#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) -#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) -#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) -/** - * @} - */ - -/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit - * @{ - */ -#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) -#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ - ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) -/** - * @} - */ - -/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State - * @{ - */ -#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000) -#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \ - ((NACK) == SMARTCARD_NACK_DISABLED)) -/** - * @} - */ - -/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests - * @{ - */ - -#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) -#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) - -/** - * @} - */ - -/** @defgroup SMARTCARD_Flags SMARTCARD Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the SR register - * @{ - */ - -#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC) -#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE) -#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE) -#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE) -/** - * @} - */ - -/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition - * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register - * - Y : Interrupt source register (4 bits) - * - 01: CR1 register - * - 10: CR3 register - - * - * @{ - */ -#define SMARTCARD_IT_PE ((uint32_t)0x10000100) -#define SMARTCARD_IT_TXE ((uint32_t)0x10000080) -#define SMARTCARD_IT_TC ((uint32_t)0x10000040) -#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020) -#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010) -#define SMARTCARD_IT_ERR ((uint32_t)0x20000001) - -/** - * @} - */ - -/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask - * @{ - */ -#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros - * @{ - */ - - -/** @brief Reset SMARTCARD handle state - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) - -/** @brief Flushs the Smartcard DR register - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) - -/** @brief Checks whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag - * @arg SMARTCARD_FLAG_TC: Transmission Complete flag - * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag - * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag - * @arg SMARTCARD_FLAG_ORE: OverRun Error flag - * @arg SMARTCARD_FLAG_NE: Noise Error flag - * @arg SMARTCARD_FLAG_FE: Framing Error flag - * @arg SMARTCARD_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified Smartcard pending flags. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @param __FLAG__: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg SMARTCARD_FLAG_TC: Transmission Complete flag. - * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun - * error) flags are cleared by software sequence: a read operation to - * USART_SR register followed by a read operation to USART_DR register. - * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. - * - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) -/** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Enables the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. - * This parameter can be one of the following values: - * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt - * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt - * @arg SMARTCARD_IT_PE: Parity Error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK))) - -/** @brief Disables the specified SmartCard interrupts. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. - * This parameter can be one of the following values: - * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt - * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt - * @arg SMARTCARD_IT_PE: Parity Error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK))) - -/** @brief Checks whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @param __IT__: specifies the SMARTCARD interrupt source to check. - * This parameter can be one of the following values: - * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt - * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt - * @arg SMARTCARD_IT_PE: Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) - -/** @brief Enable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) - -/** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. - * This parameter can be USARTx with x: 1, 2 or 3. - * @retval None - */ -#define __HAL_SMARTCARD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) - - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros - * @{ - */ - -/** @brief Macros to enable or disable the SmartCard DMA request. - * @param __HANDLE__: specifies the SmartCard Handle. - * @param __REQUEST__: specifies the SmartCard DMA request. - * This parameter can be one of the following values: - * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request - * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request - */ -#define SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) -#define SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) - -#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) -#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100) -#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -#define SMARTCARD_BRR(__PCLK__, __BAUD__) ((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) - -/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the - * maximum clock on L1 (i.e. 32 MHz) divided by the oversampling used - * on the SMARTCARD (i.e. 16). No overSampling by 16 on Smartcard. - * @param __BAUDRATE__: Baud rate set by the configuration function. - * @retval Test result (TRUE or FALSE) - */ -#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001) -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions - * @{ - */ - -/** @addtogroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc); -HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc); -HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc); -void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc); -void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc); - -/** - * @} - */ - -/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); -void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc); -void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc); -void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc); -void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc); - -/** - * @} - */ - -/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ - -/* Peripheral State and Errors functions functions *****************************/ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_SMARTCARD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h deleted file mode 100644 index 419e3055a..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h +++ /dev/null @@ -1,556 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_spi.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of SPI HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_SPI_H -#define __STM32L1xx_HAL_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SPI_Exported_Types SPI Exported Types - * @{ - */ - -/** - * @brief SPI Configuration Structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint32_t Direction; /*!< Specifies the SPI Directional mode state. - This parameter can be a value of @ref SPI_Direction_mode */ - - uint32_t DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set */ - - uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. - This parameter can be a value of @ref SPI_TI_mode */ - - uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. - This parameter can be a value of @ref SPI_CRC_Calculation */ - - uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ - -}SPI_InitTypeDef; - -/** - * @brief HAL SPI State structure definition - */ -typedef enum -{ - HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ - HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ - -}HAL_SPI_StateTypeDef; - -/** - * @brief HAL SPI Error Code structure definition - */ -typedef enum -{ - HAL_SPI_ERROR_NONE = 0x00, /*!< No error */ - HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */ - HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */ - HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */ - HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */ - HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */ - -}HAL_SPI_ErrorTypeDef; - -/** - * @brief SPI handle Structure definition - */ -typedef struct __SPI_HandleTypeDef -{ - SPI_TypeDef *Instance; /* SPI registers base address */ - - SPI_InitTypeDef Init; /* SPI communication parameters */ - - uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ - - uint16_t TxXferSize; /* SPI Tx transfer size */ - - uint16_t TxXferCount; /* SPI Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ - - uint16_t RxXferSize; /* SPI Rx transfer size */ - - uint16_t RxXferCount; /* SPI Rx Transfer Counter */ - - DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */ - - void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */ - - void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */ - - HAL_LockTypeDef Lock; /* SPI locking object */ - - __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ - - __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */ - -}SPI_HandleTypeDef; -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants SPI Exported Constants - * @{ - */ - -/** @defgroup SPI_mode SPI mode - * @{ - */ -#define SPI_MODE_SLAVE ((uint32_t)0x00000000) -#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) - -#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ - ((MODE) == SPI_MODE_MASTER)) -/** - * @} - */ - -/** @defgroup SPI_Direction_mode SPI Direction mode - * @{ - */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) -#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY -#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE - -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((MODE) == SPI_DIRECTION_1LINE)) - -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_1LINE)) - -#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) - -/** - * @} - */ - -/** @defgroup SPI_data_size SPI data size - * @{ - */ -#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) -#define SPI_DATASIZE_16BIT SPI_CR1_DFF - -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity SPI Clock Polarity - * @{ - */ -#define SPI_POLARITY_LOW ((uint32_t)0x00000000) -#define SPI_POLARITY_HIGH SPI_CR1_CPOL - -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ - ((CPOL) == SPI_POLARITY_HIGH)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase SPI Clock Phase - * @{ - */ -#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) -#define SPI_PHASE_2EDGE SPI_CR1_CPHA - -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ - ((CPHA) == SPI_PHASE_2EDGE)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management SPI Slave Select management - * @{ - */ -#define SPI_NSS_SOFT SPI_CR1_SSM -#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) -#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) - -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ - ((NSS) == SPI_NSS_HARD_INPUT) || \ - ((NSS) == SPI_NSS_HARD_OUTPUT)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler - * @{ - */ -#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) -#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) -#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) -#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) -#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) - -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission - * @{ - */ -#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) -#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST - -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ - ((BIT) == SPI_FIRSTBIT_LSB)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Calculation SPI CRC Calculation - * @{ - */ -#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) -#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN - -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) -/** - * @} - */ - -/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition - * @{ - */ -#define SPI_IT_TXE SPI_CR2_TXEIE -#define SPI_IT_RXNE SPI_CR2_RXNEIE -#define SPI_IT_ERR SPI_CR2_ERRIE -/** - * @} - */ - -/** @defgroup SPI_Flag_definition SPI Flag definition - * @{ - */ -#define SPI_FLAG_RXNE SPI_SR_RXNE -#define SPI_FLAG_TXE SPI_SR_TXE -#define SPI_FLAG_CRCERR SPI_SR_CRCERR -#define SPI_FLAG_MODF SPI_SR_MODF -#define SPI_FLAG_OVR SPI_SR_OVR -#define SPI_FLAG_BSY SPI_SR_BSY -#define SPI_FLAG_FRE SPI_SR_FRE - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SPI_Exported_Macros SPI Exported Macros - * @{ - */ - -/** @brief Reset SPI handle state - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) - -/** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg SPI_IT_TXE: Tx buffer empty interrupt enable - * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable - * @arg SPI_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) - -/** @brief Check if the specified SPI interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_IT_TXE: Tx buffer empty interrupt enable - * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable - * @arg SPI_IT_ERR: Error interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SPI_FLAG_RXNE: Receive buffer not empty flag - * @arg SPI_FLAG_TXE: Transmit buffer empty flag - * @arg SPI_FLAG_CRCERR: CRC error flag - * @arg SPI_FLAG_MODF: Mode fault flag - * @arg SPI_FLAG_OVR: Overrun flag - * @arg SPI_FLAG_BSY: Busy flag - * @arg SPI_FLAG_FRE: Frame format error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) - -/** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE);}while(0) - -/** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ - (__HANDLE__)->Instance->SR;}while(0) - -/** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR) - -/** @brief Enables the SPI. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) - -/** @brief Disables the SPI. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) -/** - * @} - */ - - -/* Private macro ------------------------------------------------------------*/ -/** @defgroup SPI_Private_Macros SPI Private Macros - * @{ - */ - -/** @brief Sets the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) - -/** @brief Sets the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) - -/** @brief Resets the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) -/** - * @} - */ - -/* Include SPI HAL Extension module */ -#include "stm32l1xx_hal_spi_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPI_Exported_Functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -/** @addtogroup SPI_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); -void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); -void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); -/** - * @} - */ - -/* I/O operation functions *****************************************************/ -/** @addtogroup SPI_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); - -void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); -/** - * @} - */ - - -/* Peripheral State and Control functions **************************************/ -/** @addtogroup SPI_Exported_Functions_Group3 - * @{ - */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi); - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_SPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi_ex.h deleted file mode 100644 index 6cb3a398e..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi_ex.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_spi_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of SPI HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_SPI_EX_H -#define __STM32L1xx_HAL_SPI_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants SPI Exported Constants - * @{ - */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** @defgroup SPI_TI_mode SPI TI mode - * @{ - */ -#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) -#define SPI_TIMODE_ENABLED SPI_CR2_FRF - -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ - ((MODE) == SPI_TIMODE_ENABLED)) -#else -/** @defgroup SPI_TI_mode SPI TI mode disable - * @brief SPI TI Mode not supported for Category 1 and 2 - * @{ - */ -#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) - -#define IS_SPI_TIMODE(MODE) ((MODE) == SPI_TIMODE_DISABLED) - -#endif -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_SPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h deleted file mode 100644 index 9b25f1328..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h +++ /dev/null @@ -1,202 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_sram.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of SRAM HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_SRAM_H -#define __STM32L1xx_HAL_SRAM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_ll_fsmc.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup SRAM - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_typedef SRAM Exported typedef - * @{ - */ - -/** - * @brief HAL SRAM State structures definition - */ -typedef enum -{ - HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ - HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ - -}HAL_SRAM_StateTypeDef; - -/** - * @brief SRAM handle Structure definition - */ -typedef struct -{ - FSMC_NORSRAM_TYPEDEF *Instance; /*!< Register base address */ - - FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended; /*!< Extended mode register base address */ - - FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ - - HAL_LockTypeDef Lock; /*!< SRAM locking object */ - - __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ - - DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ - -}SRAM_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_macro SRAM Exported macro - * @{ - */ - -/** @brief Reset SRAM handle state - * @param __HANDLE__: SRAM handle - * @retval None - */ -#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup SRAM_Exported_Functions - * @{ - */ - -/** @addtogroup SRAM_Exported_Functions_Group1 - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); - -void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group2 - * @{ - */ - -/* I/O operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); - -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group3 - * @{ - */ - -/* SRAM Control functions ******************************************************/ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); - -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group4 - * @{ - */ - -/* SRAM State functions *********************************************************/ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_SRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h deleted file mode 100644 index 59f5adba0..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h +++ /dev/null @@ -1,1508 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_TIM_H -#define __STM32L1xx_HAL_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" -#include "stm32l1xx_hal_dma.h" -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; - -/** - * @brief Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -}TIM_SlaveConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -typedef struct -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM_Counter_Mode - * @{ - */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS - -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ - ((MODE) == TIM_COUNTERMODE_DOWN) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM_ClockDivision - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) - -#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes - * @{ - */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) -#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) - -#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ - ((MODE) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ - ((MODE) == TIM_OCMODE_ACTIVE) || \ - ((MODE) == TIM_OCMODE_INACTIVE) || \ - ((MODE) == TIM_OCMODE_TOGGLE) || \ - ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) - -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTSTATE_ENABLE)) -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State - * @{ - */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) - -#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ - ((STATE) == TIM_OCFAST_ENABLE)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) - -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCPOLARITY_LOW)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State - * @{ - */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ - ((STATE) == TIM_OCIDLESTATE_RESET)) -/** - * @} - */ - -/** @defgroup TIM_Channel TIM_Channel - * @{ - */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_ALL ((uint32_t)0x0018) - -#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_ALL)) - -#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE - -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ - -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ - -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode - * @{ - */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) - -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ - ((MODE) == TIM_OPMODE_REPETITIVE)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) - -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ - ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition - * @{ - */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) - -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM_DMA_sources - * @{ - */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) - -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM_Event_Source - * @{ - */ -#define TIM_EventSource_Update TIM_EGR_UG -#define TIM_EventSource_CC1 TIM_EGR_CC1G -#define TIM_EventSource_CC2 TIM_EGR_CC2G -#define TIM_EventSource_CC3 TIM_EGR_CC3G -#define TIM_EventSource_CC4 TIM_EGR_CC4G -#define TIM_EventSource_Trigger TIM_EGR_TG - -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM_Flag_definition - * @{ - */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) - -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM_Clock_Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) - -#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ - -#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ - -#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Filter TIM_Clock_Filter - * @{ - */ -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) - -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ - - -#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ - -#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter - * @{ - */ -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ - ((STATE) == TIM_OSSR_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ - ((STATE) == TIM_OSSI_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level TIM_Lock_level - * @{ - */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) - -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ - ((LEVEL) == TIM_LOCKLEVEL_1) || \ - ((LEVEL) == TIM_LOCKLEVEL_2) || \ - ((LEVEL) == TIM_LOCKLEVEL_3)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset - * @{ - */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection - * @{ - */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM_Slave_Mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) -#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) - -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ - ((MODE) == TIM_SLAVEMODE_GATED) || \ - ((MODE) == TIM_SLAVEMODE_RESET) || \ - ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ - ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection - * @{ - */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) - -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_NONE)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ - -#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ - -#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter - * @{ - */ -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM_TI1_Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) - -#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ - ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address - * @{ - */ -#define TIM_DMABase_CR1 (0x00000000) -#define TIM_DMABase_CR2 (0x00000001) -#define TIM_DMABase_SMCR (0x00000002) -#define TIM_DMABase_DIER (0x00000003) -#define TIM_DMABase_SR (0x00000004) -#define TIM_DMABase_EGR (0x00000005) -#define TIM_DMABase_CCMR1 (0x00000006) -#define TIM_DMABase_CCMR2 (0x00000007) -#define TIM_DMABase_CCER (0x00000008) -#define TIM_DMABase_CNT (0x00000009) -#define TIM_DMABase_PSC (0x0000000A) -#define TIM_DMABase_ARR (0x0000000B) -#define TIM_DMABase_CCR1 (0x0000000D) -#define TIM_DMABase_CCR2 (0x0000000E) -#define TIM_DMABase_CCR3 (0x0000000F) -#define TIM_DMABase_CCR4 (0x00000010) -#define TIM_DMABase_DCR (0x00000012) -#define TIM_DMABase_OR (0x00000013) - -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length - * @{ - */ -#define TIM_DMABurstLength_1Transfer (0x00000000) -#define TIM_DMABurstLength_2Transfers (0x00000100) -#define TIM_DMABurstLength_3Transfers (0x00000200) -#define TIM_DMABurstLength_4Transfers (0x00000300) -#define TIM_DMABurstLength_5Transfers (0x00000400) -#define TIM_DMABurstLength_6Transfers (0x00000500) -#define TIM_DMABurstLength_7Transfers (0x00000600) -#define TIM_DMABurstLength_8Transfers (0x00000700) -#define TIM_DMABurstLength_9Transfers (0x00000800) -#define TIM_DMABurstLength_10Transfers (0x00000900) -#define TIM_DMABurstLength_11Transfers (0x00000A00) -#define TIM_DMABurstLength_12Transfers (0x00000B00) -#define TIM_DMABurstLength_13Transfers (0x00000C00) -#define TIM_DMABurstLength_14Transfers (0x00000D00) -#define TIM_DMABurstLength_15Transfers (0x00000E00) -#define TIM_DMABurstLength_16Transfers (0x00000F00) -#define TIM_DMABurstLength_17Transfers (0x00001000) -#define TIM_DMABurstLength_18Transfers (0x00001100) - -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value - * @{ - */ -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup DMA_Handle_index DMA_Handle_index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State Channel_CC_State - * @{ - */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** - * @} - */ - -/* Private Constants -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM_Private_Constants - * @{ - */ - -/* The counter of a timer instance is disabled only if all the CCx - channels have been disabled */ -#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -/** - * @} - */ - - - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } while(0) - -/** - * @brief Enable the specified TIM interrupt. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__: TIM handle - * @param __DMA__: specifies the DMA Channel to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** - * @brief Disable the specified TIM interrupt. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__: TIM handle - * @param __DMA__: specifies the DMA Channel to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** - * @brief Get the TIM Channel pending flags. - * @param __HANDLE__: TIM handle - * @param __FLAG__: Get the specified flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the TIM Channel pending flags. - * @param __HANDLE__: TIM handle - * @param __FLAG__: specifies the flag to clear. - * @retval None - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Checks whether the specified TIM interrupt has occurred or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** @brief TIM counter direction - * @param __HANDLE__: TIM handle - */ -#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** @brief Set TIM prescaler - * @param __HANDLE__: TIM handle - * @param __PRESC__: specifies the prescaler value. - * @retval None - */ -#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** @brief Set TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @param __ICPSC__: specifies the prescaler value. - * @retval None - */ -#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) - -/** @brief Reset TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @retval None - */ -#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) - -/** - * @brief Sets the TIM Capture Compare Register value on runtime without - * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__: specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) - -/** - * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval None - */ -#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ - (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) - -/** - * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_GetCounter(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) - -/** - * @brief Sets the TIM Autoreload Register value on runtime without calling - * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_GetAutoreload(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) - -/** - * @brief Sets the TIM Clock Division value on runtime without calling - * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1 - * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 - * @retval None - */ -#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_GetClockDivision(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Sets the TIM Input Capture prescaler on runtime without calling - * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ - __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None - */ -#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) - -/** - * @} - */ - -/* Include TIM HAL Extension module */ -#include "stm32l1xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 - * @{ - */ -/* Timer Output Compare functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 - * @{ - */ -/* Timer PWM functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 - * @{ - */ -/* Timer Input Capture functions ***********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 - * @{ - */ -/* Timer One Pulse functions ***************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 - * @{ - */ -/* Timer Encoder functions *****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 - * @{ - */ -/* Interrupt Handler functions **********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group8 - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group9 - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group10 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h~RF15e1dc3.TMP b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h~RF15e1dc3.TMP deleted file mode 100644 index 9d22464be..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h~RF15e1dc3.TMP +++ /dev/null @@ -1,1508 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_TIM_H -#define __STM32L1xx_HAL_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; - -/** - * @brief Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -}TIM_SlaveConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -typedef struct -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM_Counter_Mode - * @{ - */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS - -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ - ((MODE) == TIM_COUNTERMODE_DOWN) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM_ClockDivision - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) - -#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes - * @{ - */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) -#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) - -#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ - ((MODE) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ - ((MODE) == TIM_OCMODE_ACTIVE) || \ - ((MODE) == TIM_OCMODE_INACTIVE) || \ - ((MODE) == TIM_OCMODE_TOGGLE) || \ - ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) - -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTSTATE_ENABLE)) -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State - * @{ - */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) - -#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ - ((STATE) == TIM_OCFAST_ENABLE)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) - -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCPOLARITY_LOW)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State - * @{ - */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ - ((STATE) == TIM_OCIDLESTATE_RESET)) -/** - * @} - */ - -/** @defgroup TIM_Channel TIM_Channel - * @{ - */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_ALL ((uint32_t)0x0018) - -#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_ALL)) - -#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE - -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ - -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ - -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode - * @{ - */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) - -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ - ((MODE) == TIM_OPMODE_REPETITIVE)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) - -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ - ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition - * @{ - */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) - -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM_DMA_sources - * @{ - */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) - -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM_Event_Source - * @{ - */ -#define TIM_EventSource_Update TIM_EGR_UG -#define TIM_EventSource_CC1 TIM_EGR_CC1G -#define TIM_EventSource_CC2 TIM_EGR_CC2G -#define TIM_EventSource_CC3 TIM_EGR_CC3G -#define TIM_EventSource_CC4 TIM_EGR_CC4G -#define TIM_EventSource_Trigger TIM_EGR_TG - -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM_Flag_definition - * @{ - */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) - -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM_Clock_Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) - -#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ - -#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ - -#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Filter TIM_Clock_Filter - * @{ - */ -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) - -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ - - -#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ - -#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter - * @{ - */ -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ - ((STATE) == TIM_OSSR_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ - ((STATE) == TIM_OSSI_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level TIM_Lock_level - * @{ - */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) - -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ - ((LEVEL) == TIM_LOCKLEVEL_1) || \ - ((LEVEL) == TIM_LOCKLEVEL_2) || \ - ((LEVEL) == TIM_LOCKLEVEL_3)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset - * @{ - */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection - * @{ - */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM_Slave_Mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) -#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) - -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ - ((MODE) == TIM_SLAVEMODE_GATED) || \ - ((MODE) == TIM_SLAVEMODE_RESET) || \ - ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ - ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection - * @{ - */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) - -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_NONE)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ - -#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ - -#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter - * @{ - */ -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM_TI1_Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) - -#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ - ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address - * @{ - */ -#define TIM_DMABase_CR1 (0x00000000) -#define TIM_DMABase_CR2 (0x00000001) -#define TIM_DMABase_SMCR (0x00000002) -#define TIM_DMABase_DIER (0x00000003) -#define TIM_DMABase_SR (0x00000004) -#define TIM_DMABase_EGR (0x00000005) -#define TIM_DMABase_CCMR1 (0x00000006) -#define TIM_DMABase_CCMR2 (0x00000007) -#define TIM_DMABase_CCER (0x00000008) -#define TIM_DMABase_CNT (0x00000009) -#define TIM_DMABase_PSC (0x0000000A) -#define TIM_DMABase_ARR (0x0000000B) -#define TIM_DMABase_CCR1 (0x0000000D) -#define TIM_DMABase_CCR2 (0x0000000E) -#define TIM_DMABase_CCR3 (0x0000000F) -#define TIM_DMABase_CCR4 (0x00000010) -#define TIM_DMABase_DCR (0x00000012) -#define TIM_DMABase_OR (0x00000013) - -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length - * @{ - */ -#define TIM_DMABurstLength_1Transfer (0x00000000) -#define TIM_DMABurstLength_2Transfers (0x00000100) -#define TIM_DMABurstLength_3Transfers (0x00000200) -#define TIM_DMABurstLength_4Transfers (0x00000300) -#define TIM_DMABurstLength_5Transfers (0x00000400) -#define TIM_DMABurstLength_6Transfers (0x00000500) -#define TIM_DMABurstLength_7Transfers (0x00000600) -#define TIM_DMABurstLength_8Transfers (0x00000700) -#define TIM_DMABurstLength_9Transfers (0x00000800) -#define TIM_DMABurstLength_10Transfers (0x00000900) -#define TIM_DMABurstLength_11Transfers (0x00000A00) -#define TIM_DMABurstLength_12Transfers (0x00000B00) -#define TIM_DMABurstLength_13Transfers (0x00000C00) -#define TIM_DMABurstLength_14Transfers (0x00000D00) -#define TIM_DMABurstLength_15Transfers (0x00000E00) -#define TIM_DMABurstLength_16Transfers (0x00000F00) -#define TIM_DMABurstLength_17Transfers (0x00001000) -#define TIM_DMABurstLength_18Transfers (0x00001100) - -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value - * @{ - */ -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup DMA_Handle_index DMA_Handle_index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State Channel_CC_State - * @{ - */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** - * @} - */ - -/* Private Constants -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM_Private_Constants - * @{ - */ - -/* The counter of a timer instance is disabled only if all the CCx - channels have been disabled */ -#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -/** - * @} - */ - - - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } while(0) - -/** - * @brief Enable the specified TIM interrupt. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__: TIM handle - * @param __DMA__: specifies the DMA Channel to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** - * @brief Disable the specified TIM interrupt. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__: TIM handle - * @param __DMA__: specifies the DMA Channel to be enabled or disabled. - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** - * @brief Get the TIM Channel pending flags. - * @param __HANDLE__: TIM handle - * @param __FLAG__: Get the specified flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the TIM Channel pending flags. - * @param __HANDLE__: TIM handle - * @param __FLAG__: specifies the flag to clear. - * @retval None - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Checks whether the specified TIM interrupt has occurred or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** @brief TIM counter direction - * @param __HANDLE__: TIM handle - */ -#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** @brief Set TIM prescaler - * @param __HANDLE__: TIM handle - * @param __PRESC__: specifies the prescaler value. - * @retval None - */ -#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** @brief Set TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @param __ICPSC__: specifies the prescaler value. - * @retval None - */ -#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) - -/** @brief Reset TIM IC prescaler - * @param __HANDLE__: TIM handle - * @param __CHANNEL__: specifies TIM Channel - * @retval None - */ -#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) - -/** - * @brief Sets the TIM Capture Compare Register value on runtime without - * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__: specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) - -/** - * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval None - */ -#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ - (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) - -/** - * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_GetCounter(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) - -/** - * @brief Sets the TIM Autoreload Register value on runtime without calling - * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_GetAutoreload(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) - -/** - * @brief Sets the TIM Clock Division value on runtime without calling - * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1 - * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 - * @retval None - */ -#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__: TIM handle. - * @retval None - */ -#define __HAL_TIM_GetClockDivision(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Sets the TIM Input Capture prescaler on runtime without calling - * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ - __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None - */ -#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) - -/** - * @} - */ - -/* Include TIM HAL Extension module */ -#include "stm32l1xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 - * @{ - */ -/* Timer Output Compare functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 - * @{ - */ -/* Timer PWM functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 - * @{ - */ -/* Timer Input Capture functions ***********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 - * @{ - */ -/* Timer One Pulse functions ***************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 - * @{ - */ -/* Timer Encoder functions *****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 - * @{ - */ -/* Interrupt Handler functions **********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group8 - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group9 - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group10 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h deleted file mode 100644 index 437f12be6..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim_ex.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of TIM HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_TIM_EX_H -#define __STM32L1xx_HAL_TIM_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIMEx Exported Types - * @{ - */ - -/** - * @brief TIM Master configuration Structure definition - */ -typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ -}TIM_MasterConfigTypeDef; - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIMEx_Exported_Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIMEx_Remap - * @{ - */ - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /* !< TIM2 ITR1 input is connected to TIM10 OC */ -#define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /* !< TIM2 ITR1 input is connected to TIM5 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /* !< TIM3 ITR2 input is connected to TIM11 OC */ -#define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /* !< TIM3 ITR2 input is connected to TIM5 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /* !< TIM9 ITR1 input is connected to TIM3 TGO */ -#define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /* !< TIM9 ITR1 input is connected to touch sensing I/O */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ -#define TIM_TIM9_GPIO (0x00000000) /* !< TIM9 Channel1 is connected to GPIO */ -#define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /* !< TIM9 Channel1 is connected to LSE internal clock */ -#define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /* !< TIM9 Channel1 is connected to GPIO */ -#define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /* !< TIM9 Channel1 is connected to GPIO */ - - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM10_TI1RMP (0x00000000) /* !< TIM10 Channel 1 depends on TI1_RMP */ -#define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /* !< TIM10 Channel 1 is connected to RI */ -#define TIM_TIM10_ETR_LSE (0x00000000) /* !< TIM10 ETR input is connected to LSE clock */ -#define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /* !< TIM10 ETR input is connected to TIM9 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ -#define TIM_TIM10_GPIO (0x00000000) /* !< TIM10 Channel1 is connected to GPIO */ -#define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /* !< TIM10 Channel1 is connected to LSI internal clock */ -#define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /* !< TIM10 Channel1 is connected to LSE internal clock */ -#define TIM_TIM10_RTC TIM_OR_TI1RMP /* !< TIM10 Channel1 is connected to RTC wakeup interrupt */ - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define TIM_TIM11_TI1RMP (0x00000000) /* !< TIM11 Channel 1 depends on TI1_RMP */ -#define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /* !< TIM11 Channel 1 is connected to RI */ -#define TIM_TIM11_ETR_LSE (0x00000000) /* !< TIM11 ETR input is connected to LSE clock */ -#define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /* !< TIM11 ETR input is connected to TIM9 TGO */ -#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ -#define TIM_TIM11_GPIO (0x00000000) /* !< TIM11 Channel1 is connected to GPIO */ -#define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /* !< TIM11 Channel1 is connected to MSI internal clock */ -#define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /* !< TIM11 Channel1 is connected to HSE_RTC clock */ -#define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /* !< TIM11 Channel1 is connected to GPIO */ - - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \ - (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \ - (((INSTANCE) == TIM9) && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2))) || \ - (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \ - (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \ - ) -#else /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */ -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \ - (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \ - (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1))) \ - ) -#endif - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 - * @{ - */ -/* Extension Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 - * @{ - */ - -/** - * @} - */ - -/* Extension Callback *********************************************************/ - -/** @addtogroup TIMEx_Exported_Functions_Group3 - * @{ - */ - -/** - * @} - */ -/* Extension Peripheral State functions **************************************/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h deleted file mode 100644 index 0329bd7d9..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h +++ /dev/null @@ -1,624 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_uart.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains all the functions prototypes for the UART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_UART_H -#define __STM32L1xx_HAL_UART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UART_Word_Length */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode */ - - uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control */ - - uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). - This parameter can be a value of @ref UART_Over_Sampling */ -}UART_InitTypeDef; - -/** - * @brief HAL UART State structures definition - */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_UART_STATE_ERROR = 0x04 /*!< Error */ -}HAL_UART_StateTypeDef; - -/** - * @brief HAL UART Error Code structure definition - */ -typedef enum -{ - HAL_UART_ERROR_NONE = 0x00, /*!< No error */ - HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_UART_ErrorTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct -{ - USART_TypeDef *Instance; /* UART registers base address */ - - UART_InitTypeDef Init; /* UART communication parameters */ - - uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /* UART Tx Transfer size */ - - uint16_t TxXferCount; /* UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /* UART Rx Transfer size */ - - uint16_t RxXferCount; /* UART Rx Transfer Counter */ - - DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /* Locking object */ - - __IO HAL_UART_StateTypeDef State; /* UART communication state */ - - __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */ - -}UART_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported constants - * @{ - */ - -/** @defgroup UART_Word_Length UART Word Length - * @{ - */ -#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ - ((LENGTH) == UART_WORDLENGTH_9B)) -/** - * @} - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_1 ((uint32_t)0x00000000) -#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ - ((STOPBITS) == UART_STOPBITS_2)) -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE ((uint32_t)0x00000000) -#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ - ((PARITY) == UART_PARITY_EVEN) || \ - ((PARITY) == UART_PARITY_ODD)) -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) -#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) -#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == UART_HWCONTROL_NONE) || \ - ((CONTROL) == UART_HWCONTROL_RTS) || \ - ((CONTROL) == UART_HWCONTROL_CTS) || \ - ((CONTROL) == UART_HWCONTROL_RTS_CTS)) -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX ((uint32_t)USART_CR1_RE) -#define UART_MODE_TX ((uint32_t)USART_CR1_TE) -#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) -/** - * @} - */ - - /** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000) -#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) -#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ - ((STATE) == UART_STATE_ENABLE)) -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) -#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) -#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ - ((SAMPLING) == UART_OVERSAMPLING_8)) -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) -#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) -#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) -/** - * @} - */ - -/** @defgroup UART_WakeUp_functions UART Wakeup Functions - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800) -#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) -/** - * @} - */ - -/** @defgroup UART_Flags UART FLags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the SR register - * @{ - */ -#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) -#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) -#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define UART_FLAG_TC ((uint32_t)USART_SR_TC) -#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define UART_FLAG_NE ((uint32_t)USART_SR_NE) -#define UART_FLAG_FE ((uint32_t)USART_SR_FE) -#define UART_FLAG_PE ((uint32_t)USART_SR_PE) -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupt Definitions - * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register - * - Y : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - * @{ - */ -#define UART_IT_PE ((uint32_t)0x10000100) -#define UART_IT_TXE ((uint32_t)0x10000080) -#define UART_IT_TC ((uint32_t)0x10000040) -#define UART_IT_RXNE ((uint32_t)0x10000020) -#define UART_IT_IDLE ((uint32_t)0x10000010) - -#define UART_IT_LBD ((uint32_t)0x20000040) -#define UART_IT_CTS ((uint32_t)0x30000400) - -#define UART_IT_ERR ((uint32_t)0x30000001) - -/** - * @} - */ - -/** @defgroup UART_Interruption_Mask UART interruptions flag mask - * @{ - */ -#define UART_IT_MASK ((uint32_t)0x0000FFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - - -/** @brief Reset UART handle state - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) - -/** @brief Flushs the UART DR register - * @param __HANDLE__: specifies the UART Handle. - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) - -/** @brief Checks whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg UART_FLAG_LBD: LIN Break detection flag - * @arg UART_FLAG_TXE: Transmit data register empty flag - * @arg UART_FLAG_TC: Transmission Complete flag - * @arg UART_FLAG_RXNE: Receive data register not empty flag - * @arg UART_FLAG_IDLE: Idle Line detection flag - * @arg UART_FLAG_ORE: OverRun Error flag - * @arg UART_FLAG_NE: Noise Error flag - * @arg UART_FLAG_FE: Framing Error flag - * @arg UART_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified UART pending flag. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __FLAG__: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg UART_FLAG_LBD: LIN Break detection flag. - * @arg UART_FLAG_TC: Transmission Complete flag. - * @arg UART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register followed by a read - * operation to USART_DR register. - * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. - * - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) -/** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Enables or disables the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __INTERRUPT__: specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) - -/** @brief Checks whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @param __IT__: specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ERR: Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) - -/** @brief macros to enables or disables the UART's one bit sampling method - * @param __HANDLE__: specifies the UART Handle. - * This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) -#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) - -/** @brief Enable UART - * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART - * The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or - * UART peripheral (availability depending on device for UARTy). - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ - -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_))) -#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100) -#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F)) - -#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_))) -#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100) -#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F)) - -/** @brief Check UART Baud rate - * @param __BAUDRATE__: Baudrate specified by the user - * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001) -#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_UART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h deleted file mode 100644 index 115298864..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h +++ /dev/null @@ -1,579 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_usart.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_USART_H -#define __STM32L1xx_HAL_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup USART_Exported_Types USART Exported Types - * @{ - */ - - -/** - * @brief USART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -}USART_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ -}HAL_USART_StateTypeDef; - -/** - * @brief HAL USART Error Code structure definition - */ -typedef enum -{ - HAL_USART_ERROR_NONE = 0x00, /*!< No error */ - HAL_USART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_USART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_USART_ERROR_FE = 0x04, /*!< frame error */ - HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_USART_ErrorTypeDef; - -/** - * @brief USART handle Structure definition - */ -typedef struct -{ - USART_TypeDef *Instance; /* USART registers base address */ - - USART_InitTypeDef Init; /* Usart communication parameters */ - - uint8_t *pTxBuffPtr; /* Pointer to Usart Tx transfer Buffer */ - - uint16_t TxXferSize; /* Usart Tx Transfer size */ - - __IO uint16_t TxXferCount; /* Usart Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /* Pointer to Usart Rx transfer Buffer */ - - uint16_t RxXferSize; /* Usart Rx Transfer size */ - - __IO uint16_t RxXferCount; /* Usart Rx Transfer Counter */ - - DMA_HandleTypeDef *hdmatx; /* Usart Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /* Usart Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /* Locking object */ - - __IO HAL_USART_StateTypeDef State; /* Usart communication state */ - - __IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */ - -}USART_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_Exported_Constants USART Exported constants - * @{ - */ - -/** @defgroup USART_Word_Length USART Word Length - * @{ - */ -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ - ((LENGTH) == USART_WORDLENGTH_9B)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits USART Number of Stop Bits - * @{ - */ -#define USART_STOPBITS_1 ((uint32_t)0x00000000) -#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) -#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ - ((STOPBITS) == USART_STOPBITS_0_5) || \ - ((STOPBITS) == USART_STOPBITS_1_5) || \ - ((STOPBITS) == USART_STOPBITS_2)) -/** - * @} - */ - -/** @defgroup USART_Parity USART Parity - * @{ - */ -#define USART_PARITY_NONE ((uint32_t)0x00000000) -#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ - ((PARITY) == USART_PARITY_EVEN) || \ - ((PARITY) == USART_PARITY_ODD)) -/** - * @} - */ - -/** @defgroup USART_Mode USART Mode - * @{ - */ -#define USART_MODE_RX ((uint32_t)USART_CR1_RE) -#define USART_MODE_TX ((uint32_t)USART_CR1_TE) -#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000)) -/** - * @} - */ - -/** @defgroup USART_Clock USART Clock - * @{ - */ -#define USART_CLOCK_DISABLED ((uint32_t)0x00000000) -#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \ - ((CLOCK) == USART_CLOCK_ENABLED)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity USART Clock Polarity - * @{ - */ -#define USART_POLARITY_LOW ((uint32_t)0x00000000) -#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) -#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) -/** - * @} - */ - -/** @defgroup USART_Clock_Phase USART Clock Phase - * @{ - */ -#define USART_PHASE_1EDGE ((uint32_t)0x00000000) -#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) -#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) -/** - * @} - */ - -/** @defgroup USART_Last_Bit USART Last Bit - * @{ - */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) -#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ - ((LASTBIT) == USART_LASTBIT_ENABLE)) -/** - * @} - */ - -/** @defgroup USART_NACK_State USART NACK State - * @{ - */ -#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK) -#define USARTNACK_DISABLED ((uint32_t)0x00000000) -#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \ - ((NACK) == USARTNACK_DISABLED)) -/** - * @} - */ - -/** @defgroup USART_Flags USART Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the SR register - * @{ - */ - -#define USART_FLAG_CTS ((uint32_t)USART_SR_CTS) -#define USART_FLAG_LBD ((uint32_t)USART_SR_LBD) -#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define USART_FLAG_TC ((uint32_t)USART_SR_TC) -#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define USART_FLAG_NE ((uint32_t)USART_SR_NE) -#define USART_FLAG_FE ((uint32_t)USART_SR_FE) -#define USART_FLAG_PE ((uint32_t)USART_SR_PE) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition USART Interrupts Definition - * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask in the XX register - * - Y : Interrupt source register (4bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - * @{ - */ -#define USART_IT_PE ((uint32_t)0x10000100) -#define USART_IT_TXE ((uint32_t)0x10000080) -#define USART_IT_TC ((uint32_t)0x10000040) -#define USART_IT_RXNE ((uint32_t)0x10000020) -#define USART_IT_IDLE ((uint32_t)0x10000010) - -#define USART_IT_LBD ((uint32_t)0x20000040) -#define USART_IT_CTS ((uint32_t)0x30000400) - -#define USART_IT_ERR ((uint32_t)0x30000001) - - -/** - * @} - */ - -/** @defgroup USART_Interruption_Mask USART interruptions flag mask - * @{ - */ -#define USART_IT_MASK ((uint32_t)0x0000FFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USART_Exported_Macros USART Exported Macros - * @{ - */ - - -/** @brief Reset USART handle state - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @retval None - */ -#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) - -/** @brief Checks whether the specified USART flag is set or not. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ - -#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified USART pending flags. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @param __FLAG__: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register followed by a read - * operation to USART_DR register. - * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. - * - * @retval None - */ -#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** @brief Clear the USART PE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @retval None - */ -#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->DR;}while(0) -/** @brief Clear the USART FE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @retval None - */ -#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the USART NE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @retval None - */ -#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the USART ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @retval None - */ -#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clear the USART IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @retval None - */ -#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Enables or disables the specified Usart interrupts. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @param __INTERRUPT__: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) - - - -/** @brief Checks whether the specified Usart interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle. - * This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral. - * @param __IT__: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ERR: Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) - -/** @brief Enable USART - * @param __HANDLE__: specifies the USART Handle. - * The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral - * @retval None - */ -#define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) - -/** @brief Disable USART - * @param __HANDLE__: specifies the USART Handle. - * The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral - * @retval None - */ -#define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) - - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup USART_Private_Macros USART Private Macros - * @{ - */ - -#define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) -#define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100) -#define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -#define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) - -/** @brief Check USART Baud rate - * @param __BAUDRATE__: Baudrate specified by the user - * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval Test result (TRUE or FALSE) - */ -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001) -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup USART_Exported_Functions USART Exported Functions - * @{ - */ - -/** @addtogroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); -void HAL_USART_MspInit(USART_HandleTypeDef *husart); -void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); - -/** - * @} - */ - -/** @addtogroup USART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); -void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); -void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); - -/** - * @} - */ - -/* Peripheral Control functions ***********************************************/ - -/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ - -/* Peripheral State and Error functions ***************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_USART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h deleted file mode 100644 index 44d1f0970..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h +++ /dev/null @@ -1,310 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_wwdg.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of WWDG HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_WWDG_H -#define __STM32L1xx_HAL_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Types WWDG Exported Types - * @{ - */ - -/** - * @brief WWDG HAL State Structure definition - */ -typedef enum -{ - HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ - HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ - HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ - HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ - HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ -}HAL_WWDG_StateTypeDef; - -/** - * @brief WWDG Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. - This parameter can be a value of @ref WWDG_Prescaler */ - - uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. - This parameter must be a number lower than Max_Data = 0x80 */ - - uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. - This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - -}WWDG_InitTypeDef; - -/** - * @brief WWDG handle Structure definition - */ -typedef struct -{ - WWDG_TypeDef *Instance; /*!< Register base address */ - - WWDG_InitTypeDef Init; /*!< WWDG required parameters */ - - HAL_LockTypeDef Lock; /*!< WWDG locking object */ - - __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */ - -}WWDG_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants WWDG Exported Constants - * @{ - */ - -/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress AliasRegion - * @brief WWDG registers bit address in the alias region - * @{ - */ - -/* --- CFR Register ---*/ -/* Alias word address of EWI bit */ -#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04) - -/** - * @} - */ - -/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition - * @{ - */ -#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI) - -/** - * @} - */ - -/** @defgroup WWDG_Flag_definition WWDG Flag definition - * @brief WWDG Flag definition - * @{ - */ -#define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */ - -/** - * @} - */ - -/** @defgroup WWDG_Prescaler WWDG Prescaler - * @{ - */ -#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */ - -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ - ((__PRESCALER__) == WWDG_PRESCALER_8)) - -/** - * @} - */ - -/** @defgroup WWDG_Window WWDG Window - * @{ - */ -#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) - -/** - * @} - */ - -/** @defgroup WWDG_Counter WWDG Counter - * @{ - */ -#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Macros WWDG Exported Macros - * @{ - */ - -/** @brief Reset WWDG handle state - * @param __HANDLE__: WWDG handle - * @retval None - */ -#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) - -/** - * @brief Enables the WWDG peripheral. - * @param __HANDLE__: WWDG handle - * @retval None - */ -#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) - -/** - * @brief Gets the selected WWDG's flag status. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - * @retval The new state of WWDG_FLAG (SET or RESET). - */ -#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clears the WWDG's pending flags. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - * @retval None - */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) - -/** - * @brief Enables the WWDG early wakeup interrupt. - * @param __INTERRUPT__: specifies the interrupt to enable. - * This parameter can be one of the following values: - * @arg WWDG_IT_EWI: Early wakeup interrupt - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__)) - -/** @brief Clear the WWDG's interrupt pending bits - * bits to clear the selected interrupt pending bits. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - */ -#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup WWDG_Exported_Functions - * @{ - */ - -/** @addtogroup WWDG_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); - -/** - * @} - */ - -/** @addtogroup WWDG_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); -void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); - -/** - * @} - */ - -/** @addtogroup WWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h deleted file mode 100644 index 4ac76030f..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h +++ /dev/null @@ -1,567 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_ll_fsmc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of FSMC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_LL_FSMC_H -#define __STM32L1xx_LL_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FSMC_LL - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_Bank1_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_Bank1E_TypeDef - -#define FSMC_NORSRAM_DEVICE FSMC_Bank1 -#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E - -/** - * @brief FSMC_NORSRAM Configuration Structure definition - */ -typedef struct -{ - uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory device. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ - - uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - -}FSMC_NORSRAM_InitTypeDef; - - -/** - * @brief FSMC_NORSRAM Timing parameters structure definition - */ -typedef struct -{ - uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between Min_Data = 1 and Max_Data = 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ - - uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ - - uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ - -}FSMC_NORSRAM_TimingTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank - * @{ - */ -#define FSMC_BANK1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_BANK1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_BANK1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_BANK1_NORSRAM4 ((uint32_t)0x00000006) - -/* To keep compatibility with previous families */ -#define FSMC_NORSRAM_BANK1 FSMC_BANK1_NORSRAM1 -#define FSMC_NORSRAM_BANK2 FSMC_BANK1_NORSRAM2 -#define FSMC_NORSRAM_BANK3 FSMC_BANK1_NORSRAM3 -#define FSMC_NORSRAM_BANK4 FSMC_BANK1_NORSRAM4 - -#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \ - ((__BANK__) == FSMC_BANK1_NORSRAM2) || \ - ((__BANK__) == FSMC_BANK1_NORSRAM3) || \ - ((__BANK__) == FSMC_BANK1_NORSRAM4)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing - * @{ - */ - -#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) -#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) - -#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type FSMC Memory Type - * @{ - */ - -#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) -#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) -#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) - - -#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width - * @{ - */ - -#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) -#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) - -#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access - * @{ - */ - -#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) -#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode - * @{ - */ - -#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) -#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) - -#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) -/** - * @} - */ - - -/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity - * @{ - */ - -#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) -#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) - -#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode - * @{ - */ - -#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) -#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) - -#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing FSMC Wait Timing - * @{ - */ - -#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) -#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) - -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation FSMC Write Operation - * @{ - */ - -#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) -#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) - -#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal FSMC Wait Signal - * @{ - */ - -#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) -#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) - -#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) - -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode FSMC Extended Mode - * @{ - */ - -#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) -#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) - -#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait - * @{ - */ - -#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) -#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) - -#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst FSMC Write Burst - * @{ - */ - -#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) -#define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) - -#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time - * @{ - */ - -#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time - * @{ - */ - -#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time - * @{ - */ - -#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration - * @{ - */ - -#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division FSMC CLK Division - * @{ - */ - -#define FSMC_CLK_DIV2 ((uint32_t)0x00000002) -#define FSMC_CLK_DIV3 ((uint32_t)0x00000003) -#define FSMC_CLK_DIV4 ((uint32_t)0x00000004) -#define FSMC_CLK_DIV5 ((uint32_t)0x00000005) -#define FSMC_CLK_DIV6 ((uint32_t)0x00000006) -#define FSMC_CLK_DIV7 ((uint32_t)0x00000007) -#define FSMC_CLK_DIV8 ((uint32_t)0x00000008) -#define FSMC_CLK_DIV9 ((uint32_t)0x00000009) -#define FSMC_CLK_DIV10 ((uint32_t)0x0000000A) -#define FSMC_CLK_DIV11 ((uint32_t)0x0000000B) -#define FSMC_CLK_DIV12 ((uint32_t)0x0000000C) -#define FSMC_CLK_DIV13 ((uint32_t)0x0000000D) -#define FSMC_CLK_DIV14 ((uint32_t)0x0000000E) -#define FSMC_CLK_DIV15 ((uint32_t)0x0000000F) -#define FSMC_CLK_DIV16 ((uint32_t)0x00000010) -#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency FSMC Data Latency - * @{ - */ - -#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode FSMC Access Mode - * @{ - */ - -#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) -#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) -#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) -#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) - -#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ - ((__MODE__) == FSMC_ACCESS_MODE_B) || \ - ((__MODE__) == FSMC_ACCESS_MODE_C) || \ - ((__MODE__) == FSMC_ACCESS_MODE_D)) -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance - * @{ - */ - -#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) - -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance - * @{ - */ - -#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ - -/** - * @brief Enable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank - * @retval none - */ -#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN) - -/** - * @brief Disable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank - * @retval none - */ -#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup FSMC_Exported_Functions - * @{ - */ - -/** @addtogroup HAL_FSMC_NORSRAM_Group1 - * @{ - */ - -/* FSMC_NORSRAM Controller functions ******************************************/ -/* Initialization/de-initialization functions */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank); - -/** - * @} - */ - -/** @addtogroup HAL_FSMC_NORSRAM_Group2 - * @{ - */ - -/* FSMC_NORSRAM Control functions */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_LL_FSMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h deleted file mode 100644 index af0aa6cdb..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h +++ /dev/null @@ -1,907 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_ll_sdmmc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Header file of low layer SDMMC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_LL_SD_H -#define __STM32L1xx_LL_SD_H - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup SDMMC_LL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types - * @{ - */ - -/** - * @brief SDMMC Configuration Structure definition - */ -typedef struct -{ - uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ - - uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ - - uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ - - uint32_t BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ - - uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ - - uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - -}SDIO_InitTypeDef; - - -/** - * @brief SDIO Command Control structure - */ -typedef struct -{ - uint32_t Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register. */ - - uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and - Max_Data = 64 */ - - uint32_t Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDMMC_LL_Response_Type */ - - uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is - enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ - - uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_CPSM_State */ -}SDIO_CmdInitTypeDef; - - -/** - * @brief SDIO Data Control structure - */ -typedef struct -{ - uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ - - uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ - - uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ - - uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_DPSM_State */ -}SDIO_DataInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants - * @{ - */ - -/** @defgroup SDMMC_LL_Clock_Edge Clock Edge - * @{ - */ -#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) -#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE - -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ - ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass - * @{ - */ -#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) -#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS - -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ - ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving - * @{ - */ -#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) -#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV - -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ - ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Bus_Wide Bus Width - * @{ - */ -#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) -#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 -#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 - -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ - ((WIDE) == SDIO_BUS_WIDE_4B) || \ - ((WIDE) == SDIO_BUS_WIDE_8B)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control - * @{ - */ -#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) -#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN - -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ - ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Clock_Division Clock Division - * @{ - */ -#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Command_Index Command Index - * @{ - */ -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Response_Type Response Type - * @{ - */ -#define SDIO_RESPONSE_NO ((uint32_t)0x00000000) -#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 -#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP - -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ - ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ - ((RESPONSE) == SDIO_RESPONSE_LONG)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt - * @{ - */ -#define SDIO_WAIT_NO ((uint32_t)0x00000000) -#define SDIO_WAIT_IT SDIO_CMD_WAITINT -#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND - -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ - ((WAIT) == SDIO_WAIT_IT) || \ - ((WAIT) == SDIO_WAIT_PEND)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_CPSM_State CPSM State - * @{ - */ -#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) -#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN - -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ - ((CPSM) == SDIO_CPSM_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Response_Registers Response Register - * @{ - */ -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) - -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ - ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || \ - ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Data_Length Data Lenght - * @{ - */ -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size - * @{ - */ -#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) -#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 -#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 -#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030) -#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 -#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050) -#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060) -#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070) -#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 -#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090) -#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0) -#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0) -#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0) -#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0) -#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0) - -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ - ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction - * @{ - */ -#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) -#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR - -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ - ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Transfer_Type Transfer Type - * @{ - */ -#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) -#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE - -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ - ((MODE) == SDIO_TRANSFER_MODE_STREAM)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_DPSM_State DPSM State - * @{ - */ -#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) -#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN - -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ - ((DPSM) == SDIO_DPSM_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode - * @{ - */ -#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000) -#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001) - -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ - ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources - * @{ - */ -#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL -#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL -#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT -#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT -#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR -#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR -#define SDIO_IT_CMDREND SDIO_STA_CMDREND -#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT -#define SDIO_IT_DATAEND SDIO_STA_DATAEND -#define SDIO_IT_STBITERR SDIO_STA_STBITERR -#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND -#define SDIO_IT_CMDACT SDIO_STA_CMDACT -#define SDIO_IT_TXACT SDIO_STA_TXACT -#define SDIO_IT_RXACT SDIO_STA_RXACT -#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE -#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF -#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF -#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF -#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE -#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE -#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL -#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL -#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT -#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND - -/** - * @} - */ - -/** @defgroup SDMMC_LL_Flags Flags - * @{ - */ -#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL -#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL -#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT -#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT -#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR -#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR -#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND -#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT -#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND -#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR -#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND -#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT -#define SDIO_FLAG_TXACT SDIO_STA_TXACT -#define SDIO_FLAG_RXACT SDIO_STA_RXACT -#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE -#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF -#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF -#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF -#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE -#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE -#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL -#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL -#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT -#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros - * @{ - */ - -/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions - * @brief SDMMC_LL registers bit address in the alias region - * @{ - */ - -/* ------------ SDIO registers bit address in the alias region -------------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BITNUMBER 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4)) - -/* --- CMD Register ---*/ -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BITNUMBER 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BITNUMBER 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BITNUMBER 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BITNUMBER 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4)) - -/* --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BITNUMBER 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BITNUMBER 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BITNUMBER 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BITNUMBER 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BITNUMBER 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4)) - -/* ---------------------- SDIO registers bit mask --------------------------- */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ - SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ - SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) - -/* --- DCTRL Register ---*/ -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ - SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ - SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ - SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/* SDIO Intialization Frequency (400KHz max) */ -#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) - -/* SDIO Data Transfer Frequency */ -#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4) - -/** - * @} - */ - -/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/** - * @brief Enable the SDIO device. - * @retval None - */ -#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) - -/** - * @brief Disable the SDIO device. - * @retval None - */ -#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) - -/** - * @brief Enable the SDIO DMA transfer. - * @retval None - */ -#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) - -/** - * @brief Disable the SDIO DMA transfer. - * @retval None - */ -#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) - -/** - * @brief Enable the SDIO device interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval None - */ -#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) - -/** - * @brief Disable the SDIO device interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval None - */ -#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) - - -/** - * @brief Clears the SDIO pending flags. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) - -/** - * @brief Enable Start the SD I/O Read Wait operation. - * @retval None - */ -#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) - -/** - * @brief Disable Start the SD I/O Read Wait operations. - * @retval None - */ -#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) - -/** - * @brief Enable Start the SD I/O Read Wait operation. - * @retval None - */ -#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) - -/** - * @brief Disable Stop the SD I/O Read Wait operations. - * @retval None - */ -#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) - -/** - * @brief Enable the SD I/O Mode Operation. - * @retval None - */ -#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) - -/** - * @brief Disable the SD I/O Mode Operation. - * @retval None - */ -#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) - -/** - * @brief Enable the SD I/O Suspend command sending. - * @retval None - */ -#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) - -/** - * @brief Disable the SD I/O Suspend command sending. - * @retval None - */ -#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) - -/** - * @brief Enable the command completion signal. - * @retval None - */ -#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) - -/** - * @brief Disable the command completion signal. - * @retval None - */ -#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) - -/** - * @brief Enable the CE-ATA interrupt. - * @retval None - */ -#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0) - -/** - * @brief Disable the CE-ATA interrupt. - * @retval None - */ -#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1) - -/** - * @brief Enable send CE-ATA command (CMD61). - * @retval None - */ -#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) - -/** - * @brief Disable send CE-ATA command (CMD61). - * @retval None - */ -#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SDMMC_LL_Exported_Functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -/** @addtogroup HAL_SDMMC_LL_Group1 - * @{ - */ -HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); -/** - * @} - */ - -/* I/O operation functions *****************************************************/ -/** @addtogroup HAL_SDMMC_LL_Group2 - * @{ - */ -/* Blocking mode: Polling */ -uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); -HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ -/** @addtogroup HAL_SDMMC_LL_Group3 - * @{ - */ -HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); -HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); -uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); - -/* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); - -/* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); -uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); - -/* SDIO IO Cards mode management functions */ -HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#endif /* __STM32L1xx_LL_SD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Release_Notes.html b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Release_Notes.html deleted file mode 100644 index 57f318105..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Release_Notes.html +++ /dev/null @@ -1,972 +0,0 @@ - - - - - - - - - - - - - -Release Notes for STM32F4xx HAL Drivers - - - - - - - - - - -
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Release Notes for STM32L1xx HAL Drivers

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Copyright - 2014 STMicroelectronics

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Update History

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V1.0.0 / 05-September-2014

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Main Changes

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  • First official release

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- - \ No newline at end of file diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c deleted file mode 100644 index 02673c07e..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c +++ /dev/null @@ -1,454 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup HAL_Private_Defines HAL Private Defines - * @{ - */ - -/** - * @brief STM32L1xx HAL Driver version number V1.0.0 - */ -#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\ - |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32L1xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ - -static __IO uint32_t uwTick; - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout - is needed and the backup domain when enabled. - (+) de-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __Weak - to make override possible in case of other implementations in user file. - -@endverbatim - * @{ - */ - -/** - * @brief This function configures the Flash prefetch, - * Configures time base source, NVIC and Low level hardware - * @note This function is called at the beginning of program after reset and before - * the clock configuration - * @note The time base configuration is based on MSI clock when exiting from Reset. - * Once done, time base tick start incrementing. - * In the default implementation,Systick is used as source of time base. - * the tick variable is incremented each 1ms in its ISR. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the source - * of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __APB1_FORCE_RESET(); - __APB1_RELEASE_RESET(); - - __APB2_FORCE_RESET(); - __APB2_RELEASE_RESET(); - - __AHB_FORCE_RESET(); - __AHB_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __Weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority: Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during Sleep mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick++; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note ThiS function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(__IO uint32_t Delay) -{ - uint32_t tickstart = 0; - tickstart = HAL_GetTick(); - while((HAL_GetTick() - tickstart) < Delay) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Returns the HAL revision - * @retval version: 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32L1xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE) >> 16); -} - -/** - * @brief Returns the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -void HAL_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -void HAL_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c deleted file mode 100644 index 5f62045cd..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c +++ /dev/null @@ -1,1759 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_adc.c - * @author MCD Application conversion - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) - * peripheral: - * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Analog Watchdog configuration - * ++ Channels configuration on regular group - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management - * Other functions (extended functions) are available in file - * "stm32l1xx_hal_adc_ex.c". - * - @verbatim - ============================================================================== - ##### ADC specific features ##### - ============================================================================== - [..] - (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution - - (#) Interrupt generation at the end of regular conversion, end of injected - conversion, and in case of analog watchdog or overrun events. - - (#) Single and continuous conversion modes. - - (#) Scan mode for automatic conversion of channel 0 to channel 'n'. - - (#) Data alignment with in-built data coherency. - - (#) Channel-wise programmable sampling time. - - (#) ADC conversion Regular or Injected groups. - - (#) External trigger (timer or EXTI) with configurable polarity for both - regular and injected groups. - - (#) DMA request generation for transfer of conversions data of regular group. - - (#) ADC calibration - - (#) ADC offset on injected channels - - (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at - slower speed. - - (#) ADC input range: from Vref– (connected to Vssa) to Vref+ (connected to - Vdda or to an external voltage reference). - - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Enable the ADC interface - As prerequisite, ADC clock must be configured at RCC top level. - Two clocks settings are mandatory: - - ADC clock (core clock): - Example: - Into HAL_ADC_MspInit() (recommended code location): - __ADC1_CLK_ENABLE(); - - - ADC clock (conversions clock): - Only one possible clock source: derived from HSI RC 16MHz oscillator - (HSI). - Example: - Into HAL_ADC_MspInit() or with main setting of RCC: - RCC_OscInitTypeDef RCC_OscInitStructure; - HAL_RCC_GetOscConfig(&RCC_OscInitStructure); - RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); - RCC_OscInitStructure.HSIState = RCC_HSI_ON; - RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStructure.PLL.PLLSource = ... - RCC_OscInitStructure.PLL... - HAL_RCC_OscConfig(&RCC_OscInitStructure); - - Note: ADC is connected directly to HSI RC 16MHz oscillator. - Therefore, RCC PLL setting has no impact on ADC. - PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or - enabled with HSI16 as clock source - (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device - main clock source SYSCLK. - The only mandatory setting is ".HSIState = RCC_HSI_ON" - - Note: ADC clock prescaler is configured at ADC level with - parameter "ClockPrescaler" using function HAL_ADC_Init(). - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); - - (#) Configure the ADC parameters (conversion resolution, data alignment, - continuous mode, ...) using the HAL_ADC_Init() function. - - (#) Activate the ADC peripheral using one of the start functions: - HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(). - - *** Channels configuration to regular group *** - ================================================ - [..] - (+) To configure the ADC regular group features, use - HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. - (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. - - *** DMA for regular group configuration *** - =========================================== - [..] - (+) To enable the DMA mode for regular group, use the - HAL_ADC_Start_DMA() function. - (+) To enable the generation of DMA requests continuously at the end of - the last DMA transfer, use the HAL_ADC_Init() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ - - /* Fixed timeout values for ADC calibration, enable settling time. */ - /* Values defined to be higher than worst cases: low clocks freq, */ - /* maximum prescaler. */ - /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ - /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ - /* Unit: ms */ - #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) - #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) - - /* Delay for ADC stabilization time. */ - /* Maximum delay is 3.5us (refer to device datasheet, parameter tSTAB). */ - /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */ - /* have the minimum number of CPU cycles to fulfill this delay. */ - #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)112) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC -@endverbatim - * @{ - */ - -/** - * @brief Initializes the ADC peripheral and regular group according to - * parameters specified in structure "ADC_InitTypeDef". - * @note As prerequisite, ADC clock must be configured at RCC top level - * (clock source APB2). - * See commented example code below that can be copied and uncommented - * into HAL_ADC_MspInit(). - * @note Possibility to update parameters on the fly: - * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when - * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC - * MSP has to be modified again, HAL_ADC_DeInit() must be called - * before HAL_ADC_Init(). - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments - * of structure "ADC_InitTypeDef". - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - uint32_t tmp_cr1 = 0; - uint32_t tmp_cr2 = 0; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); - assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); - assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait)); - assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff)); - assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - { - assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); - } - - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - } - - - /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ - /* at RCC top level. */ - /* Refer to header of this file for more details on clock enabling */ - /* procedure. */ - - /* Actions performed only if ADC is coming from state reset: */ - /* - Initialization of ADC MSP */ - if (hadc->State == HAL_ADC_STATE_RESET) - { - /* Enable SYSCFG clock to control the routing Interface (RI) */ - __SYSCFG_CLK_ENABLE(); - - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); - } - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (tmpHALStatus != HAL_ERROR) - { - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; - - /* Set ADC parameters */ - - /* Configuration of common ADC clock: clock source HSI with selectable */ - /* prescaler */ - MODIFY_REG(ADC->CCR , - ADC_CCR_ADCPRE , - hadc->Init.ClockPrescaler ); - - /* Configuration of ADC: */ - /* - external trigger polarity */ - /* - End of conversion selection */ - /* - DMA continuous request */ - /* - Channels bank (Banks availability depends on devices categories) */ - /* - continuous conversion mode */ - tmp_cr2 |= (hadc->Init.DataAlign | - hadc->Init.EOCSelection | - __ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) | - hadc->Init.ChannelsBank | - __ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) ); - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - tmp_cr2 |= ( hadc->Init.ExternalTrigConv | - hadc->Init.ExternalTrigConvEdge ); - } - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - delay selection (LowPowerAutoWait mode) */ - /* - resolution */ - /* - auto power off (LowPowerAutoPowerOff mode) */ - /* - scan mode */ - /* - discontinuous mode disable/enable */ - /* - discontinuous mode number of conversions */ - if ((__HAL_ADC_IS_ENABLED(hadc) == RESET)) - { - tmp_cr2 |= hadc->Init.LowPowerAutoWait; - - tmp_cr1 |= (hadc->Init.Resolution | - hadc->Init.LowPowerAutoPowerOff | - __ADC_CR1_SCAN(hadc->Init.ScanConvMode) ); - - /* Enable discontinuous mode only if continuous mode is disabled */ - if ((hadc->Init.DiscontinuousConvMode == ENABLE) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* Enable discontinuous mode of regular group */ - /* Set the number of channels to be converted in discontinuous mode */ - tmp_cr1 |= ((ADC_CR1_DISCEN) | - __ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)); - } - - /* Update ADC configuration register CR1 with previous settings */ - MODIFY_REG(hadc->Instance->CR1, - ADC_CR1_RES | - ADC_CR1_PDI | - ADC_CR1_PDD | - ADC_CR1_DISCNUM | - ADC_CR1_DISCEN | - ADC_CR1_SCAN , - tmp_cr1 ); - } - - /* Update ADC configuration register CR2 with previous settings */ - MODIFY_REG(hadc->Instance->CR2 , - __ADC_CR2_MASK_ADCINIT() , - tmp_cr2 ); - - /* Configuration of regular group sequencer: */ - /* - if scan mode is disabled, regular channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ - /* Parameter "NbrOfConversion" is discarded. */ - /* Note: Scan mode is present by hardware on this device and, if */ - /* disabled, discards automatically nb of conversions. Anyway, nb of */ - /* conversions is forced to 0x00 for alignment over all STM32 devices. */ - /* - if scan mode is enabled, regular channels sequence length is set to */ - /* parameter "NbrOfConversion" */ - if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - { - MODIFY_REG(hadc->Instance->SQR1 , - ADC_SQR1_L , - __ADC_SQR1_L(hadc->Init.NbrOfConversion) ); - } - else - { - MODIFY_REG(hadc->Instance->SQR1, - ADC_SQR1_L , - 0x00000000 ); - } - - /* Check back that ADC registers have effectively been configured to */ - /* ensure of no potential problem of ADC core IP clocking. */ - /* Check through register CR2 (excluding execution control bits ADON, */ - /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */ - if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON | - ADC_CR2_SWSTART | ADC_CR2_JSWSTART | - ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL )) - == tmp_cr2) - { - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; - - tmpHALStatus = HAL_ERROR; - } - - } - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - tmpHALStatus = HAL_ERROR; - } - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Deinitialize the ADC peripheral registers to its default reset values. - * @note To not impact other ADCs, reset of common ADC registers have been - * left commented below. - * If needed, the example code can be copied and uncommented into - * function HAL_ADC_MspDeInit(). - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); - - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (tmpHALStatus != HAL_ERROR) - { - /* ========== Reset ADC registers ========== */ - /* Reset register SR */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | - ADC_FLAG_JSTRT | ADC_FLAG_STRT)); - - /* Reset register CR1 */ - CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | - ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD | - ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | - ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | - ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | - ADC_CR1_AWDCH )); - - /* Reset register CR2 */ - __ADC_CR2_CLEAR(hadc); - - /* Reset register SMPR0 */ - __ADC_SMPR0_CLEAR(hadc); - - /* Reset register SMPR1 */ - CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | - ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | - ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | - ADC_SMPR1_SMP20 )); - - /* Reset register SMPR2 */ - CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | - ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | - ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | - ADC_SMPR2_SMP10 )); - - /* Reset register SMPR3 */ - CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | - ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | - ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 | - ADC_SMPR3_SMP0 )); - - /* Reset register JOFR1 */ - CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); - /* Reset register JOFR2 */ - CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); - /* Reset register JOFR3 */ - CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); - /* Reset register JOFR4 */ - CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); - - /* Reset register HTR */ - CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); - /* Reset register LTR */ - CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); - - /* Reset register SQR1 */ - CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX)); - - /* Reset register SQR2 */ - CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | - ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 )); - - /* Reset register SQR3 */ - CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | - ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 )); - - /* Reset register SQR4 */ - CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | - ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 )); - - /* Reset register SQR5 */ - CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | - ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )); - - - /* Reset register JSQR */ - CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | - ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); - - /* Reset register JSQR */ - CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | - ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); - - /* Reset register DR */ - /* bits in access mode read only, no direct reset applicable*/ - - /* Reset registers JDR1, JDR2, JDR3, JDR4 */ - /* bits in access mode read only, no direct reset applicable*/ - - /* Reset register CCR */ - CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE); - - /* ========== Hard reset ADC peripheral ========== */ - /* Performs a global reset of the entire ADC peripheral: ADC state is */ - /* forced to a similar state after device power-on. */ - /* If needed, copy-paste and uncomment the following reset code into */ - /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ - /* */ - /* __ADC1_FORCE_RESET() */ - /* __ADC1_RELEASE_RESET() */ - - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Initializes the ADC MSP. - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitializes the ADC MSP. - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspDeInit must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular group. - (+) Stop conversion of regular group. - (+) Poll for conversion complete on regular group. - (+) Poll for conversion event. - (+) Get result of regular channel conversion. - (+) Start conversion of regular group and enable interruptions. - (+) Stop conversion of regular group and disable interruptions. - (+) Handle ADC interrupt request - (+) Start conversion of regular group and enable DMA transfer. - (+) Stop conversion of regular group and disable ADC DMA transfer. -@endverbatim - * @{ - */ - -/** - * @brief Enables ADC, starts conversion of regular group. - * Interruptions enabled in this function: None. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* State machine update: Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - } - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Start conversion of regular group if software start has been selected. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) - { - /* Start ADC conversion on regular group */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing interruption of potential - * conversion on injected group. If injected group is under use, it - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Wait for regular group conversion to be completed. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait until End of Conversion flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - } - - /* Clear end of conversion flag of regular group if low power feature "Auto */ - /* Wait" is disabled, to not interfere with this feature until data */ - /* register is read using function HAL_ADC_GetValue(). */ - if (hadc->Init.LowPowerAutoWait == DISABLE) - { - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - } - - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - /* Check if a conversion is ready on injected group */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Poll for conversion event. - * @param hadc: ADC handle - * @param EventType: the ADC event type. - * This parameter can be one of the following values: - * @arg AWD_EVENT: ADC Analog watchdog event. - * @arg OVR_EVENT: ADC Overrun event - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EVENT_TYPE(EventType)); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Check selected event flag */ - while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - } - - switch(EventType) - { - /* Analog watchdog (level out of window) event */ - case AWD_EVENT: - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - break; - - /* Overrun event */ - default: /* Case OVR_EVENT */ - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to overrun */ - hadc->ErrorCode |= HAL_ADC_ERROR_OVR; - - /* Clear ADC Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - break; - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Enables ADC, starts conversion of regular group with interruption. - * Interruptions enabled in this function: EOC (end of conversion), - * overrun. - * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* State machine update: Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - } - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable end of conversion interrupt for regular group */ - __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); - - /* Start conversion of regular group if software start has been selected. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) - { - /* Start ADC conversion on regular group */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); - } - - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable interrution of - * end-of-conversion, disable ADC peripheral. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Disable ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Enables ADC, starts conversion of regular group and transfers result - * through DMA. - * Interruptions enabled in this function: - * overrun, DMA half transfer, DMA transfer complete. - * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. - * @retval None - */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* State machine update: Check if an injected conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - } - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Enable ADC DMA mode */ - hadc->Instance->CR2 |= ADC_CR2_DMA; - - /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Start conversion of regular group if software start has been selected. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Note: Alternate trigger for single conversion could be to force an */ - /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ - if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc)) - { - /* Start ADC conversion on regular group */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable - * ADC peripheral. - * @note: ADC peripheral disable is forcing interruption of potential - * conversion on injected group. If injected group is under use, it - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Disable ADC DMA mode */ - hadc->Instance->CR2 &= ~ADC_CR2_DMA; - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* DMA transfer is on going) */ - tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Get ADC regular group conversion result. - * @param hadc: ADC handle - * @retval Converted value - */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Note: EOC flag is not cleared here by software because automatically */ - /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ - return hadc->Instance->DR; -} - -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - /* Check if a conversion is ready on injected group */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } - } - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Half conversion callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - - /* Error callback */ - HAL_ADC_ErrorCallback(hadc); -} - -/** - * @brief Handles ADC interrupt request - * @param hadc: ADC handle - * @retval None - */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - - - /* ========== Check End of Conversion flag for regular group ========== */ - if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) - { - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - /* Check if a conversion is ready on injected group */ - if(hadc->State == HAL_ADC_STATE_EOC_INJ) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } - } - } - - /* Disable interruption if no further conversion upcoming regular */ - /* external trigger or by continuous mode */ - if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* Disable ADC end of single conversion interrupt */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used by */ - /* overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - } - } - - /* ========== Check End of Conversion flag for injected group ========== */ - if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) - { - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - - if(hadc->State == HAL_ADC_STATE_EOC_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ; - } - } - } - - /* Disable interruption if no further conversion upcoming injected */ - /* external trigger or by automatic injected conversion with regular */ - /* group having no further conversion upcoming (same conditions as */ - /* regular group interruption disabling above). */ - if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) || - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) - { - /* Disable ADC end of single conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - } - - /* Conversion complete callback */ - HAL_ADCEx_InjectedConvCpltCallback(hadc); - - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); - } - } - - /* ========== Check Analog watchdog flags ========== */ - if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; - - /* Clear the ADCx's Analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD); - - /* Level out of window callback */ - HAL_ADC_LevelOutOfWindowCallback(hadc); - } - } - - /* ========== Check Overrun flag ========== */ - if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR)) - { - /* Change ADC state to error state */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to overrun */ - hadc->ErrorCode |= HAL_ADC_ERROR_OVR; - - /* Error callback */ - HAL_ADC_ErrorCallback(hadc); - - /* Clear the Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - } - -} - -/** - * @brief Conversion complete callback in non blocking mode - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Conversion DMA half-transfer callback in non blocking mode - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog callback in non blocking mode. - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) -{ - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. - */ -} - -/** - * @brief ADC error callback in non blocking mode - * (ADC conversion with interruption or transfer by DMA) - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) -{ - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ErrorCallback must be implemented in the user file. - */ -} - - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on regular group - (+) Configure the analog watchdog - -@endverbatim - * @{ - */ - -/** - * @brief Configures the the selected channel to be linked to the regular - * group. - * @note In case of usage of internal measurement channels: - * Vbat/VrefInt/TempSensor. - * These internal paths can be be disabled using function - * HAL_ADC_DeInit(). - * @note Possibility to update parameters on the fly: - * This function initializes channel into regular group, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting - * the ADC. - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_ChannelConfTypeDef". - * @param hadc: ADC handle - * @param sConfig: Structure of ADC channel for regular group. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - - /* Process locked */ - __HAL_LOCK(hadc); - - - /* Regular sequence configuration */ - /* For Rank 1 to 6 */ - if (sConfig->Rank < 7) - { - MODIFY_REG(hadc->Instance->SQR5, - __ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), - __ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 7 to 12 */ - else if (sConfig->Rank < 13) - { - MODIFY_REG(hadc->Instance->SQR4, - __ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), - __ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 13 to 18 */ - else if (sConfig->Rank < 19) - { - MODIFY_REG(hadc->Instance->SQR3, - __ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), - __ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 19 to 24 */ - else if (sConfig->Rank < 25) - { - MODIFY_REG(hadc->Instance->SQR2, - __ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), - __ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); - } - /* For Rank 25 to 28 */ - else - { - MODIFY_REG(hadc->Instance->SQR1, - __ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), - __ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); - } - - - /* Channel sampling time configuration */ - /* For channels 0 to 9 */ - if (sConfig->Channel < ADC_CHANNEL_10) - { - MODIFY_REG(hadc->Instance->SMPR3, - __ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), - __ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); - } - /* For channels 10 to 19 */ - else if (sConfig->Channel < ADC_CHANNEL_20) - { - MODIFY_REG(hadc->Instance->SMPR2, - __ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), - __ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); - } - /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ - /* For channels 20 to 29 for devices Cat4, Cat.5 */ - else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX) - { - MODIFY_REG(hadc->Instance->SMPR1, - __ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), - __ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); - } - /* For channels 30 to 31 for devices Cat4, Cat.5 */ - else - { - __ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); - } - - /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ - /* and VREFINT measurement path. */ - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || - (sConfig->Channel == ADC_CHANNEL_VREFINT) ) - { - SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Configures the analog watchdog. - * @param hadc: ADC handle - * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); - - if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) - { - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Analog watchdog configuration */ - - /* Configure ADC Analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) - { - /* Enable the ADC Analog watchdog interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); - } - else - { - /* Disable the ADC Analog watchdog interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); - } - - /* Configuration of analog watchdog: */ - /* - Set the analog watchdog enable mode: regular and/or injected groups, */ - /* one or all channels. */ - /* - Set the Analog watchdog channel (is not used if watchdog */ - /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ - hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL | - ADC_CR1_JAWDEN | - ADC_CR1_AWDEN | - ADC_CR1_AWDCH ); - - hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode | - AnalogWDGConfig->Channel ); - - /* Set the high threshold */ - hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; - - /* Set the low threshold */ - hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ - - -/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions to get in run-time the status of the - peripheral. - (+) Check the ADC state - (+) Check the ADC error code - -@endverbatim - * @{ - */ - -/** - * @brief return the ADC state - * @param hadc: ADC handle - * @retval HAL state - */ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc) -{ - /* Return ADC state */ - return hadc->State; -} - -/** - * @brief Return the ADC error code - * @param hadc: ADC handle - * @retval ADC Error Code - */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) -{ - return hadc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @brief Enable the selected ADC. - * @note Prerequisite condition to use this function: ADC must be disabled - * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) -{ - uint32_t wait_loop_index = 0; - uint32_t tickstart = 0; - - /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ - /* enabling phase not yet completed: flag ADC ready not yet set). */ - /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ - /* causes: ADC clock not running, ...). */ - if (__HAL_ADC_IS_ENABLED(hadc) == RESET) - { - /* Enable the Peripheral */ - __ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time. */ - /* Delay fixed to worst case: maximum CPU frequency */ - while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES) - { - wait_loop_index++; - } - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait for ADC effectively enabled */ - while(__HAL_ADC_IS_ENABLED(hadc) == RESET) - { - if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT) - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief Stop ADC conversion and disable the selected ADC - * @note Prerequisite condition to use this function: ADC conversions must be - * stopped to disable the ADC. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) -{ - uint32_t tickstart = 0; - - /* Verification if ADC is not already disabled: */ - if (__HAL_ADC_IS_ENABLED(hadc) != RESET) - { - /* Disable the ADC peripheral */ - __ADC_DISABLE(hadc); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait for ADC effectively disabled */ - while(__HAL_ADC_IS_ENABLED(hadc) != RESET) - { - if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT) - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; - - return HAL_ERROR; - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c deleted file mode 100644 index 58970b543..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c +++ /dev/null @@ -1,849 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_adc_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) - * peripheral: - * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Analog Watchdog configuration - * ++ Channels configuration on regular group - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management - * Other functions (generic functions) are available in file - * "stm32l1xx_hal_adc.c". - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Activate the ADC peripheral using one of the start functions: - HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(). - - *** Channels configuration to injected group *** - ================================================ - [..] - (+) To configure the ADC Injected channels group features, use - HAL_ADCEx_InjectedConfigChannel() functions. - (+) To activate the continuous mode, use the HAL_ADC_Init() function. - (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup ADCEx ADCEx - * @brief ADC HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ADCEx_Private_Constants ADCEx Private Constants - * @{ - */ - - /* ADC conversion cycles (unit: ADC clock cycles) */ - /* (selected sampling time + conversion time of 12 ADC clock cycles, with */ - /* resolution 12 bits) */ - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5 ((uint32_t) 16) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES ((uint32_t) 21) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES ((uint32_t) 28) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES ((uint32_t) 36) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES ((uint32_t) 60) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES ((uint32_t)108) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES ((uint32_t)204) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES ((uint32_t)396) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions - * @{ - */ - -/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions - * @brief Extended Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of injected group. - (+) Stop conversion of injected group. - (+) Poll for conversion complete on injected group. - (+) Get result of injected channel conversion. - (+) Start conversion of injected group and enable interruptions. - (+) Stop conversion of injected group and disable interruptions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables ADC, starts conversion of injected group. - * Interruptions enabled in this function: None. - * @param hadc: ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Check if a regular conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ; - } - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Start conversion of injected group if software start has been selected */ - /* and if automatic injected conversion is disabled. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* If automatic injected conversion is enabled, conversion will start */ - /* after next regular group conversion. */ - if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Enable ADC software conversion for injected channels */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Stop conversion of injected channels. Disable ADC peripheral if - * no regular conversion is on going. - * @note If ADC must be disabled with this function and if regular conversion - * is on going, function HAL_ADC_Stop must be used preliminarily. - * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if((hadc->State != HAL_ADC_STATE_BUSY_REG) && - (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - } - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - tmpHALStatus = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Wait for injected group conversion to be completed. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Variables for polling in case of scan mode enabled and polling for each */ - /* conversion. */ - /* Note: Variable "conversion_timeout_cpu_cycles" set to offset 28 CPU */ - /* cycles to compensate number of CPU cycles for processing of variable */ - /* "conversion_timeout_cpu_cycles_max" */ - uint32_t conversion_timeout_cpu_cycles = 28; - uint32_t conversion_timeout_cpu_cycles_max = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Polling for end of conversion: differentiation if single/sequence */ - /* conversion. */ - /* For injected group, flag JEOC is set only at the end of the sequence, */ - /* not for each conversion within the sequence. */ - /* If setting "EOCSelection" is set to poll for each single conversion, */ - /* management of polling depends on setting of injected group sequencer: */ - /* - If single conversion for injected group (scan mode disabled or */ - /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ - /* conversion completion. */ - /* - If sequence conversion for injected group (scan mode enabled and */ - /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ - /* sequence. */ - /* To poll for each conversion, the maximum conversion time is computed */ - /* from ADC conversion time (selected sampling time + conversion time of */ - /* 12 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ - /* settings, conversion time range can vary from 8 to several thousands */ - /* of CPU cycles). */ - - /* Note: On STM32L1, setting "EOCSelection" is related to regular group */ - /* only, by hardware. For compatibility with other STM32 devices, */ - /* this setting is related also to injected group by software. */ - if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) || - (hadc->Init.EOCSelection != EOC_SINGLE_CONV) ) - { - /* Wait until End of Conversion flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - } - } - else - { - /* Computation of CPU cycles corresponding to ADC conversion cycles. */ - /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ - /* channels. */ - conversion_timeout_cpu_cycles_max = __ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc); - conversion_timeout_cpu_cycles_max *= __ADC_CONVCYCLES_MAX_RANGE(hadc); - - /* Poll with maximum conversion time */ - while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - conversion_timeout_cpu_cycles ++; - } - } - - /* Clear end of conversion flag of injected group if low power feature */ - /* "Auto Wait" is disabled, to not interfere with this feature until data */ - /* register is read using function HAL_ADCEx_InjectedGetValue(). */ - if (hadc->Init.LowPowerAutoWait == DISABLE) - { - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); - } - - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Update ADC state machine */ - if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) - { - - if(hadc->State == HAL_ADC_STATE_EOC_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_INJ; - } - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Enables ADC, starts conversion of injected group with interruption. - * Interruptions enabled in this function: JEOC (end of conversion). - * Each of these interruptions has its dedicated callback function. - * @param hadc: ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Check if a regular conversion is ongoing */ - if(hadc->State == HAL_ADC_STATE_BUSY_REG) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; - } - else - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_INJ; - } - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Enable end of conversion interrupt for injected channels */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - - /* Start conversion of injected group if software start has been selected */ - /* and if automatic injected conversion is disabled. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* If automatic injected conversion is enabled, conversion will start */ - /* after next regular group conversion. */ - if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Enable ADC software conversion for injected channels */ - SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Stop conversion of injected channels, disable interruption of - * end-of-conversion. Disable ADC peripheral if no regular conversion - * is on going. - * @note If ADC must be disabled with this function and if regular conversion - * is on going, function HAL_ADC_Stop must be used preliminarily. - * @param hadc: ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if((hadc->State != HAL_ADC_STATE_BUSY_REG) && - (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - tmpHALStatus = ADC_ConversionStop_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) - { - /* Disable ADC end of conversion interrupt for injected channels */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - } - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - tmpHALStatus = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @brief Get ADC injected group conversion result. - * @param hadc: ADC handle - * @param InjectedRank: the converted ADC injected rank. - * This parameter can be one of the following values: - * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected - * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected - * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected - * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected - * @retval None - */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) -{ - uint32_t tmp_jdr = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - - /* Clear injected group conversion flag to have similar behaviour as */ - /* regular group: reading data register also clears end of conversion flag. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Get ADC converted value */ - switch(InjectedRank) - { - case ADC_INJECTED_RANK_4: - tmp_jdr = hadc->Instance->JDR4; - break; - case ADC_INJECTED_RANK_3: - tmp_jdr = hadc->Instance->JDR3; - break; - case ADC_INJECTED_RANK_2: - tmp_jdr = hadc->Instance->JDR2; - break; - case ADC_INJECTED_RANK_1: - default: - tmp_jdr = hadc->Instance->JDR1; - break; - } - - /* Return ADC converted value */ - return tmp_jdr; -} - -/** - * @brief Injected conversion complete callback in non blocking mode - * @param hadc: ADC handle - * @retval None - */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on injected group - -@endverbatim - * @{ - */ - -/** - * @brief Configures the ADC injected group and the selected channel to be - * linked to the injected group. - * @note Possibility to update parameters on the fly: - * This function initializes injected group, following calls to this - * function can be used to reconfigure some parameters of structure - * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. - * The setting of these parameters is conditioned to ADC state: - * this function must be called when ADC is not under conversion. - * @param hadc: ADC handle - * @param sConfigInjected: Structure of ADC injected group and ADC channel for - * injected group. - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) -{ - HAL_StatusTypeDef tmpHALStatus = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); - assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); - assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - { - assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); - assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); - } - - if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START) - { - assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Configuration of injected group sequencer: */ - /* - if scan mode is disabled, injected channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ - /* Parameter "InjectedNbrOfConversion" is discarded. */ - /* Note: Scan mode is present by hardware on this device and, if */ - /* disabled, discards automatically nb of conversions. Anyway, nb of */ - /* conversions is forced to 0x00 for alignment over all STM32 devices. */ - /* - if scan mode is enabled, injected channels sequence length is set to */ - /* parameter ""InjectedNbrOfConversion". */ - if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) - { - if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) - { - /* Clear the old SQx bits for all injected ranks */ - MODIFY_REG(hadc->Instance->JSQR , - ADC_JSQR_JL | - ADC_JSQR_JSQ4 | - ADC_JSQR_JSQ3 | - ADC_JSQR_JSQ2 | - ADC_JSQR_JSQ1 , - __ADC_JSQR_RK(sConfigInjected->InjectedChannel, - ADC_INJECTED_RANK_1, - 0x01) ); - } - /* If another injected rank than rank1 was intended to be set, and could */ - /* not due to ScanConvMode disabled, error is reported. */ - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - tmpHALStatus = HAL_ERROR; - } - } - else - { - /* Since injected channels rank conv. order depends on total number of */ - /* injected conversions, selected rank must be below or equal to total */ - /* number of injected conversions to be updated. */ - if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) - { - /* Clear the old SQx bits for the selected rank */ - /* Set the SQx bits for the selected rank */ - MODIFY_REG(hadc->Instance->JSQR , - - ADC_JSQR_JL | - __ADC_JSQR_RK(ADC_JSQR_JSQ1, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) , - - __ADC_JSQR_JL(sConfigInjected->InjectedNbrOfConversion) | - __ADC_JSQR_RK(sConfigInjected->InjectedChannel, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) ); - } - else - { - /* Clear the old SQx bits for the selected rank */ - MODIFY_REG(hadc->Instance->JSQR , - - ADC_JSQR_JL | - __ADC_JSQR_RK(ADC_JSQR_JSQ1, - sConfigInjected->InjectedRank, - sConfigInjected->InjectedNbrOfConversion) , - - 0x00000000 ); - } - } - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - - if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - { - MODIFY_REG(hadc->Instance->CR2 , - ADC_CR2_JEXTEN | - ADC_CR2_JEXTSEL , - sConfigInjected->ExternalTrigInjecConv | - sConfigInjected->ExternalTrigInjecConvEdge ); - } - else - { - MODIFY_REG(hadc->Instance->CR2, - ADC_CR2_JEXTEN | - ADC_CR2_JEXTSEL , - 0x00000000 ); - } - - /* Configuration of injected group */ - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - Automatic injected conversion */ - /* - Injected discontinuous mode */ - if ((__HAL_ADC_IS_ENABLED(hadc) == RESET)) - { - hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO | - ADC_CR1_JDISCEN ); - - /* Automatic injected conversion can be enabled if injected group */ - /* external triggers are disabled. */ - if (sConfigInjected->AutoInjectedConv == ENABLE) - { - if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - { - SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); - } - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - tmpHALStatus = HAL_ERROR; - } - } - - /* Injected discontinuous can be enabled only if auto-injected mode is */ - /* disabled. */ - if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) - { - if (sConfigInjected->AutoInjectedConv == DISABLE) - { - SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); - } - else - { - /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - - tmpHALStatus = HAL_ERROR; - } - } - } - - /* InjectedChannel sampling time configuration */ - /* For InjectedChannels 0 to 9 */ - if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10) - { - MODIFY_REG(hadc->Instance->SMPR3, - __ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel), - __ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); - } - /* For InjectedChannels 10 to 19 */ - else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20) - { - MODIFY_REG(hadc->Instance->SMPR2, - __ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel), - __ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); - } - /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ - /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */ - else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX) - { - MODIFY_REG(hadc->Instance->SMPR1, - __ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel), - __ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); - } - /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */ - else - { - __ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } - - - /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ - switch(sConfigInjected->InjectedRank) - { - case 1: - /* Set injected channel 1 offset */ - MODIFY_REG(hadc->Instance->JOFR1, - ADC_JOFR1_JOFFSET1, - sConfigInjected->InjectedOffset); - break; - case 2: - /* Set injected channel 2 offset */ - MODIFY_REG(hadc->Instance->JOFR2, - ADC_JOFR2_JOFFSET2, - sConfigInjected->InjectedOffset); - break; - case 3: - /* Set injected channel 3 offset */ - MODIFY_REG(hadc->Instance->JOFR3, - ADC_JOFR3_JOFFSET3, - sConfigInjected->InjectedOffset); - break; - case 4: - default: - MODIFY_REG(hadc->Instance->JOFR4, - ADC_JOFR4_JOFFSET4, - sConfigInjected->InjectedOffset); - break; - } - - /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ - /* and VREFINT measurement path. */ - if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || - (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) - { - SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmpHALStatus; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c deleted file mode 100644 index 3847a72e0..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c +++ /dev/null @@ -1,810 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_comp.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief COMP HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the COMP peripheral: - * + Initialization and de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim -================================================================================ - ##### COMP Peripheral features ##### -================================================================================ - - [..] - The STM32L1xx device family integrates 2 analog comparators COMP1 and - COMP2: - (#) The non inverting input and inverting input can be set to GPIO pins. - Refer to "table1. COMP Inputs" below. - HAL COMP driver configures the Routing Interface (RI) to connect the - selected I/O pins to comparator input. - Caution: Comparator COMP1 and ADC cannot be used at the same time as - ADC since they share the ADC switch matrix: COMP1 non-inverting - input is routed through ADC switch matrix. Except if ADC is intented - to measure voltage on COMP1 non-inverting input: it can be performed - on ADC channel VCOMP. - - (#) The COMP output is available using HAL_COMP_GetOutputLevel(). - - (#) The COMP output can be redirected to embedded timers (TIM2, TIM3, - TIM4, TIM10). - COMP output cannot be redirected to any I/O pin. - Refer to "table 2. COMP Outputs redirection to embedded timers" below. - - (#) The comparators COMP1 and COMP2 can be combined in window mode. - In this mode, COMP2 non inverting input is used as common - non-inverting input. - - (#) The 2 comparators have interrupt capability with wake-up - from Sleep and Stop modes (through the EXTI controller): - (++) COMP1 is internally connected to EXTI Line 21 - (++) COMP2 is internally connected to EXTI Line 22 - - From the corresponding IRQ handler, the right interrupt source can be - retrieved with macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: - (++) COMP_EXTI_LINE_COMP1_EVENT - (++) COMP_EXTI_LINE_COMP2_EVENT - - (#) The comparators also offer the possibility to ouput the voltage - reference (VrefInt), used on inverting inputs, on I/O pin through - a buffer. To use it, refer to macro "__HAL_VREFINT_OUT_ENABLE()". - - -[..] Table 1. COMP Inputs for the STM32L1xx devices - +----------------------------------------------------------------------+ - | | | COMP1 | COMP2 | - |-----------------|--------------------------------|---------|---------| - | | 1/4 VREFINT | -- | OK | - | | 1/2 VREFINT | -- | OK | - | | 3/4 VREFINT | -- | OK | - | Inverting | VREFINT | OK | OK | - | input | DAC Ch1 OUT (PA4) | -- | OK | - | | DAC Ch2 OUT (PA5) | -- | OK | - | | IO: PB3 | -- | OK | - |-----------------|--------------------------------|---------|---------| - | | IO: | | | - | | PB4, 5, 6*, 7* | --- | OK | - | Non-inverting | PA0*, 1*, 2*, 3*, 4, 5, 6, 7 | OK | --- | - | input | PB0, 1, 12, 13, 14, 15 | OK | --- | - | | PC0, 1, 2, 3, 4, 5 | OK | --- | - | | PE7, 8, 9, 10 | OK | --- | - | | PF6, 7, 8, 9, 10 | OK | --- | - | | OPAMP1 output | OK | --- | - | | OPAMP2 output | OK | --- | - | | OPAMP3 output** | OK | --- | - +----------------------------------------------------------------------+ - *: Available on devices category Cat.3, Cat.4, Cat.5 only. - **: Available on devices category Cat.4 only. - - [..] Table 2. COMP Outputs redirection to embedded timers - +-----------------------------------+ - | COMP1 | COMP2 | - |-----------------|-----------------| - | | TIM2 IC4 | - | | TIM2 OCREF CLR | - | (no redirection | TIM3 IC4 | - | to timers) | TIM3 OCREF CLR | - | | TIM4 IC4 | - | | TIM4 OCREF CLR | - | | TIM10 IC1 | - +-----------------------------------+ - - - ##### How to use this driver ##### -================================================================================ - [..] - This driver provides functions to configure and program the Comparators of all STM32L1xx devices. - - To use the comparator, perform the following steps: - - (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(). - (++) Configure the comparator input I/O pin using HAL_GPIO_Init(): - - For all inputs: I/O pin in analog mode (Schmitt trigger disabled) - - Possible alternate configuration, for non-inverting inputs of comparator 2: I/O pin in floating mode (Schmitt trigger enabled). - It is recommended to use analog configuration to avoid any overconsumption around VDD/2. - (++) Enable COMP Peripheral clock using macro __COMP_CLK_ENABLE() - (++) If required enable the COMP interrupt (EXTI line Interrupt): enable - the comparator interrupt vector using HAL_NVIC_EnableIRQ(COMP_IRQn) - and HAL_NVIC_SetPriority(COMP_IRQn, xxx, xxx) functions. - - (#) Configure the comparator using HAL_COMP_Init() function: - (++) Select the inverting input (COMP2 only) - (++) Select the non-inverting input - (++) Select the output redirection to timers (COMP2 only) - (++) Select the speed mode (COMP2 only) - (++) Select the window mode (related to COMP1 and COMP2, but selected - by COMP2 only) - (++) Select the pull-up/down resistors on non-inverting input (COMP1 only) - - (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() - function - - (#) If needed, use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback() - functions to manage comparator actions (output level or events) - - (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT() - function - - (#) De-initialize the comparator using HAL_COMP_DeInit() function - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup COMP COMP - * @brief COMP HAL module driver - * @{ - */ - -#ifdef HAL_COMP_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup COMP_Private_Constants COMP Private Constants - * @{ - */ - /* Delay for COMP startup time. */ - /* Maximum delay is 10us for comparator 1 and 25us for comparator 2 in slow */ - /* mode (refer to device datasheet, parameter tSTART). */ - /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */ - /* have the minimum number of CPU cycles to fulfill this delay. */ - /* - Comparator 1: delay minimum of 320 CPU cyles. Wait loop takes 3 CPU */ - /* cycles per iteration, therefore total wait iterations */ - /* number must be initialized at 106 iterations. */ - /* - Comparator 2: delay minimum of 800 CPU cyles. Wait loop takes 3 CPU */ - /* cycles per iteration, therefore total wait iterations */ - /* number must be initialized at 266 iterations. */ -#define COMP1_START_DELAY_CPU_CYCLES ((uint32_t)106) -#define COMP2_START_DELAY_CPU_CYCLES ((uint32_t)266) - - /* Comparator status "locked": to update COMP handle state (software lock */ - /* only on COMP of STM32L1xx devices) by bitfield: */ - /* states HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_BUSY_LOCKED. */ -#define COMP_STATE_BIT_LOCK ((uint32_t) 0x00000010) - -/** - * @} - */ - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup COMP_Exported_Functions COMP Exported Functions - * @{ - */ - -/** @defgroup COMP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions to initialize and de-initialize comparators - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the COMP according to the specified - * parameters in the COMP_InitTypeDef and create the associated handle. - * @note If the selected comparator is locked, initialization can't be performed. - * To unlock the configuration, perform a system reset. - * @param hcomp: COMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - if (hcomp->Instance == COMP1) - { - assert_param(IS_COMP_NONINVERTINGINPUTPULL(hcomp->Init.NonInvertingInputPull)); - } - else /* if (hcomp->Instance == COMP2) */ - { - assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput)); - assert_param(IS_COMP_OUTPUT(hcomp->Init.Output)); - assert_param(IS_COMP_MODE(hcomp->Init.Mode)); - assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); - } - - /* In window mode, non-inverting inputs of the 2 comparators are */ - /* connected together and are using inputs of COMP2 only. If COMP1 is */ - /* selected, this parameter is discarded. */ - if ((hcomp->Init.WindowMode == COMP_WINDOWMODE_DISABLED) || - (hcomp->Instance == COMP2) ) - { - assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput)); - } - - - /* Enable SYSCFG clock and the low level hardware to access comparators */ - if(hcomp->State == HAL_COMP_STATE_RESET) - { - /* Enable SYSCFG clock to control the routing Interface (RI) */ - __SYSCFG_CLK_ENABLE(); - - /* Init the low level hardware */ - HAL_COMP_MspInit(hcomp); - } - - /* Configuration of comparator: */ - /* - Output selection */ - /* - Inverting input selection */ - /* - Window mode */ - /* - Mode fast/slow speed */ - /* - Inverting input pull-up/down resistors */ - - /* Configuration depending on comparator instance */ - if (hcomp->Instance == COMP1) - { - MODIFY_REG(COMP->CSR, COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU, - hcomp->Init.NonInvertingInputPull ); - } - else /* if (hcomp->Instance == COMP2) */ - { - /* Note: If comparator 2 is not enabled, inverting input (parameter */ - /* "hcomp->Init.InvertingInput") is configured into function */ - /* "HAL_COMP_Start()" since inverting input selection also */ - /* enables the comparator 2. */ - /* If comparator 2 is already enabled, inverting input is */ - /* reconfigured on the fly. */ - if (__COMP_IS_ENABLED(hcomp) == RESET) - { - MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL | - COMP_CSR_WNDWE | - COMP_CSR_SPEED , - hcomp->Init.Output | - hcomp->Init.WindowMode | - hcomp->Init.Mode ); - } - else - { - MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL | - COMP_CSR_INSEL | - COMP_CSR_WNDWE | - COMP_CSR_SPEED , - hcomp->Init.Output | - hcomp->Init.InvertingInput | - hcomp->Init.WindowMode | - hcomp->Init.Mode ); - } - } - - /* Configure Routing Interface (RI) switches for comparator non-inverting */ - /* input. */ - /* Except in 2 cases: */ - /* - if non-inverting input has no selection: it can be the case for */ - /* COMP1 in window mode. */ - /* - particular case for PC3: if switch COMP1_SW1 is closed */ - /* (by macro "__HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1()" or */ - /* "__HAL_RI_SWITCH_COMP1_SW1_CLOSE()"), connection between pin PC3 */ - /* (or OPAMP3, if available) and COMP1 is done directly, without going */ - /* through ADC switch matrix. */ - if (__COMP_ROUTING_INTERFACE_TOBECONFIGURED(hcomp)) - { - if (hcomp->Instance == COMP1) - { - /* Enable the switch control mode */ - __HAL_RI_SWITCHCONTROLMODE_ENABLE(); - - /* Close the analog switch of ADC switch matrix to COMP1 (ADC */ - /* channel 26: Vcomp) */ - __HAL_RI_IOSWITCH_CLOSE(RI_IOSWITCH_VCOMP); - } - - /* Close the I/O analog switch corresponding to comparator */ - /* non-inverting input selected. */ - __HAL_RI_IOSWITCH_CLOSE(hcomp->Init.NonInvertingInput); - } - - - /* Initialize the COMP state*/ - if(hcomp->State == HAL_COMP_STATE_RESET) - { - hcomp->State = HAL_COMP_STATE_READY; - } - } - - return status; -} - - -/** - * @brief DeInitializes the COMP peripheral - * @note Deinitialization can't be performed if the COMP configuration is locked. - * To unlock the configuration, perform a system reset. - * @param hcomp: COMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - /* Reset configuration depending on comparator instance */ - if (hcomp->Instance == COMP1) - { - CLEAR_BIT(COMP->CSR , COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU); - } - else /* if (hcomp->Instance == COMP2) */ - { - CLEAR_BIT(COMP->CSR , COMP_CSR_OUTSEL | - COMP_CSR_WNDWE | - COMP_CSR_INSEL | - COMP_CSR_SPEED ); - } - - - /* Restore default state of Routing Interface (RI) switches for */ - /* comparator non-inverting input. */ - if (hcomp->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) - { - /* Open the I/O analog switch corresponding to comparator */ - /* non-inverting input selected. */ - __HAL_RI_IOSWITCH_OPEN(hcomp->Init.NonInvertingInput); - } - if (hcomp->Instance == COMP1) - { - /* Open the analog switch of ADC switch matrix to COMP1 (ADC */ - /* channel 26: Vcomp) */ - __HAL_RI_IOSWITCH_OPEN(RI_IOSWITCH_VCOMP); - - /* Disable the switch control mode */ - __HAL_RI_SWITCHCONTROLMODE_DISABLE(); - } - - - /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ - HAL_COMP_MspDeInit(hcomp); - - hcomp->State = HAL_COMP_STATE_RESET; - - /* Process unlocked */ - __HAL_UNLOCK(hcomp); - } - - return status; -} - -/** - * @brief Initializes the COMP MSP. - * @param hcomp: COMP handle - * @retval None - */ -__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_COMP_MspInit could be implenetd in the user file - */ -} - -/** - * @brief DeInitializes COMP MSP. - * @param hcomp: COMP handle - * @retval None - */ -__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_COMP_MspDeInit could be implenetd in the user file - */ -} - -/** - * @} - */ - -/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions - * @brief I/O operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the COMP - start and stop actions with or without interruption on ExtI line. - -@endverbatim - * @{ - */ - -/** - * @brief Start the comparator - * @param hcomp: COMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t wait_loop_cycles = 0; - __IO uint32_t wait_loop_index = 0; - - /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - if(hcomp->State == HAL_COMP_STATE_READY) - { - - /* Note: For comparator 2, inverting input (parameter */ - /* "hcomp->Init.InvertingInput") is configured into this */ - /* function instead of function "HAL_COMP_Init()" since */ - /* inverting input selection also enables the comparator 2. */ - __HAL_COMP_ENABLE(hcomp); - - /* Set delay for COMP startup time */ - if (hcomp->Instance == COMP1) - { - wait_loop_cycles = COMP1_START_DELAY_CPU_CYCLES; - } - else /* if (hcomp->Instance == COMP2) */ - { - wait_loop_cycles = COMP2_START_DELAY_CPU_CYCLES; - } - - /* Delay for COMP startup time. */ - /* Delay fixed to worst case: maximum CPU frequency */ - while(wait_loop_index < wait_loop_cycles) - { - wait_loop_index++; - } - - /* Update COMP state */ - hcomp->State = HAL_COMP_STATE_BUSY; - - } - else - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Stop the comparator - * @param hcomp: COMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - if(hcomp->State == HAL_COMP_STATE_BUSY) - { - /* Disable the selected comparator */ - __HAL_COMP_DISABLE(hcomp); - - /* Update COMP state */ - hcomp->State = HAL_COMP_STATE_READY; - } - else - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Enables the interrupt and starts the comparator - * @param hcomp: COMP handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t extiline = 0; - - status = HAL_COMP_Start(hcomp); - if(status == HAL_OK) - { - /* Check the parameter */ - assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); - - /* Get the Exti Line output configuration */ - extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); - - /* Configure the rising edge */ - /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_RISING or */ - /* COMP_TRIGGERMODE_IT_RISING_FALLING. */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET) - { - __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline); - } - else - { - __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline); - } - - /* Configure the falling edge */ - /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_FALLING or */ - /* COMP_TRIGGERMODE_IT_RISING_FALLING. */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET) - { - __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline); - } - else - { - __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline); - } - - /* Enable Exti interrupt mode */ - __HAL_COMP_EXTI_ENABLE_IT(extiline); - /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); - } - - return status; -} - -/** - * @brief Disable the interrupt and Stop the comparator - * @param hcomp: COMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the Exti Line interrupt mode */ - __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance)); - - status = HAL_COMP_Stop(hcomp); - - return status; -} - -/** - * @brief Comparator IRQ Handler - * @param hcomp: COMP handle - * @retval HAL status - */ -void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) -{ - uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); - - /* Check COMP Exti flag */ - if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET) - { - /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); - - /* COMP trigger user callback */ - HAL_COMP_TriggerCallback(hcomp); - } -} - -/** - * @} - */ - -/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the COMP - management functions: Lock status, comparator output level check, IRQ - callback (in case of usage of comparator with interruption on ExtI line). - -@endverbatim - * @{ - */ - -/** - * @brief Lock the selected comparator configuration. - * Caution: On STM32L1, HAL COMP lock is software lock only (not - * hardware lock as on some other STM32 devices) - * @param hcomp: COMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - /* Set lock flag */ - hcomp->State |= COMP_STATE_BIT_LOCK; - } - - return status; -} - -/** - * @brief Return the output level (high or low) of the selected comparator. - * The output level depends on the selected polarity. - * - Comparator output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is high when the non-inverting input is at a higher - * voltage than the inverting input - * @param hcomp: COMP handle - * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH. - * - */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) -{ - uint32_t level = 0; - - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - /* Read output level of the selected comparator */ - if(READ_BIT(COMP->CSR, __COMP_CSR_CMPXOUT(hcomp)) == RESET) - { - level = COMP_OUTPUTLEVEL_LOW; - } - else - { - level = COMP_OUTPUTLEVEL_HIGH; - } - - return(level); -} - -/** - * @brief Comparator callback. - * @param hcomp: COMP handle - * @retval None - */ -__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_COMP_TriggerCallback should be implemented in the user file - */ -} - - -/** - * @} - */ - -/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the COMP state - * @param hcomp : COMP handle - * @retval HAL state - */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) -{ - /* Check the COMP handle allocation */ - if(hcomp == NULL) - { - return HAL_COMP_STATE_RESET; - } - - /* Check the parameter */ - assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - return hcomp->State; -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_COMP_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c deleted file mode 100644 index 4aaa44978..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c +++ /dev/null @@ -1,441 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cortex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief CORTEX HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using Cortex HAL driver *** - =========================================================== - [..] - This section provide functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M3 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() - function according to the following table. - - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - ========================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ========================================================================================================================== - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() - - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest pre-emption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure Systick using Cortex HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for 1 msec interrupts. - - (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32l1xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provide the Cortex HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Sets the priority grouping field (pre-emption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) - * @param PreemptPriority: The pre-emption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK) functionalities. - - -@endverbatim - * @{ - */ - -/** - * @brief Gets the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c deleted file mode 100644 index 24fe2efd9..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c +++ /dev/null @@ -1,339 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_crc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief CRC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Cyclic Redundancy Check (CRC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The CRC HAL driver can be used as follows: - - (#) Enable CRC AHB clock using __CRC_CLK_ENABLE(); - - (#) Use HAL_CRC_Accumulate() function to compute the CRC value of - a 32-bit data buffer using combination of the previous CRC value - and the new one. - - (#) Use HAL_CRC_Calculate() function to compute the CRC Value of - a new 32-bit data buffer. This function resets the CRC computation - unit before starting the computation to avoid getting wrong CRC values. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup CRC CRC - * @brief CRC HAL module driver. - * @{ - */ - -#ifdef HAL_CRC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Functions CRC Exported Functions - * @{ - */ - -/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CRC according to the specified parameters - in the CRC_InitTypeDef and create the associated handle - (+) DeInitialize the CRC peripheral - (+) Initialize the CRC MSP - (+) DeInitialize CRC MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CRC according to the specified - * parameters in the CRC_InitTypeDef and creates the associated handle. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains - * the configuration information for CRC - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) -{ - /* Check the CRC handle allocation */ - if(hcrc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - - if(hcrc->State == HAL_CRC_STATE_RESET) - { - /* Init the low level hardware */ - HAL_CRC_MspInit(hcrc); - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the CRC peripheral. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains - * the configuration information for CRC - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) -{ - /* Check the CRC handle allocation */ - if(hcrc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_CRC_MspDeInit(hcrc); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hcrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRC MSP. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains - * the configuration information for CRC - * @retval None - */ -__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the CRC MSP. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains - * the configuration information for CRC - * @retval None - */ -__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Compute the 32-bit CRC value of 32-bit data buffer, - using combination of the previous CRC value and the new one. - (+) Compute the 32-bit CRC value of 32-bit data buffer, - independently of the previous CRC value. - -@endverbatim - * @{ - */ - -/** - * @brief Computes the 32-bit CRC of 32-bit data buffer using combination - * of the previous CRC value and the new one. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains - * the configuration information for CRC - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed (defined in word, 4 bytes) - * @retval 32-bit CRC - */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - /* Process Locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) - { - hcrc->Instance->DR = pBuffer[index]; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ - return hcrc->Instance->DR; -} - -/** - * @brief Computes the 32-bit CRC of 32-bit data buffer independently - * of the previous CRC value. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains - * the configuration information for CRC - * @param pBuffer: Pointer to the buffer containing the data to be computed - * @param BufferLength: Length of the buffer to be computed (defined in word, 4 bytes) - * @retval 32-bit CRC - */ -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - /* Process Locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC Calculation Unit */ - __HAL_CRC_DR_RESET(hcrc); - - /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) - { - hcrc->Instance->DR = pBuffer[index]; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ - return hcrc->Instance->DR; -} - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CRC state. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains - * the configuration information for CRC - * @retval HAL state - */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) -{ - return hcrc->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CRC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c deleted file mode 100644 index b7dedd2df..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c +++ /dev/null @@ -1,2111 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cryp.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief CRYP HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Cryptography (CRYP) peripheral: - * + Initialization and de-initialization functions - * + Processing functions by algorithm using polling mode - * + Processing functions by algorithm using interrupt mode - * + Processing functions by algorithm using DMA mode - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The CRYP HAL driver can be used as follows: - - (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE() - (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT()) - (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() - (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA()) - (+) Enable the DMA2 interface clock using - (++) __DMA2_CLK_ENABLE() - (+) Configure and enable two DMA Channels one for managing data transfer from - memory to peripheral (input channel) and another channel for managing data - transfer from peripheral to memory (output channel) - (+) Associate the initialized DMA handle to the CRYP DMA handle - using __HAL_LINKDMA() - (+) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - (++) HAL_NVIC_SetPriority() - (++) HAL_NVIC_EnableIRQ() - - (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly: - (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit - (##) The encryption/decryption key. - (##) The initialization vector (counter). It is not used ECB mode. - - (#)Three processing (encryption/decryption) functions are available: - (##) Polling mode: encryption and decryption APIs are blocking functions - i.e. they process the data and wait till the processing is finished - e.g. HAL_CRYP_AESCBC_Encrypt() - (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt - e.g. HAL_CRYP_AESCBC_Encrypt_IT() - (##) DMA mode: encryption and decryption APIs are not blocking functions - i.e. the data transfer is ensured by DMA - e.g. HAL_CRYP_AESCBC_Encrypt_DMA() - - (#)When the processing function is called for the first time after HAL_CRYP_Init() - the CRYP peripheral is initialized and processes the buffer in input. - At second call, the processing function performs an append of the already - processed buffer. - When a new data block is to be processed, call HAL_CRYP_Init() then the - processing function. - - (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -#ifdef HAL_CRYP_MODULE_ENABLED - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup CRYP CRYP - * @brief CRYP HAL module driver. - * @{ - */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Defines CRYP Private Defines - * @{ - */ - -#define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions CRYP Private Functions - * @{ - */ - -static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp); -static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector); -static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key); -static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout); -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAError(DMA_HandleTypeDef *hdma); -static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Functions CRYP Exported Functions - * @{ - */ - -/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CRYP according to the specified parameters - in the CRYP_InitTypeDef and creates the associated handle - (+) DeInitialize the CRYP peripheral - (+) Initialize the CRYP MSP - (+) DeInitialize CRYP MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CRYP according to the specified - * parameters in the CRYP_InitTypeDef and creates the associated handle. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) -{ - /* Check the CRYP handle allocation */ - if(hcryp == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); - - if(hcryp->State == HAL_CRYP_STATE_RESET) - { - /* Init the low level hardware */ - HAL_CRYP_MspInit(hcryp); - } - - /* Check if AES already enabled */ - if (HAL_IS_BIT_CLR(AES->CR, AES_CR_EN)) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the data type*/ - MODIFY_REG(AES->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - - /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Set the default CRYP phase */ - hcryp->Phase = HAL_CRYP_PHASE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */ - /* enabled is forbidden to avoid unpredictable AES behavior.*/ - - /* Return function status */ - return HAL_ERROR; - } - -} - -/** - * @brief DeInitializes the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) -{ - /* Check the CRYP handle allocation */ - if(hcryp == NULL) - { - return HAL_ERROR; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the default CRYP phase */ - hcryp->Phase = HAL_CRYP_PHASE_READY; - - /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; - - /* Disable the CRYP Peripheral Clock */ - __HAL_CRYP_DISABLE(); - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_CRYP_MspDeInit(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) -{ - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_CRYP_MspInit can be implemented in the user file */ -} - -/** - * @brief DeInitializes CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) -{ - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_CRYP_MspDeInit can be implemented in the user file */ -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions - * @brief processing functions. - * -@verbatim - ============================================================================== - ##### AES processing functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Encrypt plaintext using AES algorithm in different chaining modes - (+) Decrypt cyphertext using AES algorithm in different chaining modes - [..] Three processing functions are available: - (+) Polling mode - (+) Interrupt mode - (+) DMA mode - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CRYP peripheral in AES ECB encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Check that data aligned on u32 and Size multiple of 16*/ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if(hcryp->State != HAL_CRYP_STATE_RESET) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if(hcryp->State != HAL_CRYP_STATE_RESET) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR encryption mode - * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if(hcryp->State != HAL_CRYP_STATE_RESET) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if(hcryp->State != HAL_CRYP_STATE_RESET) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Cypher Data and Get Plain Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if(hcryp->State != HAL_CRYP_STATE_RESET) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Cypher Data and Get Plain Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR decryption mode - * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) -{ - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if initialization phase has already been performed */ - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY)) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CTR decryption mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Write Cypher Data and Get Plain Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Get the last input data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Get the last input data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pPlainData; - hcryp->pCrypOutBuffPtr = pCypherData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Get the last input data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Get the last input data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Get the last input data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; - hcryp->pCrypInBuffPtr = pCypherData; - hcryp->pCrypOutBuffPtr = pPlainData; - hcryp->CrypOutCount = Size; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CTR decryption mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); - - /* Get the last input data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr = 0, outputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr = 0, outputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) -{ - uint32_t inputaddr = 0, outputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pPlainData; - outputaddr = (uint32_t)pCypherData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr = 0, outputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr = 0, outputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits */ - CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) -{ - uint32_t inputaddr = 0, outputaddr = 0; - - /* Check that data aligned on u32 */ - if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) - { - /* Process Locked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_ERROR; - } - - /* Check if HAL_CRYP_Init has been called */ - if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcryp); - - inputaddr = (uint32_t)pCypherData; - outputaddr = (uint32_t)pPlainData; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions - * @brief DMA callback functions. - * -@verbatim - ============================================================================== - ##### DMA callback functions ##### - ============================================================================== - [..] This section provides DMA callback functions: - (+) DMA Input data transfer complete - (+) DMA Output data transfer complete - (+) DMA error - -@endverbatim - * @{ - */ - -/** - * @brief CRYP error callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ - __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) -{ - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_CRYP_ErrorCallback can be implemented in the user file - */ -} - -/** - * @brief Input transfer completed callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) -{ - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_CRYP_InCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Output transfer completed callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) -{ - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_CRYP_OutCpltCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler - * @brief CRYP IRQ handler. - * -@verbatim - ============================================================================== - ##### CRYP IRQ handler management ##### - ============================================================================== -[..] This section provides CRYP IRQ handler function. - -@endverbatim - * @{ - */ - -/** - * @brief This function handles CRYP interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) -{ - /* Check if error occurred*/ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_ERR) != RESET) - { - if (__HAL_CRYP_GET_FLAG(AES_FLAG_RDERR) != RESET) - { - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_RDERR); - } - - if (__HAL_CRYP_GET_FLAG(AES_FLAG_WRERR) != RESET) - { - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_WRERR); - } - - if (__HAL_CRYP_GET_FLAG(AES_FLAG_CCF) != RESET) - { - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); - } - - hcryp->State= HAL_CRYP_STATE_ERROR; - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - __HAL_CRYP_DISABLE_IT(AES_IT_ERR); - - HAL_CRYP_ErrorCallback(hcryp); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return; - } - - /* Check if computation complete interrupt was enabled*/ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_CC) != RESET) - { - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); - - CRYP_EncryptDecrypt_IT(hcryp); - } -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CRYP state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL state - */ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) -{ - return hcryp->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup CRYP_Private_Functions - * @{ - */ - -/** - * @brief IT function called under interruption context to continue encryption or decryption - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) -{ - uint32_t inputaddr = 0, outputaddr = 0; - - /* Get the last Output data adress */ - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - - /* Read the Output block from the Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - - /* Check if all input text is encrypted or decrypted */ - if(hcryp->CrypOutCount == 0) - { - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - __HAL_CRYP_DISABLE_IT(AES_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call computation complete callback */ - HAL_CRYPEx_ComputationCpltCallback(hcryp); - } - else /* Process the rest of input text */ - { - /* Get the last Intput data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } - return HAL_OK; -} -/** - * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable the DMA transfer for input request */ - CLEAR_BIT(AES->CR, AES_CR_DMAINEN); - - /* Call input data transfer complete callback */ - HAL_CRYP_InCpltCallback(hcryp); -} - -/** - * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit - in the DMACR register */ - CLEAR_BIT(AES->CR, AES_CR_DMAOUTEN); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(); - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call output data transfer complete callback */ - HAL_CRYP_OutCpltCallback(hcryp); -} - -/** - * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAError(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - hcryp->State= HAL_CRYP_STATE_ERROR; - HAL_CRYP_ErrorCallback(hcryp); -} - -/** - * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @note Key must be written as little endian. - * If Key pointer points at address n, - * n[15:0] contains key[96:127], - * (n+4)[15:0] contains key[64:95], - * (n+8)[15:0] contains key[32:63] and - * (n+12)[15:0] contains key[0:31] - * @retval None - */ -static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key) -{ - uint32_t keyaddr = (uint32_t)Key; - - AES->KEYR3 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES->KEYR2 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES->KEYR1 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES->KEYR0 = __REV(*(uint32_t*)(keyaddr)); -} - -/** - * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer - * @note Init Vector must be written as little endian. - * If Init Vector pointer points at address n, - * n[15:0] contains Vector[96:127], - * (n+4)[15:0] contains Vector[64:95], - * (n+8)[15:0] contains Vector[32:63] and - * (n+12)[15:0] contains Vector[0:31] - * @retval None - */ -static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) -{ - uint32_t ivaddr = (uint32_t)InitVector; - - AES->IVR3 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - AES->IVR2 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - AES->IVR1 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - AES->IVR0 = __REV(*(uint32_t*)(ivaddr)); -} - -/** - * @brief Process Data: Writes Input data in polling mode and reads the output data - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 16. - * @param Output: Pointer to the returned buffer - * @param Timeout: Specify Timeout value - * @retval None - */ -static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - uint32_t index = 0; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - for(index=0; (index < Ilength); index += 16) - { - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(AES->SR, AES_SR_CCF)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Change state */ - hcryp->State = HAL_CRYP_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - return HAL_TIMEOUT; - } - } - } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF); - - /* Read the Output block from the Data Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param inputaddr: address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16. - * @param outputaddr: address of the Output buffer - * @retval None - */ -static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) -{ - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; - /* Set the DMA error callback */ - hcryp->hdmain->XferErrorCallback = CRYP_DMAError; - - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; - /* Set the DMA error callback */ - hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&AES->DINR, Size/4); - - /* Enable the DMA Out DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&AES->DOUTR, outputaddr, Size/4); - - /* Enable In and Out DMA requests */ - SET_BIT(AES->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); -} - -/** - * @} - */ - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CRYP_MODULE_ENABLED */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c deleted file mode 100644 index 66db6dbb6..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c +++ /dev/null @@ -1,118 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cryp_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief CRYPEx HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Cryptography (CRYP) extension peripheral: - * + Computation completed callback. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -#ifdef HAL_CRYP_MODULE_ENABLED - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup CRYPEx CRYPEx - * @brief CRYP HAL Extended module driver. - * @{ - */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions - * @{ - */ - - -/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions. - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides callback functions: - (+) Computation completed. - -@endverbatim - * @{ - */ - -/** - * @brief Computation completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ComputationCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CRYP_MODULE_ENABLED */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c deleted file mode 100644 index 5746fec58..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c +++ /dev/null @@ -1,963 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dac.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Digital to Analog Converter (DAC) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * - @verbatim - ============================================================================== - ##### DAC Peripheral features ##### - ============================================================================== - [..] - *** DAC Channels *** - ==================== - [..] - The device integrates two 12-bit Digital Analog Converters that can - be used independently or simultaneously (dual mode): - (#) DAC channel1 with DAC_OUT1 (PA4) as output - (#) DAC channel2 with DAC_OUT2 (PA5) as output - - *** DAC Triggers *** - ==================== - [..] - Digital to Analog conversion can be non-triggered using DAC_Trigger_None - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. - [..] - Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7, TIM9 - (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) - - (#) Software using DAC_Trigger_Software - - *** DAC Buffer mode feature *** - =============================== - [..] - Each DAC channel integrates an output buffer that can be used to - reduce the output impedance, and to drive external loads directly - without having to add an external operational amplifier. - To enable, the output buffer use - sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - [..] - (@) Refer to the device datasheet for more details about output - impedance value with and without output buffer. - - *** DAC wave generation feature *** - =================================== - [..] - Both DAC channels can be used to generate - (#) Noise wave - (#) Triangle wave - - *** DAC data format *** - ======================= - [..] - The DAC data format can be: - (#) 8-bit right alignment using DAC_ALIGN_8B_R - (#) 12-bit left alignment using DAC_ALIGN_12B_L - (#) 12-bit right alignment using DAC_ALIGN_12B_R - - *** DAC data value to voltage correspondence *** - ================================================ - [..] - The analog output voltage on each DAC channel pin is determined - by the following equation: - DAC_OUTx = VREF+ * DOR / 4095 - with DOR is the Data Output Register - VEF+ is the input voltage reference (refer to the device datasheet) - e.g. To set DAC_OUT1 to 0.7V, use - Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - - *** DMA requests *** - ===================== - [..] - A DMA1 request can be generated when an external trigger (but not - a software trigger) occurs if DMA1 requests are enabled using - HAL_DAC_Start_DMA() - [..] - DMA1 requests are mapped as following: - (#) DAC channel1 : mapped on DMA1 channel2 which must be - already configured - (#) DAC channel2 : mapped on DMA1 channel3 which must be - already configured - - -@- For Dual mode and specific signal (Triangle and noise) generation please - refer to Extension Features Driver description - - - ##### How to use this driver ##### - ============================================================================== - [..] - (+) DAC APB clock must be enabled to get write access to DAC - registers using HAL_DAC_Init() - (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. - (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. - (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the DAC peripheral using HAL_DAC_Start() - (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function. - (+) Stop the DAC peripheral using HAL_DAC_Stop() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DAC_ConvHalfCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2 - (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 - (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can - add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 - (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. - HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DAC_DMAUnderrunCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DAC_DMAUnderrunCallbackCh2 - add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 - (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() - - *** DAC HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DAC HAL driver. - - (+) __HAL_DAC_ENABLE : Enable the DAC peripheral - (+) __HAL_DAC_DISABLE : Disable the DAC peripheral - (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags - (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status - - [..] - (@) You can refer to the DAC HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup DAC DAC - * @brief DAC driver modules - * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DAC_Private_Functions DAC Private Functions - * @{ - */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); - -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Functions DAC Exported Functions - * @{ - */ - -/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DAC. - (+) De-initialize the DAC. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) -{ - /* Check DAC handle */ - if(hdac == NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - if(hdac->State == HAL_DAC_STATE_RESET) - { - /* Init the low level hardware */ - HAL_DAC_MspInit(hdac); - } - - /* Initialize the DAC state*/ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Set DAC error code to none */ - hdac->ErrorCode = HAL_DAC_ERROR_NONE; - - /* Initialize the DAC state*/ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) -{ - /* Check DAC handle */ - if(hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_DAC_MspDeInit(hdac); - - /* Set DAC error code to none */ - hdac->ErrorCode = HAL_DAC_ERROR_NONE; - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion. - (+) Stop conversion. - (+) Start conversion and enable DMA transfer. - (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. - -@endverbatim - * @{ - */ - -/** - * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the Peripharal */ - __HAL_DAC_ENABLE(hdac, Channel); - - if(Channel == DAC_CHANNEL_1) - { - tmp1 = hdac->Instance->CR & DAC_CR_TEN1; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; - /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) - { - /* Enable the selected DAC software conversion */ - SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); - } - } - else - { - tmp1 = hdac->Instance->CR & DAC_CR_TEN2; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; - /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) - { - /* Enable the selected DAC software conversion*/ - SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); - } - } - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected - * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected - * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_ALIGN(Alignment)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - if(Channel == DAC_CHANNEL_1) - { - /* Set the DMA transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - - /* Set the DMA half transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - - /* Set the DMA error callback for channel1 */ - hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - - /* Enable the selected DAC channel1 DMA request */ - SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - - /* Case of use of channel 1 */ - switch(Alignment) - { - case DAC_ALIGN_12B_R: - /* Get DHR12R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12R1; - break; - case DAC_ALIGN_12B_L: - /* Get DHR12L1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12L1; - break; - case DAC_ALIGN_8B_R: - /* Get DHR8R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR8R1; - break; - default: - break; - } - } - else - { - /* Set the DMA transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; - - /* Set the DMA half transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; - - /* Set the DMA error callback for channel2 */ - hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; - - /* Enable the selected DAC channel2 DMA request */ - SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - - /* Case of use of channel 2 */ - switch(Alignment) - { - case DAC_ALIGN_12B_R: - /* Get DHR12R2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12R2; - break; - case DAC_ALIGN_12B_L: - /* Get DHR12L2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12L2; - break; - case DAC_ALIGN_8B_R: - /* Get DHR8R2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR8R2; - break; - default: - break; - } - } - - /* Enable the DMA Stream */ - if(Channel == DAC_CHANNEL_1) - { - /* Enable the DAC DMA underrun interrupt */ - __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - } - else - { - /* Enable the DAC DMA underrun interrupt */ - __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); - } - - /* Enable the Peripharal */ - __HAL_DAC_ENABLE(hdac, Channel); - - /* Process Unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); - - /* Disable the Peripharal */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Disable the DMA Channel */ - /* Channel1 is used */ - if(Channel == DAC_CHANNEL_1) - { - status = HAL_DMA_Abort(hdac->DMA_Handle1); - } - else /* Channel2 is used for */ - { - status = HAL_DMA_Abort(hdac->DMA_Handle2); - } - - /* Check if DMA Channel effectively disabled */ - if(status != HAL_OK) - { - /* Update ADC state machine to error */ - hdac->State = HAL_DAC_STATE_ERROR; - } - else - { - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Returns the DAC channel data output register value */ - if(Channel == DAC_CHANNEL_1) - { - return hdac->Instance->DOR1; - } - else - { - return hdac->Instance->DOR2; - } -} - -/** - * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) -{ - /* Check underrun flag of DAC channel 1 */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to chanel1 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN1; - - /* Error callback */ - HAL_DAC_DMAUnderrunCallbackCh1(hdac); - } - - /* Check underrun flag of DAC channel 2 */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to channel2 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); - - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN2; - - /* Error callback */ - HAL_DACEx_DMAUnderrunCallbackCh2(hdac); - } -} - -/** - * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels. - (+) Set the specified data holding register value for DAC channel. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); - /* Configure for the selected DAC channel: buffer output, trigger */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; - /* Disable wave generation */ - DAC->CR &= ~(DAC_CR_WAVE1 << Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected - * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected - * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_ALIGN(Alignment)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)hdac->Instance; - if(Channel == DAC_CHANNEL_1) - { - tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment); - } - else - { - tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment); - } - - /* Set the DAC channel selected data holding register */ - *(__IO uint32_t *) tmp = Data; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DAC state. - (+) Check the DAC Errors. - -@endverbatim - * @{ - */ - -/** - * @brief return the DAC state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL state - */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) -{ - /* Return DAC state */ - return hdac->State; -} - - -/** - * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval DAC Error Code - */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) -{ - return hdac->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DAC_Private_Functions - * @{ - */ - -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DAC_ConvCpltCallbackCh1(hdac); - - hdac->State = HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DAC_ErrorCallbackCh1(hdac); - - hdac->State = HAL_DAC_STATE_READY; -} - -/** - * @} - */ - -#endif /* HAL_DAC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c deleted file mode 100644 index 39f6b0134..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c +++ /dev/null @@ -1,382 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dac_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of DAC extension peripheral: - * + Extended features functions - * - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : - Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. - (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. - (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup DACEx DACEx - * @brief DAC driver modules - * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DACEx_Exported_Functions DACEx Exported Functions - * @{ - */ - -/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - ============================================================================== - ##### Extended features functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion. - (+) Stop conversion. - (+) Start conversion and enable DMA transfer. - (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. - (+) Get result of dual mode conversion. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval The selected DAC channel data output value. - */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) -{ - uint32_t tmp = 0; - - tmp |= hdac->Instance->DOR1; - - tmp |= hdac->Instance->DOR2 << 16; - - /* Returns the DAC channel data output register value */ - return tmp; -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. - * This parameter can be one of the following values: - * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 - * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 - * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 - * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 - * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 - * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 - * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 - * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 - * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 - * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 - * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 - * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the selected wave generation for the selected DAC channel */ - hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel; - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. - * This parameter can be one of the following values: - * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation - * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the selected wave generation for the selected DAC channel */ - hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel; - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * DAC_ALIGN_8B_R: 8bit right data alignment selected - * DAC_ALIGN_12B_L: 12bit left data alignment selected - * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(Alignment)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (Alignment == DAC_ALIGN_8B_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)hdac->Instance; - tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment); - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup DACEx_Private_Functions DACEx Private Functions - * @{ - */ -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DACEx_ConvCpltCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DACEx_ErrorCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @} - */ - -#endif /* HAL_DAC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c deleted file mode 100644 index f71b6c78c..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c +++ /dev/null @@ -1,707 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dma.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is - necessary) please refer to Reference manual for connection between peripherals - and DMA requests . - - (#) For a given Channel, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular, Normal or peripheral flow control mode, Channel Priority level, - Source and Destination Increment mode, FIFO mode and its Threshold (if needed), - Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. In this - case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants -* @{ -*/ -#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ -/** - * @} - */ - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions -* @{ -*/ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Channel priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DMA according to the specified - * parameters in the DMA_InitTypeDef and create the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0; - - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Get the CR register value */ - tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ - DMA_CCR_DIR)); - - /* Prepare the DMA Channel configuration */ - tmp |= hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the DMA peripheral - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the DMA peripheral handle */ - if(hdma->State == HAL_DMA_STATE_BUSY) - { - return HAL_ERROR; - } - - /* Disable the selected DMA Channelx */ - __HAL_DMA_DISABLE(hdma); - - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; - - /* Reset DMA Channel Number of Data to Transfer register */ - hdma->Instance->CNDTR = 0; - - /* Reset DMA Channel peripheral address register */ - hdma->Instance->CPAR = 0; - - /* Reset DMA Channel memory address register */ - hdma->Instance->CMAR = 0; - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DMA_Group2 I/O operation functions - * @brief I/O operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Starts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Process locked */ - __HAL_LOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - - return HAL_OK; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Process locked */ - __HAL_LOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); - - /* Enable the Half transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); - - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - - return HAL_OK; -} - -/** - * @brief Aborts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * - * @note After disabling a DMA Channel, a check for wait until the DMA Channel is - * effectively disabled is added. If a Channel is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Channel will be effectively disabled only after the transfer of - * this single data is finished. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - uint32_t tickstart = 0x00; - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Check if the DMA Channel is effectively disabled */ - while((hdma->Instance->CCR & DMA_CCR_EN) != 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0x00; - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Transfer Complete flag */ - temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); - } - else - { - /* Half Transfer Complete flag */ - temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); - } - - /* Get timeout */ - tickstart = HAL_GetTick(); - - while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) - { - if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) - { - /* Clear the transfer error flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_TIMEOUT; - } - } - } - - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - } - else - { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY_HALF; - /* Process unlocked */ - __HAL_UNLOCK(hdma); - } - - return HAL_OK; -} - -/** - * @brief Handles DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - /* Transfer Error Interrupt management ***************************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) - { - /* Disable the transfer error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); - - /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - } - - /* Half Transfer Complete Interrupt management ******************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF; - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - } - - /* Transfer Complete Interrupt management ***********************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) - { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the transfer complete interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); - } - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } -} -} - -/** - * @} - */ - -/** @defgroup DMA_Group3 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Returns the DMA state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - return hdma->State; -} - -/** - * @brief Return the DMA error code - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions -* @{ -*/ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Configure DMA Channel data length */ - hdma->Instance->CNDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Channel destination address */ - hdma->Instance->CPAR = DstAddress; - - /* Configure DMA Channel source address */ - hdma->Instance->CMAR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Channel source address */ - hdma->Instance->CPAR = SrcAddress; - - /* Configure DMA Channel destination address */ - hdma->Instance->CMAR = DstAddress; - } -} - -/** - * @} - */ - - -#endif /* HAL_DMA_MODULE_ENABLED */ - - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c deleted file mode 100644 index 4e77a1384..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + FLASH Interface configuration - * + FLASH Memory Programming - * + Interrupts and flags management - * - * @verbatim - - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) Option Bytes programming - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the Flash - memory of all STM32L1xx devices. - - (#) FLASH Memory Programming functions: this group includes all - needed functions to erase and program the main memory: - (++) Lock and Unlock the Flash interface. - (++) Erase function: Erase Page. - (++) Program functions: Fast Word and Half Page(should be - executed from internal SRAM). - - (#) DATA EEPROM Programming functions: this group includes all - needed functions to erase and program the DATA EEPROM memory: - (++) Lock and Unlock the DATA EEPROM interface. - (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase - Double Word (should be executed from internal SRAM). - (++) Program functions: Fast Program Byte, Fast Program Half-Word, - FastProgramWord, Program Byte, Program Half-Word, - Program Word and Program Double-Word (should be executed - from internal SRAM). - - (#) FLASH Option Bytes Programming functions: this group includes - all needed functions to: - (++) Lock and Unlock the Flash Option bytes. - (++) Set/Reset the write protection. - (++) Set the Read protection Level. - (++) Set the BOR level. - (++) Program the user option Bytes. - (++) Launch the Option Bytes loader. - (++) Get the Write protection. - (++) Get the read protection status. - (++) Get the BOR level. - (++) Get the user option bytes. - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Wait for last FLASH operation according to its status - (++) Get error flag status by calling HAL_GetErrorCode() - - (#) FLASH Interface configuration functions: this group includes - the management of following features: - (++) Enable/Disable the RUN PowerDown mode. - (++) Enable/Disable the SLEEP PowerDown mode. - - (#) FLASH Peripheral State methods: this group includes - the management of following features: - (++) Wait for the FLASH operation - (++) Get the specific FLASH error flag - - [..] In addition to these function, this driver includes a set of macros allowing - to handle the following operations: - - (+) Set/Get the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the 64 bit Read Access. - (+) Enable/Disable the Flash power-down - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - - =============================================================================== - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - - [..] The FLASH Memory Programming functions, includes the following functions: - (+) HAL_FLASH_Unlock(void); - (+) HAL_FLASH_Lock(void); - (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) - (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) - - [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and - program memory access. - (#) Call the desired function to erase page or program data. - (#) Call the HAL_FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation). - - ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== - - [..] The FLASH_Option Bytes Programming_functions, includes the following functions: - (+) HAL_FLASH_OB_Unlock(void); - (+) HAL_FLASH_OB_Lock(void); - (+) HAL_FLASH_OB_Launch(void); - (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); - (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); - - [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control - register access. - (#) Call the following functions to program the desired option bytes. - (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); - (#) Once all needed option bytes to be programmed are correctly written, call the - HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. - (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended - to protect the option Bytes against possible unwanted operations). - - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @defgroup FLASH FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Internal_Variables FLASH Internal Variables - * @{ - */ - -/** - * @brief Variable used for Program/Erase sectors under interruption - */ -FLASH_ProcessTypeDef ProcFlash; - - -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Functions FLASH Exported functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim -@endverbatim - * @{ - */ -/** - * @brief Program word at a specified address - * @note To correctly run this function, the HAL_FLASH_Unlock() function - * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation). - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&ProcFlash); - - /* Check the parameters */ - assert_param(IS_TYPEPROGRAMFLASH(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /*Program word (32-bit) at a specified address.*/ - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - - return status; -} - -/** - * @brief Program word at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&ProcFlash); - - /* Check the parameters */ - assert_param(IS_TYPEPROGRAMFLASH(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); - - ProcFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - ProcFlash.Address = Address; - - if(TypeProgram == TYPEPROGRAM_WORD) - { - /*Program word (32-bit) at a specified address.*/ - *(__IO uint32_t *)Address = Data; - } - - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - - return status; -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Pages Erase: Sector which has been erased - * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * - Pagess Erase: Sector number which returned an error - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET) - { - /* Unlocking FLASH_PECR register access*/ - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) - { - FLASH->PEKEYR = FLASH_PEKEY1; - FLASH->PEKEYR = FLASH_PEKEY2; - } - - /* Unlocking the program memory access */ - FLASH->PRGKEYR = FLASH_PRGKEY1; - FLASH->PRGKEYR = FLASH_PRGKEY2; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the PRGLOCK Bit to lock the program memory access */ - SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET) - { - /* Unlocking FLASH_PECR register access*/ - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) - { - /* Unlocking FLASH_PECR register access*/ - FLASH->PEKEYR = FLASH_PEKEY1; - FLASH->PEKEYR = FLASH_PEKEY2; - } - - /* Unlocking the option bytes block access */ - FLASH->OPTKEYR = FLASH_OPTKEY1; - FLASH->OPTKEYR = FLASH_OPTKEY2; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the option bytes block access */ - SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to lauch the option byte loading */ - SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time Errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: - * @arg FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg FLASH_ERROR_SIZE: FLASH Size error flag - * @arg FLASH_ERROR_OPTV: Option validity error flag - * @arg FLASH_ERROR_OPTVUSR: Option UserValidity Error flag (available only Cat.3, Cat.4 and Cat.5 devices) - * @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices) - */ -FLASH_ErrorTypeDef HAL_FLASH_GetError(void) -{ - return ProcFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c deleted file mode 100644 index 3f46d15fa..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c +++ /dev/null @@ -1,1952 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + FLASH Interface configuration - * + FLASH Memory Erasing - * + DATA EEPROM Programming/Erasing - * + Option Bytes Programming - * + Interrupts management - * - * @verbatim - ============================================================================== - ##### Flash peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other products, the FLASH interface for STM32L1xx - devices contains the following additional features - (+) Erase functions - (+) DATA_EEPROM memory management - (+) BOOT option bit configuration - (+) PCROP protection for all sectors - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32L1xx. It includes: - (+) Full DATA_EEPROM erase and program management - (+) Boot activation - (+) PCROP protection configuration and control for all pages - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void FLASH_SetErrorCode(void); -static void FLASH_ErasePage(uint32_t PageAddress); - -static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState); -static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState); -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState); -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState); -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState); -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR); -static uint8_t FLASH_OB_GetRDP(void); -static uint8_t FLASH_OB_GetUser(void); -static uint8_t FLASH_OB_GetBOR(void); -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState); -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT); -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data); - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 FLASH Memory Erasing functions - * @brief FLASH Memory Erasing functions - * -@verbatim - ============================================================================== - ##### FLASH Erasing Programming functions ##### - ============================================================================== - - [..] The FLASH Memory Erasing functions, includes the following functions: - (+) HAL_FLASHEx_Erase: return only when erase has been done - (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback is called with parameter - 0xFFFFFFFF - - [..] Any operation of erase should follow these steps: - (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and - program memory access. - (#) Call the desired function to erase page. - (#) Call the HAL_FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation). - -@endverbatim - * @{ - */ - -/** - * @brief Erase the specified FLASH memory Pages - * @note To correctly run this function, the HAL_FLASH_Unlock() function - * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError: pointer to variable that - * contains the configuration information on faulty sector in case of error - * (0xFFFFFFFF means that all the sectors have been correctly erased) - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index = 0; - - /* Process Locked */ - __HAL_LOCK(&ProcFlash); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; - - /* Check the parameters */ - assert_param(IS_NBPAGES(pEraseInit->NbPages)); - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); - - /* Erase by sector by sector to be done*/ - for(index = pEraseInit->PageAddress; index < ((pEraseInit->NbPages * FLASH_PAGE_SIZE)+ pEraseInit->PageAddress); index += FLASH_PAGE_SIZE) - { - FLASH_ErasePage(index); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the ERASE Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty sector*/ - *PageError = index; - break; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - - return status; -} - -/** - * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled - * @note To correctly run this function, the HAL_FLASH_Unlock() function - * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&ProcFlash); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); - - /* Check the parameters */ - assert_param(IS_NBPAGES(pEraseInit->NbPages)); - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); - - ProcFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; - ProcFlash.NbPagesToErase = pEraseInit->NbPages; - ProcFlash.Page = pEraseInit->PageAddress; - - /*Erase 1st page and wait for IT*/ - FLASH_ErasePage(pEraseInit->PageAddress); - - return status; -} - -/** - * @} - */ - - -/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== - - [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control - register access. - (#) Call following function to program the desired option bytes. - (++) HAL_FLASHEx_OBProgram: - - To Enable/Disable the desired sector write protection. - - To set the desired read Protection Level. - - To configure the user option Bytes: IWDG, STOP and the Standby. - - To Set the BOR level. - (#) Once all needed option bytes to be programmed are correctly written, call the - HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. - (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended - to protect the option Bytes against possible unwanted operations). - - [..] Proprietary code Read Out Protection (PcROP): - (#) The PcROP sector is selected by using the same option bytes as the Write - protection (nWRPi bits). As a result, these 2 options are exclusive each other. - (#) In order to activate the PcROP (change the function of the nWRPi option bits), - the SPRMOD option bit must be activated. - (#) The active value of nWRPi bits is inverted when PCROP mode is active, this - means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" - is read/write protected. - (#) To activate PCROP mode for Flash sector(s), you need to call the following function: - (++) HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected - (++) HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection - (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices. - -@endverbatim - * @{ - */ - -/** - * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&ProcFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /*Write protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == WRPSTATE_ENABLE) - { - /* Enable of Write protection on the selected Sector*/ - status = FLASH_OB_WRPConfig(pOBInit, ENABLE); - } - else - { - /* Disable of Write protection on the selected Sector*/ - status = FLASH_OB_WRPConfig(pOBInit, DISABLE); - } - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - return status; - } - } - - /* Read protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDPConfig(pOBInit->RDPLevel); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - return status; - } - } - - /* USER configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { - status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, - pOBInit->USERConfig & OB_STOP_NORST, - pOBInit->USERConfig & OB_STDBY_NORST); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - return status; - } - } - - /* BOR Level configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) - { - status = FLASH_OB_BORConfig(pOBInit->BORLevel); - } - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; - - /*Get WRP1*/ - pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1); - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - /*Get WRP2*/ - pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2); - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - /*Get WRP3*/ - pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3); - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - /*Get WRP4*/ - pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4); - -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); - - /*Get BOR Level*/ - pOBInit->BORLevel = FLASH_OB_GetBOR(); - -} - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -/** - * @brief Program option bytes - * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_OBEX(pAdvOBInit->OptionType)); - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - - /* Cat2 & Cat3 devices only */ - /*Program PCROP option byte*/ - if ((pAdvOBInit->OptionType & OBEX_PCROP) == OBEX_PCROP) - { - /* Check the parameters */ - assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); - if (pAdvOBInit->PCROPState == PCROPSTATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ - status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE); - if (status != HAL_OK) - { - return status; - } - } - else - { - /*Disable of Write protection on the selected Sector*/ - status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE); - if (status != HAL_OK) - { - return status; - } - } - } - -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - /* Cat4 & Cat5 devices only */ - /*Program BOOT config option byte*/ - if ((pAdvOBInit->OptionType & OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG) - { - status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); - } - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - return status; -} - -/** - * @brief Get the OBEX byte configuration - * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) -{ -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - - pAdvOBInit->OptionType = OBEX_PCROP; - - /*Get PCROP state */ - pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD); - - /*Get PCROP protected sector from 0 to 31 */ - pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1; - - #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - - /*Get PCROP protected sector from 32 to 63 */ - pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2; - - #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ - -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - pAdvOBInit->OptionType = OBEX_BOOTCONFIG; - - /*Get Boot config OB*/ - pAdvOBInit->BootConfig = (FLASH->OBR & 0x80000000) >> 24; - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -} - -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - -/** - * @brief Select the Protection Mode (SPRMOD). - * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices - * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @retval HAL status - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0; - uint32_t tmp2 = 0; - uint8_t optiontmp = 0; - uint16_t optiontmp2 = 0; - - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Mask RDP Byte */ - optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); - - /* Update Option Byte */ - optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); - - /* calculate the option byte to write */ - tmp1 = (uint16_t)(~(optiontmp2 )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); - - if(status == HAL_OK) - { - /* program PCRop */ - OB->RDP = tmp2; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Return the Read protection operation Status */ - return status; -} - -/** - * @brief Deselect the Protection Mode (SPRMOD). - * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices - * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @retval HAL status - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0; - uint32_t tmp2 = 0; - uint8_t optiontmp = 0; - uint16_t optiontmp2 = 0; - - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Mask RDP Byte */ - optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); - - /* Update Option Byte */ - optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); - - /* calculate the option byte to write */ - tmp1 = (uint16_t)(~(optiontmp2 )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); - - if(status == HAL_OK) - { - /* program PCRop */ - OB->RDP = tmp2; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Return the Read protection operation Status */ - return status; -} - -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -/** - * @} - */ - -/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions - * @brief DATA EEPROM Programming functions - * -@verbatim - =============================================================================== - ##### DATA EEPROM Programming functions ##### - =============================================================================== - - [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access - and Flash program erase control register access. - (#) Call the desired function to erase or program data. - (#) Call the HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access - and Flash program erase control register access(recommended - to protect the DATA_EEPROM against possible unwanted operation). - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the data memory and FLASH_PECR register access. - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void) -{ - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) - { - /* Unlocking the Data memory and FLASH_PECR register access*/ - FLASH->PEKEYR = FLASH_PEKEY1; - FLASH->PEKEYR = FLASH_PEKEY2; - } - else - { - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Locks the Data memory and FLASH_PECR register access. - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) -{ - /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ - SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK); - - return HAL_OK; -} - -/** - * @brief Erase a word in data memory. - * @param Address: specifies the address to be erased. - * @param TypeErase: Indicate the way to erase at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @note To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * Call the DATA_EEPROM_Lock() to the data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TYPEPROGRAMDATA(TypeErase)); - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if(TypeErase == TYPEERASEDATA_WORD) - { - /* Write 00000000h to valid address in the data memory */ - *(__IO uint32_t *) Address = 0x00000000; - } - - if(TypeErase == TYPEERASEDATA_HALFWORD) - { - /* Write 0000h to valid address in the data memory */ - *(__IO uint16_t *) Address = (uint16_t)0x0000; - } - - if(TypeErase == TYPEERASEDATA_BYTE) - { - /* Write 00h to valid address in the data memory */ - *(__IO uint8_t *) Address = (uint8_t)0x00; - } - } - - /* Return the erase status */ - return status; -} - -/** - * @brief Program word at a specified address - * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @note The function HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before - * this function to configure the Fixed Time Programming. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASHEx_Type_Program_Data - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ - -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&ProcFlash); - - /* Check the parameters */ - assert_param(IS_TYPEPROGRAMDATA(TypeProgram)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if(TypeProgram == TYPEPROGRAMDATA_FASTBYTE) - { - /*Program word (8-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data); - } - - if(TypeProgram == TYPEPROGRAMDATA_FASTHALFWORD) - { - /*Program word (16-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data); - } - - if(TypeProgram == TYPEPROGRAMDATA_FASTWORD) - { - /*Program word (32-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data); - } - - if(TypeProgram == TYPEPROGRAMDATA_WORD) - { - /*Program word (32-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data); - } - - if(TypeProgram == TYPEPROGRAMDATA_HALFWORD) - { - /*Program word (16-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data); - } - - if(TypeProgram == TYPEPROGRAMDATA_BYTE) - { - /*Program word (8-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data); - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - - return status; -} - -/** - * @brief Enable DATA EEPROM fixed Time programming (2*Tprog). - * @retval None - */ -void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void) -{ - SET_BIT(FLASH->PECR, FLASH_PECR_FTDW); -} - -/** - * @brief Disables DATA EEPROM fixed Time programming (2*Tprog). - * @retval None - */ -void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) -{ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASHEx_Private_Functions FLASHEx Private functions - * @{ - */ - -/* -============================================================================== - ##### FLASH STATIC functions ##### -============================================================================== -*/ - -/* -============================================================================== - FLASH -============================================================================== -*/ - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) - { - ProcFlash.ErrorCode = FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_SIZE; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_OPTV; - } - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_RD; - } -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) - { - ProcFlash.ErrorCode |= FLASH_ERROR_OPTVUSR; - } -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -} - -/** - * @brief Erases a specified page in program memory. - * @param PageAddress: The page address in program memory to be erased. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 256 bytes). - * @retval None - */ -static void FLASH_ErasePage(uint32_t PageAddress) -{ - /* Set the ERASE bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - /* Set PROG bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* Write 00000000h to the first word of the program page to erase */ - *(__IO uint32_t *)PageAddress = 0x00000000; -} - - -/* -============================================================================== - OPTIONS BYTES -============================================================================== -*/ -/** - * @brief Enables or disables the read out protection. - * @note To correctly run this function, the HAL_FLASH_OB_Unlock() function - * must be called before. - * @param OB_RDP: specifies the read protection level. - * This parameter can be: - * @arg OB_RDP_LEVEL0: No protection - * @arg OB_RDP_LEVEL1: Read protection of the memory - * @arg OB_RDP_LEVEL2: Chip protection - * - * !!!Warning!!! When enabling OB_RDP_LEVEL2 it's no more possible to go back to level 1 or 0 - * - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp1 = 0, tmp2 = 0, sprmod = 0; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - /* According to errata sheet, DocID022054 Rev 5, par2.1.5 - Before setting Level0 in the RDP register, check that the current level is not equal to Level0. - If the current level is not equal to Level0, Level0 can be activated. - If the current level is Level0 then the RDP register must not be written again with Level0. */ - tmp1 = (uint32_t)(OB->RDP & 0x000000FF); - - if ((tmp1 == OB_RDP_LEVEL0) && (OB_RDP == OB_RDP_LEVEL0)) - { - /*current level is Level0 then the RDP register must not be written again with Level0. */ - status = HAL_ERROR; - } - else - { - /* Mask SPRMOD bit */ - sprmod = (uint32_t)(OB->RDP & 0x00000100); - - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* calculate the option byte to write */ - tmp1 = (~((uint32_t)(OB_RDP | sprmod))); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)(OB_RDP | sprmod))); - - if(status == HAL_OK) - { - /* program read protection level */ - OB->RDP = tmp2; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - - /* Return the Read protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH brownout reset threshold level Option Byte. - * @param OB_BOR: Selects the brownout reset threshold level. - * This parameter can be one of the following values: - * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD - * power supply reaches the PDR(Power Down Reset) threshold (1.5V) - * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply - * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply - * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply - * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply - * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_OB_BOR_LEVEL(OB_BOR)); - - /* Get the User Option byte register */ - tmp1 = (FLASH->OBR & (FLASH_OBR_USER)) >> 16; - - /* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/ - tmp = (uint32_t)~((OB_BOR | tmp1)) << 16; - tmp |= (OB_BOR | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Write the BOR Option Byte */ - OB->USER = tmp; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @retval The FLASH User Option Bytes. - */ -static uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> POSITION_VAL(FLASH_OBR_USER)); -} - -/** - * @brief Checks whether the FLASH Read out Protection Status is set or not. - * @retval FLASH ReadOut Protection - */ -static uint8_t FLASH_OB_GetRDP(void) -{ - return (uint8_t)(FLASH->OBR & FLASH_OBR_RDPRT); -} - -/** - * @brief Returns the FLASH BOR level. - * @retval The FLASH User Option Bytes. - */ -static uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the BOR level */ - return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> POSITION_VAL(FLASH_OBR_BOR_LEV)); -} - -/** - * @brief Write protects the desired pages of the first 64KB of the Flash. - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains WRP parameters. - * @param NewState: new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval HAL_StatusTypeDef - */ -static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* WRP for sector between 0 to 31 */ - if (pOBInit->WRPSector0To31 != 0) - { - FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState); - } - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - /* Pages for Cat3, Cat4 & Cat5 devices*/ - /* WRP for sector between 32 to 63 */ - if (pOBInit->WRPSector32To63 != 0) - { - FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState); - } - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - /* Pages for devices with FLASH >= 256KB*/ - /* WRP for sector between 64 to 95 */ - if (pOBInit->WRPSector64To95 != 0) - { - FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState); - } - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - - /* Pages for Cat5 devices*/ - /* WRP for sector between 96 to 127 */ - if (pOBInit->WRPSector96To127 != 0) - { - FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState); - } - -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - - /* Return the write protection operation Status */ - return status; -} - -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) -/** - * @brief Enables the read/write protection (PCROP) of the desired - * sectors. - * @note This function can be used only for Cat2 & Cat3 devices - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains PCROP parameters. - * @param NewState: new state of the specified FLASH Pages read/Write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState) -{ - HAL_StatusTypeDef status = HAL_OK; - FunctionalState pcropstate = DISABLE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Invert state to use same function of WRP */ - if (NewState == DISABLE) - { - pcropstate = ENABLE; - } - - if(status == HAL_OK) - { - /* Pages for Cat2 devices*/ - /* PCROP for sector between 0 to 31 */ - if (pAdvOBInit->PCROPSector0To31 != 0) - { - FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate); - } - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - - /* Pages for Cat3 devices*/ - /* WRP for sector between 32 to 63 */ - if (pAdvOBInit->PCROPSector32To63 != 0) - { - FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate); - } - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - - /* Return the write protection operation Status */ - return status; -} -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -/** - * @brief Write protects the desired pages of the first 128KB of the Flash. - * @param WRP1OrPCROP1: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP1/PCROP1_PAGES0TO15 and OB_WRP1/PCROP1_PAGES496TO511 - * @arg OB_WRP1/PCROP1_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState) -{ - uint32_t wrp01data = 0, wrp23data = 0; - - uint32_t tmp1 = 0, tmp2 = 0; - - if (NewState != DISABLE) - { - wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01)); - wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 | OB->WRP23))); - tmp1 = (uint32_t)(~(wrp01data) << 16)|(wrp01data); - OB->WRP01 = tmp1; - - tmp2 = (uint32_t)(~(wrp23data) << 16)|(wrp23data); - OB->WRP23 = tmp2; - } - else - { - wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01)); - wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 & OB->WRP23))); - - tmp1 = (uint32_t)((~wrp01data) << 16)|(wrp01data); - OB->WRP01 = tmp1; - - tmp2 = (uint32_t)((~wrp23data) << 16)|(wrp23data); - OB->WRP23 = tmp2; - } -} - -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Enable Write protects the desired pages of the second 128KB of the Flash. - * @note This function can be used only for Cat3, Cat4 & Cat5 devices. - * @param WRP2OrPCROP2: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP2/PCROP2_PAGES512TO527 and OB_WRP2/PCROP2_PAGES1008TO1023 - * @arg OB_WRP2/PCROP2_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState) -{ - uint32_t wrp45data = 0, wrp67data = 0; - - uint32_t tmp1 = 0, tmp2 = 0; - - if (NewState != DISABLE) - { - wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45)); - wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 | OB->WRP67))); - tmp1 = (uint32_t)(~(wrp45data) << 16)|(wrp45data); - OB->WRP45 = tmp1; - - tmp2 = (uint32_t)(~(wrp67data) << 16)|(wrp67data); - OB->WRP67 = tmp2; - } - else - { - wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45)); - wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 & OB->WRP67))); - - tmp1 = (uint32_t)((~wrp45data) << 16)|(wrp45data); - OB->WRP45 = tmp1; - - tmp2 = (uint32_t)((~wrp67data) << 16)|(wrp67data); - OB->WRP67 = tmp2; - } -} -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Enable Write protects the desired pages of the third 128KB of the Flash. - * @note This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD & Cat5 devices. - * @param WRP3: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between WRP3_PAGES1024TO1039 and OB_WRP3_PAGES1520TO1535 - * @arg OB_WRP3_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState) -{ - uint32_t wrp89data = 0, wrp1011data = 0; - - uint32_t tmp1 = 0, tmp2 = 0; - - if (NewState != DISABLE) - { - wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89)); - wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16 | OB->WRP1011))); - tmp1 = (uint32_t)(~(wrp89data) << 16)|(wrp89data); - OB->WRP89 = tmp1; - - tmp2 = (uint32_t)(~(wrp1011data) << 16)|(wrp1011data); - OB->WRP1011 = tmp2; - } - else - { - wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89)); - wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16 & OB->WRP1011))); - - tmp1 = (uint32_t)((~wrp89data) << 16)|(wrp89data); - OB->WRP89 = tmp1; - - tmp2 = (uint32_t)((~wrp1011data) << 16)|(wrp1011data); - OB->WRP1011 = tmp2; - } -} -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Enable Write protects the desired pages of the Fourth 128KB of the Flash. - * @note This function can be used only for Cat5 devices. - * @param WRP4: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP4_PAGES1536TO1551 and OB_WRP4_PAGES2032TO2047 - * @arg OB_WRP4_ALLPAGES - * @param NewState: new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState) -{ - uint32_t wrp1213data = 0, wrp1415data = 0; - - uint32_t tmp1 = 0, tmp2 = 0; - - if (NewState != DISABLE) - { - wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213)); - wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16 | OB->WRP1415))); - tmp1 = (uint32_t)(~(wrp1213data) << 16)|(wrp1213data); - OB->WRP1213 = tmp1; - - tmp2 = (uint32_t)(~(wrp1415data) << 16)|(wrp1415data); - OB->WRP1415 = tmp2; - } - else - { - wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213)); - wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16 & OB->WRP1415))); - - tmp1 = (uint32_t)((~wrp1213data) << 16)|(wrp1213data); - OB->WRP1213 = tmp1; - - tmp2 = (uint32_t)((~wrp1415data) << 16)|(wrp1415data); - OB->WRP1415 = tmp2; - } -} -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the WDG mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software WDG selected - * @arg OB_IWDG_HW: Hardware WDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NORST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NORST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Get the User Option byte register */ - tmp1 = (FLASH->OBR & FLASH_OBR_BOR_LEV) >> 16; - - /* Calculate the user option byte to write */ - tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16); - tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Write the User Option Byte */ - OB->USER = tmp; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Return the Option Byte program Status */ - return status; -} - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Configures to boot from Bank1 or Bank2. - * @param OB_BOOT: select the FLASH Bank to boot from. - * This parameter can be one of the following values: - * @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank2 or Bank1, - * depending on the activation of the bank. The active banks are checked in - * the following order: Bank2, followed by Bank1. - * The active bank is recognized by the value programmed at the base address - * of the respective bank (corresponding to the initial stack pointer value - * in the interrupt vector table). - * @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank1(Default). - * For more information, please refer to AN2606 from www.st.com. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_OB_BOOT_BANK(OB_BOOT)); - - /* Get the User Option byte register and BOR Level*/ - tmp1 = (FLASH->OBR & (FLASH_OBR_nRST_STDBY | FLASH_OBR_nRST_STOP | FLASH_OBR_IWDG_SW | FLASH_OBR_BOR_LEV)) >> 16; - - /* Calculate the option byte to write */ - tmp = (uint32_t)~(OB_BOOT | tmp1) << 16; - tmp |= (OB_BOOT | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Write the BOOT Option Byte */ - OB->USER = tmp; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* Return the Option Byte program Status */ - return status; -} - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/* -============================================================================== - DATA -============================================================================== -*/ - -/** - * @brief Write a Byte at a specified address in data memory. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - uint32_t tmp = 0, tmpaddr = 0; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - /* Possible only on Cat1 devices */ - if(Data != (uint8_t)0x00) - { - /* If the previous operation is completed, proceed to write the new Data */ - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - else - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); - } -#else /*!Cat1*/ - /* If the previous operation is completed, proceed to write the new Data */ - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Writes a half word at a specified address in data memory. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - uint32_t tmp = 0, tmpaddr = 0; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); - -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - /* Possible only on Cat1 devices */ - if(Data != (uint16_t)0x0000) - { - /* If the previous operation is completed, proceed to write the new data */ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - else - { - if((Address & 0x3) != 0x3) - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); - } - else - { - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); - } - } -#else /* !Cat1 */ - /* If the previous operation is completed, proceed to write the new data */ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); - - /* If the previous operation is completed, proceed to program the new data */ - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Write a Byte at a specified address in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - uint32_t tmp = 0, tmpaddr = 0; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - if(Data != (uint8_t) 0x00) - { - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - } - else - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); - } -#else /* Not Cat1*/ - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Writes a half word at a specified address in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - uint32_t tmp = 0, tmpaddr = 0; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { -#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) - if(Data != (uint16_t)0x0000) - { - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - else - { - if((Address & 0x3) != 0x3) - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC); - status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp); - } - else - { - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00); - HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00); - } - } -#else /* Not Cat1*/ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions_Group1 - * @brief Interrupts functions - * -@verbatim - ============================================================================== - ##### Interrupts functions ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t temp; - - /* If the program operation is completed, disable the PROG Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* If the erase operation is completed, disable the ERASE Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - { - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /*Nb of sector to erased can be decreased*/ - ProcFlash.NbPagesToErase--; - - /* Check if there are still sectors to erase*/ - if(ProcFlash.NbPagesToErase != 0) - { - temp = ProcFlash.Page; - /*Indicate user which sector has been erased*/ - HAL_FLASH_EndOfOperationCallback(temp); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); - - /*Increment sector number*/ - temp = ProcFlash.Page + FLASH_PAGE_SIZE; - ProcFlash.Page = ProcFlash.Page + FLASH_PAGE_SIZE; - FLASH_ErasePage(temp); - } - else - { - /*No more sectors to Erase, user callback can be called.*/ - /*Reset Sector and stop Erase sectors procedure*/ - ProcFlash.Page = temp = 0xFFFFFFFF; - ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(temp); - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - } - else - { - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(ProcFlash.Address); - } - ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - } - - /* Check FLASH operation error flags */ - if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) - { - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /*return the faulty sector*/ - temp = ProcFlash.Page; - ProcFlash.Page = 0xFFFFFFFF; - } - else - { - /*retrun the faulty address*/ - temp = ProcFlash.Address; - } - - /*Save the Error code*/ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(temp); - - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK); - - /*Stop the procedure ongoing*/ - ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - if(ProcFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Disable End of FLASH Operation interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); - - /* Disable Error source interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&ProcFlash); - } - -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Internal_Functions FLASH Internal function - * @{ - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operationtimeout - * @retval HAL status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* There is no error flag set */ - return HAL_OK; -} - - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c deleted file mode 100644 index b743f19f1..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c +++ /dev/null @@ -1,545 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash_ramfunc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief FLASH RAMFUNC driver. - * This file provides a Flash firmware functions which should be - * executed from internal SRAM - * - * @verbatim - - *** ARM Compiler *** - -------------------- - [..] RAM functions are defined using the toolchain options. - Functions that are be executed in RAM should reside in a separate - source module. Using the 'Options for File' dialog you can simply change - the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - Options for Target' dialog. - - *** ICCARM Compiler *** - ----------------------- - [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". - - *** GNU Compiler *** - -------------------- - [..] RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". - -@endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHRamfunc FLASHRamfunc - * @brief FLASH functions executed from RAM - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASHRamfunc_Exported_Functions FLASH RAM Exported Functions - * -@verbatim - =============================================================================== - ##### ramfunc functions ##### - =============================================================================== - [..] - This subsection provides a set of functions that should be executed from RAM - transfers. - -@endverbatim - * @{ - */ - -/** @defgroup FLASHRamfunc_Exported_Functions_Group1 FLASH RAM Peripheral features functions - * @{ - */ - -/** - * @brief Enable the power down mode during RUN mode. - * @note This function can be used only when the user code is running from Internal SRAM. - * @retval None - */ -__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) -{ - /* Enable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_ENABLE(); - - return HAL_OK; -} - - -/** - * @brief Disable the power down mode during RUN mode. - * @note This function can be used only when the user code is running from Internal SRAM. - * @retval None - */ -__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) -{ - /* Disable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_DISABLE(); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup FLASHRamfunc_Exported_Functions_Group2 FLASH RAM Programming and erasing operation functions - * -@verbatim -@endverbatim - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Erases a specified 2 page in program memory in parallel. - * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. - * To correctly run this function, the HAL_FLASH_Unlock() function - * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation). - * @param Page_Address1: The page address in program memory to be erased in - * the first Bank (BANK1). This parameter should be between FLASH_BASE - * and FLASH_BANK1_END. - * @param Page_Address2: The page address in program memory to be erased in - * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE - * and FLASH_BANK2_END. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 256 bytes). - * @retval HAL Status: The returned value can be: - * HAL_ERROR, HAL_OK or HAL_TIMEOUT. - */ -__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* If the previous operation is completed, proceed to erase the page */ - - /* Set the PARALLBANK bit */ - FLASH->PECR |= FLASH_PECR_PARALLBANK; - - /* Set the ERASE bit */ - FLASH->PECR |= FLASH_PECR_ERASE; - - /* Set PROG bit */ - FLASH->PECR |= FLASH_PECR_PROG; - - /* Write 00000000h to the first word of the first program page to erase */ - *(__IO uint32_t *)Page_Address1 = 0x00000000; - /* Write 00000000h to the first word of the second program page to erase */ - *(__IO uint32_t *)Page_Address2 = 0x00000000; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs 2 half page in program memory in parallel. - * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. - * @param Address1: specifies the first address to be written in the first bank - * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE). - * @param pBuffer1: pointer to the buffer containing the data to be written - * to the first half page in the first bank. - * @param Address2: specifies the second address to be written in the second bank - * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE). - * @param pBuffer2: pointer to the buffer containing the data to be written - * to the second half page in the second bank. - * @note To correctly run this function, the HAL_FLASH_Unlock() function - * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation). - * @note Half page write is possible only from SRAM. - * @note If there are more than 32 words to write, after 32 words another - * Half Page programming operation starts and has to be finished. - * @note A half page is written to the program memory only if the first - * address to load is the start address of a half page (multiple of 128 - * bytes) and the 31 remaining words to load are in the same half page. - * @note During the Program memory half page write all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @note If a PGAERR is set during a Program memory half page write, the - * complete write operation is aborted. Software should then reset the - * FPRG and PROG/DATA bits and restart the write operation from the - * beginning. - * @retval HAL Status: The returned value can be: - * HAL_ERROR, HAL_OK or HAL_TIMEOUT. - */ -__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) -{ - uint32_t count = 0; - - HAL_StatusTypeDef status = HAL_OK; - - /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) - This bit prevents the interruption of multicycle instructions and therefore - will increase the interrupt latency. of Cortex-M3. */ - SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* If the previous operation is completed, proceed to program the new - half page */ - FLASH->PECR |= FLASH_PECR_PARALLBANK; - FLASH->PECR |= FLASH_PECR_FPRG; - FLASH->PECR |= FLASH_PECR_PROG; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) - { - /* Write the first half page directly with 32 different words */ - while(count < 32) - { - *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *(pBuffer1++); - count ++; - } - count = 0; - - /* Write the second half page directly with 32 different words */ - while(count < 32) - { - *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *(pBuffer2++); - count ++; - } - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - } - /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK); - } - - SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Return the Write Status */ - return status; -} -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief Programs a half page in program memory. - * @param Address: specifies the address to be written. - * @param pBuffer: pointer to the buffer containing the data to be written to - * the half page. - * @note To correctly run this function, the HAL_FLASH_Unlock() function - * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @note Half page write is possible only from SRAM. - * @note If there are more than 32 words to write, after 32 words another - * Half Page programming operation starts and has to be finished. - * @note A half page is written to the program memory only if the first - * address to load is the start address of a half page (multiple of 128 - * bytes) and the 31 remaining words to load are in the same half page. - * @note During the Program memory half page write all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @note If a PGAERR is set during a Program memory half page write, the - * complete write operation is aborted. Software should then reset the - * FPRG and PROG/DATA bits and restart the write operation from the - * beginning. - * @retval HAL Status: The returned value can be: - * HAL_ERROR, HAL_OK or HAL_TIMEOUT. - */ -__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) -{ - uint32_t count = 0; - - HAL_StatusTypeDef status = HAL_OK; - - /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) - This bit prevents the interruption of multicycle instructions and therefore - will increase the interrupt latency. of Cortex-M3. */ - SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* if the previous operation is completed, proceed to program the new - half page */ - FLASH->PECR |= FLASH_PECR_FPRG; - FLASH->PECR |= FLASH_PECR_PROG; - - /* Write one half page directly with 32 different words */ - while(count < 32) - { - *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *(pBuffer++); - count ++; - } - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* if the write operation is completed, disable the PROG and FPRG bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); - } - - SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASHRamfunc_Exported_Functions_Group3 FLASH RAM DATA EEPROM functions - * -@verbatim -@endverbatim - * @{ - */ - -/** - * @brief Erase a double word in data memory. - * @param Address: specifies the address to be erased. - * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @note Data memory double word erase is possible only from SRAM. - * @note A double word is erased to the data memory only if the first address - * to load is the start address of a double word (multiple of 8 bytes). - * @note During the Data memory double word erase, all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @retval HAL Status: The returned value can be: - * HAL_ERROR, HAL_OK or HAL_TIMEOUT. - */ - -__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) - This bit prevents the interruption of multicycle instructions and therefore - will increase the interrupt latency. of Cortex-M3. */ - SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* If the previous operation is completed, proceed to erase the next double word */ - /* Set the ERASE bit */ - FLASH->PECR |= FLASH_PECR_ERASE; - - /* Set DATA bit */ - FLASH->PECR |= FLASH_PECR_DATA; - - /* Write 00000000h to the 2 words to erase */ - *(__IO uint32_t *)Address = 0x00000000; - Address += 4; - *(__IO uint32_t *)Address = 0x00000000; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the ERASE and DATA bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); - } - - SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Return the erase status */ - return status; -} - -/** - * @brief Write a double word in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @note Data memory double word write is possible only from SRAM. - * @note A data memory double word is written to the data memory only if the - * first address to load is the start address of a double word (multiple - * of double word). - * @note During the Data memory double word write, all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @retval HAL Status: The returned value can be: - * HAL_ERROR, HAL_OK or HAL_TIMEOUT. - */ -__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) - This bit prevents the interruption of multicycle instructions and therefore - will increase the interrupt latency. of Cortex-M3. */ - SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* If the previous operation is completed, proceed to program the new data*/ - FLASH->PECR |= FLASH_PECR_FPRG; - FLASH->PECR |= FLASH_PECR_DATA; - - /* Write the 2 words */ - *(__IO uint32_t *)Address = (uint32_t) Data; - Address += 4; - *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE); - - /* If the write operation is completed, disable the FPRG and DATA bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); - } - - SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk; - - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASHRamfunc_Private_Functions FLASH RAM Private Functions - * @{ - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operationtimeout - * @retval HAL status - */ -static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00)) - { - Timeout--; - } - - if(Timeout == 0x00 ) - { - return HAL_TIMEOUT; - } - - if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || -#if defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) ) - { - return HAL_ERROR; - } - - /* If there is an error flag set */ - return HAL_OK; -} - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c deleted file mode 100644 index 1623eaaf5..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c +++ /dev/null @@ -1,540 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_gpio.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - Each port bit of the general-purpose I/O (GPIO) ports can be individually - configured by software in several modes: - (+) Input mode - (+) Analog mode - (+) Output mode - (+) Alternate function mode - (+) External interrupt/event lines - - [..] - During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - [..] - In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - [..] - The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral’s alternate function (AF) connected - to an IO pin at a time. In this way, there can be no conflict between peripherals - sharing the same IO pin. - - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] - The external interrupt/event controller consists of up to 23 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure - (++) If alternate mode is selected, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ - -#define GPIO_MODE ((uint32_t)0x00000003) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) -#define GPIO_NUMBER ((uint32_t)16) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position; - uint32_t ioposition = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Configure the port pins */ - for (position = 0; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - - if (iocurrent == ioposition) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameter */ - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - /* Configure Alternate function mapped with the current IO */ - /* Identify AFRL or AFRH register based on IO position*/ - temp = GPIOx->AFR[position >> 3]; - CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); - SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - GPIOx->MODER = temp; - - /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - SET_BIT(temp, GPIO_Init->Speed << (position * 2)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; - SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - GPIOx->OTYPER = temp; - } - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); - SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); - GPIOx->PUPDR = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - /* Enable SYSCFG Clock */ - __SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); - SET_BIT(temp, (GET_GPIO_INDEX(GPIOx)) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - SET_BIT(temp, iocurrent); - } - EXTI->IMR = temp; - - temp = EXTI->EMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - SET_BIT(temp, iocurrent); - } - EXTI->EMR = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->RTSR = temp; - - temp = EXTI->FTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->FTSR = temp; - } - } - } -} - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position; - uint32_t ioposition = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Configure the port pins */ - for (position = 0; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (GPIO_Pin) & ioposition; - - if (iocurrent == ioposition) - { - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO Direction in Input Floting Mode */ - CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); - - /* Configure the default Alternate Function in current IO */ - CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - - /* Configure the default value for IO Speed */ - CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - - /* Configure the default value IO Output Type */ - CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; - - /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ - CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2)); - - - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Configure the External Interrupt or event for the current IO */ - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); - - /* Clear EXTI line configuration */ - CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); - } - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; -} - -/** - * @brief Sets or clears the selected data port bit. - * - * @note This function uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_BIT_RESET: to clear the port pin - * @arg GPIO_BIT_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if(PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; - } -} - -/** - * @brief Toggles the specified GPIO pin - * @param GPIOx: where x can be (A..Gdepending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** -* @brief Locks GPIO Pins configuration registers. -* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, -* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. -* @note The configuration of the locked GPIO pins can no longer be modified -* until the next reset. -* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices -* @param GPIO_Pin: specifies the port bit to be locked. -* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). -* @retval None -*/ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - SET_BIT(tmp, GPIO_Pin); - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - - if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callback - * @param GPIO_Pin: Specifies the pins connected EXTI line - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c deleted file mode 100644 index 8f227dc75..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c +++ /dev/null @@ -1,3635 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_i2c.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Channel - (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx Channel - - (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, - Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ -#define I2C_TIMEOUT_FLAG ((uint32_t)35) /* 35 ms */ -#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /* 10 s */ - -#define I2C_MIN_PCLK_FREQ ((uint32_t)2000000) /* 2 MHz*/ -/** - * @} - */ - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ - -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); - -static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout); -static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout); -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout); - -static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); - -static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); -static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Communication Speed - (++) Duty cycle - (++) Addressing mode - (++) Own Address 1 - (++) Dual Addressing mode - (++) Own Address 2 - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx periperal. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and create the associated handle. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - uint32_t freqrange = 0; - uint32_t pclk1 = 0; - - /* Check the I2C handle allocation */ - if(hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); - assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if(hi2c->State == HAL_I2C_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_I2C_MspInit(hi2c); - } - - /* Get PCLK1 frequency */ - pclk1 = HAL_RCC_GetPCLK1Freq(); - - /* The minimum allowed frequency is 2 MHz */ - if(pclk1 < I2C_MIN_PCLK_FREQ) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disble the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Calculate frequency range */ - freqrange = I2C_FREQRANGE(pclk1); - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Frequency range */ - MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); - - /*---------------------------- I2Cx TRISE Configuration --------------------*/ - /* Configure I2Cx: Rise Time */ - MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); - - /*---------------------------- I2Cx CCR Configuration ----------------------*/ - /* Configure I2Cx: Speed */ - MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Configure I2Cx: Own Address1 and addressing mode */ - MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Configure I2Cx: Dual mode and Own Address2 */ - MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the I2C peripheral. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if(hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->State = HAL_I2C_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief I2C MSP Init. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief I2C MSP DeInit - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - while(Size > 0) - { - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) - { - /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; - } - } - - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - if(Size == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - } - else if(Size == 2) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - while(Size > 0) - { - if(Size <= 3) - { - /* One byte */ - if(Size == 1) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - /* Two bytes */ - else if(Size == 2) - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - /* 3 Last bytes */ - else - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - } - else - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) - { - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - } - } - - /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - while(Size > 0) - { - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) - { - /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; - } - } - - /* Wait until AF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - while(Size > 0) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) - { - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - } - - /* Wait until STOP flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_STOPFLAG(hi2c); - - /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - if(hi2c->XferCount == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - } - else if(hi2c->XferCount == 2) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); - - /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); - - /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - if(Size == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - } - else - { - /* Enable Last DMA bit */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - } - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* If 7bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in no-blocking mode with DMA - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - while(Size > 0) - { - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; - - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) - { - /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; - } - } - - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - if(Size == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - } - else if(Size == 2) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - while(Size > 0) - { - if(Size <= 3) - { - /* One byte */ - if(Size== 1) - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - /* Two bytes */ - else if(Size == 2) - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - /* 3 Last bytes */ - else - { - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - } - else - { - /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) - { - /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - } - } - } - - /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - if(hi2c->XferCount == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - } - else if(hi2c->XferCount == 2) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - if(Size == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - } - else - { - /* Enable Last DMA bit */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - } - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param Trials: Number of trials - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0, I2C_Trials = 1; - - if(hi2c->State == HAL_I2C_STATE_READY) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - - /* Wait until ADDR or AF flag are set */ - /* Get tick */ - tickstart = HAL_GetTick(); - - while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET) && \ - (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && \ - (hi2c->State != HAL_I2C_STATE_TIMEOUT)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_TIMEOUT; - } - } - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if the ADDR flag has been set */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) - { - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Clear ADDR Flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Clear AF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - }while(I2C_Trials++ < Trials); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - /* Master mode selected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == SET) - { - /* I2C in mode Transmitter -----------------------------------------------*/ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET) - { - /* TXE set and BTF reset -----------------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ - (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) - { - I2C_MasterTransmit_TXE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) - { - I2C_MasterTransmit_BTF(hi2c); - } - } - /* I2C in mode Receiver --------------------------------------------------*/ - else - { - /* RXNE set and BTF reset -----------------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ - (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) - { - I2C_MasterReceive_RXNE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) - { - I2C_MasterReceive_BTF(hi2c); - } - } - } - /* Slave mode selected */ - else - { - /* ADDR set --------------------------------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT)) == SET)) - { - I2C_Slave_ADDR(hi2c); - } - /* STOPF set --------------------------------------------------------------*/ - else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT)) == SET)) - { - I2C_Slave_STOPF(hi2c); - } - /* I2C in mode Transmitter -----------------------------------------------*/ - else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET) - { - /* TXE set and BTF reset -----------------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ - (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) - { - I2C_SlaveTransmit_TXE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) - { - I2C_SlaveTransmit_BTF(hi2c); - } - } - /* I2C in mode Receiver --------------------------------------------------*/ - else - { - /* RXNE set and BTF reset ----------------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \ - (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) - { - I2C_SlaveReceive_RXNE(hi2c); - } - /* BTF set -------------------------------------------------------------*/ - else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET)) - { - I2C_SlaveReceive_BTF(hi2c); - } - } - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - - /* I2C Bus error interrupt occurred ----------------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* I2C Acknowledge failure error interrupt occurred ------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) - { - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == RESET) && \ - (hi2c->XferCount == 0) && \ - (hi2c->State == HAL_I2C_STATE_BUSY_TX)) - { - I2C_Slave_AF(hi2c); - } - else - { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - - /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && \ - (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Disable EVT, BUF and ERR interrupts */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief Master Tx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback can be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief I2C error callbacks. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval None - */ - __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the I2C state. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -{ - return hi2c->State; -} - -/** - * @brief Return the I2C error code - * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @addtogroup I2C_Private_Functions - * @{ - */ - - -/** - * @brief Handle TXE flag for Master - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) -{ - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - - if(hi2c->XferCount == 0) - { - /* Disable BUF interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - } - - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Master transmitter - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount != 0) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - else - { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - return HAL_OK; -} - -/** - * @brief Handle RXNE flag for Master - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) -{ - uint32_t tmp = 0; - - tmp = hi2c->XferCount; - if(tmp > 3) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - else if((tmp == 2) || (tmp == 3)) - { - /* Disable BUF interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - } - else - { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Master receiver - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount == 3) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - else if(hi2c->XferCount == 2) - { - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - - /* Disable EVT and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } - else - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle TXE flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount != 0) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Slave transmitter - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount != 0) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle RXNE flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount != 0) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle BTF flag for Slave receiver - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) -{ - if(hi2c->XferCount != 0) - { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; - } - return HAL_OK; -} - -/** - * @brief Handle ADD flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) -{ - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - return HAL_OK; -} - -/** - * @brief Handle STOPF flag for Slave - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) -{ - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Clear STOPF flag */ - __HAL_I2C_CLEAR_STOPFLAG(hi2c); - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_SlaveRxCpltCallback(hi2c); - - return HAL_OK; -} - -/** - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) -{ - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_SlaveTxCpltCallback(hi2c); - - return HAL_OK; -} - -/** - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) -{ - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - } - else - { - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); - - /* Wait until ADD10 flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); - } - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address for read request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) -{ - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); - } - else - { - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); - - /* Wait until ADD10 flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Restart */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send header of slave address */ - hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); - } - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) -{ - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send LSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param DevAddress: Target device address - * @param MemAddress: Internal memory address - * @param MemAddSize: Size of internal memory address - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) -{ - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send LSB of Memory Address */ - hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TXE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Generate Restart */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - - /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send slave address */ - hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until BTF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MasterTxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until AF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveTxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C master receive process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Disable Last DMA */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MasterRxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Clear STOPF flag */ - __HAL_I2C_CLEAR_STOPFLAG(hi2c); - - /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveRxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C Memory Write process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until BTF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MemTxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C Memory Read process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Disable Last DMA */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MemRxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - HAL_I2C_ErrorCallback(hi2c); -} - -/** - * @brief This function handles I2C Communication Timeout. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param Flag: specifies the I2C flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for Master addressing phase. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @param Flag: specifies the I2C flag to check. - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) - { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - - /* Clear AF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c deleted file mode 100644 index 1506745f6..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c +++ /dev/null @@ -1,1384 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_i2s.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief I2S HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Integrated Interchip Sound (I2S) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The I2S HAL driver can be used as follow: - - (#) Declare a I2S_HandleTypeDef handle structure. - (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: - (##) Enable the SPIx interface clock. - (##) I2S pins configuration: - (+++) Enable the clock for the I2S GPIOs. - (+++) Configure these I2S pins as alternate function. - (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() - and HAL_I2S_Receive_IT() APIs). - (+++) Configure the I2Sx interrupt priority. - (+++) Enable the NVIC I2S IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() - and HAL_I2S_Receive_DMA() APIs: - (+++) Declare a DMA handle structure for the Tx/Rx Channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Channel. - (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA Tx/Rx Channel. - - (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity - using HAL_I2S_Init() function. - - -@- The specific I2S interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. - -@- Make sure that either: - (+@) External clock source is configured after setting correctly - the define constant HSE_VALUE in the stm32l1xx_hal_conf.h file. - - (#) Three mode of operations are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() - (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - (+) Pause the DMA Transfer using HAL_I2S_DMAPause() - (+) Resume the DMA Transfer using HAL_I2S_DMAResume() - (+) Stop the DMA Transfer using HAL_I2S_DMAStop() - - *** I2S HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in USART HAL driver. - - (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts - (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts - (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not - - [..] - (@) You can refer to the I2S HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup I2S I2S - * @brief I2S HAL module driver - * @{ - */ - -#ifdef HAL_I2S_MODULE_ENABLED -#if defined(STM32L100xC) || \ - defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \ - defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || \ - defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMAError(DMA_HandleTypeDef *hdma); -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2S_Exported_Functions I2S Exported Functions - * @{ - */ - -/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the I2Sx peripheral in simplex mode: - - (+) User must Implement HAL_I2S_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2S_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Standard - (++) Data Format - (++) MCLK Output - (++) Audio frequency - (++) Polarity - - (+) Call the function HAL_I2S_DeInit() to restore the default configuration - of the selected I2Sx periperal. - @endverbatim - * @{ - */ - -/** - * @brief Initializes the I2S according to the specified parameters - * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) -{ - uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; - - /* Check the I2S handle allocation */ - if(hi2s == NULL) - { - return HAL_ERROR; - } - - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); - assert_param(IS_I2S_MODE(hi2s->Init.Mode)); - assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); - assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); - assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); - - if(hi2s->State == HAL_I2S_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2S_MspInit(hi2s); - } - - hi2s->State = HAL_I2S_STATE_BUSY; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) - { - i2sodd = (uint32_t)0; - i2sdiv = (uint32_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get the source clock value: based on System Clock value */ - i2sclk = HAL_RCC_GetSysClockFreq(); - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) - { - /* MCLK output is enabled */ - tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint32_t)(tmp & (uint32_t)1); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint32_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint32_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - /* And configure the I2S with the I2S_InitStruct values */ - MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\ - SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\ - SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\ - (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\ - hi2s->Init.Standard | hi2s->Init.DataFormat |\ - hi2s->Init.CPOL)); - - /* Write to SPIx I2SPR register the computed value */ - hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State= HAL_I2S_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the I2S peripheral - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) -{ - /* Check the I2S handle allocation */ - if(hi2s == NULL) - { - return HAL_ERROR; - } - - hi2s->State = HAL_I2S_STATE_BUSY; - - /* Disable the I2S Peripheral Clock */ - __HAL_I2S_DISABLE(hi2s); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_I2S_MspDeInit(hi2s); - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief I2S MSP Init - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspInit could be implemented in the user file - */ -} - -/** - * @brief I2S MSP DeInit - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2S data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2S_Transmit() - (++) HAL_I2S_Receive() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2S_Transmit_IT() - (++) HAL_I2S_Receive_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2S_Transmit_DMA() - (++) HAL_I2S_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2S_TxCpltCallback() - (++) HAL_I2S_RxCpltCallback() - (++) HAL_I2S_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_READY) - { - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Set state and reset error code */ - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->pTxBuffPtr = pData; - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - while(hi2s->TxXferCount > 0) - { - /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); - hi2s->TxXferCount--; - } - - /* Wait until TXE flag is set, to confirm the end of the transcation */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Wait until Busy flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate - * in continouse way and as the I2S is not disabled at the end of the I2S transaction. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_READY) - { - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Set state and reset error code */ - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->pRxBuffPtr = pData; - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Receive data */ - while(hi2s->RxXferCount > 0) - { - /* Wait until RXNE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; - hi2s->RxXferCount--; - } - - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_READY) - { - hi2s->pTxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Enable TXE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation - * between Master and Slave otherwise the I2S interrupt should be optimized. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_READY) - { - hi2s->pRxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Enable TXE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Transmit data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_READY) - { - hi2s->pTxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Set the I2S Tx DMA Half transfert complete callback */ - hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; - - /* Set the I2S Tx DMA transfert complete callback */ - hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; - - /* Set the DMA error callback */ - hi2s->hdmatx->XferErrorCallback = I2S_DMAError; - - /* Enable the Tx DMA Channel */ - HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if the I2S Tx request is already enabled */ - if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) - { - /* Enable Tx DMA Request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_READY) - { - hi2s->pRxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - - /* Set the I2S Rx DMA Half transfert complete callback */ - hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; - - /* Set the I2S Rx DMA transfert complete callback */ - hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; - - /* Set the DMA error callback */ - hi2s->hdmarx->XferErrorCallback = I2S_DMAError; - - /* Check if Master Receiver mode is selected */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - /* Enable the Rx DMA Channel */ - HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize); - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if the I2S Rx request is already enabled */ - if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) - { - /* Enable Rx DMA Request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } -} - -/** - * @brief Pauses the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Disable the I2S DMA Tx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Disable the I2S DMA Rx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Enable the I2S DMA Tx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Enable the I2S DMA Rx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - - /* If the I2S peripheral is still not enabled, enable it */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA Channel tx */ - if(hi2s->hdmatx != NULL) - { - /* Disable the I2S DMA channel */ - __HAL_DMA_DISABLE(hi2s->hdmatx); - HAL_DMA_Abort(hi2s->hdmatx); - } - /* Abort the I2S DMA Channel rx */ - if(hi2s->hdmarx != NULL) - { - /* Disable the I2S DMA channel */ - __HAL_DMA_DISABLE(hi2s->hdmarx); - HAL_DMA_Abort(hi2s->hdmarx); - } - - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) -{ - uint32_t i2ssr = hi2s->Instance->SR; - - /* I2S in mode Receiver ------------------------------------------------*/ - if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) && - ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) - { - I2S_Receive_IT(hi2s); - return; - } - - /* I2S in mode Tramitter -----------------------------------------------*/ - if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) - { - I2S_Transmit_IT(hi2s); - return; - } - - /* I2S interrupt error -------------------------------------------------*/ - if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) - { - /* I2S Overrun error interrupt occured ---------------------------------*/ - if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); - } - - /* I2S Underrun error interrupt occured --------------------------------*/ - if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); - } - - /* I2S Frame format error interrupt occured --------------------------*/ - if((i2ssr & I2S_FLAG_FRE) == I2S_FLAG_FRE) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE); - } - - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - /* Call the Error Callback */ - HAL_I2S_ErrorCallback(hi2s); - } -} - -/** - * @brief Tx Transfer Half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2S error callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ - __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2S state - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL state - */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) -{ - return hi2s->State; -} - -/** - * @brief Return the I2S error code - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval I2S Error Code - */ -HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) -{ - return hi2s->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup I2S_Private_Functions I2S Private Functions - * @{ - */ -/** - * @brief DMA I2S transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - - hi2s->TxXferCount = 0; - hi2s->State = HAL_I2S_STATE_READY; - } - HAL_I2S_TxCpltCallback(hi2s); -} - -/** - * @brief DMA I2S transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_I2S_TxHalfCpltCallback(hi2s); -} - -/** - * @brief DMA I2S receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable Rx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - hi2s->RxXferCount = 0; - hi2s->State = HAL_I2S_STATE_READY; - } - HAL_I2S_RxCpltCallback(hi2s); -} - -/** - * @brief DMA I2S receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_I2S_RxHalfCpltCallback(hi2s); -} - -/** - * @brief DMA I2S communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMAError(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable Rx and Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0; - hi2s->RxXferCount = 0; - - hi2s->State= HAL_I2S_STATE_READY; - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - HAL_I2S_ErrorCallback(hi2s); -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) -{ - /* Transmit data */ - hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); - hi2s->TxXferCount--; - - if(hi2s->TxXferCount == 0) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - HAL_I2S_TxCpltCallback(hi2s); - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle - * @retval None - */ -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) -{ - /* Receive data */ - (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; - hi2s->RxXferCount--; - - if(hi2s->RxXferCount == 0) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - HAL_I2S_RxCpltCallback(hi2s); - } -} - - -/** - * @brief This function handles I2S Communication Timeout. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param Flag: Flag checked - * @param Status: Value of the flag expected - * @param Timeout: Duration of the timeout - * @retval HAL status - */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Set the I2S State ready */ - hi2s->State= HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Set the I2S State ready */ - hi2s->State= HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @} - */ -#endif /* STM32L100xC || - STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\ - STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE ||\\ - STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */ -#endif /* HAL_I2S_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c deleted file mode 100644 index de6eceb70..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c +++ /dev/null @@ -1,1571 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_irda.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief IRDA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the IrDA SIR ENDEC block (IrDA): - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The IRDA HAL driver can be used as follows: - - (#) Declare a IRDA_HandleTypeDef handle structure. - (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API: - (##) Enable the USARTx interface clock. - (##) IRDA pins configuration: - (+++) Enable the clock for the IRDA GPIOs. - (+++) Configure these IRDA pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() - and HAL_IRDA_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() - and HAL_IRDA_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler - and Mode(Receiver/Transmitter) in the hirda Init structure. - - (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_IRDA_MspInit() API. - - -@@- The specific IRDA interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() - (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback - - *** IRDA HAL driver macros list *** - ==================================== - [..] - Below the list of most used macros in IRDA HAL driver. - - (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral - (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral - (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not - (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag - (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt - (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt - - [..] - (@) You can refer to the IRDA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup IRDA IRDA - * @brief HAL IRDA module driver - * @{ - */ - -#ifdef HAL_IRDA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup IRDA_Private_Constants IRDA Private Constants - * @{ - */ -#define IRDA_TIMEOUT_VALUE 22000 -#define IRDA_DR_MASK_U16_7DATABITS (uint16_t)0x007F -#define IRDA_DR_MASK_U16_8DATABITS (uint16_t)0x00FF -#define IRDA_DR_MASK_U16_9DATABITS (uint16_t)0x01FF - -#define IRDA_DR_MASK_U8_7DATABITS (uint8_t)0x7F -#define IRDA_DR_MASK_U8_8DATABITS (uint8_t)0xFF - - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup IRDA_Private_Functions IRDA Private Functions - * @{ - */ -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); -static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup IRDA_Exported_Functions IRDA Exported Functions - * @{ - */ - -/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in IrDA mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible IRDA frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | IRDA frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). - (++) Mode: Receiver/transmitter modes - (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode. - - [..] - The HAL_IRDA_Init() function follows IRDA configuration procedures (details for the procedures - are available in reference manual (RM0038)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the IRDA mode according to the specified - * parameters in the IRDA_InitTypeDef and create the associated handle. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) -{ - /* Check the IRDA handle allocation */ - if(hirda == NULL) - { - return HAL_ERROR; - } - - /* Check the IRDA instance parameters */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - /* Check the IRDA mode parameter in the IRDA handle */ - assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode)); - - if(hirda->State == HAL_IRDA_STATE_RESET) - { - /* Init the low level hardware */ - HAL_IRDA_MspInit(hirda); - } - - hirda->State = HAL_IRDA_STATE_BUSY; - - /* Disable the IRDA peripheral */ - __HAL_IRDA_DISABLE(hirda); - - /* Set the IRDA communication parameters */ - IRDA_SetConfig(hirda); - - /* In IrDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN)); - CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); - - /* Enable the IRDA peripheral */ - __HAL_IRDA_ENABLE(hirda); - - /* Set the prescaler */ - MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); - - /* Configure the IrDA mode */ - MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode); - - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_IREN); - - /* Initialize the IRDA state*/ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->State= HAL_IRDA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the IRDA peripheral - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) -{ - /* Check the IRDA handle allocation */ - if(hirda == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - - hirda->State = HAL_IRDA_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_IRDA_DISABLE(hirda); - - /* DeInit the low level hardware */ - HAL_IRDA_MspDeInit(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->State = HAL_IRDA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief IRDA MSP Init. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ - __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_MspInit can be implemented in the user file - */ -} - -/** - * @brief IRDA MSP DeInit. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ - __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions - * @brief IRDA Transmit and Receive functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the IRDA data transfers. - - [..] - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The HAL_IRDA_ErrorCallback() user callback will be executed when a communication - error is detected - - (#) Blocking mode APIs are : - (++) HAL_IRDA_Transmit() - (++) HAL_IRDA_Receive() - - (#) Non Blocking mode APIs with Interrupt are : - (++) HAL_IRDA_Transmit_IT() - (++) HAL_IRDA_Receive_IT() - (++) HAL_IRDA_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (++) HAL_IRDA_Transmit_DMA() - (++) HAL_IRDA_Receive_DMA() - (++) HAL_IRDA_DMAPause() - (++) HAL_IRDA_DMAResume() - (++) HAL_IRDA_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_IRDA_TxHalfCpltCallback() - (++) HAL_IRDA_TxCpltCallback() - (++) HAL_IRDA_RxHalfCpltCallback() - (++) HAL_IRDA_RxCpltCallback() - (++) HAL_IRDA_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0) - { - if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) - { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData; - WRITE_REG(hirda->Instance->DR,(*tmp & IRDA_DR_MASK_U16_9DATABITS)); - if(hirda->Init.Parity == IRDA_PARITY_NONE) - { - pData +=2; - } - else - { - pData +=1; - } - } - else - { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - WRITE_REG(hirda->Instance->DR, (*pData++ & IRDA_DR_MASK_U8_8DATABITS)); - } - hirda->TxXferCount--; - } - - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - /* Check the remain data to be received */ - while(hirda->RxXferCount > 0) - { - if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) - { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData ; - if(hirda->Init.Parity == IRDA_PARITY_NONE) - { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS); - pData +=2; - } - else - { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS); - pData +=1; - } - } - else - { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if(hirda->Init.Parity == IRDA_PARITY_NONE) - { - *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS); - } - else - { - *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS); - } - } - hirda->RxXferCount--; - } - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non-blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp = 0; - - tmp = hirda->State; - if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - - /* Enable the IRDA Parity Error Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the IRDA Transmit Data Register Empty Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non-blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp = 0; - - tmp = hirda->State; - if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - - /* Enable the IRDA Data Register not empty Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); - - /* Enable the IRDA Parity Error Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non-blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; - - /* Set the IRDA DMA half transfert complete callback */ - hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmatx->XferErrorCallback = IRDA_DMAError; - - /* Enable the IRDA transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; - - /* Set the IRDA DMA half transfert complete callback */ - hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmarx->XferErrorCallback = IRDA_DMAError; - - /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the DMA Transfer. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) -{ - /* Process Locked */ - __HAL_LOCK(hirda); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - /* Disable the UART DMA Rx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx & Rx requests */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) -{ - /* Process Locked */ - __HAL_LOCK(hirda); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Enable the UART DMA Rx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Enable the UART DMA Tx & Rx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() - */ - - /* Disable the UART Tx/Rx DMA requests */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA tx channel */ - if(hirda->hdmatx != NULL) - { - HAL_DMA_Abort(hirda->hdmatx); - } - /* Abort the UART DMA rx channel */ - if(hirda->hdmarx != NULL) - { - HAL_DMA_Abort(hirda->hdmarx); - } - - hirda->State = HAL_IRDA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles IRDA interrupt request. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE); - /* IRDA parity error interrupt occurred -----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_IRDA_CLEAR_PEFLAG(hirda); - hirda->ErrorCode |= HAL_IRDA_ERROR_PE; - } - - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); - /* IRDA frame error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_IRDA_CLEAR_FEFLAG(hirda); - hirda->ErrorCode |= HAL_IRDA_ERROR_FE; - } - - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); - /* IRDA noise error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_IRDA_CLEAR_NEFLAG(hirda); - hirda->ErrorCode |= HAL_IRDA_ERROR_NE; - } - - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); - /* IRDA Over-Run interrupt occurred ---------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_IRDA_CLEAR_OREFLAG(hirda); - hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; - } - - /* Call the Error call Back in case of Errors */ - if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) - { - /* Disable PE and ERR interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; - HAL_IRDA_ErrorCallback(hirda); - } - - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE); - /* IRDA in mode Receiver --------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - IRDA_Receive_IT(hirda); - } - - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE); - /* IRDA in mode Transmitter -----------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - IRDA_Transmit_IT(hirda); - } - - tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC); - tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC); - /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - IRDA_EndTransmit_IT(hirda); - } - -} - -/** - * @brief Tx Transfer completed callbacks. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ - __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ - __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer complete callbacks. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief IRDA error callbacks. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ - __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_ErrorCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief IRDA State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of IrDA - communication process and also return Peripheral Errors occurred during communication process - (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state - of the IRDA peripheral. - (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during - communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the IRDA state. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL state - */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) -{ - return hirda->State; -} - -/** - * @brief Return the IRDA error code - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval IRDA Error Code - */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) -{ - return hirda->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IRDA_Private_Functions IRDA Private Functions - * @brief IRDA Private functions - * @{ - */ -/** - * @brief DMA IRDA transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - hirda->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Wait for IRDA TC Flag */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - hirda->State = HAL_IRDA_STATE_TIMEOUT; - HAL_IRDA_ErrorCallback(hirda); - } - else - { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - HAL_IRDA_TxCpltCallback(hirda); - } - } - /* DMA Circular mode */ - else - { - HAL_IRDA_TxCpltCallback(hirda); - } -} - -/** - * @brief DMA IRDA receive process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_IRDA_TxHalfCpltCallback(hirda); -} - -/** - * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - hirda->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the IRDA CR3 register */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - } - - HAL_IRDA_RxCpltCallback(hirda); -} - -/** - * @brief DMA IRDA receive process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_IRDA_RxHalfCpltCallback(hirda); -} - -/** - * @brief DMA IRDA communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMAError(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; - hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; - hirda->State= HAL_IRDA_STATE_READY; - - HAL_IRDA_ErrorCallback(hirda); -} - -/** - * @brief This function handles IRDA Communication Timeout. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param Flag: specifies the IRDA flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State= HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State= HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Send an amount of data in non-blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Transmit_IT() - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) - { - if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) - { - tmp = (uint16_t*) hirda->pTxBuffPtr; - WRITE_REG(hirda->Instance->DR, (uint16_t)(*tmp & IRDA_DR_MASK_U16_9DATABITS)); - if(hirda->Init.Parity == IRDA_PARITY_NONE) - { - hirda->pTxBuffPtr += 2; - } - else - { - hirda->pTxBuffPtr += 1; - } - } - else - { - WRITE_REG(hirda->Instance->DR, (uint8_t)(*hirda->pTxBuffPtr++ & IRDA_DR_MASK_U8_8DATABITS)); - } - - if(--hirda->TxXferCount == 0) - { - /* Disable the IRDA Transmit Data Register Empty Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) -{ - /* Disable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - - hirda->State = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_TxCpltCallback(hirda); - - return HAL_OK; -} - - -/** - * @brief Receive an amount of data in non-blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hirda->State; - if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX)) - { - if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) - { - tmp = (uint16_t*) hirda->pRxBuffPtr; - if(hirda->Init.Parity == IRDA_PARITY_NONE) - { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS); - hirda->pRxBuffPtr += 2; - } - else - { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS); - hirda->pRxBuffPtr += 1; - } - } - else - { - if(hirda->Init.Parity == IRDA_PARITY_NONE) - { - *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS); - } - else - { - *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS); - } - } - - if(--hirda->RxXferCount == 0) - { - - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } - HAL_IRDA_RxCpltCallback(hirda); - - return HAL_OK; - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configures the IRDA peripheral. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) -{ - /* Check the parameters */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); - assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); - assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); - assert_param(IS_IRDA_MODE(hirda->Init.Mode)); - - /*-------------------------- IRDA CR2 Configuration ------------------------*/ - /* Clear STOP[13:12] bits */ - CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to hirda->Init.WordLength value - Set PCE and PS bits according to hirda->Init.Parity value - Set TE and RE bits according to hirda->Init.Mode value */ - MODIFY_REG(hirda->Instance->CR1, - ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), - (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Clear CTSE and RTSE bits */ - CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); - - /*-------------------------- USART BRR Configuration -----------------------*/ - if(hirda->Instance == USART1) - { - hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate); - } - else - { - hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate); - } -} -/** - * @} - */ - -#endif /* HAL_IRDA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c deleted file mode 100644 index 39f65ba16..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c +++ /dev/null @@ -1,360 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_iwdg.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief IWDG HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the IWDG peripheral: - * + Initialization and Configuration functions - * + IO operation functions - * + Peripheral State functions - * - @verbatim - -================================================================================ - ##### IWDG specific features ##### -================================================================================ - [..] - (+) The IWDG can be started by either software or hardware (configurable - through option byte). - (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and - thus stays active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. - (+) The IWDG counter should be refreshed at regular intervals, otherwise the - watchdog generates an MCU reset when the counter reaches 0. - (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG - reset occurs. - - (+) Min-max timeout value @37KHz (LSI): ~108us / ~28.3s - The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM10 CH1 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. - For more information, please refer to the STM32L1xx Reference manual. - - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Set the IWDG prescaler and reload value - using HAL_IWDG_Init() function. - (+) Use IWDG using HAL_IWDG_Start() function to: - (++) Enable write access to IWDG_PR and IWDG_RLR registers. - (++) Configure the IWDG prescaler and counter reload values. - (++) Reload IWDG counter with value defined in the IWDG_RLR register. - (++) Start the IWDG, when the IWDG is used in software mode (no need - to enable the LSI, it will be enabled by hardware). - (+) Then the application program must refresh the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. - - *** IWDG HAL driver macros list *** - ==================================== - [..] - Below the list of most used macros in IWDG HAL driver. - - (+) __HAL_IWDG_START: Enable the IWDG peripheral - (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register - (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers - (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers - (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status - (+) __HAL_IWDG_CLEAR_FLAG: Clear the IWDG's pending flags - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup IWDG IWDG - * @brief IWDG HAL module driver. - * @{ - */ - -#ifdef HAL_IWDG_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Defines IWDG Private Defines - * @{ - */ - -#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000 - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Functions IWDG Exported Functions - * @{ - */ - -/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters - in the IWDG_InitTypeDef and create the associated handle - (+) Initialize the IWDG MSP - (+) DeInitialize IWDG MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the IWDG according to the specified - * parameters in the IWDG_InitTypeDef and creates the associated handle. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) -{ - /* Check the IWDG handle allocation */ - if(hiwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); - assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); - assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); - - /* Check pending flag, if previous update not done, return error */ - if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)) - { - return HAL_ERROR; - } - - if(hiwdg->State == HAL_IWDG_STATE_RESET) - { - /* Init the low level hardware */ - HAL_IWDG_MspInit(hiwdg); - } - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - /* Enable write access to IWDG_PR and IWDG_RLR registers */ - __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg); - - /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ - MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); - MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the IWDG MSP. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval None - */ -__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_IWDG_MspInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start the IWDG. - (+) Refresh the IWDG. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) -{ - /* Process Locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - /* Start the IWDG peripheral */ - __HAL_IWDG_START(hiwdg); - - /* Reload IWDG counter with value defined in the RLR register */ - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Refreshes the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - tickstart = HAL_GetTick(); - - /* Wait until RVU flag is RESET */ - while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - { - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hiwdg); - - return HAL_TIMEOUT; - } - } - - /* Reload IWDG counter with value defined in the reload register */ - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the IWDG state. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL state - */ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) -{ - return hiwdg->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_IWDG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c deleted file mode 100644 index e77f978ee..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c +++ /dev/null @@ -1,610 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_lcd.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief LCD Controller HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the LCD Controller (LCD) peripheral: - * + Initialization/de-initialization methods - * + I/O operation methods - * + Peripheral State methods - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] The LCD HAL driver can be used as follows: - - (#) Declare a LCD_HandleTypeDef handle structure. - - (#) Initialize the LCD low level resources by implement the HAL_LCD_MspInit() API: - (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows: - (+) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and - selected clock source (HSE, LSI or LSE) - - -@- The frequency generator allows you to achieve various LCD frame rates - starting from an LCD input clock frequency (LCDCLK) which can vary - from 32 kHz up to 1 MHz. - (##) LCD pins configuration: - (+) Enable the clock for the LCD GPIOs. - (+) Configure these LCD pins as alternate function no-pull. - (##) Enable the LCD interface clock. - - (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias, - Voltage Source, Dead Time, Pulse On Duration and Contrast in the hlcd Init structure. - - (#) Initialize the LCD registers by calling the HAL_LCD_Init() API. - - -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc) - by calling the custumed HAL_LCD_MspInit() API. - -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared - - (#) Optionally you can update the LCD configuration using these macros: - (+) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros - (+) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro - (+) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro - (+) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro - (+) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro - - (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called - more time to update the different LCD RAM registers before calling - HAL_LCD_UpdateDisplayRequest() API. - - (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory. - - (#) When LCD RAM memory is updated enable the update display request using - the HAL_LCD_UpdateDisplayRequest() API. - - [..] LCD and low power modes: - (#) The LCD remain active during STOP mode. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_LCD_MODULE_ENABLED - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) - -/** @defgroup LCD LCD - * @brief LCD HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup LCD_Private_Defines LCD Private Defines - * @{ - */ - -#define LCD_TIMEOUT_VALUE 1000 - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup LCD_Exported_Functions LCD Exported Functions - * @{ - */ - -/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - -@endverbatim - * @{ - */ - -/** - * @brief DeInitializes the LCD peripheral. - * @param hlcd: LCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) -{ - /* Check the LCD handle allocation */ - if(hlcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); - - hlcd->State = HAL_LCD_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_LCD_MspDeInit(hlcd); - - hlcd->ErrorCode = HAL_LCD_ERROR_NONE; - hlcd->State = HAL_LCD_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hlcd); - - return HAL_OK; -} - -/** - * @brief Initializes the LCD peripheral according to the specified parameters - * in the LCD_InitStruct. - * @note This function can be used only when the LCD is disabled. - * @param hlcd: LCD handle - * @retval None - */ -HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) -{ - uint32_t tickstart = 0x00; - uint8_t counter = 0; - - /* Check the LCD handle allocation */ - if(hlcd == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); - assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler)); - assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider)); - assert_param(IS_LCD_DUTY(hlcd->Init.Duty)); - assert_param(IS_LCD_BIAS(hlcd->Init.Bias)); - assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource)); - assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration)); - assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime)); - assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); - assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); - assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); - assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment)); - - if(hlcd->State == HAL_LCD_STATE_RESET) - { - /* Initialize the low level hardware (MSP) */ - HAL_LCD_MspInit(hlcd); - } - - hlcd->State = HAL_LCD_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_LCD_DISABLE(hlcd); - - /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit - in the LCD_SR register */ - for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) - { - hlcd->Instance->RAM[counter] = 0; - } - /* Enable the display request */ - hlcd->Instance->SR |= LCD_SR_UDR; - - /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: - Set PS[3:0] bits according to hlcd->Init.Prescaler value - Set DIV[3:0] bits according to hlcd->Init.Divider value - Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value - Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value - Set DEAD[2:0] bits according to hlcd->Init.DeadTime value - Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value - Set CC[2:0] bits according to hlcd->Init.Contrast value */ - MODIFY_REG(hlcd->Instance->FCR, \ - (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \ - LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \ - (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ - hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast)); - - /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register - This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK - domain. It is cleared by hardware when writing to the LCD_FCR register.*/ - LCD_WaitForSynchro(hlcd); - - /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast: - Set DUTY[2:0] bits according to hlcd->Init.Duty value - Set BIAS[1:0] bits according to hlcd->Init.Bias value - Set VSEL bit according to hlcd->Init.VoltageSource value - Set MUX_SEG bit according to hlcd->Init.MuxSegment value */ - MODIFY_REG(hlcd->Instance->CR, \ - (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \ - (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment)); - - /* Enable the peripheral */ - __HAL_LCD_ENABLE(hlcd); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait Until the LCD is enabled */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET) - { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) - { - hlcd->ErrorCode = HAL_LCD_ERROR_ENS; - return HAL_TIMEOUT; - } - } - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /*!< Wait Until the LCD Booster is ready */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) - { - hlcd->ErrorCode = HAL_LCD_ERROR_RDY; - return HAL_TIMEOUT; - } - } - - /* Initialize the LCD state */ - hlcd->ErrorCode = HAL_LCD_ERROR_NONE; - hlcd->State= HAL_LCD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief LCD MSP DeInit. - * @param hlcd: LCD handle - * @retval None - */ - __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_LCD_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief LCD MSP Init. - * @param hlcd: LCD handle - * @retval None - */ - __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_LCD_MspInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup LCD_Exported_Functions_Group2 IO operation methods - * @brief LCD RAM functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] Using its double buffer memory the LCD controller ensures the coherency of the - displayed information without having to use interrupts to control LCD_RAM - modification. - The application software can access the first buffer level (LCD_RAM) through - the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API, - it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API. - This UDR flag (update display request) requests the updated information to be - moved into the second buffer level (LCD_DISPLAY). - This operation is done synchronously with the frame (at the beginning of the - next frame), until the update is completed, the LCD_RAM is write protected and - the UDR flag stays high. - Once the update is completed another flag (UDD - Update Display Done) is set and - generates an interrupt if the UDDIE bit in the LCD_FCR register is set. - The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one - even frame. - The update will not occur (UDR = 1 and UDD = 0) until the display is - enabled (LCDEN = 1). - -@endverbatim - * @{ - */ - -/** - * @brief Writes a word in the specific LCD RAM. - * @param hlcd: LCD handle - * @param RAMRegisterIndex: specifies the LCD RAM Register. - * This parameter can be one of the following values: - * @arg LCD_RAM_REGISTER0: LCD RAM Register 0 - * @arg LCD_RAM_REGISTER1: LCD RAM Register 1 - * @arg LCD_RAM_REGISTER2: LCD RAM Register 2 - * @arg LCD_RAM_REGISTER3: LCD RAM Register 3 - * @arg LCD_RAM_REGISTER4: LCD RAM Register 4 - * @arg LCD_RAM_REGISTER5: LCD RAM Register 5 - * @arg LCD_RAM_REGISTER6: LCD RAM Register 6 - * @arg LCD_RAM_REGISTER7: LCD RAM Register 7 - * @arg LCD_RAM_REGISTER8: LCD RAM Register 8 - * @arg LCD_RAM_REGISTER9: LCD RAM Register 9 - * @arg LCD_RAM_REGISTER10: LCD RAM Register 10 - * @arg LCD_RAM_REGISTER11: LCD RAM Register 11 - * @arg LCD_RAM_REGISTER12: LCD RAM Register 12 - * @arg LCD_RAM_REGISTER13: LCD RAM Register 13 - * @arg LCD_RAM_REGISTER14: LCD RAM Register 14 - * @arg LCD_RAM_REGISTER15: LCD RAM Register 15 - * @param RAMRegisterMask: specifies the LCD RAM Register Data Mask. - * @param Data: specifies LCD Data Value to be written. - * @retval None - */ -HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data) -{ - uint32_t tickstart = 0x00; - - if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) - { - /* Check the parameters */ - assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex)); - - if(hlcd->State == HAL_LCD_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hlcd); - hlcd->State = HAL_LCD_STATE_BUSY; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /*!< Wait Until the LCD is ready */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) - { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) - { - hlcd->ErrorCode = HAL_LCD_ERROR_UDR; - - /* Process Unlocked */ - __HAL_UNLOCK(hlcd); - - return HAL_TIMEOUT; - } - } - } - - /* Copy the new Data bytes to LCD RAM register */ - MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Clears the LCD RAM registers. - * @param hlcd: LCD handle - * @retval None - */ -HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) -{ - uint32_t tickstart = 0x00; - uint32_t counter = 0; - - if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) - { - /* Process Locked */ - __HAL_LOCK(hlcd); - - hlcd->State = HAL_LCD_STATE_BUSY; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /*!< Wait Until the LCD is ready */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) - { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) - { - hlcd->ErrorCode = HAL_LCD_ERROR_UDR; - - /* Process Unlocked */ - __HAL_UNLOCK(hlcd); - - return HAL_TIMEOUT; - } - } - /* Clear the LCD_RAM registers */ - for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) - { - hlcd->Instance->RAM[counter] = 0; - } - - /* Update the LCD display */ - HAL_LCD_UpdateDisplayRequest(hlcd); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enables the Update Display Request. - * @param hlcd: LCD handle - * @note Each time software modifies the LCD_RAM it must set the UDR bit to - * transfer the updated data to the second level buffer. - * The UDR bit stays set until the end of the update and during this - * time the LCD_RAM is write protected. - * @note When the display is disabled, the update is performed for all - * LCD_DISPLAY locations. - * When the display is enabled, the update is performed only for locations - * for which commons are active (depending on DUTY). For example if - * DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated. - * @retval None - */ -HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) -{ - uint32_t tickstart = 0x00; - - /* Clear the Update Display Done flag before starting the update display request */ - __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD); - - /* Enable the display request */ - hlcd->Instance->SR |= LCD_SR_UDR; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /*!< Wait Until the LCD display is done */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET) - { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) - { - hlcd->ErrorCode = HAL_LCD_ERROR_UDD; - - /* Process Unlocked */ - __HAL_UNLOCK(hlcd); - - return HAL_TIMEOUT; - } - } - - hlcd->State = HAL_LCD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hlcd); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods - * @brief LCD State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the LCD: - (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State. - (+) HAL_LCD_GetError() API to return the LCD error code. -@endverbatim - * @{ - */ - -/** - * @brief Returns the LCD state. - * @param hlcd: LCD handle - * @retval HAL state - */ -HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd) -{ - return hlcd->State; -} - -/** - * @brief Return the LCD error code - * @param hlcd: LCD handle - * @retval LCD Error Code - */ -uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd) -{ - return hlcd->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup LCD_Private_Functions LCD Private Functions - * @{ - */ - -/** - * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain. - * This function must be called after any write operation to LCD_FCR register. - * @retval None - */ -HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) -{ - uint32_t tickstart = 0x00; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Loop until FCRSF flag is set */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET) - { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) - { - hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF; - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */ - -#endif /* HAL_LCD_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c deleted file mode 100644 index 75c0a849c..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c +++ /dev/null @@ -1,838 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_nor.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief NOR HAL module driver. - * This file provides a generic firmware to drive NOR memories mounted - * as external device. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control NOR flash memories. It uses the FSMC layer functions to interface - with NOR devices. This driver is used as follows: - - (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() - with control and timing parameters for both normal and extended mode. - - (+) Read NOR flash memory manufacturer code and device IDs using the function - HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef - structure declared by the function caller. - - (+) Access NOR flash memory by read/write data unit operations using the functions - HAL_NOR_Read(), HAL_NOR_Program(). - - (+) Perform NOR flash erase block/chip operations using the functions - HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). - - (+) Read the NOR flash CFI (common flash interface) IDs using the function - HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef - structure declared by the function caller. - - (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ - HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation - - (+) You can monitor the NOR device HAL state by calling the function - HAL_NOR_GetState() - [..] - (@) This driver is a set of generic APIs which handle standard NOR flash operations. - If a NOR flash device contains different operations and/or implementations, - it should be implemented separately. - - *** NOR HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in NOR HAL driver. - - (+) __NOR_WRITE : NOR memory write data to specified address - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup NOR NOR - * @brief NOR driver modules - * @{ - */ -#ifdef HAL_NOR_MODULE_ENABLED -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/** @defgroup NOR_Private_Variables NOR Private Variables - * @{ - */ - -static uint32_t uwNORAddress = NOR_MEMORY_ADRESS1; -static uint32_t uwNORMememoryDataWidth = NOR_MEMORY_8B; - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup NOR_Exported_Functions NOR Exported Functions - * @{ - */ - -/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### NOR Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize - the NOR memory - -@endverbatim - * @{ - */ - -/** - * @brief Perform the NOR memory Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Timing: pointer to NOR control timing structure - * @param ExtTiming: pointer to NOR extended mode timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) -{ - /* Check the NOR handle parameter */ - if(hnor == NULL) - { - return HAL_ERROR; - } - - if(hnor->State == HAL_NOR_STATE_RESET) - { - /* Initialize the low level hardware (MSP) */ - HAL_NOR_MspInit(hnor); - } - - /* Initialize NOR control Interface */ - FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); - - /* Initialize NOR timing Interface */ - FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); - - /* Initialize NOR extended mode timing Interface */ - FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); - - /* Enable the NORSRAM device */ - __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); - - /* Initialize NOR address mapped by FSMC */ - if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM1) - { - uwNORAddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM2) - { - uwNORAddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM3) - { - uwNORAddress = NOR_MEMORY_ADRESS3; - } - else - { - uwNORAddress = NOR_MEMORY_ADRESS4; - } - - /* Initialize NOR Memory Data Width*/ - if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8) - { - uwNORMememoryDataWidth = NOR_MEMORY_8B; - } - else - { - uwNORMememoryDataWidth = NOR_MEMORY_16B; - } - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Perform NOR memory De-Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) -{ - /* De-Initialize the low level hardware (MSP) */ - HAL_NOR_MspDeInit(hnor); - - /* Configure the NOR registers with their reset values */ - FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief NOR MSP Init - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval None - */ -__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspInit could be implemented in the user file - */ -} - -/** - * @brief NOR MSP DeInit - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval None - */ -__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief NOR BSP Wait fro Ready/Busy signal - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Timeout: Maximum timeout value - * @retval None - */ -__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_BspWait could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### NOR Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the NOR memory - -@endverbatim - * @{ - */ - -/** - * @brief Read NOR flash IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pNOR_ID : pointer to NOR ID structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read ID command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0090); - - /* Read the NOR IDs */ - pNOR_ID->ManufacturerCode = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, MC_ADDRESS); - pNOR_ID->DeviceCode1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->DeviceCode2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->DeviceCode3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE3_ADDR); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Returns the NOR memory to Read mode. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - __NOR_WRITE(uwNORAddress, 0x00F0); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Read data from NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pAddress: pointer to Device address - * @param pData : pointer to read data - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055); - __NOR_WRITE(*pAddress, 0x00F0); - - /* Read the data */ - *pData = *(__IO uint32_t *)pAddress; - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Program data to NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pAddress: Device address - * @param pData : pointer to the data to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send program data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00A0); - - /* Write the data */ - __NOR_WRITE(pAddress, *pData); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Reads a block of data from the FSMC NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param uwAddress: NOR memory internal address to read from. - * @param pData: pointer to the buffer that receives the data read from the - * NOR memory. - * @param uwBufferSize : number of Half word to read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read data command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055); - __NOR_WRITE(uwAddress, 0x00F0); - - /* Read buffer */ - while( uwBufferSize > 0) - { - *pData++ = *(__IO uint16_t *)uwAddress; - uwAddress += 2; - uwBufferSize--; - } - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Writes a half-word buffer to the FSMC NOR memory. This function - * must be used only with S29GL128P NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param uwAddress: NOR memory internal address from which the data - * @param pData: pointer to source data buffer. - * @param uwBufferSize: number of Half words to write. The maximum allowed - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) -{ - uint32_t lastloadedaddress = 0; - uint32_t currentaddress = 0; - uint32_t endaddress = 0; - - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Initialize variables */ - currentaddress = uwAddress; - endaddress = uwAddress + uwBufferSize - 1; - lastloadedaddress = uwAddress; - - /* Issue unlock command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - - /* Write Buffer Load Command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), 0x25); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), (uwBufferSize - 1)); - - /* Load Data into NOR Buffer */ - while(currentaddress <= endaddress) - { - /* Store last loaded address & data value (for polling) */ - lastloadedaddress = currentaddress; - - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, currentaddress), *pData++); - - currentaddress += 1; - } - - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, lastloadedaddress), 0x29); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; - -} - -/** - * @brief Erase the specified block of the NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param BlockAddress : Block to erase address - * @param Address: Device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send block erase command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30); - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; - -} - -/** - * @brief Erase the entire NOR chip. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address : Device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send NOR chip erase command sequence */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0010); - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Read NOR flash CFI IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pNOR_CFI : pointer to NOR CFI IDs structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read CFI query command */ - __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0055), 0x0098); - - /* read the NOR CFI information */ - pNOR_CFI->CFI1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI4_ADDRESS); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group3 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### NOR Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the NOR interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Enable write operation */ - FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief Disables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) -{ - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the SRAM controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Disable write operation */ - FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### NOR State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the NOR controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief return the NOR controller state - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval NOR controller state - */ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) -{ - return hnor->State; -} - -/** - * @brief Returns the NOR operation status. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address: Device address - * @param Timeout: NOR progamming Timeout - * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR - * or NOR_TIMEOUT - */ -NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) -{ - NOR_StatusTypedef status = NOR_ONGOING; - uint16_t tmpSR1 = 0, tmpSR2 = 0; - uint32_t tickstart = 0; - - /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ - HAL_NOR_MspWait(hnor, Timeout); - - /* Get the NOR memory operation status -------------------------------------*/ - while(status != NOR_TIMEOUT) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - status = NOR_TIMEOUT; - } - - /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) - { - return NOR_SUCCESS; - } - - if((tmpSR1 & 0x0020) == 0x0020) - { - return NOR_ONGOING; - } - - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) - { - return NOR_SUCCESS; - } - - if((tmpSR1 & 0x0020) == 0x0020) - { - return NOR_ERROR; - } - } - - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#endif /* HAL_NOR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c deleted file mode 100644 index c159523f3..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c +++ /dev/null @@ -1,1004 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_opamp.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief OPAMP HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the operational amplifiers (OPAMP1 ,... ,OPAMP3) - * peripheral: - * + OPAMP configuration - * + OPAMP calibration - * - * Thanks to - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim -================================================================================ - ##### OPAMP Peripheral Features ##### -================================================================================ - - [..] The device integrates up to 3 operational amplifiers OPAMP1, OPAMP2, - OPAMP3 (OPAMP3 availability depends on device category) - - (#) The OPAMP(s) provides several exclusive running modes. - (+) Standalone mode - (+) Follower mode - - (#) The OPAMP(s) provide(s) calibration capabilities. - (+) Calibration aims at correcting some offset for running mode. - (+) The OPAMP uses either factory calibration settings OR user defined - calibration (trimming) settings (i.e. trimming mode). - (+) The user defined settings can be figured out using self calibration - handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll - (+) HAL_OPAMP_SelfCalibrate: - (++) Runs automatically the calibration in 2 steps: for transistors - differential pair high (PMOS) or low (NMOS) - (++) Enables the user trimming mode - (++) Updates the init structure with trimming values with fresh calibration - results. - The user may store the calibration results for larger - (ex monitoring the trimming as a function of temperature - for instance) - (++) for devices having several OPAMPs, HAL_OPAMPEx_SelfCalibrateAll - runs calibration of all OPAMPs in parallel to save trimming search - wait time. - - (#) Running mode: Standalone mode - (+) Gain is set externally (gain depends on external loads). - (+) Follower mode also possible externally by connecting the inverting input to - the output. - - (#) Running mode: Follower mode - (+) No Inverting Input is connected. - (+) The OPAMP(s) output(s) are internally connected to inverting input - - (#) The OPAMPs inverting input can be selected among the list shown - in table below. - - (#) The OPAMPs non inverting input can be selected among the list shown - in table below. - - [..] Table 1. OPAMPs inverting/non-inverting inputs for STM32L1 devices: - - +--------------------------------------------------------------------------+ - | | HAL param | OPAMP1 | OPAMP2 | OPAMP3(4) | - | | name | | | | - |----------------|------------|--------------|--------------|--------------| - | Inverting | VM0 | PA2 | PA7 | PC2 | - | input (1) | VM1 | VINM pin (2) | VINM pin (2) | VINM pin (2) | - |----------------|------------|--------------|--------------|--------------| - | Non Inverting | VP0 | PA1 | PA6 | PC1 | - | input | DAC_CH1 (3)| DAC_CH1 | DAC_CH1 | --- | - | | DAC_CH2 (3)| --- | DAC_CH2 | DAC_CH2 | - +--------------------------------------------------------------------------+ - (1): NA in follower mode. - (2): OPAMP input OPAMPx_VINM are dedicated OPAMP pins, their availability - depends on device package. - (3): DAC channels 1 and 2 are connected internally to OPAMP. Nevertheless, - I/O pins connected to DAC can still be used as DAC output (pins PA4 - and PA5). - (4): OPAMP3 availability depends on device category. - - - [..] Table 2. OPAMPs outputs for STM32L1 devices: - - +--------------------------------------------------------+ - | | OPAMP1 | OPAMP2 | OPAMP3(4) | - |-----------------|------------|------------|------------| - | Output | PA3 | PB0 | PC3 | - +--------------------------------------------------------+ - (4) : OPAMP3 availability depends on device category - - - ##### How to use this driver ##### -================================================================================ - [..] - - *** Calibration *** - ============================================ - To run the opamp calibration self calibration: - - (#) Start calibration using HAL_OPAMP_SelfCalibrate. - Store the calibration results. - - *** Running mode *** - ============================================ - - To use the opamp, perform the following steps: - - (#) Fill in the HAL_OPAMP_MspInit() to - (+) Enable the OPAMP Peripheral clock using macro "__OPAMP_CLK_ENABLE()" - (++) Configure the opamp input AND output in analog mode using - HAL_GPIO_Init() to map the opamp output to the GPIO pin. - - (#) Configure the opamp using HAL_OPAMP_Init() function: - (+) Select the mode - (+) Select the inverting input - (+) Select the non-inverting input - (+) Select either factory or user defined trimming mode. - (+) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values - (typ. settings returned by HAL_OPAMP_SelfCalibrate function). - - (#) Enable the opamp using HAL_OPAMP_Start() function. - - (#) Disable the opamp using HAL_OPAMP_Stop() function. - - (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. - Caution: On STM32L1, HAL OPAMP lock is software lock only (not - hardware lock as on some other STM32 devices) - - (#) If needed, unlock the opamp using HAL_OPAMPEx_Unlock() function. - - *** Running mode: change of configuration while OPAMP ON *** - ============================================ - To Re-configure OPAMP when OPAMP is ON (change on the fly) - (#) If needed, Fill in the HAL_OPAMP_MspInit() - (+) This is the case for instance if you wish to use new OPAMP I/O - - (#) Configure the opamp using HAL_OPAMP_Init() function: - (+) As in configure case, selects first the parameters you wish to modify. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup OPAMP OPAMP - * @brief OPAMP HAL module driver - * @{ - */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions - * @{ - */ - -/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the OPAMP according to the specified - * parameters in the OPAMP_InitTypeDef and create the associated handle. - * @note If the selected opamp is locked, initialization can't be performed. - * To unlock the configuration, perform a system reset. - * @param hopamp: OPAMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp_csr = 0; /* Temporary variable to update register CSR, except bits ANAWSSELx, S7SEL2, OPA_RANGE, OPAxCALOUT */ - - /* Check the OPAMP handle allocation and lock status */ - /* Init not allowed if calibration is ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) ) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - /* Set OPAMP parameters */ - assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); - assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput)); - assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); - assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange)); - assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); - - if (hopamp->Init.Mode != OPAMP_FOLLOWER_MODE) - { - assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput)); - } - - if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) - { - if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP)); - assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN)); - } - else - { - assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower)); - assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower)); - } - } - - /* Call MSP init function */ - HAL_OPAMP_MspInit(hopamp); - - - /* Set OPAMP parameters */ - /* - Set internal switches in function of: */ - /* - OPAMP selected mode: standalone or follower. */ - /* - Non-inverting input connection */ - /* - Inverting input connection */ - /* - Set power supply range */ - /* - Set power mode and associated calibration parameters */ - - /* Get OPAMP CSR register into temporary variable */ - tmp_csr = OPAMP->CSR; - - /* Open all switches on non-inverting input, inverting input and output */ - /* feedback. */ - CLEAR_BIT(tmp_csr, __OPAMP_CSR_ALL_SWITCHES(hopamp)); - - /* Set internal switches in function of OPAMP mode selected: standalone */ - /* or follower. */ - /* If follower mode is selected, feedback switch S3 is closed and */ - /* inverting inputs switches are let opened. */ - /* If standalone mode is selected, feedback switch S3 is let opened and */ - /* the selected inverting inputs switch is closed. */ - if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE) - { - /* Follower mode: Close switches S3 and SanB */ - SET_BIT(tmp_csr, __OPAMP_CSR_S3SELX(hopamp)); - } - else - { - /* Set internal switches in function of inverting input selected: */ - /* Close switch to connect comparator inverting input to the selected */ - /* input: dedicated IO pin or alternative IO pin available on some */ - /* device packages. */ - if (hopamp->Init.InvertingInput == OPAMP_INVERTINGINPUT_VM0) - { - /* Close switch to connect comparator non-inverting input to */ - /* dedicated IO pin low-leakage. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S4SELX(hopamp)); - } - else - { - /* Close switch to connect comparator inverting input to alternative */ - /* IO pin available on some device packages. */ - SET_BIT(tmp_csr, __OPAMP_CSR_ANAWSELX(hopamp)); - } - } - - /* Set internal switches in function of non-inverting input selected: */ - /* Close switch to connect comparator non-inverting input to the selected */ - /* input: dedicated IO pin or DAC channel. */ - if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_VP0) - { - /* Close switch to connect comparator non-inverting input to */ - /* dedicated IO pin low-leakage. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S5SELX(hopamp)); - } - else if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_DAC_CH1) - { - - /* Particular case for connection to DAC channel 1: */ - /* OPAMP_NONINVERTINGINPUT_DAC_CH1 available on OPAMP1 and OPAMP2 only */ - /* (OPAMP3 availability depends on device category). */ - if ((hopamp->Instance == OPAMP1) || (hopamp->Instance == OPAMP2)) - { - /* Close switch to connect comparator non-inverting input to */ - /* DAC channel 1. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); - } - else - { - /* Set HAL status to error if another OPAMP instance as OPAMP1 or */ - /* OPAMP2 is intended to be connected to DAC channel 2. */ - status = HAL_ERROR; - } - } - else /* if (hopamp->Init.NonInvertingInput == */ - /* OPAMP_NONINVERTINGINPUT_DAC_CH2 ) */ - { - /* Particular case for connection to DAC channel 2: */ - /* OPAMP_NONINVERTINGINPUT_DAC_CH2 available on OPAMP2 and OPAMP3 only */ - /* (OPAMP3 availability depends on device category). */ - if (hopamp->Instance == OPAMP2) - { - /* Close switch to connect comparator non-inverting input to */ - /* DAC channel 2. */ - SET_BIT(tmp_csr, OPAMP_CSR_S7SEL2); - } - /* If OPAMP3 is selected (if available) */ - else if (hopamp->Instance != OPAMP1) - { - /* Close switch to connect comparator non-inverting input to */ - /* DAC channel 2. */ - SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); - } - else - { - /* Set HAL status to error if another OPAMP instance as OPAMP2 or */ - /* OPAMP3 (if available) is intended to be connected to DAC channel 2.*/ - status = HAL_ERROR; - } - } - - /* Continue OPAMP configuration if settings of switches are correct */ - if (status != HAL_ERROR) - { - /* Set power mode and associated calibration parameters */ - if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Set normal mode */ - CLEAR_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); - - if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) - { - /* Set calibration mode (factory or user) and values for */ - /* transistors differential pair high (PMOS) and low (NMOS) for */ - /* normal mode. */ - MODIFY_REG(OPAMP->OTR, OPAMP_OTR_OT_USER | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , - hopamp->Init.UserTrimming | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueN) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValueP) ); - } - else - { - /* Set calibration mode to factory */ - CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); - } - - } - else - { - /* Set low power mode */ - SET_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); - - if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) - { - /* Set calibration mode to user trimming */ - SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); - - /* Set values for transistors differential pair high (PMOS) and low */ - /* (NMOS) for low power mode. */ - MODIFY_REG(OPAMP->LPOTR, __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueNLowPower) | - __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValuePLowPower) ); - } - else - { - /* Set calibration mode to factory trimming */ - CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); - } - - } - - - /* Configure the power supply range */ - MODIFY_REG(tmp_csr, OPAMP_CSR_AOP_RANGE, - hopamp->Init.PowerSupplyRange); - - /* Set OPAMP CSR register from temporary variable */ - /* This allows to apply all changes on one time, in case of update on */ - /* the fly with OPAMP previously set and running: */ - /* - to avoid hazardous transient switches settings (risk of short */ - /* circuit) */ - /* - to avoid interruption of input signal */ - OPAMP->CSR = tmp_csr; - - - /* Update the OPAMP state */ - /* If coming from state reset: Update from state RESET to state READY */ - /* else: remain in state READY or BUSY (no update) */ - if (hopamp->State == HAL_OPAMP_STATE_RESET) - { - hopamp->State = HAL_OPAMP_STATE_READY; - } - } - } - - return status; -} - - -/** - * @brief DeInitializes the OPAMP peripheral - * @note Deinitialization can't be performed if the OPAMP configuration is locked. - * To unlock the configuration, perform a system reset. - * @param hopamp: OPAMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - /* DeInit not allowed if calibration is ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) - { - status = HAL_ERROR; - } - else - { - - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - /* Open all switches on non-inverting input, inverting input and output */ - /* feedback. */ - CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); - - /* DeInit the low level hardware */ - HAL_OPAMP_MspDeInit(hopamp); - - /* Update the OPAMP state*/ - hopamp->State = HAL_OPAMP_STATE_RESET; - } - - /* Process unlocked */ - __HAL_UNLOCK(hopamp); - - return status; -} - - -/** - * @brief Initializes the OPAMP MSP. - * @param hopamp: OPAMP handle - * @retval None - */ -__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* hopamp) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the function "HAL_OPAMP_MspInit()" must be implemented in the user file. - */ -} - -/** - * @brief DeInitializes OPAMP MSP. - * @param hopamp: OPAMP handle - * @retval None - */ -__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* hopamp) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file. - */ -} - -/** - * @} - */ - - -/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the OPAMP - start, stop and calibration actions. - -@endverbatim - * @{ - */ - -/** - * @brief Start the opamp - * @param hopamp: OPAMP handle - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - if(hopamp->State == HAL_OPAMP_STATE_READY) - { - /* Enable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); - - /* Update the OPAMP state */ - /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */ - hopamp->State = HAL_OPAMP_STATE_BUSY; - } - else - { - status = HAL_ERROR; - } - - } - return status; -} - -/** - * @brief Stop the opamp - * @param hopamp: OPAMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - /* Check if OPAMP calibration ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - if(hopamp->State == HAL_OPAMP_STATE_BUSY) - { - /* Disable the selected opamp */ - SET_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); - - /* Update the OPAMP state*/ - /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/ - hopamp->State = HAL_OPAMP_STATE_READY; - } - else - { - status = HAL_ERROR; - } - } - return status; -} - -/** - * @brief Run the self calibration of one OPAMP - * @note Trimming values (PMOS & NMOS) are updated and user trimming is - * enabled is calibration is succesful. - * @note Calibration is performed in the mode specified in OPAMP init - * structure (mode normal or low-power). To perform calibration for - * both modes, repeat this function twice after OPAMP init structure - * accordingly updated. - * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P - * and N transistors: 10 steps with 1 ms for each step). - * @param hopamp: handle - * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - - uint32_t* opamp_trimmingvalue = 0; - uint32_t opamp_trimmingvaluen = 0; - uint32_t opamp_trimmingvaluep = 0; - - uint32_t trimming_diff_pair = 0; /* Selection of differential transistors pair high or low */ - - __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - uint32_t tmp_opamp_otr_otuser = 0; /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */ - - uint32_t tmp_Opaxcalout_DefaultSate = 0; /* Bit OPAMP_CSR_OPAXCALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ - - uint32_t tmp_OpaxSwitchesContextBackup = 0; - - uint8_t trimming_diff_pair_iteration_count = 0; - uint8_t delta = 0; - - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) - { - status = HAL_ERROR; - } - else - { - - /* Check if OPAMP in calibration mode and calibration not yet enable */ - if(hopamp->State == HAL_OPAMP_STATE_READY) - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); - - /* Update OPAMP state */ - hopamp->State = HAL_OPAMP_STATE_CALIBBUSY; - - /* Backup of switches configuration to restore it at the end of the */ - /* calibration. */ - tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); - - /* Open all switches on non-inverting input, inverting input and output */ - /* feedback. */ - CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); - - /* Set calibration mode to user programmed trimming values */ - SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); - - - /* Select trimming settings depending on power mode */ - if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp_otr_otuser = OPAMP_OTR_OT_USER; - tmp_opamp_reg_trimming = &OPAMP->OTR; - } - else - { - tmp_opamp_otr_otuser = 0x00000000; - tmp_opamp_reg_trimming = &OPAMP->LPOTR; - } - - - /* Enable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); - - /* Perform trimming for both differential transistors pair high and low */ - for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) - { - if (trimming_diff_pair_iteration_count == 0) - { - /* Calibration of transistors differential pair high (NMOS) */ - trimming_diff_pair = OPAMP_FACTORYTRIMMING_N; - opamp_trimmingvalue = &opamp_trimmingvaluen; - - /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ - /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opaxcalout_DefaultSate = RESET; - - /* Enable calibration for N differential pair */ - MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_L(hopamp), - __OPAMP_CSR_OPAXCAL_H(hopamp) ); - } - else /* (trimming_diff_pair_iteration_count == 1) */ - { - /* Calibration of transistors differential pair low (PMOS) */ - trimming_diff_pair = OPAMP_FACTORYTRIMMING_P; - opamp_trimmingvalue = &opamp_trimmingvaluep; - - /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ - /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opaxcalout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp); - - /* Enable calibration for P differential pair */ - MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_H(hopamp), - __OPAMP_CSR_OPAXCAL_L(hopamp) ); - } - - - /* Perform calibration parameter search by dichotomy sweep */ - /* - Delta initial value 16: for 5 dichotomy steps: 16 for the */ - /* initial range, then successive delta sweeps (8, 4, 2, 1). */ - /* can extend the search range to +/- 15 units. */ - /* - Trimming initial value 15: search range will go from 0 to 30 */ - /* (Trimming value 31 is forbidden). */ - *opamp_trimmingvalue = 15; - delta = 16; - - while (delta != 0) - { - /* Set candidate trimming */ - MODIFY_REG(*tmp_opamp_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser); - - /* Offset trimming time: during calibration, minimum time needed */ - /* between two steps to have 1 mV accuracy. */ - HAL_Delay(OPAMP_TRIMMING_DELAY); - - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; - - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp)) != tmp_Opaxcalout_DefaultSate) - { - /* If calibration output is has toggled, try lower trimming */ - *opamp_trimmingvalue -= delta; - } - else - { - /* If calibration output is has not toggled, try higher trimming */ - *opamp_trimmingvalue += delta; - } - } - - } - - /* Disable calibration for P and N differential pairs */ - /* Disable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, (__OPAMP_CSR_OPAXCAL_H(hopamp) | - __OPAMP_CSR_OPAXCAL_L(hopamp) | - __OPAMP_CSR_OPAXPD(hopamp)) ); - - /* Backup of switches configuration to restore it at the end of the */ - /* calibration. */ - SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); - - /* Self calibration is successful */ - /* Store calibration (user trimming) results in init structure. */ - - /* Set user trimming mode */ - hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER; - - /* Affect calibration parameters depending on mode normal/low power */ - if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp->Init.TrimmingValueN = opamp_trimmingvaluen; - /* Write calibration result P */ - hopamp->Init.TrimmingValueP = opamp_trimmingvaluep; - } - else - { - /* Write calibration result N */ - hopamp->Init.TrimmingValueNLowPower = opamp_trimmingvaluen; - /* Write calibration result P */ - hopamp->Init.TrimmingValuePLowPower = opamp_trimmingvaluep; - } - - /* Update OPAMP state */ - hopamp->State = HAL_OPAMP_STATE_READY; - - } - else - { - /* OPAMP can not be calibrated from this mode */ - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Return the OPAMP factory trimming value - * Caution: On STM32L1 OPAMP, user can retrieve factory trimming if - * OPAMP has never been set to user trimming before. - * Therefore, this fonction must be called when OPAMP init - * parameter "UserTrimming" is set to trimming factory, - * and before OPAMP calibration (function - * "HAL_OPAMP_SelfCalibrate()"). - * Otherwise, factory triming value cannot be retrieved and - * error status is returned. - * @param hopamp : OPAMP handle - * @param trimmingoffset : Trimming offset (P or N) - * This parameter must be a value of @ref OPAMP_FactoryTrimming - * @note Calibration parameter retrieved is corresponding to the mode - * specified in OPAMP init structure (mode normal or low-power). - * To retrieve calibration parameters for both modes, repeat this - * function after OPAMP init structure accordingly updated. - * @retval Trimming value (P or N): range: 0->31 - * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available - * @{ - */ -OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) -{ - OPAMP_TrimmingValueTypeDef trimmingvalue; - __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - - /* Check the OPAMP handle allocation */ - /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) - || (hopamp->State == HAL_OPAMP_STATE_BUSY) - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) - || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) - { - trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY; - } - else - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset)); - assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); - - /* Check the trimming mode */ - if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) - { - /* This fonction must called when OPAMP init parameter "UserTrimming" */ - /* is set to trimming factory, and before OPAMP calibration (function */ - /* "HAL_OPAMP_SelfCalibrate()"). */ - /* Otherwise, factory triming value cannot be retrieved and error */ - /* status is returned. */ - trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY; - } - else - { - /* Select trimming settings depending on power mode */ - if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp_reg_trimming = &OPAMP->OTR; - } - else - { - tmp_opamp_reg_trimming = &OPAMP->LPOTR; - } - - /* Get factory trimming */ - trimmingvalue = ((*tmp_opamp_reg_trimming >> __OPAMP_OFFSET_TRIM_BITSPOSITION(hopamp, trimmingoffset)) & OPAMP_TRIM_VALUE_MASK); - } - } - - return trimmingvalue; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - -@endverbatim - * @{ - */ - -/** - * @brief Lock the selected opamp configuration. - * Caution: On STM32L1, HAL OPAMP lock is software lock only (not - * hardware lock as on some other STM32 devices) - * @param hopamp: OPAMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - /* OPAMP can be locked when enabled and running in normal mode */ - /* It is meaningless otherwise */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ - || (hopamp->State == HAL_OPAMP_STATE_READY) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ - || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) - - { - status = HAL_ERROR; - } - - else - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - /* OPAMP state changed to locked */ - hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED; - } - return status; -} - -/** - * @} - */ - - -/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the OPAMP state - * @param hopamp : OPAMP handle - * @retval HAL state - */ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef* hopamp) -{ - /* Check the OPAMP handle allocation */ - if(hopamp == NULL) - { - return HAL_OPAMP_STATE_RESET; - } - - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - return hopamp->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -#endif /* HAL_OPAMP_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c deleted file mode 100644 index 364e222fc..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c +++ /dev/null @@ -1,757 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_opamp_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Extended OPAMP HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (OPAMP) peripheral: - * + Extended Initialization and de-initialization functions - * + Extended Peripheral Control functions - * - @verbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup OPAMPEx OPAMPEx - * @brief OPAMP Extended HAL module driver. - * @{ - */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions - * @{ - */ - -/** @addtogroup OPAMPEx_Exported_Functions_Group1 - * @brief Extended operation functions - * -@verbatim - =============================================================================== - ##### Extended IO operation functions ##### - =============================================================================== - [..] - (+) OPAMP Self calibration. - -@endverbatim - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -/* 3 OPAMPS available */ -/* 3 OPAMPS can be calibrated in parallel */ - -/** - * @brief Run the self calibration of the 3 OPAMPs in parallel. - * @note Trimming values (PMOS & NMOS) are updated and user trimming is - * enabled is calibration is succesful. - * @note Calibration is performed in the mode specified in OPAMP init - * structure (mode normal or low-power). To perform calibration for - * both modes, repeat this function twice after OPAMP init structure - * accordingly updated. - * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P - * and N transistors: 10 steps with 1 ms for each step). - * @param hopamp1 handle - * @param hopamp2 handle - * @param hopamp3 handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3) -{ - HAL_StatusTypeDef status = HAL_OK; - - uint32_t* opamp1_trimmingvalue = 0; - uint32_t opamp1_trimmingvaluen = 0; - uint32_t opamp1_trimmingvaluep = 0; - - uint32_t* opamp2_trimmingvalue = 0; - uint32_t opamp2_trimmingvaluen = 0; - uint32_t opamp2_trimmingvaluep = 0; - - uint32_t* opamp3_trimmingvalue = 0; - uint32_t opamp3_trimmingvaluen = 0; - uint32_t opamp3_trimmingvaluep = 0; - - uint32_t trimming_diff_pair = 0; /* Selection of differential transistors pair high or low */ - - __IO uint32_t* tmp_opamp1_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - __IO uint32_t* tmp_opamp2_reg_trimming; - __IO uint32_t* tmp_opamp3_reg_trimming; - uint32_t tmp_opamp1_otr_otuser = 0; /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */ - uint32_t tmp_opamp2_otr_otuser = 0; - uint32_t tmp_opamp3_otr_otuser = 0; - - uint32_t tmp_Opa1calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ - uint32_t tmp_Opa2calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ - uint32_t tmp_Opa3calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA3CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ - - uint32_t tmp_OpaxSwitchesContextBackup = 0; - - uint8_t trimming_diff_pair_iteration_count = 0; - uint8_t delta = 0; - - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || - (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || - (hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) ) - { - status = HAL_ERROR; - } - else - { - - /* Check if OPAMP in calibration mode and calibration not yet enable */ - if((hopamp1->State == HAL_OPAMP_STATE_READY) && - (hopamp2->State == HAL_OPAMP_STATE_READY) && - (hopamp3->State == HAL_OPAMP_STATE_READY) ) - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance)); - assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); - assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); - assert_param(IS_OPAMP_POWERMODE(hopamp3->Init.PowerMode)); - - /* Update OPAMP state */ - hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY; - hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY; - hopamp3->State = HAL_OPAMP_STATE_CALIBBUSY; - - /* Backup of switches configuration to restore it at the end of the */ - /* calibration. */ - tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); - - /* Open all switches on non-inverting input, inverting input and output */ - /* feedback. */ - CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); - - /* Set calibration mode to user programmed trimming values */ - SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); - - /* Select trimming settings depending on power mode */ - if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER; - tmp_opamp1_reg_trimming = &OPAMP->OTR; - } - else - { - tmp_opamp1_otr_otuser = 0x00000000; - tmp_opamp1_reg_trimming = &OPAMP->LPOTR; - } - - if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER; - tmp_opamp2_reg_trimming = &OPAMP->OTR; - } - else - { - tmp_opamp2_otr_otuser = 0x00000000; - tmp_opamp2_reg_trimming = &OPAMP->LPOTR; - } - - if (hopamp3->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp3_otr_otuser = OPAMP_OTR_OT_USER; - tmp_opamp3_reg_trimming = &OPAMP->OTR; - } - else - { - tmp_opamp3_otr_otuser = 0x00000000; - tmp_opamp3_reg_trimming = &OPAMP->LPOTR; - } - - /* Enable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL); - - /* Perform trimming for both differential transistors pair high and low */ - for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) - { - if (trimming_diff_pair_iteration_count == 0) - { - /* Calibration of transistors differential pair high (NMOS) */ - trimming_diff_pair = OPAMP_FACTORYTRIMMING_N; - opamp1_trimmingvalue = &opamp1_trimmingvaluen; - opamp2_trimmingvalue = &opamp2_trimmingvaluen; - opamp3_trimmingvalue = &opamp3_trimmingvaluen; - - /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ - /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opa1calout_DefaultSate = RESET; - tmp_Opa2calout_DefaultSate = RESET; - tmp_Opa3calout_DefaultSate = RESET; - - /* Enable calibration for N differential pair */ - MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, - OPAMP_CSR_OPAXCAL_H_ALL); - } - else /* (trimming_diff_pair_iteration_count == 1) */ - { - /* Calibration of transistors differential pair low (PMOS) */ - trimming_diff_pair = OPAMP_FACTORYTRIMMING_P; - opamp1_trimmingvalue = &opamp1_trimmingvaluep; - opamp2_trimmingvalue = &opamp2_trimmingvaluep; - opamp3_trimmingvalue = &opamp3_trimmingvaluep; - - /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ - /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1); - tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2); - tmp_Opa3calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp3); - - /* Enable calibration for P differential pair */ - MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, - OPAMP_CSR_OPAXCAL_L_ALL); - } - - - /* Perform calibration parameter search by dichotomy sweep */ - /* - Delta initial value 16: for 5 dichotomy steps: 16 for the */ - /* initial range, then successive delta sweeps (8, 4, 2, 1). */ - /* can extend the search range to +/- 15 units. */ - /* - Trimming initial value 15: search range will go from 0 to 30 */ - /* (Trimming value 31 is forbidden). */ - *opamp1_trimmingvalue = 15; - *opamp2_trimmingvalue = 15; - *opamp3_trimmingvalue = 15; - delta = 16; - - while (delta != 0) - { - /* Set candidate trimming */ - - MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); - - MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); - - MODIFY_REG(*tmp_opamp3_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser); - - - /* Offset trimming time: during calibration, minimum time needed */ - /* between two steps to have 1 mV accuracy. */ - HAL_Delay(OPAMP_TRIMMING_DELAY); - - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; - - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - /* Trimming values update with dichotomy delta of previous */ - /* iteration. */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) - { - /* If calibration output is has toggled, try lower trimming */ - *opamp1_trimmingvalue -= delta; - } - else - { - /* If calibration output is has not toggled, try higher trimming */ - *opamp1_trimmingvalue += delta; - } - - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - /* Trimming values update with dichotomy delta of previous */ - /* iteration. */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) - { - /* If calibration output is has toggled, try lower trimming */ - *opamp2_trimmingvalue -= delta; - } - else - { - /* If calibration output is has not toggled, try higher trimming */ - *opamp2_trimmingvalue += delta; - } - - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - /* Trimming values update with dichotomy delta of previous */ - /* iteration. */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp3)) != tmp_Opa3calout_DefaultSate) - { - /* If calibration output is has toggled, try lower trimming */ - *opamp3_trimmingvalue -= delta; - } - else - { - /* If calibration output is has not toggled, try higher trimming */ - *opamp3_trimmingvalue += delta; - } - - } - } - - - /* Disable calibration for P and N differential pairs */ - /* Disable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | - OPAMP_CSR_OPAXCAL_L_ALL | - OPAMP_CSR_OPAXPD_ALL )); - - /* Backup of switches configuration to restore it at the end of the */ - /* calibration. */ - SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); - - /* Self calibration is successful */ - /* Store calibration (user trimming) results in init structure. */ - - /* Set user trimming mode */ - hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; - hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; - hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER; - - /* Affect calibration parameters depending on mode normal/low power */ - if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen; - /* Write calibration result P */ - hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep; - } - else - { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen; - /* Write calibration result P */ - hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep; - } - - if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen; - /* Write calibration result P */ - hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep; - } - else - { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen; - /* Write calibration result P */ - hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep; - } - - if (hopamp3->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp3->Init.TrimmingValueN = opamp3_trimmingvaluen; - /* Write calibration result P */ - hopamp3->Init.TrimmingValueP = opamp3_trimmingvaluep; - } - else - { - /* Write calibration result N */ - hopamp3->Init.TrimmingValueNLowPower = opamp3_trimmingvaluen; - /* Write calibration result P */ - hopamp3->Init.TrimmingValuePLowPower = opamp3_trimmingvaluep; - } - - /* Update OPAMP state */ - hopamp1->State = HAL_OPAMP_STATE_READY; - hopamp2->State = HAL_OPAMP_STATE_READY; - hopamp3->State = HAL_OPAMP_STATE_READY; - - } - else - { - /* OPAMP can not be calibrated from this mode */ - status = HAL_ERROR; - } - } - - return status; -} - -#else - -/* 2 OPAMPS available */ -/* 2 OPAMPS can be calibrated in parallel */ - -/** - * @brief Run the self calibration of the 2 OPAMPs in parallel. - * @note Trimming values (PMOS & NMOS) are updated and user trimming is - * enabled is calibration is succesful. - * @note Calibration is performed in the mode specified in OPAMP init - * structure (mode normal or low-power). To perform calibration for - * both modes, repeat this function twice after OPAMP init structure - * accordingly updated. - * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P - * and N transistors: 10 steps with 1 ms for each step). - * @param hopamp1 handle - * @param hopamp2 handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2) -{ - HAL_StatusTypeDef status = HAL_OK; - - uint32_t* opamp1_trimmingvalue = 0; - uint32_t opamp1_trimmingvaluen = 0; - uint32_t opamp1_trimmingvaluep = 0; - - uint32_t* opamp2_trimmingvalue = 0; - uint32_t opamp2_trimmingvaluen = 0; - uint32_t opamp2_trimmingvaluep = 0; - - uint32_t trimming_diff_pair = 0; /* Selection of differential transistors pair high or low */ - - __IO uint32_t* tmp_opamp1_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - __IO uint32_t* tmp_opamp2_reg_trimming; - uint32_t tmp_opamp1_otr_otuser = 0; /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */ - uint32_t tmp_opamp2_otr_otuser = 0; - - uint32_t tmp_Opa1calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ - uint32_t tmp_Opa2calout_DefaultSate = 0; /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ - - uint32_t tmp_OpaxSwitchesContextBackup = 0; - - uint8_t trimming_diff_pair_iteration_count = 0; - uint8_t delta = 0; - - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || - (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) ) - { - status = HAL_ERROR; - } - else - { - - /* Check if OPAMP in calibration mode and calibration not yet enable */ - if((hopamp1->State == HAL_OPAMP_STATE_READY) && - (hopamp2->State == HAL_OPAMP_STATE_READY) ) - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); - assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); - assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); - - /* Update OPAMP state */ - hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY; - hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY; - - /* Backup of switches configuration to restore it at the end of the */ - /* calibration. */ - tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); - - /* Open all switches on non-inverting input, inverting input and output */ - /* feedback. */ - CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS); - - /* Set calibration mode to user programmed trimming values */ - SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); - - /* Select trimming settings depending on power mode */ - if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER; - tmp_opamp1_reg_trimming = &OPAMP->OTR; - } - else - { - tmp_opamp1_otr_otuser = 0x00000000; - tmp_opamp1_reg_trimming = &OPAMP->LPOTR; - } - - if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER; - tmp_opamp2_reg_trimming = &OPAMP->OTR; - } - else - { - tmp_opamp2_otr_otuser = 0x00000000; - tmp_opamp2_reg_trimming = &OPAMP->LPOTR; - } - - /* Enable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL); - - /* Perform trimming for both differential transistors pair high and low */ - for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) - { - if (trimming_diff_pair_iteration_count == 0) - { - /* Calibration of transistors differential pair high (NMOS) */ - trimming_diff_pair = OPAMP_FACTORYTRIMMING_N; - opamp1_trimmingvalue = &opamp1_trimmingvaluen; - opamp2_trimmingvalue = &opamp2_trimmingvaluen; - - /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ - /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opa1calout_DefaultSate = RESET; - tmp_Opa2calout_DefaultSate = RESET; - - /* Enable calibration for N differential pair */ - MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, - OPAMP_CSR_OPAXCAL_H_ALL); - } - else /* (trimming_diff_pair_iteration_count == 1) */ - { - /* Calibration of transistors differential pair low (PMOS) */ - trimming_diff_pair = OPAMP_FACTORYTRIMMING_P; - opamp1_trimmingvalue = &opamp1_trimmingvaluep; - opamp2_trimmingvalue = &opamp2_trimmingvaluep; - - /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ - /* is 00000b. Used to detect the bit toggling during trimming. */ - tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1); - tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2); - - /* Enable calibration for P differential pair */ - MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, - OPAMP_CSR_OPAXCAL_L_ALL); - } - - - /* Perform calibration parameter search by dichotomy sweep */ - /* - Delta initial value 16: for 5 dichotomy steps: 16 for the */ - /* initial range, then successive delta sweeps (8, 4, 2, 1). */ - /* can extend the search range to +/- 15 units. */ - /* - Trimming initial value 15: search range will go from 0 to 30 */ - /* (Trimming value 31 is forbidden). */ - *opamp1_trimmingvalue = 15; - *opamp2_trimmingvalue = 15; - delta = 16; - - while (delta != 0) - { - /* Set candidate trimming */ - - MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser); - - MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , - __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser); - - - /* Offset trimming time: during calibration, minimum time needed */ - /* between two steps to have 1 mV accuracy. */ - HAL_Delay(OPAMP_TRIMMING_DELAY); - - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; - - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate) - { - /* If calibration output is has toggled, try lower trimming */ - *opamp1_trimmingvalue -= delta; - } - else - { - /* If calibration output is has not toggled, try higher trimming */ - *opamp1_trimmingvalue += delta; - } - - /* Set trimming values for next iteration in function of trimming */ - /* result toggle (versus initial state). */ - if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate) - { - /* If calibration output is has toggled, try lower trimming */ - *opamp2_trimmingvalue -= delta; - } - else - { - /* If calibration output is has not toggled, try higher trimming */ - *opamp2_trimmingvalue += delta; - } - - } - } - - - /* Disable calibration for P and N differential pairs */ - /* Disable the selected opamp */ - CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | - OPAMP_CSR_OPAXCAL_L_ALL | - OPAMP_CSR_OPAXPD_ALL )); - - /* Backup of switches configuration to restore it at the end of the */ - /* calibration. */ - SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); - - /* Self calibration is successful */ - /* Store calibration (user trimming) results in init structure. */ - - /* Set user trimming mode */ - hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; - hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; - - /* Affect calibration parameters depending on mode normal/low power */ - if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen; - /* Write calibration result P */ - hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep; - } - else - { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen; - /* Write calibration result P */ - hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep; - } - - if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen; - /* Write calibration result P */ - hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep; - } - else - { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen; - /* Write calibration result P */ - hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep; - } - - /* Update OPAMP state */ - hopamp1->State = HAL_OPAMP_STATE_READY; - hopamp2->State = HAL_OPAMP_STATE_READY; - - } - else - { - /* OPAMP can not be calibrated from this mode */ - status = HAL_ERROR; - } - } - - return status; -} - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** @defgroup OPAMPEx_Exported_Functions_Group2 Extended Peripheral Control functions - * @brief Extended control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - (+) OPAMP unlock. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the selected opamp configuration. - * This function must be called only when OPAMP is in state "locked". - * @param hopamp: OPAMP handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the OPAMP handle allocation */ - /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) - || (hopamp->State == HAL_OPAMP_STATE_READY) - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) - || (hopamp->State == HAL_OPAMP_STATE_BUSY)) - - { - status = HAL_ERROR; - } - else - { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - /* OPAMP state changed to locked */ - hopamp->State = HAL_OPAMP_STATE_BUSY; - } - return status; -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -#endif /* HAL_OPAMP_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c deleted file mode 100644 index 8dc7ffcf8..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c +++ /dev/null @@ -1,1345 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pcd.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The PCD HAL driver can be used as follows: - - (#) Declare a PCD_HandleTypeDef handle structure, for example: - PCD_HandleTypeDef hpcd; - - (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) - - (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __USB_CLK_ENABLE); - - (##) Initialize the related GPIO clocks - (##) Configure PCD pin-out - (##) Configure PCD NVIC interrupt - - (#)Associate the Upper USB device stack to the HAL PCD Driver: - (##) hpcd.pData = pdev; - - (#)Enable HCD transmission and reception: - (##) HAL_PCD_Start(); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup PCD PCD - * @brief PCD HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Constants PCD Private Constants - * @{ - */ -#define BTABLE_ADDRESS (0x000) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup PCD_Private_Functions PCD Private Functions - * @{ - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); -static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); - -/** - * @} - */ - - -/** @defgroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and create the associated handle. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) -{ - uint32_t i = 0; - - uint32_t wInterrupt_Mask = 0; - - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - - hpcd->State = PCD_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); - - /* Init endpoints structures */ - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) - { - /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1; - hpcd->IN_ep[i].num = i; - /* Control until ep is actvated */ - hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0; - hpcd->IN_ep[i].xfer_buff = 0; - hpcd->IN_ep[i].xfer_len = 0; - } - - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) - { - hpcd->OUT_ep[i].is_in = 0; - hpcd->OUT_ep[i].num = i; - /* Control until ep is activated */ - hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0; - hpcd->OUT_ep[i].xfer_buff = 0; - hpcd->OUT_ep[i].xfer_len = 0; - } - - /* Init Device */ - /*CNTR_FRES = 1*/ - hpcd->Instance->CNTR = USB_CNTR_FRES; - - /*CNTR_FRES = 0*/ - hpcd->Instance->CNTR = 0; - - /*Clear pending interrupts*/ - hpcd->Instance->ISTR = 0; - - /*Set Btable Adress*/ - hpcd->Instance->BTABLE = BTABLE_ADDRESS; - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - hpcd->USB_Address = 0; - hpcd->State= PCD_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the PCD peripheral - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) -{ - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - hpcd->State = PCD_BUSY; - - /* Stop Device */ - HAL_PCD_Stop(hpcd); - - /* DeInit the low level hardware */ - HAL_PCD_MspDeInit(hpcd); - - hpcd->State = PCD_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implenetd in the user file - */ -} - -/** - * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implenetd in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - HAL_PCDEx_SetConnectionState (hpcd, 1); - return HAL_OK; -} - -/** - * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - - /* disable all interrupts and force USB reset */ - hpcd->Instance->CNTR = USB_CNTR_FRES; - - /* clear interrupt status register */ - hpcd->Instance->ISTR = 0; - - /* switch-off device */ - hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - uint32_t wInterrupt_Mask = 0; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) - { - /* servicing of the endpoint correct transfer interrupt */ - /* clear of the CTR flag into the sub */ - PCD_EP_ISR_Handler(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); - HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVRM)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVRM); - } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { - hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE); - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - - /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); - HAL_PCD_SOFCallback(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) - { - /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); - } -} - -/** - * @brief Data out stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implenetd in the user file - */ -} - -/** - * @brief Data IN stage callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implenetd in the user file - */ -} -/** - * @brief Setup stage callback - * @param hpcd: ppp handle - * @retval None - */ - __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implenetd in the user file - */ -} - -/** - * @brief USB Start Of Frame callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implenetd in the user file - */ -} - -/** - * @brief USB Reset callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implenetd in the user file - */ -} - - -/** - * @brief Suspend event callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implenetd in the user file - */ -} - -/** - * @brief Resume event callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implenetd in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implenetd in the user file - */ -} - -/** - * @brief Incomplete ISO IN callbacks - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ - __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implenetd in the user file - */ -} - -/** - * @brief Connection event callbacks - * @param hpcd: PCD handle - * @retval None - */ - __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implenetd in the user file - */ -} - -/** - * @brief Disconnection event callbacks - * @param hpcd: ppp handle - * @retval None - */ - __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implenetd in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Connect the USB device - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - HAL_PCDEx_SetConnectionState (hpcd, 1); - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Disconnect the USB device - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - - /* Disable DP Pull-Down bit*/ - HAL_PCDEx_SetConnectionState (hpcd, 0); - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Set the USB Device address - * @param hpcd: PCD handle - * @param address: new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - - if(address == 0) - { - /* set device address and enable function */ - hpcd->Instance->DADDR = USB_DADDR_EF; - } - else /* USB Address will be applied later */ - { - hpcd->USB_Address = address; - } - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} -/** - * @brief Open and configure an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packert size - * @param ep_type: endpoint type - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) -{ - HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - - __HAL_LOCK(hpcd); - -/* initialize Endpoint */ - switch (ep->type) - { - case PCD_EP_TYPE_CTRL: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL); - break; - case PCD_EP_TYPE_BULK: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK); - break; - case PCD_EP_TYPE_INTR: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT); - break; - case PCD_EP_TYPE_ISOC: - PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); - break; - default: - break; - } - - PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); - - if (ep->doublebuffer == 0) - { - if (ep->is_in) - { - /*Set the endpoint Transmit buffer address */ - PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); - } - else - { - /*Set the endpoint Receive buffer address */ - PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); - /*Set the endpoint Receive buffer counter*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket); - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - /* Configure VALID status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); - } - } - /*Double Buffer*/ - else - { - /*Set the endpoint as double buffered*/ - PCD_SET_EP_DBUF(hpcd->Instance, ep->num); - /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1); - - if (ep->is_in==0) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(hpcd->Instance, ep->num); - - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - PCD_RX_DTOG(hpcd->Instance, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); - } - } - - __HAL_UNLOCK(hpcd); - return ret; -} - - -/** - * @brief Deactivate an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - - __HAL_LOCK(hpcd); - - if (ep->doublebuffer == 0) - { - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - } - else - { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); - } - } - /*Double Buffer*/ - else - { - if (ep->is_in==0) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(hpcd->Instance, ep->num); - - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - PCD_RX_DTOG(hpcd->Instance, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); - } - } - - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - - -/** - * @brief Receive an amount of data - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - - PCD_EPTypeDef *ep; - - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - __HAL_LOCK(hpcd); - - /* Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0; - } - - /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) - { - /*Set RX buffer count*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len); - } - else - { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); - } - - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Get Received Data Size - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval Data Size - */ -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; -} -/** - * @brief Send an amount of data - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep; - uint16_t pmabuffer = 0; - - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - - __HAL_LOCK(hpcd); - - /*Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0; - } - - /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); - PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); - } - else - { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); - - /*Write the data to the USB endpoint*/ - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) - { - pmabuffer = ep->pmaaddr1; - } - else - { - pmabuffer = ep->pmaaddr0; - } - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); - PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in); - } - - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Set a STALL condition over an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - __HAL_LOCK(hpcd); - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - if (ep->num == 0) - { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); - } - else - { - if (ep->is_in) - { - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL); - } - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); - } - else - { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Flush an endpoint - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return HAL_OK; -} - -/** - * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling - * @param hpcd: PCD handle - * @retval status - */ -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - hpcd->Instance->CNTR |= USB_CNTR_RESUME; - return HAL_OK; -} - -/** - * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling - * @param hpcd: PCD handle - * @retval status - */ -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - - -/** - * @brief Return the PCD state - * @param hpcd : PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) -{ - return hpcd->State; -} - - -/** - * @brief Software Device Connection - * @param hpcd: PCD handle - * @param state: Device state - * @retval None - */ - __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCDEx_SetConnectionState could be implenetd in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup PCD_Private_Functions - * @{ - */ - - -/** - * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) -{ - PCD_EPTypeDef *ep; - uint16_t count=0; - uint8_t EPindex; - __IO uint16_t wIstr; - __IO uint16_t wEPVal = 0; - - /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) - { - /* extract highest priority endpoint number */ - EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (EPindex == 0) - { - /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - ep = &hpcd->IN_ep[0]; - - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); - - - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) - { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; - } - - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0) - { - /* Get SETUP Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Process SETUP Packet*/ - HAL_PCD_SetupStageCallback(hpcd); - } - - else if ((wEPVal & USB_EP_CTR_RX) != 0) - { - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; - } - - /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); - - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); - } - } - } - else - { - - /* Decode and service non control endpoints interrupt */ - - /* process related endpoint register */ - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) - { - /* clear int flag */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); - ep = &hpcd->OUT_ep[EPindex]; - - /* OUT double Buffering*/ - if (ep->doublebuffer == 0) - { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) - { - /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); - } - /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) - { - /* RX COMPLETE */ - HAL_PCD_DataOutStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - - } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0) - { - ep = &hpcd->IN_ep[EPindex]; - - /* clear int flag */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); - } - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - } - } - } - return HAL_OK; -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx = pointer to USB register. - * @param pbUsrBuf: pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. - * @retval None - */ -static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ - uint32_t i, temp1, temp2; - uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) - { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; - *pdwVal++ = temp2; - pdwVal++; - pbUsrBuf++; - } -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx = pointer to USB register. - * @param pbUsrBuf = pointer to user memory area. - * @param wPMABufAddr: address into PMA. - * @param wNBytes: no. of bytes to be copied. - * @retval None - */ -static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1;/* /2*/ - uint32_t i; - uint32_t *pdwVal; - pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) - { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; - pbUsrBuf++; - } -} - -/** - * @} - */ - -#endif /* HAL_PCD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c deleted file mode 100644 index e920f600f..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c +++ /dev/null @@ -1,147 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pcd_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Extended PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Configururation of the PMA for EP - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup PCDEx PCDEx - * @brief PCDEx HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ - -/* -@verbatim - =============================================================================== - ##### Peripheral extended features functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Configure PMA for EP - * @param hpcd : Device instance - * @param ep_addr: endpoint address - * @param ep_kind: endpoint Kind - * USB_SNG_BUF: Single Buffer used - * USB_DBL_BUF: Double Buffer used - * @param pmaadress: EP address in The PMA: In case of single buffer endpoint - * this parameter is 16-bit value providing the address - * in PMA allocated to endpoint. - * In case of double buffer endpoint this parameter - * is a 32-bit value providing the endpoint buffer 0 address - * in the LSB part of 32-bit value and endpoint buffer 1 address - * in the MSB part of 32-bit value. - * @retval : status - */ - -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress) - -{ - PCD_EPTypeDef *ep; - - /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - /* Here we check if the endpoint is single or double Buffer*/ - if (ep_kind == PCD_SNG_BUF) - { - /*Single Buffer*/ - ep->doublebuffer = 0; - /*Configure te PMA*/ - ep->pmaadress = (uint16_t)pmaadress; - } - else /*USB_DBL_BUF*/ - { - /*Double Buffer Endpoint*/ - ep->doublebuffer = 1; - /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; - } - - return HAL_OK; -} - - - -/** - * @} - */ - -#endif /* HAL_PCD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c deleted file mode 100644 index ac34c1822..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c +++ /dev/null @@ -1,612 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief PWR HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define PVD_MODE_IT ((uint32_t)0x00010000) -#define PVD_MODE_EVT ((uint32_t)0x00020000) -#define PVD_RISING_EDGE ((uint32_t)0x00000001) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @note Before calling this function, the VOS[1:0] bits should be configured - * to "10" and the system frequency has to be configured accordingly. - * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() - * function. - * @note ULP and FWU bits are not reset by this function. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __PWR_FORCE_RESET(); - __PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers ). - * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - /* Enable access to RTC and backup registers */ - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers). - * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - /* Disable access to RTC and backup registers */ - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) The PVD can use an external input analog voltage (PVD_IN) which is compared - internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode - when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). - - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - *** WakeUp pin configuration *** - ================================ - [..] - (+) WakeUp pin is used to wake up the system from Standby mode. This pin is - forced in input pull-down configuration and is active on rising edges. - (+) There are two or three WakeUp pins: - WakeUp Pin 1 on PA.00. - WakeUp Pin 2 on PC.13. - WakeUp Pin 3 on PE.06. : Only on product with GPIOE available - - [..] - *** Main and Backup Regulators configuration *** - ================================================ - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() - macro which configure VOS bit in PWR_CR register: - (++) When this bit is set (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 32 MHz. - (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 16 MHz. - (++) When this bit is reset (Regulator voltage output Scale 3 mode selected) - the System frequency can go up to 4.2 MHz. - - Refer to the datasheets for more details. - - *** Low Power modes configuration *** - ===================================== - [..] - The device features 5 low-power modes: - (+) Low power run mode: regulator in low power mode, limited clock frequency, - limited number of peripherals running. - (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running. - (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, - limited number of peripherals running, regulator in low power mode. - (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. - (+) Standby mode: VCORE domain powered off - - *** Low power run mode *** - ========================= - [..] - To further reduce the consumption when the system is in Run mode, the regulator can be - configured in low power mode. In this mode, the system frequency should not exceed - MSI frequency range1. - In Low power run mode, all I/O pins keep the same state as in Run mode. - - (+) Entry: - (++) VCORE in range2 - (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1. - (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() - function. - (+) Exit: - (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode() - function. - (++) Increase the system frequency if needed. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Low power sleep mode *** - ============================ - [..] - (+) Entry: - The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. - This reduces power consumption but increases the wake-up time. - - (+) Exit: - (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt - acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device - from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode, - the MCU exits Sleep mode as soon as an event occurs. - - *** Stop mode *** - ================= - [..] - The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral - clock gating. The voltage regulator can be configured either in normal or low-power mode. - In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and - the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. - To get the lowest consumption in Stop mode, the internal Flash memory also enters low - power mode. When the Flash memory is in power-down mode, an additional startup delay is - incurred when waking up from Stop mode. - To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature - sensor can be switched off before entering Stop mode. They can be switched on again by - software after exiting Stop mode using the ULP bit in the PWR_CR register. - In Stop mode, all I/O pins keep the same state as in Run mode. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI ) - function with: - (++) Main regulator ON. - (++) Low Power regulator ON. - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - (+) Exit: - (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock. - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based on the - Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is - consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are - also switched off. SRAM and register contents are lost except for the RTC registers, RTC - backup registers and Standby circuitry. - - To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature - sensor can be switched off before entering the Standby mode. They can be switched - on again by software after exiting the Standby mode. - function. - - (+) Entry: - (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: - (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() - function - (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() - and HAL_RTC_SetTime() functions. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and - Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT() - or HAL_RTCEx_SetTimeStamp_IT() functions. - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and - Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer() - function. - - (+) RTC auto-wakeup (AWU) from the Standby mode - (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: - (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function. - (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() - and HAL_RTC_SetTime() functions. - (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to - detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() - or HAL_RTCEx_SetTamper_IT()functions. - (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event - using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions. - - (+) Comparator auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup - event, it is necessary to: - (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the - selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using - the COMP functions. - (+++) Configure the comparator to generate the event. - - - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - /* Enable the power voltage detector */ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - /* Disable the power voltage detector */ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 - * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Enable the EWUPx pin */ - *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; -} - -/** - * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 - * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Disable the EWUPx pin */ - *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; -} - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator: Specifies the regulator state in SLEEP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON - * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. - * When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters Stop mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by using an interrupt or a wakeup event, - * MSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enters Standby mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - WKUP pin 1 (PA0) if enabled. - * - WKUP pin 2 (PC13) if enabled. - * - WKUP pin 3 (PE6) if enabled. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select Standby mode */ - SET_BIT(PWR->CR, PWR_CR_PDDS); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c deleted file mode 100644 index a8d474f48..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c +++ /dev/null @@ -1,168 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Extended Initialization and de-initialization functions - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral extended features functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Enables the Fast WakeUp from Ultra Low Power mode. - * @note This bit works in conjunction with ULP bit. - * Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when - * exiting from low power mode. - * @retval None - */ -void HAL_PWREx_EnableFastWakeUp(void) -{ - /* Enable the fast wake up */ - *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Fast WakeUp from Ultra Low Power mode. - * @retval None - */ -void HAL_PWREx_DisableFastWakeUp(void) -{ - /* Disable the fast wake up */ - *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enables the Ultra Low Power mode - * @retval None - */ -void HAL_PWREx_EnableUltraLowPower(void) -{ - /* Enable the Ultra Low Power mode */ - *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Ultra Low Power mode - * @retval None - */ -void HAL_PWREx_DisableUltraLowPower(void) -{ - /* Disable the Ultra Low Power mode */ - *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enters the Low Power Run mode. - * @note Low power run mode can only be entered when VCORE is in range 2. - * In addition, the dynamic voltage scaling must not be used when Low - * power run mode is selected. Only Stop and Sleep modes with regulator - * configured in Low power mode is allowed when Low power run mode is - * selected. - * @note In Low power run mode, all I/O pins keep the same state as in Run mode. - * @retval None - */ -void HAL_PWREx_EnableLowPowerRunMode(void) -{ - /* Enters the Low Power Run mode */ - *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE; - *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE; -} - -/** - * @brief Exits the Low Power Run mode. - * @retval None - */ -void HAL_PWREx_DisableLowPowerRunMode(void) -{ - /* Exits the Low Power Run mode */ - *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE; - *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c deleted file mode 100644 index 731a4f872..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c +++ /dev/null @@ -1,1313 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from multispeed internal oscillator clock - (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled, - and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at MSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals whose clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - (*) SDIO only for STM32L1xxxD devices - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC -* @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Defines RCC Private Defines - * @{ - */ - -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ -const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t aPLLDivisionFactorTable[4] = {1, 2, 3, 4}; -const uint8_t aPLLMulFactorTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== -##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz, - 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. - - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 32 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) - - (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clockis automatically switched to MSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M3 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE, - HSE or PLL clock (through a configurable prescaler) on PA8 pin. - - [..] System, AHB and APB busses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() - macros to configure this clock. - (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 16. You have to use __HAL_RCC_LCD_CONFIG() - macros to configure this clock. - (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly. This clock is derived of the main PLL through PLL Multiplier. - (+@) IWDG clock which is always the LSI clock. - - (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz - and PCLK1 32 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +----------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |------------------------------------------------------| - | | voltage range 1 | voltage range 2 | voltage range 3 | - | | 1.8 V | 1.5 V | 1.2 V | - |---------------|------------------|-----------------|-----------------| - |0WS(1CPU cycle)| 0 < HCLK <= 16 | 0 < HCLK <= 8 | 0 < HCLK <= 2 | - |---------------|------------------|-----------------|-----------------| - |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 | - +----------------------------------------------------------------------+ - (#) The following table gives the different clock source frequencies depending on the product - voltage range: - +------------------------------------------------------------------------------------------+ - | Product voltage | Clock frequency | - | |------------------|-----------------------------|-----------------------| - | range | MSI | HSI | HSE | PLL | - |-----------------|---------|--------|-----------------------------|-----------------------| - | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) | 32 MHz | - | | | | or 24 MHz (crystal) | (PLLVCO max = 96 MHz) | - |-----------------|---------|--------|-----------------------------|-----------------------| - | Range 2 (1.5 V) | 4.2 MHz | 16 MHz | 16 MHz | 16 MHz | - | | | | | (PLLVCO max = 48 MHz) | - |-----------------|---------|--------|-----------------------------|-----------------------| - | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz | - | | | | | (PLLVCO max = 24 MHz) | - +------------------------------------------------------------------------------------------+ - - @endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source - * - HSI, HSE and PLL OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS and MCO1 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None - */ -void HAL_RCC_DeInit(void) -{ - /* Set MSION bit */ - SET_BIT(RCC->CR, RCC_CR_MSION); - - /* Switch SYSCLK to MSI*/ - CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); - - /* Reset HSION, HSEON, CSSON, HSEBYP & PLLON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */ - MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << POSITION_VAL(RCC_ICSCR_MSITRIM)) | RCC_ICSCR_MSIRANGE_5)); - - /* Set HSITRIM bits to the reset value */ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_ICSCR_HSITRIM))); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) - { - return HAL_ERROR; - } - } - else - { - /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ - __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is bypassed or disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- MSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - { - /* Check the parameters */ - assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); - assert_param(IS_RCC_MSIRANGE(RCC_OscInitStruct->MSIClockRange)); - - /* Configures the Internal Multi Speed oscillator (MSI) clock range. */ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - - /* Check if MSI is used as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)) - { - /* When MSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Multi Speed oscillator (MSI) calibration value. */ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - } - } - else - { - /* Check the MSI State */ - if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF) - { - /* Enable the Multi Speed oscillator (MSI). */ - __HAL_RCC_MSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Multi Speed oscillator (MSI) calibration value. */ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - } - else - { - /* Disable the Multi Speed oscillator (MSI). */ - __HAL_RCC_MSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); - - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLMUL, - RCC_OscInitStruct->PLL.PLLDIV); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle - * @arg FLASH_LATENCY_1: FLASH One Latency cycle - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The MSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else - { - /* Check the MSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) - { - return HAL_ERROR; - } - } - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /* Decreasing the CPU frequency */ - else - { - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration -------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else - { - /* Check the MSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) - { - return HAL_ERROR; - } - } - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); - } - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * - @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - - @endverbatim - * @{ - */ - -/** - * @brief Selects the clock source to output on MCO pin. - * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx: specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected - * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected - * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected - * @arg RCC_MCO1SOURCE_MSI: MSI oscillator clock selected - * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected - * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected - * @arg RCC_MCO1SOURCE_LSI: LSI clock selected - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected - * @param RCC_MCODiv: specifies the MCO DIV. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCO clock - * @arg RCC_MCODIV_2: division by 2 applied to MCO clock - * @arg RCC_MCODIV_4: division by 4 applied to MCO clock - * @arg RCC_MCODIV_8: division by 8 applied to MCO clock - * @arg RCC_MCODIV_16: division by 16 applied to MCO clock - * @retval None - */ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef gpio; - - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* MCO Clock Enable */ - __MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ - gpio.Pin = MCO1_PIN; - gpio.Mode = GPIO_MODE_AF_PP; - gpio.Speed = GPIO_SPEED_HIGH; - gpio.Pull = GPIO_NOPULL; - gpio.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - - /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE; -} - -/** - * @brief Returns the SYSCLK frequency - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is MSI, function returns values based on MSI - * Value as defined by the MSI range. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0; - uint32_t sysclockfreq = 0; - - tmpreg = RCC->CFGR; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - { - sysclockfreq = HSI_VALUE; - break; - } - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - { - pllm = aPLLMulFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; - plld = aPLLDivisionFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> POSITION_VAL(RCC_CFGR_PLLDIV)]; - if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - { - /* HSE used as PLL clock source */ - pllvco = HSE_VALUE * (pllm / plld); - } - else - { - /* HSI used as PLL clock source */ - pllvco = HSI_VALUE * (pllm / plld); - } - sysclockfreq = pllvco; - break; - } - case RCC_CFGR_SWS_MSI: /* MSI used as system clock source */ - default: /* MSI used as system clock */ - { - msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> POSITION_VAL(RCC_ICSCR_MSIRANGE); - sysclockfreq = (32768 * (1 << (msiclkrange + 1))); - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); -} - -/** - * @brief Returns the PCLK2 frequency - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ - | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI; - - /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM)); - - /* Get the MSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION) - { - RCC_OscInitStruct->MSIState = RCC_MSI_ON; - } - else - { - RCC_OscInitStruct->MSIState = RCC_MSI_OFF; - } - - RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM)); - RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE)); - - /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); - RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); -} - -/** - * @brief Configures the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency: Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CCSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval none - */ -__weak void HAL_RCC_CCSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CCSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c deleted file mode 100644 index 435d7998b..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c +++ /dev/null @@ -1,277 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Extended RCC HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup RCCEx RCCEx - * @brief RCC Extension HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCCEx_Private_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) and RCC_BDCR register are set to their reset values. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the - * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*------------------------------- RTC/LCD Configuration ------------------------*/ - if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - ) - { - /* Enable Power Controller clock */ - __PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - tmpreg = (RCC->CSR & RCC_CSR_RTCSEL); - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - if((tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - ) - { - /* Store the content of CSR register before the reset of Backup Domain */ - tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of CSR register */ - RCC->CSR = tmpreg; - } - - /* If LSE is selected as RTC clock source, wait for LSE reactivation */ - if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE) -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - ) - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - - return HAL_OK; -} - -/** - * @brief Get the PeriphClkInit according to the internal - * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t srcclk = 0; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ - - /* Get the RTC/LCD configuration -----------------------------------------------*/ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2) - { - /* Source clock is LSE or LSI*/ - PeriphClkInit->RTCClockSelection = srcclk; - } - else - { - /* Source clock is HSE. Need to get the prescaler value*/ - PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); - } -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \ - defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \ - defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \ - defined(STM32L162xE) - PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */ -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \ - defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - -/** - * @brief Enables the LSE Clock Security System. - * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied - * to the RTC but no hardware action is made to the registers. - * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup - * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104). - * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator - * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with - * RTCSEL), or take any required action to secure the application. - * @note LSE CSS available only for high density and medium+ devices - * @retval None - */ -void HAL_RCCEx_EnableLSECSS(void) -{ - *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the LSE Clock Security System. - * @note Once enabled this bit cannot be disabled, except after an LSE failure detection - * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit. - * Reset by power on reset and RTC software reset (RTCRST bit). - * @note LSE CSS available only for high density and medium+ devices - * @retval None - */ -void HAL_RCCEx_DisableLSECSS(void) -{ - *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE; -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c deleted file mode 100644 index 7ec1d1eb0..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c +++ /dev/null @@ -1,902 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) peripheral: - * + Initialization and de-initialization functions - * + RTC Time and Date functions - * + RTC Alarm functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### Backup Domain Operating Condition ##### - ============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC operating even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) PC13 to PC15 I/Os (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following pins are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following pins are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - - ##### Backup Domain Reset ##### - ================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - - ##### Backup Domain Access ##### - ================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() function. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. - (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. - - - ##### How to use this driver ##### - ================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above). - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() - and HAL_RTC_SetDate() functions. - (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. - (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. - - ##### RTC and low power modes ##### - ================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and STANDBY modes is possible only when the RTC clock source - is LSE or LSI. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup RTC RTC - * @brief RTC HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup RTC_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable - RTC registers Write protection, enter and exit the RTC initialization mode, - RTC registers synchronization check and reference clock detection enable. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize power consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter - initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is - complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - /* Check the RTC peripheral state */ - if(hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - - if(hrtc->State == HAL_RTC_STATE_RESET) - { - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; - hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; - } -} - -/** - * @brief DeInitializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This function doesn't reset the RTC Backup Data registers. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - /* Note : This function is defined into this file for library reference. */ - /* Function content is located into file stm32l1xx_hal_rtc_ex.c */ - - /* Return function status */ - return HAL_ERROR; -} - -/** - * @brief Initializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions - * @brief RTC Time and Date functions - * -@verbatim - =============================================================================== - ##### RTC Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Time and Date features - -@endverbatim - * @{ - */ - -/** - * @brief Sets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sTime->Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_TR register */ - hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Clear the bits to be configured */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* Wait for synchro */ - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - - -/** - * @brief Sets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) - { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); - } - - assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - - if(Format == FORMAT_BIN) - { - assert_param(IS_RTC_YEAR(sDate->Year)); - assert_param(IS_RTC_MONTH(sDate->Month)); - assert_param(IS_RTC_DATE(sDate->Date)); - - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); - - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_DR register */ - hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* Wait for synchro */ - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY ; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Gets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the DR register */ - datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == FORMAT_BIN) - { - /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); - sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); - } - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions - * @brief RTC Alarm functions - * -@verbatim - =============================================================================== - ##### RTC Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Alarm feature - -@endverbatim - * @{ - */ - -/** - * @brief Deactive the specified RTC Alarm - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_ALARM(Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - else - { - /* AlarmB */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief This function handles Alarm interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) -{ - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) - { - /* AlarmA callback */ - HAL_RTC_AlarmAEventCallback(hrtc); - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); - } - } - - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET) - { - /* AlarmB callback */ - HAL_RTCEx_AlarmBEventCallback(hrtc); - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); - } - } - - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm A callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles AlarmA Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Returns the RTC state. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) -{ - return hrtc->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Internal_Functions RTC Internal function - * @{ - */ - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - - /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted - * @retval Converted byte - */ -uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint32_t bcdhigh = 0; - - while(Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Converts from 2 digit BCD to Binary. - * @param Value: BCD value to be converted - * @retval Converted word - */ -uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c deleted file mode 100644 index 2a4c484a6..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c +++ /dev/null @@ -1,2482 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extension peripheral: - * + RTC Time Stamp functions - * + RTC Tamper functions - * + RTC Wake-up functions - * + Extension Control functions - * + Extension RTC features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer with interrupt mode - using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() - function. - - *** TimeStamp configuration *** - =============================== - [..] - (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the - HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with - interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - (+) The TIMESTAMP alternate function can be mapped to RTC_AF1 (PC13). - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, precharge or discharge and Pull-UP using the - HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt - mode using HAL_RTCEx_SetTamper_IT() function. - (+) The TAMPER1 alternate function can be mapped to RTC_AF1 (PC13). - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup RTC_Exported_Functions - * @{ - */ - - -/** @addtogroup RTC_Exported_Functions_Group1 - * @{ - */ - -/** - * @brief DeInitializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This function does not reset the RTC Backup Data registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; - hrtc->Instance->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= (uint32_t)0x00000007; - - tickstart = HAL_GetTick(); - - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; - hrtc->Instance->WUTR = (uint32_t)0x0000FFFF; - hrtc->Instance->PRER = (uint32_t)0x007F00FF; - hrtc->Instance->CALIBR = (uint32_t)0x00000000; - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - hrtc->Instance->TAFCR = 0x00000000; - - /* Wait for synchro */ - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); - - hrtc->State = HAL_RTC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group2 - * @{ - */ - -/** - * @brief Gets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Get subseconds values from the correspondent registers*/ - sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Get the TR register */ - tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if(Format == FORMAT_BIN) - { - /* Convert the time structure parameters to Binary format */ - sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); - sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); - sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group3 - * @{ - */ - -/** - * @brief Sets the specified RTC Alarm. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* Clear flag alarm B */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); - } - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); - - EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets the RTC Alarm value and masks. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) -{ - uint32_t tmpreg = 0; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(Alarm)); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - sAlarm->Alarm = RTC_ALARM_A; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - } - else - { - sAlarm->Alarm = RTC_ALARM_B; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - } - - /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - - if(Format == FORMAT_BIN) - { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); - sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - } - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup RTC_Exported_Functions_Group6 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Wait for RTC Time and Date Synchronization - -@endverbatim - * @{ - */ - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - { - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - - tickstart = HAL_GetTick(); - - /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTCEx RTCEx - * @brief RTC Extended HAL module driver - * @{ - */ - -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - -/** @defgroup RTCEx_Exported_Functions_Group4 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions - * -@verbatim - =============================================================================== - ##### RTC TimeStamp and Tamper functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure TimeStamp feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg|= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets TimeStamp with Interrupt. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg |= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); - - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); - - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets the RTC TimeStamp value. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * FORMAT_BIN: Binary data format - * FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - sTimeStamp->SubSeconds = (uint32_t)((hrtc->Instance->TSSSR) & RTC_TSSSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == FORMAT_BIN) - { - /* Convert the TimeStamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); - sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); - sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); - - /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); - sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); - } - - /* Clear the TIMESTAMP Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - return HAL_OK; -} - -/** - * @brief Sets Tamper - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper: Pointer to Tamper Structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) - { - /* Configure the RTC_TAFCR register */ - sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE; - } - else - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ - (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ - (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE); -#else - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Trigger)); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG); - -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - hrtc->Instance->TAFCR |= tmpreg; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper: Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Configure the tamper trigger */ - if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) - { - sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE; - } - else - { - sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1); - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ - (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ - (uint32_t)RTC_TAFCR_TAMPPUDIS); -#else - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPIE); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - hrtc->Instance->TAFCR |= tmpreg; - - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); - - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates Tamper. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Tamper: Selected tamper pin. - * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - assert_param(IS_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the selected Tamper pin */ - hrtc->Instance->TAFCR &= (uint32_t)~Tamper; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief This function handles TimeStamp interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) - { - /* TIMESTAMP callback */ - HAL_RTCEx_TimeStampEventCallback(hrtc); - - /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); - } - } - - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1)) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) - { - /* Tamper callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); - } - } - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2)) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) - { - /* Tamper callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - } - } - - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP3)) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) - { - /* Tamper callback */ - HAL_RTCEx_Tamper3EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - } - } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Clear the EXTI s Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief TimeStamp callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 1 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file - */ -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Tamper 2 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 3 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file - */ -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @brief This function handles TimeStamp polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) - { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) - { - /* Clear the TIMESTAMP OverRun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles Tamper1 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief This function handles Tamper2 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles Tamper3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group5 RTC Wake-up functions - * @brief RTC Wake-up functions - * -@verbatim - =============================================================================== - ##### RTC Wake-up functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Wake-up feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets wake up timer. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets wake up timer with interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); - - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - - tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval Counter value - */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief This function handles Wake Up Timer interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) - { - /* WAKEUPTIMER callback */ - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); - - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - } - } - - /* Clear the EXTI s line Flag for RTC WakeUpTimer */ - __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Wake Up Timer callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles Wake Up Timer Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - } - - /* Clear the WAKEUPTIMER Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group7 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extension Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Writes a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Sets the Coarse calibration parameters. - (+) Deactivates the Coarse calibration parameters - (+) Sets the Smooth calibration parameters. - (+) Configures the Synchronization Shift Control Settings. - (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enables the RTC reference clock detection. - (+) Disable the RTC reference clock detection. - (+) Enables the Bypass Shadow feature. - (+) Disables the Bypass Shadow feature. - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @brief Sets the Coarse calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CalibSign: Specifies the sign of the coarse calibration value. - * This parameter can be one of the following values : - * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive - * @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Enable the Coarse Calibration */ - __HAL_RTC_COARSE_CALIB_ENABLE(hrtc); - - /* Set the coarse calibration value */ - hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates the Coarse calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Enable the Coarse Calibration */ - __HAL_RTC_COARSE_CALIB_DISABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Sets the Smooth calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue must be equal to 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - tickstart = HAL_GetTick(); - - /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - - /* Wait for synchro */ - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) -#else -/** - * @brief Configure the Calibration Pinout (RTC_CALIB). - * @param hrtc : RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -{ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enables the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) -/** - * @brief Enables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group8 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) RTC Alram B callback - (+) RTC Poll for Alarm B request - -@endverbatim - * @{ - */ - -/** - * @brief Alarm B callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file - */ -} - -/** - * @brief This function handles AlarmB Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm Flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c deleted file mode 100644 index c47de33de..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c +++ /dev/null @@ -1,3439 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_sd.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief SD card HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Secure Digital (SD) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver implements a high level communication layer for read and write from/to - this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by - the user in HAL_SD_MspInit() function (MSP layer). - Basically, the MSP layer configuration should be the same as we provide in the - examples. - You can easily tailor this configuration according to hardware resources. - - [..] - This driver is a generic layered driver for SDIO memories which uses the HAL - SDIO driver functions to interface with SD and uSD cards devices. - It is used as follows: - - (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API: - (##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE(); - (##) SDIO pins configuration for SD card - (+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE(); - (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init() - and according to your pin assignment; - (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() - and HAL_SD_WriteBlocks_DMA() APIs). - (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE(); - (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. - (##) NVIC configuration if you need to use interrupt process when using DMA transfer. - (+++) Configure the SDIO and DMA interrupt priorities using functions - HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority - (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT() - and __HAL_SD_SDIO_DISABLE_IT() inside the communication process. - (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT() - and __HAL_SD_SDIO_CLEAR_IT() - (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - - - *** SD Card Initialization and configuration *** - ================================================ - [..] - To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - the SD Card and put it into StandBy State (Ready for data transfer). - This function provide the following operations: - - (#) Apply the SD Card initialization process at 400KHz and check the SD Card - type (Standard Capacity or High Capacity). You can change or adapt this - frequency by adjusting the "ClockDiv" field. - The SD Card frequency (SDIO_CK) is computed as follows: - - SDIO_CK = SDIOCLK / (ClockDiv + 2) - - In initialization mode and according to the SD Card standard, - make sure that the SDIO_CK frequency doesn't exceed 400KHz. - - (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo - structure. This structure provide also ready computed SD Card capacity - and Block size. - - -@- These information are stored in SD handle structure in case of future use. - - (#) Configure the SD Card Data transfer frequency. By Default, the card transfer - frequency is set to 48MHz / (SDIO_TRANSFER_CLK_DIV + 2) = 8MHz. You can change or adapt this frequency by adjusting - the "ClockDiv" field. - The SD Card frequency (SDIO_CK) is computed as follows: - - SDIO_CK = SDIOCLK / (ClockDiv + 2) - - In transfer mode and according to the SD Card standard, make sure that the - SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. - To be able to use a frequency higher than 24MHz, you should use the SDIO - peripheral in bypass mode. Refer to the corresponding reference manual - for more details. - - (#) Select the corresponding SD Card according to the address read with the step 2. - - (#) Configure the SD Card in wide bus mode: 4-bits data. - - *** SD Card Read operation *** - ============================== - [..] - (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function support only 512-byte block length (the block size should be - chosen as 512 byte). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - - (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function support only 512-byte block length (the block size should be - chosen as 512 byte). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckReadOperation(), to insure - that the read transfer is done correctly in both DMA and SD sides. - - *** SD Card Write operation *** - =============================== - [..] - (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function support only 512-byte block length (the block size should be - chosen as 512 byte). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - - (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function support only 512-byte block length (the block size should be - chosen as 512 byte). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure - that the write transfer is done correctly in both DMA and SD sides. - - *** SD card status *** - ====================== - [..] - (+) At any time, you can check the SD Card status and get the SD card state - by using the HAL_SD_GetStatus() function. This function checks first if the - SD card is still connected and then get the internal SD Card transfer state. - (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() - function. - - *** SD HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in SD HAL driver. - - (+) __HAL_SD_SDIO_ENABLE : Enable the SD device - (+) __HAL_SD_SDIO_DISABLE : Disable the SD device - (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer - (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer - (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt - (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt - (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not - (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags - - (@) You can refer to the SD HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup SD SD - * @brief SD HAL module driver - * @{ - */ - -#ifdef HAL_SD_MODULE_ENABLED -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup SD_Private_Define SD Private Define - * @{ - */ - -/** - * @brief SDIO Static flags, TimeOut, FIFO Address - */ -#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ - SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ - SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ - SDIO_FLAG_DBCKEND)) - -#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) - -/** - * @brief Mask for errors Card Status R1 (OCR Register) - */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) - -/** - * @brief Masks for R6 Response - */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) - -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) - -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) - -#define SD_HALFFIFO ((uint32_t)0x00000008) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) - -/** - * @brief Command Class Supported - */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) -#define SD_CCCC_ERASE ((uint32_t)0x00000020) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SD_Private_Functions SD Private Functions - * @{ - */ - -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr); -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus); -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD); -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA); -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** @defgroup SD_Exported_Functions SD Exported Functions - * @{ - */ - -/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize the SD - card device to be ready for use. - - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SD card according to the specified parameters in the - SD_HandleTypeDef and create the associated handle. - * @param hsd: SD handle - * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information - * @retval HAL SD error state - */ -HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo) -{ - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - SD_InitTypeDef tmpinit; - - /* Initialize the low level hardware (MSP) */ - HAL_SD_MspInit(hsd); - - /* Default SDIO peripheral configuration for SD card initialization */ - tmpinit.ClockEdge = SDIO_CLOCK_EDGE_RISING; - tmpinit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - tmpinit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - tmpinit.BusWide = SDIO_BUS_WIDE_1B; - tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - tmpinit.ClockDiv = SDIO_INIT_CLK_DIV; - - /* Initialize SDIO peripheral interface with default configuration */ - SDIO_Init(hsd->Instance, tmpinit); - - /* Identify card operating voltage */ - errorstate = SD_PowerON(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Initialize the present SDIO card(s) and put them in idle state */ - errorstate = SD_Initialize_Cards(hsd); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Read CSD/CID MSD registers */ - errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo); - - if (errorstate == SD_OK) - { - /* Select the Card */ - errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16)); - } - - /* Configure SDIO peripheral interface */ - SDIO_Init(hsd->Instance, hsd->Init); - - return errorstate; -} - -/** - * @brief De-Initializes the SD card. - * @param hsd: SD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) -{ - - /* Set SD power state to off */ - SD_PowerOFF(hsd); - - /* De-Initialize the MSP layer */ - HAL_SD_MspDeInit(hsd); - - return HAL_OK; -} - - -/** - * @brief Initializes the SD MSP. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_MspInit could be implemented in the user file - */ -} - -/** - * @brief De-Initialize SD MSP. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group2 IO operation functions - * @brief Data transfer functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the data - transfer from/to SD card. - -@endverbatim - * @{ - */ - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by polling mode. - * @param hsd: SD handle - * @param pReadBuffer: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size - * This parameter should be 512 - * @param NumberOfBlocks: Number of SD blocks to read - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - SDIO_DataInitTypeDef sdio_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t) BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdio_datainitstructure.DataBlockSize = (uint32_t)(9 << 4); - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else - { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; - } - - sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) - { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Poll on SDIO flags */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) - { - /* Read data from SDIO Rx FIFO */ - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } - } - else - { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* In case of single block transfer, no need of stop transfer at all */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) - { - /* Read data from SDIO Rx FIFO */ - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } - } - - /* Send stop transmission command in case of multiblock read */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\ - (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); - } - } - - /* Get error state */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - /* Empty FIFO if there is still any data */ - while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDIO_ReadFIFO(hsd->Instance); - tempbuff++; - count--; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Allows to write block(s) to a specified address in a card. The Data - * transfer is managed by polling mode. - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be written - * @param BlockSize: SD card Data block size - * This parameter should be 512. - * @param NumberOfBlocks: Number of SD blocks to write - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - SDIO_DataInitTypeDef sdio_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0; - uint32_t *tempbuff = (uint32_t *)pWriteBuffer; - uint8_t cardstate = 0; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - if(NumberOfBlocks > 1) - { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - } - else - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - - sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Set total number of bytes to write */ - totalnumberofbytes = NumberOfBlocks * BlockSize; - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Write block(s) in polling mode */ - if(NumberOfBlocks > 1) - { - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) - { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDIO_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else - { - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDIO_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; - } - } - } - } - else - { - /* In case of single data block transfer no need of stop command at all */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) - { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDIO_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else - { - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDIO_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; - } - } - } - } - - /* Send stop transmission command in case of multiblock write */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); - } - } - - /* Get error state */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR); - - errorstate = SD_TX_UNDERRUN; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Wait till the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) - { - errorstate = SD_IsCardProgramming(hsd, &cardstate); - } - - return errorstate; -} - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckReadOperation() - * to check the completion of the read process - * @param hsd: SD handle - * @param pReadBuffer: Pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size - * This paramater should be 512. - * @param NumberOfBlocks: Number of blocks to read. - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - SDIO_DataInitTypeDef sdio_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Read operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_READ_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_READ_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\ - SDIO_IT_DTIMEOUT |\ - SDIO_IT_DATAEND |\ - SDIO_IT_RXOVERR |\ - SDIO_IT_STBITERR)); - - /* Enable SDIO DMA transfer */ - __HAL_SD_SDIO_DMA_ENABLE(); - - /* Configure DMA user callbacks */ - hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt; - hsd->hdmarx->XferErrorCallback = SD_DMA_RxError; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Check number of blocks command */ - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else - { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; - } - - sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); - } - - /* Update the SD transfer error in SD handle */ - hsd->SdTransferErr = errorstate; - - return errorstate; -} - - -/** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckWriteOperation() - * to check the completion of the write process (by SD current status polling). - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be read - * @param BlockSize: the SD card Data block size - * This parameter should be 512. - * @param NumberOfBlocks: Number of blocks to write - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - SDIO_DataInitTypeDef sdio_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Write operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_WRITE_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\ - SDIO_IT_DTIMEOUT |\ - SDIO_IT_DATAEND |\ - SDIO_IT_TXUNDERR |\ - SDIO_IT_STBITERR)); - - /* Configure DMA user callbacks */ - hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt; - hsd->hdmatx->XferErrorCallback = SD_DMA_TxError; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)); - - /* Enable SDIO DMA transfer */ - __HAL_SD_SDIO_DMA_ENABLE(); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Check number of blocks command */ - if(NumberOfBlocks <= 1) - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - else - { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - } - - sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - hsd->SdTransferErr = errorstate; - - return errorstate; -} - -/** - * @brief This function waits until the SD DMA data read transfer is finished. - * This API should be called after HAL_SD_ReadBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } - - timeout = Timeout; - - /* Wait until the Rx transfer is no longer active */ - while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0)) - { - timeout--; - } - - /* Send stop command in multiblock read */ - if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK) - { - errorstate = HAL_SD_StopTransfer(hsd); - } - - if ((timeout == 0) && (errorstate == SD_OK)) - { - errorstate = SD_DATA_TIMEOUT; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) - { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); - } - - return errorstate; -} - -/** - * @brief This function waits until the SD DMA data write transfer is finished. - * This API should be called after HAL_SD_WriteBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } - - timeout = Timeout; - - /* Wait until the Tx transfer is no longer active */ - while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT)) && (timeout > 0)) - { - timeout--; - } - - /* Send stop command in multiblock write */ - if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK) - { - errorstate = HAL_SD_StopTransfer(hsd); - } - - if ((timeout == 0) && (errorstate == SD_OK)) - { - errorstate = SD_DATA_TIMEOUT; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) - { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); - } - - /* Wait until write is complete */ - while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK) - { - } - - return errorstate; -} - -/** - * @brief Erases the specified memory area of the given SD card. - * @param hsd: SD handle - * @param startaddr: Start byte address - * @param endaddr: End byte address - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - - uint32_t delay = 0; - __IO uint32_t maxdelay = 0; - uint8_t cardstate = 0; - - /* Check if the card command class supports erase command */ - if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0) - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } - - /* Get max delay value */ - maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2); - - if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Get start and end block for high capacity cards */ - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - startaddr /= 512; - endaddr /= 512; - } - - /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - sdio_cmdinitstructure.Argument =(uint32_t)startaddr; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - sdio_cmdinitstructure.Argument = (uint32_t)endaddr; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END); - - if (errorstate != SD_OK) - { - return errorstate; - } - } - - /* Send CMD38 ERASE */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_ERASE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE); - - if (errorstate != SD_OK) - { - return errorstate; - } - - for (; delay < maxdelay; delay++) - { - } - - /* Wait untill the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - delay = SD_DATATIMEOUT; - - while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) - { - errorstate = SD_IsCardProgramming(hsd, &cardstate); - delay--; - } - - return errorstate; -} - -/** - * @brief This function handles SD card interrupt request. - * @param hsd: SD handle - * @retval None - */ -void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) -{ - /* Check for SDIO interrupt flags */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND); - - /* SD transfer is complete */ - hsd->SdTransferCplt = 1; - - /* No transfer error */ - hsd->SdTransferErr = SD_OK; - - HAL_SD_XferCpltCallback(hsd); - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - hsd->SdTransferErr = SD_DATA_CRC_FAIL; - - HAL_SD_XferErrorCallback(hsd); - - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - hsd->SdTransferErr = SD_DATA_TIMEOUT; - - HAL_SD_XferErrorCallback(hsd); - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - hsd->SdTransferErr = SD_RX_OVERRUN; - - HAL_SD_XferErrorCallback(hsd); - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR); - - hsd->SdTransferErr = SD_TX_UNDERRUN; - - HAL_SD_XferErrorCallback(hsd); - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - hsd->SdTransferErr = SD_START_BIT_ERR; - - HAL_SD_XferErrorCallback(hsd); - } - else - { - /* No error flag set */ - } - - /* Disable all SDIO peripheral interrupt sources */ - __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\ - SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\ - SDIO_IT_RXOVERR | SDIO_IT_STBITERR); -} - - -/** - * @brief SD end of transfer callback. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SD Transfer Error callback. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @brief SD Transfer complete Rx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SD DMA transfer complete Rx error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxErrorCallback could be implemented in the user file - */ -} - -/** - * @brief SD Transfer complete Tx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SD DMA transfer complete error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the SD card - operations. - -@endverbatim - * @{ - */ - -/** - * @brief Returns information about specific card. - * @param hsd: SD handle - * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that - * contains all SD cardinformation - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t tmp = 0; - - pCardInfo->CardType = (uint8_t)(hsd->CardType); - pCardInfo->RCA = (uint16_t)(hsd->RCA); - - /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000) >> 24; - pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCardInfo->SD_csd.Reserved1 = tmp & 0x03; - - /* Byte 1 */ - tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; - pCardInfo->SD_csd.TAAC = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; - pCardInfo->SD_csd.NSAC = (uint8_t)tmp; - - /* Byte 3 */ - tmp = hsd->CSD[0] & 0x000000FF; - pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp; - - /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000) >> 24; - pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4); - - /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000) >> 16; - pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F); - - /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00) >> 8; - pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */ - - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0)) - { - pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); - pCardInfo->SD_csd.DeviceSize |= (tmp) << 2; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); - pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; - - pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); - pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); - pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - - pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ; - pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2)); - pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen); - pCardInfo->CardCapacity *= pCardInfo->CardBlockSize; - } - else if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); - pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); - - pCardInfo->SD_csd.DeviceSize |= (tmp << 8); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); - - pCardInfo->SD_csd.DeviceSize |= (tmp); - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); - - pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024; - pCardInfo->CardBlockSize = 512; - } - else - { - /* Not supported card type */ - errorstate = SD_ERROR; - } - - pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); - pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; - pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24); - pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; - pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); - pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.Reserved3 = 0; - pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01); - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); - pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; - pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; - pCardInfo->SD_csd.ECC = (tmp & 0x03); - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); - pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_csd.Reserved4 = 1; - - /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ManufacturerID = tmp; - - /* Byte 1 */ - tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.OEM_AppliID = tmp << 8; - - /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); - pCardInfo->SD_cid.OEM_AppliID |= tmp; - - /* Byte 3 */ - tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); - pCardInfo->SD_cid.ProdName1 = tmp << 24; - - /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ProdName1 |= tmp << 16; - - /* Byte 5 */ - tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdName1 |= tmp << 8; - - /* Byte 6 */ - tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdName1 |= tmp; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); - pCardInfo->SD_cid.ProdName2 = tmp; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ProdRev = tmp; - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdSN = tmp << 24; - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdSN |= tmp << 16; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); - pCardInfo->SD_cid.ProdSN |= tmp << 8; - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ProdSN |= tmp; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; - pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ManufactDate |= tmp; - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); - pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_cid.Reserved2 = 1; - - return errorstate; -} - -/** - * @brief Enables wide bus operation for the requested card if supported by - * card. - * @param hsd: SD handle - * @param WideMode: Specifies the SD card wide bus mode - * This parameter can be one of the following values: - * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC) - * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer - * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDIO_InitTypeDef init; - - /* MMC Card does not support this feature */ - if (hsd->CardType == MULTIMEDIA_CARD) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - if (WideMode == SDIO_BUS_WIDE_8B) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - else if (WideMode == SDIO_BUS_WIDE_4B) - { - errorstate = SD_WideBus_Enable(hsd); - } - else if (WideMode == SDIO_BUS_WIDE_1B) - { - errorstate = SD_WideBus_Disable(hsd); - } - else - { - /* WideMode is not a valid argument*/ - errorstate = SD_INVALID_PARAMETER; - } - - if (errorstate == SD_OK) - { - /* Configure the SDIO peripheral */ - init.ClockEdge = hsd->Init.ClockEdge; - init.ClockBypass = hsd->Init.ClockBypass; - init.ClockPowerSave = hsd->Init.ClockPowerSave; - init.BusWide = WideMode; - init.HardwareFlowControl = hsd->Init.HardwareFlowControl; - init.ClockDiv = hsd->Init.ClockDiv; - - /* Configure SDIO peripheral interface */ - SDIO_Init(hsd->Instance, init); - } - else - { - /* An error occured while enabling/disabling the wide bus*/ - } - } - else - { - /* Not supported card type */ - errorstate = SD_ERROR; - } - - return errorstate; -} - -/** - * @brief Aborts an ongoing data transfer. - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Send CMD12 STOP_TRANSMISSION */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION); - - return errorstate; -} - -/** - * @brief Switches the SD card to High Speed mode. - * This API must be used after "Transfer State" - * @note This operation should be followed by the configuration - * of PLL to have SDIOCK clock between 67 and 75 MHz - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - SDIO_DataInitTypeDef sdio_datainitstructure; - - uint8_t SD_hs[64] = {0}; - uint32_t SD_scr[2] = {0, 0}; - uint32_t SD_SPEC = 0 ; - uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; - - /* Initialize the Data control register */ - hsd->Instance->DCTRL = 0; - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, SD_scr); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Test the Version supported by the card*/ - SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000); - - if (SD_SPEC != SD_ALLZERO) - { - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)64; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = 64; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Send CMD6 switch mode */ - sdio_cmdinitstructure.Argument = 0x80FFFF01; - sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH); - - if (errorstate != SD_OK) - { - return errorstate; - } - - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDIO_ReadFIFO(hsd->Instance); - tempbuff++; - count--; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Test if the switch mode HS is ok */ - if ((SD_hs[13]& 2) != 2) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - } - - return errorstate; -} - -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in runtime the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the current SD card's status. - * @param hsd: SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status - * SD Status register) - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - SDIO_DataInitTypeDef sdio_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0; - - /* Check SD response */ - if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Set block size for card if it is not equal to current block size for card */ - sdio_cmdinitstructure.Argument = 64; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD55 */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = 64; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STAUS; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Get status data */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance); - } - - pSDstatus += 8; - } - } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) - { - *pSDstatus = SDIO_ReadFIFO(hsd->Instance); - pSDstatus++; - count--; - } - - /* Clear all the static status flags*/ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Gets the current sd card data status. - * @param hsd: SD handle - * @retval Data Transfer state - */ -HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd) -{ - HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER; - - /* Get SD card state */ - cardstate = SD_GetState(hsd); - - /* Find SD status according to card state*/ - if (cardstate == SD_CARD_TRANSFER) - { - return SD_TRANSFER_OK; - } - else if(cardstate == SD_CARD_ERROR) - { - return SD_TRANSFER_ERROR; - } - else - { - return SD_TRANSFER_BUSY; - } -} - -/** - * @brief Gets the SD card status. - * @param hsd: SD handle - * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that - * will contain the SD card status information - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t tmp = 0; - uint32_t sd_status[16]; - - errorstate = HAL_SD_SendSDStatus(hsd, sd_status); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Byte 0 */ - tmp = (sd_status[0] & 0xC0) >> 6; - pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp; - - /* Byte 0 */ - tmp = (sd_status[0] & 0x20) >> 5; - pCardStatus->SECURED_MODE = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (sd_status[2] & 0xFF); - pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8); - - /* Byte 3 */ - tmp = (sd_status[3] & 0xFF); - pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp; - - /* Byte 4 */ - tmp = (sd_status[4] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24); - - /* Byte 5 */ - tmp = (sd_status[5] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16); - - /* Byte 6 */ - tmp = (sd_status[6] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8); - - /* Byte 7 */ - tmp = (sd_status[7] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp; - - /* Byte 8 */ - tmp = (sd_status[8] & 0xFF); - pCardStatus->SPEED_CLASS = (uint8_t)tmp; - - /* Byte 9 */ - tmp = (sd_status[9] & 0xFF); - pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; - - /* Byte 10 */ - tmp = (sd_status[10] & 0xF0) >> 4; - pCardStatus->AU_SIZE = (uint8_t)tmp; - - /* Byte 11 */ - tmp = (sd_status[11] & 0xFF); - pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8); - - /* Byte 12 */ - tmp = (sd_status[12] & 0xFF); - pCardStatus->ERASE_SIZE |= (uint8_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[13] & 0xFC) >> 2; - pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[13] & 0x3); - pCardStatus->ERASE_OFFSET = (uint8_t)tmp; - - return errorstate; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SD_Private_Functions - * @{ - */ - -/** - * @brief SD DMA transfer complete Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; - - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } - - /* Transfer complete user callback */ - HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); -} - -/** - * @brief SD DMA transfer Error Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Transfer complete user callback */ - HAL_SD_DMA_RxErrorCallback(hsd->hdmarx); -} - -/** - * @brief SD DMA transfer complete Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; - - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } - - /* Transfer complete user callback */ - HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); -} - -/** - * @brief SD DMA transfer Error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Transfer complete user callback */ - HAL_SD_DMA_TxErrorCallback(hsd->hdmatx); -} - -/** - * @brief Returns the SD current state. - * @param hsd: SD handle - * @retval SD card current state - */ -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd) -{ - uint32_t resp1 = 0; - - if (SD_SendStatus(hsd, &resp1) != SD_OK) - { - return SD_CARD_ERROR; - } - else - { - return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); - } -} - -/** - * @brief Initializes all cards or single card as the case may be Card(s) come - * into standby state. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint16_t sd_rca = 1; - - if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */ - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } - - if(hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Send CMD2 ALL_SEND_CID */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get Card identification number data */ - hsd->CID[0] = SDIO_GetResponse(SDIO_RESP1); - hsd->CID[1] = SDIO_GetResponse(SDIO_RESP2); - hsd->CID[2] = SDIO_GetResponse(SDIO_RESP3); - hsd->CID[3] = SDIO_GetResponse(SDIO_RESP4); - } - - if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send CMD3 SET_REL_ADDR with argument 0 */ - /* SD Card publishes its RCA. */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca); - - if(errorstate != SD_OK) - { - return errorstate; - } - } - - if (hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Get the SD card RCA */ - hsd->RCA = sd_rca; - - /* Send CMD9 SEND_CSD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get Card Specific Data */ - hsd->CSD[0] = SDIO_GetResponse(SDIO_RESP1); - hsd->CSD[1] = SDIO_GetResponse(SDIO_RESP2); - hsd->CSD[2] = SDIO_GetResponse(SDIO_RESP3); - hsd->CSD[3] = SDIO_GetResponse(SDIO_RESP4); - } - - /* All cards are initialized */ - return errorstate; -} - -/** - * @brief Selects od Deselects the corresponding card. - * @param hsd: SD handle - * @param addr: Address of the card to be selected - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Send CMD7 SDIO_SEL_DESEL_CARD */ - sdio_cmdinitstructure.Argument = (uint32_t)addr; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD); - - return errorstate; -} - -/** - * @brief Enquires cards about their operating voltage and configures clock - * controls and stores SD information that will be needed in future - * in the SD handle. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t sdtype = SD_STD_CAPACITY; - - /* Power ON Sequence -------------------------------------------------------*/ - /* Disable SDIO Clock */ - __HAL_SD_SDIO_DISABLE(); - - /* Set Power State to ON */ - SDIO_PowerState_ON(hsd->Instance); - - /* Enable SDIO Clock */ - __HAL_SD_SDIO_ENABLE(); - - /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/ - /* No CMD response required */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_NO; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdError(hsd); - - if(errorstate != SD_OK) - { - /* CMD Response TimeOut (wait for CMDSENT flag) */ - return errorstate; - } - - /* CMD8: SEND_IF_COND ------------------------------------------------------*/ - /* Send CMD8 to verify SD card interface operating condition */ - /* Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /* CMD Response: R7 */ - sdio_cmdinitstructure.Argument = SD_CHECK_PATTERN; - sdio_cmdinitstructure.CmdIndex = SD_SDIO_SEND_IF_COND; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp7Error(hsd); - - if (errorstate == SD_OK) - { - /* SD Card 2.0 */ - hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; - sdtype = SD_HIGH_CAPACITY; - } - - /* Send CMD55 */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - /* If errorstate is Command TimeOut, it is a MMC card */ - /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - if(errorstate == SD_OK) - { - /* SD CARD */ - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) - { - - /* SEND CMD55 APP_CMD with RCA as 0 */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD41 */ - sdio_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp3Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get command response */ - response = SDIO_GetResponse(SDIO_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); - - count++; - } - - if(count >= SD_MAX_VOLT_TRIAL) - { - errorstate = SD_INVALID_VOLTRANGE; - - return errorstate; - } - - if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ - { - hsd->CardType = HIGH_CAPACITY_SD_CARD; - } - - } /* else MMC Card */ - - return errorstate; -} - -/** - * @brief Turns the SDIO output signals off. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Set Power State to OFF */ - SDIO_PowerState_OFF(hsd->Instance); - - return errorstate; -} - -/** - * @brief Returns the current card's status. - * @param hsd: SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card - * status (Card Status register) - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - if(pCardStatus == NULL) - { - errorstate = SD_INVALID_PARAMETER; - - return errorstate; - } - - /* Send Status command */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get SD card status */ - *pCardStatus = SDIO_GetResponse(SDIO_RESP1); - - return errorstate; -} - -/** - * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout, tmp; - - timeout = SDIO_CMD0TIMEOUT; - - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT); - - while((timeout > 0) && (!tmp)) - { - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT); - timeout--; - } - - if(timeout == 0) - { - errorstate = SD_CMD_RSP_TIMEOUT; - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_ERROR; - uint32_t timeout = SDIO_CMD0TIMEOUT, tmp; - - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); - - while((!tmp) && (timeout > 0)) - { - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); - timeout--; - } - - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - if((timeout == 0) || tmp) - { - /* Card is not V2.0 compliant or card does not support the set voltage range */ - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND)) - { - /* Card is SD V2.0 compliant */ - errorstate = SD_OK; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND); - - return errorstate; - } - - return errorstate; -} - -/** - * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1; - - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* We have received response, retrieve it for analysis */ - response_r1 = SDIO_GetResponse(SDIO_RESP1); - - if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } - - if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if((response_r1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - - return errorstate; -} - -/** - * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - - while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - - while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative - * address RCA - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1; - - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* We have received response, retrieve it. */ - response_r1 = SDIO_GetResponse(SDIO_RESP1); - - if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO) - { - *pRCA = (uint16_t) (response_r1 >> 16); - - return errorstate; - } - - if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - return errorstate; -} - -/** - * @brief Enables the SDIO wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - uint32_t scr[2] = {0, 0}; - - if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* If requested card supports wide bus operation */ - if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) - { - /* Send CMD55 APP_CMD with argument as card's RCA.*/ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - sdio_cmdinitstructure.Argument = 2; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) - { - return errorstate; - } - - return errorstate; - } - else - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } -} - -/** - * @brief Disables the SDIO wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - uint32_t scr[2] = {0, 0}; - - if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* If requested card supports 1 bit mode operation */ - if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) - { - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) - { - return errorstate; - } - - return errorstate; - } - else - { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; - } -} - - -/** - * @brief Finds the SD card SCR register value. - * @param hsd: SD handle - * @param pSCR: pointer to the buffer that will contain the SCR value - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - SDIO_DataInitTypeDef sdio_datainitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t index = 0; - uint32_t tempscr[2] = {0, 0}; - - /* Set Block Size To 8 Bytes */ - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)8; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = 8; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR); - - if(errorstate != SD_OK) - { - return errorstate; - } - - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) - { - *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance); - index++; - } - } - - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\ - ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - - *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\ - ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - - return errorstate; -} - -/** - * @brief Checks if the SD card is in programming state. - * @param hsd: SD handle - * @param pStatus: pointer to the variable that will contain the SD card state - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure; - HAL_SD_ErrorTypedef errorstate = SD_OK; - __IO uint32_t responseR1 = 0; - - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - - /* We have received response, retrieve it for analysis */ - responseR1 = SDIO_GetResponse(SDIO_RESP1); - - /* Find out card status */ - *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F); - - if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } - - if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } - - if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) - { - return(SD_STREAM_WRITE_OVERRUN); - } - - if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE) - { - return(SD_CID_CSD_OVERWRITE); - } - - if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } - - if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } - - if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) - { - return(SD_ERASE_RESET); - } - - if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } - - return errorstate; -} - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#endif /* HAL_SD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c deleted file mode 100644 index 198e68699..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c +++ /dev/null @@ -1,1411 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_smartcard.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief SMARTCARD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the SMARTCARD peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SMARTCARD HAL driver can be used as follows: - - (#) Declare a SMARTCARD_HandleTypeDef handle structure. - (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: - (##) Enable the USARTx interface clock. - (##) SMARTCARD pins configuration: - (+++) Enable the clock for the SMARTCARD GPIOs. - (+++) Configure these SMARTCARD pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() - and HAL_SMARTCARD_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() - and HAL_SMARTCARD_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. - - (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SMARTCARD_MspInit(&hsc) API. - - -@@- The specific SMARTCARD interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() - (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback - - *** SMARTCARD HAL driver macros list *** - ======================================== - [..] - Below the list of most used macros in SMARTCARD HAL driver. - - (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not - (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag - (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt - (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt - - [..] - (@) You can refer to the SMARTCARD HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup SMARTCARD SMARTCARD - * @brief HAL SMARTCARD module driver - * @{ - */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ -#define SMARTCARD_TIMEOUT_VALUE 22000 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions - * @{ - */ -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc); -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc); -static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc); -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions - * @{ - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in Smartcard mode. - [..] - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - [..] - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - [..] - (+) For the Smartcard mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length => Should be 9 bits (8 bits + parity) - (++) Stop Bit - (++) Parity: => Should be enabled - +-------------------------------------------------------------+ - | M bit | PCE bit | SMARTCARD frame | - |---------------------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - (++) USART polarity - (++) USART phase - (++) USART LastBit - (++) Receiver/transmitter modes - (++) Prescaler - (++) GuardTime - (++) NACKState: The Smartcard NACK state - - (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card: - (++) Word Length = 9 Bits - (++) 1.5 Stop Bit - (++) Even parity - (++) BaudRate = 12096 baud - (++) Tx and Rx enabled - [..] - Please refer to the ISO 7816-3 specification for more details. - - -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. - [..] - The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration - procedure (details for the procedure are available in reference manual (RM0038)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SmartCard mode according to the specified - * parameters in the SMARTCARD_HandleTypeDef and create the associated handle. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) -{ - /* Check the SMARTCARD handle allocation */ - if(hsc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState)); - - if(hsc->State == HAL_SMARTCARD_STATE_RESET) - { - /* Init the low level hardware */ - HAL_SMARTCARD_MspInit(hsc); - } - - hsc->State = HAL_SMARTCARD_STATE_BUSY; - - /* Set the Prescaler */ - MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler); - - /* Set the Guard Time */ - MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8)); - - /* Set the Smartcard Communication parameters */ - SMARTCARD_SetConfig(hsc); - - /* In SmartCard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register - - HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN); - CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - - /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); - - /* Enable the SMARTCARD Framing Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - - /* Enable the Peripharal */ - __HAL_SMARTCARD_ENABLE(hsc); - - /* Configure the Smartcard NACK state */ - MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState); - - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN); - - /* Initialize the SMARTCARD state*/ - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State= HAL_SMARTCARD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the SMARTCARD peripheral - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) -{ - /* Check the SMARTCARD handle allocation */ - if(hsc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - - hsc->State = HAL_SMARTCARD_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_SMARTCARD_DISABLE(hsc); - - /* DeInit the low level hardware */ - HAL_SMARTCARD_MspDeInit(hsc); - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsc); - - return HAL_OK; -} - -/** - * @brief SMARTCARD MSP Init. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ - __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspInit can be implemented in the user file - */ -} - -/** - * @brief SMARTCARD MSP DeInit. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ - __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. - - [..] - Smartcard is a single wire half duplex communication protocol. - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. The USART should be configured as: - - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register - - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the Transmit or Receive process - The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication - error is detected - - (#) Blocking mode APIs are : - (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() - - (#) Non Blocking mode APIs with Interrupt are : - (++) HAL_SMARTCARD_Transmit_IT() - (++) HAL_SMARTCARD_Receive_IT() - (++) HAL_SMARTCARD_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (++) HAL_SMARTCARD_Transmit_DMA() - (++) HAL_SMARTCARD_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SMARTCARD_TxCpltCallback() - (++) HAL_SMARTCARD_RxCpltCallback() - (++) HAL_SMARTCARD_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - - hsc->TxXferSize = Size; - hsc->TxXferCount = Size; - while(hsc->TxXferCount > 0) - { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) - { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData; - WRITE_REG(hsc->Instance->DR, (*tmp & (uint16_t)0x01FF)); - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - pData +=2; - } - else - { - pData +=1; - } - } - else - { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF)); - } - hsc->TxXferCount--; - } - - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - - hsc->RxXferSize = Size; - hsc->RxXferCount = Size; - /* Check the remain data to be received */ - while(hsc->RxXferCount > 0) - { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) - { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData; - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF); - pData +=2; - } - else - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF); - pData +=1; - } - } - else - { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F); - } - } - hsc->RxXferCount--; - } - - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pTxBuffPtr = pData; - hsc->TxXferSize = Size; - hsc->TxXferCount = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - - /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - /* Enable the SMARTCARD Transmit data register empty Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pRxBuffPtr = pData; - hsc->RxXferSize = Size; - hsc->RxXferCount = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - - /* Enable the SMARTCARD Data Register not empty Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); - - /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pTxBuffPtr = pData; - hsc->TxXferSize = Size; - hsc->TxXferCount = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - - /* Set the SMARTCARD DMA transfer complete callback */ - hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; - - /* Set the DMA error callback */ - hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError; - - /* Enable the SMARTCARD transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD CR3 register */ - SET_BIT(hsc->Instance->CR3,USART_CR3_DMAT); - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsc); - - hsc->pRxBuffPtr = pData; - hsc->RxXferSize = Size; - - hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - - /* Set the SMARTCARD DMA transfer complete callback */ - hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; - - /* Set the DMA error callback */ - hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError; - - /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the SMARTCARD CR3 register */ - SET_BIT(hsc->Instance->CR3,USART_CR3_DMAR); - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief This function handles SMARTCARD interrupt request. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE); - /* SMARTCARD parity error interrupt occurred -----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_SMARTCARD_CLEAR_PEFLAG(hsc); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; - } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); - /* SMARTCARD frame error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_SMARTCARD_CLEAR_FEFLAG(hsc); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; - } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); - /* SMARTCARD noise error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_SMARTCARD_CLEAR_NEFLAG(hsc); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; - } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); - /* SMARTCARD Over-Run interrupt occurred ---------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; - } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE); - /* SMARTCARD in mode Receiver --------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - SMARTCARD_Receive_IT(hsc); - } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE); - /* SMARTCARD in mode Transmitter -----------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - SMARTCARD_Transmit_IT(hsc); - } - - tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC); - tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC); - /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - SMARTCARD_EndTransmit_IT(hsc); - } - - /* Call the Error call Back in case of Errors */ - if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) - { - /* Set the SMARTCARD state ready to be able to start again the process */ - hsc->State= HAL_SMARTCARD_STATE_READY; - HAL_SMARTCARD_ErrorCallback(hsc); - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ - __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief SMARTCARD error callbacks. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ - __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_ErrorCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of SmartCard - communication process and also return Peripheral Errors occurred during communication process - (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state - of the SMARTCARD peripheral. - (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during - communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SMARTCARD state. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL state - */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) -{ - return hsc->State; -} - -/** - * @brief Return the SMARTCARD error code - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD Error Code - */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) -{ - return hsc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions - * @brief SMARTCARD Private functions - * @{ - */ -/** - * @brief DMA SMARTCARD transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - hsc->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD CR3 register */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); - - /* Wait for SMARTCARD TC Flag */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - hsc->State = HAL_SMARTCARD_STATE_TIMEOUT; - HAL_SMARTCARD_ErrorCallback(hsc); - } - else - { - /* No Timeout */ - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - HAL_SMARTCARD_TxCpltCallback(hsc); - } -} - -/** - * @brief DMA SMARTCARD receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - hsc->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); - - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - HAL_SMARTCARD_RxCpltCallback(hsc); -} - -/** - * @brief DMA SMARTCARD communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - hsc->RxXferCount = 0; - hsc->TxXferCount = 0; - hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - hsc->State= HAL_SMARTCARD_STATE_READY; - - HAL_SMARTCARD_ErrorCallback(hsc); -} - -/** - * @brief This function handles SMARTCARD Communication Timeout. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param Flag: specifies the SMARTCARD flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE and RXNE interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); - - hsc->State= HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE and RXNE interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); - - hsc->State= HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Send an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) - { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) - { - tmp = (uint16_t*) hsc->pTxBuffPtr; - WRITE_REG(hsc->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - hsc->pTxBuffPtr += 2; - } - else - { - hsc->pTxBuffPtr += 1; - } - } - else - { - WRITE_REG(hsc->Instance->DR, (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF)); - } - - if(--hsc->TxXferCount == 0) - { - /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - - /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); - - hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } - - HAL_SMARTCARD_TxCpltCallback(hsmartcard); - - return HAL_OK; -} - - -/** - * @brief Receive an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) -{ - uint16_t* tmp = 0; - uint32_t tmp1 = 0; - - tmp1 = hsc->State; - if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX)) - { - if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B) - { - tmp = (uint16_t*) hsc->pRxBuffPtr; - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF); - hsc->pRxBuffPtr += 2; - } - else - { - *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF); - hsc->pRxBuffPtr += 1; - } - } - else - { - if(hsc->Init.Parity == SMARTCARD_PARITY_NONE) - { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); - } - else - { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F); - } - } - - if(--hsc->RxXferCount == 0) - { - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); - - /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); - - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); - - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - - HAL_SMARTCARD_RxCpltCallback(hsc); - - return HAL_OK; - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configures the SMARTCARD peripheral. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) -{ - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity)); - assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase)); - assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); - assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate)); - assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)); - assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)); - assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity)); - assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode)); - assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState)); - - /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the - receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */ - CLEAR_BIT(hsc->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE)); - - /*-------------------------- SMARTCARD CR2 Configuration ------------------------*/ - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/ - /* Set CPOL bit according to hsc->Init.CLKPolarity value */ - /* Set CPHA bit according to hsc->Init.CLKPhase value */ - /* Set LBCL bit according to hsc->Init.CLKLastBit value */ - MODIFY_REG(hsc->Instance->CR2, - ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)), - ((uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | hsc->Init.CLKPhase| hsc->Init.CLKLastBit)) ); - - /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */ - MODIFY_REG(hsc->Instance->CR2, USART_CR2_STOP,(uint32_t)(hsc->Init.StopBits)); - - /*-------------------------- SMARTCARD CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE and RE bits */ - /* Configure the SMARTCARD Word Length, Parity and mode: - Set the M bits according to hsc->Init.WordLength value - Set PCE and PS bits according to hsc->Init.Parity value - Set TE and RE bits according to hsc->Init.Mode value */ - MODIFY_REG(hsc->Instance->CR1, - ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), - ((uint32_t)(hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode)) ); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Clear CTSE and RTSE bits */ - CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); - - /*-------------------------- USART BRR Configuration -----------------------*/ - if(hsc->Instance == USART1) - { - hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate); - } - else - { - hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate); - } -} - -/** - * @} - */ - -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c deleted file mode 100644 index d481bb749..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c +++ /dev/null @@ -1,2258 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_spi.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief SPI HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Serial Peripheral Interface (SPI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SPI HAL driver can be used as follows: - - (#) Declare a SPI_HandleTypeDef handle structure, for example: - SPI_HandleTypeDef hspi; - - (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: - (##) Enable the SPIx interface clock - (##) SPI pins configuration - (+++) Enable the clock for the SPI GPIOs - (+++) Configure these SPI pins as alternate function push-pull - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SPIx interrupt priority - (+++) Enable the NVIC SPI IRQ handle - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel - (+++) Enable the DMAx clock - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Channel - (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel - - (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS - management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - - (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SPI_MspInit() API. - [..] - Circular mode restriction: - (#) The DMA circular mode cannot be used when the SPI is configured in these modes: - (##) Master 2Lines RxOnly - (##) Master 1Line Rx - (#) The CRC feature is not managed when the DMA circular mode is enabled - (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs - the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks - - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup SPI SPI - * @brief SPI HAL module driver - * @{ - */ - -#ifdef HAL_SPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup SPI_Private_Constants SPI Private Constants - * @{ - */ -#define SPI_TIMEOUT_VALUE 10 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup SPI_Private_Functions SPI Private Functions - * @{ - */ - -static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi); -static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi); -static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi); -static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma); -static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma); -static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma); -static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Functions SPI Exported Functions - * @{ - */ - -/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the SPIx peripheral: - - (+) User must implement HAL_SPI_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SPI_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Direction - (++) Data Size - (++) Clock Polarity and Phase - (++) NSS Management - (++) BaudRate Prescaler - (++) FirstBit - (++) TIMode - (++) CRC Calculation - (++) CRC Polynomial if CRC enabled - - (+) Call the function HAL_SPI_DeInit() to restore the default configuration - of the selected SPIx periperal. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SPI according to the specified parameters - * in the SPI_InitTypeDef and create the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ - - -__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) -{ - return HAL_ERROR; -} - -/** - * @brief DeInitializes the SPI peripheral - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) -{ - /* Check the SPI handle allocation */ - if(hspi == NULL) - { - return HAL_ERROR; - } - - /* Disable the SPI Peripheral Clock */ - __HAL_SPI_DISABLE(hspi); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_SPI_MspDeInit(hspi); - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief SPI MSP Init - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ - __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) - { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_MspInit could be implenetd in the user file - */ -} - -/** - * @brief SPI MSP DeInit - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ - __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_MspDeInit could be implenetd in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the SPI - data transfers. - - [..] The SPI supports master and slave mode : - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode APIs are : - (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive() in full duplex mode - - (#) Non Blocking mode API's with Interrupt are : - (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive_IT()in full duplex mode - (++) HAL_SPI_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SPI_TxCpltCallback() - (++) HAL_SPI_RxCpltCallback() - (++) HAL_SPI_TxRxCpltCallback() - (++) HAL_SPI_TxHalfCpltCallback() - (++) HAL_SPI_RxHalfCpltCallback() - (++) HAL_SPI_TxRxHalfCpltCallback() - (++) HAL_SPI_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->RxISR = 0; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Configure communication direction : 1Line */ - SPI_1LINE_TX(hspi); - } - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Transmit data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) - { - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - } - while(hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - } - /* Transmit data in 16 Bit mode */ - else - { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) - { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - } - while(hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - } - - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - __IO uint16_t tmpreg = 0; - - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); - } - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - while(hspi->RxXferCount > 1) - { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - hspi->RxXferCount--; - } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - } - /* Receive data in 16 Bit mode */ - else - { - while(hspi->RxXferCount > 1) - { - /* Wait until RXNE flag is set to read data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - hspi->RxXferCount--; - } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Receive last data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - } - /* Receive last data in 16 Bit mode */ - else - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - } - hspi->RxXferCount--; - - /* Wait until RXNE flag is set: CRC Received */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - return HAL_TIMEOUT; - } - - /* Read CRC to Flush RXNE flag */ - tmpreg = hspi->Instance->DR; - } - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - - /* Reset CRC Calculation */ - SPI_RESET_CRC(hspi); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit and Receive an amount of data in blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer to be - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ - __IO uint16_t tmpreg = 0; - - if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) - { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State == HAL_SPI_STATE_READY) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - /* Configure communication */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->pRxBuffPtr = pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - hspi->pTxBuffPtr = pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Transmit and Receive data in 16 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) - { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) - { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - } - if(hspi->TxXferCount == 0) - { - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - hspi->RxXferCount--; - } - else - { - while(hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - - /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - hspi->RxXferCount--; - } - /* Receive the last byte */ - if(hspi->Init.Mode == SPI_MODE_SLAVE) - { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - hspi->RxXferCount--; - } - } - } - /* Transmit and Receive data in 8 Bit mode */ - else - { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) - { - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - } - if(hspi->TxXferCount == 0) - { - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->RxXferCount--; - } - else - { - while(hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - - /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - hspi->RxXferCount--; - } - if(hspi->Init.Mode == SPI_MODE_SLAVE) - { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - hspi->RxXferCount--; - } - } - } - - /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - return HAL_TIMEOUT; - } - /* Read CRC */ - tmpreg = hspi->Instance->DR; - } - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in no-blocking mode with Interrupt - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->TxISR = &SPI_TxISR; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); - }else - { - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - } - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->RxISR = &SPI_RxISR; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size ; - - /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer to be - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - - if((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) - { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process locked */ - __HAL_LOCK(hspi); - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - /* Configure communication */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->TxISR = &SPI_TxISR; - hspi->pTxBuffPtr = pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - hspi->RxISR = &SPI_2LinesRxISR; - hspi->pRxBuffPtr = pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in no-blocking mode with DMA - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->RxISR = 0; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - /* Set the SPI TxDMA Half transfer complete callback */ - hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - - /* Set the SPI TxDMA transfer complete callback */ - hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - - /* Enable the Tx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in no-blocking mode with DMA - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); - } - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - /* Set the SPI RxDMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - - /* Set the SPI Rx DMA transfer complete callback */ - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Enable the Rx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit and Receive an amount of data in no-blocking mode with DMA - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - if((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) - { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process locked */ - __HAL_LOCK(hspi); - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - /* Configure communication */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->pTxBuffPtr = (uint8_t*)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - hspi->pRxBuffPtr = (uint8_t*)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ - if(hspi->State == HAL_SPI_STATE_BUSY_RX) - { - /* Set the SPI Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - } - else - { - /* Set the SPI Tx/Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - } - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Enable the Rx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - } - else - { - hspi->hdmatx->XferErrorCallback = NULL; - } - - /* Enable the Tx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Pauses the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) -{ - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) -{ - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Enable the SPI DMA Tx & Rx requests */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() - */ - - /* Abort the SPI DMA tx Channel */ - if(hspi->hdmatx != NULL) - { - HAL_DMA_Abort(hspi->hdmatx); - } - /* Abort the SPI DMA rx Channel */ - if(hspi->hdmarx != NULL) - { - HAL_DMA_Abort(hspi->hdmarx); - } - - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - hspi->State = HAL_SPI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) -{ - /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ - if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) - { - hspi->RxISR(hspi); - return; - } - - /* SPI in mode Tramitter ---------------------------------------------------*/ - if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) - { - hspi->TxISR(hspi); - return; - } - - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) - { - /* SPI CRC error interrupt occurred ---------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - /* SPI Mode Fault error interrupt occurred --------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); - __HAL_SPI_CLEAR_MODFFLAG(hspi); - } - - /* SPI Overrun error interrupt occurred -----------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) - { - if(hspi->State != HAL_SPI_STATE_BUSY_TX) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - } - - /* SPI Frame error interrupt occurred -------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); - __HAL_SPI_CLEAR_FREFLAG(hspi); - } - - /* Call the Error call Back in case of Errors */ - if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) - { - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_ErrorCallback(hspi); - } - } -} - -/** - * @brief Tx Transfer completed callbacks - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxCpltCallback could be implenetd in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_RxCpltCallback() could be implenetd in the user file - */ -} - -/** - * @brief Tx and Rx Transfer completed callbacks - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file - */ -} - -/** - * @brief Tx and Rx Transfer completed callbacks - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file - */ -} - -/** - * @brief SPI error callbacks - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ - __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) -{ - /* NOTE : - This function Should not be modified, when the callback is needed, - the HAL_SPI_ErrorCallback() could be implenetd in the user file. - - The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occurred. - */ -} - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SPI control functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SPI. - (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral - (+) HAL_SPI_GetError() check in run-time Errors occurring during communication -@endverbatim - * @{ - */ - -/** - * @brief Return the SPI state - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL state - */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) -{ - return hspi->State; -} - -/** - * @brief Return the SPI error code - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI Error Code - */ -HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi) -{ - return hspi->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - - - -/** @addtogroup SPI_Private_Functions - * @{ - */ - - - /** - * @brief Interrupt Handler to close Tx transfer - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi) -{ - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE )); - - /* Disable ERR interrupt if Receive process is finished */ - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) - { - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - /* Check if we are in Tx or in Rx/Tx Mode */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxRxCpltCallback(hspi); - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxCpltCallback(hspi); - } - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - /* Call Error call back in case of Error */ - HAL_SPI_ErrorCallback(hspi); - } - } -} - -/** - * @brief Interrupt Handler to transmit amount of data in no-blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - } - /* Transmit data in 16 Bit mode */ - else - { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - } - hspi->TxXferCount--; - - if(hspi->TxXferCount == 0) - { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - /* calculate and transfer CRC on Tx line */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - SPI_TxCloseIRQHandler(hspi); - } -} - -/** - * @brief Interrupt Handler to close Rx transfer - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint16_t tmpreg = 0; - - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Read CRC to reset RXNE flag */ - tmpreg = hspi->Instance->DR; - - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - - /* Reset CRC Calculation */ - SPI_RESET_CRC(hspi); - } - } - - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); - - /* if Transmit process is finished */ - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) - { - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - /* Check if we are in Rx or in Rx/Tx Mode */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxRxCpltCallback(hspi); - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_RxCpltCallback(hspi); - } - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - /* Call Error call back in case of Error */ - HAL_SPI_ErrorCallback(hspi); - } - } -} - -/** - * @brief Interrupt Handler to receive amount of data in 2Lines mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi) -{ - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - } - /* Receive data in 16 Bit mode */ - else - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - } - hspi->RxXferCount--; - - if(hspi->RxXferCount==0) - { - SPI_RxCloseIRQHandler(hspi); - } -} - -/** - * @brief Interrupt Handler to receive amount of data in no-blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi) -{ - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - } - /* Receive data in 16 Bit mode */ - else - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - } - hspi->RxXferCount--; - - /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) - { - /* Set CRC Next to calculate CRC on Rx side */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - - if(hspi->RxXferCount == 0) - { - SPI_RxCloseIRQHandler(hspi); - } -} - -/** - * @brief DMA SPI transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal Mode */ - if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - hspi->TxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - } - - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); - } - else - { - HAL_SPI_TxCpltCallback(hspi); - } -} - -/** - * @brief DMA SPI receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma) -{ - __IO uint16_t tmpreg = 0; - - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) - { - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Read CRC */ - tmpreg = hspi->Instance->DR; - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - } - - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); - } - else - { - HAL_SPI_RxCpltCallback(hspi); - } - } - else - { - HAL_SPI_RxCpltCallback(hspi); - } -} - -/** - * @brief DMA SPI transmit receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma) -{ - __IO uint16_t tmpreg = 0; - - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) - { - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - /* Check if CRC is done on going (RXNE flag set) */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) - { - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - } - /* Read CRC */ - tmpreg = hspi->Instance->DR; - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - } - - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; - - hspi->State = HAL_SPI_STATE_READY; - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - HAL_SPI_ErrorCallback(hspi); - } - else - { - HAL_SPI_TxRxCpltCallback(hspi); - } - } - else - { - HAL_SPI_TxRxCpltCallback(hspi); - } -} - -/** - * @brief DMA SPI half transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_SPI_TxHalfCpltCallback(hspi); -} - -/** - * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_SPI_RxHalfCpltCallback(hspi); -} - -/** - * @brief DMA SPI Half transmit receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_SPI_TxRxHalfCpltCallback(hspi); -} - -/** - * @brief DMA SPI communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAError(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; - hspi->State= HAL_SPI_STATE_READY; - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - HAL_SPI_ErrorCallback(hspi); -} - -/** - * @brief This function handles SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param Status: Flag status to check: RESET or set - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - hspi->State= HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - SPI_RESET_CRC(hspi); - } - - hspi->State= HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} -/** - * @} - */ - -#endif /* HAL_SPI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi_ex.c deleted file mode 100644 index 642c2c532..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi_ex.c +++ /dev/null @@ -1,153 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_spi_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief Extended SPI HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities SPI extension peripheral: - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ -#ifdef HAL_SPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup SPI_Exported_Functions - * @{ - */ - -/** @addtogroup SPI_Exported_Functions_Group1 - * - * @{ - */ - -/** - * @brief Initializes the SPI according to the specified parameters - * in the SPI_InitTypeDef and create the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) -{ - /* Check the SPI handle allocation */ - if(hspi == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); - assert_param(IS_SPI_MODE(hspi->Init.Mode)); - assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); - assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); - assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); - assert_param(IS_SPI_NSS(hspi->Init.NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); - assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); - assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - - if(hspi->State == HAL_SPI_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_SPI_MspInit(hspi); - } - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Disble the selected SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ - /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, - Communication speed, First bit and CRC calculation state */ - hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); - - /* Configure : NSS management */ - hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode); - - /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ - /* Configure : CRC Polynomial */ - hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; - -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) - /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ - CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); -#endif - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_SPI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c deleted file mode 100644 index ce10a4a43..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c +++ /dev/null @@ -1,681 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_sram.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief SRAM HAL module driver. - * This file provides a generic firmware to drive SRAM memories - * mounted as external device. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control SRAM memories. It uses the FSMC layer functions to interface - with SRAM devices. - The following sequence should be followed to configure the FSMC to interface - with SRAM/PSRAM memories: - - (#) Declare a SRAM_HandleTypeDef handle structure, for example: - SRAM_HandleTypeDef hsram; and: - - (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed - values of the structure member. - - (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SRAM device - - (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined - base register instance for NOR or SRAM extended mode - - (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended - mode timings; for example: - FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming; - and fill its fields with the allowed values of the structure member. - - (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function - performs the following sequence: - - (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() - (##) Control register configuration using the FSMC NORSRAM interface function - FSMC_NORSRAM_Init() - (##) Timing register configuration using the FSMC NORSRAM interface function - FSMC_NORSRAM_Timing_Init() - (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function - FSMC_NORSRAM_Extended_Timing_Init() - (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE() - - (#) At this stage you can perform read/write accesses from/to the memory connected - to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the - following APIs: - (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access - (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer - - (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ - HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation - - (#) You can continuously monitor the SRAM device HAL state by calling the function - HAL_SRAM_GetState() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup SRAM SRAM - * @brief SRAM driver modules - * @{ - */ -#ifdef HAL_SRAM_MODULE_ENABLED - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_Functions SRAM Exported Functions - * @{ - */ - -/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### SRAM Initialization and de_initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize/de-initialize - the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Performs the SRAM device initialization sequence - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param Timing: Pointer to SRAM control timing structure - * @param ExtTiming: Pointer to SRAM extended mode timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) -{ - /* Check the SRAM handle parameter */ - if(hsram == NULL) - { - return HAL_ERROR; - } - - if(hsram->State == HAL_SRAM_STATE_RESET) - { - /* Initialize the low level hardware (MSP) */ - HAL_SRAM_MspInit(hsram); - } - - /* Initialize SRAM control Interface */ - FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); - - /* Initialize SRAM timing Interface */ - FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); - - /* Initialize SRAM extended mode timing Interface */ - FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); - - /* Enable the NORSRAM device */ - __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); - - return HAL_OK; -} - -/** - * @brief Performs the SRAM device De-initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) -{ - /* De-Initialize the low level hardware (MSP) */ - HAL_SRAM_MspDeInit(hsram); - - /* Configure the SRAM registers with their reset values */ - FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); - - hsram->State = HAL_SRAM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief SRAM MSP Init. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspInit could be implemented in the user file - */ -} - -/** - * @brief SRAM MSP DeInit. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete error callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### SRAM Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Reads 8-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint8_t * psramaddress = (uint8_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint8_t *)psramaddress; - pDstBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 8-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint8_t * psramaddress = (uint8_t *)pAddress; - - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint8_t *)psramaddress = *pSrcBuffer; - pSrcBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads 16-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) -{ - __IO uint16_t * psramaddress = (uint16_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint16_t *)psramaddress; - pDstBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 16-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) -{ - __IO uint16_t * psramaddress = (uint16_t *)pAddress; - - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint16_t *)psramaddress = *pSrcBuffer; - pSrcBuffer++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads 32-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) - { - *pDstBuffer = *(__IO uint32_t *)pAddress; - pDstBuffer++; - pAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes 32-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) - { - *(__IO uint32_t *)pAddress = *pSrcBuffer; - pSrcBuffer++; - pAddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Reads a Words data from the SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Writes a Words data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) -{ - /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### SRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the SRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Enable write operation */ - FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief Disables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) -{ - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Disable write operation */ - FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### SRAM State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the SRAM controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SRAM controller state - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL state - */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) -{ - return hsram->State; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -#endif /* HAL_SRAM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c deleted file mode 100644 index ada3b3f93..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c +++ /dev/null @@ -1,5039 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration - * + Time Master and Slave synchronization configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to interconnect - several timers together. - (#) Supports incremental (quadrature) encoder - - ##### How to use this driver ##### -================================================================================ - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending from feature used : - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); - -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); - -static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAError(DMA_HandleTypeDef *hdma); -static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); - -/** - * @} - */ - -/* External functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim: TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim : TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim : TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim : TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim : TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim : TIM handle - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim : TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * -@verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim: TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * -@verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. - (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim: TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * -@verbatim - ============================================================================== - ##### Time Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim: TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM INput Capture MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * -@verbatim - ============================================================================== - ##### Time One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM OnePulse handle - * @param OnePulseMode: Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim: TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * -@verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); - - /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= (~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F)); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim: TIM Encoder handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_ALL: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); - - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - default: - break; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim: TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - HAL_TIM_PeriodElapsedCallback(htim); - } - } - /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - HAL_TIM_TriggerCallback(htim); - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle - * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim: TIM IC handle - * @param sConfig: TIM Input Capture configuration structure - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM handle - * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: TIM One Pulse handle - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if(OutputChannel != InputChannel) - { - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Ouput compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - } - break; - default: - break; - } - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write - * This parameters can be on of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_DCR - * @param BurstRequestSrc: TIM DMA Request sources - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read - * This parameters can be on of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param BurstRequestSrc: TIM DMA Request sources - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Generate a software event - * @param htim: TIM handle - * @param EventSource: specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note TBC can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) -{ - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Clear the OCREF clear selection bit */ - CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - - /* Clear the ETR Bits */ - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - - } - break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - } - break; - - default: - break; - - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim: TIM handle - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - /* Reset the SMS and TS Bits */ - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - } - break; - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - } - break; - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - } - break; - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - } - break; - case TIM_CLOCKSOURCE_ITR0: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); - } - break; - case TIM_CLOCKSOURCE_ITR1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - case TIM_CLOCKSOURCE_ITR2: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: TIM handle. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim: TIM handle. - * @param Channel : TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0; - - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non blocking mode - * @param htim : TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ - -} -/** - * @brief Output Compare callback in non blocking mode - * @param htim : TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} -/** - * @brief Input Capture callback in non blocking mode - * @param htim : TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non blocking mode - * @param htim : TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non blocking mode - * @param htim : TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non blocking mode - * @param htim : TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base state - * @param htim: TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC state - * @param htim: TIM Ouput Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM state - * @param htim: TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture state - * @param htim: TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode state - * @param htim: TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode state - * @param htim: TIM Encoder handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @addtogroup TIM_Private_Functions - * @{ - */ - - -/** - * @brief TIM DMA error callback - * @param hdma : pointer to DMA handle. - * @retval None - */ -static void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_ErrorCallback(htim); -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma : pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_PWM_PulseFinishedCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture complete callback. - * @param hdma : pointer to DMA handle. - * @retval None - */ -static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_IC_CaptureCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma : pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_PeriodElapsedCallback(htim); -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma : pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_TriggerCallback(htim); -} - -/** - * @brief Time Base configuration - * @param TIMx: TIM periheral - * @param Structure: TIM Base configuration structure - * @retval None - */ -static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1 = 0; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Time Ouput Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure - * @retval None - */ -static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= (TIM_ICFilter << 4); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (TIM_ICPolarity << 8); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= (TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (TIM_ICPolarity << 12); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) -{ - uint32_t tmpsmcr = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. - * @retval None - */ -static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = (uint16_t)(TIM_CCER_CC1E << Channel); - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); -} - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ - - - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c deleted file mode 100644 index 8c40bfd15..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c +++ /dev/null @@ -1,260 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim_ex.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer extension peripheral: - * + Time Master and Slave synchronization configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extension features include: - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Timer remapping capabilities configuration - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM in master mode. - * @param htim: TIM handle. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the MMS Bits */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; - - /* Reset the MSM Bit */ - htim->Instance->SMCR &= ~TIM_SMCR_MSM; - /* Set or Reset the MSM Bit */ - htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM2/TIM3/TIM9/TIM10/TIM11 Remapping input capabilities. - * @param htim: TIM handle. - * @param Remap: specifies the TIM remapping source. - * This parameter is a combination of the following values depending on TIM instance. - * - * For TIM2, the parameter can have the following values: - * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC - * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO - * - * For TIM3, the parameter can have the following values: - * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC - * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO - * - * For TIM9, the parameter is a combination of 2 fields (field1 | field2): - * field1 can have the following values: - * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO - * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O - * field2 can have the following values: - * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO - * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock - * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO - * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO - * - * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): - * field1 can have the following values: - * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP - * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI - * field2 can have the following values: - * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock - * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO - * field3 can have the following values: - * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO - * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock - * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock - * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt - * - * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): - * field1 can have the following values: - * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP - * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI - * field2 can have the following values: - * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock - * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO - * field3 can have the following values: - * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO - * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock - * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock - * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - __HAL_LOCK(htim); - - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(htim->Instance,Remap)); - - /* Set the Timer remapping configuration */ - htim->Instance->OR = Remap; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extension Callbacks functions - * @brief Extension Callbacks functions - * -@verbatim - ============================================================================== - ##### Extension Callbacks functions ##### - ============================================================================== - [..] - This section provides Extension TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extension Peripheral State functions - * @brief Extension Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extension Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c deleted file mode 100644 index e154e944f..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c +++ /dev/null @@ -1,1974 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_uart.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure. - - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (##) Enable the USARTx interface clock. - (##) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required - Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the huart Init structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. - - (#) For the Multi-Processor mode, initialize the UART registers by calling - the HAL_MultiProcessor_Init() API. - - [..] - (@) The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit - and receive process. - - [..] - (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the - low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed - HAL_UART_MspInit() API. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_UART_Transmit() - (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - (+) Pause the DMA Transfer using HAL_UART_DMAPause() - (+) Resume the DMA Transfer using HAL_UART_DMAResume() - (+) Stop the DMA Transfer using HAL_UART_DMAStop() - - *** UART HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in UART HAL driver. - - (+) __HAL_UART_ENABLE: Enable the UART peripheral - (+) __HAL_UART_DISABLE: Disable the UART peripheral - (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not - (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag - (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt - (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt - - [..] - (@) You can refer to the UART HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART HAL module driver - * @brief HAL UART module driver - * @{ - */ -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#define UART_TIMEOUT_VALUE 22000 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ -static void UART_SetConfig (UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | UART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Methode - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs - follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor - configuration procedures (details for the procedures are available in reference manual (RM0038)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the UART mode according to the specified parameters in - * the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* Check the parameters */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - else - { - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - } - - if(huart->State == HAL_UART_STATE_RESET) - { - /* Init the low level hardware */ - HAL_UART_MspInit(huart); - } - - huart->State = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check UART instance */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if(huart->State == HAL_UART_STATE_RESET) - { - /* Init the low level hardware */ - HAL_UART_MspInit(huart); - } - - huart->State = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - huart->Instance->CR3 |= USART_CR3_HDSEL; - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state*/ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the LIN mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param BreakDetectLength: Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection - * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - - /* LIN mode limited to 16-bit oversampling only */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - return HAL_ERROR; - } - - if(huart->State == HAL_UART_STATE_RESET) - { - /* Init the low level hardware */ - HAL_UART_MspInit(huart); - } - - huart->State = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In LIN mode, the following bits must be kept cleared: - - CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - huart->Instance->CR2 |= USART_CR2_LINEN; - - /* Set the USART LIN Break detection length. */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state*/ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the Multi-Processor mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param Address: UART node address - * @param WakeUpMethod: specifies the UART wakeup method. - * This parameter can be one of the following values: - * @arg UART_WAKEUPMETHOD_IDLELINE: Wakeup by an idle line detection - * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wakeup by an address mark - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check UART instance capabilities */ - assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance)); - - /* Check the Address & wake up method parameters */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - assert_param(IS_UART_ADDRESS(Address)); - - if(huart->State == HAL_UART_STATE_RESET) - { - /* Init the low level hardware */ - HAL_UART_MspInit(huart); - } - - huart->State = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In Multi-Processor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); - - /* Set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, Address); - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the UART peripheral. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - huart->State = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State = HAL_UART_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief UART MSP Init. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ - __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_MspInit could be implemented in the user file - */ -} - -/** - * @brief UART MSP DeInit. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ - __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit and Receive functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) Non blocking mode: The communication is performed using Interrupts - or DMA, these APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or receive process. - The HAL_UART_ErrorCallback() user callback will be executed when - a communication error is detected. - - (#) Blocking mode APIs are: - (++) HAL_UART_Transmit() - (++) HAL_UART_Receive() - - (#) Non Blocking mode APIs with Interrupt are: - (++) HAL_UART_Transmit_IT() - (++) HAL_UART_Receive_IT() - (++) HAL_UART_IRQHandler() - - (#) Non Blocking mode functions with DMA are: - (++) HAL_UART_Transmit_DMA() - (++) HAL_UART_Receive_DMA() - (++) HAL_UART_DMAPause() - (++) HAL_UART_DMAResume() - (++) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in non blocking mode: - (++) HAL_UART_TxHalfCpltCallback() - (++) HAL_UART_TxCpltCallback() - (++) HAL_UART_RxHalfCpltCallback() - (++) HAL_UART_RxCpltCallback() - (++) HAL_UART_ErrorCallback() - - [..] - (@) In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX - can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint32_t tmp1 = 0; - - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX)) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - while(huart->TxXferCount > 0) - { - huart->TxXferCount--; - if(huart->Init.WordLength == UART_WORDLENGTH_9B) - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData; - huart->Instance->DR = (*tmp & (uint16_t)0x01FF); - if(huart->Init.Parity == UART_PARITY_NONE) - { - pData +=2; - } - else - { - pData +=1; - } - } - else - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - huart->Instance->DR = (*pData++ & (uint8_t)0xFF); - } - } - - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint32_t tmp1 = 0; - - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Check the remain data to be received */ - while(huart->RxXferCount > 0) - { - huart->RxXferCount--; - if(huart->Init.WordLength == UART_WORDLENGTH_9B) - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pData ; - if(huart->Init.Parity == UART_PARITY_NONE) - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - pData +=2; - } - else - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - pData +=1; - } - - } - else - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if(huart->Init.Parity == UART_PARITY_NONE) - { - *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } - - } - } - - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp = 0; - - tmp = huart->State; - if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX)) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Transmit data register empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp = 0; - - tmp = huart->State; - if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX)) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Data Register not empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - uint32_t tmp1 = 0; - - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX)) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Enable the UART transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - uint32_t tmp1 = 0; - - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAR; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the DMA Transfer. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - } - else if(huart->State == HAL_UART_STATE_BUSY_RX) - { - /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - else if (huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx & Rx requests */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; - } - else if(huart->State == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_UART_CLEAR_OREFLAG(huart); - /* Enable the UART DMA Rx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; - } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_UART_CLEAR_OREFLAG(huart); - /* Enable the UART DMA Tx & Rx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; - huart->Instance->CR3 |= USART_CR3_DMAR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() - */ - - /* Disable the UART Tx/Rx DMA requests */ - huart->Instance->CR3 &= ~USART_CR3_DMAT; - huart->Instance->CR3 &= ~USART_CR3_DMAR; - - /* Abort the UART DMA tx channel */ - if(huart->hdmatx != NULL) - { - HAL_DMA_Abort(huart->hdmatx); - } - /* Abort the UART DMA rx channel */ - if(huart->hdmarx != NULL) - { - HAL_DMA_Abort(huart->hdmarx); - } - - huart->State = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles UART interrupt request. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE); - /* UART parity error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_UART_CLEAR_PEFLAG(huart); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); - /* UART frame error interrupt occurred -------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_UART_CLEAR_FEFLAG(huart); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); - /* UART noise error interrupt occurred -------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_UART_CLEAR_NEFLAG(huart); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); - /* UART Over-Run interrupt occurred ----------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_UART_CLEAR_OREFLAG(huart); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE); - /* UART in mode Receiver ---------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - UART_Receive_IT(huart); - } - - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE); - /* UART in mode Transmitter ------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - UART_Transmit_IT(huart); - } - - tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC); - tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC); - /* UART in mode Transmitter end --------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - UART_EndTransmit_IT(huart); - } - - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - - HAL_UART_ErrorCallback(huart); - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ - __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ - __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief UART error callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ - __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART: - (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. - (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. - (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. - (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode - (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode - -@endverbatim - * @{ - */ - -/** - * @brief Transmits break characters. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - - /* Send break characters */ - huart->Instance->CR1 |= USART_CR1_SBK; - - huart->State = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enters the UART in mute mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - huart->Instance->CR1 |= USART_CR1_RWU; - - huart->State = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Exits the UART mute mode: wake up software. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU); - - huart->State = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00; - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - - /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_TE; - - /* Write to USART CR1 */ - huart->Instance->CR1 = (uint32_t)tmpreg; - - huart->State = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00; - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - - /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_RE; - - /* Write to USART CR1 */ - huart->Instance->CR1 = (uint32_t)tmpreg; - - huart->State = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief UART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - UART communication process, return Peripheral Errors occurred during communication - process - (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. - (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the UART state. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) -{ - return huart->State; -} - -/** -* @brief Return the UART error code -* @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. -* @retval UART Error Code -*/ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @brief UART Private functions - * @{ - */ -/** - * @brief DMA UART transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - huart->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); - - /* Wait for UART TC Flag */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - huart->State = HAL_UART_STATE_TIMEOUT; - HAL_UART_ErrorCallback(huart); - } - else - { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - HAL_UART_TxCpltCallback(huart); - } - } - /* DMA Circular mode */ - else - { - HAL_UART_TxCpltCallback(huart); - } -} - -/** - * @brief DMA UART transmit process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_UART_TxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - huart->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - } - HAL_UART_RxCpltCallback(huart); -} - -/** - * @brief DMA UART receive process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_UART_RxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - huart->TxXferCount = 0; - huart->State= HAL_UART_STATE_READY; - huart->ErrorCode |= HAL_UART_ERROR_DMA; - HAL_UART_ErrorCallback(huart); -} - -/** - * @brief This function handles UART Communication Timeout. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param Flag: specifies the UART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_UART_GET_FLAG(huart, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint32_t tmp1 = 0; - - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) - { - if(huart->Init.WordLength == UART_WORDLENGTH_9B) - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); - if(huart->Init.Parity == UART_PARITY_NONE) - { - huart->pTxBuffPtr += 2; - } - else - { - huart->pTxBuffPtr += 1; - } - } - else - { - huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); - } - - if(--huart->TxXferCount == 0) - { - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - - /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Wraps up transmission in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } - - HAL_UART_TxCpltCallback(huart); - - return HAL_OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint32_t tmp1 = 0; - - tmp1 = huart->State; - if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX)) - { - if(huart->Init.WordLength == UART_WORDLENGTH_9B) - { - tmp = (uint16_t*) huart->pRxBuffPtr; - if(huart->Init.Parity == UART_PARITY_NONE) - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - huart->pRxBuffPtr += 2; - } - else - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - huart->pRxBuffPtr += 1; - } - } - else - { - if(huart->Init.Parity == UART_PARITY_NONE) - { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } - } - - if(--huart->RxXferCount == 0) - { - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } - HAL_UART_RxCpltCallback(huart); - - return HAL_OK; - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configures the UART peripheral. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00; - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the UART Word Length, Parity and mode: - Set the M bits according to huart->Init.WordLength value - Set PCE and PS bits according to huart->Init.Parity value - Set TE and RE bits according to huart->Init.Mode value - Set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; - MODIFY_REG(huart->Instance->CR1, - (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), - tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); - - /* Check the Over Sampling */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - /*-------------------------- USART BRR Configuration ---------------------*/ - if((huart->Instance == USART1)) - { - huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); - } - else - { - huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); - } - } - else - { - /*-------------------------- USART BRR Configuration ---------------------*/ - if((huart->Instance == USART1)) - { - huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); - } - else - { - huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); - } - } -} -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c deleted file mode 100644 index 5165676e2..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c +++ /dev/null @@ -1,1879 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_usart.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief USART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The USART HAL driver can be used as follows: - - (#) Declare a USART_HandleTypeDef handle structure. - (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: - (##) Enable the USARTx interface clock. - (##) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure these USART pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), - HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() - HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the husart Init structure. - - (#) Initialize the USART registers by calling the HAL_USART_Init() API: - (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_USART_MspInit(&husart) API. - - -@@- The specific USART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_USART_Transmit() - (+) Receive an amount of data in blocking mode using HAL_USART_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() - (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() - (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback - (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxCpltCallback - (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_USART_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() - (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() - (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback - (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxCpltCallback - (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_USART_ErrorCallback - (+) Pause the DMA Transfer using HAL_USART_DMAPause() - (+) Resume the DMA Transfer using HAL_USART_DMAResume() - (+) Stop the DMA Transfer using HAL_USART_DMAStop() - - *** USART HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in USART HAL driver. - - (+) __HAL_USART_ENABLE: Enable the USART peripheral - (+) __HAL_USART_DISABLE: Disable the USART peripheral - (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not - (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag - (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt - (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt - - [..] - (@) You can refer to the USART HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup USART USART - * @brief HAL USART Synchronous module driver - * @{ - */ -#ifdef HAL_USART_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup USART_Private_Constants USART Private Constants - * @{ - */ -#define DUMMY_DATA 0xFFFF -#define USART_TIMEOUT_VALUE 22000 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup USART_Private_Functions USART Private Functions - * @{ - */ -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); -static void USART_SetConfig (USART_HandleTypeDef *husart); -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - - -/** @defgroup USART_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - (++) USART polarity - (++) USART phase - (++) USART LastBit - (++) Receiver/transmitter modes - - [..] - The HAL_USART_Init() function follows the USART synchronous configuration - procedure (details for the procedure are available in reference manual (RM0038)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the USART mode according to the specified - * parameters in the USART_InitTypeDef and create the associated handle. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) -{ - /* Check the USART handle allocation */ - if(husart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); - - if(husart->State == HAL_USART_STATE_RESET) - { - /* Init the low level hardware */ - HAL_USART_MspInit(husart); - } - - husart->State = HAL_USART_STATE_BUSY; - - /* Set the USART Communication parameters */ - USART_SetConfig(husart); - - /* In USART mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register */ - CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN); - CLEAR_BIT(husart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); - - /* Enable the Peripheral */ - __HAL_USART_ENABLE(husart); - - /* Initialize the USART state */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State= HAL_USART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the USART peripheral. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) -{ - /* Check the USART handle allocation */ - if(husart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); - - husart->State = HAL_USART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_USART_DISABLE(husart); - - /* DeInit the low level hardware */ - HAL_USART_MspDeInit(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief USART MSP Init. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ - __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_MspInit could be implemented in the user file - */ -} - -/** - * @brief USART MSP DeInit. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ - __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART synchronous - data transfers. - - [..] - The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() - user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The HAL_USART_ErrorCallback() user callback will be executed when a communication - error is detected - - (#) Blocking mode APIs are : - (++) HAL_USART_Transmit() in simplex mode - (++) HAL_USART_Receive() in full duplex receive only - (++) HAL_USART_TransmitReceive() in full duplex mode - - (#) Non Blocking mode APIs with Interrupt are : - (++) HAL_USART_Transmit_IT()in simplex mode - (++) HAL_USART_Receive_IT() in full duplex receive only - (++) HAL_USART_TransmitReceive_IT() in full duplex mode - (++) HAL_USART_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (++) HAL_USART_Transmit_DMA()in simplex mode - (++) HAL_USART_Receive_DMA() in full duplex receive only - (++) HAL_USART_TransmitReceive_DMA() in full duplex mode - (++) HAL_USART_DMAPause() - (++) HAL_USART_DMAResume() - (++) HAL_USART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_USART_TxHalfCpltCallback() - (++) HAL_USART_TxCpltCallback() - (++) HAL_USART_RxHalfCpltCallback() - (++) HAL_USART_RxCpltCallback() - (++) HAL_USART_ErrorCallback() - (++) HAL_USART_TxRxCpltCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Simplex Send an amount of data in blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pTxData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp=0; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - husart->TxXferSize = Size; - husart->TxXferCount = Size; - while(husart->TxXferCount > 0) - { - husart->TxXferCount--; - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pTxData; - WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF)); - if(husart->Init.Parity == USART_PARITY_NONE) - { - pTxData += 2; - } - else - { - pTxData += 1; - } - } - else - { - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0xFF)); - } - } - - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Receive an amount of data in blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pRxData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp=0; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pRxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - husart->RxXferSize = Size; - husart->RxXferCount = Size; - /* Check the remain data to be received */ - while(husart->RxXferCount > 0) - { - husart->RxXferCount--; - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Send dummy byte in order to generate clock */ - WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); - - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pRxData ; - if(husart->Init.Parity == USART_PARITY_NONE) - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - pRxData +=2; - } - else - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - pRxData +=1; - } - } - else - { - /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Send Dummy Byte in order to generate clock */ - WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF)); - - /* Wait until RXNE flag is set to receive the byte */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if(husart->Init.Parity == USART_PARITY_NONE) - { - /* Receive data */ - *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); - } - else - { - /* Receive data */ - *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); - } - - } - } - - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp=0; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - husart->RxXferSize = Size; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - husart->RxXferCount = Size; - - /* Check the remain data to be received */ - while(husart->TxXferCount > 0) - { - husart->TxXferCount--; - husart->RxXferCount--; - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pTxData; - WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF)); - if(husart->Init.Parity == USART_PARITY_NONE) - { - pTxData += 2; - } - else - { - pTxData += 1; - } - - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t*) pRxData ; - if(husart->Init.Parity == USART_PARITY_NONE) - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - pRxData += 2; - } - else - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - pRxData += 1; - } - } - else - { - /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF)); - - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if(husart->Init.Parity == USART_PARITY_NONE) - { - /* Receive data */ - *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); - } - else - { - /* Receive data */ - *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); - } - } - } - - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pTxData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - * @note The USART errors are not managed to avoid the overrun error. - */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) -{ - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) - are not managed by the USART transmit process to avoid the overrun interrupt - when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" - to benefit for the frame error and noise interrupts the USART mode should be - configured only for transmit "USART_MODE_TX" - The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error, - Noise error interrupt */ - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pRxData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) -{ - if(husart->State == HAL_USART_STATE_READY) - { - if((pRxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->RxXferCount = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Enable the USART Data Register not empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); - - /* Enable the USART Parity Error Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_PE); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Send dummy byte in order to generate the clock for the slave to send data */ - WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer - * @param Size: Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->RxXferCount = Size; - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX_RX; - - /* Enable the USART Data Register not empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); - - /* Enable the USART Parity Error Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_PE); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pTxData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) -{ - uint32_t *tmp=0; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - /* Set the USART DMA transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - - /* Set the DMA error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; - - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pRxData: Pointer to data buffer - * @param Size: Amount of data to be received - * @retval HAL status - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - */ -HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) -{ - uint32_t *tmp=0; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pRxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->pTxBuffPtr = pRxData; - husart->TxXferSize = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; - - /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size); - - /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, - this mode isn't a simplex receive mode but a full-duplex receive one */ - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); - - /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer - when using the USART in circular mode */ - __HAL_USART_CLEAR_OREFLAG(husart); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer - * @param Size: Amount of data to be received - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - uint32_t *tmp=0; - - if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX_RX; - - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - - /* Set the USART DMA Tx transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - - /* Set the USART DMA Tx transfer error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; - - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; - - /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size); - - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); - - /* Clear the Overrun flag: mandatory for the second transfer in circular mode */ - __HAL_USART_CLEAR_OREFLAG(husart); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the DMA Transfer. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) -{ - /* Process Locked */ - __HAL_LOCK(husart); - - /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_DMAT)); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) -{ - /* Process Locked */ - __HAL_LOCK(husart); - - /* Enable the USART DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() - */ - - /* Abort the USART DMA Tx channel */ - if(husart->hdmatx != NULL) - { - HAL_DMA_Abort(husart->hdmatx); - } - /* Abort the USART DMA Rx channel */ - if(husart->hdmarx != NULL) - { - HAL_DMA_Abort(husart->hdmarx); - } - - /* Disable the USART Tx/Rx DMA requests */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - husart->State = HAL_USART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief This function handles USART interrupt request. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE); - /* USART parity error interrupt occurred -----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_USART_CLEAR_PEFLAG(husart); - husart->ErrorCode |= HAL_USART_ERROR_PE; - } - - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); - /* USART frame error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_USART_CLEAR_FEFLAG(husart); - husart->ErrorCode |= HAL_USART_ERROR_FE; - } - - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); - /* USART noise error interrupt occurred ------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_USART_CLEAR_NEFLAG(husart); - husart->ErrorCode |= HAL_USART_ERROR_NE; - } - - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); - /* USART Over-Run interrupt occurred ---------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_USART_CLEAR_OREFLAG(husart); - husart->ErrorCode |= HAL_USART_ERROR_ORE; - } - - if(husart->ErrorCode != HAL_USART_ERROR_NONE) - { - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_ErrorCallback(husart); - } - - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE); - /* USART in mode Receiver --------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - USART_Receive_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } - } - - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE); - /* USART in mode Transmitter -----------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - USART_Transmit_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } - } - - tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC); - tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC); - /* USART in mode Transmitter (transmission end) -----------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - USART_EndTransmit_IT(husart); - } - -} - - -/** - * @brief Tx Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ - __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ - __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_TxRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief USART error callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ - __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_USART_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief USART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - USART communication - process, return Peripheral Errors occurred during communication process - (+) HAL_USART_GetState() API can be helpful to check in run-time the state - of the USART peripheral. - (+) HAL_USART_GetError() check in run-time errors that could be occurred during - communication. -@endverbatim - * @{ - */ - -/** - * @brief Returns the USART state. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL state - */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) -{ - return husart->State; -} - -/** - * @brief Return the USART error code - * @param husart : pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART. - * @retval USART Error Code - */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) -{ - return husart->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions USART Private Functions - * @brief USART Private functions - * @{ - */ -/** - * @brief DMA USART transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - husart->TxXferCount = 0; - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Wait for USART TC Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - husart->State = HAL_USART_STATE_TIMEOUT; - HAL_USART_ErrorCallback(husart); - } - else - { - /* No Timeout */ - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - husart->State= HAL_USART_STATE_READY; - HAL_USART_TxCpltCallback(husart); - } - } - } - /* DMA Circular mode */ - else - { - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - HAL_USART_TxCpltCallback(husart); - } - } -} - -/** - * @brief DMA USART transmit process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_USART_TxHalfCpltCallback(husart); -} - -/** - * @brief DMA USART receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - husart->RxXferCount = 0; - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - /* Disable the DMA transfer for the receiver requests by setting the DMAR bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - HAL_USART_RxCpltCallback(husart); - } - /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ - else - { - /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - HAL_USART_TxRxCpltCallback(husart); - } - husart->State= HAL_USART_STATE_READY; - } - /* DMA circular mode */ - else - { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - HAL_USART_RxCpltCallback(husart); - } - /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ - else - { - HAL_USART_TxRxCpltCallback(husart); - } - } -} - -/** - * @brief DMA USART receive process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - HAL_USART_RxHalfCpltCallback(husart); -} - -/** - * @brief DMA USART communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void USART_DMAError(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - husart->RxXferCount = 0; - husart->TxXferCount = 0; - husart->ErrorCode |= HAL_USART_ERROR_DMA; - husart->State= HAL_USART_STATE_READY; - - HAL_USART_ErrorCallback(husart); -} - -/** - * @brief This function handles USART Communication Timeout. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @param Flag: specifies the USART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_USART_GET_FLAG(husart, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_USART_GET_FLAG(husart, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - * @note The USART errors are not managed to avoid the overrun error. - */ -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) -{ - uint16_t* tmp=0; - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - tmp = (uint16_t*) husart->pTxBuffPtr; - WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); - if(husart->Init.Parity == USART_PARITY_NONE) - { - husart->pTxBuffPtr += 2; - } - else - { - husart->pTxBuffPtr += 1; - } - } - else - { - WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF)); - } - - if(--husart->TxXferCount == 0) - { - /* Disable the USART Transmit data register empty Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - - /* Enable the USART Transmit Complete Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Wraps up transmission in non blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) -{ - /* Disable the USART Transmit Complete Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TC); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxCpltCallback(husart); - - return HAL_OK; -} - - -/** - * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) -{ - uint16_t* tmp=0; - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - tmp = (uint16_t*) husart->pRxBuffPtr; - if(husart->Init.Parity == USART_PARITY_NONE) - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - husart->pRxBuffPtr += 2; - } - else - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - husart->pRxBuffPtr += 1; - } - if(--husart->RxXferCount != 0x00) - { - /* Send dummy byte in order to generate the clock for the slave to send the next data */ - WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); - } - } - else - { - if(husart->Init.Parity == USART_PARITY_NONE) - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); - } - - if(--husart->RxXferCount != 0x00) - { - /* Send dummy byte in order to generate the clock for the slave to send the next data */ - WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF)); - } - } - - if(husart->RxXferCount == 0) - { - /* Disable the USART RXNE Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - - /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State = HAL_USART_STATE_READY; - HAL_USART_RxCpltCallback(husart); - - return HAL_OK; - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) -{ - uint16_t* tmp=0; - - if(husart->State == HAL_USART_STATE_BUSY_TX_RX) - { - if(husart->TxXferCount != 0x00) - { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) - { - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - tmp = (uint16_t*) husart->pTxBuffPtr; - WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); - if(husart->Init.Parity == USART_PARITY_NONE) - { - husart->pTxBuffPtr += 2; - } - else - { - husart->pTxBuffPtr += 1; - } - } - else - { - WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF)); - } - husart->TxXferCount--; - - /* Check the latest data transmitted */ - if(husart->TxXferCount == 0) - { - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - } - } - } - - if(husart->RxXferCount != 0x00) - { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) - { - if(husart->Init.WordLength == USART_WORDLENGTH_9B) - { - tmp = (uint16_t*) husart->pRxBuffPtr; - if(husart->Init.Parity == USART_PARITY_NONE) - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - husart->pRxBuffPtr += 2; - } - else - { - *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - husart->pRxBuffPtr += 1; - } - } - else - { - if(husart->Init.Parity == USART_PARITY_NONE) - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); - } - } - husart->RxXferCount--; - } - } - - /* Check the latest data received */ - if(husart->RxXferCount == 0) - { - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - - /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxRxCpltCallback(husart); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configures the USART peripheral. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -static void USART_SetConfig(USART_HandleTypeDef *husart) -{ - /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); - assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); - assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); - assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); - assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); - assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); - assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); - assert_param(IS_USART_PARITY(husart->Init.Parity)); - assert_param(IS_USART_MODE(husart->Init.Mode)); - - /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the - receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */ - CLEAR_BIT(husart->Instance->CR1, ((uint32_t)(USART_CR1_TE | USART_CR1_RE))); - - /*---------------------------- USART CR2 Configuration ---------------------*/ - /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/ - /* Set CPOL bit according to husart->Init.CLKPolarity value */ - /* Set CPHA bit according to husart->Init.CLKPhase value */ - /* Set LBCL bit according to husart->Init.CLKLastBit value */ - /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */ - /* Write to USART CR2 */ - MODIFY_REG(husart->Instance->CR2, - (uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP), - ((uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits))); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to husart->Init.WordLength value - Set PCE and PS bits according to husart->Init.Parity value - Set TE and RE bits according to husart->Init.Mode value */ - MODIFY_REG(husart->Instance->CR1, - (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), - (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Clear CTSE and RTSE bits */ - CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)); - - /*-------------------------- USART BRR Configuration -----------------------*/ - if((husart->Instance == USART1)) - { - husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate); - } - else - { - husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate); - } -} - -/** - * @} - */ - -#endif /* HAL_USART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c deleted file mode 100644 index a0dffd772..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c +++ /dev/null @@ -1,444 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_wwdg.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief WWDG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State functions - @verbatim - ============================================================================== - ##### WWDG specific features ##### - ============================================================================== - [..] - Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (downcounter) - before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). - - (+) An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This - implies that the counter must be refreshed in a limited window. - (+) Once enabled the WWDG cannot be disabled except by a system reset. - (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - reset occurs. - (+) The WWDG counter input clock is derived from the APB clock divided - by a programmable prescaler. - (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) - (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock - (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (mS) = 1000 * (Counter – Window) / WWDG clock - (++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock - - (+) Min-max timeout value at @32MHz (PCLK1): ~128us / ~65.6ms. - - - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of function pointer HAL_WWDG_WakeupCallback - Once enabled, EWI interrupt cannot be disabled except by a system reset. - (+) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the refresh window value already programmed. - - *** WWDG HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in WWDG HAL driver. - - (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags - (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup WWDG WWDG - * @brief WWDG HAL module driver. - * @{ - */ - -#ifdef HAL_WWDG_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Functions WWDG Exported Functions - * @{ - */ - -/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize the WWDG according to the specified parameters - in the WWDG_InitTypeDef and create the associated handle - (+) DeInitialize the WWDG peripheral - (+) Initialize the WWDG MSP - (+) DeInitialize the WWDG MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the WWDG according to the specified - * parameters in the WWDG_InitTypeDef and creates the associated handle. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) -{ - /* Check the WWDG handle allocation */ - if(hwwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); - assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); - assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); - assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); - - if(hwwdg->State == HAL_WWDG_STATE_RESET) - { - /* Init the low level hardware */ - HAL_WWDG_MspInit(hwwdg); - } - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Set WWDG Prescaler and Window */ - MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); - - /* Set WWDG Counter */ - MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the WWDG peripheral. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Check the parameters */ - assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_WWDG_MspDeInit(hwwdg); - - /* Reset WWDG Control register */ - hwwdg->Instance->CR = (uint32_t)0x0000007F; - - /* Reset WWDG Configuration register */ - hwwdg->Instance->CFR = (uint32_t)0x0000007F; - - /* Reset WWDG Status register */ - hwwdg->Instance->SR = 0; - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the WWDG. - (+) Refresh the WWDG. - (+) Handle WWDG interrupt request. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the WWDG with interrupt enabled. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the Early Wakeup Interrupt */ - __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI); - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Refreshes the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @param Counter: value of counter to put in WWDG counter - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - - /* Write to WWDG CR the WWDG Counter value to refresh with */ - MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles WWDG interrupt request. - * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations - * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro. - * When the downcounter reaches the value 0x40, and EWI interrupt is - * generated and the corresponding Interrupt Service Routine (ISR) can - * be used to trigger specific actions (such as communications or data - * logging), before resetting the device. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) -{ - /* WWDG Early Wakeup Interrupt occurred */ - if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) - { - /* Early Wakeup callback */ - HAL_WWDG_WakeupCallback(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Clear the WWDG Data Ready flag */ - __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF); - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - } -} - -/** - * @brief Early Wakeup WWDG callback. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_WakeupCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the WWDG state. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL state - */ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) -{ - return hwwdg->State; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_WWDG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c deleted file mode 100644 index b2b03f1f1..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c +++ /dev/null @@ -1,359 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_ll_fsmc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief FSMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================= - ##### FSMC peripheral features ##### - ============================================================================= - [..] The Flexible static memory controller (FSMC) includes following memory controllers: - (+) The NOR/PSRAM memory controller - - [..] The FSMC functional block makes the interface with synchronous and asynchronous static - memories and SDRAM memories. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol. - (+) to meet the access time requirements of the external memory devices. - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FSMC performs - only one access at a time to an external device. - The main features of the FSMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM). - (++) NOR Flash memory. - (++) PSRAM (4 memory banks). - (+) Independent Chip Select control for each memory bank. - (+) Independent configuration for each memory bank. - - ============================================================================= - ##### How to use NORSRAM device driver ##### - ============================================================================= - - [..] - This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order - to run the NORSRAM external devices. - - (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() - (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() - (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() - (+) FSMC NORSRAM bank extended timing configuration using the function - FSMC_NORSRAM_Extended_Timing_Init() - (+) FSMC NORSRAM bank enable/disable write operation using the functions - FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup FSMC_LL FSMC_LL - * @brief FSMC driver modules - * @{ - */ - -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FSMC_Exported_Functions FSMC Exported Functions - * @{ - */ - -/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FSMC NORSRAM interface - (+) De-initialize the FSMC NORSRAM interface - (+) Configure the FSMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the FSMC_NORSRAM device according to the specified - * control parameters in the FSMC_NORSRAM_InitTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Init: Pointer to NORSRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef* Init) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); - assert_param(IS_FSMC_MUX(Init->DataAddressMux)); - assert_param(IS_FSMC_MEMORY(Init->MemoryType)); - assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); - assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); - assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); - assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); - - /* Set NORSRAM device control parameters */ - tmpr = (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WrapMode |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst - ); - - if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) - { - tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; - } - - Device->BTCR[Init->NSBank] = tmpr; - - return HAL_OK; -} - - -/** - * @brief DeInitialize the FSMC_NORSRAM peripheral - * @param Device: Pointer to NORSRAM device instance - * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); - - /* Disable the FSMC_NORSRAM device */ - __FSMC_NORSRAM_DISABLE(Device, Bank); - - /* De-initialize the FSMC_NORSRAM device */ - /* FSMC_NORSRAM_BANK1 */ - if(Bank == FSMC_BANK1_NORSRAM1) - { - Device->BTCR[Bank] = 0x000030DB; - } - /* FSMC_BANK1_NORSRAM2, FSMC_BANK1_NORSRAM3 or FSMC_BANK1_NORSRAM4 */ - else - { - Device->BTCR[Bank] = 0x000030D2; - } - - Device->BTCR[Bank + 1] = 0x0FFFFFFF; - ExDevice->BWTR[Bank] = 0x0FFFFFFF; - - return HAL_OK; -} - - -/** - * @brief Initialize the FSMC_NORSRAM Timing according to the specified - * parameters in the FSMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0; - - /* Check the parameters */ - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); - - /* Set FSMC_NORSRAM device timing parameters */ - tmpr = (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) |\ - ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) |\ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) |\ - (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) |\ - (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BTRx_DATLAT)) |\ - (Timing->AccessMode) - ); - - Device->BTCR[Bank + 1] = tmpr; - - return HAL_OK; -} - -/** - * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified - * parameters in the FSMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number - * @param ExtendedMode: FSMC Extended Mode - * This parameter can be one of the following values: - * @arg FSMC_EXTENDED_MODE_DISABLE - * @arg FSMC_EXTENDED_MODE_ENABLE - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) -{ - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) - { - /* Check the parameters */ - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); - - Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) |\ - ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) |\ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)) |\ - (Timing->AccessMode)); - } - else - { - Device->BWTR[Bank] = 0x0FFFFFFF; - } - - return HAL_OK; -} - - -/** - * @} - */ - - -/** @defgroup HAL_FSMC_NORSRAM_Group2 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### FSMC_NORSRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FSMC NORSRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FSMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank) -{ - /* Enable write operation */ - Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FSMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank) -{ - /* Disable write operation */ - Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#endif /* HAL_FSMC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c b/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c deleted file mode 100644 index d3305e557..000000000 --- a/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c +++ /dev/null @@ -1,519 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_ll_sdmmc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief SDMMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the SDMMC peripheral: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### SDMMC peripheral features ##### - ============================================================================== - [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 - peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA - devices. - - [..] The MultiMedia Card system specifications are available through the MultiMedia Card - Association website at www.mmca.org, published by the MMCA technical committee. - SD memory card and SD I/O card system specifications are available through the SD card - Association website at www.sdcard.org. - CE-ATA system specifications are available through the CE-ATA work group web site at - www.ce-ata.org. - - [..] The SDIO features include the following: - (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support - for three different databus modes: 1-bit (default), 4-bit and 8-bit - (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) - (+) Full compliance with SD Memory Card Specifications Version 2.0 - (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two - different data bus modes: 1-bit (default) and 4-bit - (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol - Rev1.1) - (+) Data transfer up to 48 MHz for the 8 bit mode - (+) Data and command output enable signals to control external bidirectional drivers. - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a considered as a driver of service for external devices drivers - that interfaces with the SDIO peripheral. - According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs - is used in the device's driver to perform SDIO operations and functionalities. - - This driver is almost transparent for the final user, it is only used to implement other - functionalities of the external device. - - [..] - (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from the PLL. Before start working with SDIO peripheral make sure that the - PLL is well configured. - The SDIO peripheral uses two clock signals: - (++) SDIO adapter clock (SDIOCLK = 48 MHz) - (++) APB2 bus clock (PCLK2) - - -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: - Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - - (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO - peripheral. - - (+) Enable the Power ON State using the SDIO_PowerState_ON(hsdio) - function and disable it using the function SDIO_PowerState_OFF(hsdio). - - (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. - - (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) - and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. - - (+) When using the DMA mode - (++) Configure the DMA in the MSP layer of the external device - (++) Active the needed channel Request - (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro - __SDIO_DMA_DISABLE(). - - (+) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDIO_SendCommand(), - SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has - to fill the command structure (pointer to SDIO_CmdInitTypeDef) according - to the selected command to be sent. - The parameters that should be filled are: - (++) Command Argument - (++) Command Index - (++) Command Response type - (++) Command Wait - (++) CPSM Status (Enable or Disable). - - -@@- To check if the command is well received, read the SDIO_CMDRESP - register using the SDIO_GetCommandResponse(). - The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - SDIO_GetResponse() function. - - (+) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. - - *** Read Operations *** - ======================= - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be from card (To SDIO) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to receive the data from the card - according to selected transfer mode. - - (#) Send the selected Read command. - - (#) Use the SDIO flags/interrupts to check the transfer status. - - *** Write Operations *** - ======================== - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be to card (To CARD) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to send the data to the card according to - selected transfer mode. - - (#) Send the selected Write command. - - (#) Use the SDIO flags/interrupts to check the transfer status. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup SDMMC_LL SDMMC_LL - * @brief Low layer module for SD and MMC driver - * @{ - */ - -#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions - * @{ - */ - -/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO according to the specified - * parameters in the SDIO_InitTypeDef and create the associated handle. - * @param SDIOx: Pointer to SDIO register base - * @param Init: SDIO initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); - assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); - assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); - - /* Set SDIO configuration parameters */ - tmpreg |= (Init.ClockEdge |\ - Init.ClockBypass |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ - Init.ClockDiv - ); - - /* Write to SDIO CLKCR */ - MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); - - return HAL_OK; -} - - - -/** - * @} - */ - -/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### I/O operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SDIO data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Read data (word) from Rx FIFO in blocking mode (polling) - * @param SDIOx: Pointer to SDIO register base - * @retval HAL status - */ -uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) -{ - /* Read data from Rx FIFO */ - return (SDIOx->FIFO); -} - -/** - * @brief Write data (word) to Tx FIFO in blocking mode (polling) - * @param SDIOx: Pointer to SDIO register base - * @param pWriteData: pointer to data to write - * @retval HAL status - */ -HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) -{ - /* Write data to FIFO */ - SDIOx->FIFO = *pWriteData; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SDIO data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Set SDIO Power state to ON. - * @param SDIOx: Pointer to SDIO register base - * @retval HAL status - */ -HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) -{ - /* Set power state to ON */ - SDIOx->POWER = SDIO_POWER_PWRCTRL; - - return HAL_OK; -} - -/** - * @brief Set SDIO Power state to OFF. - * @param SDIOx: Pointer to SDIO register base - * @retval HAL status - */ -HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) -{ - /* Set power state to OFF */ - SDIOx->POWER = (uint32_t)0x00000000; - - return HAL_OK; -} - -/** - * @brief Get SDIO Power state. - * @param SDIOx: Pointer to SDIO register base - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) -{ - return (SDIOx->POWER & SDIO_POWER_PWRCTRL); -} - -/** - * @brief Configure the SDIO command path according to the specified parameters in - * SDIO_CmdInitTypeDef structure and send the command - * @param SDIOx: Pointer to SDIO register base - * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains - * the configuration information for the SDIO command - * @retval HAL status - */ -HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM)); - - /* Set the SDIO Argument value */ - SDIOx->ARG = SDIO_CmdInitStruct->Argument; - - /* Set SDIO command parameters */ - tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\ - SDIO_CmdInitStruct->Response |\ - SDIO_CmdInitStruct->WaitForInterrupt |\ - SDIO_CmdInitStruct->CPSM); - - /* Write to SDIO CMD register */ - MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); - - return HAL_OK; -} - -/** - * @brief Return the command index of last command for which response received - * @param SDIOx: Pointer to SDIO register base - * @retval Command index of the last command response received - */ -uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) -{ - return (uint8_t)(SDIOx->RESPCMD); -} - - -/** - * @brief Return the response received from the card for the last command - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - /* Get the response */ - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Configure the SDIO data path according to the specified - * parameters in the SDIO_DataInitTypeDef. - * @param SDIOx: Pointer to SDIO register base - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO command. - * @retval HAL status - */ -HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM)); - - /* Set the SDIO Data TimeOut value */ - SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut; - - /* Set the SDIO DataLength value */ - SDIOx->DLEN = SDIO_DataInitStruct->DataLength; - - /* Set the SDIO data configuration parameters */ - tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\ - SDIO_DataInitStruct->TransferDir |\ - SDIO_DataInitStruct->TransferMode |\ - SDIO_DataInitStruct->DPSM); - - /* Write to SDIO DCTRL */ - MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); - - return HAL_OK; - -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param SDIOx: Pointer to SDIO register base - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) -{ - return (SDIOx->DCOUNT); -} - -/** - * @brief Get the FIFO data - * @param SDIOx: Pointer to SDIO register base - * @retval Data received - */ -uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) -{ - return (SDIOx->FIFO); -} - - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode; - - return HAL_OK; -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/clock.c b/cpu/arm/stm32l152/clock.c index 14f474219..a38248de7 100644 --- a/cpu/arm/stm32l152/clock.c +++ b/cpu/arm/stm32l152/clock.c @@ -28,29 +28,25 @@ * * */ - - +/*---------------------------------------------------------------------------*/ #include #include "contiki.h" #include "platform-conf.h" #include "contiki-conf.h" #include "dev/leds.h" - #include "stm32l1xx.h" - #include "stm32l1xx_hal_rcc.h" #include "stm32l1xx_hal_cortex.h" #include "stm32l1xx_hal.h" - +#include "st-lib.h" /*---------------------------------------------------------------------------*/ #define RELOAD_VALUE ((F_CPU/CLOCK_CONF_SECOND) - 1) - +/*---------------------------------------------------------------------------*/ static volatile unsigned long seconds = 0; static volatile clock_time_t ticks; -void SysTick_Handler(void); +void st_lib_sys_tick_handler(void); /*---------------------------------------------------------------------------*/ - -void SysTick_Handler(void) +void st_lib_sys_tick_handler(void) { ticks++; if((ticks % CLOCK_SECOND) == 0) { @@ -58,35 +54,34 @@ void SysTick_Handler(void) energest_flush(); } HAL_IncTick(); -// HAL_SYSTICK_IRQHandler(); + if(etimer_pending()) { etimer_request_poll(); } - } - +/*---------------------------------------------------------------------------*/ void clock_init(void) { ticks = 0; - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - HAL_SYSTICK_Config(RELOAD_VALUE); - + st_lib_hal_systick_clk_source_config(SYSTICK_CLKSOURCE_HCLK); + st_lib_hal_systick_config(RELOAD_VALUE); } +/*---------------------------------------------------------------------------*/ unsigned long clock_seconds(void) { return seconds; } - +/*---------------------------------------------------------------------------*/ void clock_set_seconds(unsigned long sec) { seconds = sec; } - +/*---------------------------------------------------------------------------*/ clock_time_t clock_time(void) { return ticks; } - +/*---------------------------------------------------------------------------*/ void clock_delay(unsigned int i) { for(; i > 0; i--) { @@ -96,7 +91,7 @@ void clock_delay(unsigned int i) } } } - +/*---------------------------------------------------------------------------*/ /** * Wait for a multiple of clock ticks (7.8 ms at 128 Hz). */ @@ -106,4 +101,4 @@ void clock_wait(clock_time_t i) start = clock_time(); while(clock_time() - start < (clock_time_t)i); } - +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/console.c b/cpu/arm/stm32l152/console.c index 3644af8ec..f3b2896f4 100644 --- a/cpu/arm/stm32l152/console.c +++ b/cpu/arm/stm32l152/console.c @@ -34,131 +34,115 @@ * ****************************************************************************** */ - +/*---------------------------------------------------------------------------*/ #include #include -//#include "console.h" +#include "console.h" #include "stm32l1xx.h" #include "stm32l1xx_hal_dma.h" #include "stm32l1xx_hal_uart.h" - - -extern UART_HandleTypeDef UartHandle; - -/** @addtogroup STM32F4xx_HAL_Examples - * @{ - */ - -/** @addtogroup X_NUCLEO_IKC01A1_Demonstration - * @{ - */ - -/** @defgroup X_NUCLEO_IKC01A1_Demonstration_Console_Utilities - * @{ - */ - - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +extern st_lib_uart_handle_typedef st_lib_uart_handle; +/*---------------------------------------------------------------------------*/ /** - * @brief Initialises Nucleo UART port for user IO - * @param None + * @brief Initialises Nucleo UART port for user IO * @retval 0 */ -int consoleInit(void) +int console_init(void) { - UartHandle.Instance = USART2; + st_lib_uart_handle.Instance = USART2; - UartHandle.Init.BaudRate = 9600; - UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - UartHandle.Init.StopBits = UART_STOPBITS_1; - UartHandle.Init.Parity = UART_PARITY_NONE; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - UartHandle.Init.Mode = UART_MODE_TX_RX; + st_lib_uart_handle.Init.BaudRate = 115200; + st_lib_uart_handle.Init.WordLength = UART_WORDLENGTH_8B; + st_lib_uart_handle.Init.StopBits = UART_STOPBITS_1; + st_lib_uart_handle.Init.Parity = UART_PARITY_NONE; + st_lib_uart_handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + st_lib_uart_handle.Init.Mode = UART_MODE_TX_RX; - HAL_UART_Init(&UartHandle); + st_lib_hal_uart_init(&st_lib_uart_handle); - return 0; + return 0; } - - +/*---------------------------------------------------------------------------*/ /** @brief Sends a character to serial port * @param ch Character to send * @retval Character sent */ -int uartSendChar(int ch) +int uart_send_char(int ch) { - HAL_UART_Transmit(&UartHandle, (uint8_t *)&ch, 1, HAL_MAX_DELAY); - return ch; + st_lib_hal_uart_transmit(&st_lib_uart_handle, (uint8_t *)&ch, 1, HAL_MAX_DELAY); + return ch; } - +/*---------------------------------------------------------------------------*/ /** @brief Receives a character from serial port - * @param None * @retval Character received */ -int uartReceiveChar(void) +int uart_receive_char(void) { - uint8_t ch; - HAL_UART_Receive(&UartHandle, &ch, 1, HAL_MAX_DELAY); + uint8_t ch; + st_lib_hal_uart_receive(&st_lib_uart_handle, &ch, 1, HAL_MAX_DELAY); - /* Echo character back to console */ - HAL_UART_Transmit(&UartHandle, &ch, 1, HAL_MAX_DELAY); + /* Echo character back to console */ + st_lib_hal_uart_transmit(&st_lib_uart_handle, &ch, 1, HAL_MAX_DELAY); - /* And cope with Windows */ - if(ch == '\r'){ - uint8_t ret = '\n'; - HAL_UART_Transmit(&UartHandle, &ret, 1, HAL_MAX_DELAY); - } + /* And cope with Windows */ + if(ch == '\r'){ + uint8_t ret = '\n'; + st_lib_hal_uart_transmit(&st_lib_uart_handle, &ret, 1, HAL_MAX_DELAY); + } - return ch; + return ch; } - - +/*---------------------------------------------------------------------------*/ #if defined (__IAR_SYSTEMS_ICC__) size_t __write(int Handle, const unsigned char * Buf, size_t Bufsize); size_t __read(int Handle, unsigned char *Buf, size_t Bufsize); /** @brief IAR specific low level standard input - * @param Handle IAR internal handle - * @param Buf Buffer where to store characters read from stdin - * @param Bufsize Number of characters to read + * @param handle IAR internal handle + * @param buf Buffer where to store characters read from stdin + * @param bufsize Number of characters to read * @retval Number of characters read */ -size_t __read(int Handle, unsigned char *Buf, size_t Bufsize) +size_t __read(int handle, unsigned char *buf, size_t bufsize) { - int i; + int i; - if (Handle != 0){ - return -1; - } + if (handle != 0){ + return -1; + } - for(i=0; i #include +/*---------------------------------------------------------------------------*/ int _lseek (int file, int ptr, int dir) { return 0; } +/*---------------------------------------------------------------------------*/ int _close (int file) { return -1; } - +/*---------------------------------------------------------------------------*/ void _exit (int n) { /* FIXME: return code is thrown away. */ while(1); } - - +/*---------------------------------------------------------------------------*/ int _kill (int n, int m) { return -1; } +/*---------------------------------------------------------------------------*/ int _fstat(int file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } +/*---------------------------------------------------------------------------*/ int _isatty (int fd) { return 1; fd = fd; } - +/*---------------------------------------------------------------------------*/ int _getpid (int n) { return -1; } -int _open (const char * path, - int flags, - ...) +/*---------------------------------------------------------------------------*/ +int _open (const char * path, int flags, ...) { return -1; } -#if 0 -int _fflush_r(struct _reent *r, FILE *f) -{ - return 0; -} -#endif +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/cube_hal.h b/cpu/arm/stm32l152/cube_hal.h deleted file mode 100644 index 118024e2c..000000000 --- a/cpu/arm/stm32l152/cube_hal.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - ****************************************************************************** - * @file Projects/Multi/Examples/DataLog/Inc/cube_hal.h - * @author CL - * @version V1.0.0 - * @date 03-November-2014 - * @brief Header for cube_hal_f4.c and cube_hal_l0.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef _CUBE_HAL_H_ -#define _CUBE_HAL_H_ - -/* Includes ------------------------------------------------------------------*/ -//#ifdef USE_STM32F4XX_NUCLEO -// #include "stm32f4xx_hal.h" -// #include "stm32f4xx_nucleo.h" -// #include "stm32f4xx_hal_conf.h" -// #include "stm32f4xx_hal_def.h" -//#endif - -//#ifdef USE_STM32L0XX_NUCLEO - - #include "stm32l1xx_hal.h" - #include "stm32l1xx_nucleo.h" - #include "stm32l1xx_hal_conf.h" - #include "stm32l1xx_hal_def.h" -//#endif - -void SystemClock_Config(void); -uint32_t Get_DMA_Flag_Status(DMA_HandleTypeDef *handle_dma); -uint32_t Get_DMA_Counter(DMA_HandleTypeDef *handle_dma); -void Config_DMA_Handler(DMA_HandleTypeDef *handle_dma); - -#endif //_CUBE_HAL_H_ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/e_stdio_intonly_thumb2.a b/cpu/arm/stm32l152/lib/e_stdio_intonly_thumb2.a similarity index 100% rename from cpu/arm/stm32l152/e_stdio_intonly_thumb2.a rename to cpu/arm/stm32l152/lib/e_stdio_intonly_thumb2.a diff --git a/cpu/arm/stm32l152/e_stdio_thumb2.a b/cpu/arm/stm32l152/lib/e_stdio_thumb2.a similarity index 100% rename from cpu/arm/stm32l152/e_stdio_thumb2.a rename to cpu/arm/stm32l152/lib/e_stdio_thumb2.a diff --git a/cpu/arm/stm32l152/smallprintf_thumb2.a b/cpu/arm/stm32l152/lib/smallprintf_thumb2.a similarity index 100% rename from cpu/arm/stm32l152/smallprintf_thumb2.a rename to cpu/arm/stm32l152/lib/smallprintf_thumb2.a diff --git a/cpu/arm/stm32l152/mtarch.h b/cpu/arm/stm32l152/mtarch.h index 640035036..b8792fb7e 100644 --- a/cpu/arm/stm32l152/mtarch.h +++ b/cpu/arm/stm32l152/mtarch.h @@ -1,13 +1,47 @@ +/** + ****************************************************************************** + * @file console.c + * @author AST + * @version V1.0.0 + * @date 26-Aug-2014 + * @brief This file provides implementation of standard input/output + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ /* * Implementation of multithreading in ARM Cortex-M3. To be done. */ - - #ifndef __MTARCH_H__ #define __MTARCH_H__ - +/*---------------------------------------------------------------------------*/ struct mtarch_thread { short mt_thread; }; - -#endif /* __MTARCH_H__ */ \ No newline at end of file +/*---------------------------------------------------------------------------*/ +#endif /* __MTARCH_H__ */ diff --git a/cpu/arm/stm32l152/regs.h b/cpu/arm/stm32l152/regs.h index 5c60f682a..6d570f31c 100644 --- a/cpu/arm/stm32l152/regs.h +++ b/cpu/arm/stm32l152/regs.h @@ -1,7 +1,37 @@ +/* +* Copyright (c) 2012, STMicroelectronics. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the Institute nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +* +*/ +/*---------------------------------------------------------------------------*/ #ifndef REGS_H_ #define REGS_H_ 1 - - +/*---------------------------------------------------------------------------*/ #define ReadRegister(a) a #define WriteRegister(a, b) a = b @@ -11540,5 +11570,6 @@ #define DATA_VENDOR_END (0xFFFFFFFFu) #define DATA_VENDOR_SIZE (DATA_VENDOR_END - DATA_VENDOR_BASE + 1) - +/*---------------------------------------------------------------------------*/ #endif /*REGS_H_*/ +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/rtimer-arch.c b/cpu/arm/stm32l152/rtimer-arch.c index 2a47efc87..33922703e 100644 --- a/cpu/arm/stm32l152/rtimer-arch.c +++ b/cpu/arm/stm32l152/rtimer-arch.c @@ -28,7 +28,7 @@ * * */ - +/*---------------------------------------------------------------------------*/ #include "contiki.h" #include "platform-conf.h" @@ -41,65 +41,64 @@ #include "stm32l1xx_hal_rcc.h" #include "stm32l1xx_hal_tim.h" #include "stm32l1xx_hal_cortex.h" - - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ volatile uint32_t rtimer_clock = 0uL; - -TIM_HandleTypeDef htim2; - -void TIM2_IRQHandler(void) +/*---------------------------------------------------------------------------*/ +st_lib_tim_handle_typedef htim2; +/*---------------------------------------------------------------------------*/ +void st_lib_tim2_irq_handler(void) { /* clear interrupt pending flag */ - __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); + st_lib_hal_tim_clear_it(&htim2, TIM_IT_UPDATE); rtimer_clock++; - } - - +/*---------------------------------------------------------------------------*/ void rtimer_arch_init(void) { - TIM_ClockConfigTypeDef sClockSourceConfig; - TIM_OC_InitTypeDef sConfigOC; + st_lib_tim_clock_config_typedef s_clock_source_config; + st_lib_tim_oc_init_typedef s_config_oc; - __TIM2_CLK_ENABLE(); + st_lib_tim2_clk_enable(); htim2.Instance = TIM2; htim2.Init.Prescaler = PRESCALER; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 1; - HAL_TIM_Base_Init(&htim2); - HAL_TIM_Base_Start_IT(&htim2); + st_lib_hal_tim_base_init(&htim2); + st_lib_hal_tim_base_start_it(&htim2); - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig); + s_clock_source_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + st_lib_hal_tim_config_clock_source(&htim2, &s_clock_source_config); - HAL_TIM_OC_Init(&htim2); + st_lib_hal_tim_oc_init(&htim2); - sConfigOC.OCMode = TIM_OCMODE_TIMING; - sConfigOC.Pulse = 0; - sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1); + s_config_oc.OCMode = TIM_OCMODE_TIMING; + s_config_oc.Pulse = 0; + s_config_oc.OCPolarity = TIM_OCPOLARITY_HIGH; + st_lib_hal_tim_oc_config_channel(&htim2, &s_config_oc, TIM_CHANNEL_1); - __HAL_TIM_CLEAR_FLAG(&htim2, TIM_FLAG_UPDATE); + st_lib_hal_tim_clear_flag(&htim2, TIM_FLAG_UPDATE); /* Enable TIM2 Update interrupt */ - __HAL_TIM_ENABLE_IT(&htim2, TIM_IT_UPDATE); + st_lib_hal_tim_enable_it(&htim2, TIM_IT_UPDATE); - __HAL_TIM_ENABLE(&htim2); + st_lib_hal_tim_enable(&htim2); - HAL_NVIC_SetPriority((IRQn_Type) TIM2_IRQn, 0, 0); - HAL_NVIC_EnableIRQ((IRQn_Type)(TIM2_IRQn)); + st_lib_hal_nvic_set_priority((st_lib_irq_n_type) TIM2_IRQn, 0, 0); + st_lib_hal_nvic_enable_irq((st_lib_irq_n_type)(TIM2_IRQn)); } - +/*---------------------------------------------------------------------------*/ rtimer_clock_t rtimer_arch_now(void) { return rtimer_clock; } - +/*---------------------------------------------------------------------------*/ void rtimer_arch_schedule(rtimer_clock_t t) { } +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/rtimer-arch.h b/cpu/arm/stm32l152/rtimer-arch.h index d0c40dbcd..1f8dd08fc 100644 --- a/cpu/arm/stm32l152/rtimer-arch.h +++ b/cpu/arm/stm32l152/rtimer-arch.h @@ -30,15 +30,16 @@ * This file is part of the Contiki OS * */ - +/*---------------------------------------------------------------------------*/ #ifndef __RTIMER_ARCH_H__ #define __RTIMER_ARCH_H__ - +/*---------------------------------------------------------------------------*/ #include "contiki-conf.h" #include "sys/clock.h" - +/*---------------------------------------------------------------------------*/ rtimer_clock_t rtimer_arch_now(void); void rtimer_arch_disable_irq(void); void rtimer_arch_enable_irq(void); - +/*---------------------------------------------------------------------------*/ #endif /* __RTIMER_ARCH_H__ */ +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/startup_stm32l152xe-IAR.s b/cpu/arm/stm32l152/startup_stm32l152xe-IAR.s deleted file mode 100644 index 3543a4546..000000000 --- a/cpu/arm/stm32l152/startup_stm32l152xe-IAR.s +++ /dev/null @@ -1,546 +0,0 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** -;* File Name : startup_stm32l152xe.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 5-September-2014 -;* Description : STM32L152XE Devices vector for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;*

© COPYRIGHT(c) 2014 STMicroelectronics

-;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp - DCD RTC_WKUP_IRQHandler ; RTC Wakeup - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line 0 - DCD EXTI1_IRQHandler ; EXTI Line 1 - DCD EXTI2_IRQHandler ; EXTI Line 2 - DCD EXTI3_IRQHandler ; EXTI Line 3 - DCD EXTI4_IRQHandler ; EXTI Line 4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD USB_HP_IRQHandler ; USB High Priority - DCD USB_LP_IRQHandler ; USB Low Priority - DCD DAC_IRQHandler ; DAC - DCD COMP_IRQHandler ; COMP through EXTI Line - DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 - DCD LCD_IRQHandler ; LCD - DCD TIM9_IRQHandler ; TIM9 - DCD TIM10_IRQHandler ; TIM10 - DCD TIM11_IRQHandler ; TIM11 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 - DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line - DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - - PUBWEAK TAMPER_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMPER_STAMP_IRQHandler - B TAMPER_STAMP_IRQHandler - - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - - PUBWEAK USB_HP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_HP_IRQHandler - B USB_HP_IRQHandler - - - PUBWEAK USB_LP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_LP_IRQHandler - B USB_LP_IRQHandler - - - PUBWEAK DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC_IRQHandler - B DAC_IRQHandler - - - PUBWEAK COMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_IRQHandler - B COMP_IRQHandler - - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - - PUBWEAK TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM9_IRQHandler - B TIM9_IRQHandler - - - PUBWEAK TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM10_IRQHandler - B TIM10_IRQHandler - - - PUBWEAK TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM11_IRQHandler - B TIM11_IRQHandler - - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - - PUBWEAK USB_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_FS_WKUP_IRQHandler - B USB_FS_WKUP_IRQHandler - - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK DMA2_Channel1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel1_IRQHandler - B DMA2_Channel1_IRQHandler - - - PUBWEAK DMA2_Channel2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel2_IRQHandler - B DMA2_Channel2_IRQHandler - - - PUBWEAK DMA2_Channel3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel3_IRQHandler - B DMA2_Channel3_IRQHandler - - - PUBWEAK DMA2_Channel4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel4_IRQHandler - B DMA2_Channel4_IRQHandler - - - PUBWEAK DMA2_Channel5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Channel5_IRQHandler - B DMA2_Channel5_IRQHandler - - - PUBWEAK COMP_ACQ_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -COMP_ACQ_IRQHandler - B COMP_ACQ_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/arm/stm32l152/startup_stm32l152xe.s b/cpu/arm/stm32l152/startup_stm32l152xe.s deleted file mode 100644 index a4e083e1d..000000000 --- a/cpu/arm/stm32l152/startup_stm32l152xe.s +++ /dev/null @@ -1,427 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l152xe.s - * @author MCD Application Team - * @version V2.1.0 - * @date 16-January-2015 - * @brief STM32L152XE Devices vector table for - * Atollic toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word LCD_IRQHandler - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word 0 - .word COMP_ACQ_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32L152XE devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - // .weak EXTI9_5_IRQHandler - // .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak LCD_IRQHandler - .thumb_set LCD_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak COMP_ACQ_IRQHandler - .thumb_set COMP_ACQ_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/cpu/arm/stm32l152/stm32l152xe_flash.icf b/cpu/arm/stm32l152/stm32l152xe_flash.icf deleted file mode 100644 index 3c134b79d..000000000 --- a/cpu/arm/stm32l152/stm32l152xe_flash.icf +++ /dev/null @@ -1,31 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20020000; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file diff --git a/cpu/arm/stm32l152/stm32l1xx.h b/cpu/arm/stm32l152/stm32l1xx.h deleted file mode 100644 index dcd0a4ccb..000000000 --- a/cpu/arm/stm32l152/stm32l1xx.h +++ /dev/null @@ -1,5169 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L1xx devices. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#include "stdint.h" - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L1XX_MD) - #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx - microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. - - */ - -#if !defined (STM32L1XX_MD) - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -//#define HSE_VALUE ((uint32_t)32000000) /*!< Value of the External oscillator in Hz*/ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - Timeout value - */ -#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ - -#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ - -/** - * @brief STM32L1xx Standard Peripheral Library version number - */ -#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32L1XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __MPU_PRESENT 1 /*!< STM32L provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*!< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ -} IRQn_Type; -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef int32_t vs32; -typedef int16_t vs16; -typedef int8_t vs8; - -typedef int32_t vsc32; /*!< Read Only */ -typedef int16_t vsc16; /*!< Read Only */ -typedef int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef uint32_t vu32; -typedef uint16_t vu16; -typedef uint8_t vu8; - -typedef uint32_t vuc32; /*!< Read Only */ -typedef uint16_t vuc16; /*!< Read Only */ -typedef uint8_t vuc8; /*!< Read Only */ - -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source - module. Using the 'Options for File' dialog you can simply change the - 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - 'Options for Target' dialog. -*/ - #define __RAM_FUNC FLASH_Status - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ - #define __RAM_FUNC __ramfunc FLASH_Status - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".data")))". -*/ - #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) - -#elif defined ( __TASKING__ ) -/* TASKING Compiler - ---------------- - RAM functions are defined using a specific toolchain pragma. This pragma is - defined in the stm32l1xx_flash_ramfunc.c -*/ - #define __RAM_FUNC FLASH_Status - -#endif - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t SMPR3; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t SQR4; - __IO uint32_t SQR5; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; - __IO uint32_t SR; -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; - __IO uint32_t APB1FZ; - __IO uint32_t APB2FZ; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t PECR; - __IO uint32_t PDKEYR; - __IO uint32_t PEKEYR; - __IO uint32_t PRGKEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t OBR; - __IO uint32_t WRPR; -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint32_t RDP; - __IO uint32_t USER; - __IO uint32_t WRP01; - __IO uint32_t WRP23; -} OB_TypeDef; - -/** - * @brief General Purpose IO - */ - -typedef struct -{ - __IO uint32_t MODER; - __IO uint16_t OTYPER; - uint16_t RESERVED0; - __IO uint32_t OSPEEDR; - __IO uint32_t PUPDR; - __IO uint16_t IDR; - uint16_t RESERVED1; - __IO uint16_t ODR; - uint16_t RESERVED2; - __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */ - __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */ - __IO uint32_t LCKR; - __IO uint32_t AFR[2]; -} GPIO_TypeDef; - -/** - * @brief SysTem Configuration - */ - -typedef struct -{ - __IO uint32_t MEMRMP; - __IO uint32_t PMC; - __IO uint32_t EXTICR[4]; -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - - -/** - * @brief LCD - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t FCR; - __IO uint32_t SR; - __IO uint32_t CLR; - uint32_t RESERVED; - __IO uint32_t RAM[16]; -} LCD_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t ICSCR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t AHBRSTR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t AHBLPENR; - __IO uint32_t APB2LPENR; - __IO uint32_t APB1LPENR; - __IO uint32_t CSR; -} RCC_TypeDef; - -/** - * @brief Routing Interface - */ - -typedef struct -{ - __IO uint32_t ICR; - __IO uint32_t ASCR1; - __IO uint32_t ASCR2; - __IO uint32_t HYSCR1; - __IO uint32_t HYSCR2; - __IO uint32_t HYSCR3; -} RI_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; - __IO uint32_t DR; - __IO uint32_t CR; - __IO uint32_t ISR; - __IO uint32_t PRER; - __IO uint32_t WUTR; - __IO uint32_t CALIBR; - __IO uint32_t ALRMAR; - __IO uint32_t ALRMBR; - __IO uint32_t WPR; - uint32_t RESERVED1; - uint32_t RESERVED2; - __IO uint32_t TSTR; - __IO uint32_t TSDR; - uint32_t RESERVED3; - uint32_t RESERVED4; - __IO uint32_t TAFCR; - uint32_t RESERVED5; - uint32_t RESERVED6; - uint32_t RESERVED7; - __IO uint32_t BKP0R; - __IO uint32_t BKP1R; - __IO uint32_t BKP2R; - __IO uint32_t BKP3R; - __IO uint32_t BKP4R; - __IO uint32_t BKP5R; - __IO uint32_t BKP6R; - __IO uint32_t BKP7R; - __IO uint32_t BKP8R; - __IO uint32_t BKP9R; - __IO uint32_t BKP10R; - __IO uint32_t BKP11R; - __IO uint32_t BKP12R; - __IO uint32_t BKP13R; - __IO uint32_t BKP14R; - __IO uint32_t BKP15R; - __IO uint32_t BKP16R; - __IO uint32_t BKP17R; - __IO uint32_t BKP18R; - __IO uint32_t BKP19R; -} RTC_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - uint32_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - uint32_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; - __IO uint16_t OR; - uint16_t RESERVED20; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define COMP_BASE (APB1PERIPH_BASE + 0x7C00) -#define RI_BASE (APB1PERIPH_BASE + 0x7C04) - -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define TIM9_BASE (APB2PERIPH_BASE + 0x0800) -#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) -#define TIM11_BASE (APB2PERIPH_BASE + 0x1000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC_BASE (APB2PERIPH_BASE + 0x2700) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) -#define RCC_BASE (AHBPERIPH_BASE + 0x3800) - - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ -#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ - -#define DMA1_BASE (AHBPERIPH_BASE + 0x6000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) - - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define COMP ((COMP_TypeDef *) COMP_BASE) -#define RI ((RI_TypeDef *) RI_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) - -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) - -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) - -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ -#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ -#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ -#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ -#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ -#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ - -#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ -#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ -#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ -#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ -#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ -#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ -#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ -#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ -#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR3 register *******************/ -#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ -#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ -#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ -#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ -#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ -#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ -#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ -#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ -#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ -#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ -#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR4 register *******************/ -#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR5 register *******************/ -#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ - - -/******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ -#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ - -/******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/******************************************************************************/ -/* */ -/* Analog Comparators (COMP) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for COMP_CSR register ********************/ -#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ -#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ -#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ -#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ - -#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ -#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ - -#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ -#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ - -#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ -#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ - -#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ -#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ -#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter (DAC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*! #include - +/*---------------------------------------------------------------------------*/ /* Variables */ extern int errno; register char * stack_ptr asm("sp"); - +/*---------------------------------------------------------------------------*/ /* Functions */ +/*---------------------------------------------------------------------------*/ /** _sbrk Increase program data space. Malloc and related functions depend on this **/ caddr_t _sbrk(int incr) { - extern char end asm("end"); - static char *heap_end; - char *prev_heap_end; + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end; - if (heap_end == 0) - heap_end = &end; + if (heap_end == 0) { + heap_end = &end; + } - prev_heap_end = heap_end; - if (heap_end + incr > stack_ptr) - { - errno = ENOMEM; - return (caddr_t) -1; - } + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) { + errno = ENOMEM; + return (caddr_t) -1; + } - heap_end += incr; + heap_end += incr; - return (caddr_t) prev_heap_end; + return (caddr_t) prev_heap_end; } +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/uart.c b/cpu/arm/stm32l152/uart.c index 9813909d6..74c577764 100644 --- a/cpu/arm/stm32l152/uart.c +++ b/cpu/arm/stm32l152/uart.c @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file uart.c +* @file cpu/arm/stm32l152/uart.c * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,28 +34,26 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/*---------------------------------------------------------------------------*/ #include "console.h" #include - - +/*---------------------------------------------------------------------------*/ size_t _write(int handle, const unsigned char *buffer, size_t size) { - int DataIdx; + int data_idx; - for (DataIdx = 0; DataIdx < size; DataIdx++) - { - __io_putchar( *buffer++ ); - } - return size; + for (data_idx = 0; data_idx < size; data_idx++) { + __io_putchar( *buffer++ ); + } + return size; } - +/*---------------------------------------------------------------------------*/ size_t _read(int handle, unsigned char *buffer, size_t size) { - /* scanf calls _read() with len=1024, so eat one character at time */ - *buffer = __io_getchar(); - return 1; + /* scanf calls _read() with len=1024, so eat one character at time */ + *buffer = __io_getchar(); + return 1; } +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/watchdog.c b/cpu/arm/stm32l152/watchdog.c index 8d8774140..b5efb2663 100644 --- a/cpu/arm/stm32l152/watchdog.c +++ b/cpu/arm/stm32l152/watchdog.c @@ -29,22 +29,10 @@ * * This file is part of the Contiki OS * - * $Id: watchdog.c,v 1.1 2010/10/25 09:03:39 salvopitru Exp $ */ /*---------------------------------------------------------------------------*/ -/** -* \file -* Watchdog -* \author -* Salvatore Pitrulli -*/ -/*---------------------------------------------------------------------------*/ - #include - #include "dev/watchdog.h" - - /*---------------------------------------------------------------------------*/ void watchdog_init(void) @@ -55,28 +43,24 @@ watchdog_init(void) void watchdog_start(void) { - /* We setup the watchdog to reset the device after 2.048 seconds, - unless watchdog_periodic() is called. */ - //halInternalEnableWatchDog(); + } /*---------------------------------------------------------------------------*/ void watchdog_periodic(void) { - /* This function is called periodically to restart the watchdog - timer. */ - //halResetWatchdog(); + } /*---------------------------------------------------------------------------*/ void watchdog_stop(void) { - //halInternalDisableWatchDog(MICRO_DISABLE_WATCH_DOG_KEY); + } /*---------------------------------------------------------------------------*/ void watchdog_reboot(void) { - //halReboot(); + } /*---------------------------------------------------------------------------*/ diff --git a/doc/Doxyfile b/doc/Doxyfile index cd0d1ac7c..fcf372ed2 100644 --- a/doc/Doxyfile +++ b/doc/Doxyfile @@ -807,7 +807,8 @@ EXCLUDE_SYMLINKS = NO # Note that the wildcards are matched against the file with absolute path, so to # exclude all test directories for example use the pattern */test/* -EXCLUDE_PATTERNS = */cpu/cc26xx/lib/* +EXCLUDE_PATTERNS = */cpu/cc26xx/lib/* \ + */platform/stm32nucleo-spirit1/stm32cube-lib/* # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # (namespaces, classes, functions, etc.) that should be excluded from the diff --git a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 index 037e64be8..fc6c50f6a 100644 --- a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 +++ b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 @@ -29,17 +29,22 @@ endif #Currently we support only GCC GCC=1 -CONTIKI_TARGET_DIRS += stm32cube-hal/Src CONTIKI_TARGET_DIRS += dev -CONTIKI_TARGET_DIRS += drivers/stm32l1xx_nucleo -CONTIKI_TARGET_DIRS += drivers/x_nucleo_ids01ax -CONTIKI_TARGET_DIRS += drivers/Common -CONTIKI_TARGET_DIRS += drivers/spirit1/src drivers/spirit1/inc +CONTIKI_TARGET_DIRS += stm32cube-lib/stm32cube-prj/Src +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/stm32l1xx_nucleo +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/x_nucleo_ids01ax +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/Common +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/spirit1/src stm32cube-lib/drivers/spirit1/inc +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/CMSIS +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/STM32L1xx_HAL_Driver +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/STM32L1xx_HAL_Driver/Src +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/STM32L1xx_HAL_Driver/Inc + ifeq ($(COMPILE_SENSORS),TRUE) -CONTIKI_TARGET_DIRS += drivers/x_nucleo_iks01a1 -CONTIKI_TARGET_DIRS += drivers/sensors/hts221 drivers/sensors/lps25h drivers/sensors/lps25hb\ - drivers/sensors/lsm6ds0 drivers/sensors/lsm6ds3 drivers/sensors/lis3mdl +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/x_nucleo_iks01a1 +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/sensors/hts221 stm32cube-lib/drivers/sensors/lps25h stm32cube-lib/drivers/sensors/lps25hb\ + stm32cube-lib/drivers/sensors/lsm6ds0 stm32cube-lib/drivers/sensors/lsm6ds3 stm32cube-lib/drivers/sensors/lis3mdl endif @@ -86,12 +91,58 @@ ARCH_DRIVERS_SENSORS = hts221.c \ lsm6ds0.c \ lsm6ds3.c +STM32L1XX_HAL =\ + stm32l1xx_hal.c\ + stm32l1xx_hal_adc_ex.c\ + stm32l1xx_hal_adc.c\ + stm32l1xx_hal_comp.c\ + stm32l1xx_hal_cortex.c\ + stm32l1xx_hal_crc.c\ + stm32l1xx_hal_cryp_ex.c\ + stm32l1xx_hal_cryp.c\ + stm32l1xx_hal_dac_ex.c\ + stm32l1xx_hal_dac.c\ + stm32l1xx_hal_dma.c\ + stm32l1xx_hal_flash_ex.c\ + stm32l1xx_hal_flash.c\ + stm32l1xx_hal_flash_ramfunc.c\ + stm32l1xx_hal_gpio.c\ + stm32l1xx_hal_i2c.c\ + stm32l1xx_hal_i2s.c\ + stm32l1xx_hal_irda.c\ + stm32l1xx_hal_iwdg.c\ + stm32l1xx_hal_lcd.c\ + stm32l1xx_hal_nor.c\ + stm32l1xx_hal_opamp_ex.c\ + stm32l1xx_hal_opamp.c\ + stm32l1xx_hal_pcd_ex.c\ + stm32l1xx_hal_pcd.c\ + stm32l1xx_hal_pwr_ex.c\ + stm32l1xx_hal_pwr.c\ + stm32l1xx_hal_rcc_ex.c\ + stm32l1xx_hal_rcc.c\ + stm32l1xx_hal_rtc_ex.c\ + stm32l1xx_hal_rtc.c\ + stm32l1xx_hal_sd.c\ + stm32l1xx_hal_smartcard.c\ + stm32l1xx_hal_spi_ex.c\ + stm32l1xx_hal_spi.c\ + stm32l1xx_hal_sram.c\ + stm32l1xx_hal_tim_ex.c\ + stm32l1xx_hal_tim.c\ + stm32l1xx_hal_uart.c\ + stm32l1xx_hal_usart.c\ + stm32l1xx_hal_wwdg.c\ + stm32l1xx_ll_fsmc.c\ + stm32l1xx_ll_sdmmc.c + ARCH+=$(ARCH_DEV) ARCH+=$(ARCH_NUCLEOSPIRIT1) ARCH+=$(ARCH_NUCLEOSPIRIT1_STM32CUBEHAL) ARCH+=$(ARCH_DRIVERS_STM32L1xx) ARCH+=$(ARCH_DRIVERS_IDS01AX) ARCH+=$(ARCH_DRIVERS_SPIRIT1) +ARCH+=$(STM32L1XX_HAL) ifeq ($(COMPILE_SENSORS),TRUE) ARCH+=$(ARCH_DEV_SENSORS) @@ -111,18 +162,15 @@ CFLAGS += -DUSE_STM32L152_EVAL \ CFLAGS += -I. \ -I$(CONTIKI)/platform/$(TARGET)/ \ - -I$(CONTIKI)/platform/$(TARGET)/stm32cube-hal/Inc \ - -I$(CONTIKI)/platform/$(TARGET)/drivers/Common \ - -I$(CONTIKI)/platform/$(TARGET)/divers/x_nucleo_ids01ax\ - -I$(CONTIKI)/platform/$(TARGET)/drivers/spirit1/inc \ - -I$(CONTIKI)/cpu/arm/stm32l152/CMSIS \ - -I$(CONTIKI)/platform/$(TARGET)/drvers/stm32l1xx_nucleo \ - -I$(CONTIKI)/cpu/arm/stm32l152/STM32L1xx_HAL_Driver/Inc \ + -I$(CONTIKI)/platform/$(TARGET)/stm32cube-lib/stm32cube-prj/Inc \ + -I$(CONTIKI)/platform/$(TARGET)/stm32cube-lib/drivers/Common \ + -I$(CONTIKI)/platform/$(TARGET)/stm32cube-lib/drivers/spirit1/inc \ + -I$(CONTIKI)/platform/$(TARGET)/stm32cube-lib/drivers/CMSIS \ + -I$(CONTIKI)/platform/$(TARGET)/stm32cube-lib/drivers/STM32L1xx_HAL_Driver/Inc \ -I$(CONTIKI)/cpu/arm/stm32l152 \ -I$(CONTIKI)/core \ -I$(CONTIKI)/platform/$(TARGET)/dev - ifdef UIP_CONF_IPV6 CFLAGS += -DWITH_UIP6=1 endif diff --git a/platform/stm32nucleo-spirit1/contiki-conf.h b/platform/stm32nucleo-spirit1/contiki-conf.h index f77e4d35d..d6c5e87ad 100644 --- a/platform/stm32nucleo-spirit1/contiki-conf.h +++ b/platform/stm32nucleo-spirit1/contiki-conf.h @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file contiki-conf.h +* @file platform/stm32nucleo-spirit1/contiki-conf.h * @author System LAB * @version V1.0.0 * @date 17-May-2015 @@ -34,12 +34,12 @@ * ****************************************************************************** */ - +/*---------------------------------------------------------------------------*/ #ifndef __CONTIKI_CONF_H__ #define __CONTIKI_CONF_H__ - +/*---------------------------------------------------------------------------*/ #include "platform-conf.h" - +/*---------------------------------------------------------------------------*/ #define SLIP_BRIDGE_CONF_NO_PUTCHAR 1 #define NETSTACK_CONF_RDC_CHANNEL_CHECK_RATE 8 @@ -65,7 +65,6 @@ /* Network setup for IPv6 */ - #define CXMAC_CONF_ANNOUNCEMENTS 0 @@ -142,13 +141,12 @@ #define UIP_CONF_UDP 1 #define UIP_CONF_UDP_CHECKSUMS 1 #define UIP_CONF_TCP 1 - +/*---------------------------------------------------------------------------*/ /* include the project config */ /* PROJECT_CONF_H might be defined in the project Makefile */ #ifdef PROJECT_CONF_H #include PROJECT_CONF_H #endif /* PROJECT_CONF_H */ - - - +/*---------------------------------------------------------------------------*/ #endif /* CONTIKI_CONF_H */ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c index 8e25ba9a7..c8ab0edf9 100644 --- a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c +++ b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c @@ -4,7 +4,7 @@ * @author System LAB * @version V1.0.0 * @date 17-June-2015 -* @brief Contiki main file for SPIRIT1 platform +* @brief Contiki main file for stm32nucleo-spirit1 platform ****************************************************************************** * @attention * @@ -34,7 +34,14 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1 + * @{ + * + * \file + * main file for stm32nucleo-spirit1 platform + */ +/*---------------------------------------------------------------------------*/ #include #include #include "stm32cube_hal_init.h" @@ -60,11 +67,11 @@ #include "hw-config.h" #include "stdbool.h" #include "dev/button-sensor.h" - +/*---------------------------------------------------------------------------*/ #if NETSTACK_CONF_WITH_IPV6 #include "net/ipv6/uip-ds6.h" #endif /*NETSTACK_CONF_WITH_IPV6*/ - +/*---------------------------------------------------------------------------*/ #if COMPILE_SENSORS extern const struct sensors_sensor temperature_sensor; extern const struct sensors_sensor humidity_sensor; @@ -79,11 +86,12 @@ SENSORS(&button_sensor, &magneto_sensor, &acceleration_sensor, &gyroscope_sensor); -#else +#else /*COMPILE_SENSORS*/ SENSORS(&button_sensor); -#endif - +#endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ extern unsigned char node_mac[8]; +/*---------------------------------------------------------------------------*/ #ifdef __GNUC__ /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf set to 'Yes') calls __io_putchar() */ @@ -91,27 +99,23 @@ set to 'Yes') calls __io_putchar() */ #else #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) #endif /* __GNUC__ */ - - +/*---------------------------------------------------------------------------*/ #if NETSTACK_CONF_WITH_IPV6 PROCINIT(&etimer_process, &tcpip_process); -#else +#else /*NETSTACK_CONF_WITH_IPV6*/ PROCINIT(&etimer_process); #warning "No TCP/IP process!" -#endif - +#endif /*NETSTACK_CONF_WITH_IPV6*/ +/*---------------------------------------------------------------------------*/ #define BUSYWAIT_UNTIL(cond, max_time) \ -do { \ - rtimer_clock_t t0; \ +do { \ + rtimer_clock_t t0; \ t0 = RTIMER_NOW(); \ - while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ + while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ } while(0) - - /*---------------------------------------------------------------------------*/ static void set_rime_addr(void); -int Stack_6LoWPAN_Init(int argc, char *argv[]); - +void stm32cube_hal_init(); /*---------------------------------------------------------------------------*/ #if 0 static void panic_main(void) @@ -126,7 +130,6 @@ static void panic_main(void) /*---------------------------------------------------------------------------*/ int main (int argc, char *argv[]) { - stm32cube_hal_init(); /* init LEDs */ @@ -171,18 +174,13 @@ int main (int argc, char *argv[]) watchdog_start(); - while(1) - { - - int r = 0; - do { - r = process_run(); - } while(r > 0); - - } + while(1) { + int r = 0; + do { + r = process_run(); + } while(r > 0); + } } - - /*---------------------------------------------------------------------------*/ static void set_rime_addr(void) { @@ -193,3 +191,5 @@ static void set_rime_addr(void) linkaddr_set_node_addr(&addr); } +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c index 20eb12dec..288faab98 100644 --- a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c @@ -34,98 +34,102 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/** + * \addtogroup stm32nucleo-spirit1-temperature-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Temperature sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ #if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "acceleration-sensor.h" - -#include "x_nucleo_iks01a1_imu_6axes.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ static int _active = 1; - +/*---------------------------------------------------------------------------*/ static void init(void) { /*Acceleration and Gyroscope sensors share the same hw*/ - if (!BSP_IMU_6AXES_isInitialized()) - { - if (IMU_6AXES_OK == BSP_IMU_6AXES_Init()) - { + if (!st_lib_bsp_imu_6axes_is_initialized()) { + if (IMU_6AXES_OK == st_lib_bsp_imu_6axes_init()) { _active = 1; } } } - +/*---------------------------------------------------------------------------*/ static void activate(void) { _active = 1; } - +/*---------------------------------------------------------------------------*/ static void deactivate(void) { _active = 0; } - - +/*---------------------------------------------------------------------------*/ static int active(void) { return _active; } - - +/*---------------------------------------------------------------------------*/ static int value(int type) { - int32_t RetVal; - volatile AxesRaw_TypeDef AxesRaw_Data; + int32_t ret_val = 0; + volatile st_lib_axes_raw_typedef axes_raw_data; - BSP_IMU_6AXES_X_GetAxesRaw(&AxesRaw_Data); + st_lib_bsp_imu_6axes_x_get_axes_raw(&axes_raw_data); - switch (type) - { + switch (type) { case X_AXIS: - RetVal = AxesRaw_Data.AXIS_X ; + ret_val = axes_raw_data.AXIS_X ; break; case Y_AXIS: - RetVal = AxesRaw_Data.AXIS_Y ; + ret_val = axes_raw_data.AXIS_Y ; break; case Z_AXIS: - RetVal = AxesRaw_Data.AXIS_Z ; + ret_val = axes_raw_data.AXIS_Z ; break; default: break; } - return (RetVal); + return ret_val; } - +/*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) - activate(); - else - deactivate(); - return 1; + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } - +/*---------------------------------------------------------------------------*/ static int status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } return 0; } - -SENSORS_SENSOR(acceleration_sensor, ACCELERATION_SENSOR, value, configure, status); - +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(acceleration_sensor, ACCELERATION_SENSOR, + value, configure, status); +/*---------------------------------------------------------------------------*/ #endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h index b61592241..818eb979f 100644 --- a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h @@ -34,16 +34,33 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \defgroup stm32nucleo-spirit1-acceleration-sensor Acceleration Sensor + * + * Maps the acceleration sensor on the STM32 Nucleo Sensor Expansion board. + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 Acceleration Sensor Driver + */ +/*---------------------------------------------------------------------------*/ #ifndef ACCELERATION_SENSOR_H_ #define ACCELERATION_SENSOR_H_ - +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "sensor-common.h" - +/*---------------------------------------------------------------------------*/ extern const struct sensors_sensor acceleration_sensor; - +/*---------------------------------------------------------------------------*/ #define ACCELERATION_SENSOR "Acceleration" - +/*---------------------------------------------------------------------------*/ #endif /* ACCELERATION_SENSOR_H_ */ - +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/dev/button-sensor.c b/platform/stm32nucleo-spirit1/dev/button-sensor.c index ab2ca12ec..9a1e7c8a8 100644 --- a/platform/stm32nucleo-spirit1/dev/button-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/button-sensor.c @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file button-sensor.c +* @file platform/stm32nucleo-spirit1/dev/button-sensor.c * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,72 +34,76 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 User Button + */ +/*---------------------------------------------------------------------------*/ #include "dev/button-sensor.h" #include "lib/sensors.h" - -#include "stm32l1xx_nucleo.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ static int _active = 0 ; - +/*---------------------------------------------------------------------------*/ static void init(void) { /* See spirit1_appli.c for the Callback: it triggers the relevant * sensors_changed event */ - BSP_PB_Init(BUTTON_USER, BUTTON_MODE_EXTI); + st_lib_bsp_pb_init(BUTTON_USER, BUTTON_MODE_EXTI); } - +/*---------------------------------------------------------------------------*/ static void activate(void) { _active = 1; } - +/*---------------------------------------------------------------------------*/ static void deactivate(void) { _active = 0; } - +/*---------------------------------------------------------------------------*/ static int active(void) { return active; } - +/*---------------------------------------------------------------------------*/ static int value(int type) { - return BSP_PB_GetState(BUTTON_USER); + return st_lib_bsp_pb_get_state(BUTTON_USER); } - +/*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) - activate(); - else - deactivate(); - return 1; + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } - +/*---------------------------------------------------------------------------*/ static int status(int type) { switch(type) { - - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } return 0; } - - +/*---------------------------------------------------------------------------*/ SENSORS_SENSOR(button_sensor, BUTTON_SENSOR, value, configure, status); - +/*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c index f7140652b..34ea00139 100644 --- a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c @@ -34,98 +34,101 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/** + * \addtogroup stm32nucleo-spirit1-gyroscope-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Gyroscope sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ #if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "gyroscope-sensor.h" - -#include "x_nucleo_iks01a1_imu_6axes.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ static int _active = 1; - +/*---------------------------------------------------------------------------*/ static void init(void) { /*Acceleration and Gyroscope sensors share the same hw*/ - if (!BSP_IMU_6AXES_isInitialized()) - { - if (IMU_6AXES_OK == BSP_IMU_6AXES_Init()) - { + if (!st_lib_bsp_imu_6axes_is_initialized()) { + if (IMU_6AXES_OK == st_lib_bsp_imu_6axes_init()) { _active = 1; } } } - +/*---------------------------------------------------------------------------*/ static void activate(void) { _active = 1; } - +/*---------------------------------------------------------------------------*/ static void deactivate(void) { _active = 0; } - - +/*---------------------------------------------------------------------------*/ static int active(void) { return _active; } - - +/*---------------------------------------------------------------------------*/ static int value(int type) { - int32_t RetVal; - volatile AxesRaw_TypeDef AxesRaw_Data; + int32_t ret_val = 0; + volatile st_lib_axes_raw_typedef axes_raw_data; - BSP_IMU_6AXES_G_GetAxesRaw(&AxesRaw_Data); + st_lib_bsp_imu_6axes_g_get_axes_raw(&axes_raw_data); - switch (type) - { + switch (type) { case X_AXIS: - RetVal = AxesRaw_Data.AXIS_X ; + ret_val = axes_raw_data.AXIS_X ; break; case Y_AXIS: - RetVal = AxesRaw_Data.AXIS_Y ; + ret_val = axes_raw_data.AXIS_Y ; break; case Z_AXIS: - RetVal = AxesRaw_Data.AXIS_Z ; + ret_val = axes_raw_data.AXIS_Z ; break; default: break; } - return (RetVal); + return ret_val; } - +/*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) - activate(); - else - deactivate(); - return 1; + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } - +/*---------------------------------------------------------------------------*/ static int status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } return 0; } - +/*---------------------------------------------------------------------------*/ SENSORS_SENSOR(gyroscope_sensor, GYROSCOPE_SENSOR, value, configure, status); - +/*---------------------------------------------------------------------------*/ #endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h index 083525ef8..43bc4ce64 100644 --- a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h @@ -34,16 +34,33 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \defgroup stm32nucleo-spirit1-gyroscope-sensor Gyroscope Sensor + * + * Maps the gyroscope sensor on the STM32 Sensor Expansion board. + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 Gyroscope Sensor Driver + */ +/*---------------------------------------------------------------------------*/ #ifndef GYROSCOPE_SENSOR_H_ #define GYROSCOPE_SENSOR_H_ - +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "sensor-common.h" - +/*---------------------------------------------------------------------------*/ extern const struct sensors_sensor gyroscope_sensor; - +/*---------------------------------------------------------------------------*/ #define GYROSCOPE_SENSOR "Gyroscope" - +/*---------------------------------------------------------------------------*/ #endif /* GYROSCOPE_SENSOR_H_ */ - +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/dev/humidity-sensor.c b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c index ec3772677..54256a332 100644 --- a/platform/stm32nucleo-spirit1/dev/humidity-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c @@ -34,84 +34,87 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - - +/** + * \addtogroup stm32nucleo-spirit1-humidity-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Humidity sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ #if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "humidity-sensor.h" - -#include "x_nucleo_iks01a1_hum_temp.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ static int _active = 1; - +/*---------------------------------------------------------------------------*/ static void init(void) { /*Temperature and Humity sensors share the same hw*/ - if (!BSP_HUM_TEMP_isInitialized()) - { - BSP_HUM_TEMP_Init(); - _active = 1; + if (!st_lib_bsp_hum_temp_is_initialized()) { + st_lib_bsp_hum_temp_init(); + _active=1; } } - +/*---------------------------------------------------------------------------*/ static void activate(void) { _active = 1; } - +/*---------------------------------------------------------------------------*/ static void deactivate(void) { _active = 0; } - - +/*---------------------------------------------------------------------------*/ static int active(void) { return _active; } - - +/*---------------------------------------------------------------------------*/ static int value(int type) { uint32_t humidity; - volatile float HUMIDITY_Value; + volatile float humidity_value; - BSP_HUM_TEMP_GetHumidity((float *)&HUMIDITY_Value); + st_lib_bsp_hum_temp_get_humidity((float *)&humidity_value); - humidity = HUMIDITY_Value * 10; - return(humidity); + humidity = humidity_value * 10; + return humidity; } - - +/*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) - activate(); - else - deactivate(); - return 1; + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } - +/*---------------------------------------------------------------------------*/ static int status(int type) { - switch(type) - { - case SENSORS_READY: - return active(); + switch(type) { + case SENSORS_READY: + return active(); } return 0; } - +/*---------------------------------------------------------------------------*/ SENSORS_SENSOR(humidity_sensor, HUMIDITY_SENSOR, value, configure, status); +/*---------------------------------------------------------------------------*/ #endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/humidity-sensor.h b/platform/stm32nucleo-spirit1/dev/humidity-sensor.h index fc18349bb..3de0b0687 100644 --- a/platform/stm32nucleo-spirit1/dev/humidity-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/humidity-sensor.h @@ -34,15 +34,32 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \defgroup stm32nucleo-spirit1-humidity-sensor Humidity Sensor + * + * Maps the humidity sensor on the STM32 Nucleo Sensor Expansion board. + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 Humidity Sensor Driver + */ +/*---------------------------------------------------------------------------*/ #ifndef HUMIDITY_SENSOR_H_ #define HUMIDITY_SENSOR_H_ - +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" - +/*---------------------------------------------------------------------------*/ extern const struct sensors_sensor humidity_sensor; - +/*---------------------------------------------------------------------------*/ #define HUMIDITY_SENSOR "Humidity" - +/*---------------------------------------------------------------------------*/ #endif /* HUMIDITY_SENSOR_H_ */ - +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/dev/leds-arch.c b/platform/stm32nucleo-spirit1/dev/leds-arch.c index 52e2a9cfb..a05fe0832 100644 --- a/platform/stm32nucleo-spirit1/dev/leds-arch.c +++ b/platform/stm32nucleo-spirit1/dev/leds-arch.c @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file leds-arch.c +* @file platform/stm32nucleo-spirit1/dev/leds-arch.c * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,78 +34,82 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 LEDs + */ +/*---------------------------------------------------------------------------*/ #include "contiki-conf.h" #include "dev/leds.h" -#include "stm32l1xx_nucleo.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ #ifndef COMPILE_SENSORS -#include "radio_shield_config.h" -extern GPIO_TypeDef* aLED_GPIO_PORT[]; -extern const uint16_t aLED_GPIO_PIN[]; +/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT + * used, becasue of a pin conflict. + */ +extern st_lib_gpio_typedef* st_lib_a_led_gpio_port[]; +extern const uint16_t st_lib_a_led_gpio_pin[]; #endif /*COMPILE_SENSORS*/ -extern GPIO_TypeDef* GPIO_PORT[]; -extern const uint16_t GPIO_PIN[]; - - +extern st_lib_gpio_typedef* st_lib_gpio_port[]; +extern const uint16_t st_lib_gpio_pin[]; /*---------------------------------------------------------------------------*/ void leds_arch_init(void) { - /* We have two led, one on the Nucleo (GREEN) ....*/ - BSP_LED_Init(LED2); - BSP_LED_Off(LED2); + /* We have at least one led, the one on the Nucleo (GREEN)*/ + st_lib_bsp_led_init(LED2); + st_lib_bsp_led_off(LED2); #ifndef COMPILE_SENSORS - /* ... and one the SPIRIT1 (RED) ....*/ - RadioShieldLedInit(RADIO_SHIELD_LED); - RadioShieldLedOff(RADIO_SHIELD_LED); +/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT + * used, becasue of a pin conflict. + */ + st_lib_radio_shield_led_init(RADIO_SHIELD_LED); + st_lib_radio_shield_led_off(RADIO_SHIELD_LED); #endif /*COMPILE_SENSORS*/ } - /*---------------------------------------------------------------------------*/ unsigned char leds_arch_get(void) { unsigned char ret = 0 ; - if (HAL_GPIO_ReadPin(GPIO_PORT[LED2],GPIO_PIN[LED2])) - { + if (st_lib_hal_gpio_read_pin(st_lib_gpio_port[LED2],st_lib_gpio_pin[LED2])) { ret |= LEDS_GREEN; } #ifndef COMPILE_SENSORS - if (HAL_GPIO_ReadPin(aLED_GPIO_PORT[RADIO_SHIELD_LED], - aLED_GPIO_PIN[RADIO_SHIELD_LED]) - ) - { +/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT + * used, becasue of a pin conflict. + */ + if (st_lib_hal_gpio_read_pin(st_lib_a_led_gpio_port[RADIO_SHIELD_LED], + st_lib_a_led_gpio_pin[RADIO_SHIELD_LED])) { ret |= LEDS_RED; } #endif /*COMPILE_SENSORS*/ return ret; } - /*---------------------------------------------------------------------------*/ void leds_arch_set(unsigned char leds) { - if (leds & LEDS_GREEN) - { - BSP_LED_On(LED2); - } - else - { - BSP_LED_Off(LED2); + if (leds & LEDS_GREEN) { + st_lib_bsp_led_on(LED2); + } else { + st_lib_bsp_led_off(LED2); } #ifndef COMPILE_SENSORS - if (leds & LEDS_RED) - { - RadioShieldLedOn(RADIO_SHIELD_LED); - } - else - { - RadioShieldLedOff(RADIO_SHIELD_LED); +/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT + * used, becasue of a pin conflict. + */ + if (leds & LEDS_RED) { + st_lib_radio_shield_led_on(RADIO_SHIELD_LED); + } else { + st_lib_radio_shield_led_off(RADIO_SHIELD_LED); } #endif /*COMPILE_SENSORS*/ } /*---------------------------------------------------------------------------*/ - +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c index b2f23f67c..6535b37b4 100644 --- a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c @@ -34,92 +34,97 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/** + * \addtogroup stm32nucleo-spirit1-magneto-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Magneto sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ #if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "magneto-sensor.h" - -#include "x_nucleo_iks01a1_magneto.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ static int _active = 1; - +/*---------------------------------------------------------------------------*/ static void init(void) { BSP_MAGNETO_Init(); _active = 1; } - +/*---------------------------------------------------------------------------*/ static void activate(void) { _active = 1; } - +/*---------------------------------------------------------------------------*/ static void deactivate(void) { _active = 0; } - - +/*---------------------------------------------------------------------------*/ static int active(void) { return _active; } - - +/*---------------------------------------------------------------------------*/ static int value(int type) { - int32_t RetVal; - volatile AxesRaw_TypeDef AxesRaw_Data; + int32_t ret_val = 0; + volatile st_lib_axes_raw_typedef axes_raw_data; - BSP_MAGNETO_M_GetAxesRaw(&AxesRaw_Data); + st_lib_bsp_magneto_m_get_axes_raw(&axes_raw_data); - switch (type) - { + switch (type) { case X_AXIS: - RetVal = AxesRaw_Data.AXIS_X ; + ret_val = axes_raw_data.AXIS_X ; break; case Y_AXIS: - RetVal = AxesRaw_Data.AXIS_Y ; + ret_val = axes_raw_data.AXIS_Y ; break; case Z_AXIS: - RetVal = AxesRaw_Data.AXIS_Z ; + ret_val = axes_raw_data.AXIS_Z ; break; default: break; } - return(RetVal); + return ret_val; } - +/*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) - activate(); - else - deactivate(); - return 1; + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } - +/*---------------------------------------------------------------------------*/ static int status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } return 0; } - +/*---------------------------------------------------------------------------*/ SENSORS_SENSOR(magneto_sensor, MAGNETO_SENSOR, value, configure, status); - +/*---------------------------------------------------------------------------*/ #endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.h b/platform/stm32nucleo-spirit1/dev/magneto-sensor.h index adaeef7ad..b75d47292 100644 --- a/platform/stm32nucleo-spirit1/dev/magneto-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.h @@ -34,16 +34,33 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \defgroup stm32nucleo-spirit1-magneto-sensor Magneto Sensor + * + * Maps the magneto sensor on the STM32 Nucleo Sensor Expansion board. + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 Magneto Sensor Driver + */ +/*---------------------------------------------------------------------------*/ #ifndef MAGNETO_SENSOR_H_ #define MAGNETO_SENSOR_H_ - +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "sensor-common.h" - +/*---------------------------------------------------------------------------*/ extern const struct sensors_sensor magneto_sensor; - +/*---------------------------------------------------------------------------*/ #define MAGNETO_SENSOR "Magneto" - +/*---------------------------------------------------------------------------*/ #endif /* MAGNETO_SENSOR_H_ */ - +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/dev/pressure-sensor.c b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c index c9535ab59..df1e752da 100644 --- a/platform/stm32nucleo-spirit1/dev/pressure-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c @@ -34,79 +34,83 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/** + * \addtogroup stm32nucleo-spirit1-pressure-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Pressure sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ #if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "pressure-sensor.h" - -#include "x_nucleo_iks01a1_pressure.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ static int _active = 1; - +/*---------------------------------------------------------------------------*/ static void init(void) { - BSP_PRESSURE_Init(); + st_lib_bsp_pressure_init(); _active =1; } - - +/*---------------------------------------------------------------------------*/ static void activate(void) { _active = 1; } - +/*---------------------------------------------------------------------------*/ static void deactivate(void) { _active = 0; } - - +/*---------------------------------------------------------------------------*/ static int active(void) { return _active; } - - +/*---------------------------------------------------------------------------*/ static int value(int type) { uint16_t pressure; - volatile float PRESSURE_Value; + volatile float pressure_value; - BSP_PRESSURE_GetPressure((float *)&PRESSURE_Value); - pressure = PRESSURE_Value * 10; + st_lib_bsp_pressure_get_pressure((float *)&pressure_value); + pressure = pressure_value * 10; - return(pressure); + return pressure; } - +/*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) - activate(); - else - deactivate(); - return 1; + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } - +/*---------------------------------------------------------------------------*/ static int status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } return 0; } - +/*---------------------------------------------------------------------------*/ SENSORS_SENSOR(pressure_sensor, PRESSURE_SENSOR, value, configure, status); - +/*---------------------------------------------------------------------------*/ #endif /*COMPILE_SENSORS*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/pressure-sensor.h b/platform/stm32nucleo-spirit1/dev/pressure-sensor.h index d68ce27a5..d226f1de5 100644 --- a/platform/stm32nucleo-spirit1/dev/pressure-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/pressure-sensor.h @@ -34,15 +34,32 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \defgroup stm32nucleo-spirit1-pressure-sensor Pressure Sensor + * + * Maps the pressure sensor on the STM32 Nucleo Sensor Expansion board. + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 Pressure Sensor Driver + */ +/*---------------------------------------------------------------------------*/ #ifndef PRESSURE_SENSOR_H_ #define PRESSURE_SENSOR_H_ - +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" - +/*---------------------------------------------------------------------------*/ extern const struct sensors_sensor pressure_sensor; - +/*---------------------------------------------------------------------------*/ #define PRESSURE_SENSOR "Pressure" - +/*---------------------------------------------------------------------------*/ #endif /* PRESSURE_SENSOR_H_ */ - +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/dev/sensor-common.h b/platform/stm32nucleo-spirit1/dev/sensor-common.h index 8748dfaeb..0b1368203 100644 --- a/platform/stm32nucleo-spirit1/dev/sensor-common.h +++ b/platform/stm32nucleo-spirit1/dev/sensor-common.h @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file sensor-common.h +* @file platform/stm32nucleo-spirit1/dev/sensor-common.h * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,12 +34,23 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * + * \file + * Header file for common sensor definitions. + */ +/*---------------------------------------------------------------------------*/ #ifndef SENSOR_COMMON_H_ #define SENSOR_COMMON_H_ - +/*---------------------------------------------------------------------------*/ #define X_AXIS 0x00 #define Y_AXIS 0x01 #define Z_AXIS 0x02 - +/*---------------------------------------------------------------------------*/ #endif /*SENSOR_COMMON_H_*/ +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/temperature-sensor.c b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c index 17e187934..7370b33d0 100644 --- a/platform/stm32nucleo-spirit1/dev/temperature-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file temperature-sensor.c +* @file platform/stm32nucleo-spirit1/dev/temperature-sensor.c * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,79 +34,86 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/** + * \addtogroup stm32nucleo-spirit1-temperature-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Temperature sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ #if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "temperature-sensor.h" - -#include "x_nucleo_iks01a1_hum_temp.h" - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ static int _active = 0; - +/*---------------------------------------------------------------------------*/ static void init(void) { /*Temperature and Humity sensors share the same hw*/ - if (!BSP_HUM_TEMP_isInitialized()) - { - BSP_HUM_TEMP_Init(); + if (!st_lib_bsp_hum_temp_is_initialized()) { + st_lib_bsp_hum_temp_init(); _active=1; } } - +/*---------------------------------------------------------------------------*/ static void activate(void) { _active = 1; } - +/*---------------------------------------------------------------------------*/ static void deactivate(void) { _active = 0; } - - +/*---------------------------------------------------------------------------*/ static int active(void) { return _active; } - +/*---------------------------------------------------------------------------*/ static int value(int type) { int32_t temperature; - volatile float TEMPERATURE_Value; + volatile float temperature_value; - BSP_HUM_TEMP_GetTemperature((float *)&TEMPERATURE_Value); - temperature = TEMPERATURE_Value * 10; - return(temperature); + st_lib_bsp_hum_temp_get_temperature((float *)&temperature_value); + temperature = temperature_value * 10; + return temperature; } - +/*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) - activate(); - else - deactivate(); - return 1; + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } - +/*---------------------------------------------------------------------------*/ static int status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } return 0; } - -SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, value, configure, status); +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, + value, configure, status); #endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/temperature-sensor.h b/platform/stm32nucleo-spirit1/dev/temperature-sensor.h index c54fb47ef..eb6fd2376 100644 --- a/platform/stm32nucleo-spirit1/dev/temperature-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/temperature-sensor.h @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file temperature-sensor.h +* @file platform/stm32nucleo-spirit1/dev/temperature-sensor.h * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,15 +34,32 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \defgroup stm32nucleo-spirit1-temperature-sensor Temperature Sensor + * + * Maps the temperature sensor on the STM32 Nucleo Sensor Expansion board. + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 Temperature Sensor Driver + */ +/*---------------------------------------------------------------------------*/ #ifndef TEMPERATURE_SENSOR_H_ #define TEMPERATURE_SENSOR_H_ - +/*---------------------------------------------------------------------------*/ #include "lib/sensors.h" - +/*---------------------------------------------------------------------------*/ extern const struct sensors_sensor temperature_sensor; - +/*---------------------------------------------------------------------------*/ #define TEMPERATURE_SENSOR "Temperature" - +/*---------------------------------------------------------------------------*/ #endif /* TEMPERATURE_SENSOR_H_ */ - +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/dev/uart1.h b/platform/stm32nucleo-spirit1/dev/uart1.h index 7867bc5ec..a1d719083 100644 --- a/platform/stm32nucleo-spirit1/dev/uart1.h +++ b/platform/stm32nucleo-spirit1/dev/uart1.h @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file uart1.h +* @file platform/stm32nucleo-spirit1/dev/uart1.h * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,14 +34,21 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - - +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * + * \file + * Header file for UART related definitions. + */ +/*---------------------------------------------------------------------------*/ #ifndef UART1_H_ #define UART1_H_ - +/*---------------------------------------------------------------------------*/ #define BAUD2UBR(baud) baud - - +/*---------------------------------------------------------------------------*/ #endif /* UART1_H_ */ - +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/drivers/Common/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/Common/Release_Notes.html deleted file mode 100644 index e3b4d49a2..000000000 --- a/platform/stm32nucleo-spirit1/drivers/Common/Release_Notes.html +++ /dev/null @@ -1,412 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - Release Notes for BSP Components Common Drivers - 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Release -Notes for BSP Components Common  Drivers

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Update History

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V1.2.1 / 02-December-2014

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  • gyro.h: change “__GIRO_H” by “__GYRO_H” to fix compilation issue under Mac OS
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V1.2.0 / 18-June-2014

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  • EPD (E Paper Display)  driver function prototype added (epd.h file)
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V1.1.0 / 21-March-2014

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  • Temperature Sensor driver function prototype added

V1.0.0 / 18-February-2014

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  • First official release with  Accelerometer, Audio, Camera, Gyroscope, IO, LCD and Touch Screen drivers function prototypes

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For -complete documentation on STM32 Microcontrollers -visit www.st.com/STM32

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- - \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/Common/hum_temp.h b/platform/stm32nucleo-spirit1/drivers/Common/hum_temp.h deleted file mode 100644 index 460708ef6..000000000 --- a/platform/stm32nucleo-spirit1/drivers/Common/hum_temp.h +++ /dev/null @@ -1,151 +0,0 @@ -/** - ****************************************************************************** - * @file hum_temp.h - * @author MEMS Application Team - * @version V1.2.0 - * @date 28-January-2015 - * @brief This header file contains the functions prototypes for the - * humidity and temperature driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __HUM_TEMP_H -#define __HUM_TEMP_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup HUM_TEMP - * @{ - */ - -/** @defgroup HUM_TEMP_Exported_Types - * @{ - */ - -/** - * @brief Humidity and temperature init structure definition - */ -typedef struct -{ - uint8_t Power_Mode; /* Power-down/Sleep/Normal Mode */ - uint8_t Data_Update_Mode; /* continuous update/output registers not updated until MSB and LSB reading*/ - uint8_t Reboot_Mode; /* Normal Mode/Reboot memory content */ - uint8_t Humidity_Resolutin; /* Humidity Resolution */ - uint8_t Temperature_Resolution; /* Temperature Resolution */ - uint8_t OutputDataRate; /* One-shot / 1Hz / 7 Hz / 12.5 Hz */ -} HUM_TEMP_InitTypeDef; - -/** - * @brief Humidity and temperature status enumerator definition - */ -typedef enum -{ - HUM_TEMP_OK = 0, - HUM_TEMP_ERROR = 1, - HUM_TEMP_TIMEOUT = 2, - HUM_TEMP_NOT_IMPLEMENTED = 3 -} HUM_TEMP_StatusTypeDef; - -/** - * @brief Humidity and temperature component id enumerator definition - */ -typedef enum -{ - HUM_TEMP_NONE_COMPONENT = 0, - HUM_TEMP_HTS221_COMPONENT = 1 -} HUM_TEMP_ComponentTypeDef; - -/** - * @brief Humidity and temperature driver extended structure definition - */ -typedef struct -{ - HUM_TEMP_ComponentTypeDef - id; /* This id must be unique for each component belonging to this class that wants to extend common class */ - void *pData; /* This pointer is specific for each component */ -} HUM_TEMP_DrvExtTypeDef; - -/** - * @brief Humidity and temperature driver structure definition - */ -typedef struct -{ - HUM_TEMP_StatusTypeDef (*Init)(HUM_TEMP_InitTypeDef *); - HUM_TEMP_StatusTypeDef (*PowerOFF)(void); - HUM_TEMP_StatusTypeDef (*ReadID)(uint8_t *); - HUM_TEMP_StatusTypeDef (*Reset)(void); - void (*ConfigIT)(uint16_t); - void (*EnableIT)(uint8_t); - void (*DisableIT)(uint8_t); - uint8_t (*ITStatus)(uint16_t, uint16_t); - void (*ClearIT)(uint16_t, uint16_t); - HUM_TEMP_StatusTypeDef (*GetHumidity)(float *); - HUM_TEMP_StatusTypeDef (*GetTemperature)(float *); - HUM_TEMP_DrvExtTypeDef *extData; -} HUM_TEMP_DrvTypeDef; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HUM_TEMP_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/Common/imu_6axes.h b/platform/stm32nucleo-spirit1/drivers/Common/imu_6axes.h deleted file mode 100644 index 44099539b..000000000 --- a/platform/stm32nucleo-spirit1/drivers/Common/imu_6axes.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - ****************************************************************************** - * @file imu_6axes.h - * @author MEMS Application Team - * @version V1.2.0 - * @date 28-January-2015 - * @brief This header file contains the functions prototypes for the - * accelerometer and gyroscope driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __IMU_6AXES_H -#define __IMU_6AXES_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup IMU_6AXES - * @{ - */ - -/** @defgroup IMU_6AXES_Exported_Types - * @{ - */ - -/** - * @brief IMU_6AXES init structure definition - */ -typedef struct -{ - float G_OutputDataRate; - float G_FullScale; - uint8_t G_X_Axis; - uint8_t G_Y_Axis; - uint8_t G_Z_Axis; - float X_OutputDataRate; - float X_FullScale; - uint8_t X_X_Axis; - uint8_t X_Y_Axis; - uint8_t X_Z_Axis; -} IMU_6AXES_InitTypeDef; - -/** - * @brief IMU_6AXES status enumerator definition - */ -typedef enum -{ - IMU_6AXES_OK = 0, - IMU_6AXES_ERROR = 1, - IMU_6AXES_TIMEOUT = 2, - IMU_6AXES_NOT_IMPLEMENTED = 3 -} IMU_6AXES_StatusTypeDef; - -/** - * @brief IMU_6AXES component id enumerator definition - */ -typedef enum -{ - IMU_6AXES_NONE_COMPONENT = 0, - IMU_6AXES_LSM6DS0_COMPONENT = 1, - IMU_6AXES_LSM6DS3_DIL24_COMPONENT = 2 -} IMU_6AXES_ComponentTypeDef; - -/** - * @brief IMU_6AXES driver extended structure definition - */ -typedef struct -{ - IMU_6AXES_ComponentTypeDef - id; /* This id must be unique for each component belonging to this class that wants to extend common class */ - void *pData; /* This pointer is specific for each component */ -} IMU_6AXES_DrvExtTypeDef; - -/** - * @brief IMU_6AXES driver structure definition - */ -typedef struct -{ - IMU_6AXES_StatusTypeDef (*Init)(IMU_6AXES_InitTypeDef *); - IMU_6AXES_StatusTypeDef (*Read_XG_ID)(uint8_t *); - IMU_6AXES_StatusTypeDef (*Get_X_Axes)(int32_t *); - IMU_6AXES_StatusTypeDef (*Get_X_AxesRaw)(int16_t *); - IMU_6AXES_StatusTypeDef (*Get_G_Axes)(int32_t *); - IMU_6AXES_StatusTypeDef (*Get_G_AxesRaw)(int16_t *); - IMU_6AXES_StatusTypeDef (*Get_X_ODR) (float *); - IMU_6AXES_StatusTypeDef (*Set_X_ODR) (float); - IMU_6AXES_StatusTypeDef (*Get_X_Sensitivity) (float *); - IMU_6AXES_StatusTypeDef (*Get_X_FS) (float *); - IMU_6AXES_StatusTypeDef (*Set_X_FS) (float); - IMU_6AXES_StatusTypeDef (*Get_G_ODR) (float *); - IMU_6AXES_StatusTypeDef (*Set_G_ODR) (float); - IMU_6AXES_StatusTypeDef (*Get_G_Sensitivity) (float *); - IMU_6AXES_StatusTypeDef (*Get_G_FS) (float *); - IMU_6AXES_StatusTypeDef (*Set_G_FS) (float); - IMU_6AXES_DrvExtTypeDef *extData; -} IMU_6AXES_DrvTypeDef; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __IMU_6AXES_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/Common/magneto.h b/platform/stm32nucleo-spirit1/drivers/Common/magneto.h deleted file mode 100644 index b22da5af7..000000000 --- a/platform/stm32nucleo-spirit1/drivers/Common/magneto.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - ****************************************************************************** - * @file magneto.h - * @author MEMS Application Team - * @version V1.2.0 - * @date 28-January-2015 - * @brief This header file contains the functions prototypes for the - * magneto driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAGNETO_H -#define __MAGNETO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup MAGNETO - * @{ - */ - -/** @defgroup MAGNETO_Exported_Types - * @{ - */ - -/** -* @brief MAGNETO init structure definition -*/ -typedef struct -{ - uint8_t M_OutputDataRate; - uint8_t M_OperatingMode; - uint8_t M_FullScale; - uint8_t M_XYOperativeMode; -} MAGNETO_InitTypeDef; - -/** -* @brief MAGNETO status enumerator definition -*/ -typedef enum -{ - MAGNETO_OK = 0, - MAGNETO_ERROR = 1, - MAGNETO_TIMEOUT = 2, - MAGNETO_NOT_IMPLEMENTED = 3 -} MAGNETO_StatusTypeDef; - -/** - * @brief MAGNETO component id enumerator definition - */ -typedef enum -{ - MAGNETO_NONE_COMPONENT = 0, - MAGNETO_LIS3MDL_COMPONENT = 1 -} MAGNETO_ComponentTypeDef; - -/** - * @brief MAGNETO driver extended structure definition - */ -typedef struct -{ - MAGNETO_ComponentTypeDef - id; /* This id must be unique for each component belonging to this class that wants to extend common class */ - void *pData; /* This pointer is specific for each component */ -} MAGNETO_DrvExtTypeDef; - -/** -* @brief MAGNETO driver structure definition -*/ -typedef struct -{ - MAGNETO_StatusTypeDef (*Init)(MAGNETO_InitTypeDef *); - MAGNETO_StatusTypeDef (*Read_M_ID)(uint8_t *); - MAGNETO_StatusTypeDef (*Get_M_Axes)(int32_t *); - MAGNETO_StatusTypeDef (*Get_M_AxesRaw)(int16_t *); - MAGNETO_DrvExtTypeDef *extData; -} MAGNETO_DrvTypeDef; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MAGNETO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/Common/pressure.h b/platform/stm32nucleo-spirit1/drivers/Common/pressure.h deleted file mode 100644 index 5bcd8e099..000000000 --- a/platform/stm32nucleo-spirit1/drivers/Common/pressure.h +++ /dev/null @@ -1,153 +0,0 @@ -/** - ****************************************************************************** - * @file pressure.h - * @author MEMS Application Team - * @version V1.2.0 - * @date 28-January-2015 - * @brief This header file contains the functions prototypes for the - * pressure driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PRESSURE_H -#define __PRESSURE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup PRESSURE - * @{ - */ - -/** @defgroup PRESSURE_Exported_Types - * @{ - */ - -/** - * @brief PRESSURE init structure definition - */ -typedef struct -{ - uint8_t OutputDataRate; - uint8_t PressureResolution; - uint8_t TemperatureResolution; - uint8_t DiffEnable; - uint8_t BlockDataUpdate; - uint8_t SPIMode; -} PRESSURE_InitTypeDef; - -/** - * @brief PRESSURE status enumerator definition - */ -typedef enum -{ - PRESSURE_OK = 0, - PRESSURE_ERROR = 1, - PRESSURE_TIMEOUT = 2, - PRESSURE_NOT_IMPLEMENTED = 3 -} PRESSURE_StatusTypeDef; - -/** - * @brief PRESSURE component id enumerator definition - */ -typedef enum -{ - PRESSURE_NONE_COMPONENT = 0, - PRESSURE_LPS25H_COMPONENT = 1, - PRESSURE_LPS25HB_DIL24_COMPONENT = 2 -} PRESSURE_ComponentTypeDef; - -/** - * @brief PRESSURE driver extended structure definition - */ -typedef struct -{ - PRESSURE_ComponentTypeDef - id; /* This id must be unique for each component belonging to this class that wants to extend common class */ - void *pData; /* This pointer is specific for each component */ -} PRESSURE_DrvExtTypeDef; - -/** - * @brief PRESSURE driver structure definition - */ -typedef struct -{ - PRESSURE_StatusTypeDef (*Init)(PRESSURE_InitTypeDef *); - PRESSURE_StatusTypeDef (*PowerOff)(void); - PRESSURE_StatusTypeDef (*ReadID)(uint8_t *); - PRESSURE_StatusTypeDef (*Reset)(void); - void (*ConfigIT)(uint16_t); - void (*EnableIT)(uint8_t); - void (*DisableIT)(uint8_t); - uint8_t (*ITStatus)(uint16_t, uint16_t); - void (*ClearIT)(uint16_t, uint16_t); - PRESSURE_StatusTypeDef (*GetPressure)(float *); - PRESSURE_StatusTypeDef (*GetTemperature)(float *); - void (*SlaveAddrRemap)(uint8_t); - PRESSURE_DrvExtTypeDef *extData; -} PRESSURE_DrvTypeDef; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PRESSURE_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/Release_Notes.html deleted file mode 100644 index f2cac615b..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/Release_Notes.html +++ /dev/null @@ -1,191 +0,0 @@ - - - - - -Release Notes for STM32 BlueEnergy Library - - - - - -
-


-

-
- - - - - - -
- - - - - - - - - -
-

Back to Release page

-
-

Release Notes for HTS221 component

-

Copyright -2015 STMicroelectronics

-

-
-

 

- - - - - - -
- - -

Update History

- - -

V1.2.0 -/ 11-February-2015

-

Main -Changes

- - - - - - - - - -
    -
  • Add extended features support for the Component -
    • -
- -

V1.1.0 -/ 12-December-2014

-

Main -Changes

- - - - - - - - - -
    -
  • Add error control in the Component API -
    • -
- -

V1.0.0 -/ 10-September-2014

-

Main -Changes

- - - - - - - - - -
    -
  • First -official release
    • -
- - -

License
-

- - -Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

- - -
- http://www.st.com/software_license_agreement_liberty_v2


- -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - - - - - -

- -
-
-

For -complete documentation on STM32 STM BlueNRG -visit www.st.com/BlueNRG

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.c b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.c deleted file mode 100644 index 9d084c066..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.c +++ /dev/null @@ -1,503 +0,0 @@ -/** - ****************************************************************************** - * @file hts221.c - * @author MEMS Application Team - * @version V1.2.0 - * @date 11-February-2015 - * @brief This file provides a set of functions needed to manage the hts221. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "hts221.h" -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup HTS221 - * @{ - */ - -static HUM_TEMP_StatusTypeDef HTS221_Init(HUM_TEMP_InitTypeDef *HTS221_Init); -static HUM_TEMP_StatusTypeDef HTS221_Power_OFF(void); -static HUM_TEMP_StatusTypeDef HTS221_ReadID(uint8_t *ht_id); -static HUM_TEMP_StatusTypeDef HTS221_RebootCmd(void); -static HUM_TEMP_StatusTypeDef HTS221_GetHumidity(float* pfData); -static HUM_TEMP_StatusTypeDef HTS221_GetTemperature(float* pfData); - -/** @defgroup HTS221_Private_Variables HTS221_Private_Variables - * @{ - */ - -HUM_TEMP_DrvTypeDef Hts221Drv = -{ - HTS221_Init, - HTS221_Power_OFF, - HTS221_ReadID, - HTS221_RebootCmd, - 0, - 0, - 0, - 0, - 0, - HTS221_GetHumidity, - HTS221_GetTemperature, - NULL -}; - -/* ------------------------------------------------------- */ -/* Here you should declare the variable that implements */ -/* the internal struct of extended features of HTS221. */ -/* Then you must update the NULL pointer in the variable */ -/* of the extended features below. */ -/* See the example of LSM6DS3 in lsm6ds3.c */ -/* ------------------------------------------------------- */ - -HUM_TEMP_DrvExtTypeDef Hts221Drv_ext = -{ - HUM_TEMP_HTS221_COMPONENT, /* unique ID for HTS221 in the humidity and temperature driver class */ - NULL /* pointer to internal struct of extended features of HTS221 */ -}; - - -/* Temperature in degree for calibration */ -float T0_degC, T1_degC; - -/* Output temperature value for calibration */ -int16_t T0_out, T1_out; - - -/* Humidity for calibration */ -float H0_rh, H1_rh; - -/* Output Humidity value for calibration */ -int16_t H0_T0_out, H1_T0_out; - -/** - * @} - */ - -static HUM_TEMP_StatusTypeDef HTS221_Power_On(void); -static HUM_TEMP_StatusTypeDef HTS221_Calibration(void); - -/** @defgroup HTS221_Private_Functions HTS221_Private_Functions - * @{ - */ - -/** - * @brief HTS221 Calibration procedure - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_Calibration(void) -{ - /* Temperature Calibration */ - /* Temperature in degree for calibration ( "/8" to obtain float) */ - uint16_t T0_degC_x8_L, T0_degC_x8_H, T1_degC_x8_L, T1_degC_x8_H; - uint8_t H0_rh_x2, H1_rh_x2; - uint8_t tempReg[2] = {0, 0}; - - if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T0_degC_X8_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - T0_degC_x8_L = (uint16_t)tempReg[0]; - - if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T1_T0_MSB_X8_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - T0_degC_x8_H = (uint16_t) (tempReg[0] & 0x03); - T0_degC = ((float)((T0_degC_x8_H << 8) | (T0_degC_x8_L))) / 8; - - if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T1_degC_X8_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - T1_degC_x8_L = (uint16_t)tempReg[0]; - - if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, HTS221_T1_T0_MSB_X8_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - T1_degC_x8_H = (uint16_t) (tempReg[0] & 0x0C); - T1_degC_x8_H = T1_degC_x8_H >> 2; - T1_degC = ((float)((T1_degC_x8_H << 8) | (T1_degC_x8_L))) / 8; - - if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, (HTS221_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), 2) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(HTS221_IO_Read(tempReg, HTS221_ADDRESS, (HTS221_T1_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), 2) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - T1_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - /* Humidity Calibration */ - /* Humidity in degree for calibration ( "/2" to obtain float) */ - - if(HTS221_IO_Read(&H0_rh_x2, HTS221_ADDRESS, HTS221_H0_RH_X2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - if(HTS221_IO_Read(&H1_rh_x2, HTS221_ADDRESS, HTS221_H1_RH_X2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_H0_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), - 2) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - H0_T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_H1_T0_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), - 2) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - H1_T0_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - H0_rh = ((float)H0_rh_x2) / 2; - H1_rh = ((float)H1_rh_x2) / 2; - - return HUM_TEMP_OK; -} - - -/** - * @brief Set HTS221 Initialization - * @param HTS221_Init the configuration setting for the HTS221 - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_Init(HUM_TEMP_InitTypeDef *HTS221_Init) -{ - uint8_t tmp = 0x00; - - /* Configure the low level interface ---------------------------------------*/ - if(HTS221_IO_Init() != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - if(HTS221_Power_On() != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - if(HTS221_Calibration() != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Output Data Rate selection */ - tmp &= ~(HTS221_ODR_MASK); - tmp |= HTS221_Init->OutputDataRate; - - if(HTS221_IO_Write(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - HTS221_IO_ITConfig(); - - return HUM_TEMP_OK; -} - -/** - * @brief Read ID address of HTS221 - * @param ht_id the pointer where the ID of the device is stored - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_ReadID(uint8_t *ht_id) -{ - if(!ht_id) - { - return HUM_TEMP_ERROR; - } - - return HTS221_IO_Read(ht_id, HTS221_ADDRESS, HTS221_WHO_AM_I_ADDR, 1); -} - -/** - * @brief Reboot memory content of HTS221 - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_RebootCmd(void) -{ - uint8_t tmpreg; - - /* Read CTRL_REG2 register */ - if(HTS221_IO_Read(&tmpreg, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Enable or Disable the reboot memory */ - tmpreg |= HTS221_BOOT_REBOOTMEMORY; - - /* Write value to MEMS CTRL_REG2 regsister */ - if(HTS221_IO_Write(&tmpreg, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - return HUM_TEMP_OK; -} - - -/** - * @brief Read HTS221 output register, and calculate the humidity - * @param pfData the pointer to data output - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_GetHumidity(float* pfData) -{ - int16_t H_T_out, humidity_t; - uint8_t tempReg[2] = {0, 0}; - uint8_t tmp = 0x00; - float H_rh; - - if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Output Data Rate selection */ - tmp &= (HTS221_ODR_MASK); - - if(tmp == 0x00) - { - if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Serial Interface Mode selection */ - tmp &= ~(HTS221_ONE_SHOT_MASK); - tmp |= HTS221_ONE_SHOT_START; - - if(HTS221_IO_Write(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - do - { - - if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_STATUS_REG_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - } - while(!(tmp && 0x02)); - } - - - if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_HUMIDITY_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), - 2) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - H_T_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - H_rh = ( float )(((( H_T_out - H0_T0_out ) * ( H1_rh - H0_rh )) / ( H1_T0_out - H0_T0_out )) + H0_rh ); - - // Truncate to specific number of decimal digits - humidity_t = (uint16_t)(H_rh * pow(10, HUM_DECIMAL_DIGITS)); - *pfData = ((float)humidity_t) / pow(10, HUM_DECIMAL_DIGITS); - - // Prevent data going below 0% and above 100% due to linear interpolation - if ( *pfData < 0.0f ) *pfData = 0.0f; - if ( *pfData > 100.0f ) *pfData = 100.0f; - - return HUM_TEMP_OK; -} - -/** - * @brief Read HTS221 output register, and calculate the temperature - * @param pfData the pointer to data output - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_GetTemperature(float* pfData) -{ - int16_t T_out, temperature_t; - uint8_t tempReg[2] = {0, 0}; - uint8_t tmp = 0x00; - float T_degC; - - if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Output Data Rate selection */ - tmp &= (HTS221_ODR_MASK); - - if(tmp == 0x00) - { - if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Serial Interface Mode selection */ - tmp &= ~(HTS221_ONE_SHOT_MASK); - tmp |= HTS221_ONE_SHOT_START; - - if(HTS221_IO_Write(&tmp, HTS221_ADDRESS, HTS221_CTRL_REG2_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - do - { - - if(HTS221_IO_Read(&tmp, HTS221_ADDRESS, HTS221_STATUS_REG_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - } - while(!(tmp && 0x01)); - } - - if(HTS221_IO_Read(&tempReg[0], HTS221_ADDRESS, (HTS221_TEMP_OUT_L_ADDR | HTS221_I2C_MULTIPLEBYTE_CMD), - 2) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - T_out = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - T_degC = ((float)(T_out - T0_out)) / (T1_out - T0_out) * (T1_degC - T0_degC) + T0_degC; - - temperature_t = (int16_t)(T_degC * pow(10, TEMP_DECIMAL_DIGITS)); - - *pfData = ((float)temperature_t) / pow(10, TEMP_DECIMAL_DIGITS); - - return HUM_TEMP_OK; -} - - -/** - * @brief Exit the shutdown mode for HTS221 - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_Power_On(void) -{ - uint8_t tmpReg; - - /* Read the register content */ - if(HTS221_IO_Read(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Set the power down bit */ - tmpReg |= HTS221_MODE_ACTIVE; - - /* Write register */ - if(HTS221_IO_Write(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - return HUM_TEMP_OK; -} - -/** - * @brief Enter the shutdown mode for HTS221 - * @retval HUM_TEMP_OK in case of success, an error code otherwise - */ -static HUM_TEMP_StatusTypeDef HTS221_Power_OFF(void) -{ - uint8_t tmpReg; - - /* Read the register content */ - if(HTS221_IO_Read(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - /* Reset the power down bit */ - tmpReg &= ~(HTS221_MODE_ACTIVE); - - /* Write register */ - if(HTS221_IO_Write(&tmpReg, HTS221_ADDRESS, HTS221_CTRL_REG1_ADDR, 1) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - return HUM_TEMP_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.h b/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.h deleted file mode 100644 index 3dfd16109..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/hts221/hts221.h +++ /dev/null @@ -1,599 +0,0 @@ -/** - ****************************************************************************** - * @file hts221.h - * @author MEMS Application Team - * @version V1.2.0 - * @date 11-February-2015 - * @brief This file contains definitions for the hts221.c - * firmware driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __HTS221_H -#define __HTS221_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "hum_temp.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup HTS221 - * @{ - */ - -/** @defgroup HTS221_Exported_Defines HTS221_Exported_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif - -/** - * @brief Device Address - */ -#define HTS221_ADDRESS 0xBE - -/******************************************************************************/ -/*************************** START REGISTER MAPPING **************************/ -/******************************************************************************/ - - -/** - * @brief Device identification register. - * \code - * Read - * Default value: 0xBC - * 7:0 This read-only register contains the device identifier that, for HTS221, is set to BCh. - * \endcode -*/ -#define HTS221_WHO_AM_I_ADDR 0x0F - - -/** - * @brief Humidity resolution Register - * \code - * Read/write - * Default value: 0x1B - * 7:6 RFU - * 5:3 AVGT2-AVGT0: Temperature internal average. - * AVGT2 | AVGT1 | AVGT0 | Nr. Internal Average - * ------------------------------------------------------ - * 0 | 0 | 0 | 2 - * 0 | 0 | 1 | 4 - * 0 | 1 | 0 | 8 - * 0 | 1 | 1 | 16 - * 1 | 0 | 0 | 32 - * 1 | 0 | 1 | 64 - * 1 | 1 | 0 | 128 - * 1 | 1 | 1 | 256 - * - * 2:0 AVGH2-AVGH0: Humidity internal average. - * AVGH2 | AVGH1 | AVGH0 | Nr. Internal Average - * ------------------------------------------------------ - * 0 | 0 | 0 | 4 - * 0 | 0 | 1 | 8 - * 0 | 1 | 0 | 16 - * 0 | 1 | 1 | 32 - * 1 | 0 | 0 | 64 - * 1 | 0 | 1 | 128 - * 1 | 1 | 0 | 256 - * 1 | 1 | 1 | 512 - * - * \endcode - */ -#define HTS221_RES_CONF_ADDR 0x10 - - -/** -* @brief INFO Register (LSB data) -* \code -* Read/write -* Default value: 0x00 -* 7:0 INFO7-INFO0: Lower part of the INFO reference -* used for traceability of the sample. -* \endcode -*/ -#define HTS221_INFO_L_ADDR 0x1E - - -/** -* @brief INFO & Calibration Version Register (LSB data) -* \code -* Read/write -* Default value: 0x00 -* 7:6 CALVER1:CALVER0 -* 5:0 INFO13-INFO8: Higher part of the INFO reference -* used for traceability of the sample. -* \endcode -*/ -#define HTS221_INFO_H_ADDR 0x1F - - -/** -* @brief Humidity sensor control register 1 -* \code -* Read/write -* Default value: 0x00 -* 7 PD: power down control. 0 - disable; 1 - enable -* 6:3 RFU -* 2 BDU: block data update. 0 - disable; 1 - enable -* 1:0 RFU -* \endcode -*/ - -#define HTS221_CTRL_REG1_ADDR 0x20 - - -/** -* @brief Humidity sensor control register 2 -* \code -* Read/write -* Default value: 0x00 -* 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content -* 6:3 Reserved. -* 2 Reserved. -* 1 Reserved. -* 0 ONE_SHOT: One shot enable. 0: waiting for start of conversion; 1: start for a new dataset -* \endcode -*/ -#define HTS221_CTRL_REG2_ADDR 0x21 - - -/** -* @brief Humidity sensor control register 3 -* \code -* Read/write -* Default value: 0x00 -* [7] DRDY_H_L: Data Ready output signal active high, low (0: active high -default;1: active low) -* [6] PP_OD: Push-pull / Open Drain selection on pin 3 (DRDY) (0: push-pull - default; 1: open drain) -* [5:3] Reserved -* [2] DRDY_EN: Data Ready enable (0: Data Ready disabled - default;1: Data Ready signal available on pin 3) -* [1:0] Reserved -* \endcode -*/ -#define HTS221_CTRL_REG3_ADDR 0x22 - - -/** -* @brief Status Register -* \code -* Read -* Default value: 0x00 -* 7:2 RFU -* 1 H_DA: Humidity data available. 0: new data for Humidity is not yet available; 1: new data for Humidity is available. -* 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. -* \endcode -*/ -#define HTS221_STATUS_REG_ADDR 0x27 - - -/** -* @brief Humidity data (LSB). -* \code -* Read -* Default value: 0x00. -* POUT7 - POUT0: Humidity data LSB (2's complement) => signed 16 bits -* RAW Humidity output data: Hout(%)=(HUMIDITY_OUT_H & HUMIDITY_OUT_L). -* \endcode -*/ -#define HTS221_HUMIDITY_OUT_L_ADDR 0x28 - - -/** -* @brief Humidity data (MSB). -* \code -* Read -* Default value: 0x00. -* POUT7 - POUT0: Humidity data LSB (2's complement) => signed 16 bits -* RAW Humidity output data: Hout(%)=(HUMIDITY_OUT_H & HUMIDITY_OUT_L). -* \endcode -*/ -#define HTS221_HUMIDITY_OUT_H_ADDR 0x29 - - -/** -* @brief Temperature data (LSB). -* \code -* Read -* Default value: 0x00. -* TOUT7 - TOUT0: temperature data LSB (2's complement) => signed 16 bits -* RAW Temperature output data: Tout (LSB)=(TEMP_OUT_H & TEMP_OUT_L). -* \endcode -*/ -#define HTS221_TEMP_OUT_L_ADDR 0x2A - - -/** -* @brief Temperature data (MSB). -* \code -* Read -* Default value: 0x00. -* TOUT15 - TOUT8: temperature data MSB (2's complement) => signed 16 bits -* RAW Temperature output data: Tout (LSB)=(TEMP_OUT_H & TEMP_OUT_L). -* \endcode -*/ -#define HTS221_TEMP_OUT_H_ADDR 0x2B - - -/** -*@brief Humidity 0 Register in %RH with sensitivity=2 -*\code -* Read -* Value: (Unsigned 8 Bit)/2 -*\endcode -*/ -#define HTS221_H0_RH_X2_ADDR 0x30 - - -/** -*@brief Humidity 1 Register in %RH with sensitivity=2 -*\code -* Read -* Value: (Unsigned 8 Bit)/2 -*\endcode -*/ -#define HTS221_H1_RH_X2_ADDR 0x31 - - -/** -*@brief Temperature 0 Register in deg with sensitivity=8 -*\code -* Read -* Value: (Unsigned 16 Bit)/2 -*\endcode -*/ -#define HTS221_T0_degC_X8_ADDR 0x32 - - -/** -*@brief Temperature 1 Register in deg with sensitivity=8 -*\code -* Read -* Value: (Unsigned 16 Bit)/2 -*\endcode -*/ -#define HTS221_T1_degC_X8_ADDR 0x33 - - -/** -*@brief Temperature 1/0 MSB Register in deg with sensitivity=8 -*\code -* Read -* Value: (Unsigned 16 Bit)/2 -* 3:2 T1(9):T1(8) MSB T1_degC_X8 bits -* 1:0 T0(9):T0(8) MSB T0_degC_X8 bits -*\endcode -*/ -#define HTS221_T1_T0_MSB_X8_ADDR 0x35 - - -/** -*@brief Humidity LOW CALIBRATION Register -*\code -* Read -* Default value: 0x00. -* H0_T0_TOUT7 - H0_T0_TOUT0: HUMIDITY data lSB (2's complement) => signed 16 bits -*\endcode -*/ -#define HTS221_H0_T0_OUT_L_ADDR 0x36 - - -/** -*@brief Humidity LOW CALIBRATION Register -*\code -* Read -* Default value: 0x00. -* H0_T0_TOUT15 - H0_T0_TOUT8: HUMIDITY data mSB (2's complement) => signed 16 bits -*\endcode -*/ -#define HTS221_H0_T0_OUT_H_ADDR 0x37 - - -/** -*@brief Humidity HIGH CALIBRATION Register -*\code -* Read -* Default value: 0x00. -* H1_T0_TOUT7 - H1_T0_TOUT0: HUMIDITY data lSB (2's complement) => signed 16 bits -*\endcode -*/ -#define HTS221_H1_T0_OUT_L_ADDR 0x3A - - -/** -*@brief Humidity HIGH CALIBRATION Register -*\code -* Read -* Default value: 0x00. -* H1_T0_TOUT15 - H1_T0_TOUT8: HUMIDITY data mSB (2's complement) => signed 16 bits -*\endcode -*/ -#define HTS221_H1_T0_OUT_H_ADDR 0x3B - - -/** -* @brief Low Calibration Temperature Register (LSB). -* \code -* Read -* Default value: 0x00. -* T0_OUT7 - T0_OUT0: temperature data LSB (2's complement) => signed 16 bits -* RAW LOW Calibration data: T0_OUT (LSB)=(T0_OUT_H & T0_OUT_L). -* \endcode -*/ -#define HTS221_T0_OUT_L_ADDR 0x3C - - -/** -* @brief Low Calibration Temperature Register (MSB) -* \code -* Read -* Default value: 0x00. -* T0_OUT15 - T0_OUT8: temperature data MSB (2's complement) => signed 16 bits -* RAW LOW Calibration data: T0_OUT (LSB)=(T0_OUT_H & T0_OUT_L). -* \endcode -*/ -#define HTS221_T0_OUT_H_ADDR 0x3D - - -/** -* @brief Low Calibration Temperature Register (LSB). -* \code -* Read -* Default value: 0x00. -* T1_OUT7 - T1_OUT0: temperature data LSB (2's complement) => signed 16 bits -* RAW LOW Calibration data: T1_OUT (LSB)=(T1_OUT_H & T1_OUT_L). -* \endcode -*/ -#define HTS221_T1_OUT_L_ADDR 0x3E - - -/** -* @brief Low Calibration Temperature Register (MSB) -* \code -* Read -* Default value: 0x00. -* T1_OUT15 - T1_OUT8: temperature data MSB (2's complement) => signed 16 bits -* RAW LOW Calibration data: T1_OUT (LSB)=(T1_OUT_H & T1_OUT_L). -* \endcode -*/ -#define HTS221_T1_OUT_H_ADDR 0x3F - - -/******************************************************************************/ -/**************************** END REGISTER MAPPING ***************************/ -/******************************************************************************/ - -/** - * @brief Multiple Byte. Mask for enabling multiple byte read/write command. - */ -#define HTS221_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) - -/** - * @brief Device Identifier. Default value of the WHO_AM_I register. - */ -#define I_AM_HTS221 ((uint8_t)0xBC) - - -/** @defgroup HTS221_Power_Mode_Selection_CTRL_REG1 HTS221_Power_Mode_Selection_CTRL_REG1 - * @{ - */ -#define HTS221_MODE_POWERDOWN ((uint8_t)0x00) -#define HTS221_MODE_ACTIVE ((uint8_t)0x80) - -#define HTS221_MODE_MASK ((uint8_t)0x80) -/** - * @} - */ - - -/** @defgroup HTS221_Block_Data_Update_Mode_Selection_CTRL_REG1 HTS221_Block_Data_Update_Mode_Selection_CTRL_REG1 - * @{ - */ -#define HTS221_BDU_CONTINUOUS ((uint8_t)0x00) -#define HTS221_BDU_NOT_UNTIL_READING ((uint8_t)0x04) - -#define HTS221_BDU_MASK ((uint8_t)0x04) -/** - * @} - */ - -/** @defgroup HTS221_Output_Data_Rate_Selection_CTRL_REG1 HTS221_Output_Data_Rate_Selection_CTRL_REG1 - * @{ - */ -#define HTS221_ODR_ONE_SHOT ((uint8_t)0x00) /*!< Output Data Rate: H - one shot, T - one shot */ -#define HTS221_ODR_1Hz ((uint8_t)0x01) /*!< Output Data Rate: H - 1Hz, T - 1Hz */ -#define HTS221_ODR_7Hz ((uint8_t)0x02) /*!< Output Data Rate: H - 7Hz, T - 7Hz */ -#define HTS221_ODR_12_5Hz ((uint8_t)0x03) /*!< Output Data Rate: H - 12.5Hz, T - 12.5Hz */ - -#define HTS221_ODR_MASK ((uint8_t)0x03) -/** -* @} -*/ - - -/** @defgroup HTS221_Boot_Mode_Selection_CTRL_REG2 HTS221_Boot_Mode_Selection_CTRL_REG2 - * @{ - */ -#define HTS221_BOOT_NORMALMODE ((uint8_t)0x00) -#define HTS221_BOOT_REBOOTMEMORY ((uint8_t)0x80) - -#define HTS221_BOOT_MASK ((uint8_t)0x80) -/** - * @} - */ - - -/** @defgroup HTS221_One_Shot_Selection_CTRL_REG2 HTS221_One_Shot_Selection_CTRL_REG2 - * @{ - */ -#define HTS221_ONE_SHOT_START ((uint8_t)0x01) - -#define HTS221_ONE_SHOT_MASK ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup HTS221_PushPull_OpenDrain_Selection_CTRL_REG3 HTS221_PushPull_OpenDrain_Selection_CTRL_REG3 - * @{ - */ -#define HTS221_PP_OD_PUSH_PULL ((uint8_t)0x00) -#define HTS221_PP_OD_OPEN_DRAIN ((uint8_t)0x40) - -#define HTS221_PP_OD_MASK ((uint8_t)0x40) -/** - * @} - */ - - -/** @defgroup HTS221_Data_Ready_Selection_CTRL_REG3 HTS221_Data_Ready_Selection_CTRL_REG3 - * @{ - */ -#define HTS221_DRDY_DISABLE ((uint8_t)0x00) -#define HTS221_DRDY_AVAILABLE ((uint8_t)0x04) - -#define HTS221_DRDY_MASK ((uint8_t)0x04) -/** - * @} - */ - - -/** @defgroup HTS221_Humidity_Resolution_Selection_RES_CONF HTS221_Humidity_Resolution_Selection_RES_CONF - * @{ - */ -#define HTS221_H_RES_AVG_4 ((uint8_t)0x00) -#define HTS221_H_RES_AVG_8 ((uint8_t)0x01) -#define HTS221_H_RES_AVG_16 ((uint8_t)0x02) -#define HTS221_H_RES_AVG_32 ((uint8_t)0x03) -#define HTS221_H_RES_AVG_64 ((uint8_t)0x04) -#define HTS221_H_RES_AVG_128 ((uint8_t)0x05) - -#define HTS221_H_RES_MASK ((uint8_t)0x07) -/** - * @} - */ - - -/** @defgroup HTS221_Temperature_Resolution_Selection_RES_CONF HTS221_Temperature_Resolution_Selection_RES_CONF - * @{ - */ -#define HTS221_T_RES_AVG_2 ((uint8_t)0x00) -#define HTS221_T_RES_AVG_4 ((uint8_t)0x08) -#define HTS221_T_RES_AVG_8 ((uint8_t)0x10) -#define HTS221_T_RES_AVG_16 ((uint8_t)0x18) -#define HTS221_T_RES_AVG_32 ((uint8_t)0x20) -#define HTS221_T_RES_AVG_64 ((uint8_t)0x28) - -#define HTS221_T_RES_MASK ((uint8_t)0x38) -/** - * @} - */ - - -/** @defgroup HTS221_Temperature_Humidity_Data_Available_STATUS_REG HTS221_Temperature_Humidity_Data_Available_STATUS_REG - * @{ - */ -#define HTS221_H_DATA_AVAILABLE_MASK ((uint8_t)0x02) -#define HTS221_T_DATA_AVAILABLE_MASK ((uint8_t)0x01) -/** - * @} - */ - -/* Data resolution */ -#define HUM_DECIMAL_DIGITS (2) -#define TEMP_DECIMAL_DIGITS (2) - -/** - * @} - */ - - -/** @defgroup HTS221_Imported_Functions HTS221_Imported_Functions - * @{ - */ -/* HUM_TEMP sensor IO functions */ -extern HUM_TEMP_StatusTypeDef HTS221_IO_Init(void); -extern HUM_TEMP_StatusTypeDef HTS221_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToWrite); -extern HUM_TEMP_StatusTypeDef HTS221_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToRead); -extern void HTS221_IO_ITConfig( void ); - -/** - * @} - */ - -/* ------------------------------------------------------- */ -/* Here you should declare the internal struct of */ -/* extended features of HTS221. See the example of */ -/* LSM6DS3 in lsm6ds3.h */ -/* ------------------------------------------------------- */ - -/** @addtogroup HTS221_Exported_Variables HTS221_Exported_Variables - * @{ - */ -/* HUM_TEMP sensor driver structure */ -extern HUM_TEMP_DrvTypeDef Hts221Drv; -extern HUM_TEMP_DrvExtTypeDef Hts221Drv_ext; -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HTS221_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/Release_Notes.html deleted file mode 100644 index 6992e69ea..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/Release_Notes.html +++ /dev/null @@ -1,209 +0,0 @@ - - - - - -Release Notes for STM32 BlueEnergy Library - - - - - -
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Back to Release page

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Release Notes for LIS3MDL component

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Copyright -2015 STMicroelectronics

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Update History

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V1.3.0 -/ 28-May-2015

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Main -Changes

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  • Add LIS3MDL_M_GetAxes API -
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V1.2.0 -/ 11-February-2015

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Main -Changes

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  • Add extended features support for the Component -
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V1.1.0 -/ 12-December-2014

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Main -Changes

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  • Add error control in the Component API -
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V1.0.0 -/ 10-September-2014

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Main -Changes

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  • First -official release
    • -
- - -

License
-

- - -Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

- - -
- http://www.st.com/software_license_agreement_liberty_v2


- -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - - - - - -

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For -complete documentation on STM32 STM BlueNRG -visit www.st.com/BlueNRG

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-
- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.c b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.c deleted file mode 100644 index 00be3ea3d..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.c +++ /dev/null @@ -1,280 +0,0 @@ -/** - ****************************************************************************** - * @file lis3mdl.c - * @author MEMS Application Team - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file provides a set of functions needed to manage the lis3mdl. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "lis3mdl.h" -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LIS3MDL - * @{ - */ - -static MAGNETO_StatusTypeDef LIS3MDL_Init(MAGNETO_InitTypeDef *LIS3MDL_Init); -static MAGNETO_StatusTypeDef LIS3MDL_Read_M_ID(uint8_t *m_id); -static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxes(int32_t *pData); -static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxesRaw(int16_t *pData); - -/** @defgroup LIS3MDL_Private_Variables LIS3MDL_Private_Variables - * @{ - */ -MAGNETO_DrvTypeDef LIS3MDLDrv = -{ - LIS3MDL_Init, - LIS3MDL_Read_M_ID, - LIS3MDL_M_GetAxes, - LIS3MDL_M_GetAxesRaw, - NULL -}; - -/* ------------------------------------------------------- */ -/* Here you should declare the variable that implements */ -/* the internal struct of extended features of LIS3MDL. */ -/* Then you must update the NULL pointer in the variable */ -/* of the extended features below. */ -/* See the example of LSM6DS3 in lsm6ds3.c */ -/* ------------------------------------------------------- */ - -MAGNETO_DrvExtTypeDef LIS3MDLDrv_ext = -{ - MAGNETO_LIS3MDL_COMPONENT, /* unique ID for LIS3MDL in the MAGNETO driver class */ - NULL /* pointer to internal struct of extended features of LIS3MDL */ -}; - -/** - * @} - */ - -/** @defgroup LIS3MDL_Private_Functions LIS3MDL_Private_Functions - * @{ - */ - -/** - * @brief Set LIS3MDL Initialization - * @param LIS3MDL_Init the configuration setting for the LIS3MDL - * @retval MAGNETO_OK in case of success, an error code otherwise - */ -static MAGNETO_StatusTypeDef LIS3MDL_Init(MAGNETO_InitTypeDef *LIS3MDL_Init) -{ - uint8_t tmp1 = 0x00; - - /* Configure the low level interface ---------------------------------------*/ - if(LIS3MDL_IO_Init() != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - /****** Magnetic sensor *******/ - - if(LIS3MDL_IO_Read(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG3_M, 1) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - /* Conversion mode selection */ - tmp1 &= ~(LIS3MDL_M_MD_MASK); - tmp1 |= LIS3MDL_Init->M_OperatingMode; - - if(LIS3MDL_IO_Write(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG3_M, 1) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - if(LIS3MDL_IO_Read(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG1_M, 1) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - /* Output data rate selection */ - tmp1 &= ~(LIS3MDL_M_DO_MASK); - tmp1 |= LIS3MDL_Init->M_OutputDataRate; - - /* X and Y axes Operative mode selection */ - tmp1 &= ~(LIS3MDL_M_OM_MASK); - tmp1 |= LIS3MDL_Init->M_XYOperativeMode; - - if(LIS3MDL_IO_Write(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG1_M, 1) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - if(LIS3MDL_IO_Read(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG2_M, 1) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - /* Full scale selection */ - tmp1 &= ~(LIS3MDL_M_FS_MASK); - tmp1 |= LIS3MDL_Init->M_FullScale; - - if(LIS3MDL_IO_Write(&tmp1, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG2_M, 1) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - /* Configure interrupt lines */ - LIS3MDL_IO_ITConfig(); - - return MAGNETO_OK; - - /******************************/ -} - - -/** - * @brief Read ID of LIS3MDL Magnetic sensor - * @param m_id the pointer where the ID of the device is stored - * @retval MAGNETO_OK in case of success, an error code otherwise - */ -static MAGNETO_StatusTypeDef LIS3MDL_Read_M_ID(uint8_t *m_id) -{ - if(!m_id) - { - return MAGNETO_ERROR; - } - - return LIS3MDL_IO_Read(m_id, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_WHO_AM_I_ADDR, 1); -} - - -/** - * @brief Read raw data from LIS3MDL Magnetic sensor output register - * @param pData the pointer where the magnetometer raw data are stored - * @retval MAGNETO_OK in case of success, an error code otherwise - */ -static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxesRaw(int16_t *pData) -{ - uint8_t tempReg[2] = {0, 0}; - - if(LIS3MDL_IO_Read(&tempReg[0], LIS3MDL_M_MEMS_ADDRESS, (LIS3MDL_M_OUT_X_L_M | LIS3MDL_I2C_MULTIPLEBYTE_CMD), - 2) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LIS3MDL_IO_Read(&tempReg[0], LIS3MDL_M_MEMS_ADDRESS, (LIS3MDL_M_OUT_Y_L_M | LIS3MDL_I2C_MULTIPLEBYTE_CMD), - 2) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LIS3MDL_IO_Read(&tempReg[0], LIS3MDL_M_MEMS_ADDRESS, (LIS3MDL_M_OUT_Z_L_M | LIS3MDL_I2C_MULTIPLEBYTE_CMD), - 2) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - return MAGNETO_OK; -} - - -/** - * @brief Read data from LIS3MDL Magnetic sensor and calculate Magnetic in mgauss - * @param pData the pointer where the magnetometer data are stored - * @retval MAGNETO_OK in case of success, an error code otherwise - */ -static MAGNETO_StatusTypeDef LIS3MDL_M_GetAxes(int32_t *pData) -{ - uint8_t tempReg = 0x00; - int16_t pDataRaw[3]; - float sensitivity = 0; - - if(LIS3MDL_M_GetAxesRaw(pDataRaw) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - if(LIS3MDL_IO_Read(&tempReg, LIS3MDL_M_MEMS_ADDRESS, LIS3MDL_M_CTRL_REG2_M, 1) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - tempReg &= LIS3MDL_M_FS_MASK; - - switch(tempReg) - { - case LIS3MDL_M_FS_4: - sensitivity = 0.14; - break; - case LIS3MDL_M_FS_8: - sensitivity = 0.29; - break; - case LIS3MDL_M_FS_12: - sensitivity = 0.43; - break; - case LIS3MDL_M_FS_16: - sensitivity = 0.58; - break; - } - - pData[0] = (int32_t)(pDataRaw[0] * sensitivity); - pData[1] = (int32_t)(pDataRaw[1] * sensitivity); - pData[2] = (int32_t)(pDataRaw[2] * sensitivity); - - return MAGNETO_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.h b/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.h deleted file mode 100644 index 08096e7f0..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lis3mdl/lis3mdl.h +++ /dev/null @@ -1,455 +0,0 @@ -/** - ****************************************************************************** - * @file lis3mdl.h - * @author MEMS Application Team - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file contains definitions for the lis3mdl.c - * firmware driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __LIS3MDL_H -#define __LIS3MDL_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "magneto.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LIS3MDL - * @{ - */ - -/** @defgroup LIS3MDL_Exported_Defines LIS3MDL_Exported_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif - - -/******************************************************************************/ -/***************** START MAGNETIC SENSOR REGISTER MAPPING ********************/ -/******************************************************************************/ - -/** - * @brief Device identifier register. - * \code - * Read - * Default value: - * 7:0 This read-only register contains the device identifier - * \endcode -*/ -#define LIS3MDL_M_WHO_AM_I_ADDR 0x0F - - -/** - * @brief Magnetic sensor Control Register 1 - * \code - * Read/write - * Default value: 0x10 - * [7] TEMP_COMP: Temperature compensation enable - * [6:5] OM1-0: X and Y axes operative mode selection - * [4:2] DO2-0: Output data rate selection - * [1] This bit must be set to ‘0’ for the correct operation of the device - * [0] ST: Self-test enable - * \endcode - */ -#define LIS3MDL_M_CTRL_REG1_M 0x20 - - -/** - * @brief Magnetic sensor Control Register 2 - * \code - * Read/write - * Default value: 0x00 - * [7] These bits must be set to ‘0’ for the correct operation of the device - * [6:5] FS1-0: Full-scale configuration - * [4] These bits must be set to ‘0’ for the correct operation of the device - * [3] REBOOT: Reboot memory content - * [2] SOFT_RST: Configuration registers and user register reset function - * [1:0] These bits must be set to ‘0’ for the correct operation of the device - * \endcode - */ -#define LIS3MDL_M_CTRL_REG2_M 0x21 - - -/** - * @brief Magnetic sensor Control Register 3 - * \code - * Read/write - * Default value: 0x03 - * [7] I2C_DISABLE: Disable I2C interface - * [6] These bits must be set to ‘0’ for the correct operation of the device - * [5] LP: Low-power mode configuration - * [4:3] These bits must be set to ‘0’ for the correct operation of the device - * [2] SIM: SPI Serial Interface mode selection - * [1:0] MD1-0: Operating mode selection - * \endcode - */ -#define LIS3MDL_M_CTRL_REG3_M 0x22 - - -/** - * @brief Magnetic sensor data (LSB) - * \code - * Read - * \endcode - */ -#define LIS3MDL_M_OUT_X_L_M 0x28 - - -/** - * @brief Magnetic sensor data (MSB) - * \code - * Read - * \endcode - */ -#define LIS3MDL_M_OUT_X_H_M 0x29 - - -/** - * @brief Magnetic sensor data (LSB) - * \code - * Read - * \endcode - */ -#define LIS3MDL_M_OUT_Y_L_M 0x2A - - -/** - * @brief Magnetic sensor data (MSB) - * \code - * Read - * \endcode - */ -#define LIS3MDL_M_OUT_Y_H_M 0x2B - - -/** - * @brief Magnetic sensor data (LSB) - * \code - * Read - * \endcode - */ -#define LIS3MDL_M_OUT_Z_L_M 0x2C - - -/** - * @brief Magnetic sensor data (MSB) - * \code - * Read - * \endcode - */ -#define LIS3MDL_M_OUT_Z_H_M 0x2D - - -/** - * @brief Magnetic sensor Interrupt config register - * \code - * Read/write - * Default value: 0x00 - * [7] XIEN: Enable interrupt generation on X axis - * [6] YIEN: Enable interrupt generation on Y axis - * [5] ZIEN: Enable interrupt generation on Z axis - * [4:3] Must be 0 - * [2] IEA: Interrupt active configuration on INT - * [1] LIR: Latch interrupt request - * [0] IEN: Interrupt enable on INT pin - * \endcode - */ -#define LIS3MDL_M_INT_CFG 0x30 - - -/** - * @brief Magnetic sensor Interrupt source register - * \code - * Read/write - * Default value: 0x00 - * [7] PTH_X: Value on X-axis exceeds the threshold on the positive side - * [6] PTH_Y: Value on Y-axis exceeds the threshold on the positive side - * [5] PTH_Z: Value on Z-axis exceeds the threshold on the positive side - * [4] NTH_X: Value on X-axis exceeds the threshold on the negative side - * [3] NTH_Y: Value on Y-axis exceeds the threshold on the negative side - * [2] NTH_Z: Value on Z-axis exceeds the threshold on the negative side - * [1] MROI: Internal measurement range overflow on magnetic value - * [0] INT: This bit signals when interrupt event occours - * \endcode - */ -#define LIS3MDL_M_INT_SRC 0x31 - - -/** - * @brief Magnetic sensor Interrupt threshold register low - * \code - * Read/write - * Default value: 0x00 - * [7:0] THS7-0: Least 8 significant bits of interrupt threshold - * \endcode - */ -#define LIS3MDL_M_INT_THS_L_M 0x32 - - -/** - * @brief Magnetic sensor Interrupt threshold register high - * \code - * Read/write - * Default value: 0x00 - * [7] Must be 0 - * [6:0] THS14-8: Most 7 significant bits of interrupt threshold - * \endcode - */ -#define LIS3MDL_M_INT_THS_H_M 0x33 - -/******************************************************************************/ -/******************* END MAGNETIC SENSOR REGISTER MAPPING ********************/ -/******************************************************************************/ - -/** - * @brief Multiple Byte. Mask for enabling multiple byte read/write command. - */ -#define LIS3MDL_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) - -/** - * @brief Device Address - */ - -#define LIS3MDL_M_MEMS_ADDRESS 0x3C // SAD[1] = 1 - -/** - * @brief Device Identifier. Default value of the WHO_AM_I register. - */ -#define I_AM_LIS3MDL_M ((uint8_t)0x3D) - - -/*********************************** MAGNETIC SENSOR REGISTERS VALUE ****************************************/ - -/** @defgroup LIS3MDL_M_Temperature_Compensation_Enable_Selection_CTRL_REG1_M LIS3MDL_M_Temperature_Compensation_Enable_Selection_CTRL_REG1_M - * @{ - */ -#define LIS3MDL_M_TEMP_COMP_DISABLE ((uint8_t)0x00) /*!< Temperature compensation: disable */ -#define LIS3MDL_M_TEMP_COMP_ENABLE ((uint8_t)0x80) /*!< Temperature compensation: enable */ - -#define LIS3MDL_M_TEMP_COMP_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_X_And_Y_Axes_Operative_Mode_Selection_CTRL_REG1_M LIS3MDL_M_X_And_Y_Axes_Operative_Mode_Selection_CTRL_REG1_M - * @{ - */ -#define LIS3MDL_M_OM_LP ((uint8_t)0x00) /*!< X and Y axes operative mode: Low-power mode */ -#define LIS3MDL_M_OM_MP ((uint8_t)0x20) /*!< X and Y axes operative mode: Medium-performance mode */ -#define LIS3MDL_M_OM_HP ((uint8_t)0x40) /*!< X and Y axes operative mode: High-performance mode */ -#define LIS3MDL_M_OM_UHP ((uint8_t)0x60) /*!< X and Y axes operative mode: Ultra-high performance mode */ - -#define LIS3MDL_M_OM_MASK ((uint8_t)0x60) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Output_Data_Rate_Selection_CTRL_REG1_M LIS3MDL_M_Output_Data_Rate_Selection_CTRL_REG1_M - * @{ - */ -#define LIS3MDL_M_DO_0_625 ((uint8_t)0x00) /*!< Output data rate selection: 0.625 */ -#define LIS3MDL_M_DO_1_25 ((uint8_t)0x04) /*!< Output data rate selection: 1.25 */ -#define LIS3MDL_M_DO_2_5 ((uint8_t)0x08) /*!< Output data rate selection: 2.5 */ -#define LIS3MDL_M_DO_5 ((uint8_t)0x0C) /*!< Output data rate selection: 5 */ -#define LIS3MDL_M_DO_10 ((uint8_t)0x10) /*!< Output data rate selection: 10 */ -#define LIS3MDL_M_DO_20 ((uint8_t)0x14) /*!< Output data rate selection: 20 */ -#define LIS3MDL_M_DO_40 ((uint8_t)0x18) /*!< Output data rate selection: 40 */ -#define LIS3MDL_M_DO_80 ((uint8_t)0x1C) /*!< Output data rate selection: 80 */ - -#define LIS3MDL_M_DO_MASK ((uint8_t)0x1C) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Self_Test_Enable_Selection_CTRL_REG1_M LIS3MDL_M_Self_Test_Enable_Selection_CTRL_REG1_M - * @{ - */ -#define LIS3MDL_M_ST_DISABLE ((uint8_t)0x00) /*!< Self-test: disable */ -#define LIS3MDL_M_ST_ENABLE ((uint8_t)0x01) /*!< Self-test: enable */ - -#define LIS3MDL_M_ST_MASK ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Full_Scale_Selection_CTRL_REG2_M LIS3MDL_M_Full_Scale_Selection_CTRL_REG2_M - * @{ - */ -#define LIS3MDL_M_FS_4 ((uint8_t)0x00) /*!< Full scale: +-4 guass */ -#define LIS3MDL_M_FS_8 ((uint8_t)0x20) /*!< Full scale: +-8 gauss */ -#define LIS3MDL_M_FS_12 ((uint8_t)0x40) /*!< Full scale: +-12 gauss */ -#define LIS3MDL_M_FS_16 ((uint8_t)0x60) /*!< Full scale: +-16 gauss */ - -#define LIS3MDL_M_FS_MASK ((uint8_t)0x60) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Reboot_Memory_Selection_CTRL_REG2_M LIS3MDL_M_Reboot_Memory_Selection_CTRL_REG2_M - * @{ - */ -#define LIS3MDL_M_REBOOT_NORMAL ((uint8_t)0x00) /*!< Reboot mode: normal mode */ -#define LIS3MDL_M_REBOOT_MEM_CONTENT ((uint8_t)0x08) /*!< Reboot mode: reboot memory content */ - -#define LIS3MDL_M_REBOOT_MASK ((uint8_t)0x08) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Configuration_Registers_And_User_Register_Reset_CTRL_REG2_M LIS3MDL_M_Configuration_Registers_And_User_Register_Reset_CTRL_REG2_M - * @{ - */ -#define LIS3MDL_M_SOFT_RST_DEFAULT ((uint8_t)0x00) /*!< Reset function: default value */ -#define LIS3MDL_M_SOFT_RST_RESET ((uint8_t)0x04) /*!< Reset function: reset operation */ - -#define LIS3MDL_M_SOFT_RST_MASK ((uint8_t)0x04) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Disable_I2C_Interface_Selection_CTRL_REG3_M LIS3MDL_M_Disable_I2C_Interface_Selection_CTRL_REG3_M - * @{ - */ -#define LIS3MDL_M_I2C_ENABLE ((uint8_t)0x00) /*!< I2C interface: enable */ -#define LIS3MDL_M_I2C_DISABLE ((uint8_t)0x80) /*!< I2C interface: disable */ - -#define LIS3MDL_M_I2C_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Low_Power_Mode_Selection_CTRL_REG3_M LIS3MDL_M_Low_Power_Mode_Selection_CTRL_REG3_M - * @{ - */ -#define LIS3MDL_M_LP_ENABLE ((uint8_t)0x00) /*!< Low-power mode: magnetic data rate is configured by - the DO bits in the CTRL_REG1_M */ -#define LIS3MDL_M_LP_DISABLE ((uint8_t)0x20) /*!< Low-power mode: the DO bits is set to 0.625 Hz and the system performs, - for each channel, the minimum number of averages */ - -#define LIS3MDL_M_LP_MASK ((uint8_t)0x20) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_SPI_Serial_Interface_Mode_Selection_CTRL_REG3_M LIS3MDL_M_SPI_Serial_Interface_Mode_Selection_CTRL_REG3_M - * @{ - */ -#define LIS3MDL_M_SPI_R_ENABLE ((uint8_t)0x00) /*!< SPI Serial Interface mode: only write operations enabled */ -#define LIS3MDL_M_SPI_R_DISABLE ((uint8_t)0x40) /*!< SPI Serial Interface mode: read and write operations enable */ - -#define LIS3MDL_M_SPI_R_MASK ((uint8_t)0x40) -/** - * @} - */ - -/** @defgroup LIS3MDL_M_Operating_Mode_Selection_CTRL_REG3_M LIS3MDL_M_Operating_Mode_Selection_CTRL_REG3_M - * @{ - */ -#define LIS3MDL_M_MD_CONTINUOUS ((uint8_t)0x00) /*!< Operating mode: Continuous-conversion mode */ -#define LIS3MDL_M_MD_SINGLE ((uint8_t)0x01) /*!< Operating mode: Single-conversion mode has to be used with sampling frequency from 0.625 Hz to 80 Hz. */ -#define LIS3MDL_M_MD_PD ((uint8_t)0x02) /*!< Operating mode: Power-down mode */ - -#define LIS3MDL_M_MD_MASK ((uint8_t)0x03) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup LIS3MDL_Imported_Functions LIS3MDL_Imported_Functions - * @{ - */ - -/* Magneto sensor IO functions */ -extern MAGNETO_StatusTypeDef LIS3MDL_IO_Init(void); -extern MAGNETO_StatusTypeDef LIS3MDL_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToWrite); -extern MAGNETO_StatusTypeDef LIS3MDL_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToRead); -extern void LIS3MDL_IO_ITConfig( void ); - -/** - * @} - */ - -/* ------------------------------------------------------- */ -/* Here you should declare the internal struct of */ -/* extended features of LSM6DS0. See the example of */ -/* LSM6DS3 in lsm6ds3.h */ -/* ------------------------------------------------------- */ - -/** @addtogroup LIS3MDL_Exported_Variables LIS3MDL_Exported_Variables - * @{ - */ -/* Magneto sensor driver structure */ -extern MAGNETO_DrvTypeDef LIS3MDLDrv; -extern MAGNETO_DrvExtTypeDef LIS3MDLDrv_ext; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LIS3MDL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/Release_Notes.html deleted file mode 100644 index d60d45e68..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/Release_Notes.html +++ /dev/null @@ -1,191 +0,0 @@ - - - - - -Release Notes for STM32 BlueEnergy Library - - - - - -
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Release Notes for LPS25H component

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Copyright -2015 STMicroelectronics

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Update History

- - -

V1.2.0 -/ 11-February-2015

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Main -Changes

- - - - - - - - - -
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  • Add extended features support for the Component -
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V1.1.0 -/ 12-December-2014

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Main -Changes

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  • Add error control in the Component API -
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V1.0.0 -/ 10-September-2014

-

Main -Changes

- - - - - - - - - -
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  • First -official release
    • -
- - -

License
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- - -Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

- - -
- http://www.st.com/software_license_agreement_liberty_v2


- -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - - - - - -

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For -complete documentation on STM32 STM BlueNRG -visit www.st.com/BlueNRG

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-
- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.c b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.c deleted file mode 100644 index d2f1348b6..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.c +++ /dev/null @@ -1,394 +0,0 @@ -/** - ****************************************************************************** - * @file lps25h.c - * @author MEMS Application Team - * @version V1.2.0 - * @date 11-February-2015 - * @brief This file provides a set of functions needed to manage the lps25h. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "lps25h.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LPS25H - * @{ - */ - -static PRESSURE_StatusTypeDef LPS25H_Init(PRESSURE_InitTypeDef *LPS25H_Init); -static PRESSURE_StatusTypeDef LPS25H_ReadID(uint8_t *p_id); -static PRESSURE_StatusTypeDef LPS25H_RebootCmd(void); -static PRESSURE_StatusTypeDef LPS25H_GetPressure(float* pfData); -static PRESSURE_StatusTypeDef LPS25H_GetTemperature(float* pfData); -static PRESSURE_StatusTypeDef LPS25H_PowerOff(void); -static void LPS25H_SlaveAddrRemap(uint8_t SA0_Bit_Status); - -/** @defgroup LPS25H_Private_Variables LPS25H_Private_Variables - * @{ - */ -PRESSURE_DrvTypeDef LPS25HDrv = -{ - LPS25H_Init, - LPS25H_PowerOff, - LPS25H_ReadID, - LPS25H_RebootCmd, - 0, - 0, - 0, - 0, - 0, - LPS25H_GetPressure, - LPS25H_GetTemperature, - LPS25H_SlaveAddrRemap, - NULL -}; - -/* ------------------------------------------------------- */ -/* Here you should declare the variable that implements */ -/* the internal struct of extended features of LPS25H. */ -/* Then you must update the NULL pointer in the variable */ -/* of the extended features below. */ -/* See the example of LSM6DS3 in lsm6ds3.c */ -/* ------------------------------------------------------- */ - -PRESSURE_DrvExtTypeDef LPS25HDrv_ext = -{ - PRESSURE_LPS25H_COMPONENT, /* unique ID for LPS25H in the PRESSURE driver class */ - NULL /* pointer to internal struct of extended features of LPS25H */ -}; - -uint8_t LPS25H_SlaveAddress = LPS25H_ADDRESS_HIGH; - -/** - * @} - */ - -static PRESSURE_StatusTypeDef LPS25H_PowerOn(void); -static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawPressure(int32_t *raw_press); -static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawTemperature(int16_t *raw_data); - -/** @defgroup LPS25H_Private_Functions LPS25H_Private_Functions - * @{ - */ - -/** - * @brief Set LPS25H Initialization - * @param LPS25H_Init the configuration setting for the LPS25H - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_Init(PRESSURE_InitTypeDef *LPS25H_Init) -{ - uint8_t tmp1 = 0x00; - - /* Configure the low level interface ---------------------------------------*/ - if(LPS25H_IO_Init() != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - if(LPS25H_PowerOn() != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - if(LPS25H_IO_Read(&tmp1, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Output Data Rate selection */ - tmp1 &= ~(LPS25H_ODR_MASK); - tmp1 |= LPS25H_Init->OutputDataRate; - - /* Interrupt circuit selection */ - tmp1 &= ~(LPS25H_DIFF_EN_MASK); - tmp1 |= LPS25H_Init->DiffEnable; - - /* Block Data Update selection */ - tmp1 &= ~(LPS25H_BDU_MASK); - tmp1 |= LPS25H_Init->BlockDataUpdate; - - /* Serial Interface Mode selection */ - tmp1 &= ~(LPS25H_SPI_SIM_MASK); - tmp1 |= LPS25H_Init->SPIMode; - - if(LPS25H_IO_Write(&tmp1, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - if(LPS25H_IO_Read(&tmp1, LPS25H_SlaveAddress, LPS25H_RES_CONF_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Serial Interface Mode selection */ - tmp1 &= ~(LPS25H_P_RES_MASK); - tmp1 |= LPS25H_Init->PressureResolution; - - /* Serial Interface Mode selection */ - tmp1 &= ~(LPS25H_T_RES_MASK); - tmp1 |= LPS25H_Init->TemperatureResolution; - - if(LPS25H_IO_Write(&tmp1, LPS25H_SlaveAddress, LPS25H_RES_CONF_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - LPS25H_IO_ITConfig(); - - return PRESSURE_OK; -} - -/** - * @brief Read ID address of LPS25H - * @param ht_id the pointer where the ID of the device is stored - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_ReadID(uint8_t *p_id) -{ - if(!p_id) - { - return PRESSURE_ERROR; - } - - return LPS25H_IO_Read(p_id, LPS25H_SlaveAddress, LPS25H_WHO_AM_I_ADDR, 1); -} - -/** - * @brief Reboot memory content of LPS25H - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_RebootCmd(void) -{ - uint8_t tmpreg; - - /* Read CTRL_REG5 register */ - if(LPS25H_IO_Read(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG2_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Enable or Disable the reboot memory */ - tmpreg |= LPS25H_RESET_MEMORY; - - /* Write value to MEMS CTRL_REG5 regsister */ - if(LPS25H_IO_Write(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG2_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - return PRESSURE_OK; -} - - -/** - * @brief Read LPS25H output register, and calculate the raw pressure - * @param raw_press the pressure raw value - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawPressure(int32_t *raw_press) -{ - uint8_t buffer[3], i; - uint32_t tempVal = 0; - - /* Read the register content */ - - if(LPS25H_IO_Read(buffer, LPS25H_SlaveAddress, (LPS25H_PRESS_POUT_XL_ADDR | LPS25H_I2C_MULTIPLEBYTE_CMD), - 3) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Build the raw data */ - for (i = 0 ; i < 3 ; i++) - tempVal |= (((uint32_t) buffer[i]) << (8 * i)); - - /* convert the 2's complement 24 bit to 2's complement 32 bit */ - if (tempVal & 0x00800000) - tempVal |= 0xFF000000; - - /* return the built value */ - *raw_press = ((int32_t) tempVal); - - return PRESSURE_OK; -} - -/** - * @brief Read LPS25H output register, and calculate the pressure in mbar - * @param pfData the pressure value in mbar - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_GetPressure(float* pfData) -{ - int32_t raw_press = 0; - - if(LPS25H_I2C_ReadRawPressure(&raw_press) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - *pfData = (float)raw_press / 4096.0f; - - return PRESSURE_OK; -} - -/** - * @brief Read LPS25H output register, and calculate the raw temperature - * @param raw_data the temperature raw value - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_I2C_ReadRawTemperature(int16_t *raw_data) -{ - uint8_t buffer[2]; - uint16_t tempVal = 0; - - /* Read the register content */ - if(LPS25H_IO_Read(buffer, LPS25H_SlaveAddress, (LPS25H_TEMP_OUT_L_ADDR | LPS25H_I2C_MULTIPLEBYTE_CMD), - 2) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Build the raw value */ - tempVal = (((uint16_t)buffer[1]) << 8) + (uint16_t)buffer[0]; - - /* Return it */ - *raw_data = ((int16_t)tempVal); - - return PRESSURE_OK; -} - -/** - * @brief Read LPS25H output register, and calculate the temperature - * @param pfData the temperature value - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_GetTemperature(float *pfData) -{ - int16_t raw_data; - - if(LPS25H_I2C_ReadRawTemperature(&raw_data) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - *pfData = (float)((((float)raw_data / 480.0f) + 42.5f)); - - return PRESSURE_OK; -} -/** - * @brief Exit the shutdown mode for LPS25H - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_PowerOn(void) -{ - uint8_t tmpreg; - - /* Read the register content */ - if(LPS25H_IO_Read(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Set the power down bit */ - tmpreg |= LPS25H_MODE_ACTIVE; - - /* Write register */ - if(LPS25H_IO_Write(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - return PRESSURE_OK; -} - - -/** - * @brief Enter the shutdown mode for LPS25H - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25H_PowerOff(void) -{ - uint8_t tmpreg; - - /* Read the register content */ - if(LPS25H_IO_Read(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Reset the power down bit */ - tmpreg &= ~(LPS25H_MODE_ACTIVE); - - /* Write register */ - if(LPS25H_IO_Write(&tmpreg, LPS25H_SlaveAddress, LPS25H_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - return PRESSURE_OK; -} - -/** - * @brief Set the slave address according to SA0 bit - * @param SA0_Bit_Status LPS25H_SA0_LOW or LPS25H_SA0_HIGH - * @retval None - */ -static void LPS25H_SlaveAddrRemap(uint8_t SA0_Bit_Status) -{ - LPS25H_SlaveAddress = (SA0_Bit_Status == LPS25H_SA0_LOW ? LPS25H_ADDRESS_LOW : LPS25H_ADDRESS_HIGH); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.h b/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.h deleted file mode 100644 index 7a9f9f7c7..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lps25h/lps25h.h +++ /dev/null @@ -1,572 +0,0 @@ -/** - ****************************************************************************** - * @file lps25h.h - * @author MEMS Application Team - * @version V1.2.0 - * @date 11-February-2015 - * @brief This file contains definitions for the lps25h.c - * firmware driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __LPS25H_H -#define __LPS25H_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "pressure.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LPS25H - * @{ - */ - -/** @defgroup LPS25H_Exported_Defines LPS25H_Exported_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif - - -/******************************************************************************/ -/*************************** START REGISTER MAPPING **************************/ -/******************************************************************************/ - - -/** - * @brief Reference pressure (LSB data) - * \code - * Read/write - * Default value: 0x00 - * 7:0 REF7-ODR0: Lower part of the reference pressure that - * is sum to the sensor output pressure. - * \endcode - */ -#define LPS25H_REF_P_XL_ADDR 0x08 - -/** - * @brief Reference pressure (middle part) - * \code - * Read/write - * Default value: 0x00 - * 7:0 REF15-ODR8: Middle part of the reference pressure that - * is sum to the sensor output pressure. - * \endcode - */ -#define LPS25H_REF_P_L_ADDR 0x09 - -/** - * @brief Reference pressure (MSB part) - * \code - * Read/write - * Default value: 0x00 - * 7:0 REF15-ODR8: Higher part of the reference pressure that - * is sum to the sensor output pressure. - * \endcode - */ -#define LPS25H_REF_P_H_ADDR 0x0A - -/** - * @brief Device identifier register. - * \code - * Read - * Default value: 0xBD - * 7:0 This read-only register contains the device identifier that, - for LPS25H, is set to 0xCA. - * \endcode - */ -#define LPS25H_WHO_AM_I_ADDR 0x0F - -/** - * @brief Pressure and temperature resolution mode register. - * \code - * Read - * Default value: 0x05 - * [7:4] Reserved - * [3:2] AVGP1-0: select the pressure internal average. - * [1:0] AVGT1-0: select the temperature internal average. - * \endcode - */ -#define LPS25H_RES_CONF_ADDR 0x10 - -/** - * @brief Pressure sensor control register 1 - * \code - * Read/write - * Default value: 0x00 - * 7 PD: power down control. 0 - disable; 1 - enable - * 6:4 ODR2, ODR1, ODR0: output data rate selection. - * ODR2 | ODR1 | ODR0 | Pressure output data-rate(Hz) | Temperature output data-rate(Hz) - * ---------------------------------------------------------------------------------- - * 0 | 0 | 0 | one shot | one shot - * 0 | 0 | 1 | 1 | 1 - * 0 | 1 | 0 | 7 | 7 - * 0 | 1 | 1 | 12.5 | 12.5 - * 1 | 0 | 0 | 25 | 25 - * 1 | 0 | 1 | Reserved | Reserved - * 1 | 1 | 0 | Reserved | Reserved - * 1 | 1 | 1 | Reserved | Reserved - * - * 3 DIFF_EN: Interrupt circuit. 0 - disable; 1 - enable - * 2 BDU: block data update. 0 - disable; 1 - enable - * 1 DELTA_EN: delta pressure. 0 - disable; 1 - enable - * 1 RESET_AZ: reset AutoZero. 0 - disable; 1 - enable ///////ALE REVIEW - * 0 SIM: SPI Serial Interface Mode selection. 0 - SPI 4-wire; 1 - SPI 3-wire ///////ALE REVIEW - * \endcode - */ -#define LPS25H_CTRL_REG1_ADDR 0x20 - -/** - * @brief Pressure sensor control register 2 - * \code - * Read/write - * Default value: 0x00 - * 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content - * 6 FIFO_EN: FIFO. 0: disable; 1: enable - * 5 WTM_EN: FIFO Watermark level use. 0: disable; 1: enable - * 4:3 Reserved. keep these bits at 0 - * 2 SWRESET: Software reset. 0: normal mode; 1: SW reset. - * 1 AUTO_ZERO: Autozero enable. 0: normal mode; 1: autozero enable. - * 0 ONE_SHOT: One shot enable. 0: waiting for start of conversion; 1: start for a new dataset - * \endcode - */ -#define LPS25H_CTRL_REG2_ADDR 0x21 - -/** - * @brief Pressure sensor control register 3 - * \code - * Read/write - * Default value: 0x00 - * 7 INT_H_L: Interrupt. 0:active high; 1: active low. - * 6 PP_OD: Push-Pull/OpenDrain selection on interrupt pads. 0: Push-pull; 1: open drain. - * 5 Reserved - * 4:3 INT2_S2, INT2_S1: INT2 output signal selection control bits. // TO DO - * 1:0 INT1_S2, INT1_S1: data signal on INT1 pad control bits. - * INT1(2)_S2 | INT1(2)_S1 | INT1(2) pin - * ------------------------------------------------------ - * 0 | 0 | Data signal - * 0 | 1 | Pressure high (P_high) - * 1 | 0 | Pressure low (P_low) - * 1 | 1 | P_low OR P_high - - - * \endcode - */ -#define LPS25H_CTRL_REG3_ADDR 0x22 - -/** - * @brief Pressure sensor control register 4 - * \code - * Read/write - * Default value: 0x00 - * 7 P2_EMPTY: Empty Signal on INT2 pin. - * 6 P2_WTM: Watermark Signal on INT2 pin. - * 5 P2_Overrun:Overrun Signal on INT2 pin. - * 4 P2_DRDY: Data Ready Signal on INT2 pin. - * 3 P1_EMPTY: Empty Signal on INT1 pin. - * 2 P1_WTM: Watermark Signal on INT1 pin. - * 1 P1_Overrunn:Overrun Signal on INT1 pin. - * 0 P1_DRDY: Data Ready Signal on INT1 pin. - * \endcode - */ -#define LPS25H_CTRL_REG4_ADDR 0x23 - -/** - * @brief Interrupt configuration Register - * \code - * Read/write - * Default value: 0x00. - * 7:3 Reserved. - * 2 LIR: Latch Interrupt request into INT_SOURCE register. 0 - disable; 1 - enable - * 1 PL_E: Enable interrupt generation on differential pressure low event. 0 - disable; 1 - enable - * 0 PH_E: Enable interrupt generation on differential pressure high event. 0 - disable; 1 - enable - * \endcode - */ -#define LPS25H_INT_CFG_REG_ADDR 0x24 - -/** - * @brief Interrupt source Register - * \code - * Read - * Default value: 0x00. - * 7:3 0. - * 2 IA: Interrupt Active.0: no interrupt has been generated; 1: one or more interrupt events have been generated. - * 1 PL: Differential pressure Low. 0: no interrupt has been generated; 1: Low differential pressure event has occurred. - * 0 PH: Differential pressure High. 0: no interrupt has been generated; 1: High differential pressure event has occurred. - * \endcode - */ -#define LPS25H_INT_SOURCE_REG_ADDR 0x25 - -/** - * @brief Threshold pressure (LSB) - * \code - * Read - * Default value: 0x00. - * 7:0 THS7-THS0: Low part of threshold value for pressure interrupt - * generation. The complete threshold value is given by THS_P_H & THS_P_L and is - * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. - * \endcode - */ -#define LPS25H_THS_P_LOW_REG_ADDR 0x30 - -/** - * @brief Threshold pressure (MSB) - * \code - * Read - * Default value: 0x00. - * 7:0 THS15-THS8: High part of threshold value for pressure interrupt - * generation. The complete threshold value is given by THS_P_H & THS_P_L and is - * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. - * \endcode - */ -#define LPS25H_THS_P_HIGH_REG_ADDR 0x31 - -/** - * @brief Status Register - * \code - * Read - * Default value: 0x00 - * 7:6 0 - * 5 P_OR: Pressure data overrun. 0: no overrun has occurred; 1: new data for pressure has overwritten the previous one. - * 4 T_OR: Temperature data overrun. 0: no overrun has occurred; 1: a new data for temperature has overwritten the previous one. - * 3:2 0 - * 1 P_DA: Pressure data available. 0: new data for pressure is not yet available; 1: new data for pressure is available. - * 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. - * \endcode - */ -#define LPS25H_STATUS_REG_ADDR 0x27 - -/** - * @brief Pressure data (LSB). - * \code - * Read - * Default value: 0x00. - * POUT7 - POUT0: Pressure data LSB (2's complement). - * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & - * PRESS_OUT_XL)[dec]/4096. - * \endcode - */ -#define LPS25H_PRESS_POUT_XL_ADDR 0x28 - -/** - * @brief Pressure data (Middle part). - * \code - * Read - * Default value: 0x80. - * POUT15 - POUT8: Pressure data middle part (2's complement). - * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & - * PRESS_OUT_XL)[dec]/4096. - * \endcode - */ -#define LPS25H_PRESS_OUT_L_ADDR 0x29 - -/** - * @brief Pressure data (MSB). - * \code - * Read - * Default value: 0x2F. - * POUT23 - POUT16: Pressure data MSB (2's complement). - * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & - * PRESS_OUT_XL)[dec]/4096. - * \endcode - */ -#define LPS25H_PRESS_OUT_H_ADDR 0x2A - -/** - * @brief Temperature data (LSB). - * \code - * Read - * Default value: 0x00. - * TOUT7 - TOUT0: temperature data LSB. - * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. - * \endcode - */ -#define LPS25H_TEMP_OUT_L_ADDR 0x2B - -/** - * @brief Temperature data (MSB). - * \code - * Read - * Default value: 0x00. - * TOUT15 - TOUT8: temperature data MSB. - * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. - * \endcode - */ -#define LPS25H_TEMP_OUT_H_ADDR 0x2C - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * 7:5 F_MODE2, F_MODE1, F_MODE0: FIFO mode selection. - * FM2 | FM1 | FM0 | FIFO MODE - * --------------------------------------------------- - * 0 | 0 | 0 | BYPASS MODE - * 0 | 0 | 1 | FIFO MODE. Stops collecting data when full - * 0 | 1 | 0 | STREAM MODE: Keep the newest measurements in the FIFO - * 0 | 1 | 1 | STREAM MODE until trigger deasserted, then change to FIFO MODE - * 1 | 0 | 0 | BYPASS MODE until trigger deasserted, then STREAM MODE - * 1 | 0 | 1 | Reserved - * 1 | 1 | 0 | FIFO_MEAN MODE: Fifo is used to generate a running average filtered pressure - * 1 | 1 | 1 | BYPASS mode until trigger deasserted, then FIFO MODE - * - * 4:0 FIFO Mean Mode Sample size - * WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | Sample Size - * ---------------------------------------------------------------------------------- - * 0 | 0 | 0 | 0 | 1 | 2 - * 0 | 0 | 0 | 1 | 1 | 4 - * 0 | 0 | 1 | 1 | 1 | 8 - * 0 | 1 | 1 | 1 | 1 | 16 - * 1 | 1 | 1 | 1 | 1 | 32 - * other values operation not guaranteed - * \endcode - */ -#define LPS25H_CTRL_FIFO_ADDR 0x2E - -/** - * @brief FIFO Status register - * \code - * Read/write - * Default value: 0x00 - * 7 WTM_FIFO: Watermark status. 0:FIFO filling is lower than watermark level; 1: FIFO is equal or higher than watermark level. - * 6 FULL_FIFO: Overrun bit status. 0 - FIFO not full; 1 -FIFO is full. - * 5 EMPTY_FIFO: Empty FIFO bit. 0 - FIFO not empty; 1 -FIFO is empty. - * 4:0 DIFF_POINT4...0: FIFOsStored data level. - * \endcode - */ -#define LPS25H_STATUS_FIFO_ADDR 0x2F - -/** - * @brief Pressure offset register - * \code - * Read/write - * Default value: 0x00 - * 7:0 RPDS15...8:Pressure Offset for 1 point calibration after soldering. - * \endcode - */ -#define LPS25H_RPDS_TRIM_L_ADDR 0x39 - -/** - * @brief Pressure offset register - * \code - * Read/write - * Default value: 0x00 - * 7:0 RPDS23...16:Pressure Offset for 1 point calibration after soldering. - * \endcode - */ -#define LPS25H_RPDS_TRIM_H_ADDR 0x3A - -/******************************************************************************/ -/**************************** END REGISTER MAPPING ***************************/ -/******************************************************************************/ - -/** - * @brief Multiple Byte. Mask for enabling multiple byte read/write command. - */ -#define LPS25H_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) - -/** - * @brief Device Address - */ -#define LPS25H_ADDRESS_LOW 0xB8 -#define LPS25H_ADDRESS_HIGH 0xBA - - -/** - * @brief Device Identifier. Default value of the WHO_AM_I register. - */ -#define I_AM_LPS25H ((uint8_t)0xBD) - -/** @defgroup LPS25H_Power_Mode_Selection_CTRL_REG1 LPS25H_Power_Mode_Selection_CTRL_REG1 - * @{ - */ -#define LPS25H_MODE_POWERDOWN ((uint8_t)0x00) -#define LPS25H_MODE_ACTIVE ((uint8_t)0x80) - -#define LPS25H_MODE_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup LPS25H_Output_Data_Rate_Selection_CTRL_REG1 LPS25H_Output_Data_Rate_Selection_CTRL_REG1 - * @{ - */ -#define LPS25H_ODR_ONE_SHOT ((uint8_t)0x00) /*!< Output Data Rate: P - one shot, T - one shot */ -#define LPS25H_ODR_1Hz ((uint8_t)0x10) /*!< Output Data Rate: P - 1Hz, T - 1Hz */ -#define LPS25H_ODR_7Hz ((uint8_t)0x20) /*!< Output Data Rate: P - 7Hz, T - 7Hz */ -#define LPS25H_ODR_12_5Hz ((uint8_t)0x30) /*!< Output Data Rate: P - 12.5Hz, T - 12.5Hz */ -#define LPS25H_ODR_25Hz ((uint8_t)0x40) /*!< Output Data Rate: P - 25Hz, T - 25Hz */ - -#define LPS25H_ODR_MASK ((uint8_t)0x70) -/** - * @} - */ - -/** @defgroup LPS25H_Interrupt_Circuit_Enable_CTRL_REG1 LPS25H_Interrupt_Circuit_Enable_CTRL_REG1 - * @{ - */ -#define LPS25H_DIFF_DISABLE ((uint8_t)0x00) /*!< interrupt circuit enabled */ -#define LPS25H_DIFF_ENABLE ((uint8_t)0x08) /*!< interrupt generation disabled */ - -#define LPS25H_DIFF_EN_MASK ((uint8_t)0x08) -/** - * @} - */ - -/** @defgroup LPS25H_Block_Data_Update_CTRL_REG1 LPS25H_Block_Data_Update_CTRL_REG1 - * @{ - */ -#define LPS25H_BDU_CONT ((uint8_t)0x00) /*!< continuous update */ -#define LPS25H_BDU_READ ((uint8_t)0x04) /*!< output registers not updated until MSB and LSB reading */ - -#define LPS25H_BDU_MASK ((uint8_t)0x04) -/** - * @} - */ - -/** @defgroup LPS25H_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 LPS25H_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 - * @{ - */ -#define LPS25H_SPI_SIM_4W ((uint8_t)0x00) /*!< 4-wire interface */ -#define LPS25H_SPI_SIM_3W ((uint8_t)0x01) /*!< 3-wire interface */ - -#define LPS25H_SPI_SIM_MASK ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup LPS25H_Refresh_Registers_Flash_Memory_CTRL_REG2 LPS25H_Refresh_Registers_Flash_Memory_CTRL_REG2 - * @{ - */ -#define LPS25H_NORMAL_MODE ((uint8_t)0x00) -#define LPS25H_RESET_MEMORY ((uint8_t)0x80) - -#define LPS25H_RESET_MEMORY_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup LPS25H_Pressure_Resolution_Selection_RES_CONF LPS25H_Pressure_Resolution_Selection_RES_CONF - * @{ - */ -#define LPS25H_P_RES_AVG_8 ((uint8_t)0x00) -#define LPS25H_P_RES_AVG_32 ((uint8_t)0x01) -#define LPS25H_P_RES_AVG_128 ((uint8_t)0x02) -#define LPS25H_P_RES_AVG_512 ((uint8_t)0x03) - -#define LPS25H_P_RES_MASK ((uint8_t)0x03) -/** - * @} - */ - -/** @defgroup LPS25H_Temperature_Resolution_Selection_RES_CONF LPS25H_Temperature_Resolution_Selection_RES_CONF - * @{ - */ -#define LPS25H_T_RES_AVG_8 ((uint8_t)0x00) -#define LPS25H_T_RES_AVG_16 ((uint8_t)0x04) -#define LPS25H_T_RES_AVG_32 ((uint8_t)0x08) -#define LPS25H_T_RES_AVG_64 ((uint8_t)0x0C) - -#define LPS25H_T_RES_MASK ((uint8_t)0x0C) -/** - * @} - */ - -#define LPS25H_SA0_LOW ((uint8_t)0x00) -#define LPS25H_SA0_HIGH ((uint8_t)0x01) - -/** - * @} - */ - -/** @defgroup LPS25H_Imported_Functions LPS25H_Imported_Functions - * @{ - */ -/* Pressure sensor IO functions */ -extern PRESSURE_StatusTypeDef LPS25H_IO_Init(void); -extern PRESSURE_StatusTypeDef LPS25H_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToWrite); -extern PRESSURE_StatusTypeDef LPS25H_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToRead); -extern void LPS25H_IO_ITConfig( void ); - -/** - * @} - */ - -/* ------------------------------------------------------- */ -/* Here you should declare the internal struct of */ -/* extended features of LPS25H. See the example of */ -/* LSM6DS3 in lsm6ds3.h */ -/* ------------------------------------------------------- */ - -/** @addtogroup LPS25H_Exported_Variables LPS25H_Exported_Variables - * @{ - */ -/* Pressure sensor driver structure */ -extern PRESSURE_DrvTypeDef LPS25HDrv; -extern PRESSURE_DrvExtTypeDef LPS25HDrv_ext; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LPS25H_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/Release_Notes.html deleted file mode 100644 index 7eff65b16..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/Release_Notes.html +++ /dev/null @@ -1,155 +0,0 @@ - - - - - -Release Notes for STM32 BlueEnergy Library - - - - - -
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Release Notes for LPS25HB component

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Copyright -2015 STMicroelectronics

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V1.0.0 -/ 11-February-2015

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- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.c b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.c deleted file mode 100644 index 742ba74c1..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.c +++ /dev/null @@ -1,394 +0,0 @@ -/** - ****************************************************************************** - * @file lps25hb.c - * @author MEMS Application Team - * @version V1.0.0 - * @date 11-February-2015 - * @brief This file provides a set of functions needed to manage the lps25hb. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "lps25hb.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LPS25HB - * @{ - */ - -static PRESSURE_StatusTypeDef LPS25HB_Init(PRESSURE_InitTypeDef *LPS25HB_Init); -static PRESSURE_StatusTypeDef LPS25HB_ReadID(uint8_t *p_id); -static PRESSURE_StatusTypeDef LPS25HB_RebootCmd(void); -static PRESSURE_StatusTypeDef LPS25HB_GetPressure(float* pfData); -static PRESSURE_StatusTypeDef LPS25HB_GetTemperature(float* pfData); -static PRESSURE_StatusTypeDef LPS25HB_PowerOff(void); -static void LPS25HB_SlaveAddrRemap(uint8_t SA0_Bit_Status); - -/** @defgroup LPS25HB_Private_Variables LPS25HB_Private_Variables - * @{ - */ -PRESSURE_DrvTypeDef LPS25HBDrv = -{ - LPS25HB_Init, - LPS25HB_PowerOff, - LPS25HB_ReadID, - LPS25HB_RebootCmd, - 0, - 0, - 0, - 0, - 0, - LPS25HB_GetPressure, - LPS25HB_GetTemperature, - LPS25HB_SlaveAddrRemap, - NULL -}; - -/* ------------------------------------------------------- */ -/* Here you should declare the variable that implements */ -/* the internal struct of extended features of LPS25HB. */ -/* Then you must update the NULL pointer in the variable */ -/* of the extended features below. */ -/* See the example of LSM6DS3 in lsm6ds3.c */ -/* ------------------------------------------------------- */ - -PRESSURE_DrvExtTypeDef LPS25HBDrv_ext = -{ - PRESSURE_LPS25HB_DIL24_COMPONENT, /* unique ID for LPS25HB in the PRESSURE driver class */ - NULL /* pointer to internal struct of extended features of LPS25HB */ -}; - -uint8_t LPS25HB_SlaveAddress = LPS25HB_ADDRESS_LOW; - -/** - * @} - */ - -static PRESSURE_StatusTypeDef LPS25HB_PowerOn(void); -static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawPressure(int32_t *raw_press); -static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawTemperature(int16_t *raw_data); - -/** @defgroup LPS25HB_Private_Functions LPS25HB_Private_Functions - * @{ - */ - -/** - * @brief Set LPS25HB Initialization - * @param LPS25HB_Init the configuration setting for the LPS25HB - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_Init(PRESSURE_InitTypeDef *LPS25HB_Init) -{ - uint8_t tmp1 = 0x00; - - /* Configure the low level interface ---------------------------------------*/ - if(LPS25HB_IO_Init() != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - if(LPS25HB_PowerOn() != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - if(LPS25HB_IO_Read(&tmp1, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Output Data Rate selection */ - tmp1 &= ~(LPS25HB_ODR_MASK); - tmp1 |= LPS25HB_Init->OutputDataRate; - - /* Interrupt circuit selection */ - tmp1 &= ~(LPS25HB_DIFF_EN_MASK); - tmp1 |= LPS25HB_Init->DiffEnable; - - /* Block Data Update selection */ - tmp1 &= ~(LPS25HB_BDU_MASK); - tmp1 |= LPS25HB_Init->BlockDataUpdate; - - /* Serial Interface Mode selection */ - tmp1 &= ~(LPS25HB_SPI_SIM_MASK); - tmp1 |= LPS25HB_Init->SPIMode; - - if(LPS25HB_IO_Write(&tmp1, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - if(LPS25HB_IO_Read(&tmp1, LPS25HB_SlaveAddress, LPS25HB_RES_CONF_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Serial Interface Mode selection */ - tmp1 &= ~(LPS25HB_P_RES_MASK); - tmp1 |= LPS25HB_Init->PressureResolution; - - /* Serial Interface Mode selection */ - tmp1 &= ~(LPS25HB_T_RES_MASK); - tmp1 |= LPS25HB_Init->TemperatureResolution; - - if(LPS25HB_IO_Write(&tmp1, LPS25HB_SlaveAddress, LPS25HB_RES_CONF_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - LPS25HB_IO_ITConfig(); - - return PRESSURE_OK; -} - -/** - * @brief Read ID address of LPS25HB - * @param ht_id the pointer where the ID of the device is stored - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_ReadID(uint8_t *p_id) -{ - if(!p_id) - { - return PRESSURE_ERROR; - } - - return LPS25HB_IO_Read(p_id, LPS25HB_SlaveAddress, LPS25HB_WHO_AM_I_ADDR, 1); -} - -/** - * @brief Reboot memory content of LPS25HB - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_RebootCmd(void) -{ - uint8_t tmpreg; - - /* Read CTRL_REG5 register */ - if(LPS25HB_IO_Read(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG2_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Enable or Disable the reboot memory */ - tmpreg |= LPS25HB_RESET_MEMORY; - - /* Write value to MEMS CTRL_REG5 regsister */ - if(LPS25HB_IO_Write(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG2_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - return PRESSURE_OK; -} - - -/** - * @brief Read LPS25HB output register, and calculate the raw pressure - * @param raw_press the pressure raw value - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawPressure(int32_t *raw_press) -{ - uint8_t buffer[3], i; - uint32_t tempVal = 0; - - /* Read the register content */ - - if(LPS25HB_IO_Read(buffer, LPS25HB_SlaveAddress, (LPS25HB_PRESS_POUT_XL_ADDR | LPS25HB_I2C_MULTIPLEBYTE_CMD), - 3) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Build the raw data */ - for (i = 0 ; i < 3 ; i++) - tempVal |= (((uint32_t) buffer[i]) << (8 * i)); - - /* convert the 2's complement 24 bit to 2's complement 32 bit */ - if (tempVal & 0x00800000) - tempVal |= 0xFF000000; - - /* return the built value */ - *raw_press = ((int32_t) tempVal); - - return PRESSURE_OK; -} - -/** - * @brief Read LPS25HB output register, and calculate the pressure in mbar - * @param pfData the pressure value in mbar - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_GetPressure(float* pfData) -{ - int32_t raw_press = 0; - - if(LPS25HB_I2C_ReadRawPressure(&raw_press) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - *pfData = (float)raw_press / 4096.0f; - - return PRESSURE_OK; -} - -/** - * @brief Read LPS25HB output register, and calculate the raw temperature - * @param raw_data the temperature raw value - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_I2C_ReadRawTemperature(int16_t *raw_data) -{ - uint8_t buffer[2]; - uint16_t tempVal = 0; - - /* Read the register content */ - if(LPS25HB_IO_Read(buffer, LPS25HB_SlaveAddress, (LPS25HB_TEMP_OUT_L_ADDR | LPS25HB_I2C_MULTIPLEBYTE_CMD), - 2) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Build the raw value */ - tempVal = (((uint16_t)buffer[1]) << 8) + (uint16_t)buffer[0]; - - /* Return it */ - *raw_data = ((int16_t)tempVal); - - return PRESSURE_OK; -} - -/** - * @brief Read LPS25HB output register, and calculate the temperature - * @param pfData the temperature value - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_GetTemperature(float *pfData) -{ - int16_t raw_data; - - if(LPS25HB_I2C_ReadRawTemperature(&raw_data) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - *pfData = (float)((((float)raw_data / 480.0f) + 42.5f)); - - return PRESSURE_OK; -} -/** - * @brief Exit the shutdown mode for LPS25HB - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_PowerOn(void) -{ - uint8_t tmpreg; - - /* Read the register content */ - if(LPS25HB_IO_Read(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Set the power down bit */ - tmpreg |= LPS25HB_MODE_ACTIVE; - - /* Write register */ - if(LPS25HB_IO_Write(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - return PRESSURE_OK; -} - - -/** - * @brief Enter the shutdown mode for LPS25HB - * @retval PRESSURE_OK in case of success, an error code otherwise - */ -static PRESSURE_StatusTypeDef LPS25HB_PowerOff(void) -{ - uint8_t tmpreg; - - /* Read the register content */ - if(LPS25HB_IO_Read(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - /* Reset the power down bit */ - tmpreg &= ~(LPS25HB_MODE_ACTIVE); - - /* Write register */ - if(LPS25HB_IO_Write(&tmpreg, LPS25HB_SlaveAddress, LPS25HB_CTRL_REG1_ADDR, 1) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - return PRESSURE_OK; -} - -/** - * @brief Set the slave address according to SA0 bit - * @param SA0_Bit_Status LPS25HB_SA0_LOW or LPS25HB_SA0_HIGH - * @retval None - */ -static void LPS25HB_SlaveAddrRemap(uint8_t SA0_Bit_Status) -{ - LPS25HB_SlaveAddress = (SA0_Bit_Status == LPS25HB_SA0_LOW ? LPS25HB_ADDRESS_LOW : LPS25HB_ADDRESS_HIGH); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.h b/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.h deleted file mode 100644 index d600dc37d..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lps25hb/lps25hb.h +++ /dev/null @@ -1,572 +0,0 @@ -/** - ****************************************************************************** - * @file lps25hb.h - * @author MEMS Application Team - * @version V1.0.0 - * @date 11-February-2015 - * @brief This file contains definitions for the lps25hb.c - * firmware driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __LPS25HB_H -#define __LPS25HB_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "pressure.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LPS25HB - * @{ - */ - -/** @defgroup LPS25HB_Exported_Defines LPS25HB_Exported_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif - - -/******************************************************************************/ -/*************************** START REGISTER MAPPING **************************/ -/******************************************************************************/ - - -/** - * @brief Reference pressure (LSB data) - * \code - * Read/write - * Default value: 0x00 - * 7:0 REF7-ODR0: Lower part of the reference pressure that - * is sum to the sensor output pressure. - * \endcode - */ -#define LPS25HB_REF_P_XL_ADDR 0x08 - -/** - * @brief Reference pressure (middle part) - * \code - * Read/write - * Default value: 0x00 - * 7:0 REF15-ODR8: Middle part of the reference pressure that - * is sum to the sensor output pressure. - * \endcode - */ -#define LPS25HB_REF_P_L_ADDR 0x09 - -/** - * @brief Reference pressure (MSB part) - * \code - * Read/write - * Default value: 0x00 - * 7:0 REF15-ODR8: Higher part of the reference pressure that - * is sum to the sensor output pressure. - * \endcode - */ -#define LPS25HB_REF_P_H_ADDR 0x0A - -/** - * @brief Device identifier register. - * \code - * Read - * Default value: 0xBD - * 7:0 This read-only register contains the device identifier that, - for LPS25HB, is set to 0xCA. - * \endcode - */ -#define LPS25HB_WHO_AM_I_ADDR 0x0F - -/** - * @brief Pressure and temperature resolution mode register. - * \code - * Read - * Default value: 0x05 - * [7:4] Reserved - * [3:2] AVGP1-0: select the pressure internal average. - * [1:0] AVGT1-0: select the temperature internal average. - * \endcode - */ -#define LPS25HB_RES_CONF_ADDR 0x10 - -/** - * @brief Pressure sensor control register 1 - * \code - * Read/write - * Default value: 0x00 - * 7 PD: power down control. 0 - disable; 1 - enable - * 6:4 ODR2, ODR1, ODR0: output data rate selection. - * ODR2 | ODR1 | ODR0 | Pressure output data-rate(Hz) | Temperature output data-rate(Hz) - * ---------------------------------------------------------------------------------- - * 0 | 0 | 0 | one shot | one shot - * 0 | 0 | 1 | 1 | 1 - * 0 | 1 | 0 | 7 | 7 - * 0 | 1 | 1 | 12.5 | 12.5 - * 1 | 0 | 0 | 25 | 25 - * 1 | 0 | 1 | Reserved | Reserved - * 1 | 1 | 0 | Reserved | Reserved - * 1 | 1 | 1 | Reserved | Reserved - * - * 3 DIFF_EN: Interrupt circuit. 0 - disable; 1 - enable - * 2 BDU: block data update. 0 - disable; 1 - enable - * 1 DELTA_EN: delta pressure. 0 - disable; 1 - enable - * 1 RESET_AZ: reset AutoZero. 0 - disable; 1 - enable ///////ALE REVIEW - * 0 SIM: SPI Serial Interface Mode selection. 0 - SPI 4-wire; 1 - SPI 3-wire ///////ALE REVIEW - * \endcode - */ -#define LPS25HB_CTRL_REG1_ADDR 0x20 - -/** - * @brief Pressure sensor control register 2 - * \code - * Read/write - * Default value: 0x00 - * 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content - * 6 FIFO_EN: FIFO. 0: disable; 1: enable - * 5 WTM_EN: FIFO Watermark level use. 0: disable; 1: enable - * 4:3 Reserved. keep these bits at 0 - * 2 SWRESET: Software reset. 0: normal mode; 1: SW reset. - * 1 AUTO_ZERO: Autozero enable. 0: normal mode; 1: autozero enable. - * 0 ONE_SHOT: One shot enable. 0: waiting for start of conversion; 1: start for a new dataset - * \endcode - */ -#define LPS25HB_CTRL_REG2_ADDR 0x21 - -/** - * @brief Pressure sensor control register 3 - * \code - * Read/write - * Default value: 0x00 - * 7 INT_H_L: Interrupt. 0:active high; 1: active low. - * 6 PP_OD: Push-Pull/OpenDrain selection on interrupt pads. 0: Push-pull; 1: open drain. - * 5 Reserved - * 4:3 INT2_S2, INT2_S1: INT2 output signal selection control bits. // TO DO - * 1:0 INT1_S2, INT1_S1: data signal on INT1 pad control bits. - * INT1(2)_S2 | INT1(2)_S1 | INT1(2) pin - * ------------------------------------------------------ - * 0 | 0 | Data signal - * 0 | 1 | Pressure high (P_high) - * 1 | 0 | Pressure low (P_low) - * 1 | 1 | P_low OR P_high - - - * \endcode - */ -#define LPS25HB_CTRL_REG3_ADDR 0x22 - -/** - * @brief Pressure sensor control register 4 - * \code - * Read/write - * Default value: 0x00 - * 7 P2_EMPTY: Empty Signal on INT2 pin. - * 6 P2_WTM: Watermark Signal on INT2 pin. - * 5 P2_Overrun:Overrun Signal on INT2 pin. - * 4 P2_DRDY: Data Ready Signal on INT2 pin. - * 3 P1_EMPTY: Empty Signal on INT1 pin. - * 2 P1_WTM: Watermark Signal on INT1 pin. - * 1 P1_Overrunn:Overrun Signal on INT1 pin. - * 0 P1_DRDY: Data Ready Signal on INT1 pin. - * \endcode - */ -#define LPS25HB_CTRL_REG4_ADDR 0x23 - -/** - * @brief Interrupt configuration Register - * \code - * Read/write - * Default value: 0x00. - * 7:3 Reserved. - * 2 LIR: Latch Interrupt request into INT_SOURCE register. 0 - disable; 1 - enable - * 1 PL_E: Enable interrupt generation on differential pressure low event. 0 - disable; 1 - enable - * 0 PH_E: Enable interrupt generation on differential pressure high event. 0 - disable; 1 - enable - * \endcode - */ -#define LPS25HB_INT_CFG_REG_ADDR 0x24 - -/** - * @brief Interrupt source Register - * \code - * Read - * Default value: 0x00. - * 7:3 0. - * 2 IA: Interrupt Active.0: no interrupt has been generated; 1: one or more interrupt events have been generated. - * 1 PL: Differential pressure Low. 0: no interrupt has been generated; 1: Low differential pressure event has occurred. - * 0 PH: Differential pressure High. 0: no interrupt has been generated; 1: High differential pressure event has occurred. - * \endcode - */ -#define LPS25HB_INT_SOURCE_REG_ADDR 0x25 - -/** - * @brief Threshold pressure (LSB) - * \code - * Read - * Default value: 0x00. - * 7:0 THS7-THS0: Low part of threshold value for pressure interrupt - * generation. The complete threshold value is given by THS_P_H & THS_P_L and is - * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. - * \endcode - */ -#define LPS25HB_THS_P_LOW_REG_ADDR 0x30 - -/** - * @brief Threshold pressure (MSB) - * \code - * Read - * Default value: 0x00. - * 7:0 THS15-THS8: High part of threshold value for pressure interrupt - * generation. The complete threshold value is given by THS_P_H & THS_P_L and is - * expressed as unsigned number. P_ths(mbar)=(THS_P_H & THS_P_L)[dec]/16. - * \endcode - */ -#define LPS25HB_THS_P_HIGH_REG_ADDR 0x31 - -/** - * @brief Status Register - * \code - * Read - * Default value: 0x00 - * 7:6 0 - * 5 P_OR: Pressure data overrun. 0: no overrun has occurred; 1: new data for pressure has overwritten the previous one. - * 4 T_OR: Temperature data overrun. 0: no overrun has occurred; 1: a new data for temperature has overwritten the previous one. - * 3:2 0 - * 1 P_DA: Pressure data available. 0: new data for pressure is not yet available; 1: new data for pressure is available. - * 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. - * \endcode - */ -#define LPS25HB_STATUS_REG_ADDR 0x27 - -/** - * @brief Pressure data (LSB). - * \code - * Read - * Default value: 0x00. - * POUT7 - POUT0: Pressure data LSB (2's complement). - * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & - * PRESS_OUT_XL)[dec]/4096. - * \endcode - */ -#define LPS25HB_PRESS_POUT_XL_ADDR 0x28 - -/** - * @brief Pressure data (Middle part). - * \code - * Read - * Default value: 0x80. - * POUT15 - POUT8: Pressure data middle part (2's complement). - * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & - * PRESS_OUT_XL)[dec]/4096. - * \endcode - */ -#define LPS25HB_PRESS_OUT_L_ADDR 0x29 - -/** - * @brief Pressure data (MSB). - * \code - * Read - * Default value: 0x2F. - * POUT23 - POUT16: Pressure data MSB (2's complement). - * Pressure output data: Pout(mbar)=(PRESS_OUT_H & PRESS_OUT_L & - * PRESS_OUT_XL)[dec]/4096. - * \endcode - */ -#define LPS25HB_PRESS_OUT_H_ADDR 0x2A - -/** - * @brief Temperature data (LSB). - * \code - * Read - * Default value: 0x00. - * TOUT7 - TOUT0: temperature data LSB. - * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. - * \endcode - */ -#define LPS25HB_TEMP_OUT_L_ADDR 0x2B - -/** - * @brief Temperature data (MSB). - * \code - * Read - * Default value: 0x00. - * TOUT15 - TOUT8: temperature data MSB. - * T(degC) = 42.5 + (Temp_OUTH & TEMP_OUT_L)[dec]/480. - * \endcode - */ -#define LPS25HB_TEMP_OUT_H_ADDR 0x2C - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * 7:5 F_MODE2, F_MODE1, F_MODE0: FIFO mode selection. - * FM2 | FM1 | FM0 | FIFO MODE - * --------------------------------------------------- - * 0 | 0 | 0 | BYPASS MODE - * 0 | 0 | 1 | FIFO MODE. Stops collecting data when full - * 0 | 1 | 0 | STREAM MODE: Keep the newest measurements in the FIFO - * 0 | 1 | 1 | STREAM MODE until trigger deasserted, then change to FIFO MODE - * 1 | 0 | 0 | BYPASS MODE until trigger deasserted, then STREAM MODE - * 1 | 0 | 1 | Reserved - * 1 | 1 | 0 | FIFO_MEAN MODE: Fifo is used to generate a running average filtered pressure - * 1 | 1 | 1 | BYPASS mode until trigger deasserted, then FIFO MODE - * - * 4:0 FIFO Mean Mode Sample size - * WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | WTM_POINT4 | Sample Size - * ---------------------------------------------------------------------------------- - * 0 | 0 | 0 | 0 | 1 | 2 - * 0 | 0 | 0 | 1 | 1 | 4 - * 0 | 0 | 1 | 1 | 1 | 8 - * 0 | 1 | 1 | 1 | 1 | 16 - * 1 | 1 | 1 | 1 | 1 | 32 - * other values operation not guaranteed - * \endcode - */ -#define LPS25HB_CTRL_FIFO_ADDR 0x2E - -/** - * @brief FIFO Status register - * \code - * Read/write - * Default value: 0x00 - * 7 WTM_FIFO: Watermark status. 0:FIFO filling is lower than watermark level; 1: FIFO is equal or higher than watermark level. - * 6 FULL_FIFO: Overrun bit status. 0 - FIFO not full; 1 -FIFO is full. - * 5 EMPTY_FIFO: Empty FIFO bit. 0 - FIFO not empty; 1 -FIFO is empty. - * 4:0 DIFF_POINT4...0: FIFOsStored data level. - * \endcode - */ -#define LPS25HB_STATUS_FIFO_ADDR 0x2F - -/** - * @brief Pressure offset register - * \code - * Read/write - * Default value: 0x00 - * 7:0 RPDS15...8:Pressure Offset for 1 point calibration after soldering. - * \endcode - */ -#define LPS25HB_RPDS_TRIM_L_ADDR 0x39 - -/** - * @brief Pressure offset register - * \code - * Read/write - * Default value: 0x00 - * 7:0 RPDS23...16:Pressure Offset for 1 point calibration after soldering. - * \endcode - */ -#define LPS25HB_RPDS_TRIM_H_ADDR 0x3A - -/******************************************************************************/ -/**************************** END REGISTER MAPPING ***************************/ -/******************************************************************************/ - -/** - * @brief Multiple Byte. Mask for enabling multiple byte read/write command. - */ -#define LPS25HB_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) - -/** - * @brief Device Address - */ -#define LPS25HB_ADDRESS_LOW 0xB8 -#define LPS25HB_ADDRESS_HIGH 0xBA - - -/** - * @brief Device Identifier. Default value of the WHO_AM_I register. - */ -#define I_AM_LPS25HB ((uint8_t)0xBD) - -/** @defgroup LPS25HB_Power_Mode_Selection_CTRL_REG1 LPS25HB_Power_Mode_Selection_CTRL_REG1 - * @{ - */ -#define LPS25HB_MODE_POWERDOWN ((uint8_t)0x00) -#define LPS25HB_MODE_ACTIVE ((uint8_t)0x80) - -#define LPS25HB_MODE_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup LPS25HB_Output_Data_Rate_Selection_CTRL_REG1 LPS25HB_Output_Data_Rate_Selection_CTRL_REG1 - * @{ - */ -#define LPS25HB_ODR_ONE_SHOT ((uint8_t)0x00) /*!< Output Data Rate: P - one shot, T - one shot */ -#define LPS25HB_ODR_1Hz ((uint8_t)0x10) /*!< Output Data Rate: P - 1Hz, T - 1Hz */ -#define LPS25HB_ODR_7Hz ((uint8_t)0x20) /*!< Output Data Rate: P - 7Hz, T - 7Hz */ -#define LPS25HB_ODR_12_5Hz ((uint8_t)0x30) /*!< Output Data Rate: P - 12.5Hz, T - 12.5Hz */ -#define LPS25HB_ODR_25Hz ((uint8_t)0x40) /*!< Output Data Rate: P - 25Hz, T - 25Hz */ - -#define LPS25HB_ODR_MASK ((uint8_t)0x70) -/** - * @} - */ - -/** @defgroup LPS25HB_Interrupt_Circuit_Enable_CTRL_REG1 LPS25HB_Interrupt_Circuit_Enable_CTRL_REG1 - * @{ - */ -#define LPS25HB_DIFF_DISABLE ((uint8_t)0x00) /*!< interrupt circuit enabled */ -#define LPS25HB_DIFF_ENABLE ((uint8_t)0x08) /*!< interrupt generation disabled */ - -#define LPS25HB_DIFF_EN_MASK ((uint8_t)0x08) -/** - * @} - */ - -/** @defgroup LPS25HB_Block_Data_Update_CTRL_REG1 LPS25HB_Block_Data_Update_CTRL_REG1 - * @{ - */ -#define LPS25HB_BDU_CONT ((uint8_t)0x00) /*!< continuous update */ -#define LPS25HB_BDU_READ ((uint8_t)0x04) /*!< output registers not updated until MSB and LSB reading */ - -#define LPS25HB_BDU_MASK ((uint8_t)0x04) -/** - * @} - */ - -/** @defgroup LPS25HB_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 LPS25HB_SPI_Serial_Interface_Mode_Selection_CTRL_REG1 - * @{ - */ -#define LPS25HB_SPI_SIM_4W ((uint8_t)0x00) /*!< 4-wire interface */ -#define LPS25HB_SPI_SIM_3W ((uint8_t)0x01) /*!< 3-wire interface */ - -#define LPS25HB_SPI_SIM_MASK ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup LPS25HB_Refresh_Registers_Flash_Memory_CTRL_REG2 LPS25HB_Refresh_Registers_Flash_Memory_CTRL_REG2 - * @{ - */ -#define LPS25HB_NORMAL_MODE ((uint8_t)0x00) -#define LPS25HB_RESET_MEMORY ((uint8_t)0x80) - -#define LPS25HB_RESET_MEMORY_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup LPS25HB_Pressure_Resolution_Selection_RES_CONF LPS25HB_Pressure_Resolution_Selection_RES_CONF - * @{ - */ -#define LPS25HB_P_RES_AVG_8 ((uint8_t)0x00) -#define LPS25HB_P_RES_AVG_32 ((uint8_t)0x01) -#define LPS25HB_P_RES_AVG_128 ((uint8_t)0x02) -#define LPS25HB_P_RES_AVG_512 ((uint8_t)0x03) - -#define LPS25HB_P_RES_MASK ((uint8_t)0x03) -/** - * @} - */ - -/** @defgroup LPS25HB_Temperature_Resolution_Selection_RES_CONF LPS25HB_Temperature_Resolution_Selection_RES_CONF - * @{ - */ -#define LPS25HB_T_RES_AVG_8 ((uint8_t)0x00) -#define LPS25HB_T_RES_AVG_16 ((uint8_t)0x04) -#define LPS25HB_T_RES_AVG_32 ((uint8_t)0x08) -#define LPS25HB_T_RES_AVG_64 ((uint8_t)0x0C) - -#define LPS25HB_T_RES_MASK ((uint8_t)0x0C) -/** - * @} - */ - -#define LPS25HB_SA0_LOW ((uint8_t)0x00) -#define LPS25HB_SA0_HIGH ((uint8_t)0x01) - -/** - * @} - */ - -/** @defgroup LPS25HB_Imported_Functions LPS25HB_Imported_Functions - * @{ - */ -/* Pressure sensor IO functions */ -extern PRESSURE_StatusTypeDef LPS25HB_IO_Init(void); -extern PRESSURE_StatusTypeDef LPS25HB_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToWrite); -extern PRESSURE_StatusTypeDef LPS25HB_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToRead); -extern void LPS25HB_IO_ITConfig( void ); - -/** - * @} - */ - -/* ------------------------------------------------------- */ -/* Here you should declare the internal struct of */ -/* extended features of LPS25HB. See the example of */ -/* LSM6DS3 in lsm6ds3.h */ -/* ------------------------------------------------------- */ - -/** @addtogroup LPS25HB_Exported_Variables LPS25HB_Exported_Variables - * @{ - */ -/* Pressure sensor driver structure */ -extern PRESSURE_DrvTypeDef LPS25HBDrv; -extern PRESSURE_DrvExtTypeDef LPS25HBDrv_ext; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LPS25HB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/Release_Notes.html deleted file mode 100644 index 3e823ebb6..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/Release_Notes.html +++ /dev/null @@ -1,211 +0,0 @@ - - - - - -Release Notes for STM32 BlueEnergy Library - - - - - -
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Release Notes for LSM6DS0 component

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Copyright -2015 STMicroelectronics

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Update History

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V1.3.0 -/ 28-May-2015

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Main -Changes

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  • Add output data rate and full scale settings APIs for the Component -
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  • Add LSM6DS0_X_GetAxes and LSM6DS0_G_GetAxes APIs -
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V1.2.0 -/ 11-February-2015

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Main -Changes

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  • Add extended features support for the Component -
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V1.1.0 -/ 12-December-2014

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Main -Changes

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  • Add error control in the Component API -
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V1.0.0 -/ 10-September-2014

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Main -Changes

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  • First -official release
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License
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- - -Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

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- http://www.st.com/software_license_agreement_liberty_v2


- -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - - - - - -

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For -complete documentation on STM32 STM BlueNRG -visit www.st.com/BlueNRG

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- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.c b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.c deleted file mode 100644 index 5d9f8f541..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.c +++ /dev/null @@ -1,795 +0,0 @@ -/** - ****************************************************************************** - * @file lsm6ds0.c - * @author MEMS Application Team - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file provides a set of functions needed to manage the lsm6ds0. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "lsm6ds0.h" -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LSM6DS0 - * @{ - */ - -static IMU_6AXES_StatusTypeDef LSM6DS0_Init(IMU_6AXES_InitTypeDef *LSM6DS0_Init); -static IMU_6AXES_StatusTypeDef LSM6DS0_Read_XG_ID(uint8_t *xg_id); -static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxes(int32_t *pData); -static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxesRaw(int16_t *pData); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxes(int32_t *pData); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxesRaw(int16_t *pData); -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_ODR( float *odr ); -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_ODR( float odr ); -static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetSensitivity( float *pfData ); -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_FS( float *fullScale ); -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_FS( float fullScale ); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_ODR( float *odr ); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_ODR( float odr ); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetSensitivity( float *pfData ); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_FS( float *fullScale ); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_FS( float fullScale ); - -/** @defgroup LSM6DS0_Private_Variables LSM6DS0_Private_Variables - * @{ - */ - -IMU_6AXES_DrvTypeDef LSM6DS0Drv = -{ - LSM6DS0_Init, - LSM6DS0_Read_XG_ID, - LSM6DS0_X_GetAxes, - LSM6DS0_X_GetAxesRaw, - LSM6DS0_G_GetAxes, - LSM6DS0_G_GetAxesRaw, - LSM6DS0_X_Get_ODR, - LSM6DS0_X_Set_ODR, - LSM6DS0_X_GetSensitivity, - LSM6DS0_X_Get_FS, - LSM6DS0_X_Set_FS, - LSM6DS0_G_Get_ODR, - LSM6DS0_G_Set_ODR, - LSM6DS0_G_GetSensitivity, - LSM6DS0_G_Get_FS, - LSM6DS0_G_Set_FS, - NULL -}; - -/* ------------------------------------------------------- */ -/* Here you should declare the variable that implements */ -/* the internal struct of extended features of LSM6DS0. */ -/* Then you must update the NULL pointer in the variable */ -/* of the extended features below. */ -/* See the example of LSM6DS3 in lsm6ds3.c */ -/* ------------------------------------------------------- */ - -IMU_6AXES_DrvExtTypeDef LSM6DS0Drv_ext = -{ - IMU_6AXES_LSM6DS0_COMPONENT, /* unique ID for LSM6DS0 in the IMU 6-axes driver class */ - NULL /* pointer to internal struct of extended features of LSM6DS0 */ -}; - -/** - * @} - */ - -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); - -/** @defgroup LSM6DS0_Private_Functions LSM6DS0_Private_Functions - * @{ - */ - -/** - * @brief Set LSM6DS0 Initialization - * @param LSM6DS0_Init the configuration setting for the LSM6DS0 - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_Init(IMU_6AXES_InitTypeDef *LSM6DS0_Init) -{ - /* Configure the low level interface ---------------------------------------*/ - if(LSM6DS0_IO_Init() != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /******* Gyroscope init *******/ - - if(LSM6DS0_G_Set_ODR( LSM6DS0_Init->G_OutputDataRate ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS0_G_Set_FS( LSM6DS0_Init->G_FullScale ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS0_G_Set_Axes_Status(LSM6DS0_Init->G_X_Axis, LSM6DS0_Init->G_Y_Axis, LSM6DS0_Init->G_Z_Axis) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /******************************/ - - /***** Accelerometer init *****/ - - if(LSM6DS0_X_Set_ODR( LSM6DS0_Init->X_OutputDataRate ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS0_X_Set_FS( LSM6DS0_Init->X_FullScale ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS0_X_Set_Axes_Status(LSM6DS0_Init->X_X_Axis, LSM6DS0_Init->X_Y_Axis, LSM6DS0_Init->X_Z_Axis) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Configure interrupt lines */ - LSM6DS0_IO_ITConfig(); - - return IMU_6AXES_OK; - - /******************************/ -} - - -/** - * @brief Read ID of LSM6DS0 Accelerometer and Gyroscope - * @param xg_id the pointer where the ID of the device is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_Read_XG_ID(uint8_t *xg_id) -{ - if(!xg_id) - { - return IMU_6AXES_ERROR; - } - - return LSM6DS0_IO_Read(xg_id, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_WHO_AM_I_ADDR, 1); -} - - -/** - * @brief Read raw data from LSM6DS0 Accelerometer output register - * @param pData the pointer where the accelerometer raw data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxesRaw(int16_t *pData) -{ - uint8_t tempReg[2] = {0, 0}; - - if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_X_L_XL | LSM6DS0_I2C_MULTIPLEBYTE_CMD), - 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Y_L_XL | LSM6DS0_I2C_MULTIPLEBYTE_CMD), - 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Z_L_XL | LSM6DS0_I2C_MULTIPLEBYTE_CMD), - 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - return IMU_6AXES_OK; -} - - -/** - * @brief Read data from LSM6DS0 Accelerometer and calculate linear acceleration in mg - * @param pData the pointer where the accelerometer data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetAxes(int32_t *pData) -{ - int16_t pDataRaw[3]; - float sensitivity = 0; - - if(LSM6DS0_X_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS0_X_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = (int32_t)(pDataRaw[0] * sensitivity); - pData[1] = (int32_t)(pDataRaw[1] * sensitivity); - pData[2] = (int32_t)(pDataRaw[2] * sensitivity); - - return IMU_6AXES_OK; -} - - -/** - * @brief Read raw data from LSM6DS0 Gyroscope output register - * @param pData the pointer where the gyroscope raw data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxesRaw(int16_t *pData) -{ - uint8_t tempReg[2] = {0, 0}; - - if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_X_L_G | LSM6DS0_I2C_MULTIPLEBYTE_CMD), - 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Y_L_G | LSM6DS0_I2C_MULTIPLEBYTE_CMD), - 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS0_IO_Read(&tempReg[0], LSM6DS0_XG_MEMS_ADDRESS, (LSM6DS0_XG_OUT_Z_L_G | LSM6DS0_I2C_MULTIPLEBYTE_CMD), - 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - return IMU_6AXES_OK; -} - -/** - * @brief Set the status of the axes for accelerometer - * @param enableX the status of the x axis to be set - * @param enableY the status of the y axis to be set - * @param enableZ the status of the z axis to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) -{ - uint8_t tmp1 = 0x00; - uint8_t eX = 0x00; - uint8_t eY = 0x00; - uint8_t eZ = 0x00; - - eX = ( enableX == 0 ) ? LSM6DS0_XL_XEN_DISABLE : LSM6DS0_XL_XEN_ENABLE; - eY = ( enableY == 0 ) ? LSM6DS0_XL_YEN_DISABLE : LSM6DS0_XL_YEN_ENABLE; - eZ = ( enableZ == 0 ) ? LSM6DS0_XL_ZEN_DISABLE : LSM6DS0_XL_ZEN_ENABLE; - - if(LSM6DS0_IO_Read(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG5_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Enable X axis selection */ - tmp1 &= ~(LSM6DS0_XL_XEN_MASK); - tmp1 |= eX; - - /* Enable Y axis selection */ - tmp1 &= ~(LSM6DS0_XL_YEN_MASK); - tmp1 |= eY; - - /* Enable Z axis selection */ - tmp1 &= ~(LSM6DS0_XL_ZEN_MASK); - tmp1 |= eZ; - - if(LSM6DS0_IO_Write(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG5_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Set the status of the axes for gyroscope - * @param enableX the status of the x axis to be set - * @param enableY the status of the y axis to be set - * @param enableZ the status of the z axis to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) -{ - uint8_t tmp1 = 0x00; - uint8_t eX = 0x00; - uint8_t eY = 0x00; - uint8_t eZ = 0x00; - - eX = ( enableX == 0 ) ? LSM6DS0_G_XEN_DISABLE : LSM6DS0_G_XEN_ENABLE; - eY = ( enableY == 0 ) ? LSM6DS0_G_YEN_DISABLE : LSM6DS0_G_YEN_ENABLE; - eZ = ( enableZ == 0 ) ? LSM6DS0_G_ZEN_DISABLE : LSM6DS0_G_ZEN_ENABLE; - - if(LSM6DS0_IO_Read(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG4, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Enable X axis selection */ - tmp1 &= ~(LSM6DS0_G_XEN_MASK); - tmp1 |= eX; - - /* Enable Y axis selection */ - tmp1 &= ~(LSM6DS0_G_YEN_MASK); - tmp1 |= eY; - - /* Enable Z axis selection */ - tmp1 &= ~(LSM6DS0_G_ZEN_MASK); - tmp1 |= eZ; - - if(LSM6DS0_IO_Write(&tmp1, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG4, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - - -/** - * @brief Read data from LSM6DS0 Gyroscope and calculate angular rate in mdps - * @param pData the pointer where the gyroscope data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetAxes(int32_t *pData) -{ - int16_t pDataRaw[3]; - float sensitivity = 0; - - if(LSM6DS0_G_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS0_G_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = (int32_t)(pDataRaw[0] * sensitivity); - pData[1] = (int32_t)(pDataRaw[1] * sensitivity); - pData[2] = (int32_t)(pDataRaw[2] * sensitivity); - - return IMU_6AXES_OK; -} - -/** - * @brief Read Accelero Output Data Rate - * @param odr the pointer where the accelerometer output data rate is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_ODR( float *odr ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS0_XL_ODR_MASK; - - switch( tempReg ) - { - case LSM6DS0_XL_ODR_PD: - *odr = 0.0f; - break; - case LSM6DS0_XL_ODR_10HZ: - *odr = 10.0f; - break; - case LSM6DS0_XL_ODR_50HZ: - *odr = 50.0f; - break; - case LSM6DS0_XL_ODR_119HZ: - *odr = 119.0f; - break; - case LSM6DS0_XL_ODR_238HZ: - *odr = 238.0f; - break; - case LSM6DS0_XL_ODR_476HZ: - *odr = 476.0f; - break; - case LSM6DS0_XL_ODR_952HZ: - *odr = 952.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Accelero Output Data Rate - * @param odr the accelerometer output data rate to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_ODR( float odr ) -{ - uint8_t new_odr = 0x00; - uint8_t tempReg = 0x00; - - new_odr = ( odr <= 0.0f ) ? LSM6DS0_XL_ODR_PD /* Power Down */ - : ( odr <= 10.0f ) ? LSM6DS0_XL_ODR_10HZ - : ( odr <= 50.0f ) ? LSM6DS0_XL_ODR_50HZ - : ( odr <= 119.0f ) ? LSM6DS0_XL_ODR_119HZ - : ( odr <= 238.0f ) ? LSM6DS0_XL_ODR_238HZ - : ( odr <= 476.0f ) ? LSM6DS0_XL_ODR_476HZ - : LSM6DS0_XL_ODR_952HZ; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS0_XL_ODR_MASK); - tempReg |= new_odr; - - if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Accelero Sensitivity - * @param pfData the pointer where the accelerometer sensitivity is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_X_GetSensitivity( float *pfData ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS0_XL_FS_MASK; - - switch( tempReg ) - { - case LSM6DS0_XL_FS_2G: - *pfData = 0.061f; - break; - case LSM6DS0_XL_FS_4G: - *pfData = 0.122f; - break; - case LSM6DS0_XL_FS_8G: - *pfData = 0.244f; - break; - case LSM6DS0_XL_FS_16G: - *pfData = 0.732f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Accelero Full Scale - * @param fullScale the pointer where the accelerometer full scale is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Get_FS( float *fullScale ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS0_XL_FS_MASK; - - switch( tempReg ) - { - case LSM6DS0_XL_FS_2G: - *fullScale = 2.0f; - break; - case LSM6DS0_XL_FS_4G: - *fullScale = 4.0f; - break; - case LSM6DS0_XL_FS_8G: - *fullScale = 8.0f; - break; - case LSM6DS0_XL_FS_16G: - *fullScale = 16.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Accelero Full Scale - * @param fullScale the accelerometer full scale to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_X_Set_FS( float fullScale ) -{ - uint8_t new_fs = 0x00; - uint8_t tempReg = 0x00; - - new_fs = ( fullScale <= 2.0f ) ? LSM6DS0_XL_FS_2G - : ( fullScale <= 4.0f ) ? LSM6DS0_XL_FS_4G - : ( fullScale <= 8.0f ) ? LSM6DS0_XL_FS_8G - : LSM6DS0_XL_FS_16G; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS0_XL_FS_MASK); - tempReg |= new_fs; - - if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG6_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Gyro Output Data Rate - * @param odr the pointer where the gyroscope output data rate is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_ODR( float *odr ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS0_G_ODR_MASK; - - switch( tempReg ) - { - case LSM6DS0_G_ODR_PD: - *odr = 0.0f; - break; - case LSM6DS0_G_ODR_14_9HZ: - *odr = 14.9f; - break; - case LSM6DS0_G_ODR_59_5HZ: - *odr = 59.5f; - break; - case LSM6DS0_G_ODR_119HZ: - *odr = 119.0f; - break; - case LSM6DS0_G_ODR_238HZ: - *odr = 238.0f; - break; - case LSM6DS0_G_ODR_476HZ: - *odr = 476.0f; - break; - case LSM6DS0_G_ODR_952HZ: - *odr = 952.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Gyro Output Data Rate - * @param odr the gyroscope output data rate to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_ODR( float odr ) -{ - uint8_t new_odr = 0x00; - uint8_t tempReg = 0x00; - - new_odr = ( odr <= 0.0f ) ? LSM6DS0_G_ODR_PD /* Power Down */ - : ( odr <= 14.9f ) ? LSM6DS0_G_ODR_14_9HZ - : ( odr <= 59.5f ) ? LSM6DS0_G_ODR_59_5HZ - : ( odr <= 119.0f ) ? LSM6DS0_G_ODR_119HZ - : ( odr <= 238.0f ) ? LSM6DS0_G_ODR_238HZ - : ( odr <= 476.0f ) ? LSM6DS0_G_ODR_476HZ - : LSM6DS0_G_ODR_952HZ; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS0_G_ODR_MASK); - tempReg |= new_odr; - - if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Gyro Sensitivity - * @param pfData the pointer where the gyroscope sensitivity is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_GetSensitivity( float *pfData ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS0_G_FS_MASK; - - switch( tempReg ) - { - case LSM6DS0_G_FS_245: - *pfData = 8.75f; - break; - case LSM6DS0_G_FS_500: - *pfData = 17.50f; - break; - case LSM6DS0_G_FS_2000: - *pfData = 70.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Gyro Full Scale - * @param fullScale the pointer where the gyroscope full scale is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Get_FS( float *fullScale ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS0_G_FS_MASK; - - switch( tempReg ) - { - case LSM6DS0_G_FS_245: - *fullScale = 245.0f; - break; - case LSM6DS0_G_FS_500: - *fullScale = 500.0f; - break; - case LSM6DS0_G_FS_2000: - *fullScale = 2000.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Gyro Full Scale - * @param fullScale the gyroscope full scale to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS0_G_Set_FS( float fullScale ) -{ - uint8_t new_fs = 0x00; - uint8_t tempReg = 0x00; - - new_fs = ( fullScale <= 245.0f ) ? LSM6DS0_G_FS_245 - : ( fullScale <= 500.0f ) ? LSM6DS0_G_FS_500 - : LSM6DS0_G_FS_2000; - - if(LSM6DS0_IO_Read( &tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS0_G_FS_MASK); - tempReg |= new_fs; - - if(LSM6DS0_IO_Write(&tempReg, LSM6DS0_XG_MEMS_ADDRESS, LSM6DS0_XG_CTRL_REG1_G, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.h b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.h deleted file mode 100644 index a8600642d..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds0/lsm6ds0.h +++ /dev/null @@ -1,602 +0,0 @@ -/** - ****************************************************************************** - * @file lsm6ds0.h - * @author MEMS Application Team - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file contains definitions for the lsm6ds0.c - * firmware driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __LSM6DS0_H -#define __LSM6DS0_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "imu_6axes.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LSM6DS0 - * @{ - */ - -/** @defgroup LSM6DS0_Exported_Defines LSM6DS0_Exported_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif - - -/******************************************************************************/ -/*********** START ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ -/******************************************************************************/ - - -/***************************************** COMMON REGISTERS ********************************************/ - -/** - * @brief Interrupt config register - * \code - * Read/write - * Default value: 0x00 - * [7] INT_IG_G: Gyroscope interrupt enable on INT pin - * [6] INT_IG_XL: Accelerometer interrupt generator on INT pin - * [5] INT_FSS5: FSS5 interrupt enable on INT pin - * [4] INT_OVR: Overrun interrupt on INT pin - * [3] INT_FTH: Gyroscope interrupt enable on INT pin - * [2] INT_BOOT: Accelerometer interrupt generator on INT pin - * [1] INT_DRDY_G: FSS5 interrupt enable on INT pin - * [0] INT_DRDY_XL: Overrun interrupt on INT pin - * \endcode - */ -#define LSM6DS0_XG_INT_CTRL 0x0C - - -/** - * @brief Device identifier register. - * \code - * Read - * Default value: - * [7:0] This read-only register contains the device identifier - * \endcode -*/ -#define LSM6DS0_XG_WHO_AM_I_ADDR 0x0F - - -/** - * @brief Control Register 4 - * \code - * Read/write - * Default value: 0x38 - * [5] Zen_G: Gyroscope’s Z-axis output enable - * [4] Yen_G: Gyroscope’s Y-axis output enable - * [3] Xen_G: Gyroscope’s X-axis output enable - * \endcode -*/ -#define LSM6DS0_XG_CTRL_REG4 0x1E - - -/** - * @brief Control Register 10 - * \code - * Read/write - * Default value: 0x00 - * [2] ST_G: Gyro selftest disable (0) / enable (1) - * [0] ST_XL: Accel selftest disable (0) / enable (1) - * \endcode -*/ -#define LSM6DS0_XG_CTRL_REG10 0x24 - - -/***************************************** GYROSCOPE REGISTERS ********************************************/ - -/** - * @brief Angular rate sensor Control Register 1 - * \code - * Read/write - * Default value: 0x00 - * [7:5] ODR_G2-0: Gyroscope output data rate selection - * [4:3] FS_G1-0: Gyroscope full-scale selection - * [2] This bit must be set to ‘0’ for the correct operation of the device - * [1:0] BW_G1-0: Gyroscope bandwidth selection - * \endcode - */ -#define LSM6DS0_XG_CTRL_REG1_G 0x10 - - -/** - * @brief Gyroscope data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_X_L_G 0x18 - - -/** - * @brief Gyroscope data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_X_H_G 0x19 - - -/** - * @brief Gyroscope data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Y_L_G 0x1A - - -/** - * @brief Gyroscope data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Y_H_G 0x1B - - -/** - * @brief Gyroscope data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Z_L_G 0x1C - - -/** - * @brief Gyroscope data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Z_H_G 0x1D - - - -/*************************************** ACCELEROMETER REGISTERS *******************************************/ - -/** - * @brief Linear acceleration sensor Control Register 6 - * \code - * Read/write - * Default value: 0x00 - * [7:5] ODR_XL2-0: Accelerometer Output data rate and power mode selection - * [4:3] FS1_XL-FS0_XL: Accelerometer full-scale selection - * [2] BW_SCAL_ODR: Bandwidth selection - * [1:0] BW_XL1-0: Anti-aliasing filter bandwidth selection - * \endcode - */ -#define LSM6DS0_XG_CTRL_REG6_XL 0x20 - - -/** - * @brief Linear acceleration sensor Control Register 5 - * \code - * Read/write - * Default value: 0x38 - * [7:6] DEC1-0: Decimation of acceleration data on OUT REG and FIFO - * [5] Zen_XL: Accelerometer’s Z-axis output enable - * [4] Yen_XL: Accelerometer’s Y-axis output enable - * [3] Xen_XL: Accelerometer’s X-axis output enable - * [2:0] These bits must be set to ‘0’ for the correct operation of the device - * \endcode - */ -#define LSM6DS0_XG_CTRL_REG5_XL 0x1F - - -/** - * @brief Accelerometer data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_X_L_XL 0x28 - - -/** - * @brief Accelerometer data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_X_H_XL 0x29 - - -/** - * @brief Accelerometer data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Y_L_XL 0x2A - - -/** - * @brief Accelerometer data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Y_H_XL 0x2B - - -/** - * @brief Accelerometer data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Z_L_XL 0x2C - - -/** - * @brief Accelerometer data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS0_XG_OUT_Z_H_XL 0x2D - -/******************************************************************************/ -/************* END ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ -/******************************************************************************/ - -/** - * @brief Multiple Byte. Mask for enabling multiple byte read/write command. - */ -#define LSM6DS0_I2C_MULTIPLEBYTE_CMD ((uint8_t)0x80) - -/** -* @brief Device Address -*/ -#define LSM6DS0_ADDRESS_LOW 0xD4 // SAD[0] = 0 -#define LSM6DS0_ADDRESS_HIGH 0xD6 // SAD[0] = 1 -#define LSM6DS0_XG_MEMS_ADDRESS LSM6DS0_ADDRESS_HIGH // SAD[0] = 1 - -/** - * @brief Device Identifier. Default value of the WHO_AM_I register. - */ -#define I_AM_LSM6DS0_XG ((uint8_t)0x68) - - - -/************************************** GYROSCOPE REGISTERS VALUE *******************************************/ - - -/** @defgroup LSM6DS0_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G LSM6DS0_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G - * @{ - */ -#define LSM6DS0_G_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ -#define LSM6DS0_G_ODR_14_9HZ ((uint8_t)0x20) /*!< Output Data Rate: 14.9 Hz, cutoff 5Hz */ -#define LSM6DS0_G_ODR_59_5HZ ((uint8_t)0x40) /*!< Output Data Rate: 59.5 Hz, cutoff 19Hz */ -#define LSM6DS0_G_ODR_119HZ ((uint8_t)0x60) /*!< Output Data Rate: 119 Hz, cutoff 38Hz*/ -#define LSM6DS0_G_ODR_238HZ ((uint8_t)0x80) /*!< Output Data Rate: 238 Hz, cutoff 76Hz*/ -#define LSM6DS0_G_ODR_476HZ ((uint8_t)0xA0) /*!< Output Data Rate: 476 Hz, cutoff 100Hz*/ -#define LSM6DS0_G_ODR_952HZ ((uint8_t)0xC0) /*!< Output Data Rate: 952 Hz, cutoff 100Hz*/ - -#define LSM6DS0_G_ODR_MASK ((uint8_t)0xE0) -/** - * @} - */ - - -/** @defgroup LSM6DS0_XG_Gyroscope_Bandwidth_Selection_CTRL_REG1_G LSM6DS0_XG_Gyroscope_Bandwidth_Selection_CTRL_REG1_G - * @{ - */ -#define LSM6DS0_G_BW_00 ((uint8_t)0x00) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down - - cutoff = n.a. when ODR = 14.9 - - cutoff = 16 when ODR = 59.5 - - cutoff = 14 when ODR = 119 - - cutoff = 14 when ODR = 238 - - cutoff = 21 when ODR = 476 - - cutoff = 33 when ODR = 952 */ -#define LSM6DS0_G_BW_01 ((uint8_t)0x01) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down - - cutoff = n.a. when ODR = 14.9 - - cutoff = 16 when ODR = 59.5 - - cutoff = 31 when ODR = 119 - - cutoff = 29 when ODR = 238 - - cutoff = 28 when ODR = 476 - - cutoff = 40 when ODR = 952 */ -#define LSM6DS0_G_BW_10 ((uint8_t)0x02) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down - - cutoff = n.a. when ODR = 14.9 - - cutoff = 16 when ODR = 59.5 - - cutoff = 31 when ODR = 119 - - cutoff = 63 when ODR = 238 - - cutoff = 57 when ODR = 476 - - cutoff = 58 when ODR = 952 */ -#define LSM6DS0_G_BW_11 ((uint8_t)0x03) /*!< Bandwidth selection: - cutoff = n.a. when ODR = Power-down - - cutoff = n.a. when ODR = 14.9 - - cutoff = 16 when ODR = 59.5 - - cutoff = 31 when ODR = 119 - - cutoff = 78 when ODR = 238 - - cutoff = 100 when ODR = 476 - - cutoff = 100 when ODR = 952 */ - -#define LSM6DS0_G_BW_MASK ((uint8_t)0x03) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Gyroscope_Full_Scale_Selection_CTRL_REG1_G LSM6DS0_XG_Gyroscope_Full_Scale_Selection_CTRL_REG1_G - * @{ - */ -#define LSM6DS0_G_FS_245 ((uint8_t)0x00) /*!< Full scale: 245 dps*/ -#define LSM6DS0_G_FS_500 ((uint8_t)0x08) /*!< Full scale: 500 dps */ -#define LSM6DS0_G_FS_2000 ((uint8_t)0x18) /*!< Full scale: 2000 dps */ - -#define LSM6DS0_G_FS_MASK ((uint8_t)0x18) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL_REG4 LSM6DS0_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL_REG4 - * @{ - */ -#define LSM6DS0_G_ZEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Z-axis output enable: disable */ -#define LSM6DS0_G_ZEN_ENABLE ((uint8_t)0x20) /*!< Gyroscope’s Z-axis output enable: enable */ - -#define LSM6DS0_G_ZEN_MASK ((uint8_t)0x20) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL_REG4 LSM6DS0_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL_REG4 - * @{ - */ -#define LSM6DS0_G_YEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Y-axis output enable: disable */ -#define LSM6DS0_G_YEN_ENABLE ((uint8_t)0x10) /*!< Gyroscope’s Y-axis output enable: enable */ - -#define LSM6DS0_G_YEN_MASK ((uint8_t)0x10) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL_REG4 LSM6DS0_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL_REG4 - * @{ - */ -#define LSM6DS0_G_XEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s X-axis output enable: disable */ -#define LSM6DS0_G_XEN_ENABLE ((uint8_t)0x08) /*!< Gyroscope’s X-axis output enable: enable */ - -#define LSM6DS0_G_XEN_MASK ((uint8_t)0x08) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Gyroscope_Selftest_Enable_Selection_CTRL_REG10 LSM6DS0_XG_Gyroscope_Selftest_Enable_Selection_CTRL_REG10 - * @{ - */ -#define LSM6DS0_G_ST_DISABLE ((uint8_t)0x00) /*!< Gyro selftest disable */ -#define LSM6DS0_G_ST_ENABLE ((uint8_t)0x04) /*!< Gyro selftest enable */ - -#define LSM6DS0_G_ST_MASK ((uint8_t)0x04) -/** - * @} - */ - - -/************************************ ACCELEROMETER REGISTERS VALUE *****************************************/ - -/** @defgroup LSM6DS0_XG_Accelerometer_Output_Data_Rate_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Output_Data_Rate_Selection_CTRL_REG6_XL - * @{ - */ -#define LSM6DS0_XL_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ -#define LSM6DS0_XL_ODR_10HZ ((uint8_t)0x20) /*!< Output Data Rate: 10 Hz*/ -#define LSM6DS0_XL_ODR_50HZ ((uint8_t)0x40) /*!< Output Data Rate: 50 Hz */ -#define LSM6DS0_XL_ODR_119HZ ((uint8_t)0x60) /*!< Output Data Rate: 119 Hz */ -#define LSM6DS0_XL_ODR_238HZ ((uint8_t)0x80) /*!< Output Data Rate: 238 Hz */ -#define LSM6DS0_XL_ODR_476HZ ((uint8_t)0xA0) /*!< Output Data Rate: 476 Hz */ -#define LSM6DS0_XL_ODR_952HZ ((uint8_t)0xC0) /*!< Output Data Rate: 952 Hz */ - -#define LSM6DS0_XL_ODR_MASK ((uint8_t)0xE0) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Accelerometer_Full_Scale_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Full_Scale_Selection_CTRL_REG6_XL - * @{ - */ -#define LSM6DS0_XL_FS_2G ((uint8_t)0x00) /*!< Full scale: +- 2g */ -#define LSM6DS0_XL_FS_4G ((uint8_t)0x10) /*!< Full scale: +- 4g */ -#define LSM6DS0_XL_FS_8G ((uint8_t)0x18) /*!< Full scale: +- 8g */ -#define LSM6DS0_XL_FS_16G ((uint8_t)0x08) /*!< Full scale: +- 16g */ - -#define LSM6DS0_XL_FS_MASK ((uint8_t)0x18) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Accelerometer_Bandwidth_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Bandwidth_Selection_CTRL_REG6_XL - * @{ - */ -#define LSM6DS0_XL_BW_SCAL_ODR ((uint8_t)0x00) /*!< Bandwidth selection: determined by ODR: - - BW = 408Hz when ODR = 952Hz, 50Hz, 10Hz - - BW = 211Hz when ODR = 476Hz - - BW = 105Hz when ODR = 238Hz - - BW = 50Hz when ODR = 119Hz */ -#define LSM6DS0_XL_BW_SCAL_BW ((uint8_t)0x04) /*!< Bandwidth selection: selected according to Anti aliasing filter bandwidth */ - -#define LSM6DS0_XL_BW_SCAL_MASK ((uint8_t)0x04) -/** - * @} - */ - - -/** @defgroup LSM6DS0_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL_REG6_XL LSM6DS0_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL_REG6_XL - * @{ - */ -#define LSM6DS0_XL_BW_408HZ ((uint8_t)0x00) /*!< Anti-aliasing filter bandwidht: 408 Hz */ -#define LSM6DS0_XL_BW_211HZ ((uint8_t)0x01) /*!< Anti-aliasing filter bandwidht: 211 Hz */ -#define LSM6DS0_XL_BW_105HZ ((uint8_t)0x02) /*!< Anti-aliasing filter bandwidht: 105 Hz */ -#define LSM6DS0_XL_BW_50HZ ((uint8_t)0x03) /*!< Anti-aliasing filter bandwidht: 50 Hz */ - -#define LSM6DS0_XL_BW_MASK ((uint8_t)0x03) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Accelerometer_Decimation_Acceleration_Data_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_Decimation_Acceleration_Data_Selection_CTRL_REG5_XL - * @{ - */ -#define LSM6DS0_XL_DEC_NO ((uint8_t)0x00) /*!< Decimation of acceleration data: no decimation */ -#define LSM6DS0_XL_DEC_EVERY_2S ((uint8_t)0x40) /*!< Decimation of acceleration data: update every 2 samples */ -#define LSM6DS0_XL_DEC_EVERY_4S ((uint8_t)0x80) /*!< Decimation of acceleration data: update every 4 samples */ -#define LSM6DS0_XL_DEC_EVERY_8S ((uint8_t)0xC0) /*!< Decimation of acceleration data: update every 8 samples */ - -#define LSM6DS0_XL_DEC_MASK ((uint8_t)0xC0) -/** - * @} - */ - - -/** @defgroup LSM6DS0_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL_REG5_XL - * @{ - */ -#define LSM6DS0_XL_ZEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Z-axis output enable: disable */ -#define LSM6DS0_XL_ZEN_ENABLE ((uint8_t)0x20) /*!< Accelerometer’s Z-axis output enable: enable */ - -#define LSM6DS0_XL_ZEN_MASK ((uint8_t)0x20) -/** - * @} - */ - -/** @defgroup LSM6DS0_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL_REG5_XL - * @{ - */ -#define LSM6DS0_XL_YEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Y-axis output enable: disable */ -#define LSM6DS0_XL_YEN_ENABLE ((uint8_t)0x10) /*!< Accelerometer’s Y-axis output enable: enable */ - -#define LSM6DS0_XL_YEN_MASK ((uint8_t)0x10) -/** - * @} - */ - - -/** @defgroup LSM6DS0_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL_REG5_XL LSM6DS0_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL_REG5_XL - * @{ - */ -#define LSM6DS0_XL_XEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s X-axis output enable: disable */ -#define LSM6DS0_XL_XEN_ENABLE ((uint8_t)0x08) /*!< Accelerometer’s X-axis output enable: enable */ - -#define LSM6DS0_XL_XEN_MASK ((uint8_t)0x08) - -/** - * @} - */ - - -/** @defgroup LSM6DS0_XG_Accelerometer_Selftest_Enable_Selection_CTRL_REG10 LSM6DS0_XG_Accelerometer_Selftest_Enable_Selection_CTRL_REG10 - * @{ - */ -#define LSM6DS0_XL_ST_DISABLE ((uint8_t)0x00) /*!< Accel selftest disable */ -#define LSM6DS0_XL_ST_ENABLE ((uint8_t)0x01) /*!< Accel selftest enable */ - -#define LSM6DS0_XL_ST_MASK ((uint8_t)0x01) - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup LSM6DS0_Imported_Functions LSM6DS0_Imported_Functions - * @{ - */ - -/* Six axes sensor IO functions */ -extern IMU_6AXES_StatusTypeDef LSM6DS0_IO_Init(void); -extern IMU_6AXES_StatusTypeDef LSM6DS0_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToWrite); -extern IMU_6AXES_StatusTypeDef LSM6DS0_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToRead); -extern void LSM6DS0_IO_ITConfig( void ); - -/** - * @} - */ - -/* ------------------------------------------------------- */ -/* Here you should declare the internal struct of */ -/* extended features of LIS3MDL. See the example of */ -/* LSM6DS3 in lsm6ds3.h */ -/* ------------------------------------------------------- */ - -/** @addtogroup LSM6DS0_Exported_Variables LSM6DS0_Exported_Variables - * @{ - */ - -/* Six axes sensor driver structure */ -extern IMU_6AXES_DrvTypeDef LSM6DS0Drv; -extern IMU_6AXES_DrvExtTypeDef LSM6DS0Drv_ext; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LSM6DS0_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/Release_Notes.html deleted file mode 100644 index c6ebdd291..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/Release_Notes.html +++ /dev/null @@ -1,195 +0,0 @@ - - - - - -Release Notes for STM32 BlueEnergy Library - - - - - -
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Release Notes for LSM6DS3 component

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Copyright -2015 STMicroelectronics

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Update History

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V1.2.0 -/ 28-May-2015

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Main -Changes

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  • Add output data rate and full scale settings APIs for the Component -
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  • Add LSM6DS3_X_GetAxes and LSM6DS3_G_GetAxes APIs -
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V1.1.0 -/ 11-February-2015

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Main -Changes

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  • Add extended features support for the Component -
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  • Add support for free fall detection feature for the Component -
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V1.0.0 -/ 12-December-2014

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Main -Changes

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  • First -official release
    • -
- - -

License
-

- - -Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

- - -
- http://www.st.com/software_license_agreement_liberty_v2


- -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - - - - - -

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For -complete documentation on STM32 STM BlueNRG -visit www.st.com/BlueNRG

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- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.c b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.c deleted file mode 100644 index 1c1e9e1c7..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.c +++ /dev/null @@ -1,1111 +0,0 @@ -/** - ****************************************************************************** - * @file lsm6ds3.c - * @author MEMS Application Team - * @version V1.2.0 - * @date 28-May-2015 - * @brief This file provides a set of functions needed to manage the LSM6DS3 sensor - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "lsm6ds3.h" -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LSM6DS3 - * @{ - */ - -static IMU_6AXES_StatusTypeDef LSM6DS3_Init( IMU_6AXES_InitTypeDef *LSM6DS3_Init ); -static IMU_6AXES_StatusTypeDef LSM6DS3_Read_XG_ID( uint8_t *xg_id); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxes( int32_t *pData ); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxesRaw(int16_t *pData); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxes( int32_t *pData ); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxesRaw(int16_t *pData); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_ODR( float *odr ); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_ODR( float odr ); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetSensitivity( float *pfData ); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_FS( float *fullScale ); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_FS( float fullScale ); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_ODR( float *odr ); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_ODR( float odr ); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetSensitivity( float *pfData ); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_FS( float *fullScale ); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_FS( float fullScale ); -static IMU_6AXES_StatusTypeDef LSM6DS3_Enable_Free_Fall_Detection( void ); -static IMU_6AXES_StatusTypeDef LSM6DS3_Disable_Free_Fall_Detection( void ); -static IMU_6AXES_StatusTypeDef LSM6DS3_Get_Status_Free_Fall_Detection( uint8_t *status ); - -/** @addtogroup LSM6DS3_Private_Variables LSM6DS3_Private_Variables - * @{ - */ -IMU_6AXES_DrvTypeDef LSM6DS3Drv = -{ - LSM6DS3_Init, - LSM6DS3_Read_XG_ID, - LSM6DS3_X_GetAxes, - LSM6DS3_X_GetAxesRaw, - LSM6DS3_G_GetAxes, - LSM6DS3_G_GetAxesRaw, - LSM6DS3_X_Get_ODR, - LSM6DS3_X_Set_ODR, - LSM6DS3_X_GetSensitivity, - LSM6DS3_X_Get_FS, - LSM6DS3_X_Set_FS, - LSM6DS3_G_Get_ODR, - LSM6DS3_G_Set_ODR, - LSM6DS3_G_GetSensitivity, - LSM6DS3_G_Get_FS, - LSM6DS3_G_Set_FS, - NULL -}; - -LSM6DS3_DrvExtTypeDef LSM6DS3Drv_ext_internal = -{ - - LSM6DS3_Enable_Free_Fall_Detection, - LSM6DS3_Disable_Free_Fall_Detection, - LSM6DS3_Get_Status_Free_Fall_Detection -}; - -IMU_6AXES_DrvExtTypeDef LSM6DS3Drv_ext = -{ - IMU_6AXES_LSM6DS3_DIL24_COMPONENT, /* unique ID for LSM6DS3 in the IMU 6-axes driver class */ - &LSM6DS3Drv_ext_internal /* pointer to internal struct of extended features of LSM6DS3 */ -}; - -/** - * @} - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_Common_Sensor_Enable(void); -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ); - -/** @addtogroup LSM6DS3_Private_Functions LSM6DS3_Private_Functions - * @{ - */ - -/** - * @brief Set LSM6DS3 Initialization - * @param LSM6DS3_Init the configuration setting for the LSM6DS3 - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_Init( IMU_6AXES_InitTypeDef *LSM6DS3_Init ) -{ - /*Here we have to add the check if the parameters are valid*/ - - /* Configure the low level interface -------------------------------------*/ - if(LSM6DS3_IO_Init() != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - - /******** Common init *********/ - - if(LSM6DS3_Common_Sensor_Enable() != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - - /******* Gyroscope init *******/ - - if(LSM6DS3_G_Set_ODR( LSM6DS3_Init->G_OutputDataRate ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_G_Set_FS( LSM6DS3_Init->G_FullScale ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_G_Set_Axes_Status(LSM6DS3_Init->G_X_Axis, LSM6DS3_Init->G_Y_Axis, LSM6DS3_Init->G_Z_Axis) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - - /***** Accelerometer init *****/ - - if(LSM6DS3_X_Set_ODR( LSM6DS3_Init->X_OutputDataRate ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_X_Set_FS( LSM6DS3_Init->X_FullScale ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_X_Set_Axes_Status(LSM6DS3_Init->X_X_Axis, LSM6DS3_Init->X_Y_Axis, LSM6DS3_Init->X_Z_Axis) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Configure interrupt lines */ - LSM6DS3_IO_ITConfig(); - - return IMU_6AXES_OK; -} - -/** - * @brief Read ID of LSM6DS3 Accelerometer and Gyroscope - * @param xg_id the pointer where the ID of the device is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_Read_XG_ID( uint8_t *xg_id) -{ - if(!xg_id) - { - return IMU_6AXES_ERROR; - } - - return LSM6DS3_IO_Read(xg_id, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WHO_AM_I_ADDR, 1); -} - -/** - * @brief Set LSM6DS3 common initialization - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_Common_Sensor_Enable(void) -{ - uint8_t tmp1 = 0x00; - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL3_C, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Enable register address automatically incremented during a multiple byte - access with a serial interface (I2C or SPI) */ - tmp1 &= ~(LSM6DS3_XG_IF_INC_MASK); - tmp1 |= LSM6DS3_XG_IF_INC; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL3_C, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_FIFO_CTRL5, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* FIFO ODR selection */ - tmp1 &= ~(LSM6DS3_XG_FIFO_ODR_MASK); - tmp1 |= LSM6DS3_XG_FIFO_ODR_NA; - - /* FIFO mode selection */ - tmp1 &= ~(LSM6DS3_XG_FIFO_MODE_MASK); - tmp1 |= LSM6DS3_XG_FIFO_MODE_BYPASS; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_FIFO_CTRL5, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read raw data from LSM6DS3 Accelerometer output register - * @param pData the pointer where the accelerometer raw data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxesRaw( int16_t *pData ) -{ - /*Here we have to add the check if the parameters are valid*/ - - uint8_t tempReg[2] = {0, 0}; - - - if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_X_L_XL, 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Y_L_XL, 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Z_L_XL, 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - return IMU_6AXES_OK; -} - - - -/** - * @brief Read data from LSM6DS3 Accelerometer and calculate linear acceleration in mg - * @param pData the pointer where the accelerometer data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetAxes( int32_t *pData ) -{ - /*Here we have to add the check if the parameters are valid*/ - int16_t pDataRaw[3]; - float sensitivity = 0.0f; - - if(LSM6DS3_X_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_X_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = (int32_t)(pDataRaw[0] * sensitivity); - pData[1] = (int32_t)(pDataRaw[1] * sensitivity); - pData[2] = (int32_t)(pDataRaw[2] * sensitivity); - - return IMU_6AXES_OK; -} - - - -/** - * @brief Read raw data from LSM6DS3 Gyroscope output register - * @param pData the pointer where the gyroscope raw data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxesRaw( int16_t *pData ) -{ - /*Here we have to add the check if the parameters are valid*/ - - uint8_t tempReg[2] = {0, 0}; - - - if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_X_L_G, 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Y_L_G, 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[1] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - if(LSM6DS3_IO_Read(&tempReg[0], LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_OUT_Z_L_G, 2) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[2] = ((((int16_t)tempReg[1]) << 8) + (int16_t)tempReg[0]); - - return IMU_6AXES_OK; -} - -/** - * @brief Set the status of the axes for accelerometer - * @param enableX the status of the x axis to be set - * @param enableY the status of the y axis to be set - * @param enableZ the status of the z axis to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) -{ - uint8_t tmp1 = 0x00; - uint8_t eX = 0x00; - uint8_t eY = 0x00; - uint8_t eZ = 0x00; - - eX = ( enableX == 0 ) ? LSM6DS3_XL_XEN_DISABLE : LSM6DS3_XL_XEN_ENABLE; - eY = ( enableY == 0 ) ? LSM6DS3_XL_YEN_DISABLE : LSM6DS3_XL_YEN_ENABLE; - eZ = ( enableZ == 0 ) ? LSM6DS3_XL_ZEN_DISABLE : LSM6DS3_XL_ZEN_ENABLE; - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL9_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Enable X axis selection */ - tmp1 &= ~(LSM6DS3_XL_XEN_MASK); - tmp1 |= eX; - - /* Enable Y axis selection */ - tmp1 &= ~(LSM6DS3_XL_YEN_MASK); - tmp1 |= eY; - - /* Enable Z axis selection */ - tmp1 &= ~(LSM6DS3_XL_ZEN_MASK); - tmp1 |= eZ; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL9_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Set the status of the axes for gyroscope - * @param enableX the status of the x axis to be set - * @param enableY the status of the y axis to be set - * @param enableZ the status of the z axis to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_Axes_Status(uint8_t enableX, uint8_t enableY, uint8_t enableZ) -{ - uint8_t tmp1 = 0x00; - uint8_t eX = 0x00; - uint8_t eY = 0x00; - uint8_t eZ = 0x00; - - eX = ( enableX == 0 ) ? LSM6DS3_G_XEN_DISABLE : LSM6DS3_G_XEN_ENABLE; - eY = ( enableY == 0 ) ? LSM6DS3_G_YEN_DISABLE : LSM6DS3_G_YEN_ENABLE; - eZ = ( enableZ == 0 ) ? LSM6DS3_G_ZEN_DISABLE : LSM6DS3_G_ZEN_ENABLE; - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL10_C, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Enable X axis selection */ - tmp1 &= ~(LSM6DS3_G_XEN_MASK); - tmp1 |= eX; - - /* Enable Y axis selection */ - tmp1 &= ~(LSM6DS3_G_YEN_MASK); - tmp1 |= eY; - - /* Enable Z axis selection */ - tmp1 &= ~(LSM6DS3_G_ZEN_MASK); - tmp1 |= eZ; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL10_C, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read data from LSM6DS3 Gyroscope and calculate angular rate in mdps - * @param pData the pointer where the gyroscope data are stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetAxes( int32_t *pData ) -{ - /*Here we have to add the check if the parameters are valid*/ - int16_t pDataRaw[3]; - float sensitivity = 0.0f; - - if(LSM6DS3_G_GetAxesRaw(pDataRaw) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_G_GetSensitivity( &sensitivity ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - pData[0] = (int32_t)(pDataRaw[0] * sensitivity); - pData[1] = (int32_t)(pDataRaw[1] * sensitivity); - pData[2] = (int32_t)(pDataRaw[2] * sensitivity); - - return IMU_6AXES_OK; -} - -/** - * @brief Read Accelero Output Data Rate - * @param odr the pointer where the accelerometer output data rate is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_ODR( float *odr ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_XL_ODR_MASK; - - switch( tempReg ) - { - case LSM6DS3_XL_ODR_PD: - *odr = 0.0f; - break; - case LSM6DS3_XL_ODR_13HZ: - *odr = 13.0f; - break; - case LSM6DS3_XL_ODR_26HZ: - *odr = 26.0f; - break; - case LSM6DS3_XL_ODR_52HZ: - *odr = 52.0f; - break; - case LSM6DS3_XL_ODR_104HZ: - *odr = 104.0f; - break; - case LSM6DS3_XL_ODR_208HZ: - *odr = 208.0f; - break; - case LSM6DS3_XL_ODR_416HZ: - *odr = 416.0f; - break; - case LSM6DS3_XL_ODR_833HZ: - *odr = 833.0f; - break; - case LSM6DS3_XL_ODR_1660HZ: - *odr = 1660.0f; - break; - case LSM6DS3_XL_ODR_3330HZ: - *odr = 3330.0f; - break; - case LSM6DS3_XL_ODR_6660HZ: - *odr = 6660.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Accelero Output Data Rate - * @param odr the accelerometer output data rate to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_ODR( float odr ) -{ - uint8_t new_odr = 0x00; - uint8_t tempReg = 0x00; - - new_odr = ( odr <= 0.0f ) ? LSM6DS3_XL_ODR_PD /* Power Down */ - : ( odr <= 13.0f ) ? LSM6DS3_XL_ODR_13HZ - : ( odr <= 26.0f ) ? LSM6DS3_XL_ODR_26HZ - : ( odr <= 52.0f ) ? LSM6DS3_XL_ODR_52HZ - : ( odr <= 104.0f ) ? LSM6DS3_XL_ODR_104HZ - : ( odr <= 208.0f ) ? LSM6DS3_XL_ODR_208HZ - : ( odr <= 416.0f ) ? LSM6DS3_XL_ODR_416HZ - : ( odr <= 833.0f ) ? LSM6DS3_XL_ODR_833HZ - : ( odr <= 1660.0f ) ? LSM6DS3_XL_ODR_1660HZ - : ( odr <= 3330.0f ) ? LSM6DS3_XL_ODR_3330HZ - : LSM6DS3_XL_ODR_6660HZ; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS3_XL_ODR_MASK); - tempReg |= new_odr; - - if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Accelero Sensitivity - * @param pfData the pointer where the accelerometer sensitivity is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_GetSensitivity( float *pfData ) -{ - /*Here we have to add the check if the parameters are valid*/ - - uint8_t tempReg = 0x00; - - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_XL_FS_MASK; - - switch( tempReg ) - { - case LSM6DS3_XL_FS_2G: - *pfData = 0.061f; - break; - case LSM6DS3_XL_FS_4G: - *pfData = 0.122f; - break; - case LSM6DS3_XL_FS_8G: - *pfData = 0.244f; - break; - case LSM6DS3_XL_FS_16G: - *pfData = 0.488f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Accelero Full Scale - * @param fullScale the pointer where the accelerometer full scale is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Get_FS( float *fullScale ) -{ - /*Here we have to add the check if the parameters are valid*/ - - uint8_t tempReg = 0x00; - - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_XL_FS_MASK; - - switch( tempReg ) - { - case LSM6DS3_XL_FS_2G: - *fullScale = 2.0f; - break; - case LSM6DS3_XL_FS_4G: - *fullScale = 4.0f; - break; - case LSM6DS3_XL_FS_8G: - *fullScale = 8.0f; - break; - case LSM6DS3_XL_FS_16G: - *fullScale = 16.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Accelero Full Scale - * @param fullScale the accelerometer full scale to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_X_Set_FS( float fullScale ) -{ - uint8_t new_fs = 0x00; - uint8_t tempReg = 0x00; - - new_fs = ( fullScale <= 2.0f ) ? LSM6DS3_XL_FS_2G - : ( fullScale <= 4.0f ) ? LSM6DS3_XL_FS_4G - : ( fullScale <= 8.0f ) ? LSM6DS3_XL_FS_8G - : LSM6DS3_XL_FS_16G; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS3_XL_FS_MASK); - tempReg |= new_fs; - - if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Gyro Output Data Rate - * @param odr the pointer where the gyroscope output data rate is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_ODR( float *odr ) -{ - /*Here we have to add the check if the parameters are valid*/ - uint8_t tempReg = 0x00; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_G_ODR_MASK; - - switch( tempReg ) - { - case LSM6DS3_G_ODR_PD: - *odr = 0.0f; - break; - case LSM6DS3_G_ODR_13HZ: - *odr = 13.0f; - break; - case LSM6DS3_G_ODR_26HZ: - *odr = 26.0f; - break; - case LSM6DS3_G_ODR_52HZ: - *odr = 52.0f; - break; - case LSM6DS3_G_ODR_104HZ: - *odr = 104.0f; - break; - case LSM6DS3_G_ODR_208HZ: - *odr = 208.0f; - break; - case LSM6DS3_G_ODR_416HZ: - *odr = 416.0f; - break; - case LSM6DS3_G_ODR_833HZ: - *odr = 833.0f; - break; - case LSM6DS3_G_ODR_1660HZ: - *odr = 1660.0f; - break; - default: - break; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Gyro Output Data Rate - * @param odr the gyroscope output data rate to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise - */ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_ODR( float odr ) -{ - uint8_t new_odr = 0x00; - uint8_t tempReg = 0x00; - - new_odr = ( odr <= 0.0f ) ? LSM6DS3_G_ODR_PD /* Power Down */ - : ( odr <= 13.0f ) ? LSM6DS3_G_ODR_13HZ - : ( odr <= 26.0f ) ? LSM6DS3_G_ODR_26HZ - : ( odr <= 52.0f ) ? LSM6DS3_G_ODR_52HZ - : ( odr <= 104.0f ) ? LSM6DS3_G_ODR_104HZ - : ( odr <= 208.0f ) ? LSM6DS3_G_ODR_208HZ - : ( odr <= 416.0f ) ? LSM6DS3_G_ODR_416HZ - : ( odr <= 833.0f ) ? LSM6DS3_G_ODR_833HZ - : LSM6DS3_G_ODR_1660HZ; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS3_G_ODR_MASK); - tempReg |= new_odr; - - if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Gyro Sensitivity - * @param pfData the pointer where the gyroscope sensitivity is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_GetSensitivity( float *pfData ) -{ - /*Here we have to add the check if the parameters are valid*/ - - uint8_t tempReg = 0x00; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_G_FS_125_MASK; - - if(tempReg == LSM6DS3_G_FS_125_ENABLE) - { - *pfData = 4.375f; - } - else - { - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_G_FS_MASK; - - switch( tempReg ) - { - case LSM6DS3_G_FS_245: - *pfData = 8.75f; - break; - case LSM6DS3_G_FS_500: - *pfData = 17.50f; - break; - case LSM6DS3_G_FS_1000: - *pfData = 35.0f; - break; - case LSM6DS3_G_FS_2000: - *pfData = 70.0f; - break; - default: - break; - } - } - - return IMU_6AXES_OK; -} - -/** - * @brief Read Gyro Full Scale - * @param fullScale the pointer where the gyroscope full scale is stored - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Get_FS( float *fullScale ) -{ - /*Here we have to add the check if the parameters are valid*/ - - uint8_t tempReg = 0x00; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_G_FS_125_MASK; - - if(tempReg == LSM6DS3_G_FS_125_ENABLE) - { - *fullScale = 125.0f; - } - else - { - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= LSM6DS3_G_FS_MASK; - - switch( tempReg ) - { - case LSM6DS3_G_FS_245: - *fullScale = 245.0f; - break; - case LSM6DS3_G_FS_500: - *fullScale = 500.0f; - break; - case LSM6DS3_G_FS_1000: - *fullScale = 1000.0f; - break; - case LSM6DS3_G_FS_2000: - *fullScale = 2000.0f; - break; - default: - break; - } - } - - return IMU_6AXES_OK; -} - -/** - * @brief Write Gyro Full Scale - * @param fullScale the gyroscope full scale to be set - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS3_G_Set_FS( float fullScale ) -{ - uint8_t new_fs = 0x00; - uint8_t tempReg = 0x00; - - if(fullScale <= 125.0f) - { - new_fs = LSM6DS3_G_FS_125_ENABLE; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS3_G_FS_125_MASK); - tempReg |= new_fs; - - if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - } - else - { - /* Disable G FS 125dpp */ - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS3_G_FS_125_MASK); - tempReg |= LSM6DS3_G_FS_125_DISABLE; - - if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - new_fs = ( fullScale <= 245.0f ) ? LSM6DS3_G_FS_245 - : ( fullScale <= 500.0f ) ? LSM6DS3_G_FS_500 - : ( fullScale <= 1000.0f ) ? LSM6DS3_G_FS_1000 - : LSM6DS3_G_FS_2000; - - if(LSM6DS3_IO_Read( &tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1 ) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tempReg &= ~(LSM6DS3_G_FS_MASK); - tempReg |= new_fs; - - if(LSM6DS3_IO_Write(&tempReg, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL2_G, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - } - - return IMU_6AXES_OK; -} - -/** - * @brief Enable free fall detection - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS3_Enable_Free_Fall_Detection( void ) -{ - uint8_t tmp1 = 0x00; - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* Output Data Rate selection */ - tmp1 &= ~(LSM6DS3_XL_ODR_MASK); - tmp1 |= LSM6DS3_XL_ODR_416HZ; - - /* Full scale selection */ - tmp1 &= ~(LSM6DS3_XL_FS_MASK); - tmp1 |= LSM6DS3_XL_FS_2G; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_CTRL1_XL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_UP_DUR, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* FF_DUR5 setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_MASK); - tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_DEFAULT; - - /* WAKE_DUR setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_MASK); - tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_DEFAULT; - - /* TIMER_HR setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_MASK); - tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_DEFAULT; - - /* SLEEP_DUR setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_MASK); - tmp1 |= LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_DEFAULT; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_UP_DUR, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* FF_DUR setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK); - tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_TYPICAL; - - /* FF_THS setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK); - tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_312MG; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* INT1_FF setting */ - tmp1 &= ~(LSM6DS3_XG_MD1_CFG_INT1_FF_MASK); - tmp1 |= LSM6DS3_XG_MD1_CFG_INT1_FF_ENABLE; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Disable free fall detection - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS3_Disable_Free_Fall_Detection( void ) -{ - uint8_t tmp1 = 0x00; - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* INT1_FF setting */ - tmp1 &= ~(LSM6DS3_XG_MD1_CFG_INT1_FF_MASK); - tmp1 |= LSM6DS3_XG_MD1_CFG_INT1_FF_DISABLE; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_MD1_CFG, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - /* FF_DUR setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK); - tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_DEFAULT; - - /* FF_THS setting */ - tmp1 &= ~(LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK); - tmp1 |= LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_156MG; - - if(LSM6DS3_IO_Write(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_FREE_FALL, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - return IMU_6AXES_OK; -} - -/** - * @brief Get status of free fall detection - * @param status the pointer where the status of free fall detection is stored; 0 means no detection, 1 means detection happened - * @retval IMU_6AXES_OK in case of success, an error code otherwise -*/ -static IMU_6AXES_StatusTypeDef LSM6DS3_Get_Status_Free_Fall_Detection( uint8_t *status ) -{ - uint8_t tmp1 = 0x00; - - if(LSM6DS3_IO_Read(&tmp1, LSM6DS3_XG_MEMS_ADDRESS, LSM6DS3_XG_WAKE_UP_SRC, 1) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - tmp1 &= LSM6DS3_XG_WAKE_UP_SRC_FF_IA_MASK; - - switch( tmp1 ) - { - case LSM6DS3_XG_WAKE_UP_SRC_FF_IA_ENABLE: - *status = 1; - break; - case LSM6DS3_XG_WAKE_UP_SRC_FF_IA_DISABLE: - default: - *status = 0; - break; - } - - return IMU_6AXES_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.h b/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.h deleted file mode 100644 index 72fced378..000000000 --- a/platform/stm32nucleo-spirit1/drivers/sensors/lsm6ds3/lsm6ds3.h +++ /dev/null @@ -1,1481 +0,0 @@ -/** - ****************************************************************************** - * @file lsm6ds3.h - * @author MEMS Application Team - * @version V1.2.0 - * @date 28-May-2015 - * @brief This file contains definitions for the lsm6ds3.c firmware driver - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __LSM6DS3_H -#define __LSM6DS3_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "imu_6axes.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup LSM6DS3 - * @{ - */ - -/** @addtogroup LSM6DS3_Exported_Defines LSM6DS3_Exported_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif - -/******************************************************************************/ -/*********** START ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ -/******************************************************************************/ - - -/***************************************** COMMON REGISTERS ********************************************/ - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7] FUNC_CFG_EN: Enable access to the embedded functions configuration registers (1) from address 02h to 32h. Default value: 0. - * [6:0] This bit must be set to ‘0’ for the correct operation of the device - * \endcode -*/ -#define LSM6DS3_XG_FUNC_CFG_ACCESS 0x01 - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7:0] TPH_[7:0]: Sensor SyncronizationTime Frame with the step of 500ms and full range of 5s. Default: 0000 0000 - * \endcode -*/ -#define LSM6DS3_XG_SENSOR_SYNC_TIME_FRAME 0x04 - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7:2] This bit must be set to ‘0’ for the correct operation of the device - * [1] HP_RST: Gyro digital HP filter reset. Default: 0 - * [1] SENSOR_SYNC_ENHP_RST: Enable sensor synchronization feature. Default 0 - * \endcode -*/ -#define LSM6DS3_XG_SENSOR_SYNC_ENABLE 0x05 - - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7:0] FTH_7-0 FIFO threshold level setting - watermark flag is toggled when the number of bytes written to FIFO is greater or equal to threshold level. - * \endcode -*/ -#define LSM6DS3_XG_FIFO_CTRL1 0x06 - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7] TIMER_PEDO_FIFO_EN: Enable Pedometer step counter and time stamp as 4th sensor FIFO data. Default: 0 disabled - * [6] TIMER_PEDO_FIFO_DRDY : Pedometer FIFO write mode. Default: 0 disabled - * [5:4] This bit must be set to ‘0’ for the correct operation of the device - * [3:0] FTH_[11:8] FIFO threshold level setting(1). Default value: 0000 - * \endcode -*/ -#define LSM6DS3_XG_FIFO_CTRL2 0x07 - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7:6] This bit must be set to ‘0’ for the correct operation of the device - * [5:3] DEC_FIFO_GYRO[2:0]: Gyro FIFO decimation setting. Default value: 000 - * [2:0] DEC_FIFO_XL[2:0]: XL FIFO decimation setting. Default value: 000 - * \endcode -*/ -#define LSM6DS3_XG_FIFO_CTRL3 0x08 - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7] This bit must be set to ‘0’ for the correct operation of the device - * [6] ONLY_HIGH_DATA :8 bit data storing in FIFO. Default: 0 - * [5:3] DEC_SLV1_FIFO[2:0] Second external sensor FIFO decimation setting. Default: 000 - * [2:0] DEC_SLV1_FIFO[2:0] First external sensor FIFO decimation setting. Default: 000 - * \endcode -*/ -#define LSM6DS3_XG_FIFO_CTRL4 0x09 - - -/** - * @brief FIFO control register - * \code - * Read/write - * Default value: 0x00 - * [7] This bit must be set to ‘0’ for the correct operation of the device - * [6:3] ODR_FIFO_[3:0]: FIFO ODR selection. Default: 0000 - * [2:0] FIFO_MODE_[2:0] : FIFO mode selection bits. Default value: 000 - * \endcode -*/ -#define LSM6DS3_XG_FIFO_CTRL5 0x0A - - -/** - * @brief Angular rate sensor sign and orientation register - * \code - * Read/write - * Default value: 0x00 - * [7:6] This bit must be set to ‘0’ for the correct operation of the device - * [5] SignX_G: Pitch axis (X) Angular rate sign. Default value: 0 - * [5] SignY_G: Roll axis (Y) Angular rate sign. Default value: 0 - * [5] SignZ_G: Pitch axis (Z) Angular rate sign. Default value: 0 - * [2:0] Orient[2:0] : Directional user orientation selection. Default Value: 000 - * \endcode -*/ -#define LSM6DS3_XG_ORIENT_CFG_G 0x0B - -/** - * @brief INT1 pad control registrer - * \code - * Read/write - * Default value: 0x00 - * [7] INT1_PEDO: Pedometer step recognition interrupt enable on INT1 pad. Default value: 0 - * [6] INT1_SIGN_MOT: Significant motion interrupt enable on INT1 pad. Default value: 0 - * [5] INT1_FULL_FLAG: Full flag Interrupt Enable on INT1 pad. Default value: 0 - * [4] INT1_OVR: Overrun Interrupt on INT1 pad. Default value: 0 - * [3] INT1_FTH: FIFO threshold interrupt on INT1 pad. Default value: 0 - * [2] INT1_BOOT: Overrun Interrupt on INT1 pad. Default value: 0 - * [1] INT1_DRDY_G: Gyroscope Data Ready on INT1 pad. Default value: 0. - * [0] INT1_DRDY_XL: Accelerometer Data Ready on INT1 pad. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_INT1_CTRL 0x0D - - -//new, done -/** - * @brief INT2 pad control registrer - * \code - * Read/write - * Default value: 0x00 - * [7] INT2_PEDO: Pedometer step recognition interrupt enable on INT1 pad. Default value: 0 - * [6] INT2_SIGN_MOT: Significant motion interrupt enable on INT1 pad. Default value: 0 - * [5] INT2_FULL_FLAG: Full flag Interrupt Enable on INT1 pad. Default value: 0 - * [4] INT2_OVR: Overrun Interrupt on INT1 pad. Default value: 0 - * [3] INT2_FTH: FIFO threshold interrupt on INT1 pad. Default value: 0 - * [2] INT2_BOOT: Overrun Interrupt on INT1 pad. Default value: 0 - * [1] INT2_DRDY_G: Gyroscope Data Ready on INT1 pad. Default value: 0. - * [0] INT2_DRDY_XL: Accelerometer Data Ready on INT1 pad. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_INT2_CTRL 0x0E - - -/** - * @brief Device identifier register. - * \code - * Read - * Default value:69 - * [7:0] This read-only register contains the device identifier - * \endcode -*/ -#define LSM6DS3_XG_WHO_AM_I_ADDR 0x0F - - -/** - * @brief Control Register 3 - * \code - * Read/write - * Default value: 0x00 - * [7] BOOT: Reboot memory content. Default value: 0 - * [6] BDU: Block Data Update. Default value: 0 - * [5] H_LACTIVE: Interrupt activation level. Default value: 0 - * [4] PP_OD: Push-pull/Open Drain selection on INT pad. Default value: 0 - * [3] SIM: SPI Serial Interface Mode selection. Default value: 0 - * [2] IF_INC: Register address automatically incremented during a multiple byte access with a serial interface (I2C or SPI). Default value: 0 - * [1] BLE: Big/Little Endian Data Selection. Default value: 0 - * [0] SW_RESET: Software Reset. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_CTRL3_C 0x12 - -/** - * @brief Control Register 4 - * \code - * Read/write - * Default value: 0x00 - * [7] BW_SCAL_ODR: Accelerometer bandwidth selection. Default value: 0 - * [6] SLEEP_G: Gyroscope sleep mode enable. Default value: 0 - * [5] INT2_on_INT1: All interrupt signals available on INT1 pad enable. Default value: 0 - * [4] This bit must be set to ‘0’ for the correct operation of the device - * [3] DRDY_MASK: Configuration 1(3) Data Available Enable bit. Default Value: 0 - * [2] I2C_disable Disable I2C interface. Default value: 0 - * [1] MODE3_EN Enable auxiliary SPI interface (Mode3, refer to Table 1.). Default value: 0 - * [0] STOP_ON_FTH Enable FIFO threshold level use. Default value: 0. - - * \endcode -*/ -#define LSM6DS3_XG_CTRL4_C 0x13 - -/** - * @brief Control Register 4 - * \code - * Read/write - * Default value: 0x00 - * [7:4] This bit must be set to ‘0’ for the correct operation of the device - * [3:2] ST_G[1:0]: Angular rate sensor Self Test Enable. Default value: 00 - * [1:0] ST_XL[1:0]: Linear acceleration sensor Self Test Enable. Default value: 00 - * \endcode -*/ -#define LSM6DS3_XG_CTRL5_C 0x14 - - -/** - * @brief Control Register 10 - * \code - * Read/write - * Default value: 0x38 - * [7:6] These bits must be set to ‘0’ for the correct operation of the device - * [5] Zen_G: Gyroscope’s Z-axis output enable. Default value: 1 - * [4] Yen_G: Gyroscope’s Y-axis output enable. Default value: 1 - * [3] Xen_G: Gyroscope’s X-axis output enable. Default value: 1 - * [2] FUNC_EN: Enable embedded functionalities (pedometer, tilt and significant motion) . Default value: 0 - * [1] PEDO_RST_STEP: Reset pedometer step counter . Default value: 0 - * [0] SIGN_MOTION_EN: Enable significant motion function. For a correct functionality of significant motion function, TILT_EN bit in FUNC_SRC (53h) register must be set to 1 . Default value: 1 - * \endcode -*/ -#define LSM6DS3_XG_CTRL10_C 0x19 - - -/** - * @brief Sensor hub Master config Register - * \code - * Read/write - * Default value: 0x00 - * [7] DRDY_ON_INT1:Manage the DRDY signal on INT1 pad. Default: 0 - * [6] DATA_VALID_SEL_FIFO: Selection of FIFO data-valid signal. Default value: 0 - * [5] This bit must be set to ‘0’ for the correct operation of the device - * [4] START_CONFIG: Sensor Hub trigger signal selection. Default value: 0 - * [3] PULL_UP_EN: Auxiliary I2C pull-up. Default value: 0 - * [2] PASS_THROUGH_MODE: I2C interface pass-through. Default value: 0 - * [1] IRON_EN:Enable soft iron correction algorithm for magnetometer. Default value: 0. - * [0] MASTER_ON: Sensor Hub I2C master enable. Default: 0 - * \endcode -*/ -#define LSM6DS3_XG_MASTER_CONFIG 0x1A - - -/** - * @brief Wake up interrupt source register - * \code - * Read - * Default value: output - * [7:6] This bit must be set to ‘0’ for the correct operation of the device - * [5] FF_IA: Free fall event detection status. Default: 0 - * [4] SLEEP_STATE_IA: Sleep event status. Default value: 0 - * [3] WU_IA: Wake up event detection status. Default - * [2] X_WU: detection status on X axis. Default value: 0 - * [1] Y_WU: detection status on Y axis. Default value: 0 - * [0] Z_WU: detection status on Z axis. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_WAKE_UP_SRC 0x1B - -/** - * @brief Tap source register - * \code - * Read - * Default value: output - * [7] This bit must be set to ‘0’ for the correct operation of the device - * [6] TAP_IA: Tap event detection status. Default: 0 - * [5] SINGLE_TAP: Single tap event status. Default value: 0 - * [4] DOUBLE_TAP: Double tap event detection status. Default value: 0 - * [3] TAP_SIGN: Sign of acceleration detected by tap event. Default: 0 - * [2] X_TAP: Tap event detection status on X axis. Default value: 0 - * [1] Y_TAP: Tap event detection status on Y axis. Default value: 0 - * [0] Z_TAP: Tap event detection status on Z axis. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_TAP_SRC 0x1C - -/** - * @brief Portrait, landscape face-up and face-down source register - * \code - * Read - * Default value: output - * [7] This bit must be set to ‘0’ for the correct operation of the device - * [6] D6D_IA: Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0 - * [5] ZH: Z-axis high event (over-threshold). Default value: 0 - * [4] ZL: Z-axis low event (under-threshold). Default value: 0 - * [5] YH: Y-axis high event (over-threshold). Default value: 0 - * [4] YL: Y-axis low event (under-threshold). Default value: 0 - * [5] X_H: X-axis high event (over-threshold). Default value: 0 - * [4] X_L: X-axis low event (under-threshold). Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_D6D_SRC 0x1D - -/** - * @brief Status register - * \code - * Read - * Default value: output - * [7:4] No meaning set - * [3] EV_BOOT: Boot running flag signal. Default value: 0 - * [2] No meaning set - * [1] GDA: Gyroscope new data avaialble. Default value: 0 - * [0] XLDA: Accelerometer new data avaialble. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_STATUS_REG 0x1E - -/** - * @brief FIFO status control register - * \code - * Read - * Default value: 0x00 - * [7:0] DIFF_FIFO_[7:0]: Number of unread words (16 bit axes) stored in FIFO . For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS2 (3Bh) - * \endcode -*/ -#define LSM6DS3_XG_FIFO_STATUS1 0x3A - -/** - * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. - * \code - * Read - * Default value: 0x00 - * [7] FTH FIFO watermark status. Deafult value: 0 - * [6] OVER_RUN: FIFO overrun status. Default value: 0 - * [5] FIFO_FULL: FIFO full status. Default value: 0 - * [5] FIFO_EMPTY: FIFO empty bit. Default value: 0; 0: FIFO contains data; 1: FIFO is empty - * [3:0] DIFF_FIFO_[11:8] Number of unread words (16 bit axes) stored in FIFO : For a complete number of unread samples, consider DIFF_FIFO [11:8] in FIFO_STATUS1 (3Ah) - * \endcode -*/ -#define LSM6DS3_XG_FIFO_STATUS2 0x3B - -/** - * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0 - * \code - * Read - * Default value: 0x00 - * [7:0] FIFO_PATTERN_[7:0] : Word of recursive pattern read at the next reading - * \endcode -*/ -#define LSM6DS3_XG_FIFO_STATUS3 0x3C - -/** - * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0 - * \code - * Read - * Default value: 0x00 - * [1:0] FIFO_PATTERN_[9:8] : Word of recursive pattern read at the next reading - * \endcode -*/ -#define LSM6DS3_XG_FIFO_STATUS4 0x3D - -/** - * @brief FIFO status control register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. - * \code - * Read - * Default value: 0x00 - * [4:0] FIFO_PATTERN_[9:8] : Word of recursive pattern read at the next reading - * \endcode -*/ -#define LSM6DS3_XG_FIFO_STATUS4 0x3D - -/** - * @brief FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. - * \code - * Read - * Default value: 0x00 - * [7:0] DATA_OUT_FIFO_L_[7:0]: FIFO data output (First byte) - * \endcode -*/ -#define LSM6DS3_XG_FIFO_DATA_OUT_L 0x3E - -/** - * @brief FIFO data output register (r). For a proper reading of the register it is suggested to set BDU bit in CTRL3_C (12h) to 0. - * \code - * Read - * Default value: 0x00 - * [7:0] DATA_OUT_FIFO_H_[7:0]: FIFO data output (second byte) - * \endcode -*/ -#define LSM6DS3_XG_FIFO_DATA_OUT_H 0x3F - -/** - * @brief Time stamp first byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). - * \code - * Read - * Default value: output - * [7:0] TIMESTAMP0_[7:0]: FIFO first byte data output - * \endcode -*/ -#define LSM6DS3_XG_TIMESTAMP0_REG 0x40 - -/** - * @brief Time stamp second byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). - * \code - * Read - * Default value: output - * [7:0] TIMESTAMP1_[7:0]: FIFO second byte data output - * \endcode -*/ -#define LSM6DS3_XG_TIMESTAMP1_REG 0x41 - -/** - * @brief Time stamp third byte data output register (r). The value is expressed as 24 bit and the bit resolution is defined by setting value in WAKE_UP_DUR (5Ch). - * \code - * Read - * Default value: output - * [7:0] TIMESTAMP2_[7:0]: FIFO third byte data output - * \endcode -*/ -#define LSM6DS3_XG_TIMESTAMP2_REG 0x42 - -/** - * @brief Step counter output register (r). - * \code - * Read - * Default value: output - * [7:0] STEP_COUNTER_L_[7:0]: Step counter output (LSbyte) - * \endcode -*/ -#define LSM6DS3_XG_STEP_COUNTER_L 0x4B - -/** - * @brief Step counter output register (r). - * \code - * Read - * Default value: output - * [7:0] STEP_COUNTER_H_[7:0]: Step counter output (MSbyte) - * \endcode -*/ -#define LSM6DS3_XG_STEP_COUNTER_H 0x4C - -/** - * @brief Significant motion, tilt, step detector, soft iron and sensor hub interrupt source register - * \code - * Read - * Default value: output - * [7] This bit must be set to ‘0’ for the correct operation of the device - * [6] SIGN_MOTION_IA: Significant motion event detection status. Default value: 0 - * [5] TILT_IA: Tilt event detection status. Default value: 0 - * [5] STEP_DETECTED: Step detector event detection status. Default value: 0 - * [3:2] This bit must be set to ‘0’ for the correct operation of the device - * [1] SI_END_OP:Soft iron calculation status. Default value: 0 - * [0] SENSORHUB_END_OP:Senso hub communication status. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_FUNC_SRC 0x53 - -/** - * @brief Time stamp, pedometer, tilt, filtering, and tap recognition functions configuration register - * \code - * Read/write - * Default value: 0x00 - * [7] TIMER_EN: Time stamp count enable, output data are collected in TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h), TIMESTAMP2_REG (42h) register. Default: 0 - * [6] PEDO_EN: Pedometer algorithm enable(1). Default value: 0 - * [5] TILT_EN: Tilt calculation enable.(2) Default value: 0 - * [4] This bit must be set to ‘0’ for the correct operation of the device - * [3] TAP_X_EN: Enable X direction in tap recognition. Default value: 0 - * [2] TAP_Y_EN: Enable Z direction in tap recognition. Default value: 0 - * [1] TAP_Z_EN: Enable Z direction in tap recognition. Default value: 0 - * [0] LIR: Relatch of the time stamp, pedometer, tilt, filtering, and tap recognition functions routed to PINs. - * \endcode -*/ -#define LSM6DS3_XG_TAP_CFG 0x58 - -/** - * @brief Portrait/landscape position and tap function threshold register - * \code - * Read/write - * Default value: 0x00 - * [7] This bit must be set to ‘0’ for the correct operation of the device - * [6:5] SIXD_THS[1:0]: Threshold for D6D function. Default value: 00 - * [4:0] TAP_THS[4:0]: Threshold for tap recognition. Default value: 0000 - * \endcode -*/ -#define LSM6DS3_XG_TAP_THS_6D 0x59 - -/** - * @brief Tap recognition function setting register (r/w) - * \code - * Read/write - * Default value: 0x00 - * [7:4] DUR[3:0]: Duration of maximum time gap for double tap recognition. Default: 0000 - * [3:2] QUIET[1:0]: Expected quiet time after a tap detection. Default value: 00 - * [1:0] SHOCK[1:0]: Maximum duration of over-threshold event. Default value: 00 - * \endcode -*/ -#define LSM6DS3_XG_INT_DUR2 0x5A - -/** - * @brief Tap recognition function setting register - * \code - * Read/write - * Default value: 0x00 - * [7] SINGLE_DOUBLE_TAP: Single/double tap event detection. Default: 0 - * [6] INACTIVITY: Inactivity event enable. Default value: 0 - * [5:0] WK_THS[5:0]:Threshold for wake-up. Default value: 0000 - * \endcode -*/ -#define LSM6DS3_XG_WAKE_UP_THS 0x5B - -/** - * @brief Free-fall, wake-up, time stamp and sleep mode functions duration setting register (r/w). - * \code - * Read/write - * Default value: 0x00 - * [7] FF_DUR5:Free fall duration event. Default: 0 - * [6:5] WAKE_DUR[1:0]: Wake up duration event. Default: 00 - * [4] TIMER_HR: Time stamp register resolution setting(1). Default value: 0 - * [3:0] SLEEP_DUR[3:0] : Duration to go in sleep mode. Default value: 0000 - * \endcode -*/ -#define LSM6DS3_XG_WAKE_UP_DUR 0x5C - -/** - * @brief Free-fall function duration setting register - * \code - * Read/write - * Default value: 0x00 - * [7:3] FF_DUR[4:0]: Free fall duration event. Default: 0. For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch) configuration - * [2:0] FF_THS[2:0]: Free fall threshold setting. Default: 000. - * \endcode -*/ -#define LSM6DS3_XG_WAKE_FREE_FALL 0x5D - -/** - * @brief Functions routing on INT1 register - * \code - * Read/write - * Default value: 0x00 - * [7] INT1_INACT_STATE: Routing on INT1 of inactivity mode. Default: 0 - * [6] INT1_SINGLE_TAP: Single tap recognition routing on INT1. Default: 0 - * [5] INT1_WU: Routing of wake-up event on INT1. Default value: 0 - * [4] INT1_FF: Routing of free-fall event on INT1. Default value: 0 - * [3] INT1_TAP: Routing of tap event on INT1. Default value: 0 - * [2] INT1_6D: Routing of 6D event on INT1. Default value: 0 - * [1] INT1_TILT: Routing of tilt event on INT1. Default value: 0 - * [0] INT1_TIMER: Routing of end counter event of timer on INT1. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_MD1_CFG 0x5E - -/** - * @brief Functions routing on INT2 register - * \code - * Read/write - * Default value: 0x00 - * [7] INT2_INACT_STATE: Routing on INT1 of inactivity mode. Default: 0 - * [6] INT2_SINGLE_TAP: Single tap recognition routing on INT1. Default: 0 - * [5] INT2_WU: Routing of wake-up event on INT1. Default value: 0 - * [4] INT2_FF: Routing of free-fall event on INT1. Default value: 0 - * [3] INT2_TAP: Routing of tap event on INT1. Default value: 0 - * [2] INT2_6D: Routing of 6D event on INT1. Default value: 0 - * [1] INT2_TILT: Routing of tilt event on INT1. Default value: 0 - * [0] INT2_TIMER: Routing of end counter event of timer on INT1. Default value: 0 - * \endcode -*/ -#define LSM6DS3_XG_MD2_CFG 0x5F - -/***************************************** SENSORHUB REGISTERS ********************************************/ - -/** - * @brief SENSORHUB REGISTER 1 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB1[7:0]: SLV0 first external sensor, first byte of the first axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB1_REG 0x2E - -/** - * @brief SENSORHUB REGISTER 2 : SLV0 first external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB2[7:0]: SLV0 first external sensor, second byte of the first axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB2_REG 0x2F - -/** - * @brief SENSORHUB REGISTER 3 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB3[7:0]: SLV0 first external sensor, first byte of the second axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB3_REG 0x30 - -/** - * @brief SENSORHUB REGISTER 4 : SLV0 first external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB4[7:0]: SLV0 first external sensor, second byte of the second axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB4_REG 0x31 - -/** - * @brief SENSORHUB REGISTER 5 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB5[7:0]: SLV0 first external sensor, second byte of the second axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB5_REG 0x32 - -/** - * @brief SENSORHUB REGISTER 6 : SLV0 first external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB6[7:0]: SLV0 first external sensor, second byte of the third axis - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB6_REG 0x33 - -/** - * @brief SENSORHUB REGISTER 7 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB7[7:0]: SLV1 second external sensor, first byte of the first axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB7_REG 0x34 - -/** - * @brief SENSORHUB REGISTER 8 : SLV1 second external sensor, first axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB8[7:0]: SLV1 second external sensor, second byte of the first axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB8_REG 0x35 - -/** - * @brief SENSORHUB REGISTER 9 : SLV1 second external sensor,, second axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB9[7:0]: SLV1 second external sensor, first byte of the second axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB9_REG 0x36 - -/** - * @brief SLV1 second external sensor, second axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB10[7:0]: SLV1 second external sensor, second byte of the second axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB10_REG 0x37 - -/** - * @brief SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB11[7:0]: SLV1 second external sensor, first byte of the third axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB11_REG 0x38 - -/** - * @brief SLV1 second external sensor, third axis output register (r). The value is expressed as 16bit word in two’s complement - * \code - * Read - * Default value: 0x00 - * [7:0] SHUB12[7:0]: SLV1 second external sensor, second byte of the third axis. - * \endcode -*/ -#define LSM6DS3_XG_SENSORHUB12_REG 0x39 - - - - -/***************************************** GYROSCOPE REGISTERS ********************************************/ - -/** - * @brief Angular rate sensor Control Register 2 - * \code - * Read/write - * Default value: 0x00 - * [7:4] ODR_G[3:0]: Gyroscope output data rate selection - * [3:2] FS_G[1-0]: Gyroscope full-scale selection - * [1] FS_125: Gyroscope full-scale at 125 dps - * [0] This bit must be set to ‘0’ for the correct operation of the device - * \endcode - */ -#define LSM6DS3_XG_CTRL2_G 0x11 - - -/** - * @brief Angular rate sensor Control Register 6 - * \code - * Read/write - * Default value: 0x00 - * [7] TRIG_EN: Data edge sensitive trigger Enable. Default value: 0 - * [6] LVLen: Data level sensitive trigger Enable. Default value: 0 - * [5] LVL2en: Level sensitive latched Enable. Default value: 0 - * [4] XL_H_MODE: High Performance operating mode disable for accelerometer(1). Default value: 0 - * [3:0] This bit must be set to ‘0’ for the correct operation of the device - * \endcode - */ -#define LSM6DS3_XG_CTRL6_G 0x15 - - -/** -* @brief Angular rate sensor Control Register 7 -* \code -* Read/write -* Default value: 0x00 -* [7] G_H_MODE: High Performance operating mode disable for Gyroscope(1) . Default: 0 -* [6] HP_EN: High Pass filter Enable. Default Value: 0 -* [5:4] HPCF_G[1:0]: Gyroscope High Pass filter Cut Off frequency selection. Default value: 00 -* [3:0] This bit must be set to ‘0’ for the correct operation of the device -* \endcode -*/ -#define LSM6DS3_XG_CTRL7_G 0x16 - -/** - * @brief Gyroscope data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_X_L_G 0x22 - - -/** - * @brief Gyroscope data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_X_H_G 0x23 - - -/** - * @brief Gyroscope data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Y_L_G 0x24 - - -/** - * @brief Gyroscope data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Y_H_G 0x25 - - -/** - * @brief Gyroscope data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Z_L_G 0x26 - - -/** - * @brief Gyroscope data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Z_H_G 0x27 - - - -/*************************************** ACCELEROMETER REGISTERS *******************************************/ - -/** - * @brief Linear acceleration sensor Control Register 1 - * \code - * Read/write - * Default value: 0x00 - * [7:4] ODR_XL3-0: Accelerometer Output data rate and power mode selection - * [3:2] FS_XL1-0: Accelerometer full-scale selection - * [1:0] BW_XL1-0: Anti-aliasing filter bandwidth selection - * \endcode - */ -#define LSM6DS3_XG_CTRL1_XL 0x10 - -/** -* @brief XL sensor Control Register 8 -* \code -* Read/write -* Default value: 0x00 -* [7:3] This bit must be set to ‘0’ for the correct operation of the device -* [2] SLOPE_FDS: Enable HP filter on output registers and FIFO. Default value: 0 -* [1:0] This bit must be set to ‘0’ for the correct operation of the device -* \endcode -*/ -#define LSM6DS3_XG_CTRL8_XL 0x17 - -/** - * @brief Linear acceleration sensor Control Register 9 - * \code - * Read/write - * Default value: 0x38 - * [7:6] These bits must be set to ‘0’ for the correct operation of the device - * [5] Zen_XL: Accelerometers’s Z-axis output enable - * [4] Yen_XL: Accelerometers’s Y-axis output enable - * [3] Xen_XL: Accelerometers’s X-axis output enable - * [2:0] These bits must be set to ‘0’ for the correct operation of the device - * \endcode -*/ -#define LSM6DS3_XG_CTRL9_XL 0x18 - - -/** - * @brief Accelerometer data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_X_L_XL 0x28 - - -/** - * @brief Accelerometer data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_X_H_XL 0x29 - - -/** - * @brief Accelerometer data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Y_L_XL 0x2A - - -/** - * @brief Accelerometer data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Y_H_XL 0x2B - - -/** - * @brief Accelerometer data (LSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Z_L_XL 0x2C - - -/** - * @brief Accelerometer data (MSB) - * \code - * Read - * \endcode - */ -#define LSM6DS3_XG_OUT_Z_H_XL 0x2D - -/******************************************************************************/ -/************* END ACCELEROMETER AND GYROSCOPE REGISTER MAPPING **************/ -/******************************************************************************/ - - -/************************************** COMMON REGISTERS VALUE *******************************************/ - -/** -* @brief Device Address -*/ -#define LSM6DS3_ADDRESS_LOW 0xD4 // SAD[0] = 0 -#define LSM6DS3_ADDRESS_HIGH 0xD6 // SAD[0] = 1 -#define LSM6DS3_XG_MEMS_ADDRESS LSM6DS3_ADDRESS_LOW // SAD[0] = 0 - - -/** - * @brief Device Identifier. Default value of the WHO_AM_I register. - */ -#define I_AM_LSM6DS3_XG ((uint8_t)0x69) - - -/** - * @brief Register address automatically incremented during a multiple byte - * access with a serial interface (I2C or SPI). Default value of the - * LSM6DS3_XG_CTRL3_C register. - */ -#define LSM6DS3_XG_IF_INC ((uint8_t)0x04) - -#define LSM6DS3_XG_IF_INC_MASK ((uint8_t)0x04) - -/** @defgroup LSM6DS3_XG_FIFO_Output_Data_Rate_Selection_FIFO_CTRL5 LSM6DS3_XG_FIFO_Output_Data_Rate_Selection_FIFO_CTRL5 - * @{ - */ -#define LSM6DS3_XG_FIFO_ODR_NA ((uint8_t)0x00) /*!< FIFO ODR NA */ -#define LSM6DS3_XG_FIFO_ODR_10HZ ((uint8_t)0x08) /*!< FIFO ODR 10Hz */ -#define LSM6DS3_XG_FIFO_ODR_25HZ ((uint8_t)0x10) /*!< FIFO ODR 25Hz */ -#define LSM6DS3_XG_FIFO_ODR_50HZ ((uint8_t)0x18) /*!< FIFO ODR 50Hz */ -#define LSM6DS3_XG_FIFO_ODR_100HZ ((uint8_t)0x20) /*!< FIFO ODR 100Hz */ -#define LSM6DS3_XG_FIFO_ODR_200HZ ((uint8_t)0x28) /*!< FIFO ODR 200Hz */ -#define LSM6DS3_XG_FIFO_ODR_400HZ ((uint8_t)0x30) /*!< FIFO ODR 400Hz */ -#define LSM6DS3_XG_FIFO_ODR_800HZ ((uint8_t)0x38) /*!< FIFO ODR 800Hz */ -#define LSM6DS3_XG_FIFO_ODR_1600HZ ((uint8_t)0x40) /*!< FIFO ODR 1600Hz */ -#define LSM6DS3_XG_FIFO_ODR_3300HZ ((uint8_t)0x48) /*!< FIFO ODR 3300Hz */ -#define LSM6DS3_XG_FIFO_ODR_6600HZ ((uint8_t)0x50) /*!< FIFO ODR 6600Hz */ - -#define LSM6DS3_XG_FIFO_ODR_MASK ((uint8_t)0x78) -/** - * @} - */ - -/** @defgroup LSM6DS3_XG_FIFO_Mode_Selection_FIFO_CTRL5 LSM6DS3_XG_FIFO_Mode_Selection_FIFO_CTRL5 - * @{ - */ -#define LSM6DS3_XG_FIFO_MODE_BYPASS ((uint8_t)0x00) /*!< BYPASS Mode. FIFO turned off */ -#define LSM6DS3_XG_FIFO_MODE_FIFO ((uint8_t)0x01) /*!< FIFO Mode. Stop collecting data when FIFO is full */ -#define LSM6DS3_XG_FIFO_MODE_CONTINUOUS_THEN_FIFO ((uint8_t)0x03) /*!< CONTINUOUS mode until trigger is deasserted, then FIFO mode */ -#define LSM6DS3_XG_FIFO_MODE_BYPASS_THEN_CONTINUOUS ((uint8_t)0x04) /*!< BYPASS mode until trigger is deasserted, then CONTINUOUS mode */ -#define LSM6DS3_XG_FIFO_MODE_CONTINUOUS_OVERWRITE ((uint8_t)0x05) /*!< CONTINUOUS mode. If the FIFO is full the new sample overwrite the older one */ - -#define LSM6DS3_XG_FIFO_MODE_MASK ((uint8_t)0x07) -/** - * @} - */ - - -/************************************** GYROSCOPE REGISTERS VALUE *******************************************/ - - -/** @addtogroup LSM6DS3_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G LSM6DS3_XG_Gyroscope_Output_Data_Rate_Selection_CTRL_REG1_G - * @{ - */ -#define LSM6DS3_G_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ -#define LSM6DS3_G_ODR_13HZ ((uint8_t)0x10) /*!< Output Data Rate: 13 Hz*/ -#define LSM6DS3_G_ODR_26HZ ((uint8_t)0x20) /*!< Output Data Rate: 26 Hz*/ -#define LSM6DS3_G_ODR_52HZ ((uint8_t)0x30) /*!< Output Data Rate: 52 Hz */ -#define LSM6DS3_G_ODR_104HZ ((uint8_t)0x40) /*!< Output Data Rate: 104 Hz */ -#define LSM6DS3_G_ODR_208HZ ((uint8_t)0x50) /*!< Output Data Rate: 208 Hz */ -#define LSM6DS3_G_ODR_416HZ ((uint8_t)0x60) /*!< Output Data Rate: 416 Hz */ -#define LSM6DS3_G_ODR_833HZ ((uint8_t)0x70) /*!< Output Data Rate: 833 Hz */ -#define LSM6DS3_G_ODR_1660HZ ((uint8_t)0x80) /*!< Output Data Rate: 1.66 kHz */ - -#define LSM6DS3_G_ODR_MASK ((uint8_t)0xF0) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Gyroscope_Full_Scale_Selection_CTRL2_G LSM6DS3_XG_Gyroscope_Full_Scale_Selection_CTRL2_G - * @{ - */ -#define LSM6DS3_G_FS_125_DISABLE ((uint8_t)0x00) /*!< Full scale: 125 dps enable: disable */ -#define LSM6DS3_G_FS_125_ENABLE ((uint8_t)0x02) /*!< Full scale: 125 dps enable: enable */ - -#define LSM6DS3_G_FS_125_MASK ((uint8_t)0x02) - -#define LSM6DS3_G_FS_245 ((uint8_t)0x00) /*!< Full scale: 245 dps*/ -#define LSM6DS3_G_FS_500 ((uint8_t)0x04) /*!< Full scale: 500 dps */ -#define LSM6DS3_G_FS_1000 ((uint8_t)0x08) /*!< Full scale: 1000 dps */ -#define LSM6DS3_G_FS_2000 ((uint8_t)0x0C) /*!< Full scale: 2000 dps */ - -#define LSM6DS3_G_FS_MASK ((uint8_t)0x0C) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_Z_Axis_Output_Enable_Selection_CTRL10_C - * @{ - */ -#define LSM6DS3_G_ZEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Z-axis output enable: disable */ -#define LSM6DS3_G_ZEN_ENABLE ((uint8_t)0x20) /*!< Gyroscope’s Z-axis output enable: enable */ - -#define LSM6DS3_G_ZEN_MASK ((uint8_t)0x20) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_Y_Axis_Output_Enable_Selection_CTRL10_C - * @{ - */ -#define LSM6DS3_G_YEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s Y-axis output enable: disable */ -#define LSM6DS3_G_YEN_ENABLE ((uint8_t)0x10) /*!< Gyroscope’s Y-axis output enable: enable */ - -#define LSM6DS3_G_YEN_MASK ((uint8_t)0x10) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL10_C LSM6DS3_XG_Gyroscope_X_Axis_Output_Enable_Selection_CTRL10_C - * @{ - */ -#define LSM6DS3_G_XEN_DISABLE ((uint8_t)0x00) /*!< Gyroscope’s X-axis output enable: disable */ -#define LSM6DS3_G_XEN_ENABLE ((uint8_t)0x08) /*!< Gyroscope’s X-axis output enable: enable */ - -#define LSM6DS3_G_XEN_MASK ((uint8_t)0x08) - -/** - * @} - */ - - -/************************************ ACCELEROMETER REGISTERS VALUE *****************************************/ - -/** @addtogroup LSM6DS3_XG_Accelerometer_Output_Data_Rate_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Output_Data_Rate_Selection_CTRL1_XL - * @{ - */ -#define LSM6DS3_XL_ODR_PD ((uint8_t)0x00) /*!< Output Data Rate: Power-down*/ -#define LSM6DS3_XL_ODR_13HZ ((uint8_t)0x10) /*!< Output Data Rate: 13 Hz*/ -#define LSM6DS3_XL_ODR_26HZ ((uint8_t)0x20) /*!< Output Data Rate: 26 Hz*/ -#define LSM6DS3_XL_ODR_52HZ ((uint8_t)0x30) /*!< Output Data Rate: 52 Hz */ -#define LSM6DS3_XL_ODR_104HZ ((uint8_t)0x40) /*!< Output Data Rate: 104 Hz */ -#define LSM6DS3_XL_ODR_208HZ ((uint8_t)0x50) /*!< Output Data Rate: 208 Hz */ -#define LSM6DS3_XL_ODR_416HZ ((uint8_t)0x60) /*!< Output Data Rate: 416 Hz */ -#define LSM6DS3_XL_ODR_833HZ ((uint8_t)0x70) /*!< Output Data Rate: 833 Hz */ -#define LSM6DS3_XL_ODR_1660HZ ((uint8_t)0x80) /*!< Output Data Rate: 1.66 kHz */ -#define LSM6DS3_XL_ODR_3330HZ ((uint8_t)0x90) /*!< Output Data Rate: 3.33 kHz */ -#define LSM6DS3_XL_ODR_6660HZ ((uint8_t)0xA0) /*!< Output Data Rate: 6.66 kHz */ - -#define LSM6DS3_XL_ODR_MASK ((uint8_t)0xF0) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Accelerometer_Full_Scale_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Full_Scale_Selection_CTRL1_XL - * @{ - */ -#define LSM6DS3_XL_FS_2G ((uint8_t)0x00) /*!< Full scale: +- 2g */ -#define LSM6DS3_XL_FS_4G ((uint8_t)0x08) /*!< Full scale: +- 4g */ -#define LSM6DS3_XL_FS_8G ((uint8_t)0x0C) /*!< Full scale: +- 8g */ -#define LSM6DS3_XL_FS_16G ((uint8_t)0x04) /*!< Full scale: +- 16g */ - -#define LSM6DS3_XL_FS_MASK ((uint8_t)0x0C) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL1_XL LSM6DS3_XG_Accelerometer_Anti_Aliasing_Filter_Bandwidth_Selection_CTRL1_XL - * @{ - */ -#define LSM6DS3_XL_BW_400HZ ((uint8_t)0x00) /*!< Anti-aliasing filter bandwidht: 400 Hz */ -#define LSM6DS3_XL_BW_200HZ ((uint8_t)0x01) /*!< Anti-aliasing filter bandwidht: 200 Hz */ -#define LSM6DS3_XL_BW_100HZ ((uint8_t)0x02) /*!< Anti-aliasing filter bandwidht: 100 Hz */ -#define LSM6DS3_XL_BW_50HZ ((uint8_t)0x03) /*!< Anti-aliasing filter bandwidht: 50 Hz */ - -#define LSM6DS3_XL_BW_MASK ((uint8_t)0x03) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_Z_Axis_Output_Enable_Selection_CTRL9_XL - * @{ - */ -#define LSM6DS3_XL_ZEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Z-axis output enable: disable */ -#define LSM6DS3_XL_ZEN_ENABLE ((uint8_t)0x20) /*!< Accelerometer’s Z-axis output enable: enable */ - -#define LSM6DS3_XL_ZEN_MASK ((uint8_t)0x20) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_Y_Axis_Output_Enable_Selection_CTRL9_XL - * @{ - */ -#define LSM6DS3_XL_YEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s Y-axis output enable: disable */ -#define LSM6DS3_XL_YEN_ENABLE ((uint8_t)0x10) /*!< Accelerometer’s Y-axis output enable: enable */ - -#define LSM6DS3_XL_YEN_MASK ((uint8_t)0x10) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL9_XL LSM6DS3_XG_Accelerometer_X_Axis_Output_Enable_Selection_CTRL9_XL - * @{ - */ -#define LSM6DS3_XL_XEN_DISABLE ((uint8_t)0x00) /*!< Accelerometer’s X-axis output enable: disable */ -#define LSM6DS3_XL_XEN_ENABLE ((uint8_t)0x08) /*!< Accelerometer’s X-axis output enable: enable */ - -#define LSM6DS3_XL_XEN_MASK ((uint8_t)0x08) - -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_FF_DUR5_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_FF_DUR5_Selection_WAKE_UP_DUR - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_DEFAULT ((uint8_t)0x00) - -#define LSM6DS3_XG_WAKE_UP_DUR_FF_DUR5_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_WAKE_DUR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_WAKE_DUR_Selection_WAKE_UP_DUR - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_DEFAULT ((uint8_t)0x00) - -#define LSM6DS3_XG_WAKE_UP_DUR_WAKE_DUR_MASK ((uint8_t)0x60) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_TIMER_HR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_TIMER_HR_Selection_WAKE_UP_DUR - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_DEFAULT ((uint8_t)0x00) - -#define LSM6DS3_XG_WAKE_UP_DUR_TIMER_HR_MASK ((uint8_t)0x10) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_SLEEP_DUR_Selection_WAKE_UP_DUR LSM6DS3_XG_Accelerometer_SLEEP_DUR_Selection_WAKE_UP_DUR - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_DEFAULT ((uint8_t)0x00) - -#define LSM6DS3_XG_WAKE_UP_DUR_SLEEP_DUR_MASK ((uint8_t)0x0F) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_FF_DUR_Selection_FREE_FALL LSM6DS3_XG_Accelerometer_FF_DUR_Selection_FREE_FALL - * @{ - */ -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_DEFAULT ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_TYPICAL ((uint8_t)0x30) - -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_DUR_MASK ((uint8_t)0xF8) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_FF_THS_Selection_FREE_FALL LSM6DS3_XG_Accelerometer_FF_THS_Selection_FREE_FALL - * @{ - */ -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_156MG ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_219MG ((uint8_t)0x01) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_250MG ((uint8_t)0x02) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_312MG ((uint8_t)0x03) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_344MG ((uint8_t)0x04) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_406MG ((uint8_t)0x05) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_469MG ((uint8_t)0x06) -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_500MG ((uint8_t)0x07) - -#define LSM6DS3_XG_WAKE_FREE_FALL_FF_THS_MASK ((uint8_t)0x07) - -/** - * @} - */ - - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_INACT_STATE_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_INACT_STATE_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_ENABLE ((uint8_t)0x80) - -#define LSM6DS3_XG_MD1_CFG_INT1_INACT_STATE_MASK ((uint8_t)0x80) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_SINGLE_TAP_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_SINGLE_TAP_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_ENABLE ((uint8_t)0x40) - -#define LSM6DS3_XG_MD1_CFG_INT1_SINGLE_TAP_MASK ((uint8_t)0x40) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_WU_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_WU_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_WU_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_WU_ENABLE ((uint8_t)0x20) - -#define LSM6DS3_XG_MD1_CFG_INT1_WU_MASK ((uint8_t)0x20) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_FF_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_FF_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_FF_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_FF_ENABLE ((uint8_t)0x10) - -#define LSM6DS3_XG_MD1_CFG_INT1_FF_MASK ((uint8_t)0x10) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_DOUBLE_TAP_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_DOUBLE_TAP_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_ENABLE ((uint8_t)0x08) - -#define LSM6DS3_XG_MD1_CFG_INT1_DOUBLE_TAP_MASK ((uint8_t)0x08) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_6D_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_6D_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_6D_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_6D_ENABLE ((uint8_t)0x04) - -#define LSM6DS3_XG_MD1_CFG_INT1_6D_MASK ((uint8_t)0x04) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_TILT_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_TILT_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_TILT_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_TILT_ENABLE ((uint8_t)0x02) - -#define LSM6DS3_XG_MD1_CFG_INT1_TILT_MASK ((uint8_t)0x02) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_INT1_TIMER_Selection_MD1_CFG LSM6DS3_XG_Accelerometer_INT1_TIMER_Selection_MD1_CFG - * @{ - */ -#define LSM6DS3_XG_MD1_CFG_INT1_TIMER_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_MD1_CFG_INT1_TIMER_ENABLE ((uint8_t)0x01) - -#define LSM6DS3_XG_MD1_CFG_INT1_TIMER_MASK ((uint8_t)0x01) - -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_FF_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_FF_IA_Enable_WAKE_UP_SRC - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_ENABLE ((uint8_t)0x20) - -#define LSM6DS3_XG_WAKE_UP_SRC_FF_IA_MASK ((uint8_t)0x20) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_SLEEP_STATE_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_SLEEP_STATE_IA_Enable_WAKE_UP_SRC - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_ENABLE ((uint8_t)0x10) - -#define LSM6DS3_XG_WAKE_UP_SRC_SLEEP_STATE_IA_MASK ((uint8_t)0x10) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_WU_IA_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_WU_IA_Enable_WAKE_UP_SRC - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_ENABLE ((uint8_t)0x08) - -#define LSM6DS3_XG_WAKE_UP_SRC_WU_IA_MASK ((uint8_t)0x08) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_X_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_X_WU_Enable_WAKE_UP_SRC - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_SRC_X_WU_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_UP_SRC_X_WU_ENABLE ((uint8_t)0x04) - -#define LSM6DS3_XG_WAKE_UP_SRC_X_WU_MASK ((uint8_t)0x04) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_Y_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_Y_WU_Enable_WAKE_UP_SRC - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_ENABLE ((uint8_t)0x02) - - -#define LSM6DS3_XG_WAKE_UP_SRC_Y_WU_MASK ((uint8_t)0x02) -/** - * @} - */ - -/** @addtogroup LSM6DS3_XG_Accelerometer_Z_WU_Enable_WAKE_UP_SRC LSM6DS3_XG_Accelerometer_Z_WU_Enable_WAKE_UP_SRC - * @{ - */ -#define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_DISABLE ((uint8_t)0x00) -#define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_ENABLE ((uint8_t)0x01) - -#define LSM6DS3_XG_WAKE_UP_SRC_Z_WU_MASK ((uint8_t)0x01) -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup LSM6DS3_Imported_Functions LSM6DS3_Imported_Functions - * @{ - */ - -/* Six axes sensor IO functions */ -extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Init( void ); -extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Write( uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToWrite ); -extern IMU_6AXES_StatusTypeDef LSM6DS3_IO_Read( uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, - uint16_t NumByteToRead ); -extern void LSM6DS3_IO_ITConfig( void ); - -/** - * @} - */ - -/** @addtogroup LSM6DS3_Exported_Types LSM6DS3_Exported_Types - * @{ - */ -/** - * @brief LSM6DS3 driver extended internal structure definition - */ -typedef struct -{ - IMU_6AXES_StatusTypeDef (*Enable_Free_Fall_Detection) (void); - IMU_6AXES_StatusTypeDef (*Disable_Free_Fall_Detection) (void); - IMU_6AXES_StatusTypeDef (*Get_Status_Free_Fall_Detection) (uint8_t *); -} LSM6DS3_DrvExtTypeDef; - -/** - * @} - */ - -/** @addtogroup LSM6DS3_Exported_Variables LSM6DS3_Exported_Variables - * @{ - */ - -/* Six axes sensor driver structure */ -extern IMU_6AXES_DrvTypeDef LSM6DS3Drv; -extern IMU_6AXES_DrvExtTypeDef LSM6DS3Drv_ext; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __LSM6DS3_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/MCU_Interface.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/MCU_Interface.h deleted file mode 100644 index 1a801cee1..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/MCU_Interface.h +++ /dev/null @@ -1,152 +0,0 @@ -/** - * @file MCU_Interface.h - * @author VMA division - AMS - * @version V2.0.2 - * @date Febrary 7, 2015 - * @brief Header file for low level SPIRIT SPI driver. - * @details - * - * This header file constitutes an interface to the SPI driver used to - * communicate with Spirit. - * It exports some function prototypes to write/read registers and FIFOs - * and to send command strobes. - * Since the Spirit libraries are totally platform independent, the implementation - * of these functions are not provided here. The user have to implement these functions - * taking care to keep the exported prototypes. - * - * These functions are: - * - *
    - *
  • SpiritSpiInit - *
  • SpiritSpiWriteRegisters - *
  • SpiritSpiReadRegisters - *
  • SpiritSpiCommandStrobes - *
  • SpiritSpiWriteLinearFifo - *
  • SpiritSpiReadLinearFifo - *
- * - * @note An example of SPI driver implementation is available in the Sdk_Eval library. - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * THIS SOURCE CODE IS PROTECTED BY A LICENSE. - * FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED - * IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. - * - *

© COPYRIGHT 2015 STMicroelectronics

- */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MCU_INTERFACE_H -#define __MCU_INTERFACE_H - - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** @defgroup SPIRIT_SPI_Driver SPI Driver - * @brief Header file for low level SPIRIT SPI driver. - * @details See the file @ref MCU_Interface.h for more details. - * @{ - */ - - - -/** @defgroup SPI_Exported_Types SPI Exported Types - * @{ - */ - -/** - * @} - */ - - - -/** @defgroup SPI_Exported_Constants SPI Exported Constants - * @{ - */ - -/** - * @} - */ - - - -/** @defgroup SPI_Exported_Macros SPI Exported Macros - * @{ - */ - -/** - * @} - */ - - - -/** @defgroup SPI_Exported_Functions SPI Exported Functions - * @{ - */ - -typedef SpiritStatus StatusBytes; - -void SdkEvalSpiInit(void); -StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); -StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); -StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode); -StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer); -StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer); - -void SdkEvalEnterShutdown(void); -void SdkEvalExitShutdown(void); -SpiritFlagStatus SdkEvalCheckShutdown(void); - -#define SpiritEnterShutdown SdkEvalEnterShutdown -#define SpiritExitShutdown SdkEvalExitShutdown -#define SpiritCheckShutdown (SpiritFlagStatus)SdkEvalCheckShutdown - - -#define SpiritSpiInit SdkEvalSpiInit -#define SpiritSpiWriteRegisters(cRegAddress, cNbBytes, pcBuffer) SdkEvalSpiWriteRegisters(cRegAddress, cNbBytes, pcBuffer) -#define SpiritSpiReadRegisters(cRegAddress, cNbBytes, pcBuffer) SdkEvalSpiReadRegisters(cRegAddress, cNbBytes, pcBuffer) -#define SpiritSpiCommandStrobes(cCommandCode) SdkEvalSpiCommandStrobes(cCommandCode) -#define SpiritSpiWriteLinearFifo(cNbBytes, pcBuffer) SdkEvalSpiWriteFifo(cNbBytes, pcBuffer) -#define SpiritSpiReadLinearFifo(cNbBytes, pcBuffer) SdkEvalSpiReadFifo(cNbBytes, pcBuffer) - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT1_Util.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT1_Util.h deleted file mode 100644 index 45a1e950f..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT1_Util.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * @file SPIRIT1_Util.h - * @author High End Analog & RF BU - AMS / ART Team IMS-Systems Lab - * @version V3.0.1 - * @date November 19, 2012 - * @brief Identification functions for SPIRIT DK. - * @details - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - * THIS SOURCE CODE IS PROTECTED BY A LICENSE. - * FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED - * IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. - * - *

© COPYRIGHT 2012 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT1_UTIL_H -#define __SPIRIT1_UTIL_H - - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Config.h" -#include "radio_gpio.h" - -#ifdef __cplusplus - "C" { -#endif - - -/** - * @addtogroup ST_SPIRIT1 - * @{ - */ - -typedef struct -{ - uint16_t nSpiritVersion; - SpiritVersion xSpiritVersion; -}SpiritVersionMap; - -#define CUT_MAX_NO 3 -#define CUT_2_1v3 0x0103 -#define CUT_2_1v4 0x0104 -#define CUT_3_0 0x0130 - -/** - * @brief Range extender type - */ -typedef enum -{ - RANGE_EXT_NONE = 0x00, - RANGE_EXT_SKYWORKS_169, - RANGE_EXT_SKYWORKS_868 -} RangeExtType; - -/** - * @addgroup SPIRIT1_Util_FUNCTIONS - * @{ - */ -void SpiritManagementIdentificationRFBoard(void); - -RangeExtType SpiritManagementGetRangeExtender(void); -void SpiritManagementSetRangeExtender(RangeExtType xRangeType); -void SpiritManagementRangeExtInit(void); -void SpiritManagementSetBand(uint8_t value); -uint8_t SpiritManagementGetBand(void); - -uint8_t SdkEvalGetHasEeprom(void); - -void Spirit1InterfaceInit(void); -void Spirit1GpioIrqInit(SGpioInit *pGpioIRQ); -void Spirit1RadioInit(SRadioInit *pRadioInit); -void Spirit1SetPower(uint8_t cIndex, float fPowerdBm); -void Spirit1PacketConfig(void); -void Spirit1SetPayloadlength(uint8_t length); -void Spirit1SetDestinationAddress(uint8_t address); -void Spirit1EnableTxIrq(void); -void Spirit1EnableRxIrq(void); -void Spirit1DisableIrq(void); -void Spirit1SetRxTimeout(float cRxTimeOut); -void Spirit1EnableSQI(void); -void Spirit1SetRssiTH(int dbmValue); -float Spirit1GetRssiTH(void); -void Spirit1ClearIRQ(void); -void Spirit1StartRx(void); -void Spirit1GetRxPacket(uint8_t *buffer, uint8_t size ); -void Spirit1StartTx(uint8_t *buffer, uint8_t size); - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -#ifdef __cplusplus -} -#endif - - -#endif - - - /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/ - diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Aes.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Aes.h deleted file mode 100644 index 1e41bafb3..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Aes.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Aes.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT AES Engine. - * - * @details - * - * In order to encrypt data, the user must manage the AES_END IRQ. - * The data have to be splitted in blocks of 16 bytes and written - * into the AES DATA IN registers. Then, after the key is written - * into the AES KEY registers, a command of Execute encryption - * has to be sent. - * - * Example: - * @code - * - * SpiritAesWriteDataIn(data_buff , N_BYTES); - * SpiritAesExecuteEncryption(); - * - * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq - * aes_end_flag=RESET; - * - * SpiritAesReadDataOut(enc_data_buff , N_BYTES); - * - * @endcode - * - * In order to decrypt data, the user must manage the AES_END IRQ and have a decryption key. - * There are two operative modes to make the data decryption: - *
    - *
  • Derive the decryption key from the encryption key and decrypt data directly - * using the SpiritAesDeriveDecKeyExecuteDec() function - * - * Example: - * @code - * - * SpiritAesWriteDataIn(enc_data_buff , N_BYTES); - * SpiritAesDeriveDecKeyExecuteDec(); - * - * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq - * aes_end_flag=RESET; - * - * SpiritAesReadDataOut(data_buff , N_BYTES); - * - * @endcode - *
    • - * - *
  • Derive the decryption key from the encryption key using the SpiritAesDeriveDecKeyFromEnc() - * function, store it into the AES KEY registers and then decrypt data using the - * SpiritAesExecuteDecryption() function - * - * Example: - * @code - * - * SpiritAesWriteDataIn(key_enc , 16); - * SpiritAesDeriveDecKeyFromEnc(); - * - * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq - * aes_end_flag=RESET; - * - * SpiritAesReadDataOut(key_dec , 16); - * - * SpiritAesWriteKey(key_dec); - * SpiritAesWriteDataIn(enc_data_buff , 16); - * SpiritAesExecuteDecryption(); - * - * while(!aes_end_flag); // the flag is set by the ISR routine which manages the AES_END irq - * aes_end_flag=RESET; - * - * SpiritAesReadDataOut(data_buff , N_BYTES); - * - * @endcode - *
    • - *
- * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_AES_H -#define __SPIRIT_AES_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Aes AES - * @brief Configuration and management of SPIRIT AES Engine. - * @details See the file @ref SPIRIT_Aes.h for more details. - * @{ - */ - -/** - * @defgroup Aes_Exported_Types AES Exported Types - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Aes_Exported_Constants AES Exported Constants - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup Aes_Exported_Macros AES Exported Macros - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup Aes_Exported_Functions AES Exported Functions - * @{ - */ - -void SpiritAesMode(SpiritFunctionalState xNewState); -void SpiritAesWriteDataIn(uint8_t* pcBufferDataIn, uint8_t cDataLength); -void SpiritAesReadDataOut(uint8_t* pcBufferDataOut, uint8_t cDataLength); -void SpiritAesWriteKey(uint8_t* pcKey); -void SpiritAesReadKey(uint8_t* pcKey); -void SpiritAesDeriveDecKeyFromEnc(void); -void SpiritAesExecuteEncryption(void); -void SpiritAesExecuteDecryption(void); -void SpiritAesDeriveDecKeyExecuteDec(void); - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Calibration.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Calibration.h deleted file mode 100644 index 6edc42442..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Calibration.h +++ /dev/null @@ -1,226 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Calibration.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT VCO-RCO calibration. - * - * @details - * - * This module allows the user to set some parameters which deal - * with the oscillators calibration. - * The state machine of Spirit contemplates some optional calibrating operations - * in the transition between the READY and the LOCK state. - * The user is allowed to enable or disable the automatic RCO/VCO calibration - * by calling the functions @ref SpiritCalibrationVco() and @ref SpiritCalibrationRco(). - * The following example shows how to do an initial calibration of VCO. - * - * Example: - * @code - * uint8_t calData; - * - * SpiritCalibrationVco(S_ENABLE); - * SpiritCmdStrobeLockTx(); - * - * while(g_xStatus.MC_STATE != MC_STATE_LOCK){ - * SpiritRefreshStatus(); - * } - * - * calData = SpiritCalibrationGetVcoCalDataTx(); - * SpiritCalibrationSetVcoCalDataTx(calData); - * - * SpiritCmdStrobeReady(); - * SpiritCalibrationVco(S_DISABLE); - * - * @endcode - * - * Similar operations can be done for the RCO calibrator. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_CALIBRATION_H -#define __SPIRIT_CALIBRATION_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Calibration Calibration - * @brief Configuration and management of SPIRIT VCO-RCO calibration. - * @details See the file @ref SPIRIT_Calibration.h for more details. - * @{ - */ - -/** - * @defgroup Calibration_Exported_Types Calibration Exported Types - * @{ - */ - - -/** - * @brief VCO / RCO calibration window. - */ -typedef enum -{ - - CALIB_TIME_7_33_US_24MHZ = 0x00, /*!< calibration window of 7.33 us with XTAL=24MHz */ - CALIB_TIME_14_67_US_24MHZ, /*!< calibration window of 14.67 us with XTAL=24MHz */ - CALIB_TIME_29_33_US_24MHZ, /*!< calibration window of 29.33 us with XTAL=24MHz */ - CALIB_TIME_58_67_US_24MHZ, /*!< calibration window of 58.67 us with XTAL=24MHz */ - - CALIB_TIME_6_77_US_26MHZ = 0x00, /*!< calibration window of 6.77 us with XTAL=26MHz */ - CALIB_TIME_13_54_US_26MHZ, /*!< calibration window of 13.54 us with XTAL=26MHz */ - CALIB_TIME_27_08_US_26MHZ, /*!< calibration window of 27.08 us with XTAL=26MHz */ - CALIB_TIME_54_15_US_26MHZ /*!< calibration window of 54.15 us with XTAL=26MHz */ - -} VcoWin; - - -#define IS_VCO_WIN(REF) (REF == CALIB_TIME_7_33_US_24MHZ ||\ - REF == CALIB_TIME_14_67_US_24MHZ ||\ - REF == CALIB_TIME_29_33_US_24MHZ ||\ - REF == CALIB_TIME_58_67_US_24MHZ ||\ - REF == CALIB_TIME_6_77_US_26MHZ ||\ - REF == CALIB_TIME_13_54_US_26MHZ ||\ - REF == CALIB_TIME_27_08_US_26MHZ ||\ - REF == CALIB_TIME_54_15_US_26MHZ \ - ) - -/** - * @brief VCO_H / VCO_L selection. - */ -typedef enum -{ - - VCO_L = 0x00, /*!< VCO lower */ - VCO_H, /*!< VCO higher */ -} VcoSel; - - -#define IS_VCO_SEL(REF) (REF == VCO_L ||\ - REF == VCO_H \ - ) - - -/** - * @} - */ - - -/** - * @defgroup Calibration_Exported_Constants Calibration Exported Constants - * @{ - */ - -/** - * @} - */ - - - -/** @defgroup VCO_Calibration VCO Calibration - * @{ - */ - -/** - * @} - */ - - - - -/** - * @defgroup Calibration_Exported_Macros Calibration Exported Macros - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup Calibration_Exported_Functions Calibration Exported Functions - * @{ - */ - -void SpiritCalibrationRco(SpiritFunctionalState xNewState); -void SpiritCalibrationVco(SpiritFunctionalState xNewState); -void SpiritCalibrationSetRcoCalWords(uint8_t cRwt, uint8_t cRfb); -void SpiritCalibrationGetRcoCalWords(uint8_t* pcRwt, uint8_t* pcRfb); -uint8_t SpiritCalibrationGetVcoCalData(void); -void SpiritCalibrationSetVcoCalDataTx(uint8_t cVcoCalData); -uint8_t SpiritCalibrationGetVcoCalDataTx(void); -void SpiritCalibrationSetVcoCalDataRx(uint8_t cVcoCalData); -uint8_t SpiritCalibrationGetVcoCalDataRx(void); -void SpiritCalibrationSetVcoWindow(VcoWin xRefWord); -VcoWin SpiritCalibrationGetVcoWindow(void); -VcoSel SpiritCalibrationGetVcoSelecttion(void); -void SpiritCalibrationSelectVco(VcoSel xVco); - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Commands.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Commands.h deleted file mode 100644 index 7a8fa07fc..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Commands.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Commands.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Management of SPIRIT Commands. - * - * @details - * - * In this module can be found all the API used to strobe commands to - * Spirit. - * Every command strobe is an SPI transaction with a specific command code. - * - * Example: - * @code - * ... - * - * SpiritCmdStrobeRx(); - * - * ... - * @endcode - * - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_COMMANDS_H -#define __SPIRIT_COMMANDS_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Commands Commands - * @brief Management of SPIRIT Commands. - * @details See the file @ref SPIRIT_Commands.h for more details. - * @{ - */ - -/** - * @defgroup Commands_Exported_Types Commands Exported Types - * @{ - */ - -/** - * @brief SPIRIT Commands codes enumeration - */ -typedef enum -{ - CMD_TX = COMMAND_TX, /*!< Start to transmit; valid only from READY */ - CMD_RX = COMMAND_RX, /*!< Start to receive; valid only from READY */ - CMD_READY = COMMAND_READY, /*!< Go to READY; valid only from STANDBY or SLEEP or LOCK */ - CMD_STANDBY = COMMAND_STANDBY, /*!< Go to STANDBY; valid only from READY */ - CMD_SLEEP = COMMAND_SLEEP, /*!< Go to SLEEP; valid only from READY */ - CMD_LOCKRX = COMMAND_LOCKRX, /*!< Go to LOCK state by using the RX configuration of the synth; valid only from READY */ - CMD_LOCKTX = COMMAND_LOCKTX, /*!< Go to LOCK state by using the TX configuration of the synth; valid only from READY */ - CMD_SABORT = COMMAND_SABORT, /*!< Force exit form TX or RX states and go to READY state; valid only from TX or RX */ - CMD_LDC_RELOAD = COMMAND_LDC_RELOAD, /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER registers; valid from all states */ - CMD_SEQUENCE_UPDATE = COMMAND_SEQUENCE_UPDATE, /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register valid from all states */ - CMD_AES_ENC = COMMAND_AES_ENC, /*!< Commands: Start the encryption routine; valid from all states; valid from all states */ - CMD_AES_KEY = COMMAND_AES_KEY, /*!< Commands: Start the procedure to compute the key for the decryption; valid from all states */ - CMD_AES_DEC = COMMAND_AES_DEC, /*!< Commands: Start the decryption routine using the current key; valid from all states */ - CMD_AES_KEY_DEC = COMMAND_AES_KEY_DEC, /*!< Commands: Compute the key and start the decryption; valid from all states */ - CMD_SRES = COMMAND_SRES, /*!< Reset of all digital part, except SPI registers */ - CMD_FLUSHRXFIFO = COMMAND_FLUSHRXFIFO, /*!< Clean the RX FIFO; valid from all states */ - CMD_FLUSHTXFIFO = COMMAND_FLUSHTXFIFO, /*!< Clean the TX FIFO; valid from all states */ -} SpiritCmd; - -#define IS_SPIRIT_CMD(CMD) (CMD == CMD_TX || \ - CMD == CMD_RX || \ - CMD == CMD_READY || \ - CMD == CMD_STANDBY || \ - CMD == CMD_SLEEP || \ - CMD == CMD_LOCKRX || \ - CMD == CMD_LOCKTX || \ - CMD == CMD_SABORT || \ - CMD == CMD_LDC_RELOAD || \ - CMD == CMD_SEQUENCE_UPDATE || \ - CMD == CMD_AES_ENC || \ - CMD == CMD_AES_KEY || \ - CMD == CMD_AES_DEC || \ - CMD == CMD_AES_KEY_DEC || \ - CMD == CMD_SRES || \ - CMD == CMD_FLUSHRXFIFO || \ - CMD == CMD_FLUSHTXFIFO \ - ) - -/** - * @} - */ - - -/** - * @defgroup Commands_Exported_Constants Commands Exported Constants - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup Commands_Exported_Macros Commands Exported Macros - * @{ - */ - -/** - * @brief Sends the TX command to SPIRIT. Start to transmit. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeTx() {SpiritManagementWaCmdStrobeTx(); \ - SpiritCmdStrobeCommand(CMD_TX);} - - -/** - * @brief Sends the RX command to SPIRIT. Start to receive. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeRx() {SpiritManagementWaCmdStrobeRx(); \ - SpiritCmdStrobeCommand(CMD_RX); \ - } - - -/** - * @brief Sends the Ready state command to SPIRIT. Go to READY. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeReady() SpiritCmdStrobeCommand(CMD_READY) - - - -/** - * @brief Sends the Standby command to SPIRIT. Go to STANDBY. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeStandby() SpiritCmdStrobeCommand(CMD_STANDBY) - - - -/** - * @brief Sends the Sleep command to SPIRIT. Go to SLEEP. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeSleep() SpiritCmdStrobeCommand(CMD_SLEEP) - - - -/** - * @brief Sends the LOCK_RX command to SPIRIT. Go to the LOCK state by using the RX configuration of the synthesizer. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeLockRx() SpiritCmdStrobeCommand(CMD_LOCKRX) - - - -/** - * @brief Sends the LOCK_TX command to SPIRIT. Go to the LOCK state by using the TX configuration of the synthesizer. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeLockTx() SpiritCmdStrobeCommand(CMD_LOCKTX) - - - -/** - * @brief Sends the SABORT command to SPIRIT. Exit from TX or RX states and go to READY state. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeSabort() SpiritCmdStrobeCommand(CMD_SABORT) - - -/** - * @brief Sends the LDC_RELOAD command to SPIRIT. Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER registers. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeLdcReload() SpiritCmdStrobeCommand(CMD_LDC_RELOAD) - - - -/** - * @brief Sends the SEQUENCE_UPDATE command to SPIRIT. Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeSequenceUpdate() SpiritCmdStrobeCommand(CMD_SEQUENCE_UPDATE) - - - -/** - * @brief Sends the AES_ENC command to SPIRIT. Starts the encryption routine. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeAesEnc() SpiritCmdStrobeCommand(CMD_AES_ENC) - - - -/** - * @brief Sends the AES_KEY command to SPIRIT. Starts the procedure to compute the key for the decryption. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeAesKey() SpiritCmdStrobeCommand(CMD_AES_KEY) - - - -/** - * @brief Sends the AES_DEC command to SPIRIT. Starts the decryption using the current key. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeAesDec() SpiritCmdStrobeCommand(CMD_AES_DEC) - - - -/** - * @brief Sends the KEY_DEC command to SPIRIT. Computes the key derivation and start the decryption. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeAesKeyDec() SpiritCmdStrobeCommand(CMD_AES_KEY_DEC) - -/** - * @brief Sends the SRES command to SPIRIT. Partial reset: all digital circuit will be reset (exception for SPI only). - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeSres() SpiritCmdStrobeCommand(CMD_SRES) - - -/** - * @brief Sends the FLUSHRXFIFO command to SPIRIT. Clean the RX FIFO. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeFlushRxFifo() SpiritCmdStrobeCommand(CMD_FLUSHRXFIFO) - - - -/** - * @brief Sends the FLUSHTXFIFO command to SPIRIT. Clean the TX FIFO. - * @param None. - * @retval None. - */ -#define SpiritCmdStrobeFlushTxFifo() SpiritCmdStrobeCommand(CMD_FLUSHTXFIFO) - - - -/** - * @} - */ - - -/** - * @defgroup Commands_Exported_Functions Commands Exported Functions - * @{ - */ -void SpiritCmdStrobeCommand(SpiritCmd xCommandCode); - - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Config.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Config.h deleted file mode 100644 index 9d96975c4..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Config.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Config.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Spirit Configuration and useful defines - * - * @details - * - * This file is used to include all or a part of the Spirit - * libraries into the application program which will be used. - * Moreover some important parameters are defined here and the - * user is allowed to edit them. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_CONFIG_H -#define __SPIRIT_CONFIG_H - - - /* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Regs.h" -#include "SPIRIT_Aes.h" -#include "SPIRIT_Calibration.h" -#include "SPIRIT_Commands.h" -#include "SPIRIT_Csma.h" -#include "SPIRIT_DirectRF.h" -#include "SPIRIT_General.h" -#include "SPIRIT_Gpio.h" -#include "SPIRIT_Irq.h" -#include "SPIRIT_Timer.h" -#include "SPIRIT_LinearFifo.h" -#include "SPIRIT_PktBasic.h" -#include "SPIRIT_PktMbus.h" -#include "SPIRIT_PktStack.h" - -#include "SPIRIT_Qi.h" -#include "SPIRIT_Radio.h" -#include "MCU_Interface.h" -#include "SPIRIT_Types.h" -#include "SPIRIT_Management.h" - - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @addtogroup SPIRIT_Libraries SPIRIT Libraries - * @brief This firmware implements libraries which allow the user - * to manage the features of Spirit without knowing the hardware details. - * @details The SPIRIT_Libraries modules are totally platform independent. The library provides one - * module for each device feature. Each module refers to some functions whose prototypes are located in the - * header file @ref MCU_Interface.h. The user who want to use these libraries on a particular - * platform has to implement these functions respecting them signatures. - * @{ - */ - -/** @defgroup SPIRIT_Configuration Configuration - * @brief Spirit Configuration and useful defines. - * @details See the file @ref SPIRIT_Config.h for more details. - * @{ - */ - - -/** @defgroup Configuration_Exported_Types Configuration Exported Types - * @{ - */ - -/** - * @} - */ - - -/** @defgroup Configuration_Exported_Constants Configuration Exported Constants - * @{ - */ -#define DOUBLE_XTAL_THR 30000000 - -/** - * @} - */ - - -/** @defgroup Configuration_Exported_Macros Configuration Exported Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup Configuration_Exported_Functions Configuration Exported Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Csma.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Csma.h deleted file mode 100644 index 88db8b353..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Csma.h +++ /dev/null @@ -1,263 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Csma.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT CSMA. - * @details - * - * The Spirit CSMA feature, when configured and enabled, is transparent - * for the user. It means the user has only to call the @ref SpiritCsmaInit() - * function on a filled structure and then enable the CSMA policy using the @ref SpiritCsma() - * function. - * - * Example: - * @code - * - * CsmaInit csmaInit={ - * S_DISABLE, // persistent mode - * TBIT_TIME_64, // Tbit time - * TCCA_TIME_3, // Tcca time - * 5, // max number of backoffs - * 0xFA21, // BU counter seed - * 32 // CU prescaler - * }; - * - * ... - * - * SpiritCsmaInit(&csmaInit); - * SpiritCsma(S_ENABLE); - * - * - * @endcode - * - * @note The CS status depends of the RSSI threshold set. Please see the Spirit_Qi - * module for details. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_CSMA_H -#define __SPIRIT_CSMA_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Types.h" -#include "SPIRIT_Regs.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Csma CSMA - * @brief Configuration and management of SPIRIT CSMA. - * @details See the file @ref SPIRIT_Csma.h for more details. - * @{ - */ - -/** - * @defgroup Csma_Exported_Types CSMA Exported Types - * @{ - */ - - -/** - * @brief Multiplier for Tcca time enumeration (Tcca = Multiplier*Tbit). - */ -typedef enum -{ - TBIT_TIME_64 = CSMA_CCA_PERIOD_64TBIT, /*!< CSMA/CA: Sets CCA period to 64*TBIT */ - TBIT_TIME_128 = CSMA_CCA_PERIOD_128TBIT, /*!< CSMA/CA: Sets CCA period to 128*TBIT */ - TBIT_TIME_256 = CSMA_CCA_PERIOD_256TBIT, /*!< CSMA/CA: Sets CCA period to 256*TBIT */ - TBIT_TIME_512 = CSMA_CCA_PERIOD_512TBIT, /*!< CSMA/CA: Sets CCA period to 512*TBIT */ -}CcaPeriod; - -#define IS_CCA_PERIOD(PERIOD) (PERIOD == TBIT_TIME_64 || \ - PERIOD == TBIT_TIME_128 || \ - PERIOD == TBIT_TIME_256 || \ - PERIOD == TBIT_TIME_512) - - -/** - * @brief Multiplier of Tcca time enumeration to obtain Tlisten (Tlisten = [1...15]*Tcca). - */ -typedef enum -{ - TCCA_TIME_0 = 0x00, /*!< CSMA/CA: Sets CCA length to 0 */ - TCCA_TIME_1 = 0x10, /*!< CSMA/CA: Sets CCA length to 1*TLISTEN */ - TCCA_TIME_2 = 0x20, /*!< CSMA/CA: Sets CCA length to 2*TLISTEN */ - TCCA_TIME_3 = 0x30, /*!< CSMA/CA: Sets CCA length to 3*TLISTEN */ - TCCA_TIME_4 = 0x40, /*!< CSMA/CA: Sets CCA length to 4*TLISTEN */ - TCCA_TIME_5 = 0x50, /*!< CSMA/CA: Sets CCA length to 5*TLISTEN */ - TCCA_TIME_6 = 0x60, /*!< CSMA/CA: Sets CCA length to 6*TLISTEN */ - TCCA_TIME_7 = 0x70, /*!< CSMA/CA: Sets CCA length to 7*TLISTEN */ - TCCA_TIME_8 = 0x80, /*!< CSMA/CA: Sets CCA length to 8*TLISTEN */ - TCCA_TIME_9 = 0x90, /*!< CSMA/CA: Sets CCA length to 9*TLISTEN */ - TCCA_TIME_10 = 0xA0, /*!< CSMA/CA: Sets CCA length to 10*TLISTEN */ - TCCA_TIME_11 = 0xB0, /*!< CSMA/CA: Sets CCA length to 11*TLISTEN */ - TCCA_TIME_12 = 0xC0, /*!< CSMA/CA: Sets CCA length to 12*TLISTEN */ - TCCA_TIME_13 = 0xD0, /*!< CSMA/CA: Sets CCA length to 13*TLISTEN */ - TCCA_TIME_14 = 0xE0, /*!< CSMA/CA: Sets CCA length to 14*TLISTEN */ - TCCA_TIME_15 = 0xF0, /*!< CSMA/CA: Sets CCA length to 15*TLISTEN */ -}CsmaLength; - -#define IS_CSMA_LENGTH(LENGTH) (LENGTH == TCCA_TIME_0 || \ - LENGTH == TCCA_TIME_1 || \ - LENGTH == TCCA_TIME_2 || \ - LENGTH == TCCA_TIME_3 || \ - LENGTH == TCCA_TIME_4 || \ - LENGTH == TCCA_TIME_5 || \ - LENGTH == TCCA_TIME_6 || \ - LENGTH == TCCA_TIME_7 || \ - LENGTH == TCCA_TIME_8 || \ - LENGTH == TCCA_TIME_9 || \ - LENGTH == TCCA_TIME_10 || \ - LENGTH == TCCA_TIME_11 || \ - LENGTH == TCCA_TIME_12 || \ - LENGTH == TCCA_TIME_13 || \ - LENGTH == TCCA_TIME_14 || \ - LENGTH == TCCA_TIME_15) - - -/** - * @brief SPIRIT CSMA Init structure definition - */ -typedef struct -{ - SpiritFunctionalState xCsmaPersistentMode; /*!< Specifies if the CSMA persistent mode has to be on or off. - This parameter can be S_ENABLE or S_DISABLE */ - CcaPeriod xMultiplierTbit; /*!< Specifies the Tbit multiplier to obtain the Tcca. - This parameter can be a value of @ref CcaPeriod */ - CsmaLength xCcaLength; /*!< Specifies the Tcca multiplier to determinate the Tlisten. - This parameter can be a value of @ref CsmaLength. */ - uint8_t cMaxNb; /*!< Specifies the max number of backoff cycles. Not used in persistent mode. - This parameter is an uint8_t. */ - uint16_t nBuCounterSeed; /*!< Specifies the BU counter seed. Not used in persistent mode. - This parameter can be a value of 16 bits. */ - uint8_t cBuPrescaler; /*!< Specifies the BU prescaler. Not used in persistent mode. - This parameter can be a value of 6 bits. */ -}CsmaInit; - - -/** - *@} - */ - - -/** - * @defgroup Csma_Exported_Constants CSMA Exported Constants - * @{ - */ - -/** - * @defgroup Csma_Parameters CSMA Parameters - * @{ - */ - -#define IS_BU_COUNTER_SEED(SEED) (SEED!=0) -#define IS_BU_PRESCALER(PRESCALER) (PRESCALER<64) -#define IS_CMAX_NB(NB) (NB<8) - -/** - *@} - */ - -/** - *@} - */ - - -/** - * @defgroup Csma_Exported_Macros CSMA Exported Macros - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup Csma_Exported_Functions CSMA Exported Functions - * @{ - */ - -void SpiritCsmaInit(CsmaInit* pxCsmaInit); -void SpiritCsmaGetInfo(CsmaInit* pxCsmaInit); -void SpiritCsma(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritCsmaGetCsma(void); -void SpiritCsmaPersistentMode(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritCsmaGetPersistentMode(void); -void SpiritCsmaSeedReloadMode(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritCsmaGetSeedReloadMode(void); -void SpiritCsmaSetBuCounterSeed(uint16_t nBuCounterSeed); -uint16_t SpiritCsmaGetBuCounterSeed(void); -void SpiritCsmaSetBuPrescaler(uint8_t cBuPrescaler); -uint8_t SpiritCsmaGetBuPrescaler(void); -void SpiritCsmaSetCcaPeriod(CcaPeriod xMultiplierTbit); -CcaPeriod SpiritCsmaGetCcaPeriod(void); -void SpiritCsmaSetCcaLength(CsmaLength xCcaLength); -uint8_t SpiritCsmaGetCcaLength(void); -void SpiritCsmaSetMaxNumberBackoff(uint8_t cMaxNb); -uint8_t SpiritCsmaGetMaxNumberBackoff(void); - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_DirectRF.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_DirectRF.h deleted file mode 100644 index f60090718..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_DirectRF.h +++ /dev/null @@ -1,165 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_DirectRF.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT direct transmission / receive modes. - * @details - * - * This module contains functions to manage the direct Tx/Rx mode. - * The user can choose the way to send data to Spirit through the - * enumerative types @ref DirectTx/@ref DirectRx. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT1_DIRECT_RF_H -#define __SPIRIT1_DIRECT_RF_H - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_DirectRf Direct RF - * @brief Configuration and management of SPIRIT direct transmission / receive modes. - * @details See the file @ref SPIRIT_DirectRF.h for more details. - * @{ - */ - -/** - * @defgroup DirectRf_Exported_Types Direct RF Exported Types - * @{ - */ - -/** - * @brief Direct transmission mode enumeration for SPIRIT. - */ -typedef enum -{ - NORMAL_TX_MODE = 0x00, /*!< Normal mode, no direct transmission is used */ - DIRECT_TX_FIFO_MODE = 0x04, /*!< Source is FIFO: payload bits are continuously read from the TX FIFO */ - DIRECT_TX_GPIO_MODE = 0x08, /*!< Source is GPIO: payload bits are continuously read from one of the GPIO ports and transmitted without any processing */ - PN9_TX_MODE = 0x0C /*!< A pseudorandom binary sequence is generated internally */ -}DirectTx; - -#define IS_DIRECT_TX(MODE) (((MODE) == NORMAL_TX_MODE) || \ - ((MODE) == DIRECT_TX_FIFO_MODE) || \ - ((MODE) == DIRECT_TX_GPIO_MODE) || \ - ((MODE) == PN9_TX_MODE)) - -/** - * @brief Direct receive mode enumeration for SPIRIT. - */ -typedef enum -{ - NORMAL_RX_MODE = 0x00, /*!< Normal mode, no direct reception is used */ - DIRECT_RX_FIFO_MODE = 0x10, /*!< Destination is FIFO: payload bits are continuously written to the RX FIFO and not subjected to any processing*/ - DIRECT_RX_GPIO_MODE = 0x20 /*!< Destination is GPIO: payload bits are continuously written to one of the GPIO ports and not subjected to any processing*/ -}DirectRx; - -#define IS_DIRECT_RX(MODE) (((MODE) == NORMAL_RX_MODE) || \ - ((MODE) == DIRECT_RX_FIFO_MODE) || \ - ((MODE) == DIRECT_RX_GPIO_MODE)) - - -/** - *@} - */ - - -/** - * @defgroup DirectRf_Exported_Constants Direct RF Exported Constants - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup DirectRf_Exported_Macros Direct RF Exported Macros - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup DirectRf_Exported_Functions Direct RF Exported Functions - * @{ - */ - -void SpiritDirectRfSetRxMode(DirectRx xDirectRx); -DirectRx SpiritDirectRfGetRxMode(void); -void SpiritDirectRfSetTxMode(DirectTx xDirectTx); -DirectTx SpiritDirectRfGetTxMode(void); - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_General.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_General.h deleted file mode 100644 index 0f723fb7e..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_General.h +++ /dev/null @@ -1,227 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_General.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT General functionalities. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_GENERAL_H -#define __SPIRIT_GENERAL_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_General General - * @brief Configuration and management of SPIRIT General functionalities. - * @details See the file @ref SPIRIT_General.h for more details. - * @{ - */ - -/** - * @defgroup General_Exported_Types General Exported Types - * @{ - */ - - -/** - * @brief SPIRIT ModeExtRef enumeration - */ - -typedef enum -{ - MODE_EXT_XO = 0, - MODE_EXT_XIN = !MODE_EXT_XO -} ModeExtRef; - -#define IS_MODE_EXT(MODE) (MODE == MODE_EXT_XO || \ - MODE == MODE_EXT_XIN) - - -/** - * @brief SPIRIT BatteryLevel enumeration - */ - -typedef enum -{ - BLD_LVL_2_7_V = 0, - BLD_LVL_2_5_V = 1, - BLD_LVL_2_3_V = 2, - BLD_LVL_2_1_V = 3 -} BatteryLevel; - -#define IS_BLD_LVL(MODE) (MODE == BLD_LVL_2_7_V || \ - MODE == BLD_LVL_2_5_V || \ - MODE == BLD_LVL_2_3_V || \ - MODE == BLD_LVL_2_1_V) - - -/** - * @brief SPIRIT GmConf enumeration - */ - -typedef enum -{ - GM_SU_13_2 = 0, - GM_SU_18_2, - GM_SU_21_5, - GM_SU_25_6, - GM_SU_28_8, - GM_SU_33_9, - GM_SU_38_5, - GM_SU_43_0 -} GmConf; - -#define IS_GM_CONF(MODE) (MODE == GM_SU_13_2 || \ - MODE == GM_SU_18_2 || \ - MODE == GM_SU_21_5 || \ - MODE == GM_SU_25_6 || \ - MODE == GM_SU_28_8 || \ - MODE == GM_SU_33_9 || \ - MODE == GM_SU_38_5 || \ - MODE == GM_SU_43_0) - - -/** - * @brief SPIRIT packet type enumeration - */ - -typedef enum -{ - PKT_BASIC = 0x00, - PKT_MBUS = 0x02, - PKT_STACK - -} PacketType; - -#define IS_PKT_TYPE(TYPE) (TYPE == PKT_BASIC || \ - TYPE == PKT_MBUS || \ - TYPE == PKT_STACK || \ - ) - - -/** - * @brief SPIRIT version type enumeration - */ - -typedef enum -{ - SPIRIT_VERSION_2_1 = 0x01, /* Deprecated */ - SPIRIT_VERSION_3_0, /* The only version of SPIRIT1 */ -} SpiritVersion; - - -/** - * @} - */ - - -/** - * @defgroup General_Exported_Constants General Exported Constants - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup General_Exported_Macros General Exported Macros - * @{ - */ -#define SpiritGeneralLibraryVersion() "Spirit1_Libraries_v.3.2.0" - - -/** - * @} - */ - - -/** - * @defgroup General_Exported_Functions General Exported Functions - * @{ - */ - - -void SpiritGeneralBatteryLevel(SpiritFunctionalState xNewState); -void SpiritGeneralSetBatteryLevel(BatteryLevel xBatteryLevel); -BatteryLevel SpiritGeneralGetBatteryLevel(void); -void SpiritGeneralBrownOut(SpiritFunctionalState xNewState); -void SpiritGeneralHighPwr(SpiritFunctionalState xNewState); -void SpiritGeneralSetExtRef(ModeExtRef xExtMode); -ModeExtRef SpiritGeneralGetExtRef(void); -void SpiritGeneralSetXoGm(GmConf xGm); -GmConf SpiritGeneralGetXoGm(void); -PacketType SpiritGeneralGetPktType(void); -uint16_t SpiritGeneralGetDevicePartNumber(void); -uint8_t SpiritGeneralGetSpiritVersion(void); - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Gpio.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Gpio.h deleted file mode 100644 index 8ea32e004..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Gpio.h +++ /dev/null @@ -1,405 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Gpio.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief This file provides all the low level API to manage SPIRIT GPIO. - * - * @details - * - * This module can be used to configure the Spirit GPIO pins to perform - * specific functions. - * The structure @ref gpioIRQ can be used to specify these features for - * one of the four Spirit Gpio pin. - * The following example shows how to configure a pin (GPIO 3) to be used as an IRQ source - * for a microcontroller using the @ref SpiritGpioInit() function. - * - * Example: - * @code - * - * SGpioInit gpioIRQ={ - * SPIRIT_GPIO_3, - * SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, - * SPIRIT_GPIO_DIG_OUT_IRQ - * }; - * - * ... - * - * SpiritGpioInit(&gpioIRQ); - * - * @endcode - * - * @note Please read the functions documentation for the other GPIO features. - * - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_GPIO_H -#define __SPIRIT_GPIO_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** @defgroup SPIRIT_Gpio GPIO - * @brief Configuration and management of SPIRIT GPIO. - * @details See the file @ref SPIRIT_Gpio.h for more details. - * @{ - */ - - - -/** @defgroup Gpio_Exported_Types GPIO Exported Types - * @{ - */ - -/** - * @brief SPIRIT GPIO pin enumeration. - */ -typedef enum -{ - SPIRIT_GPIO_0 = GPIO0_CONF_BASE, /*!< GPIO_0 selected */ - SPIRIT_GPIO_1 = GPIO1_CONF_BASE, /*!< GPIO_1 selected */ - SPIRIT_GPIO_2 = GPIO2_CONF_BASE, /*!< GPIO_2 selected */ - SPIRIT_GPIO_3 = GPIO3_CONF_BASE /*!< GPIO_3 selected */ -}SpiritGpioPin; - - -#define IS_SPIRIT_GPIO(PIN) ((PIN == SPIRIT_GPIO_0) || \ - (PIN == SPIRIT_GPIO_1) || \ - (PIN == SPIRIT_GPIO_2) || \ - (PIN == SPIRIT_GPIO_3)) - - -/** - * @brief SPIRIT GPIO mode enumeration. - */ -typedef enum -{ - SPIRIT_GPIO_MODE_DIGITAL_INPUT = 0x01, /*!< Digital Input on GPIO */ - SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP = 0x02, /*!< Digital Output on GPIO (low current) */ - SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP = 0x03 /*!< Digital Output on GPIO (high current) */ -}SpiritGpioMode; - -#define IS_SPIRIT_GPIO_MODE(MODE) ((MODE == SPIRIT_GPIO_MODE_DIGITAL_INPUT) || \ - (MODE == SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP) || \ - (MODE == SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP)) - - - -/** - * @brief SPIRIT I/O selection enumeration. - */ -typedef enum -{ - SPIRIT_GPIO_DIG_OUT_IRQ = 0x00, /*!< nIRQ (Interrupt Request, active low) , default configuration after POR */ - SPIRIT_GPIO_DIG_OUT_POR_INV = 0x08, /*!< POR inverted (active low) */ - SPIRIT_GPIO_DIG_OUT_WUT_EXP = 0x10, /*!< Wake-Up Timer expiration: "1" when WUT has expired */ - SPIRIT_GPIO_DIG_OUT_LBD = 0x18, /*!< Low battery detection: "1" when battery is below threshold setting */ - SPIRIT_GPIO_DIG_OUT_TX_DATA = 0x20, /*!< TX data internal clock output (TX data are sampled on the rising edge of it) */ - SPIRIT_GPIO_DIG_OUT_TX_STATE = 0x28, /*!< TX state indication: "1" when Spirit1 is passing in the TX state */ - SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_EMPTY = 0x30, /*!< TX FIFO Almost Empty Flag */ - SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_FULL = 0x38, /*!< TX FIFO Almost Full Flag */ - SPIRIT_GPIO_DIG_OUT_RX_DATA = 0x40, /*!< RX data output */ - SPIRIT_GPIO_DIG_OUT_RX_CLOCK = 0x48, /*!< RX clock output (recovered from received data) */ - SPIRIT_GPIO_DIG_OUT_RX_STATE = 0x50, /*!< RX state indication: "1" when Spirit1 is passing in the RX state */ - SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_FULL = 0x58, /*!< RX FIFO Almost Full Flag */ - SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_EMPTY = 0x60, /*!< RX FIFO Almost Empty Flag */ - SPIRIT_GPIO_DIG_OUT_ANTENNA_SWITCH = 0x68, /*!< Antenna switch used for antenna diversity */ - SPIRIT_GPIO_DIG_OUT_VALID_PREAMBLE = 0x70, /*!< Valid Preamble Detected Flag */ - SPIRIT_GPIO_DIG_OUT_SYNC_DETECTED = 0x78, /*!< Sync WordSync Word Detected Flag */ - SPIRIT_GPIO_DIG_OUT_RSSI_THRESHOLD = 0x80, /*!< RSSI above threshold */ - SPIRIT_GPIO_DIG_OUT_MCU_CLOCK = 0x88, /*!< MCU Clock */ - SPIRIT_GPIO_DIG_OUT_TX_RX_MODE = 0x90, /*!< TX or RX mode indicator (to enable an external range extender) */ - SPIRIT_GPIO_DIG_OUT_VDD = 0x98, /*!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) */ - SPIRIT_GPIO_DIG_OUT_GND = 0xA0, /*!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) */ - SPIRIT_GPIO_DIG_OUT_SMPS_EXT = 0xA8, /*!< External SMPS enable signal (active high) */ - SPIRIT_GPIO_DIG_OUT_SLEEP_OR_STANDBY = 0xB0, - SPIRIT_GPIO_DIG_OUT_READY = 0xB8, - SPIRIT_GPIO_DIG_OUT_LOCK = 0xC0, - SPIRIT_GPIO_DIG_OUT_WAIT_FOR_LOCK_SIG = 0xC8, - SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_LOCK = 0xD0, - SPIRIT_GPIO_DIG_OUT_WAIT_FOR_READY2_SIG = 0xD8, - SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_PM_SET = 0xE0, - SPIRIT_GPIO_DIG_OUT_WAIT_VCO_CALIBRATION = 0xE8, - SPIRIT_GPIO_DIG_OUT_ENABLE_SYNTH_FULL_CIRCUIT = 0xF0, - SPIRIT_GPIO_DIG_OUT_WAIT_FOR_RCCAL_OK_SIG = 0xFF, - - SPIRIT_GPIO_DIG_IN_TX_COMMAND = 0x00, - SPIRIT_GPIO_DIG_IN_RX_COMMAND = 0x08, - SPIRIT_GPIO_DIG_IN_TX_DATA_INPUT_FOR_DIRECTRF = 0x10, - SPIRIT_GPIO_DIG_IN_DATA_WAKEUP = 0x18, - SPIRIT_GPIO_DIG_IN_EXT_CLOCK_AT_34_7KHZ = 0x20 - -}SpiritGpioIO; - -#define IS_SPIRIT_GPIO_IO(IO_SEL) ((IO_SEL == SPIRIT_GPIO_DIG_OUT_IRQ) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_POR_INV) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_WUT_EXP) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_LBD) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_DATA) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_STATE) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_EMPTY) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_FIFO_ALMOST_FULL) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_DATA) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_CLOCK) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_STATE) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_FULL) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_RX_FIFO_ALMOST_EMPTY) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_ANTENNA_SWITCH) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_VALID_PREAMBLE) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_SYNC_DETECTED) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_RSSI_THRESHOLD) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_MCU_CLOCK) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_TX_RX_MODE) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_VDD) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_GND) || \ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_SMPS_EXT) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_SLEEP_OR_STANDBY) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_READY) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_LOCK) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_LOCK_SIG) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_LOCK) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_READY2_SIG) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_TIMER_FOR_PM_SET) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_VCO_CALIBRATION) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_ENABLE_SYNTH_FULL_CIRCUIT) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_OUT_WAIT_FOR_RCCAL_OK_SIG) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_IN_TX_COMMAND) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_IN_RX_COMMAND) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_IN_TX_DATA_INPUT_FOR_DIRECTRF) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_IN_DATA_WAKEUP) ||\ - (IO_SEL == SPIRIT_GPIO_DIG_IN_EXT_CLOCK_AT_34_7KHZ)) - -/** - * @brief SPIRIT OutputLevel enumeration. - */ - -typedef enum -{ - LOW = 0, - HIGH = !LOW -}OutputLevel; - -#define IS_SPIRIT_GPIO_LEVEL(LEVEL) ((LEVEL == LOW) || \ - (LEVEL == HIGH)) - - -/** - * @brief SPIRIT GPIO Init structure definition. - */ -typedef struct -{ - SpiritGpioPin xSpiritGpioPin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref SpiritGpioPin */ - - SpiritGpioMode xSpiritGpioMode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref SpiritGpioMode */ - - SpiritGpioIO xSpiritGpioIO; /*!< Specifies the I/O selection for the selected pins. - This parameter can be a value of @ref SpiritGpioIO */ - -}SGpioInit; - - - -/** - * @brief SPIRIT clock output XO prescaler enumeration. - */ - -typedef enum -{ - XO_RATIO_1 = 0x00, /*!< XO Clock signal available on the GPIO divided by 1 */ - XO_RATIO_2_3 = 0x02, /*!< XO Clock signal available on the GPIO divided by 2/3 */ - XO_RATIO_1_2 = 0x04, /*!< XO Clock signal available on the GPIO divided by 1/2 */ - XO_RATIO_1_3 = 0x06, /*!< XO Clock signal available on the GPIO divided by 1/3 */ - XO_RATIO_1_4 = 0x08, /*!< XO Clock signal available on the GPIO divided by 1/4 */ - XO_RATIO_1_6 = 0x0A, /*!< XO Clock signal available on the GPIO divided by 1/6 */ - XO_RATIO_1_8 = 0x0C, /*!< XO Clock signal available on the GPIO divided by 1/8 */ - XO_RATIO_1_12 = 0x0E, /*!< XO Clock signal available on the GPIO divided by 1/12 */ - XO_RATIO_1_16 = 0x10, /*!< XO Clock signal available on the GPIO divided by 1/16 */ - XO_RATIO_1_24 = 0x12, /*!< XO Clock signal available on the GPIO divided by 1/24 */ - XO_RATIO_1_36 = 0x14, /*!< XO Clock signal available on the GPIO divided by 1/36 */ - XO_RATIO_1_48 = 0x16, /*!< XO Clock signal available on the GPIO divided by 1/48 */ - XO_RATIO_1_64 = 0x18, /*!< XO Clock signal available on the GPIO divided by 1/64 */ - XO_RATIO_1_96 = 0x1A, /*!< XO Clock signal available on the GPIO divided by 1/96 */ - XO_RATIO_1_128 = 0x1C, /*!< XO Clock signal available on the GPIO divided by 1/128 */ - XO_RATIO_1_192 = 0x1E /*!< XO Clock signal available on the GPIO divided by 1/196 */ -}ClockOutputXOPrescaler; - -#define IS_SPIRIT_CLOCK_OUTPUT_XO(RATIO) ((RATIO == XO_RATIO_1) || \ - (RATIO == XO_RATIO_2_3) || \ - (RATIO == XO_RATIO_1_2) || \ - (RATIO == XO_RATIO_1_3) || \ - (RATIO == XO_RATIO_1_4) || \ - (RATIO == XO_RATIO_1_6) || \ - (RATIO == XO_RATIO_1_8) || \ - (RATIO == XO_RATIO_1_12) || \ - (RATIO == XO_RATIO_1_16) || \ - (RATIO == XO_RATIO_1_24) || \ - (RATIO == XO_RATIO_1_36) || \ - (RATIO == XO_RATIO_1_48) || \ - (RATIO == XO_RATIO_1_64) || \ - (RATIO == XO_RATIO_1_96) || \ - (RATIO == XO_RATIO_1_128) || \ - (RATIO == XO_RATIO_1_192)) - -/** - * @brief SPIRIT Clock Output RCO prescaler enumeration. - */ - -typedef enum -{ - RCO_RATIO_1 = 0x00, /*!< RCO Clock signal available on the GPIO divided by 1 */ - RCO_RATIO_1_128 = 0x01 /*!< RCO Clock signal available on the GPIO divided by 1/128 */ -}ClockOutputRCOPrescaler; - -#define IS_SPIRIT_CLOCK_OUTPUT_RCO(RATIO) ((RATIO == RCO_RATIO_1) || \ - (RATIO == RCO_RATIO_1_128)) - -/** - * @brief SPIRIT ExtraClockCycles enumeration. - */ - -typedef enum -{ -EXTRA_CLOCK_CYCLES_0 = 0x00, /*!< 0 extra clock cycles provided to the MCU before switching to STANDBY state */ -EXTRA_CLOCK_CYCLES_64 = 0x20, /*!< 64 extra clock cycles provided to the MCU before switching to STANDBY state */ -EXTRA_CLOCK_CYCLES_256 = 0x40, /*!< 256 extra clock cycles provided to the MCU before switching to STANDBY state */ -EXTRA_CLOCK_CYCLES_512 = 0x60 /*!< 512 extra clock cycles provided to the MCU before switching to STANDBY state */ -}ExtraClockCycles; - -#define IS_SPIRIT_CLOCK_OUTPUT_EXTRA_CYCLES(CYCLES) ((CYCLES == EXTRA_CLOCK_CYCLES_0) || \ - (CYCLES == EXTRA_CLOCK_CYCLES_64) || \ - (CYCLES == EXTRA_CLOCK_CYCLES_256) || \ - (CYCLES == EXTRA_CLOCK_CYCLES_512)) - - -/** - * @brief SPIRIT Clock Output initialization structure definition. - */ -typedef struct -{ - ClockOutputXOPrescaler xClockOutputXOPrescaler; /*!< Specifies the XO Ratio as clock output. - This parameter can be any value of @ref ClockOutputXOPrescaler */ - - ClockOutputRCOPrescaler xClockOutputRCOPrescaler; /*!< Specifies the RCO Ratio as clock output. - This parameter can be a value of @ref ClockOutputRCOPrescaler */ - - ExtraClockCycles xExtraClockCycles; /*!< Specifies the Extra Clock Cycles provided before entering in Standby State. - This parameter can be a value of @ref ExtraClockCycles */ - -}ClockOutputInit; - - - -/** - * @} - */ - - - -/** @defgroup Gpio_Exported_Constants GPIO Exported Constants - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Gpio_Exported_Macros GPIO Exported Macros - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Gpio_Exported_Functions GPIO Exported Functions - * @{ - */ - -void SpiritGpioInit(SGpioInit* pxGpioInitStruct); -void SpiritGpioTemperatureSensor(SpiritFunctionalState xNewState); -void SpiritGpioSetLevel(SpiritGpioPin xGpioX, OutputLevel xLevel); -OutputLevel SpiritGpioGetLevel(SpiritGpioPin xGpioX); -void SpiritGpioClockOutput(SpiritFunctionalState xNewState); -void SpiritGpioClockOutputInit(ClockOutputInit* pxClockOutputInitStruct); -void SpiritGpioSetXOPrescaler(ClockOutputXOPrescaler xXOPrescaler); -ClockOutputXOPrescaler SpiritGpioGetXOPrescaler(void); -void SpiritGpioSetRCOPrescaler(ClockOutputRCOPrescaler xRCOPrescaler); -ClockOutputRCOPrescaler SpiritGpioGetRCOPrescaler(void); -void SpiritGpioSetExtraClockCycles(ExtraClockCycles xExtraCycles); -ExtraClockCycles SpiritGpioGetExtraClockCycles(void); - - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Irq.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Irq.h deleted file mode 100644 index 07ef93981..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Irq.h +++ /dev/null @@ -1,349 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Irq.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT IRQs. - * - * @details - * - * On the Spirit side specific IRQs can be enabled by setting a specific bitmask. - * The Spirit libraries allow the user to do this in two different ways: - *
    - * - *
  • The first enables the IRQs one by one, i.e. using an SPI transaction for each - * IRQ to enable. - * - * Example: - * @code - * - * SpiritIrqDeInit(NULL); // this call is used to reset the IRQ mask registers - * SpiritIrq(RX_DATA_READY , S_ENABLE); - * SpiritIrq(VALID_SYNC , S_ENABLE); - * SpiritIrq(RX_TIMEOUT , S_ENABLE); - * - * @endcode - * - *
    • - * - *
  • The second strategy is to set the IRQ bitfields structure. So, during the initialization the user - * has to fill the @ref SpiritIrqs structure setting to one the single field related to the IRQ he - * wants to enable, and to zero the single field related to all the IRQs he wants to disable. - * - * Example: - * @code - * - * SpiritIrqs irqMask; - * - * ... - * - * SpiritIrqDeInit(&irqMask); // this call is used to reset the IRQ mask registers - * // and to set to 0x00000000 the irq mask in order to disable - * // all IRQs (disabled by default on startup) - * irqMask.IRQ_RX_DATA_READY = 1; - * irqMask.IRQ_VALID_SYNC = 1; - * irqMask.IRQ_RX_TIMEOUT = 1; - * - * ... - * @endcode - *
    • - *
- * - * The most applications will require a Spirit IRQ notification on an microcontroller EXTI line. - * Then, the user can check which IRQ has been raised using two different ways. - * - * On the ISR of the EXTI line phisically linked to the Spirit pin configured for IRQ: - * - *
    - *
  • Check only one Spirit IRQ (because the Spirit IRQ status register automatically blanks itself - * after an SPI reading) into the ISR. - * - * Example: - * @code - * - * if(SpiritIrqCheckFlag(RX_DATA_READY)) - * { - * // do something... - * } - * - * @endcode - *
    • - * - *
  • Check more than one Spirit IRQ status by storing the entire IRQ status registers into a bitfields @ref SpiritIrqs structure - * and then check the interested bits. - * - * Example: - * @code - * - * SpiritIrqGetStatus(&irqStatus); - * - * if(irqStatus.IRQ_RX_DATA_READY) - * { - * // do something... - * } - * if(irqStatus.IRQ_VALID_SYNC) - * { - * // do something... - * } - * if(irqStatus.RX_TIMEOUT) - * { - * // do something... - * } - * - * @endcode - *
    • - *
- * - - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT1_IRQ_H -#define __SPIRIT1_IRQ_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Irq IRQ - * @brief Configuration and management of SPIRIT IRQs. - * @details See the file @ref SPIRIT_Irq.h for more details. - * @{ - */ - -/** - * @defgroup Irq_Exported_Types IRQ Exported Types - * @{ - */ - - -/** - * @brief IRQ bitfield structure for SPIRIT. This structure is used to read or write the single IRQ bit. - * During the initialization the user has to fill this structure setting to one the single field related - * to the IRQ he wants to enable, and to zero the single field related to all the IRQs he wants to disable. - * The same structure can be used to retrieve all the IRQ events from the IRQ registers IRQ_STATUS[3:0], - * and read if one or more specific IRQ raised. - * @note The fields order in the structure depends on used endianness (little or big - * endian). The actual definition is valid ONLY for LITTLE ENDIAN mode. Be sure to - * change opportunely the fields order when use a different endianness. - */ -typedef struct -{ - SpiritFlagStatus IRQ_RX_DATA_READY:1; /*!< IRQ: RX data ready */ - SpiritFlagStatus IRQ_RX_DATA_DISC:1; /*!< IRQ: RX data discarded (upon filtering) */ - SpiritFlagStatus IRQ_TX_DATA_SENT:1; /*!< IRQ: TX data sent */ - SpiritFlagStatus IRQ_MAX_RE_TX_REACH:1; /*!< IRQ: Max re-TX reached */ - SpiritFlagStatus IRQ_CRC_ERROR:1; /*!< IRQ: CRC error */ - SpiritFlagStatus IRQ_TX_FIFO_ERROR:1; /*!< IRQ: TX FIFO underflow/overflow error */ - SpiritFlagStatus IRQ_RX_FIFO_ERROR:1; /*!< IRQ: RX FIFO underflow/overflow error */ - SpiritFlagStatus IRQ_TX_FIFO_ALMOST_FULL:1; /*!< IRQ: TX FIFO almost full */ - - SpiritFlagStatus IRQ_TX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: TX FIFO almost empty */ - SpiritFlagStatus IRQ_RX_FIFO_ALMOST_FULL:1; /*!< IRQ: RX FIFO almost full */ - SpiritFlagStatus IRQ_RX_FIFO_ALMOST_EMPTY:1; /*!< IRQ: RX FIFO almost empty */ - SpiritFlagStatus IRQ_MAX_BO_CCA_REACH:1; /*!< IRQ: Max number of back-off during CCA */ - SpiritFlagStatus IRQ_VALID_PREAMBLE:1; /*!< IRQ: Valid preamble detected */ - SpiritFlagStatus IRQ_VALID_SYNC:1; /*!< IRQ: Sync word detected */ - SpiritFlagStatus IRQ_RSSI_ABOVE_TH:1; /*!< IRQ: RSSI above threshold */ - SpiritFlagStatus IRQ_WKUP_TOUT_LDC:1; /*!< IRQ: Wake-up timeout in LDC mode */ - - SpiritFlagStatus IRQ_READY:1; /*!< IRQ: READY state */ - SpiritFlagStatus IRQ_STANDBY_DELAYED:1; /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ - SpiritFlagStatus IRQ_LOW_BATT_LVL:1; /*!< IRQ: Battery level below threshold*/ - SpiritFlagStatus IRQ_POR:1; /*!< IRQ: Power On Reset */ - SpiritFlagStatus IRQ_BOR:1; /*!< IRQ: Brown out event (both accurate and inaccurate)*/ - SpiritFlagStatus IRQ_LOCK:1; /*!< IRQ: LOCK state */ - SpiritFlagStatus IRQ_PM_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ - SpiritFlagStatus IRQ_XO_COUNT_EXPIRED:1; /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ - - SpiritFlagStatus IRQ_SYNTH_LOCK_TIMEOUT:1; /*!< IRQ: only for debug; LOCK state timeout */ - SpiritFlagStatus IRQ_SYNTH_LOCK_STARTUP:1; /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ - SpiritFlagStatus IRQ_SYNTH_CAL_TIMEOUT:1; /*!< IRQ: only for debug; SYNTH calibration timeout */ - SpiritFlagStatus IRQ_TX_START_TIME:1; /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ - SpiritFlagStatus IRQ_RX_START_TIME:1; /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ - SpiritFlagStatus IRQ_RX_TIMEOUT:1; /*!< IRQ: RX operation timeout */ - SpiritFlagStatus IRQ_AES_END:1; /*!< IRQ: AES End of operation */ - SpiritFlagStatus :1; /*!< Reserved bit */ - -} SpiritIrqs; - - -/** - * @brief IRQ list enumeration for SPIRIT. This enumeration type can be used to address a - * specific IRQ. - */ -typedef enum -{ - RX_DATA_READY = 0x00000001, /*!< IRQ: RX data ready */ - RX_DATA_DISC = 0x00000002, /*!< IRQ: RX data discarded (upon filtering) */ - TX_DATA_SENT = 0x00000004, /*!< IRQ: TX data sent */ - MAX_RE_TX_REACH = 0x00000008, /*!< IRQ: Max re-TX reached */ - CRC_ERROR = 0x00000010, /*!< IRQ: CRC error */ - TX_FIFO_ERROR = 0x00000020, /*!< IRQ: TX FIFO underflow/overflow error */ - RX_FIFO_ERROR = 0x00000040, /*!< IRQ: RX FIFO underflow/overflow error */ - TX_FIFO_ALMOST_FULL = 0x00000080, /*!< IRQ: TX FIFO almost full */ - TX_FIFO_ALMOST_EMPTY = 0x00000100, /*!< IRQ: TX FIFO almost empty */ - RX_FIFO_ALMOST_FULL = 0x00000200, /*!< IRQ: RX FIFO almost full */ - RX_FIFO_ALMOST_EMPTY = 0x00000400, /*!< IRQ: RX FIFO almost empty */ - MAX_BO_CCA_REACH = 0x00000800, /*!< IRQ: Max number of back-off during CCA */ - VALID_PREAMBLE = 0x00001000, /*!< IRQ: Valid preamble detected */ - VALID_SYNC = 0x00002000, /*!< IRQ: Sync word detected */ - RSSI_ABOVE_TH = 0x00004000, /*!< IRQ: RSSI above threshold */ - WKUP_TOUT_LDC = 0x00008000, /*!< IRQ: Wake-up timeout in LDC mode */ - READY = 0x00010000, /*!< IRQ: READY state */ - STANDBY_DELAYED = 0x00020000, /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ - LOW_BATT_LVL = 0x00040000, /*!< IRQ: Battery level below threshold*/ - POR = 0x00080000, /*!< IRQ: Power On Reset */ - BOR = 0x00100000, /*!< IRQ: Brown out event (both accurate and inaccurate)*/ - LOCK = 0x00200000, /*!< IRQ: LOCK state */ - PM_COUNT_EXPIRED = 0x00400000, /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ - XO_COUNT_EXPIRED = 0x00800000, /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ - SYNTH_LOCK_TIMEOUT = 0x01000000, /*!< IRQ: only for debug; LOCK state timeout */ - SYNTH_LOCK_STARTUP = 0x02000000, /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ - SYNTH_CAL_TIMEOUT = 0x04000000, /*!< IRQ: only for debug; SYNTH calibration timeout */ - TX_START_TIME = 0x08000000, /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ - RX_START_TIME = 0x10000000, /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ - RX_TIMEOUT = 0x20000000, /*!< IRQ: RX operation timeout */ - AES_END = 0x40000000, /*!< IRQ: AES End of operation */ - ALL_IRQ = 0x7FFFFFFF /*!< All the above mentioned IRQs */ - -} IrqList; - -#define IS_SPIRIT_IRQ_LIST(VALUE) ((VALUE == RX_DATA_READY) || \ - (VALUE == RX_DATA_DISC) || \ - (VALUE == TX_DATA_SENT) || \ - (VALUE == MAX_RE_TX_REACH) || \ - (VALUE == CRC_ERROR) || \ - (VALUE == TX_FIFO_ERROR) || \ - (VALUE == RX_FIFO_ERROR) || \ - (VALUE == TX_FIFO_ALMOST_FULL) || \ - (VALUE == TX_FIFO_ALMOST_EMPTY) || \ - (VALUE == RX_FIFO_ALMOST_FULL) || \ - (VALUE == RX_FIFO_ALMOST_EMPTY) || \ - (VALUE == MAX_BO_CCA_REACH) || \ - (VALUE == VALID_PREAMBLE) || \ - (VALUE == VALID_SYNC) || \ - (VALUE == RSSI_ABOVE_TH) || \ - (VALUE == WKUP_TOUT_LDC) || \ - (VALUE == READY) || \ - (VALUE == STANDBY_DELAYED) || \ - (VALUE == LOW_BATT_LVL) || \ - (VALUE == POR) || \ - (VALUE == BOR) || \ - (VALUE == LOCK) || \ - (VALUE == PM_COUNT_EXPIRED) || \ - (VALUE == XO_COUNT_EXPIRED) || \ - (VALUE == SYNTH_LOCK_TIMEOUT) || \ - (VALUE == SYNTH_LOCK_STARTUP) || \ - (VALUE == SYNTH_CAL_TIMEOUT) || \ - (VALUE == TX_START_TIME) || \ - (VALUE == RX_START_TIME) || \ - (VALUE == RX_TIMEOUT) || \ - (VALUE == AES_END) || \ - (VALUE == ALL_IRQ )) - - -/** - * @} - */ - - -/** - * @defgroup Irq_Exported_Constants IRQ Exported Constants - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup Irq_Exported_Macros IRQ Exported Macros - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup Irq_Exported_Functions IRQ Exported Functions - * @{ - */ - -void SpiritIrqDeInit(SpiritIrqs* pxIrqInit); -void SpiritIrqInit(SpiritIrqs* pxIrqInit); -void SpiritIrq(IrqList xIrq, SpiritFunctionalState xNewState); -void SpiritIrqGetMask(SpiritIrqs* pxIrqMask); -void SpiritIrqGetStatus(SpiritIrqs* pxIrqStatus); -void SpiritIrqClearStatus(void); -SpiritBool SpiritIrqCheckFlag(IrqList xFlag); - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_LinearFifo.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_LinearFifo.h deleted file mode 100644 index f4e66a0ad..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_LinearFifo.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_LinearFifo.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT Fifo. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_LINEAR_FIFO_H -#define __SPIRIT_LINEAR_FIFO_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_LinearFifo Linear FIFO - * @brief Configuration and management of SPIRIT FIFO. - * @details See the file @ref SPIRIT_LinearFifo.h for more details. - * @{ - */ - -/** - * @defgroup LinearFifo_Exported_Types Linear FIFO Exported Types - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup LinearFifo_Exported_Constants Linear FIFO Exported Constants - * @{ - */ -#define IS_FIFO_THR(VAL) (VAL<=96) - -/** - * @} - */ - - -/** - * @defgroup LinearFifo_Exported_Macros Linear FIFO Exported Macros - * @{ - */ - - -/** - * @} - */ - - -/** - * @defgroup LinearFifo_Exported_Functions Linear FIFO Exported Functions - * @{ - */ - -uint8_t SpiritLinearFifoReadNumElementsRxFifo(void); -uint8_t SpiritLinearFifoReadNumElementsTxFifo(void); -void SpiritLinearFifoSetAlmostFullThresholdRx(uint8_t cThrRxFifo); -uint8_t SpiritLinearFifoGetAlmostFullThresholdRx(void); -void SpiritLinearFifoSetAlmostEmptyThresholdRx(uint8_t cThrRxFifo); -uint8_t SpiritLinearFifoGetAlmostEmptyThresholdRx(void); -void SpiritLinearFifoSetAlmostFullThresholdTx(uint8_t cThrTxFifo); -uint8_t SpiritLinearFifoGetAlmostFullThresholdTx(void); -void SpiritLinearFifoSetAlmostEmptyThresholdTx(uint8_t cThrTxFifo); -uint8_t SpiritLinearFifoGetAlmostEmptyThresholdTx(void); - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Management.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Management.h deleted file mode 100644 index 0f1bc49e2..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Management.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Management.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief The management layer for SPIRIT1 library. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef SPIRIT_MANAGEMENT_H_ -#define SPIRIT_MANAGEMENT_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Config.h" - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_MANAGEMENT Management - * @brief Workarounds for Spirit1. - * @details See the file @ref SPIRIT_Management.h for more details. - * @{ - */ - - -/** - * @addgroup SPIRIT_MANAGEMENT_FUNCTIONS - * @{ - */ - - - - -uint8_t SpiritManagementWaVcoCalibration(void); -void SpiritManagementWaCmdStrobeTx(void); -void SpiritManagementWaCmdStrobeRx(void); -void SpiritManagementWaTRxFcMem(uint32_t nDesiredFreq); -void SpiritManagementWaExtraCurrent(void); - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -#ifdef __cplusplus -} -#endif - - -#endif - - - /******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ - diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktBasic.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktBasic.h deleted file mode 100644 index 743cbb94e..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktBasic.h +++ /dev/null @@ -1,696 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktBasic.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT Basic packets. - * - * @details - * - * This module can be used to manage the configuration of Spirit Basic - * packets. - * The user can obtain a packet configuration filling the structure - * @ref PktBasicInit, defining in it some general parameters - * for the Spirit Basic packet format. - * Another structure the user can fill is @ref PktBasicAddressesInit - * to define the addresses which will be used during the communication. - * Moreover, functions to set the payload length and the destination address - * are provided. - * - * Example: - * @code - * - * PktBasicInit basicInit={ - * PKT_PREAMBLE_LENGTH_08BYTES, // preamble length in bytes - * PKT_SYNC_LENGTH_4BYTES, // sync word length in bytes - * 0x1A2635A8, // sync word - * PKT_LENGTH_VAR, // variable or fixed payload length - * 7, // length field width in bits (used only for variable length) - * PKT_NO_CRC, // CRC mode - * PKT_CONTROL_LENGTH_0BYTES, // control field length - * S_ENABLE, // address field - * S_DISABLE, // FEC - * S_ENABLE // whitening - * }; - * - * PktBasicAddressesInit addressInit={ - * S_ENABLE, // enable/disable filtering on my address - * 0x34, // my address (address of the current node) - * S_DISABLE, // enable/disable filtering on multicast address - * 0xEE, // multicast address - * S_DISABLE, // enable/disable filtering on broadcast address - * 0xFF // broadcast address - * }; - * - * ... - * - * SpiritPktBasicInit(&basicInit); - * SpiritPktBasicAddressesInit(&addressInit); - * - * ... - * - * SpiritPktBasicSetPayloadLength(20); - * SpiritPktBasicSetDestinationAddress(0x44); - * - * ... - * - * @endcode - * - * The module provides some other functions that can be used to modify - * or read only some configuration parameters. - * - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_PKT_BASIC_H -#define __SPIRIT_PKT_BASIC_H - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" -#include "SPIRIT_PktCommon.h" - -#ifdef __cplusplus - extern "C" { -#endif - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_PktBasic Pkt Basic - * @brief Configuration and management of SPIRIT Basic packets. - * @details See the file @ref SPIRIT_PktBasic.h for more details. - * @{ - */ - -/** - * @defgroup PktBasic_Exported_Types Pkt Basic Exported Types - * @{ - */ - - -/** - * @brief Preamble length in bytes enumeration. - */ -typedef PktPreambleLength BasicPreambleLength; - -#define IS_BASIC_PREAMBLE_LENGTH IS_PKT_PREAMBLE_LENGTH - -/** - * @brief Sync length in bytes enumeration. - */ -typedef PktSyncLength BasicSyncLength; - -#define IS_BASIC_SYNC_LENGTH IS_PKT_SYNC_LENGTH - - - -/** - * @brief CRC length in bytes enumeration. - */ -typedef PktCrcMode BasicCrcMode; - -#define IS_BASIC_CRC_MODE IS_PKT_CRC_MODE - - -/** - * @brief Fixed or variable payload length enumeration. - */ -typedef PktFixVarLength BasicFixVarLength; - -#define IS_BASIC_FIX_VAR_LENGTH IS_PKT_FIX_VAR_LENGTH - -/** - * @brief Control length in bytes enumeration. - */ -typedef PktControlLength BasicControlLength; - -#define IS_BASIC_CONTROL_LENGTH IS_PKT_CONTROL_LENGTH - -/** - * @brief Sync words enumeration. - */ -typedef PktSyncX BasicSyncX; - -#define IS_BASIC_SYNCx IS_PKT_SYNCx - - -/** - * @brief SPIRIT Basic Packet Init structure definition. This structure allows users to set the main options - * for the Basic packet. - */ -typedef struct -{ - - BasicPreambleLength xPreambleLength; /*!< Specifies the preamble length. - This parameter can be any value of @ref BasicPreambleLength */ - BasicSyncLength xSyncLength; /*!< Specifies the sync word length. The 32bit word passed (lSyncWords) will be stored in the SYNCx registers from the MSb - until the number of bytes in xSyncLength has been stored. - This parameter can be any value of @ref BasicSyncLength */ - uint32_t lSyncWords; /*!< Specifies the sync words. - This parameter is a uint32_t word with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4| */ - BasicFixVarLength xFixVarLength; /*!< Specifies if a fixed length of packet has to be used. - This parameter can be any value of @ref BasicFixVarLength */ - uint8_t cPktLengthWidth; /*!< Specifies the size of the length of packet in bits. This field is useful only if - the field xFixVarLength is set to BASIC_LENGTH_VAR. For Basic packets the length width - is log2( max payload length + control length (0 to 4) + address length (0 or 1)). - This parameter is an uint8_t */ - BasicCrcMode xCrcMode; /*!< Specifies the CRC word length of packet. - This parameter can be any value of @ref BasicCrcMode */ - BasicControlLength xControlLength; /*!< Specifies the length of a control field to be sent. - This parameter can be any value of @ref BasicControlLength */ - SpiritFunctionalState xAddressField; /*!< Specifies if the destination address has to be sent. - This parameter can be S_ENABLE or S_DISABLE */ - SpiritFunctionalState xFec; /*!< Specifies if FEC has to be enabled. - This parameter can be S_ENABLE or S_DISABLE */ - SpiritFunctionalState xDataWhitening; /*!< Specifies if data whitening has to be enabled. - This parameter can be S_ENABLE or S_DISABLE */ -}PktBasicInit; - - -/** - * @brief SPIRIT Basic Packet address structure definition. This structure allows users to specify - * the node/multicast/broadcast addresses and the correspondent filtering options. - */ -typedef struct -{ - - SpiritFunctionalState xFilterOnMyAddress; /*!< If set RX packet is accepted if its destination address matches with cMyAddress. - This parameter can be S_ENABLE or S_DISABLE */ - uint8_t cMyAddress; /*!< Specifies the TX packet source address (address of this node). - This parameter is an uint8_t */ - SpiritFunctionalState xFilterOnMulticastAddress; /*!< If set RX packet is accepted if its destination address matches with cMulticastAddress. - This parameter can be S_ENABLE or S_DISABLE */ - uint8_t cMulticastAddress; /*!< Specifies the Multicast group address for this node. - This parameter is an uint8_t */ - SpiritFunctionalState xFilterOnBroadcastAddress; /*!< If set RX packet is accepted if its destination address matches with cBroadcastAddress. - This parameter can be S_ENABLE or S_DISABLE */ - uint8_t cBroadcastAddress; /*!< Specifies the Broadcast address for this node. - This parameter is an uint8_t */ -}PktBasicAddressesInit; - -/** - *@} - */ - - -/** - * @defgroup PktBasic_Exported_Constants Pkt Basic Exported Constants - * @{ - */ - -#define IS_BASIC_LENGTH_WIDTH_BITS IS_PKT_LENGTH_WIDTH_BITS - - -/** - *@} - */ - - -/** - * @defgroup PktBasic_Exported_Macros Pkt Basic Exported Macros - * @{ - */ - -/** - * @brief Macro used to compute per lower part of the packet length - * for Spirit Basic packets, to write in the PCKTLEN0 register. - * @param nLength Length of the packet payload. - * This parameter is an uint16_t. - * @retval None. - */ -#define BASIC_BUILD_PCKTLEN0(nLength) BUILD_PCKTLEN0(nLength) - - -/** - * @brief Macro used to compute per upper part of the packet length - * for Spirit Basic packets, to write the PCKTLEN1 register. - * @param nLengthLength of the packet payload. - * This parameter is an uint16_t. - * @retval None. - */ -#define BASIC_BUILD_PCKTLEN1(nLength) BUILD_PCKTLEN1(nLength) - -/** - * @brief Sets the CONTROL field length for SPIRIT Basic packets. - * @param xControlLength length of CONTROL field in bytes. - * This parameter can be any value of @ref PktControlLength. - * @retval None. - */ -#define SpiritPktBasicSetControlLength(xControlLength) SpiritPktCommonSetControlLength(xControlLength) - - -/** - * @brief Returns the CONTROL field length for SPIRIT Basic packets. - * @param None. - * @retval uint8_t Control field length. - */ -#define SpiritPktBasicGetControlLength() SpiritPktCommonGetControlLength() - - -/** - * @brief Sets the PREAMBLE field length for SPIRIT Basic packets. - * @param xPreambleLength length of PREAMBLE field in bytes. - * This parameter can be any value of @ref BasicPreambleLength. - * @retval None. - */ -#define SpiritPktBasicSetPreambleLength(xPreambleLength) SpiritPktCommonSetPreambleLength((PktPreambleLength)xPreambleLength) - - -/** - * @brief Returns the PREAMBLE field length mode for SPIRIT Basic packets. - * @param None. - * @retval uint8_t Preamble field length in bytes. - */ -#define SpiritPktBasicGetPreambleLength() SpiritPktCommonGetPreambleLength() - - -/** - * @brief Sets the SYNC field length for SPIRIT Basic packets. - * @param xSyncLength length of SYNC field in bytes. - * This parameter can be any value of @ref BasicSyncLength. - * @retval None. - */ -#define SpiritPktBasicSetSyncLength(xSyncLength) SpiritPktCommonSetSyncLength((PktSyncLength)xSyncLength) - - -/** - * @brief Returns the SYNC field length for SPIRIT Basic packets. - * @param None. - * @retval uint8_t SYNC field length in bytes. - */ -#define SpiritPktBasicGetSyncLength() SpiritPktCommonGetSyncLength() - - -/** - * @brief Sets fixed or variable payload length mode for SPIRIT packets. - * @param xFixVarLength variable or fixed length. - * BASIC_FIXED_LENGTH_VAR -> variable (the length is extracted from the received packet). - * BASIC_FIXED_LENGTH_FIX -> fix (the length is set by PCKTLEN0 and PCKTLEN1). - * @retval None. - */ -#define SpiritPktBasicSetFixVarLength(xFixVarLength) SpiritPktCommonSetFixVarLength((PktFixVarLength)xFixVarLength) - - -/** - * @brief Enables or Disables the CRC filtering. - * @param xNewState new state for CRC_CHECK. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktBasicFilterOnCrc(xNewState) SpiritPktCommonFilterOnCrc(xNewState) - - -/** - * @brief Returns the CRC filtering bit. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktBasicGetFilterOnCrc() SpiritPktCommonGetFilterOnCrc() - - -/** - * @brief Sets the CRC mode for SPIRIT Basic packets. - * @param xCrcMode CRC mode. - * This parameter can be any value of @ref BasicCrcMode. - * @retval None. - */ -#define SpiritPktBasicSetCrcMode(xCrcMode) SpiritPktCommonSetCrcMode((PktCrcMode)xCrcMode) - - -/** - * @brief Returns the CRC mode for SPIRIT Basic packets. - * @param None. - * @retval BasicCrcMode Crc mode. - */ -#define SpiritPktBasicGetCrcMode() (BasicCrcMode)SpiritPktCommonGetCrcMode() - - -/** - * @brief Enables or Disables WHITENING for SPIRIT packets. - * @param xNewState new state for WHITENING mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktBasicWhitening(xNewState) SpiritPktCommonWhitening(xNewState) - - -/** - * @brief Enables or Disables FEC for SPIRIT Basic packets. - * @param xNewState new state for FEC mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktBasicFec(xNewState) SpiritPktCommonFec(xNewState) - - -/** - * @brief Sets a specific SYNC word for SPIRIT Basic packets. - * @param xSyncX SYNC word number to be set. - * This parameter can be any value of @ref BasicSyncX. - * @param cSyncWord SYNC word. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktBasicSetSyncxWord(xSyncX, cSyncWord) SpiritPktCommonSetSyncxWord((PktSyncX)xSyncX, cSyncWord) - - -/** - * @brief Returns a specific SYNC words for SPIRIT Basic packets. - * @param xSyncX SYNC word number to be get. - * This parameter can be any value of @ref BasicSyncX. - * @retval uint8_t Sync word x. - */ -#define SpiritPktBasicGetSyncxWord(xSyncX) SpiritPktCommonGetSyncxWord(xSyncX) - - -/** - * @brief Sets multiple SYNC words for SPIRIT Basic packets. - * @param lSyncWords SYNC words to be set with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4|. - * This parameter is a uint32_t. - * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb - * until the number of bytes in xSyncLength has been stored. - * This parameter is a @ref BasicSyncLength. - * @retval None. - */ -#define SpiritPktBasicSetSyncWords(lSyncWords, xSyncLength) SpiritPktCommonSetSyncWords(lSyncWords, (PktSyncLength)xSyncLength) - - -/** - * @brief Returns multiple SYNC words for SPIRIT Basic packets. - * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb - * until the number of bytes in xSyncLength has been stored. - * This parameter is a pointer to @ref BasicSyncLength. - * @retval uint32_t Sync words. The format of the read 32 bit word is 0x|SYNC1|SYNC2|SYNC3|SYNC4|. - */ -#define SpiritPktBasicGetSyncWords(xSyncLength) SpiritPktCommonGetSyncWords((PktSyncLength)xSyncLength) - - -/** - * @brief Returns the SPIRIT variable length width (in number of bits). - * @param None. - * @retval Variable length width in bits. - */ -#define SpiritPktBasicGetVarLengthWidth() SpiritPktCommonGetVarLengthWidth() - - -/** - * @brief Sets the destination address for the Tx packet. - * @param cAddress destination address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktBasicSetDestinationAddress(cAddress) SpiritPktCommonSetDestinationAddress(cAddress) - - -/** - * @brief Returns the settled destination address. - * @param None. - * @retval uint8_t Transmitted destination address. - */ -#define SpiritPktBasicGetTransmittedDestAddress() SpiritPktCommonGetTransmittedDestAddress() - - -/** - * @brief Sets the node address. When the filtering on my address is on, if the destination address extracted from the received packet is equal to the content of the - * my address, then the packet is accepted (this is the address of the node). - * @param cAddress Address of the present node. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktBasicSetMyAddress(cAddress) SpiritPktCommonSetMyAddress(cAddress) - - -/** - * @brief Returns the address of the present node. - * @param None. - * @retval uint8_t My address (address of this node). - */ -#define SpiritPktBasicGetMyAddress() SpiritPktCommonGetMyAddress() - - -/** - * @brief Sets the broadcast address. When the broadcast filtering is on, if the destination address extracted from the received packet is equal to the content of the - * BROADCAST_ADDR register, then the packet is accepted. - * @param cAddress Broadcast address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktBasicSetBroadcastAddress(cAddress) SpiritPktCommonSetBroadcastAddress(cAddress) - - -/** - * @brief Returns the broadcast address. - * @param None. - * @retval uint8_t Broadcast address. - */ -#define SpiritPktBasicGetBroadcastAddress() SpiritPktCommonGetBroadcastAddress() - - -/** - * @brief Sets the multicast address. When the multicast filtering is on, if the destination address extracted from the received packet is equal to the content of the - * MULTICAST_ADDR register, then the packet is accepted. - * @param cAddress Multicast address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktBasicSetMulticastAddress(cAddress) SpiritPktCommonSetMulticastAddress(cAddress) - - -/** - * @brief Returns the multicast address. - * @param None. - * @retval uint8_t Multicast address. - */ -#define SpiritPktBasicGetMulticastAddress() SpiritPktCommonGetMulticastAddress() - - -/** - * @brief Sets the control mask. The 1 bits of the CONTROL_MASK indicate the - * bits to be used in filtering. (All 0s no filtering) - * @param lMask Control mask. - * This parameter is an uint32_t. - * @retval None. - */ -#define SpiritPktBasicSetCtrlMask(lMask) SpiritPktCommonSetCtrlMask(lMask) - - -/** - * @brief Returns the control mask. The 1 bits of the CONTROL_MASK indicate the - * bits to be used in filtering. (All 0s no filtering) - * @param None. - * @retval uint32_t Control mask. - */ -#define SpiritPktBasicGetCtrlMask() SpiritPktCommonGetCtrlMask() - - -/** - * @brief Sets the control field reference. If the bits enabled by the - * CONTROL_MASK match the ones of the control fields extracted from the received packet - * then the packet is accepted. - * @param lReference Control reference. - * This parameter is an uint32_t. - * @retval None. - */ -#define SpiritPktBasicSetCtrlReference(lReference) SpiritPktCommonSetCtrlReference(lReference) - - -/** - * @brief Returns the control field reference. - * @param None. - * @retval uint32_t Control reference. - */ -#define SpiritPktBasicGetCtrlReference() SpiritPktCommonGetCtrlReference() - - -/** - * @brief Sets the TX control field. - * @param lField Tx control field. - * This parameter is an uint32_t. - * @retval None. - */ -#define SpiritPktBasicSetTransmittedCtrlField(lField) SpiritPktCommonSetTransmittedCtrlField(lField) - - -/** - * @brief Returns the TX control field. - * @param None. - * @retval uint32_t Control field of the transmitted packet. - */ -#define SpiritPktBasicGetTransmittedCtrlField() SpiritPktCommonGetTransmittedCtrlField() - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with My address. - * @param xNewState new state for DEST_VS_SOURCE_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktBasicFilterOnMyAddress(xNewState) SpiritPktCommonFilterOnMyAddress(xNewState) - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with multicast address. - * @param xNewState new state for DEST_VS_MULTICAST_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktBasicFilterOnMulticastAddress(xNewState) SpiritPktCommonFilterOnMulticastAddress(xNewState) - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with broadcast address. - * @param xNewState new state for DEST_VS_BROADCAST_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktBasicFilterOnBroadcastAddress(xNewState) SpiritPktCommonFilterOnBroadcastAddress(xNewState) - - -/** - * @brief Returns the enable bit of the my address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktBasicGetFilterOnMyAddress() SpiritPktCommonGetFilterOnMyAddress(); - - -/** - * @brief Returns the enable bit of the multicast address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktBasicGetFilterOnMulticastAddress() SpiritPktCommonGetFilterOnMulticastAddress(); - - -/** - * @brief Returns the enable bit of the broadcast address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktBasicGetFilterOnBroadcastAddress() SpiritPktCommonGetFilterOnBroadcastAddress(); - - -/** - * @brief Returns the destination address of the received packet. - * @param None. - * @retval uint8_t Destination address of the received packet. - */ -#define SpiritPktBasicGetReceivedDestAddress() SpiritPktCommonGetReceivedDestAddress() - - -/** - * @brief Returns the control field of the received packet. - * @param None. - * @retval uint32_t Received control field. - */ -#define SpiritPktBasicGetReceivedCtrlField() SpiritPktCommonGetReceivedCtrlField() - - -/** - * @brief Returns the CRC field of the received packet. - * @param cCrcFieldVect array in which the CRC field has to be stored. - * This parameter is an uint8_t array of 3 elements. - * @retval None. - */ -#define SpiritPktBasicGetReceivedCrcField(cCrcFieldVect) SpiritPktCommonGetReceivedCrcField(cCrcFieldVect) - - -/** - * @brief If enabled RX packet is accepted only if the masked control field matches the - * masked control field reference (CONTROL_MASK & CONTROL_FIELD_REF == CONTROL_MASK & RX_CONTROL_FIELD). - * @param xNewState new state for Control filtering enable bit. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - * @note This filtering control is enabled by default but the control mask is by default set to 0. - * As a matter of fact the user has to enable the control filtering bit after the packet initialization - * because the PktInit routine disables it. - */ -#define SpiritPktBasicFilterOnControlField(xNewState) SpiritPktCommonFilterOnControlField(xNewState) - - -/** - * @brief Returns the enable bit of the control field filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktBasicGetFilterOnControlField() SpiritPktCommonGetFilterOnControlField(); - -/** - *@} - */ - - -/** - * @defgroup PktBasic_Exported_Functions Pkt Basic Exported Functions - * @{ - */ - -void SpiritPktBasicInit(PktBasicInit* pxPktBasicInit); -void SpiritPktBasicGetInfo(PktBasicInit* pxPktBasicInit); -void SpiritPktBasicAddressesInit(PktBasicAddressesInit* pxPktBasicAddresses); -void SpiritPktBasicGetAddressesInfo(PktBasicAddressesInit* pxPktBasicAddresses); -void SpiritPktBasicSetFormat(void); -void SpiritPktBasicAddressField(SpiritFunctionalState xAddressField); -SpiritFunctionalState SpiritPktBasicGetAddressField(void); -void SpiritPktBasicSetPayloadLength(uint16_t nPayloadLength); -uint16_t SpiritPktBasicGetPayloadLength(void); -uint16_t SpiritPktBasicGetReceivedPktLength(void); -void SpiritPktBasicSetVarLengthWidth(uint16_t nMaxPayloadLength,SpiritFunctionalState xAddressField, BasicControlLength xControlLength); - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktCommon.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktCommon.h deleted file mode 100644 index ce81e8e4a..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktCommon.h +++ /dev/null @@ -1,432 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktCommon.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of the common features of SPIRIT packets. - * - * @details - * - * This module provides all the common functions and definitions used by the - * packets modules. - * Here are also defined all the generic enumeration types that are redefined - * in the specific packets modules, but every enumeration value is referred - * to this module. So the user who wants to configure the preamble of a Basic, - * or a STack packet has to use the enumeration values defined here. - * - * Example: - * @code - * - * ... - * - * SpiritPktBasicSetPreambleLength(PKT_PREAMBLE_LENGTH_18BYTES); - * - * ... - * - * @endcode - * - * @note Is recommended for the user to not use these API directly - * importing this module in his application. - * - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_PKT_COMMON_H -#define __SPIRIT_PKT_COMMON_H - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_PktCommon Pkt Common - * @brief Configuration and management of the common features of SPIRIT packets. - * @details See the file @ref SPIRIT_PktCommon.h for more details. - * @{ - */ - -/** - * @defgroup PktCommon_Exported_Types Pkt Common Exported Types - * @{ - */ - - -/** - * @brief Preamble length in bytes enumeration. - */ -typedef enum -{ - PKT_PREAMBLE_LENGTH_01BYTE = 0x00, /*!< Preamble length 1 byte*/ - PKT_PREAMBLE_LENGTH_02BYTES = 0x08, /*!< Preamble length 2 bytes */ - PKT_PREAMBLE_LENGTH_03BYTES = 0x10, /*!< Preamble length 3 bytes */ - PKT_PREAMBLE_LENGTH_04BYTES = 0x18, /*!< Preamble length 4 bytes */ - PKT_PREAMBLE_LENGTH_05BYTES = 0x20, /*!< Preamble length 5 bytes */ - PKT_PREAMBLE_LENGTH_06BYTES = 0x28, /*!< Preamble length 6 bytes */ - PKT_PREAMBLE_LENGTH_07BYTES = 0x30, /*!< Preamble length 7 bytes */ - PKT_PREAMBLE_LENGTH_08BYTES = 0x38, /*!< Preamble length 8 bytes */ - PKT_PREAMBLE_LENGTH_09BYTES = 0x40, /*!< Preamble length 9 bytes */ - PKT_PREAMBLE_LENGTH_10BYTES = 0x48, /*!< Preamble length 10 bytes */ - PKT_PREAMBLE_LENGTH_11BYTES = 0x50, /*!< Preamble length 11 bytes */ - PKT_PREAMBLE_LENGTH_12BYTES = 0x58, /*!< Preamble length 12 bytes */ - PKT_PREAMBLE_LENGTH_13BYTES = 0x60, /*!< Preamble length 13 bytes */ - PKT_PREAMBLE_LENGTH_14BYTES = 0x68, /*!< Preamble length 14 bytes */ - PKT_PREAMBLE_LENGTH_15BYTES = 0x70, /*!< Preamble length 15 bytes */ - PKT_PREAMBLE_LENGTH_16BYTES = 0x78, /*!< Preamble length 16 bytes */ - PKT_PREAMBLE_LENGTH_17BYTES = 0x80, /*!< Preamble length 17 bytes */ - PKT_PREAMBLE_LENGTH_18BYTES = 0x88, /*!< Preamble length 18 bytes */ - PKT_PREAMBLE_LENGTH_19BYTES = 0x90, /*!< Preamble length 19 bytes */ - PKT_PREAMBLE_LENGTH_20BYTES = 0x98, /*!< Preamble length 20 bytes */ - PKT_PREAMBLE_LENGTH_21BYTES = 0xA0, /*!< Preamble length 21 bytes */ - PKT_PREAMBLE_LENGTH_22BYTES = 0xA8, /*!< Preamble length 22 bytes */ - PKT_PREAMBLE_LENGTH_23BYTES = 0xB0, /*!< Preamble length 23 bytes */ - PKT_PREAMBLE_LENGTH_24BYTES = 0xB8, /*!< Preamble length 24 bytes */ - PKT_PREAMBLE_LENGTH_25BYTES = 0xC0, /*!< Preamble length 25 bytes */ - PKT_PREAMBLE_LENGTH_26BYTES = 0xC8, /*!< Preamble length 26 bytes */ - PKT_PREAMBLE_LENGTH_27BYTES = 0xD0, /*!< Preamble length 27 bytes */ - PKT_PREAMBLE_LENGTH_28BYTES = 0xD8, /*!< Preamble length 28 bytes */ - PKT_PREAMBLE_LENGTH_29BYTES = 0xE0, /*!< Preamble length 29 bytes */ - PKT_PREAMBLE_LENGTH_30BYTES = 0xE8, /*!< Preamble length 30 bytes */ - PKT_PREAMBLE_LENGTH_31BYTES = 0xF0, /*!< Preamble length 31 bytes */ - PKT_PREAMBLE_LENGTH_32BYTES = 0xF8 /*!< Preamble length 32 bytes */ - -}PktPreambleLength; - -#define IS_PKT_PREAMBLE_LENGTH(LENGTH) ((LENGTH == PKT_PREAMBLE_LENGTH_01BYTE) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_02BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_03BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_04BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_05BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_06BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_07BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_08BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_09BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_10BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_11BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_12BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_13BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_14BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_15BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_16BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_17BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_18BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_19BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_20BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_21BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_22BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_23BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_24BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_25BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_26BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_27BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_28BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_29BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_30BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_31BYTES) || \ - (LENGTH == PKT_PREAMBLE_LENGTH_32BYTES)) - - - -/** - * @brief Sync length in bytes enumeration. - */ -typedef enum -{ - PKT_SYNC_LENGTH_1BYTE = 0x00, /*!< Sync length 1 byte*/ - PKT_SYNC_LENGTH_2BYTES = 0x02, /*!< Sync length 2 bytes*/ - PKT_SYNC_LENGTH_3BYTES = 0x04, /*!< Sync length 3 bytes */ - PKT_SYNC_LENGTH_4BYTES = 0x06 , /*!< Sync length 4 bytes */ - -}PktSyncLength; - -#define IS_PKT_SYNC_LENGTH(LENGTH) ((LENGTH == PKT_SYNC_LENGTH_1BYTE) || \ - (LENGTH == PKT_SYNC_LENGTH_2BYTES)|| \ - (LENGTH == PKT_SYNC_LENGTH_3BYTES)|| \ - (LENGTH == PKT_SYNC_LENGTH_4BYTES)) - - - -/** - * @brief CRC length in bytes enumeration. - */ -typedef enum -{ - PKT_NO_CRC = 0x00, /*!< No CRC */ - PKT_CRC_MODE_8BITS = 0x20, /*!< CRC length 8 bits - poly: 0x07 */ - PKT_CRC_MODE_16BITS_1 = 0x40, /*!< CRC length 16 bits - poly: 0x8005 */ - PKT_CRC_MODE_16BITS_2 = 0x60, /*!< CRC length 16 bits - poly: 0x1021 */ - PKT_CRC_MODE_24BITS = 0x80, /*!< CRC length 24 bits - poly: 0x864CFB */ - -}PktCrcMode; - -#define IS_PKT_CRC_MODE(MODE) ((MODE == PKT_NO_CRC) || \ - (MODE == PKT_CRC_MODE_8BITS) || \ - (MODE == PKT_CRC_MODE_16BITS_1) || \ - (MODE == PKT_CRC_MODE_16BITS_2) || \ - (MODE == PKT_CRC_MODE_24BITS)) - - - -/** - * @brief Fixed or variable payload length enumeration. - */ -typedef enum -{ - PKT_LENGTH_FIX = 0x00, /*!< Fixed payload length */ - PKT_LENGTH_VAR = 0x01 /*!< Variable payload length */ - -}PktFixVarLength; - -#define IS_PKT_FIX_VAR_LENGTH(LENGTH) ((LENGTH == PKT_LENGTH_FIX) || \ - (LENGTH == PKT_LENGTH_VAR)) - - -/** - * @brief Control length in bytes enumeration for SPIRIT packets. - */ -typedef enum -{ - PKT_CONTROL_LENGTH_0BYTES = 0x00, /*!< Control length 0 byte*/ - PKT_CONTROL_LENGTH_1BYTE, /*!< Control length 1 byte*/ - PKT_CONTROL_LENGTH_2BYTES, /*!< Control length 2 bytes*/ - PKT_CONTROL_LENGTH_3BYTES, /*!< Control length 3 bytes*/ - PKT_CONTROL_LENGTH_4BYTES /*!< Control length 4 bytes*/ - -}PktControlLength; - -#define IS_PKT_CONTROL_LENGTH(LENGTH) ((LENGTH == PKT_CONTROL_LENGTH_0BYTES) || \ - (LENGTH == PKT_CONTROL_LENGTH_1BYTE) || \ - (LENGTH == PKT_CONTROL_LENGTH_2BYTES) || \ - (LENGTH == PKT_CONTROL_LENGTH_3BYTES) || \ - (LENGTH == PKT_CONTROL_LENGTH_4BYTES)) - -/** - * @brief Sync words enumeration for SPIRIT packets. - */ -typedef enum -{ - PKT_SYNC_WORD_1=0x01, /*!< Index of the 1st sync word*/ - PKT_SYNC_WORD_2, /*!< Index of the 2nd sync word*/ - PKT_SYNC_WORD_3, /*!< Index of the 3rd sync word*/ - PKT_SYNC_WORD_4 /*!< Index of the 4th sync word*/ - -}PktSyncX; - -#define IS_PKT_SYNCx(WORD) ((WORD == PKT_SYNC_WORD_1) || \ - (WORD == PKT_SYNC_WORD_2) || \ - (WORD == PKT_SYNC_WORD_3) || \ - (WORD == PKT_SYNC_WORD_4)) - - - -/** - * @brief Max retransmissions number enumeration for SPIRIT packets. - */ -typedef enum -{ - PKT_DISABLE_RETX = 0x00, /*!< No retrasmissions*/ - PKT_N_RETX_1 = 0x10, /*!< Max retrasmissions 1*/ - PKT_N_RETX_2 = 0x20, /*!< Max retrasmissions 2*/ - PKT_N_RETX_3 = 0x30, /*!< Max retrasmissions 3*/ - PKT_N_RETX_4 = 0x40, /*!< Max retrasmissions 4*/ - PKT_N_RETX_5 = 0x50, /*!< Max retrasmissions 5*/ - PKT_N_RETX_6 = 0x60, /*!< Max retrasmissions 6*/ - PKT_N_RETX_7 = 0x70, /*!< Max retrasmissions 7*/ - PKT_N_RETX_8 = 0x80, /*!< Max retrasmissions 8*/ - PKT_N_RETX_9 = 0x90, /*!< Max retrasmissions 9*/ - PKT_N_RETX_10 = 0xA0, /*!< Max retrasmissions 10*/ - PKT_N_RETX_11 = 0xB0, /*!< Max retrasmissions 11*/ - PKT_N_RETX_12 = 0xC0, /*!< Max retrasmissions 12*/ - PKT_N_RETX_13 = 0xD0, /*!< Max retrasmissions 13*/ - PKT_N_RETX_14 = 0xE0, /*!< Max retrasmissions 14*/ - PKT_N_RETX_15 = 0xF0 /*!< Max retrasmissions 15*/ - -}PktNMaxReTx; - -#define IS_PKT_NMAX_RETX(N_RETX) ((N_RETX == PKT_DISABLE_RETX) || \ - (N_RETX == PKT_N_RETX_1) || \ - (N_RETX == PKT_N_RETX_2) || \ - (N_RETX == PKT_N_RETX_3) || \ - (N_RETX == PKT_N_RETX_4) || \ - (N_RETX == PKT_N_RETX_5) || \ - (N_RETX == PKT_N_RETX_6) || \ - (N_RETX == PKT_N_RETX_7) || \ - (N_RETX == PKT_N_RETX_8) || \ - (N_RETX == PKT_N_RETX_9) || \ - (N_RETX == PKT_N_RETX_10) || \ - (N_RETX == PKT_N_RETX_11) || \ - (N_RETX == PKT_N_RETX_12) || \ - (N_RETX == PKT_N_RETX_13) || \ - (N_RETX == PKT_N_RETX_14) || \ - (N_RETX == PKT_N_RETX_15)) - - -/** - *@} - */ - - -/** - * @defgroup PktCommon_Exported_Constants Pkt Common Exported Constants - * @{ - */ - -#define IS_PKT_LENGTH_WIDTH_BITS(BITS) (BITS<=16) -#define IS_PKT_SEQ_NUMBER_RELOAD(SEQN) (SEQN<=3) - -/** - *@} - */ - - -/** - * @defgroup PktCommon_Exported_Macros Pkt Common Exported Macros - * @{ - */ - - -/** - * @brief Macro used to compute the lower part of the packet length, to write in the PCKTLEN0 register - * @param nLength Length of the packet payload. - * This parameter is an uint16_t. - * @retval None. - */ -#define BUILD_PCKTLEN0(nLength) (nLength & 0xFF) - - -/** - * @brief Macro used to compute the upper part of the packet length, to write the PCKTLEN1 register - * @param nLength Length of the packet payload. - * This parameter is an uint16_t. - * @retval None. - */ -#define BUILD_PCKTLEN1(nLength) (nLength >> 8) - -/** - *@} - */ - - -/** - * @defgroup PktCommon_Exported_Functions Pkt Common Exported Functions - * @{ - */ - -void SpiritPktCommonSetControlLength(PktControlLength xControlLength); -uint8_t SpiritPktCommonGetControlLength(void); -void SpiritPktCommonSetPreambleLength(PktPreambleLength xPreambleLength); -uint8_t SpiritPktCommonGetPreambleLength(void); -void SpiritPktCommonSetSyncLength(PktSyncLength xSyncLength); -uint8_t SpiritPktCommonGetSyncLength(void); -void SpiritPktCommonSetFixVarLength(PktFixVarLength xFixVarLength); -void SpiritPktCommonFilterOnCrc(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritPktCommonGetFilterOnCrc(void); -void SpiritPktCommonSetCrcMode(PktCrcMode xCrcLength); -PktCrcMode SpiritPktCommonGetCrcMode(void); -void SpiritPktCommonWhitening(SpiritFunctionalState xNewState); -void SpiritPktCommonFec(SpiritFunctionalState xNewState); -void SpiritPktCommonSetSyncxWord(PktSyncX xSyncX, uint8_t cSyncWord); -uint8_t SpiritPktCommonGetSyncxWord(PktSyncX xSyncX); -void SpiritPktCommonSetSyncWords(uint32_t lSyncWords, PktSyncLength xSyncLength); -uint32_t SpiritPktCommonGetSyncWords(PktSyncLength xSyncLength); -uint8_t SpiritPktCommonGetVarLengthWidth(void); -void SpiritPktCommonSetDestinationAddress(uint8_t cAddress); -uint8_t SpiritPktCommonGetTransmittedDestAddress(void); -void SpiritPktCommonSetMyAddress(uint8_t cAddress); -uint8_t SpiritPktCommonGetMyAddress(void); -void SpiritPktCommonSetBroadcastAddress(uint8_t cAddress); -uint8_t SpiritPktCommonGetBroadcastAddress(void); -SpiritFunctionalState SpiritPktCommonGetTxAckRequest(void); -void SpiritPktCommonSetMulticastAddress(uint8_t cAddress); -uint8_t SpiritPktCommonGetMulticastAddress(void); -void SpiritPktCommonSetCtrlMask(uint32_t lMask); -uint32_t SpiritPktCommonGetCtrlMask(void); -void SpiritPktCommonSetCtrlReference(uint32_t lReference); -uint32_t SpiritPktCommonGetCtrlReference(void); -void SpiritPktCommonSetTransmittedCtrlField(uint32_t lField); -uint32_t SpiritPktCommonGetTransmittedCtrlField(void); -void SpiritPktCommonFilterOnMyAddress(SpiritFunctionalState xNewState); -void SpiritPktCommonFilterOnMulticastAddress(SpiritFunctionalState xNewState); -void SpiritPktCommonFilterOnBroadcastAddress(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritPktCommonGetFilterOnMyAddress(void); -SpiritFunctionalState SpiritPktCommonGetFilterOnMulticastAddress(void); -SpiritFunctionalState SpiritPktCommonGetFilterOnBroadcastAddress(void); -uint8_t SpiritPktCommonGetReceivedDestAddress(void); -uint32_t SpiritPktCommonGetReceivedCtrlField(void); -void SpiritPktCommonGetReceivedCrcField(uint8_t* cCrcFieldVect); -void SpiritPktCommonAutoAck(SpiritFunctionalState xAutoAck,SpiritFunctionalState xPiggybacking); -void SpiritPktCommonRequireAck(SpiritFunctionalState xRequireAck); -void SpiritPktCommonSetTransmittedSeqNumberReload(uint8_t cSeqNumberReload); -void SpiritPktCommonSetNMaxReTx(PktNMaxReTx xNMaxReTx); -uint8_t SpiritPktCommonGetNMaxReTx(void); -uint8_t SpiritPktCommonGetReceivedDestAddress(void); -uint8_t SpiritPktCommonGetReceivedSourceAddress(void); -uint8_t SpiritPktCommonGetReceivedSeqNumber(void); -uint8_t SpiritPktCommonGetReceivedNackRx(void); -uint8_t SpiritPktCommonGetTransmittedSeqNumber(void); -uint8_t SpiritPktCommonGetNReTx(void); -void SpiritPktCommonFilterOnControlField(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritPktCommonGetFilterOnControlField(void); - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktMbus.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktMbus.h deleted file mode 100644 index 2d524bf83..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktMbus.h +++ /dev/null @@ -1,206 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktMbus.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT MBUS packets. - * - * @details - * - * This module can be used to manage the configuration of Spirit MBUS - * packets. - * The user can obtain a packet configuration filling the structure - * @ref PktMbusInit, defining in it some general parameters - * for the Spirit MBUS packet format. - * Since the MBUS protocol is a standard, the configuration of a MBUS - * packet is very simple to do. - * - * Example: - * @code - * - * PktMbusInit mbusInit={ - * MBUS_SUBMODE_S1_S2_LONG_HEADER, // MBUS submode selection - * 36, // added "01" chips on preamble - * 16 // postamble length in "01" chips - * }; - * - * ... - * - * SpiritPktMbusInit(&mbusInit); - * - * ... - * - * @endcode - * - * The module provides some other functions that can be used to modify - * or read only some configuration parameters. - * - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_PACKET_MBUS_H -#define __SPIRIT_PACKET_MBUS_H - - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" -#include "SPIRIT_PktCommon.h" - -#ifdef __cplusplus - extern "C" { -#endif - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_PktMbus Pkt MBUS - * @brief Configuration and management of SPIRIT MBUS packets. - * @details See the file @ref SPIRIT_PktMbus.h for more details. - * @{ - */ - -/** - * @defgroup PktMbus_Exported_Types Pkt MBUS Exported Types - * @{ - */ - - - -/** - * @brief MBUS submode enumeration. - */ - -typedef enum -{ - MBUS_SUBMODE_S1_S2_LONG_HEADER = MBUS_CTRL_MBUS_SUBMODE_S1_S2L, /*!< MBUS submode S1, S2 (long header) - Header length = mbus_prmbl_ctrl + 279 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits) */ - MBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER = MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER, /*!< MBUS submode S1-m, S2, T2 (other to meter) - Header length = mbus_prmbl_ctrl + 15 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits)*/ - MBUS_SUBMODE_T1_T2_METER_TO_OTHER = MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER, /*!< MBUS submode T1, T2 (meter to other) - Header length = mbus_prmbl_ctrl + 19 (in "01" bit pairs) , Sync word = 0x3D (length 10 bits)*/ - MBUS_SUBMODE_R2_SHORT_HEADER = MBUS_CTRL_MBUS_SUBMODE_R2, /*!< MBUS submode R2, short header - Header length = mbus_prmbl_ctrl + 39 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits)*/ - -}MbusSubmode; - -#define IS_MBUS_SUBMODE(MODE) (((MODE) == MBUS_SUBMODE_S1_S2_LONG_HEADER) || \ - ((MODE) == MBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER) || \ - ((MODE) == MBUS_SUBMODE_T1_T2_METER_TO_OTHER) || \ - ((MODE) == MBUS_SUBMODE_R2_SHORT_HEADER)) - - -/** - * @brief SPIRIT MBUS Packet Init structure definition - */ -typedef struct -{ - MbusSubmode xMbusSubmode; /*!< Specifies the SUBMODE to be configured. - This parameter can be a value of @ref MbusSubmode */ - - uint8_t cPreambleLength; /*!< Specifies the PREAMBLE length. - This parameter can be any value between 0 and 255 chip sequence '01' */ - - uint8_t cPostambleLength; /*!< Specifies the POSTAMBLE length. - This parameter can be any value between 0 and 255 chip sequence '01' */ - -}PktMbusInit; - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Exported_Constants Pkt MBUS Exported Constants - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Exported_Macros Pkt MBUS Exported Macros - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Exported_Functions Pkt MBUS Exported Functions - * @{ - */ -void SpiritPktMbusInit(PktMbusInit* pxPktMbusInit); -void SpiritPktMbusGetInfo(PktMbusInit* pxPktMbusInit); -void SpiritPktMbusSetFormat(void); -void SpiritPktMbusSetPreamble(uint8_t cPreamble); -uint8_t SpiritPktMbusGetPreamble(void); -void SpiritPktMbusSetPostamble(uint8_t cPostamble); -uint8_t SpiritPktMbusGetPostamble(void); -void SpiritPktMbusSetSubmode(MbusSubmode xMbusSubmode); -MbusSubmode SpiritPktMbusGetSubmode(void); -void SpiritPktMbusSetPayloadLength(uint16_t nPayloadLength); -uint16_t SpiritPktMbusGetPayloadLength(void); - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktStack.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktStack.h deleted file mode 100644 index 8255ac5dc..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_PktStack.h +++ /dev/null @@ -1,849 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktStack.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT STack packets. - * - * @details - * - * This module can be used to manage the configuration of Spirit STack - * packets, and it is quite similar to the Basic packets one since the - * STack packets can be considered an extension of Basic. - * The user can obtain a packet configuration filling the structure - * @ref PktStackInit, defining in it some general parameters - * for the Spirit STack packet format. - * Another structure the user can fill is @ref PktStackAddressesInit - * to define the addresses which will be used during the communication. - * The structure @ref PktStackLlpInit is provided in order to configure - * the link layer protocol features like autoack, autoretransmission - * or piggybacking. - * Moreover, functions to set the payload length and the destination address - * are provided. - * - * Example: - * @code - * - * PktStackInit stackInit={ - * PKT_PREAMBLE_LENGTH_08BYTES, // preamble length in bytes - * PKT_SYNC_LENGTH_4BYTES, // sync word length in bytes - * 0x1A2635A8, // sync word - * PKT_LENGTH_VAR, // variable or fixed payload length - * 7, // length field width in bits (used only for variable length) - * PKT_NO_CRC, // CRC mode - * PKT_CONTROL_LENGTH_0BYTES, // control field length - * S_DISABLE, // FEC - * S_ENABLE // whitening - * }; - * - * PktStackAddressesInit addressInit={ - * S_ENABLE, // enable/disable filtering on my address - * 0x34, // my address (address of the current node) - * S_DISABLE, // enable/disable filtering on multicast address - * 0xEE, // multicast address - * S_DISABLE, // enable/disable filtering on broadcast address - * 0xFF // broadcast address - * }; - * - * PktStackLlpInit stackLLPInit ={ - * S_DISABLE, // enable/disable the autoack feature - * S_DISABLE, // enable/disable the piggybacking feature - * PKT_DISABLE_RETX // set the max number of retransmissions or disable them - * }; - * ... - * - * SpiritPktStackInit(&stackInit); - * SpiritPktStackAddressesInit(&addressInit); - * SpiritPktStackLlpInit(&stackLLPInit); - * - * ... - * - * SpiritPktStackSetPayloadLength(20); - * SpiritPktStackSetDestinationAddress(0x44); - * - * ... - * - * @endcode - * - * The module provides some other functions that can be used to modify - * or read only some configuration parameters. - * - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_PKT_STACK_H -#define __SPIRIT_PKT_STACK_H - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" -#include "SPIRIT_PktCommon.h" - -#ifdef __cplusplus - extern "C" { -#endif - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_PktStack Pkt STack - * @brief Configuration and management of SPIRIT STack packets. - * @details See the file @ref SPIRIT_PktStack.h for more details. - * @{ - */ - -/** - * @defgroup PktStack_Exported_Types Pkt STack Exported Types - * @{ - */ - -/** - * @brief Preamble length in bytes enumeration. - */ -typedef PktPreambleLength StackPreambleLength; - -#define IS_STACK_PREAMBLE_LENGTH IS_PKT_PREAMBLE_LENGTH - -/** - * @brief Sync length in bytes enumeration. - */ -typedef PktSyncLength StackSyncLength; - -#define IS_STACK_SYNC_LENGTH IS_PKT_SYNC_LENGTH - - - -/** - * @brief CRC length in bytes enumeration. - */ -typedef PktCrcMode StackCrcMode; - -#define IS_STACK_CRC_MODE IS_PKT_CRC_MODE - - -/** - * @brief Fixed or variable payload length enumeration. - */ -typedef PktFixVarLength StackFixVarLength; - -#define IS_STACK_FIX_VAR_LENGTH IS_PKT_FIX_VAR_LENGTH - -/** - * @brief Control length in bytes enumeration for SPIRIT. - */ -typedef PktControlLength StackControlLength; - -#define IS_STACK_CONTROL_LENGTH IS_PKT_CONTROL_LENGTH - -/** - * @brief Sync words enumeration for SPIRIT. - */ -typedef PktSyncX StackSyncX; - -#define IS_STACK_SYNCx IS_PKT_SYNCx - -/** - * @brief Max retransmission number enumeration for SPIRIT. - */ -typedef PktNMaxReTx StackNMaxReTx; - -#define IS_STACK_NMAX_RETX IS_PKT_NMAX_RETX - - -/** - * @brief SPIRIT STack Packet Init structure definition. This structure allows users to set the main options - * for the STack packet. - */ -typedef struct -{ - - StackPreambleLength xPreambleLength; /*!< Specifies the preamble length of packet. - This parameter can be any value of @ref StackPreambleLength */ - StackSyncLength xSyncLength; /*!< Specifies the sync word length of packet. - This parameter can be any value of @ref StackSyncLength */ - uint32_t lSyncWords; /*!< Specifies the sync words. - This parameter is a uint32_t word with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4| */ - StackFixVarLength xFixVarLength; /*!< Specifies if a fixed length of packet has to be used. - This parameter can be any value of @ref StackFixVarLength */ - uint8_t cPktLengthWidth; /*!< Specifies the size of the length of packet in bits. This field is useful only if - the field xFixVarLength is set to STACK_LENGTH_VAR. For STack packets the length width - is log2( max payload length + control length (0 to 4) + address length (always 2)). - This parameter is an uint8_t */ - StackCrcMode xCrcMode; /*!< Specifies the CRC word length of packet. - This parameter can be any value of @ref StackCrcMode */ - StackControlLength xControlLength; /*!< Specifies the length of a control field to be sent. - This parameter can be any value of @ref StackControlLength */ - SpiritFunctionalState xFec; /*!< Specifies if FEC has to be enabled. - This parameter can be any value of @ref SpiritFunctionalState */ - SpiritFunctionalState xDataWhitening; /*!< Specifies if data whitening has to be enabled. - This parameter can be any value of @ref SpiritFunctionalState */ - -}PktStackInit; - - -/** - * @brief SPIRIT STack packet address structure definition. This structure allows users to specify - * the node/multicast/broadcast addresses and the correspondent filtering options. - */ -typedef struct -{ - - SpiritFunctionalState xFilterOnMyAddress; /*!< If set RX packet is accepted if its destination address matches with cMyAddress. - This parameter can be S_ENABLE or S_DISABLE */ - uint8_t cMyAddress; /*!< Specifies the TX packet source address (address of this node). - This parameter is an uint8_t */ - SpiritFunctionalState xFilterOnMulticastAddress; /*!< If set RX packet is accepted if its destination address matches with cMulticastAddress. - This parameter can be S_ENABLE or S_DISABLE */ - uint8_t cMulticastAddress; /*!< Specifies the Multicast group address for this node. - This parameter is an uint8_t */ - SpiritFunctionalState xFilterOnBroadcastAddress; /*!< If set RX packet is accepted if its destination address matches with cBroadcastAddress. - This parameter can be S_ENABLE or S_DISABLE */ - uint8_t cBroadcastAddress; /*!< Specifies the Broadcast address for this node. - This parameter is an uint8_t */ -}PktStackAddressesInit; - - -/** - * @brief SPIRIT STack packet LLP structure definition. This structure allows users to configure - * all the LLP options for STack packets. - */ -typedef struct -{ - - SpiritFunctionalState xAutoAck; /*!< Specifies if the auto ACK feature is used or not. - This parameter can be a value of @ref SpiritFunctionalState */ - SpiritFunctionalState xPiggybacking; /*!< Specifies if the piggybacking feature is used or not. - This parameter can be a value of @ref SpiritFunctionalState */ - StackNMaxReTx xNMaxRetx; /*!< Specifies the number of MAX-Retransmissions. - This parameter can be a value of @ref StackNMaxReTx */ -}PktStackLlpInit; - - - -/** - *@} - */ - - -/** - * @defgroup PktStack_Exported_Constants Pkt STack Exported Constants - * @{ - */ - -#define IS_STACK_LENGTH_WIDTH_BITS IS_PKT_LENGTH_WIDTH_BITS - -/** - *@} - */ - - -/** - * @defgroup PktStack_Exported_Macros Pkt STack Exported Macros - * @{ - */ - -/** - * @brief Macro used to compute the lower part of the packet length - * for Spirit STack packets, to write in the PCKTLEN0 register. - * @param nLength length of the packet payload. - * This parameter is an uint16_t. - * @retval None. - */ -#define STACK_BUILD_PCKTLEN0(nLength) BUILD_PCKTLEN0(nLength) - - -/** - * @brief Macro used to compute the upper part of the packet length - * for Spirit STack packets, to write the PCKTLEN1 register. - * @param nLength length of the packet payload. - * This parameter is an uint16_t. - * @retval None. - */ -#define STACK_BUILD_PCKTLEN1(nLength) BUILD_PCKTLEN1(nLength) - - -/** - * @brief Sets the CONTROL length for SPIRIT STack packets. - * @param xControlLength length of CONTROL field in bytes. - * This parameter can be any value of @ref StackControlLength. - * @retval None. - */ -#define SpiritPktStackSetControlLength(xControlLength) SpiritPktCommonSetControlLength(xControlLength) - - -/** - * @brief Returns the CONTROL length for SPIRIT STack packets. - * @param None. - * @retval Control length. - */ -#define SpiritPktStackGetControlLength() SpiritPktCommonGetControlLength() - - -/** - * @brief Sets the PREAMBLE Length mode for SPIRIT STack packets. - * @param xPreambleLength length of PREAMBLE field in bytes. - * This parameter can be any value of @ref StackPreambleLength. - * @retval None. - */ -#define SpiritPktStackSetPreambleLength(xPreambleLength) SpiritPktCommonSetPreambleLength((PktPreambleLength)xPreambleLength) - - -/** - * @brief Returns the PREAMBLE Length mode for SPIRIT STack packets. - * @param None. - * @retval uint8_t Preamble length in bytes. - */ -#define SpiritPktStackGetPreambleLength() SpiritPktCommonGetPreambleLength() - - -/** - * @brief Sets the SYNC Length for SPIRIT STack packets. - * @param xSyncLength length of SYNC field in bytes. - * This parameter can be any value of @ref StackSyncLength. - * @retval None. - */ -#define SpiritPktStackSetSyncLength(xSyncLength) SpiritPktCommonSetSyncLength((PktSyncLength)xSyncLength) - - -/** - * @brief Returns the SYNC Length for SPIRIT STack packets. - * @param None. - * @retval uint8_t Sync length in bytes. - */ -#define SpiritPktStackGetSyncLength() SpiritPktCommonGetSyncLength() - - -/** - * @brief Sets fixed or variable payload length mode for SPIRIT STack packets. - * @param xFixVarLength variable or fixed length. - * PKT_FIXED_LENGTH_VAR -> variable (the length is extracted from the received packet). - * PKT_FIXED_LENGTH_FIX -> fix (the length is set by PCKTLEN0 and PCKTLEN1). - * @retval None. - */ -#define SpiritPktStackSetFixVarLength(xFixVarLength) SpiritPktCommonSetFixVarLength((PktFixVarLength)xFixVarLength) - - -/** - * @brief Enables or Disables the CRC filtering. - * @param xNewState new state for CRC_CHECK. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackFilterOnCrc(xNewState) SpiritPktCommonFilterOnCrc(xNewState) - - -/** - * @brief Returns the CRC filtering bit. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktStackGetFilterOnCrc() SpiritPktCommonGetFilterOnCrc() - - -/** - * @brief Sets the CRC mode for SPIRIT STack packets. - * @param xCrcMode CRC mode. - * This parameter can be any value of @ref StackCrcMode. - * @retval None. - */ -#define SpiritPktStackSetCrcMode(xCrcMode) SpiritPktCommonSetCrcMode((PktCrcMode)xCrcMode) - - -/** - * @brief Returns the CRC mode for SPIRIT packets. - * @param None. - * @retval StackCrcMode Crc mode. - */ -#define SpiritPktStackGetCrcMode() (StackCrcMode)SpiritPktCommonGetCrcMode() - - -/** - * @brief Enables or Disables WHITENING for SPIRIT STack packets. - * @param xNewState new state for WHITENING mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackWhitening(xNewState) SpiritPktCommonWhitening(xNewState) - - -/** - * @brief Enables or Disables FEC for SPIRIT STack packets. - * @param xNewState new state for FEC mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackFec(xNewState) SpiritPktCommonFec(xNewState) - - -/** - * @brief Sets a specific SYNC word for SPIRIT STack packets. - * @param xSyncX SYNC word number to be set. - * This parameter can be any value of @ref StackSyncX. - * @param cSyncWord SYNC word. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktStackSetSyncxWord(xSyncX, cSyncWord) SpiritPktCommonSetSyncxWord((PktSyncX)xSyncX,cSyncWord) - - -/** - * @brief Returns a specific SYNC word for SPIRIT STack packets. - * @param xSyncX SYNC word number to be get. - * This parameter can be any value of @ref StackSyncX. - * @retval uint8_t Sync word x. - */ -#define SpiritPktStackGetSyncxWord(xSyncX) SpiritPktCommonGetSyncxWord(xSyncX) - - -/** - * @brief Sets multiple SYNC words for SPIRIT STack packets. - * @param lSyncWords SYNC words to be set with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4|. - * This parameter is a uint32_t. - * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb - * until the number of bytes in xSyncLength has been stored. - * This parameter is a @ref StackSyncLength. - * @retval None. - */ -#define SpiritPktStackSetSyncWords(lSyncWords, xSyncLength) SpiritPktCommonSetSyncWords(lSyncWords,(PktSyncLength)xSyncLength) - - -/** - * @brief Returns multiple SYNC words for SPIRIT packets. - * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb - * until the number of bytes in xSyncLength has been stored. - * This parameter is a pointer to @ref StackSyncLength. - * @retval uint32_t Sync words. The format of the read 32 bit word is 0x|SYNC1|SYNC2|SYNC3|SYNC4|. - */ -#define SpiritPktStackGetSyncWords(xSyncLength) SpiritPktCommonGetSyncWords((PktSyncLength)xSyncLength) - - -/** - * @brief Returns the SPIRIT variable length width (in number of bits). - * @param None. - * @retval uint8_t Variable length width in bits. - */ -#define SpiritPktStackGetVarLengthWidth() SpiritPktCommonGetVarLengthWidth() - - -/** - * @brief Sets the destination address for the Tx packet. - * @param cAddress destination address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktStackSetDestinationAddress(cAddress) SpiritPktCommonSetDestinationAddress(cAddress) - - -/** - * @brief Sets the Rx packet reference source address. The source address extracted from the received packet is masked - * with the source reference mask and then compared to the masked reference value. - * @param cAddress Reference source address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktStackSetSourceReferenceAddress(cAddress) SpiritPktCommonSetDestinationAddress(cAddress) - - -/** - * @brief Returns the Rx packet reference source address. The source address extracted from the received packet is masked - * with the source reference mask and then compared to the masked reference value. - * @param cAddress Reference source address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktStackGetSourceReferenceAddress() SpiritPktCommonGetTransmittedDestAddress() - - -/** - * @brief Returns the settled destination address. - * @param None. - * @retval uint8_t Transmitted destination address. - */ -#define SpiritPktStackGetTransmittedDestAddress() SpiritPktCommonGetTransmittedDestAddress() - - -/** - * @brief Sets the node address. When the filtering on my address is on, if the destination address extracted from the received packet is equal to the content of the - * my address, then the packet is accepted (this is the address of the node). - * @param cAddress Address of the present node. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktStackSetMyAddress(cAddress) SpiritPktCommonSetMyAddress(cAddress) - - -/** - * @brief Returns the address of the present node. - * @param None. - * @retval uint8_t My address (address of this node). - */ -#define SpiritPktStackGetMyAddress() SpiritPktCommonGetMyAddress() - - -/** - * @brief Sets the broadcast address. When the broadcast filtering is on, if the destination address extracted from the received packet is equal to the content of the - * BROADCAST_ADDR register, then the packet is accepted. - * @param cAddress Broadcast address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktStackSetBroadcastAddress(cAddress) SpiritPktCommonSetBroadcastAddress(cAddress) - - -/** - * @brief Returns the broadcast address. - * @param None. - * @retval uint8_t Broadcast address. - */ -#define SpiritPktStackGetBroadcastAddress() SpiritPktCommonGetBroadcastAddress() - - -/** - * @brief Sets the multicast address. When the multicast filtering is on, if the destination address extracted from the received packet is equal to the content of the - * MULTICAST_ADDR register, then the packet is accepted. - * @param cAddress Multicast address. - * This parameter is an uint8_t. - * @retval None. - */ -#define SpiritPktStackSetMulticastAddress(cAddress) SpiritPktCommonSetMulticastAddress(cAddress) - - -/** - * @brief Returns the multicast address. - * @param None. - * @retval uint8_t Multicast address. - */ -#define SpiritPktStackGetMulticastAddress() SpiritPktCommonGetMulticastAddress() - - -/** - * @brief Sets the control mask. The 1 bits of the CONTROL_MASK indicate the - * bits to be used in filtering. (All 0s no filtering) - * @param lMask Control mask. - * This parameter is an uint32_t. - * @retval None. - */ -#define SpiritPktStackSetCtrlMask(lMask) SpiritPktCommonSetCtrlMask(lMask) - - -/** - * @brief Returns the control mask. The 1 bits of the CONTROL_MASK indicate the - * bits to be used in filtering. (All 0s no filtering) - * @param None. - * @retval uint32_t Control mask. - */ -#define SpiritPktStackGetCtrlMask() SpiritPktCommonGetCtrlMask() - - -/** - * @brief Sets the control field reference. If the bits enabled by the - * CONTROL_MASK match the ones of the control fields extracted from the received packet - * then the packet is accepted. - * @param lReference Control reference. - * This parameter is an uint32_t. - * @retval None. - */ -#define SpiritPktStackSetCtrlReference(lReference) SpiritPktCommonSetCtrlReference(lReference) - - -/** - * @brief Returns the control field reference. - * @param None. - * @retval uint32_t Control reference. - */ -#define SpiritPktStackGetCtrlReference() SpiritPktCommonGetCtrlReference() - - -/** - * @brief Sets the TX control field. - * @param lField TX CONTROL FIELD. - * This parameter is an uint32_t. - * @retval None. - */ -#define SpiritPktStackSetTransmittedCtrlField(lField) SpiritPktCommonSetTransmittedCtrlField(lField) - - -/** - * @brief Returns the TX control field. - * @param None. - * @retval uint32_t Control field of the transmitted packet. - */ -#define SpiritPktStackGetTransmittedCtrlField() SpiritPktCommonGetTransmittedCtrlField() - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with TX_SOURCE_ADDRESS. - * @param xNewState new state for DEST_VS_SOURCE_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackFilterOnMyAddress(xNewState) SpiritPktCommonFilterOnMyAddress(xNewState) - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with MULTICAST_ADDRESS. - * @param xNewState new state for DEST_VS_MULTICAST_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackFilterOnMulticastAddress(xNewState) SpiritPktCommonFilterOnMulticastAddress(xNewState) - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with BROADCAST_ADDRESS. - * @param xNewState new state for DEST_VS_BROADCAST_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackFilterOnBroadcastAddress(xNewState) SpiritPktCommonFilterOnBroadcastAddress(xNewState) - - -/** - * @brief Returns the enable bit of the my address filtering. - * @param None. - * @retval SpiritFunctionalStateThis parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktStackGetFilterOnMyAddress() SpiritPktCommonGetFilterOnMyAddress(); - - -/** - * @brief Returns the enable bit of the multicast address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktStackGetFilterOnMulticastAddress() SpiritPktCommonGetFilterOnMulticastAddress(); - - -/** - * @brief Returns the enable bit of the broadcast address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktStackGetFilterOnBroadcastAddress() SpiritPktCommonGetFilterOnBroadcastAddress(); - - -/** - * @brief Returns the control field of the received packet. - * @param None. - * @retval uint32_t Received control field. - */ -#define SpiritPktStackGetReceivedCtrlField() SpiritPktCommonGetReceivedCtrlField() - - -/** - * @brief Returns the CRC field of the received packet. - * @param cCrcFieldVect array in which the CRC field has to be stored. - * This parameter is an uint8_t array of 3 elements. - * @retval None. - */ -#define SpiritPktStackGetReceivedCrcField(cCrcFieldVect) SpiritPktCommonGetReceivedCrcField(cCrcFieldVect) - -/** - * @brief Sets the AUTO ACKNOLEDGEMENT mechanism on the receiver. When the feature is enabled and - * a data packet has been correctly received, then an acknowledgement packet is sent back to the originator of the received - * packet. If the PIGGYBACKING bit is also set, payload data will be read from the FIFO; otherwise an empty packet is sent - * only containing the source and destination addresses and the sequence number of the packet being acknowledged. - * @param xAutoAck new state for autoack. - * This parameter can be: S_ENABLE or S_DISABLE. - * @param xPiggybacking new state for autoack. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackAutoAck(xAutoAck, xPiggybacking) SpiritPktCommonAutoAck(xAutoAck, xPiggybacking) - - -/** - * @brief Sets the AUTO ACKNOLEDGEMENT mechanism on the transmitter. On the transmitter side, the NACK_TX field can be used to require or not an acknowledgment for each individual packet: if - * NACK_TX is set to "1" then acknowledgment will not be required; if NACK_TX is set to "0" then acknowledgment will be - * required. - * @param xNewState new state for TX_AUTOACK. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackRequireAck(xNewState) SpiritPktCommonRequireAck(xNewState) - - -/** - * @brief Sets the TX sequence number to be used to start counting. - * @param cSeqNumberReload new value for Tx seq number reload. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -#define SpiritPktStackSetTransmittedSeqNumberReload(cSeqNumberReload) SpiritPktCommonSetTransmittedSeqNumberReload(cSeqNumberReload) - - -/** - * @brief Sets the max number of automatic retransmission. - * @param xNMaxReTx max number of retransmission. - * This parameter can be any value of @ref PktNMaxReTx. - * @retval None. - */ -#define SpiritPktStackSetNMaxReTx(xNMaxReTx) SpiritPktCommonSetNMaxReTx((PktNMaxReTx)xNMaxReTx) - - -/** - * @brief Returns the max number of automatic retransmission. - * @param None. - * @retval uint8_t Max number of retransmissions. - */ -#define SpiritPktStackGetNMaxReTx() SpiritPktCommonGetNMaxReTx() - - -/** - * @brief Returns the TX ACK request. - * @param None. - * @retval SpiritFunctionalState. - */ -#define SpiritPktStackGetGetTxAckRequest() SpiritPktCommonGetTxAckRequest() - -/** - * @brief Returns the destination address of the received packet. - * @param None. - * @retval uint8_t Destination address of the received packet. - */ -#define SpiritPktStackGetReceivedDestAddress() SpiritPktCommonGetReceivedDestAddress() - - -/** - * @brief Returns the source address of the received packet. - * @param None. - * @retval uint8_t Source address of the received packet. - */ -#define SpiritPktStackGetReceivedSourceAddress() SpiritPktCommonGetReceivedSourceAddress() - - -/** - * @brief Returns the sequence number of the received packet. - * @param None. - * @retval uint8_t Received Sequence number. - */ -#define SpiritPktStackGetReceivedSeqNumber() SpiritPktCommonGetReceivedSeqNumber() - - -/** - * @brief Returns the Nack bit of the received packet - * @param None. - * @retval uint8_t Value of the NAck bit. - */ -#define SpiritPktStackGetReceivedNackRx() SpiritPktCommonGetReceivedNackRx() - - -/** - * @brief Returns the sequence number of the transmitted packet. - * @param None. - * @retval uint8_t Sequence number of the transmitted packet. - */ -#define SpiritPktStackGetTransmittedSeqNumber() SpiritPktCommonGetTransmittedSeqNumber() - - -/** - * @brief Returns the number of retransmission done on the transmitted packet. - * @param None. - * @retval uint8_t Number of retransmissions done until now. - */ -#define SpiritPktStackGetNReTx() SpiritPktCommonGetNReTx() - - -/** - * @brief If enabled RX packet is accepted only if the masked control field matches the - * masked control field reference (CONTROL_MASK & CONTROL_FIELD_REF == CONTROL_MASK & RX_CONTROL_FIELD). - * @param xNewState new state for Control filtering enable bit. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - * @note This filtering control is enabled by default but the control mask is by default set to 0. - * As a matter of fact the user has to enable the control filtering bit after the packet initialization - * because the PktInit routine disables it. - */ -#define SpiritPktStackFilterOnControlField(xNewState) SpiritPktCommonFilterOnControlField(xNewState) - - -/** - * @brief Returns the enable bit of the control field filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -#define SpiritPktStackGetFilterOnControlField() SpiritPktCommonGetFilterOnControlField(); - - -/** - *@} - */ - - -/** - * @defgroup PktStack_Exported_Functions Pkt STack Exported Functions - * @{ - */ - -void SpiritPktStackInit(PktStackInit* pxPktStackInit); -void SpiritPktStackGetInfo(PktStackInit* pxPktStackInit); -void SpiritPktStackAddressesInit(PktStackAddressesInit* pxPktStackAddresses); -void SpiritPktStackGetAddressesInfo(PktStackAddressesInit* pxPktStackAddresses); -void SpiritPktStackLlpInit(PktStackLlpInit* pxPktStackLlpInit); -void SpiritPktStackLlpGetInfo(PktStackLlpInit* pxPktStackLlpInit); -void SpiritPktStackSetFormat(void); -void SpiritPktStackSetPayloadLength(uint16_t nPayloadLength); -uint16_t SpiritPktStackGetPayloadLength(void); -void SpiritPktStackSetVarLengthWidth(uint16_t nMaxPayloadLength, StackControlLength xControlLength); -void SpiritPktStackSetRxSourceMask(uint8_t cMask); -uint8_t SpiritPktStackGetRxSourceMask(void); -uint16_t SpiritPktStackGetReceivedPktLength(void); -void SpiritPktStackFilterOnSourceAddress(SpiritFunctionalState xNewState); -void SpiritPktStackSetAddressLength(void); - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Qi.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Qi.h deleted file mode 100644 index d7055d01a..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Qi.h +++ /dev/null @@ -1,300 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Qi.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT QI. - * @details - * - * This module can be used to configure and read some quality indicators - * used by Spirit. - * API to set thresholds and to read values in raw mode or in dBm are - * provided. - * - * Example: - * @code - * - * float rssiValuedBm; - * uint8_t pqiValue, sqiValue; - * - * SpiritQiPqiCheck(S_ENABLE); - * SpiritQiSqiCheck(S_ENABLE); - * - * ... - * - * rssiValueDbm = SpiritQiGetRssidBm(); - * pqiValue = SpiritQiGetPqi(); - * sqiValue = SpiritQiGetSqi(); - * - * ... - * - * @endcode - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_QI_H -#define __SPIRIT_QI_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Qi QI - * @brief Configuration and management of SPIRIT QI. - * @details See the file @ref SPIRIT_Qi.h for more details. - * @{ - */ - -/** - * @defgroup Qi_Exported_Types QI Exported Types - * @{ - */ - - -/** - * @brief PQI threshold value enumeration. - */ -typedef enum -{ - PQI_TH_0=0x00, - PQI_TH_1=0x04, - PQI_TH_2=0x08, - PQI_TH_3=0x0C, - PQI_TH_4=0x10, - PQI_TH_5=0x14, - PQI_TH_6=0x18, - PQI_TH_7=0x1C, - PQI_TH_8=0x20, - PQI_TH_9=0x24, - PQI_TH_10=0x28, - PQI_TH_11=0x2C, - PQI_TH_12=0x30, - PQI_TH_13=0x34, - PQI_TH_14=0x38, - PQI_TH_15=0x3C - -} PqiThreshold; - -#define IS_PQI_THR(VALUE) (VALUE==PQI_TH_0 ||\ - VALUE==PQI_TH_1 ||\ - VALUE==PQI_TH_2 ||\ - VALUE==PQI_TH_3 ||\ - VALUE==PQI_TH_4 ||\ - VALUE==PQI_TH_5 ||\ - VALUE==PQI_TH_6 ||\ - VALUE==PQI_TH_7 ||\ - VALUE==PQI_TH_8 ||\ - VALUE==PQI_TH_9 ||\ - VALUE==PQI_TH_10 ||\ - VALUE==PQI_TH_11 ||\ - VALUE==PQI_TH_12 ||\ - VALUE==PQI_TH_13 ||\ - VALUE==PQI_TH_14 ||\ - VALUE==PQI_TH_15) - -/** - * @brief SQI threshold value enumeration. - */ -typedef enum -{ - SQI_TH_0=0x00, - SQI_TH_1=0x40, - SQI_TH_2=0x80, - SQI_TH_3=0xC0 - -} SqiThreshold; - -#define IS_SQI_THR(VALUE) (VALUE==SQI_TH_0 ||\ - VALUE==SQI_TH_1 ||\ - VALUE==SQI_TH_2 ||\ - VALUE==SQI_TH_3) - - -/** - * @brief RSSI filter gain value enumeration. - */ -typedef enum -{ - RSSI_FG_0=0x00, - RSSI_FG_1=0x10, - RSSI_FG_2=0x20, - RSSI_FG_3=0x30, - RSSI_FG_4=0x40, - RSSI_FG_5=0x50, - RSSI_FG_6=0x60, - RSSI_FG_7=0x70, - RSSI_FG_8=0x80, - RSSI_FG_9=0x90, - RSSI_FG_10=0xA0, - RSSI_FG_11=0xB0, - RSSI_FG_12=0xC0, - RSSI_FG_13=0xD0, - RSSI_FG_14=0xE0, /*=-130 && VALUE<=-2) - -/** - *@} - */ - - -/** - * @defgroup Qi_Exported_Macros QI Exported Macros - * @{ - */ - -/** - * @brief Macro to obtain the RSSI value in dBm - * @param None. - * @retval RSSI in dBm. - * This parameter is a float. - */ -#define SpiritQiGetRssidBm() (-120.0+((float)(SpiritQiGetRssi()-20))/2) - -/** - *@} - */ - - -/** - * @defgroup Qi_Exported_Functions QI Exported Functions - * @{ - */ - -void SpiritQiPqiCheck(SpiritFunctionalState xNewState); -void SpiritQiSqiCheck(SpiritFunctionalState xNewState); -void SpiritQiSetPqiThreshold(PqiThreshold xPqiThr); -PqiThreshold SpiritQiGetPqiThreshold(void); -void SpiritQiSetSqiThreshold(SqiThreshold xSqiThr); -SqiThreshold SpiritQiGetSqiThreshold(void); -void SpiritQiSetRssiThreshold(uint8_t cRssiThr); -uint8_t SpiritQiGetRssiThreshold(void); -uint8_t SpiritQiComputeRssiThreshold(int cDbmValue); -void SpiritQiSetRssiThresholddBm(int nDbmValue); -uint8_t SpiritQiGetPqi(void); -uint8_t SpiritQiGetSqi(void); -uint8_t SpiritQiGetLqi(void); -SpiritFlagStatus SpiritQiGetCs(void); -uint8_t SpiritQiGetRssi(void); -void SpiritQiSetRssiFilterGain(RssiFilterGain xRssiFg); -RssiFilterGain SpiritQiGetRssiFilterGain(void); -void SpiritQiSetCsMode(CSMode xCsMode); -CSMode SpiritQiGetCsMode(void); -void SpiritQiCsTimeoutMask(SpiritFunctionalState xNewState); -void SpiritQiPqiTimeoutMask(SpiritFunctionalState xNewState); -void SpiritQiSqiTimeoutMask(SpiritFunctionalState xNewState); - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Radio.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Radio.h deleted file mode 100644 index 020829194..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Radio.h +++ /dev/null @@ -1,636 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Radio.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief This file provides all the low level API to manage Analog and Digital - * radio part of SPIRIT. - * @details - * - * In order to configure the Radio main parameters, the user can - * fit SRadioInit structure the and call the SpiritRadioInit() - * function passing its pointer as an argument. - * - * Example: - * @code - * - * SRadioInit radioInit = { - * 0, // Xtal offset in ppm - * 433.4e6, // base frequency - * 20e3, // channel space - * 0, // channel number - * FSK, // modulation select - * 38400, // datarate - * 20e3, // frequency deviation - * 100.5e3 // channel filter bandwidth - * }; - * - * ... - * - * SpiritRadioInit(&radioInit); - * @endcode - * - * Another important parameter for the radio configuration is the - * transmission power. - * The user is allowed to configure it using the function SpiritRadioSetPALeveldBm() - * which sets the PA LEVEL specified by the first argument to the - * power expressed in dBm by the second parameter. - * - * Example: - * @code - * - * SpiritRadioSetPALeveldBm(0 , 10.0); - * - * @endcode - * - * - * @note The effective power that is set can be a little different from the - * passed argument in dBm because the function performs an approximation. - * - - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_RADIO_H -#define __SPIRIT_RADIO_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" -#include "SPIRIT_Config.h" - - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** @defgroup SPIRIT_Radio Radio - * @brief Configuration and management of SPIRIT RF Analog and Digital part. - * @details See the file @ref SPIRIT_Radio.h for more details. - * @{ - */ - - - -/** @defgroup Radio_Exported_Types Radio Exported Types - * @{ - */ - - -/** - * @brief SPIRIT XTAL frequency enumeration - */ -typedef enum -{ - XTAL_FLAG_24_MHz = 0x00, /*!< 24 MHz Xtal selected */ - XTAL_FLAG_26_MHz = 0x01 /*!< 26 MHz Xtal selected */ - -}XtalFlag; - - -#define IS_XTAL_FLAG(FLAG) (((FLAG) == XTAL_FLAG_24_MHz) || \ - ((FLAG) == XTAL_FLAG_26_MHz)) - -/** - * @brief SPIRIT Band enumeration - */ -typedef enum -{ - HIGH_BAND = 0x00, /*!< High_Band selected: from 779 MHz to 915 MHz */ - MIDDLE_BAND = 0x01, /*!< Middle Band selected: from 387 MHz to 470 MHz */ - LOW_BAND = 0x02, /*!< Low Band selected: from 300 MHz to 348 MHz */ - VERY_LOW_BAND = 0x03 /*!< Vary low Band selected: from 150 MHz to 174 MHz */ -}BandSelect; - - -#define IS_BAND_SELECTED(BAND) ((BAND == HIGH_BAND) || \ - (BAND == MIDDLE_BAND) || \ - (BAND == LOW_BAND) || \ - (BAND == VERY_LOW_BAND)) - -/** - * @brief SPIRIT Modulation enumeration - */ -typedef enum -{ - FSK = 0x00, /*!< 2-FSK modulation selected */ - GFSK_BT05 = 0x50, /*!< GFSK modulation selected with BT=0.5 */ - GFSK_BT1 = 0x10, /*!< GFSK modulation selected with BT=1 */ - ASK_OOK = 0x20, /*!< ASK or OOK modulation selected. ASK will use power ramping */ - MSK = 0x30 /*!< MSK modulation selected */ - -}ModulationSelect; - - -#define IS_MODULATION_SELECTED(MOD) (((MOD) == FSK) || \ - ((MOD) == GFSK_BT05) || \ - ((MOD) == GFSK_BT1) || \ - ((MOD) == ASK_OOK) || \ - ((MOD) == MSK)) - - -/** - * @brief SPIRIT PA additional load capacitors bank enumeration - */ -typedef enum -{ - LOAD_0_PF = PA_POWER0_CWC_0, /*!< No additional PA load capacitor */ - LOAD_1_2_PF = PA_POWER0_CWC_1_2P, /*!< 1.2pF additional PA load capacitor */ - LOAD_2_4_PF = PA_POWER0_CWC_2_4P, /*!< 2.4pF additional PA load capacitor */ - LOAD_3_6_PF = PA_POWER0_CWC_3_6P /*!< 3.6pF additional PA load capacitor */ - -}PALoadCapacitor; - -#define IS_PA_LOAD_CAP(CWC) (((CWC) == LOAD_0_PF) || \ - ((CWC) == LOAD_1_2_PF) || \ - ((CWC) == LOAD_2_4_PF) || \ - ((CWC) == LOAD_3_6_PF)) - - -/** - * @brief SPIRIT AFC Mode selection - */ -typedef enum -{ - AFC_SLICER_CORRECTION = AFC2_AFC_MODE_SLICER, /*!< AFC loop closed on slicer */ - AFC_2ND_IF_CORRECTION = AFC2_AFC_MODE_MIXER /*!< AFC loop closed on 2nd conversion stage */ - -}AFCMode; - -#define IS_AFC_MODE(MODE) ((MODE) == AFC_SLICER_CORRECTION || (MODE) == AFC_2ND_IF_CORRECTION) - - -/** - * @brief SPIRIT AGC Mode selection - */ -typedef enum -{ - AGC_LINEAR_MODE = AGCCTRL0_AGC_MODE_LINEAR, /*!< AGC works in linear mode */ - AGC_BINARY_MODE = AGCCTRL0_AGC_MODE_BINARY /*!< AGC works in binary mode */ - -}AGCMode; - -#define IS_AGC_MODE(MODE) ((MODE) == AGC_LINEAR_MODE || (MODE) == AGC_BINARY_MODE) - - -/** - * @brief SPIRIT Clock Recovery Mode selection - */ -typedef enum -{ - CLK_REC_PLL = FDEV0_CLOCK_REG_ALGO_SEL_PLL, /*!< PLL alogrithm for clock recovery */ - CLK_REC_DLL = FDEV0_CLOCK_REG_ALGO_SEL_DLL /*!< DLL alogrithm for clock recovery */ - -}ClkRecMode; - -#define IS_CLK_REC_MODE(MODE) ((MODE) == CLK_REC_PLL || (MODE) == CLK_REC_DLL) - - -/** - * @brief SPIRIT Postfilter length - */ -typedef enum -{ - PSTFLT_LENGTH_8 = 0x00, /*!< Postfilter length is 8 symbols */ - PSTFLT_LENGTH_16 = 0x10 /*!< Postfilter length is 16 symbols */ - -}PstFltLength; - -#define IS_PST_FLT_LENGTH(LENGTH) ((LENGTH) == PSTFLT_LENGTH_8 || (LENGTH) == PSTFLT_LENGTH_16) - - -/** - * @brief SPIRIT OOK Peak Decay - */ -typedef enum -{ - FAST_DECAY = 0x00, /*!< Peak decay control for OOK: fast decay */ - MEDIUM_FAST_DECAY = 0x01, /*!< Peak decay control for OOK: medium_fast decay */ - MEDIUM_SLOW_DECAY = 0x02, /*!< Peak decay control for OOK: medium_fast decay */ - SLOW_DECAY = 0x03 /*!< Peak decay control for OOK: slow decay */ - -}OokPeakDecay; - -#define IS_OOK_PEAK_DECAY(DECAY) (((DECAY) == FAST_DECAY) ||\ - ((DECAY) == MEDIUM_FAST_DECAY) ||\ - ((DECAY) == MEDIUM_SLOW_DECAY) ||\ - ((DECAY) == SLOW_DECAY)) - - -/** - * @brief SPIRIT Radio Init structure definition - */ -typedef struct -{ - int16_t nXtalOffsetPpm; /*!< Specifies the offset frequency (in ppm) - to compensate crystal inaccuracy expressed - as signed value.*/ - - uint32_t lFrequencyBase; /*!< Specifies the base carrier frequency (in Hz), - i.e. the carrier frequency of channel #0. - This parameter can be in one of the following ranges: - High_Band: from 779 MHz to 915 MHz - Middle Band: from 387 MHz to 470 MHz - Low Band: from 300 MHz to 348 MHz */ - uint32_t nChannelSpace; /*!< Specifies the channel spacing expressed in Hz. - The channel spacing is expressed as: - NxFREQUENCY_STEPS, where FREQUENCY STEPS - is F_Xo/2^15. - This parameter can be in the range: [0, F_Xo/2^15*255] Hz */ - uint8_t cChannelNumber; /*!< Specifies the channel number. This value - is multiplied by the channel spacing and - added to synthesizer base frequency to - generate the actual RF carrier frequency */ - ModulationSelect xModulationSelect; /*!< Specifies the modulation. This - parameter can be any value of - @ref ModulationSelect */ - uint32_t lDatarate; /*!< Specifies the datarate expressed in bps. - This parameter can be in the range between - 100 bps and 500 kbps */ - uint32_t lFreqDev; /*!< Specifies the frequency deviation expressed in Hz. - This parameter can be in the range: [F_Xo*8/2^18, F_Xo*7680/2^18] Hz */ - uint32_t lBandwidth; /*!< Specifies the channel filter bandwidth - expressed in Hz. This parameter can be - in the range between 1100 and 800100 Hz */ - -}SRadioInit; - -/** - * @} - */ - - - -/** @defgroup Radio_Exported_Constants Radio Exported Constants - * @{ - */ - -/** @defgroup Radio_Band - * @{ - */ - -#define FBASE_DIVIDER 262144 /*!< 2^18 factor dividing fxo in fbase formula */ - -#define HIGH_BAND_FACTOR 6 /*!< Band select factor for high band. Factor B in the equation 2 */ -#define MIDDLE_BAND_FACTOR 12 /*!< Band select factor for middle band. Factor B in the equation 2 */ -#define LOW_BAND_FACTOR 16 /*!< Band select factor for low band. Factor B in the equation 2 */ -#define VERY_LOW_BAND_FACTOR 32 /*!< Band select factor for very low band. Factor B in the equation 2 */ - -#define HIGH_BAND_LOWER_LIMIT 778000000 /*!< Lower limit of the high band: 779 MHz */ -#define HIGH_BAND_UPPER_LIMIT 957100000 /*!< Upper limit of the high band: 956 MHz */ -#define MIDDLE_BAND_LOWER_LIMIT 386000000 /*!< Lower limit of the middle band: 387 MHz */ -#define MIDDLE_BAND_UPPER_LIMIT 471100000 /*!< Upper limit of the middle band: 470 MHz */ -#define LOW_BAND_LOWER_LIMIT 299000000 /*!< Lower limit of the low band: 300 MHz */ -#define LOW_BAND_UPPER_LIMIT 349100000 /*!< Upper limit of the low band: 348 MHz */ -#define VERY_LOW_BAND_LOWER_LIMIT 149000000 /*!< Lower limit of the very low band: 150 MHz */ -#define VERY_LOW_BAND_UPPER_LIMIT 175100000 /*!< Upper limit of the very low band: 174 MHz */ - -#define IS_FREQUENCY_BAND_HIGH(FREQUENCY) ((FREQUENCY)>=HIGH_BAND_LOWER_LIMIT && \ - (FREQUENCY)<=HIGH_BAND_UPPER_LIMIT) - -#define IS_FREQUENCY_BAND_MIDDLE(FREQUENCY) ((FREQUENCY)>=MIDDLE_BAND_LOWER_LIMIT && \ - (FREQUENCY)<=MIDDLE_BAND_UPPER_LIMIT) - -#define IS_FREQUENCY_BAND_LOW(FREQUENCY) ((FREQUENCY)>=LOW_BAND_LOWER_LIMIT && \ - (FREQUENCY)<=LOW_BAND_UPPER_LIMIT) - -#define IS_FREQUENCY_BAND_VERY_LOW(FREQUENCY) ((FREQUENCY)>=VERY_LOW_BAND_LOWER_LIMIT && \ - (FREQUENCY)<=VERY_LOW_BAND_UPPER_LIMIT) - -#define IS_FREQUENCY_BAND(FREQUENCY) (IS_FREQUENCY_BAND_HIGH(FREQUENCY)|| \ - IS_FREQUENCY_BAND_MIDDLE(FREQUENCY)|| \ - IS_FREQUENCY_BAND_LOW(FREQUENCY)|| \ - IS_FREQUENCY_BAND_VERY_LOW(FREQUENCY)) - -/** - * @} - */ - - -/** @defgroup Radio_IF_Offset Radio IF Offset - * @{ - */ -#define IF_OFFSET_ANA(F_Xo) (lroundf(480140.0/(F_Xo)*12288-64.0)) /*!< It represents the IF_OFFSET_ANA in order - to have an intermediate frequency of 480 kHz */ -/** - * @} - */ - - -/** @defgroup Radio_FC_Offset Radio FC Offset - * @{ - */ -#define F_OFFSET_DIVIDER 262144 /*!< 2^18 factor dividing fxo in foffset formula */ -#define PPM_FACTOR 1000000 /*!< 10^6 factor to use with Xtal_offset_ppm */ - - -#define F_OFFSET_LOWER_LIMIT(F_Xo) ((-(int32_t)F_Xo)/F_OFFSET_DIVIDER*2048) -#define F_OFFSET_UPPER_LIMIT(F_Xo) ((int32_t)(F_Xo/F_OFFSET_DIVIDER*2047)) - -#define IS_FREQUENCY_OFFSET(OFFSET, F_Xo) (OFFSET>=F_OFFSET_LOWER_LIMIT(F_Xo) && OFFSET<=F_OFFSET_UPPER_LIMIT(F_Xo)) - - -/** - * @} - */ - - -/** @defgroup Radio_Channel_Space Radio Channel Space - * @{ - */ - - -#define CHSPACE_DIVIDER 32768 /*!< 2^15 factor dividing fxo in channel space formula */ - -#define IS_CHANNEL_SPACE(CHANNELSPACE, F_Xo) (CHANNELSPACE<=(F_Xo/32768*255)) - - - - - -/** - * @} - */ - - -/** @defgroup Radio_Datarate Radio Datarate - * @{ - */ -#define MINIMUM_DATARATE 100 /*!< Minimum datarate supported by SPIRIT1 100 bps */ -#define MAXIMUM_DATARATE 510000 /*!< Maximum datarate supported by SPIRIT1 500 kbps */ - -#define IS_DATARATE(DATARATE) (DATARATE>=MINIMUM_DATARATE && DATARATE<=MAXIMUM_DATARATE) - -/** - * @} - */ - - -/** @defgroup Radio_Frequency_Deviation Radio Frequency Deviation - * @{ - */ -#define F_DEV_MANTISSA_UPPER_LIMIT 7 /*!< Maximum value for the mantissa in frequency deviation formula */ -#define F_DEV_EXPONENT_UPPER_LIMIT 9 /*!< Maximum value for the exponent in frequency deviation formula */ - -#define F_DEV_LOWER_LIMIT(F_Xo) (F_Xo>>16) -#define F_DEV_UPPER_LIMIT(F_Xo) ((F_Xo*15)>>10) - -#define IS_F_DEV(FDEV,F_Xo) (FDEV>=F_DEV_LOWER_LIMIT(F_Xo) && FDEV<=F_DEV_UPPER_LIMIT(F_Xo)) - - -/** - * @} - */ - - -/** @defgroup Radio_Channel_Bandwidth Radio Channel Bandwidth - * @{ - */ -#define CH_BW_LOWER_LIMIT(F_Xo) 1100*(F_Xo/1000000)/26 /*!< Minimum value of the channel filter bandwidth */ -#define CH_BW_UPPER_LIMIT(F_Xo) 800100*(F_Xo/1000000)/26 /*!< Maximum value of the channel filter bandwidth */ - -#define IS_CH_BW(BW,F_Xo) ((BW)>=CH_BW_LOWER_LIMIT(F_Xo) && (BW)<=CH_BW_UPPER_LIMIT(F_Xo)) - -/** - * @} - */ - - -/** @defgroup Radio_Power_Amplifier Radio Power Amplifier - * @{ - */ - -#define IS_PA_MAX_INDEX(INDEX) ((INDEX)<=7) -#define IS_PAPOWER_DBM(PATABLE) ((PATABLE)>= (-31) && (PATABLE)<=(12)) -#define IS_PAPOWER(PATABLE) ((PATABLE)<=90) -#define IS_PA_STEP_WIDTH(WIDTH) ((WIDTH)>=1 && (WIDTH)<=4) - -/** - * @} - */ - - -/** @defgroup Radio_Automatic_Frequency_Correction Radio Automatic Frequency Correction - * @{ - */ - -#define IS_AFC_FAST_GAIN(GAIN) ((GAIN)<=15) -#define IS_AFC_SLOW_GAIN(GAIN) ((GAIN)<=15) -#define IS_AFC_PD_LEAKAGE(LEAKAGE) ((LEAKAGE)<=31) - -/** - * @} - */ - -/** @defgroup Radio_Automatic_Gain_Control Radio Automatic Gain Control - * @{ - */ - -#define AGC_MEASURE_TIME_UPPER_LIMIT_US(F_Xo) (393216.0/F_Xo) - -#define IS_AGC_MEASURE_TIME_US(TIME, F_Xo) (TIME<=AGC_MEASURE_TIME_UPPER_LIMIT_US(F_Xo)) - -#define IS_AGC_MEASURE_TIME(TIME) (TIME<=15) - -#define AGC_HOLD_TIME_UPPER_LIMIT_US(F_Xo) (756.0/F_Xo) - -#define IS_AGC_HOLD_TIME_US(TIME,F_Xo) (TIME<=AGC_HOLD_TIME_UPPER_LIMIT_US(F_Xo)) - - -#define IS_AGC_HOLD_TIME(TIME) (TIME<=63) - -#define IS_AGC_THRESHOLD(THRESHOLD) (THRESHOLD<=15) - -/** - * @} - */ - - -/** @defgroup Radio_Clock_Recovery Radio Clock Recovery - * @{ - */ - -#define IS_CLK_REC_P_GAIN(GAIN) ((GAIN)<=7) -#define IS_CLK_REC_I_GAIN(GAIN) ((GAIN)<=15) - -/** - * @} - */ - -/** - * @} - */ - - - -/** @defgroup Radio_Exported_Macros Radio Exported Macros - * @{ - */ - - -/** - * @} - */ - -/** @defgroup Radio_Exported_Functions Radio Exported Functions - * @{ - */ - -uint8_t SpiritRadioInit(SRadioInit* pxSRadioInitStruct); -void SpiritRadioGetInfo(SRadioInit* pxSRadioInitStruct); -void SpiritRadioSetXtalFlag(XtalFlag xXtal); -XtalFlag SpiritRadioGetXtalFlag(void); -uint8_t SpiritRadioSearchWCP(uint32_t lFc); -void SpiritRadioSetSynthWord(uint32_t lSynthWord); -uint32_t SpiritRadioGetSynthWord(void); -void SpiritRadioSetBand(BandSelect xBand); -BandSelect SpiritRadioGetBand(void); -void SpiritRadioSetChannel(uint8_t cChannel); -uint8_t SpiritRadioGetChannel(void); -void SpiritRadioSetChannelSpace(uint32_t lChannelSpace); -uint32_t SpiritRadioGetChannelSpace(void); -void SpiritRadioSetFrequencyOffsetPpm(int16_t nXtalPpm); -void SpiritRadioSetFrequencyOffset(int32_t lFOffset); -int32_t SpiritRadioGetFrequencyOffset(void); -void SpiritRadioVcoCalibrationWAFB(SpiritFunctionalState xNewstate); -uint8_t SpiritRadioSetFrequencyBase(uint32_t lFBase); -uint32_t SpiritRadioGetFrequencyBase(void); -uint32_t SpiritRadioGetCenterFrequency(void); -void SpiritRadioSearchDatarateME(uint32_t lDatarate, uint8_t* pcM, uint8_t* pcE); -void SpiritRadioSearchFreqDevME(uint32_t lFDev, uint8_t* pcM, uint8_t* pcE); -void SpiritRadioSearchChannelBwME(uint32_t lBandwidth, uint8_t* pcM, uint8_t* pcE); -void SpiritRadioSetDatarate(uint32_t lDatarate); -uint32_t SpiritRadioGetDatarate(void); -void SpiritRadioSetFrequencyDev(uint32_t lFDev); -uint32_t SpiritRadioGetFrequencyDev(void); -void SpiritRadioSetChannelBW(uint32_t lBandwidth); -uint32_t SpiritRadioGetChannelBW(void); -void SpiritRadioSetModulation(ModulationSelect xModulation); -ModulationSelect SpiritRadioGetModulation(void); -void SpiritRadioCWTransmitMode(SpiritFunctionalState xNewState); -void SpiritRadioSetOokPeakDecay(OokPeakDecay xOokDecay); -OokPeakDecay SpiritRadioGetOokPeakDecay(void); -uint8_t SpiritRadioGetdBm2Reg(uint32_t lFBase, float fPowerdBm); -float SpiritRadioGetReg2dBm(uint32_t lFBase, uint8_t cPowerReg); -void SpiritRadioSetPATabledBm(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, float* pfPAtabledBm); -void SpiritRadioGetPATabledBm(uint8_t* pcPALevelMaxIndex, float* pfPAtabledBm); -void SpiritRadioSetPATable(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, uint8_t* pcPAtable); -void SpiritRadioGetPATable(uint8_t* pcPALevelMaxIndex, uint8_t* pcPAtable); -void SpiritRadioSetPALeveldBm(uint8_t cIndex, float fPowerdBm); -float SpiritRadioGetPALeveldBm(uint8_t cIndex); -void SpiritRadioSetPALevel(uint8_t cIndex, uint8_t cPower); -uint8_t SpiritRadioGetPALevel(uint8_t cIndex); -void SpiritRadioSetPACwc(PALoadCapacitor xCLoad); -PALoadCapacitor SpiritRadioGetPACwc(void); -void SpiritRadioSetPALevelMaxIndex(uint8_t cIndex); -uint8_t SpiritRadioGetPALevelMaxIndex(void); -void SpiritRadioSetPAStepWidth(uint8_t cWidth); -uint8_t SpiritRadioGetPAStepWidth(void); -void SpiritRadioPARamping(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritRadioGetPARamping(void); -void SpiritRadioAFC(SpiritFunctionalState xNewState); -void SpiritRadioAFCFreezeOnSync(SpiritFunctionalState xNewState); -void SpiritRadioSetAFCMode(AFCMode xMode); -AFCMode SpiritRadioGetAFCMode(void); -void SpiritRadioSetAFCPDLeakage(uint8_t cLeakage); -uint8_t SpiritRadioGetAFCPDLeakage(void); -void SpiritRadioSetAFCFastPeriod(uint8_t cLength); -uint8_t SpiritRadioGetAFCFastPeriod(void); -void SpiritRadioSetAFCFastGain(uint8_t cGain); -uint8_t SpiritRadioGetAFCFastGain(void); -void SpiritRadioSetAFCSlowGain(uint8_t cGain); -uint8_t SpiritRadioGetAFCSlowGain(void); -int8_t SpiritRadioGetAFCCorrectionReg(void); -int32_t SpiritRadioGetAFCCorrectionHz(void); -void SpiritRadioAGC(SpiritFunctionalState xNewState); -void SpiritRadioSetAGCMode(AGCMode xMode); -AGCMode SpiritRadioGetAGCMode(void); -void SpiritRadioAGCFreezeOnSteady(SpiritFunctionalState xNewState); -void SpiritRadioAGCFreezeOnSync(SpiritFunctionalState xNewState); -void SpiritRadioAGCStartMaxAttenuation(SpiritFunctionalState xNewState); -void SpiritRadioSetAGCMeasureTimeUs(uint16_t nTime); -uint16_t SpiritRadioGetAGCMeasureTimeUs(void); -void SpiritRadioSetAGCMeasureTime(uint8_t cTime); -uint8_t SpiritRadioGetAGCMeasureTime(void); -void SpiritRadioSetAGCHoldTimeUs(uint8_t cTime); -uint8_t SpiritRadioGetAGCHoldTimeUs(void); -void SpiritRadioSetAGCHoldTime(uint8_t cTime); -uint8_t SpiritRadioGetAGCHoldTime(void); -void SpiritRadioSetAGCHighThreshold(uint8_t cHighThreshold); -uint8_t SpiritRadioGetAGCHighThreshold(void); -void SpiritRadioSetAGCLowThreshold(uint8_t cLowThreshold); -uint8_t SpiritRadioGetAGCLowThreshold(void); -void SpiritRadioSetClkRecMode(ClkRecMode xMode); -ClkRecMode SpiritRadioGetClkRecMode(void); -void SpiritRadioSetClkRecPGain(uint8_t cPGain); -uint8_t SpiritRadioGetClkRecPGain(void); -void SpiritRadioSetClkRecIGain(uint8_t cIGain); -uint8_t SpiritRadioGetClkRecIGain(void); -void SpiritRadioSetClkRecPstFltLength(PstFltLength xLength); -PstFltLength SpiritRadioGetClkRecPstFltLength(void); -void SpiritRadioCsBlanking(SpiritFunctionalState xNewState); -void SpiritRadioPersistenRx(SpiritFunctionalState xNewState); -uint32_t SpiritRadioGetXtalFrequency(void); -void SpiritRadioSetXtalFrequency(uint32_t lXtalFrequency); -void SpiritRadioSetRefDiv(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritRadioGetRefDiv(void); -void SpiritRadioSetDigDiv(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritRadioGetDigDiv(void); -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Regs.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Regs.h deleted file mode 100644 index af742adca..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Regs.h +++ /dev/null @@ -1,3244 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Regs.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief This file contains all the SPIRIT registers address and masks. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT1_REGS_H -#define __SPIRIT1_REGS_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** - * @addtogroup SPIRIT_Registers SPIRIT Registers - * @brief Header file containing all the SPIRIT registers address and masks. - * @details See the file @ref SPIRIT_Regs.h for more details. - * @{ - */ - -/** @defgroup General_Configuration_Registers - * @{ - */ - -/** @defgroup ANA_FUNC_CONF_1_Register - * @{ - */ - -/** - * \brief ANA_FUNC_CONF register 1 - * \code - * Read Write - * Default value: 0x0C - * 7:5 NUM_EN_PIPES: Number of enabled pipes (starting from Data Pipe 0). - * 4:2 GM_CONF[2:0]: Sets the driver gm of the XO at start-up: - * GM_CONF2 | GM_CONF1 | GM_CONF0 | GM [mS] - * ------------------------------------------ - * 0 | 0 | 0 | 13.2 - * 0 | 0 | 1 | 18.2 - * 0 | 1 | 0 | 21.5 - * 0 | 1 | 1 | 25.6 - * 1 | 0 | 0 | 28.8 - * 1 | 0 | 1 | 33.9 - * 1 | 1 | 0 | 38.5 - * 1 | 1 | 1 | 43.0 - * 1:0 SET_BLD_LVL[1:0]: Sets the Battery Level Detector threshold: - * SET_BLD_LVL1 | SET_BLD_LVL0 | Threshold [V] - * ------------------------------------------ - * 0 | 0 | 2.7 - * 0 | 1 | 2.5 - * 1 | 0 | 2.3 - * 1 | 1 | 2.1 - * \endcode - */ - -#define ANA_FUNC_CONF1_BASE ((uint8_t)0x00) /*!< ANA_FUNC_CONF1 Address (R/W) */ - -#define ANA_FUNC_CONF1_NUM_PIPES_MASK ((uint8_t)0xE0) /*!< Mask for number of enabled pipes*/ - -#define ANA_FUNC_CONF1_GMCONF_MASK ((uint8_t)0x1C) /*!< Mask of the GmConf field of ANA_FUNC_CONF1 register (R/W) */ - -#define GM_13_2 ((uint8_t)0x00) /*!< Transconducatance Gm at start-up 13.2 mS */ -#define GM_18_2 ((uint8_t)0x04) /*!< Transconducatance Gm at start-up 18.2 mS */ -#define GM_21_5 ((uint8_t)0x08) /*!< Transconducatance Gm at start-up 21.5 mS */ -#define GM_25_6 ((uint8_t)0x0C) /*!< Transconducatance Gm at start-up 25.6 mS */ -#define GM_28_8 ((uint8_t)0x10) /*!< Transconducatance Gm at start-up 28.8 mS */ -#define GM_33_9 ((uint8_t)0x14) /*!< Transconducatance Gm at start-up 33.9 mS */ -#define GM_38_5 ((uint8_t)0x18) /*!< Transconducatance Gm at start-up 38.5 mS */ -#define GM_43_0 ((uint8_t)0x1C) /*!< Transconducatance Gm at start-up 43.0 mS */ - -#define ANA_FUNC_CONF1_SET_BLD_LVL_MASK ((uint8_t)0x03) /*!< Mask of the SET_BLD_LV field of ANA_FUNC_CONF1 register (R/W) */ - -#define BLD_LVL_2_7 ((uint8_t)0x00) /*!< Sets the Battery Level Detector threshold to 2.7V */ -#define BLD_LVL_2_5 ((uint8_t)0x01) /*!< Sets the Battery Level Detector threshold to 2.5V */ -#define BLD_LVL_2_3 ((uint8_t)0x02) /*!< Sets the Battery Level Detector threshold to 2.3V */ -#define BLD_LVL_2_1 ((uint8_t)0x03) /*!< Sets the Battery Level Detector threshold to 2.1V */ - -/** - * @} - */ - - -/** @defgroup ANA_FUNC_CONF_0_Register - * @{ - */ - -/** - * \brief ANA_FUNC_CONF register 0 - * \code - * Read Write - * Default value: 0xC0 - * 7 Reserved. - * 6 24_26_MHz_SELECT: 1 - 26 MHz configuration - * 0 - 24 MHz configuration - * 5 AES_ON: 1 - AES engine enabled - * 0 - AES engine disabled - * 4 EXT_REF: 1 - Reference signal from XIN pin - * 0 - Reference signal from XO circuit - * 3 HIGH_POWER_MODE: 1 - SET_SMPS_LEVEL word will be set to the value to - * PM_TEST register in RX state, while in TX state it - * will be fixed to 111 (which programs the SMPS output - * at max value 1.8V) - * 0 - SET_SMPS_LEVEL word will hold the value written in the - * PM_TEST register both in RX and TX state - * 2 BROWN_OUT: 1 - Brown_Out Detection enabled - * 0 - Brown_Out Detection disabled - * 1 BATTERY_LEVEL: 1 - Battery level detector enabled - * 0 - Battery level detector disabled - * 0 TS: 1 - Enable the "Temperature Sensor" function - * 0 - Disable the "Temperature Sensor" function - * \endcode - */ - - -#define ANA_FUNC_CONF0_BASE ((uint8_t)0x01) /*!< ANA_FUNC_CONF0 Address (R/W) */ - -#define SELECT_24_26_MHZ_MASK ((uint8_t)0x40) /*!< Configure the RCO if using 26 MHz or 24 MHz master clock/reference signal */ -#define AES_MASK ((uint8_t)0x20) /*!< AES engine on/off */ -#define EXT_REF_MASK ((uint8_t)0x10) /*!< Reference signal from XIN pin (oscillator external) or from XO circuit (oscillator internal)*/ -#define HIGH_POWER_MODE_MASK ((uint8_t)0x08) /*!< SET_SMPS_LEVEL word will be set to the value to PM_TEST register - in RX state, while in TX state it will be fixed to 111 - (which programs the SMPS output at max value, 1.8V) */ -#define BROWN_OUT_MASK ((uint8_t)0x04) /*!< Accurate Brown-Out detection on/off */ -#define BATTERY_LEVEL_MASK ((uint8_t)0x02) /*!< Battery level detector circuit on/off */ -#define TEMPERATURE_SENSOR_MASK ((uint8_t)0x01) /*!< The Temperature Sensor (available on GPIO0) on/off */ - -/** - * @} - */ - -/** @defgroup ANT_SELECT_CONF_Register - * @{ - */ - -/** - * \brief ANT_SELECT_CONF register - * \code - * Read Write - * Default value: 0x05 - * - * 7:5 Reserved. - * - * 4 CS_BLANKING: Blank received data if signal is below the CS threshold - * - * 3 AS_ENABLE: Enable antenna switching - * 1 - Enable - * 0 - Disable - * - * 2:0 AS_MEAS_TIME[2:0]: Measurement time according to the formula Tmeas = 24*2^(EchFlt)*2^AS_MEAS_TIME/fxo - * \endcode - */ -#define ANT_SELECT_CONF_BASE ((uint8_t)0x27) /*!< Antenna diversity (works only in static carrier sense mode) */ -#define ANT_SELECT_CS_BLANKING_MASK ((uint8_t)0x10) /*!< CS data blanking on/off */ -#define ANT_SELECT_CONF_AS_MASK ((uint8_t)0x08) /*!< Antenna diversity on/off */ - -/** - * @} - */ - -/** @defgroup DEVICE_INFO1_Register - * @{ - */ - -/** - * \brief DEVICE_INFO1[7:0] registers - * \code - * Default value: 0x01 - * Read - * - * 7:0 PARTNUM[7:0]: Device part number - * \endcode - */ -#define DEVICE_INFO1_PARTNUM ((uint8_t)(0xF0)) /*!< Device part number [7:0] */ - -/** - * @} - */ - -/** @defgroup DEVICE_INFO0_Register - * @{ - */ - -/** - * \brief DEVICE_INFO0[7:0] registers - * \code - * Read - * - * 7:0 VERSION[7:0]: Device version number - * \endcode - */ -#define DEVICE_INFO0_VERSION ((uint8_t)(0xF1)) /*!< Device version [7:0]; (0x55 in CUT1.0) */ - -/** - * @} - */ - - -/** - * @} - */ - - -/** @defgroup GPIO_Registers - * @{ - */ - -/** @defgroup GPIOx_CONF_Registers - * @{ - */ - -/** - * \brief GPIOx registers - * \code - * Read Write - * Default value: 0x03 - * 7:3 GPIO_SELECT[4:0]: Specify the I/O signal. - * GPIO_SELECT[4:0] | I/O | Signal - * ------------------------------------------------ - * 0 | Output | nIRQ - * 0 | Input | TX command - * 1 | Output | POR inverted - * 1 | Input | RX command - * 2 | Output | Wake-Up timer expiration - * 2 | Input | TX data for direct modulation - * 3 | Output | Low Battery Detection - * 3 | Input | Wake-up from external input - * 4 | Output | TX clock output - * 5 | Output | TX state - * 6 | Output | TX FIFO Almost Empty Flag - * 7 | Output | TX FIFO ALmost Full Flag - * 8 | Output | RX data output - * 9 | Output | RX clock output - * 10 | Output | RX state - * 11 | Output | RX FIFO Almost Full Flag - * 12 | Output | RX FIFO Almost Empty Flag - * 13 | Output | Antenna switch - * 14 | Output | Valid preamble detected - * 15 | Output | Sync word detected - * 16 | Output | RSSI above threshold - * 17 | Output | MCU clock - * 18 | Output | TX or RX mode indicator - * 19 | Output | VDD - * 20 | Output | GND - * 21 | Output | External SMPS enable signal - * 22-31 | Not Used | Not Used - * 2 Reserved - * 1:0 GpioMode[1:0]: Specify the mode: - * GPIO_MODE1 | GPIO_MODE0 | MODE - * ------------------------------------------------------------ - * 0 | 0 | Analog (valid only for GPIO_0) - * 0 | 1 | Digital Input - * 1 | 0 | Digital Output Low Power - * 1 | 1 | Digital Output High Power - * - * Note: The Analog mode is used only for temperature sensor indication. This is available only - * on GPIO_0 by setting the TS bit in the ANA_FUNC_CONF_0_Register. - * \endcode - */ - - -#define GPIO3_CONF_BASE ((uint8_t)0x02) /*!< GPIO_3 register address */ -#define GPIO2_CONF_BASE ((uint8_t)0x03) /*!< GPIO_3 register address */ -#define GPIO1_CONF_BASE ((uint8_t)0x04) /*!< GPIO_3 register address */ -#define GPIO0_CONF_BASE ((uint8_t)0x05) /*!< GPIO_3 register address */ - -#define CONF_GPIO_IN_TX_Command ((uint8_t)0x00) /*!< TX command direct from PIN (rising edge, width min=50ns) */ -#define CONF_GPIO_IN_RX_Command ((uint8_t)0x08) /*!< RX command direct from PIN (rising edge, width min=50ns)*/ -#define CONF_GPIO_IN_TX_Data ((uint8_t)0x10) /*!< TX data input for direct modulation */ -#define CONF_GPIO_IN_WKUP_Ext ((uint8_t)0x18) /*!< Wake up from external input */ - -#define CONF_GPIO_OUT_nIRQ ((uint8_t)0x00) /*!< nIRQ (Interrupt Request, active low) , default configuration after POR */ -#define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /*!< POR inverted (active low) */ -#define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /*!< Wake-Up Timer expiration: ‘1’ when WUT has expired */ -#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /*!< Low battery detection: ‘1’ when battery is below threshold setting */ -#define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /*!< TX data internal clock output (TX data are sampled on the rising edge of it) */ -#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /*!< TX state indication: ‘1’ when Spirit1 is transiting in the TX state */ -#define CONF_GPIO_OUT_TX_FIFO_Almost_Empty ((uint8_t)0x30) /*!< TX FIFO Almost Empty Flag */ -#define CONF_GPIO_OUT_TX_FIFO_Amost_Full ((uint8_t)0x38) /*!< TX FIFO Almost Full Flag */ -#define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /*!< RX data output */ -#define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /*!< RX clock output (recovered from received data) */ -#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /*!< RX state indication: ‘1’ when Spirit1 is transiting in the RX state */ -#define CONF_GPIO_OUT_RX_FIFO_Almost_Full ((uint8_t)0x58) /*!< RX FIFO Almost Full Flag */ -#define CONF_GPIO_OUT_RX_FIFO_Almost_Empty ((uint8_t)0x60) /*!< RX FIFO Almost Empty Flag */ -#define CONF_GPIO_OUT_Antenna_Switch ((uint8_t)0x68) /*!< Antenna switch used for antenna diversity */ -#define CONF_GPIO_OUT_Valid_Preamble ((uint8_t)0x70) /*!< Valid Preamble Detected Flag */ -#define CONF_GPIO_OUT_Sync_Detected ((uint8_t)0x78) /*!< Sync WordSync Word Detected Flag */ -#define CONF_GPIO_OUT_RSSI_Threshold ((uint8_t)0x80) /*!< CCA Assessment Flag */ -#define CONF_GPIO_OUT_MCU_Clock ((uint8_t)0x88) /*!< MCU Clock */ -#define CONF_GPIO_OUT_TX_RX_Mode ((uint8_t)0x90) /*!< TX or RX mode indicator (to enable an external range extender) */ -#define CONF_GPIO_OUT_VDD ((uint8_t)0x98) /*!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) */ -#define CONF_GPIO_OUT_GND ((uint8_t)0xA0) /*!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) */ -#define CONF_GPIO_OUT_SMPS_Ext ((uint8_t)0xA8) /*!< External SMPS enable signal (active high) */ - -#define CONF_GPIO_MODE_ANALOG ((uint8_t)0x00) /*!< Analog test BUS on GPIO; used only in test mode (except for temperature sensor) */ -#define CONF_GPIO_MODE_DIG_IN ((uint8_t)0x01) /*!< Digital Input on GPIO */ -#define CONF_GPIO_MODE_DIG_OUTL ((uint8_t)0x02) /*!< Digital Output on GPIO (low current) */ -#define CONF_GPIO_MODE_DIG_OUTH ((uint8_t)0x03) /*!< Digital Output on GPIO (high current) */ - -/** - * @} - */ - - -/** @defgroup MCU_CK_CONF_Register - * @{ - */ - -/** - * \brief MCU_CK_CONF register - * \code - * Read Write - * Default value: 0x00 - * 7 Reserved. - * 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided before entering in STANDBY state. - * CLOCK_TAIL1 | CLOCK_TAIL0 | Number of Extra Cycles - * ------------------------------------------------------------ - * 0 | 0 | 0 - * 0 | 1 | 64 - * 1 | 0 | 256 - * 1 | 1 | 512 - * 4:1 XO_RATIO[3:0]: Specifies the division ratio when XO oscillator is the clock source - * XO_RATIO[3:0] | Division Ratio - * ----------------------------------- - * 0 | 1 - * 1 | 2/3 - * 2 | 1/2 - * 3 | 1/3 - * 4 | 1/4 - * 5 | 1/6 - * 6 | 1/8 - * 7 | 1/12 - * 8 | 1/16 - * 9 | 1/24 - * 10 | 1/36 - * 11 | 1/48 - * 12 | 1/64 - * 13 | 1/96 - * 14 | 1/128 - * 15 | 1/256 - * 0 RCO_RATIO: Specifies the divsion ratio when RC oscillator is the clock source - * 0 - Division Ratio equal to 0 - * 1 - Division Ratio equal to 1/128 - * \endcode - */ - - -#define MCU_CK_CONF_BASE ((uint8_t)0x06) /*!< MCU Clock Config register address */ - -#define MCU_CK_ENABLE ((uint8_t)0x80) /*!< MCU clock enable bit */ - -#define MCU_CK_CONF_CLOCK_TAIL_0 ((uint8_t)0x00) /*!< 0 extra clock cycles provided to the MCU before switching to STANDBY state */ -#define MCU_CK_CONF_CLOCK_TAIL_64 ((uint8_t)0x20) /*!< 64 extra clock cycles provided to the MCU before switching to STANDBY state */ -#define MCU_CK_CONF_CLOCK_TAIL_256 ((uint8_t)0x40) /*!< 256 extra clock cycles provided to the MCU before switching to STANDBY state */ -#define MCU_CK_CONF_CLOCK_TAIL_512 ((uint8_t)0x60) /*!< 512 extra clock cycles provided to the MCU before switching to STANDBY state */ -#define MCU_CK_CONF_XO_RATIO_1 ((uint8_t)0x00) /*!< XO Clock signal available on the GPIO divided by 1 */ -#define MCU_CK_CONF_XO_RATIO_2_3 ((uint8_t)0x02) /*!< XO Clock signal available on the GPIO divided by 2/3 */ -#define MCU_CK_CONF_XO_RATIO_1_2 ((uint8_t)0x04) /*!< XO Clock signal available on the GPIO divided by 1/2 */ -#define MCU_CK_CONF_XO_RATIO_1_3 ((uint8_t)0x06) /*!< XO Clock signal available on the GPIO divided by 1/3 */ -#define MCU_CK_CONF_XO_RATIO_1_4 ((uint8_t)0x08) /*!< XO Clock signal available on the GPIO divided by 1/4 */ -#define MCU_CK_CONF_XO_RATIO_1_6 ((uint8_t)0x0A) /*!< XO Clock signal available on the GPIO divided by 1/6 */ -#define MCU_CK_CONF_XO_RATIO_1_8 ((uint8_t)0x0C) /*!< XO Clock signal available on the GPIO divided by 1/8 */ -#define MCU_CK_CONF_XO_RATIO_1_12 ((uint8_t)0x0E) /*!< XO Clock signal available on the GPIO divided by 1/12 */ -#define MCU_CK_CONF_XO_RATIO_1_16 ((uint8_t)0x10) /*!< XO Clock signal available on the GPIO divided by 1/16 */ -#define MCU_CK_CONF_XO_RATIO_1_24 ((uint8_t)0x12) /*!< XO Clock signal available on the GPIO divided by 1/24 */ -#define MCU_CK_CONF_XO_RATIO_1_36 ((uint8_t)0x14) /*!< XO Clock signal available on the GPIO divided by 1/36 */ -#define MCU_CK_CONF_XO_RATIO_1_48 ((uint8_t)0x16) /*!< XO Clock signal available on the GPIO divided by 1/48 */ -#define MCU_CK_CONF_XO_RATIO_1_64 ((uint8_t)0x18) /*!< XO Clock signal available on the GPIO divided by 1/64 */ -#define MCU_CK_CONF_XO_RATIO_1_96 ((uint8_t)0x1A) /*!< XO Clock signal available on the GPIO divided by 1/96 */ -#define MCU_CK_CONF_XO_RATIO_1_128 ((uint8_t)0x1C) /*!< XO Clock signal available on the GPIO divided by 1/128 */ -#define MCU_CK_CONF_XO_RATIO_1_192 ((uint8_t)0x1E) /*!< XO Clock signal available on the GPIO divided by 1/196 */ -#define MCU_CK_CONF_RCO_RATIO_1 ((uint8_t)0x00) /*!< RCO Clock signal available on the GPIO divided by 1 */ -#define MCU_CK_CONF_RCO_RATIO_1_128 ((uint8_t)0x01) /*!< RCO Clock signal available on the GPIO divided by 1/128*/ - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup Radio_Configuration_Registers - * @{ - */ - - - -/** @defgroup SYNT3_Register - * @{ - */ - -/** - * \brief SYNT3 register - * \code - * Read Write - * Default value: 0x0C - * - * 7:5 WCP[2:0]: Set the charge pump current according to the VCO frequency in RX mode. - * - * VCO Frequency | WCP2 | WCP1 | WCP0 | Charge Pump Current (uA) - * ------------------------------------------------------------------------------------------------------------ - * 4644-4678 | 0 | 0 | 0 | 378.4 - * 4708-4772 | 0 | 0 | 1 | 368.9 - * 4772-4836 | 0 | 1 | 0 | 359.5 - * 4836-4902 | 0 | 1 | 1 | 350 - * 4902-4966 | 1 | 0 | 0 | 340.5 - * 4966-5030 | 1 | 0 | 1 | 331.1 - * 5030-5095 | 1 | 1 | 0 | 321.6 - * 5095-5161 | 1 | 1 | 1 | 312.2 - * 5161-5232 | 0 | 0 | 0 | 378.4 - * 5232-5303 | 0 | 0 | 1 | 368.9 - * 5303-5375 | 0 | 1 | 0 | 359.5 - * 5375-5448 | 0 | 1 | 1 | 350 - * 5448-5519 | 1 | 0 | 0 | 340.5 - * 5519-5592 | 1 | 0 | 1 | 331.1 - * 5592-5663 | 1 | 1 | 0 | 321.6 - * 5663-5736 | 1 | 1 | 1 | 312.2 - * - * - * 4:0 SYNT[25:21]: highest 5 bits of the PLL programmable divider - * The valid range depends on fXO and REFDIV settings; for - * fXO=26MHz - * REFDIV = 0 - SYNT[25:21] = 11...13 - * REFDIV = 1 - SYNT[25:21] = 22…27 - * - * - * \endcode - */ -#define SYNT3_BASE ((uint8_t)0x08) /*!< [4:0] -> SYNT[25:21], highest 5 bits of the PLL programmable divider */ - -#define WCP_CONF_WCP_378UA ((uint8_t)0x00) /*!< Charge pump current nominal value = 378uA [VCO 4644-4708]&[VCO 5161-5232] */ -#define WCP_CONF_WCP_369UA ((uint8_t)0x01) /*!< Charge pump current nominal value = 369uA [VCO 4708-4772]&[VCO 5232-5303] */ -#define WCP_CONF_WCP_359UA ((uint8_t)0x02) /*!< Charge pump current nominal value = 359uA [VCO 4772-4836]&[VCO 5303-5375] */ -#define WCP_CONF_WCP_350UA ((uint8_t)0x03) /*!< Charge pump current nominal value = 350uA [VCO 4836-4902]&[VCO 5375-5448] */ -#define WCP_CONF_WCP_340UA ((uint8_t)0x04) /*!< Charge pump current nominal value = 340uA [VCO 4902-4966]&[VCO 5448-5519] */ -#define WCP_CONF_WCP_331UA ((uint8_t)0x05) /*!< Charge pump current nominal value = 331uA [VCO 4966-5030]&[VCO 5519-5592] */ -#define WCP_CONF_WCP_321UA ((uint8_t)0x06) /*!< Charge pump current nominal value = 321uA [VCO 5030-5095]&[VCO 5592-5563] */ -#define WCP_CONF_WCP_312UA ((uint8_t)0x07) /*!< Charge pump current nominal value = 312uA [VCO 5095-5160]&[VCO 5563-5736] */ - - -/** - * @} - */ - - -/** @defgroup SYNT2_Register - * @{ - */ - -/** - * \brief SYNT2 register - * \code - * Read Write - * Default value: 0x84 - * 7:0 SYNT[20:13]: intermediate bits of the PLL programmable divider. - * - * \endcode - */ - -#define SYNT2_BASE ((uint8_t)0x09) /*!< SYNT[20:13], intermediate bits of the PLL programmable divider */ - -/** - * @} - */ - -/** @defgroup SYNT1_Register - * @{ - */ - -/** - * \brief SYNT1 register - * \code - * Read Write - * Default value: 0xEC - * 7:0 SYNT[12:5]: intermediate bits of the PLL programmable divider. - * - * \endcode - */ - -#define SYNT1_BASE ((uint8_t)0x0A) /*!< SYNT[12:5], intermediate bits of the PLL programmable divider */ - -/** - * @} - */ - -/** @defgroup SYNT0_Register - * @{ - */ - -/** - * \brief SYNT0 register - * \code - * Read Write - * Default value: 0x51 - * 7:3 SYNT[4:0]: lowest bits of the PLL programmable divider. - * 2:0 BS[2:0]: Synthesizer band select. This parameter selects the out-of-loop divide factor of the synthesizer - * according to the formula fxo/(B/2)/D*SYNT/2^18 - * - * BS2 | BS1 | BS0 | value of B - * --------------------------------------------------------------------------- - * 0 | 0 | 1 | 6 - * 0 | 1 | 0 | 8 - * 0 | 1 | 1 | 12 - * 1 | 0 | 0 | 16 - * 1 | 0 | 1 | 32 - * - * \endcode - */ -#define SYNT0_BASE ((uint8_t)0x0B) /*!< [7:3] -> SYNT[4:0], lowest bits of the PLL programmable divider */ - -#define SYNT0_BS_6 ((uint8_t)0x01) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=6 (779-956MHz) */ -#define SYNT0_BS_8 ((uint8_t)0x02) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=8 (387-470MHz)*/ -#define SYNT0_BS_12 ((uint8_t)0x03) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=12 (387-470MHz)*/ -#define SYNT0_BS_16 ((uint8_t)0x04) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=16 (300-348MHz)*/ -#define SYNT0_BS_32 ((uint8_t)0x05) /*!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=32 (150-174MHz)*/ - -/** - * @} - */ - -/** @defgroup CHSPACE_Register - * @{ - */ - -/** - * \brief CHSPACE register - * \code - * Read Write - * Default value: 0xFC - * 7:0 CH_SPACING[7:0]: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps - * (in general, frequency step is fXO/215=26MHz/215~793Hz). - * - * \endcode - */ - -#define CHSPACE_BASE ((uint8_t)0x0C) /*!< Channel spacing. From ~0.8KHz to ~200KHz in (fXO/2^15)Hz (793Hz for 26MHz XO) steps */ - -/** - * @} - */ - - - -/** @defgroup IF_OFFSET_DIG_Register - * @{ - */ - -/** - * \brief IF_OFFSET_DIG register - * \code - * Read Write - * Default value: 0xA3 - * 7:0 IF_OFFSET_DIG[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz. - * - * \endcode - */ -#define IF_OFFSET_DIG_BASE ((uint8_t)0x0D) /*!< Intermediate frequency fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz */ - -/** - * @} - */ - -/** @defgroup IF_OFFSET_ANA_Register - * @{ - */ - -/** - * \brief IF_OFFSET_ANA register - * \code - * Read Write - * Default value: 0xA3 - * 7:0 IF_OFFSET_ANA[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz. - * - * \endcode - */ -#define IF_OFFSET_ANA_BASE ((uint8_t)0x07) /*!< Intermediate frequency fIF=fXO*(IF_OFFSET_ANA+64)/(12*2^10)=fCLK*(IF_OFFSET_DIG+64)/(12*2^10) Hz */ - - -/** - * @} - */ - -/** @defgroup FC_OFFSET1_Register - * @{ - */ - -/** - * \brief FC_OFFSET1 registers - * \code - * Read Write - * Default value: 0xA3 - * 7:4 Reserved. - * 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a 12-bit 2’s complement integer - * representing an offset in 99Hz(2) units added/subtracted to the - * carrier frequency set by registers SYNT3…SYNT0. - * This register can be used to set a fixed correction value - * obtained e.g. from crystal measurements. - * - * \endcode - */ -#define FC_OFFSET1_BASE ((uint8_t)0x0E) /*!< [3:0] -> [11:8] Carrier offset (upper part) */ - -/** - * @} - */ - - -/** @defgroup FC_OFFSET0_Register - * @{ - */ - -/** - * \brief FC_OFFSET0 registers - * \code - * Default value: 0x00 - * Read Write - * 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a 12-bit 2’s complement integer - * representing an offset in 99Hz(2) units added/subtracted to the - * carrier frequency set by registers SYNT3…SYNT0. - * This register can be used to set a fixed correction value - * obtained e.g. from crystal measurements. - * - * \endcode - */ -#define FC_OFFSET0_BASE ((uint8_t)0x0F) /*!< [7:0] -> [7:0] Carrier offset (lower part). This value is a 12-bit 2’s complement integer - representing an offset in fXO/2^18 (99Hz for 26 MHz XO) units added/subtracted to the carrier frequency - set by registers SYNT3…SYNT0. Range is +/-200kHz with 26 MHz XO */ -/** - * @} - */ - - -/** @defgroup PA_LEVEL_x_Registers - * @{ - */ - -/** - * \brief PA_POWER_x[8:1] registers - * \code - * Default values from 8 to 1: [0x03, 0x0E, 0x1A, 0x25, 0x35, 0x40, 0x4E, 0x00] - * Read Write - * - * 7 Reserved. - * 6:0 PA_LEVEL_(x-1)[6:0]: Output power level for x-th slot. - * \endcode - */ - -#define PA_POWER8_BASE ((uint8_t)0x10) /*!< PA Power level for 8th slot of PA ramping or ASK modulation */ -#define PA_POWER7_BASE ((uint8_t)0x11) /*!< PA Power level for 7th slot of PA ramping or ASK modulation */ -#define PA_POWER6_BASE ((uint8_t)0x12) /*!< PA Power level for 6th slot of PA ramping or ASK modulation */ -#define PA_POWER5_BASE ((uint8_t)0x13) /*!< PA Power level for 5th slot of PA ramping or ASK modulation */ -#define PA_POWER4_BASE ((uint8_t)0x14) /*!< PA Power level for 4th slot of PA ramping or ASK modulation */ -#define PA_POWER3_BASE ((uint8_t)0x15) /*!< PA Power level for 3rd slot of PA ramping or ASK modulation */ -#define PA_POWER2_BASE ((uint8_t)0x16) /*!< PA Power level for 2nd slot of PA ramping or ASK modulation */ -#define PA_POWER1_BASE ((uint8_t)0x17) /*!< PA Power level for 1st slot of PA ramping or ASK modulation */ - -/** - * @} - */ - -/** @defgroup PA_POWER_CONF_Registers - * @{ - */ - -/** - * \brief PA_POWER_CONF_Registers - * \code - * Default value:0x07 - * Read Write - * - * 7:6 CWC[1:0]: Output stage additional load capacitors bank (to be used to - * optimize the PA for different sub-bands). - * - * CWC1 | CWC0 | Total capacity in pF - * --------------------------------------------------------- - * 0 | 0 | 0 - * 0 | 1 | 1.2 - * 1 | 0 | 2.4 - * 1 | 1 | 3.6 - * - * 5 PA_RAMP_ENABLE: - * 1 - Enable the power ramping - * 0 - Disable the power ramping - * 4:3 PA_RAMP_STEP_WIDTH[1:0]: Step width in bit period - * - * PA_RAMP_STEP_WIDTH1 | PA_RAMP_STEP_WIDTH0 | PA ramping time step - * ------------------------------------------------------------------------------------------- - * 0 | 0 | 1/8 Bit period - * 0 | 1 | 2/8 Bit period - * 1 | 0 | 3/8 Bit period - * 1 | 1 | 4/8 Bit period - * - * 2:0 PA_LEVEL_MAX_INDEX[2:0]: Fixes the MAX PA LEVEL in PA ramping or ASK modulation - * - * \endcode - */ -#define PA_POWER0_BASE ((uint8_t)0x18) /*!< PA ramping settings and additional load capacitor banks used - for PA optimization in different sub bands*/ -#define PA_POWER0_CWC_MASK ((uint8_t)0x20) /*!< Output stage additional load capacitors bank */ -#define PA_POWER0_CWC_0 ((uint8_t)0x00) /*!< No additional PA load capacitor */ -#define PA_POWER0_CWC_1_2P ((uint8_t)0x40) /*!< 1.2pF additional PA load capacitor */ -#define PA_POWER0_CWC_2_4P ((uint8_t)0x80) /*!< 2.4pF additional PA load capacitor */ -#define PA_POWER0_CWC_3_6P ((uint8_t)0xC0) /*!< 3.6pF additional PA load capacitor */ -#define PA_POWER0_PA_RAMP_MASK ((uint8_t)0x20) /*!< The PA power ramping */ -#define PA_POWER0_PA_RAMP_STEP_WIDTH_MASK ((uint8_t)0x20) /*!< The step width */ -#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_8 ((uint8_t)0x00) /*!< PA ramping time step = 1/8 Bit period*/ -#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_4 ((uint8_t)0x08) /*!< PA ramping time step = 2/8 Bit period*/ -#define PA_POWER0_PA_RAMP_STEP_WIDTH_3TB_8 ((uint8_t)0x10) /*!< PA ramping time step = 3/8 Bit period*/ -#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_2 ((uint8_t)0x18) /*!< PA ramping time step = 4/8 Bit period*/ -#define PA_POWER0_PA_LEVEL_MAX_INDEX ((uint8_t)0x20) /*!< Final level for power ramping */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_0 ((uint8_t)0x00) /*!< */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_1 ((uint8_t)0x01) /*!< Fixes the MAX PA LEVEL in PA ramping or ASK modulation */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_2 ((uint8_t)0x02) /*!< */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_3 ((uint8_t)0x03) /*!< _________ */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_4 ((uint8_t)0x04) /*!< PA_LVL2 _| <--| */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_5 ((uint8_t)0x05) /*!< _| | */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_6 ((uint8_t)0x06) /*!< PA_LVL1 _| | */ -#define PA_POWER0_PA_LEVEL_MAX_INDEX_7 ((uint8_t)0x07) /*!< PA_LVL0 _| MAX_INDEX- */ - - - -/** - * @} - */ - - -/** @defgroup MOD1_Register - * @{ - */ - -/** - * \brief MOD1 register - * \code - * Read Write - * Default value: 0x83 - * 7:0 DATARATE_M[7:0]: The Mantissa of the specified data rate - * - * \endcode - */ -#define MOD1_BASE ((uint8_t)0x1A) /*!< The Mantissa of the specified data rate */ - -/** - * @} - */ - -/** @defgroup MOD0_Register - * @{ - */ - -/** - * \brief MOD0 register - * \code - * Read Write - * Default value: 0x1A - * 7 CW: 1 - CW Mode enabled - enables the generation of a continous wave carrier without any modulation - * 0 - CW Mode disabled - * - * 6 BT_SEL: Select BT value for GFSK - * 1 - BT=0.5 - * 0 - BT=1 - * - * 5:4 MOD_TYPE[1:0]: Modulation type - * - * - * MOD_TYPE1 | MOD_TYPE0 | Modulation - * --------------------------------------------------------- - * 0 | 0 | 2-FSK,MSK - * 0 | 1 | GFSK,GMSK - * 1 | 0 | ASK/OOK - * - * 3:0 DATARATE_E[3:0]: The Exponent of the specified data rate - * - * \endcode - */ -#define MOD0_BASE ((uint8_t)0x1B) /*!< Modulation Settings, Exponent of the specified data rate, CW mode*/ - -#define MOD0_MOD_TYPE_2_FSK ((uint8_t)0x00) /*!< Modulation type 2-FSK (MSK if the frequency deviation is identical to a quarter of the data rate) */ -#define MOD0_MOD_TYPE_GFSK ((uint8_t)0x10) /*!< Modulation type GFSK (GMSK if the frequency deviation is identical to a quarter of the data rate) */ -#define MOD0_MOD_TYPE_ASK ((uint8_t)0x20) /*!< Modulation type ASK (OOK the PA is switched off for symbol "0") */ -#define MOD0_MOD_TYPE_MSK ((uint8_t)0x00) /*!< Modulation type MSK (the frequency deviation must be identical to a quarter of the data rate) */ -#define MOD0_MOD_TYPE_GMSK ((uint8_t)0x10) /*!< Modulation type GMSK (the frequency deviation must be identical to a quarter of the data rate) */ -#define MOD0_BT_SEL_BT_MASK ((uint8_t)0x00) /*!< Select the BT = 1 or BT = 0.5 valid only for GFSK or GMSK modulation*/ -#define MOD0_CW ((uint8_t)0x80) /*!< Set the Continous Wave (no modulation) transmit mode */ - -/** - * @} - */ - - -/** @defgroup FDEV0_Register - * @{ - */ - -/** - * \brief FDEV0 register - * \code - * Read Write - * Default value: 0x45 - * 7:4 FDEV_E[3:0]: Exponent of the frequency deviation (allowed values from 0 to 9) - * - * 3 CLOCK_REC_ALGO_SEL: Select PLL or DLL mode for clock recovery - * 1 - DLL mode - * 0 - PLL mode - * - * 2:0 FDEV_M[1:0]: Mantissa of the frequency deviation (allowed values from 0 to 7) - * - * - * \endcode - */ -#define FDEV0_BASE ((uint8_t)0x1C) /*!< Sets the Mantissa and exponent of frequency deviation (frequency separation/2) - and PLL or DLL alogrithm from clock recovery in RX digital demod*/ -#define FDEV0_CLOCK_REG_ALGO_SEL_MASK ((uint8_t)0x08) /*!< Can be DLL or PLL algorithm for clock recovery in RX digital demod (see CLOCKREC reg) */ -#define FDEV0_CLOCK_REG_ALGO_SEL_PLL ((uint8_t)0x00) /*!< Sets PLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) */ -#define FDEV0_CLOCK_REG_ALGO_SEL_DLL ((uint8_t)0x08) /*!< Sets DLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) */ - -/** - * @} - */ - -/** @defgroup CHFLT_Register - * @{ - */ - -/** - * \brief CHFLT register - * \code - * Read Write - * Default value: 0x23 - * 7:4 CHFLT_M[3:0]: Mantissa of the channel filter BW (allowed values from 0 to 8) - * - * 3:0 CHFLT_E[3:0]: Exponent of the channel filter BW (allowed values from 0 to 9) - * - * M\E | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | - * -----+-------+-------+-------+-------+------+------+------+-----+-----+-----+ - * 0 | 800.1 | 450.9 | 224.7 | 112.3 | 56.1 | 28.0 | 14.0 | 7.0 | 3.5 | 1.8 | - * 1 | 795.1 | 425.9 | 212.4 | 106.2 | 53.0 | 26.5 | 13.3 | 6.6 | 3.3 | 1.7 | - * 2 | 768.4 | 403.2 | 201.1 | 100.5 | 50.2 | 25.1 | 12.6 | 6.3 | 3.1 | 1.6 | - * 3 | 736.8 | 380.8 | 190.0 | 95.0 | 47.4 | 23.7 | 11.9 | 5.9 | 3.0 | 1.5 | - * 4 | 705.1 | 362.1 | 180.7 | 90.3 | 45.1 | 22.6 | 11.3 | 5.6 | 2.8 | 1.4 | - * 5 | 670.9 | 341.7 | 170.6 | 85.3 | 42.6 | 21.3 | 10.6 | 5.3 | 2.7 | 1.3 | - * 6 | 642.3 | 325.4 | 162.4 | 81.2 | 40.6 | 20.3 | 10.1 | 5.1 | 2.5 | 1.3 | - * 7 | 586.7 | 294.5 | 147.1 | 73.5 | 36.7 | 18.4 | 9.2 | 4.6 | 2.3 | 1.2 | - * 8 | 541.4 | 270.3 | 135.0 | 67.5 | 33.7 | 16.9 | 8.4 | 4.2 | 2.1 | 1.1 | - * - * \endcode - */ -#define CHFLT_BASE ((uint8_t)0x1D) /*!< RX Channel Filter Bandwidth */ - -#define CHFLT_800_1 ((uint8_t)0x00) /*!< RX Channel Filter Bandwidth = 800.1 kHz */ -#define CHFLT_795_1 ((uint8_t)0x10) /*!< RX Channel Filter Bandwidth = 795.1 kHz */ -#define CHFLT_768_4 ((uint8_t)0x20) /*!< RX Channel Filter Bandwidth = 768.4 kHz */ -#define CHFLT_736_8 ((uint8_t)0x30) /*!< RX Channel Filter Bandwidth = 736.8 kHz */ -#define CHFLT_705_1 ((uint8_t)0x40) /*!< RX Channel Filter Bandwidth = 705.1 kHz */ -#define CHFLT_670_9 ((uint8_t)0x50) /*!< RX Channel Filter Bandwidth = 670.9 kHz */ -#define CHFLT_642_3 ((uint8_t)0x60) /*!< RX Channel Filter Bandwidth = 642.3 kHz */ -#define CHFLT_586_7 ((uint8_t)0x70) /*!< RX Channel Filter Bandwidth = 586.7 kHz */ -#define CHFLT_541_4 ((uint8_t)0x80) /*!< RX Channel Filter Bandwidth = 541.4 kHz */ -#define CHFLT_450_9 ((uint8_t)0x01) /*!< RX Channel Filter Bandwidth = 450.9 kHz */ -#define CHFLT_425_9 ((uint8_t)0x11) /*!< RX Channel Filter Bandwidth = 425.9 kHz */ -#define CHFLT_403_2 ((uint8_t)0x21) /*!< RX Channel Filter Bandwidth = 403.2 kHz */ -#define CHFLT_380_8 ((uint8_t)0x31) /*!< RX Channel Filter Bandwidth = 380.8 kHz */ -#define CHFLT_362_1 ((uint8_t)0x41) /*!< RX Channel Filter Bandwidth = 362.1 kHz */ -#define CHFLT_341_7 ((uint8_t)0x51) /*!< RX Channel Filter Bandwidth = 341.7 kHz */ -#define CHFLT_325_4 ((uint8_t)0x61) /*!< RX Channel Filter Bandwidth = 325.4 kHz */ -#define CHFLT_294_5 ((uint8_t)0x71) /*!< RX Channel Filter Bandwidth = 294.5 kHz */ -#define CHFLT_270_3 ((uint8_t)0x81) /*!< RX Channel Filter Bandwidth = 270.3 kHz */ -#define CHFLT_224_7 ((uint8_t)0x02) /*!< RX Channel Filter Bandwidth = 224.7 kHz */ -#define CHFLT_212_4 ((uint8_t)0x12) /*!< RX Channel Filter Bandwidth = 212.4 kHz */ -#define CHFLT_201_1 ((uint8_t)0x22) /*!< RX Channel Filter Bandwidth = 201.1 kHz */ -#define CHFLT_190 ((uint8_t)0x32) /*!< RX Channel Filter Bandwidth = 190.0 kHz */ -#define CHFLT_180_7 ((uint8_t)0x42) /*!< RX Channel Filter Bandwidth = 180.7 kHz */ -#define CHFLT_170_6 ((uint8_t)0x52) /*!< RX Channel Filter Bandwidth = 170.6 kHz */ -#define CHFLT_162_4 ((uint8_t)0x62) /*!< RX Channel Filter Bandwidth = 162.4 kHz */ -#define CHFLT_147_1 ((uint8_t)0x72) /*!< RX Channel Filter Bandwidth = 147.1 kHz */ -#define CHFLT_135 ((uint8_t)0x82) /*!< RX Channel Filter Bandwidth = 135.0 kHz */ -#define CHFLT_112_3 ((uint8_t)0x03) /*!< RX Channel Filter Bandwidth = 112.3 kHz */ -#define CHFLT_106_2 ((uint8_t)0x13) /*!< RX Channel Filter Bandwidth = 106.2 kHz */ -#define CHFLT_100_5 ((uint8_t)0x23) /*!< RX Channel Filter Bandwidth = 100.5 kHz */ -#define CHFLT_95 ((uint8_t)0x33) /*!< RX Channel Filter Bandwidth = 95.0 kHz */ -#define CHFLT_90_3 ((uint8_t)0x43) /*!< RX Channel Filter Bandwidth = 90.3 kHz */ -#define CHFLT_85_3 ((uint8_t)0x53) /*!< RX Channel Filter Bandwidth = 85.3 kHz */ -#define CHFLT_81_2 ((uint8_t)0x63) /*!< RX Channel Filter Bandwidth = 81.2 kHz */ -#define CHFLT_73_5 ((uint8_t)0x73) /*!< RX Channel Filter Bandwidth = 73.5 kHz */ -#define CHFLT_67_5 ((uint8_t)0x83) /*!< RX Channel Filter Bandwidth = 67.5 kHz */ -#define CHFLT_56_1 ((uint8_t)0x04) /*!< RX Channel Filter Bandwidth = 56.1 kHz */ -#define CHFLT_53 ((uint8_t)0x14) /*!< RX Channel Filter Bandwidth = 53.0 kHz */ -#define CHFLT_50_2 ((uint8_t)0x24) /*!< RX Channel Filter Bandwidth = 50.2 kHz */ -#define CHFLT_47_4 ((uint8_t)0x34) /*!< RX Channel Filter Bandwidth = 47.4 kHz */ -#define CHFLT_45_1 ((uint8_t)0x44) /*!< RX Channel Filter Bandwidth = 45.1 kHz */ -#define CHFLT_42_6 ((uint8_t)0x54) /*!< RX Channel Filter Bandwidth = 42.6 kHz */ -#define CHFLT_40_6 ((uint8_t)0x64) /*!< RX Channel Filter Bandwidth = 40.6 kHz */ -#define CHFLT_36_7 ((uint8_t)0x74) /*!< RX Channel Filter Bandwidth = 36.7 kHz */ -#define CHFLT_33_7 ((uint8_t)0x84) /*!< RX Channel Filter Bandwidth = 33.7 kHz */ -#define CHFLT_28 ((uint8_t)0x05) /*!< RX Channel Filter Bandwidth = 28.0 kHz */ -#define CHFLT_26_5 ((uint8_t)0x15) /*!< RX Channel Filter Bandwidth = 26.5 kHz */ -#define CHFLT_25_1 ((uint8_t)0x25) /*!< RX Channel Filter Bandwidth = 25.1 kHz */ -#define CHFLT_23_7 ((uint8_t)0x35) /*!< RX Channel Filter Bandwidth = 23.7 kHz */ -#define CHFLT_22_6 ((uint8_t)0x45) /*!< RX Channel Filter Bandwidth = 22.6 kHz */ -#define CHFLT_21_3 ((uint8_t)0x55) /*!< RX Channel Filter Bandwidth = 21.3 kHz */ -#define CHFLT_20_3 ((uint8_t)0x65) /*!< RX Channel Filter Bandwidth = 20.3 kHz */ -#define CHFLT_18_4 ((uint8_t)0x75) /*!< RX Channel Filter Bandwidth = 18.4 kHz */ -#define CHFLT_16_9 ((uint8_t)0x85) /*!< RX Channel Filter Bandwidth = 16.9 kHz */ -#define CHFLT_14 ((uint8_t)0x06) /*!< RX Channel Filter Bandwidth = 14.0 kHz */ -#define CHFLT_13_3 ((uint8_t)0x16) /*!< RX Channel Filter Bandwidth = 13.3 kHz */ -#define CHFLT_12_6 ((uint8_t)0x26) /*!< RX Channel Filter Bandwidth = 12.6 kHz */ -#define CHFLT_11_9 ((uint8_t)0x36) /*!< RX Channel Filter Bandwidth = 11.9 kHz */ -#define CHFLT_11_3 ((uint8_t)0x46) /*!< RX Channel Filter Bandwidth = 11.3 kHz */ -#define CHFLT_10_6 ((uint8_t)0x56) /*!< RX Channel Filter Bandwidth = 10.6 kHz */ -#define CHFLT_10_1 ((uint8_t)0x66) /*!< RX Channel Filter Bandwidth = 10.1 kHz */ -#define CHFLT_9_2 ((uint8_t)0x76) /*!< RX Channel Filter Bandwidth = 9.2 kHz */ -#define CHFLT_8_4 ((uint8_t)0x86) /*!< RX Channel Filter Bandwidth = 8.4 kHz */ -#define CHFLT_7 ((uint8_t)0x07) /*!< RX Channel Filter Bandwidth = 7.0 kHz */ -#define CHFLT_6_6 ((uint8_t)0x17) /*!< RX Channel Filter Bandwidth = 6.6 kHz */ -#define CHFLT_6_3 ((uint8_t)0x27) /*!< RX Channel Filter Bandwidth = 6.3 kHz */ -#define CHFLT_5_9 ((uint8_t)0x37) /*!< RX Channel Filter Bandwidth = 5.9 kHz */ -#define CHFLT_5_6 ((uint8_t)0x47) /*!< RX Channel Filter Bandwidth = 5.6 kHz */ -#define CHFLT_5_3 ((uint8_t)0x57) /*!< RX Channel Filter Bandwidth = 5.3 kHz */ -#define CHFLT_5_1 ((uint8_t)0x67) /*!< RX Channel Filter Bandwidth = 5.1 kHz */ -#define CHFLT_4_6 ((uint8_t)0x77) /*!< RX Channel Filter Bandwidth = 4.6 kHz */ -#define CHFLT_4_2 ((uint8_t)0x87) /*!< RX Channel Filter Bandwidth = 4.2 kHz */ -#define CHFLT_3_5 ((uint8_t)0x08) /*!< RX Channel Filter Bandwidth = 3.5 kHz */ -#define CHFLT_3_3 ((uint8_t)0x18) /*!< RX Channel Filter Bandwidth = 3.3 kHz */ -#define CHFLT_3_1 ((uint8_t)0x28) /*!< RX Channel Filter Bandwidth = 3.1 kHz */ -#define CHFLT_3 ((uint8_t)0x38) /*!< RX Channel Filter Bandwidth = 3.0 kHz */ -#define CHFLT_2_8 ((uint8_t)0x48) /*!< RX Channel Filter Bandwidth = 2.8 kHz */ -#define CHFLT_2_7 ((uint8_t)0x58) /*!< RX Channel Filter Bandwidth = 2.7 kHz */ -#define CHFLT_2_5 ((uint8_t)0x68) /*!< RX Channel Filter Bandwidth = 2.5 kHz */ -#define CHFLT_2_3 ((uint8_t)0x78) /*!< RX Channel Filter Bandwidth = 2.3 kHz */ -#define CHFLT_2_1 ((uint8_t)0x88) /*!< RX Channel Filter Bandwidth = 2.1 kHz */ -#define CHFLT_1_8 ((uint8_t)0x09) /*!< RX Channel Filter Bandwidth = 1.8 kHz */ -#define CHFLT_1_7 ((uint8_t)0x19) /*!< RX Channel Filter Bandwidth = 1.7 kHz */ -#define CHFLT_1_6 ((uint8_t)0x29) /*!< RX Channel Filter Bandwidth = 1.6 kHz */ -#define CHFLT_1_5 ((uint8_t)0x39) /*!< RX Channel Filter Bandwidth = 1.5 kHz */ -#define CHFLT_1_4 ((uint8_t)0x49) /*!< RX Channel Filter Bandwidth = 1.4 kHz */ -#define CHFLT_1_3a ((uint8_t)0x59) /*!< RX Channel Filter Bandwidth = 1.3 kHz */ -#define CHFLT_1_3 ((uint8_t)0x69) /*!< RX Channel Filter Bandwidth = 1.3 kHz */ -#define CHFLT_1_2 ((uint8_t)0x79) /*!< RX Channel Filter Bandwidth = 1.2 kHz */ -#define CHFLT_1_1 ((uint8_t)0x89) /*!< RX Channel Filter Bandwidth = 1.1 kHz */ - -/** - * @} - */ - -/** @defgroup AFC2_Register - * @{ - */ - -/** - * \brief AFC2 register - * \code - * Read Write - * Default value: 0x48 - * 7 AFC Freeze on Sync: Freeze AFC correction upon sync word detection. - * 1 - AFC Freeze enabled - * 0 - AFC Freeze disabled - * - * 6 AFC Enabled: Enable AFC - * 1 - AFC enabled - * 0 - AFC disabled - * - * 5 AFC Mode: Select AFC mode - * 1 - AFC Loop closed on 2nd conversion stage. - * 0 - AFC Loop closed on slicer - * - * 4:0 AFC PD leakage[4:0]: Peak detector leakage. This parameter sets the decay speed of the min/max frequency peak detector (AFC2 register), - * the range allowed is 0..31 (0 - no leakage, 31 - high leakage). The recommended value for this parameter is 4. - * - * \endcode - */ -#define AFC2_BASE ((uint8_t)0x1E) /*!< Automatic frequency compensation algorithm parameters (FSK/GFSK/MSK)*/ - -#define AFC2_AFC_FREEZE_ON_SYNC_MASK ((uint8_t)0x80) /*!< The frequency correction value is frozen when SYNC word is detected */ -#define AFC2_AFC_MASK ((uint8_t)0x40) /*!< Mask of Automatic Frequency Correction */ -#define AFC2_AFC_MODE_MASK ((uint8_t)0x20) /*!< Automatic Frequency Correction can be in Main MODE or Auxiliary MODE*/ -#define AFC2_AFC_MODE_SLICER ((uint8_t)0x00) /*!< Automatic Frequency Correction Main MODE */ -#define AFC2_AFC_MODE_MIXER ((uint8_t)0x20) /*!< Automatic Frequency Correction Auxiliary MODE */ - -/** - * @} - */ - -/** @defgroup AFC1_Register - * @{ - */ - -/** - * \brief AFC1 register - * \code - * Read Write - * Default value: 0x18 - * 7:0 AFC_FAST_PERIOD: Length of the AFC fast period. this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed - * is 0..255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the - * algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble - * symbols. - * - * \endcode - */ -#define AFC1_BASE ((uint8_t)0x1F) /*!< Length of the AFC fast period */ - -/** - * @} - */ - -/** @defgroup AFC0_Register - * @{ - */ - -/** - * \brief AFC0 register - * \code - * Read Write - * Default value: 0x25 - * 7:4 AFC_FAST_GAIN_LOG2[3:0]: AFC loop gain in fast mode (2's log) - * - * 3:0 AFC_SLOW_GAIN_LOG2[3:0]: AFC loop gain in slow mode (2's log) - * - * \endcode - */ -#define AFC0_BASE ((uint8_t)0x20) /*!< AFC loop gain in fast and slow modes (2's log) */ - -/** - * @} - */ - -/** @defgroup CLOCKREC_Register - * @{ - */ - -/** - * \brief CLOCKREC register - * \code - * Read Write - * Default value: 0x58 - * - * 7:5 CLK_REC_P_GAIN [2:0]: Clock recovery loop gain (log2) - * - * 4 PSTFLT_LEN: Set Postfilter length - * 1 - 16 symbols - * 0 - 8 symbols - * - * 3:0 CLK_REC_I_GAIN[3:0]: Integral gain for the clock recovery loop - * \endcode - */ - -#define CLOCKREC_BASE ((uint8_t)0x23) /*!< Gain of clock recovery loop - Postfilter length 0-8 symbols, 1-16 symbols */ - -/** - * @} - */ - -/** @defgroup AGCCTRL2_Register - * @{ - */ - -/** - * \brief AGCCTRL2 register - * \code - * Read Write - * Default value: 0x22 - * - * 7 Reserved - * - * 6 FREEZE_ON_STEADY: Enable freezing on steady state - * 1 - Enable - * 0 - Disable - * - * 5 FREEZE_ON_SYNC: Enable freezing on sync detection - * 1 - Enable - * 0 - Disable - * - * 4 START_MAX_ATTENUATION: Start with max attenuation - * 1 - Enable - * 0 - Disable - * - * 3:0 MEAS_TIME[3:0]: Measure time during which the signal peak is detected (according to the formula 12/fxo*2^MEAS_TIME) - * \endcode - */ -#define AGCCTRL2_BASE ((uint8_t)0x24) /*!< AGC freeze strategy, AGC attenuation strategy, AGC measure time */ - -#define AGCCTRL2_FREEZE_ON_STEADY_MASK ((uint8_t)0x40) /*!< The attenuation settings will be frozen as soon as signal level - is betweeen min and max treshold (see AGCCTRL1) */ -#define AGCCTRL2_FREEZE_ON_SYNC_MASK ((uint8_t)0x20) /*!< The attenuation settings will be frozen as soon sync word is detected */ -#define AGCCTRL2_START_MAX_ATTENUATION_MASK ((uint8_t)0x10) /*!< The AGC algorithm can start with MAX attenuation or MIN attenuation */ - -/** - * @} - */ - -/** @defgroup AGCCTRL1_Register - * @{ - */ - -/** - * \brief AGCCTRL1 register - * \code - * Read Write - * Default value: 0x65 - * - * 7:4 THRESHOLD_HIGH[3:0]: High threshold for the AGC - * - * 3:0 THRESHOLD_LOW[3:0]: Low threshold for the AGC - * \endcode - */ -#define AGCCTRL1_BASE ((uint8_t)0x25) /*!< Sets low and high threshold for AGC */ - -/** - * @} - */ - -/** @defgroup AGCCTRL0_Register - * @{ - */ - -/** - * \brief AGCCTRL0 register - * \code - * Read Write - * Default value: 0x8A - * - * 7 AGC S_ENABLE: Enable AGC - * 1 - Enable - * 0 - Disable - * - * 6 AGC_MODE: Set linear-Binary AGC mode - * 1 - Enable - * 0 - Disable - * - * 5:0 HOLD_TIME[5:0]: Hold time after gain adjustment according to formula 12/fxo*HOLD_TIME - * \endcode - */ -#define AGCCTRL0_BASE ((uint8_t)0x26) /*!< Enables AGC, set AGC algo between linear/binary mode, set hold time - to account signal propagation through RX chain */ -#define AGCCTRL0_AGC_MASK ((uint8_t)0x80) /*!< AGC on/off */ -#define AGCCTRL0_AGC_MODE_MASK ((uint8_t)0x40) /*!< AGC search correct attenuation in binary mode or sequential mode */ -#define AGCCTRL0_AGC_MODE_LINEAR ((uint8_t)0x00) /*!< AGC search correct attenuation in sequential mode (recommended) */ -#define AGCCTRL0_AGC_MODE_BINARY ((uint8_t)0x40) /*!< AGC search correct attenuation in binary mode */ - -/** - * @} - */ - -/** @defgroup CHNUM_Register - * @{ - */ - -/** - * \brief CHNUM registers - * \code - * Default value: 0x00 - * Read Write - * 7:0 CH_NUM[7:0]: Channel number. This value is multiplied by the channel spacing and added to the - * synthesizer base frequency to generate the actual RF carrier frequency. - * \endcode - */ -#define CHNUM_BASE ((uint8_t)0x6C) /*!< Channel number. This value is multiplied by the channel - spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency */ -/** - * @} - */ - -/** @defgroup AFC_CORR_Register - * @{ - */ - -/** - * \brief AFC_CORR registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 AFC_CORR[7:0]: AFC word of the received packet - * \endcode - */ -#define AFC_CORR_BASE ((uint8_t)(0xC4)) /*!< AFC word of the received packet */ - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup Packet_Configuration_Registers - * @{ - */ - -/** @defgroup PCKTCTRL4_Register - * @{ - */ - -/** - * \brief PCKTCTRL4 register - * \code - * Read Write - * Default value: 0x00 - * - * 7:5 NOT_USED. - * - * 4:3 ADDRESS_LEN[1:0]: length of address field in bytes - * - * 2:0 control_len[2:0]: length of control field in bytes - * \endcode - */ -#define PCKTCTRL4_BASE ((uint8_t)0x30) /*!< lenghts of address and control field */ - -#define PCKTCTRL4_ADDRESS_LEN_MASK ((uint8_t)0x18) -#define PCKTCTRL4_CONTROL_LEN_MASK ((uint8_t)0x07) - -/** - * @} - */ - -/** @defgroup PCKTCTRL3_Register - * @{ - */ - -/** - * \brief PCKTCTRL3 register - * \code - * Read Write - * Default value: 0x07 - * - * 7:6 PCKT_FRMT[1:0]: format of packet - * - * PCKT_FRMT1 | PCKT_FRMT0 | Format - * ---------------------------------------------------------------------- - * 0 | 0 | BASIC - * 1 | 0 | MBUS - * 1 | 1 | STACK - * - * 5:4 RX_MODE[1:0]: length of address 0x30 field in bytes - * - * RX_MODE1 | RX_MODE0 | Rx Mode - * -------------------------------------------------------------------- - * 0 | 0 | normal - * 0 | 1 | direct through FIFO - * 1 | 0 | direct through GPIO - * - * 3:0 LEN_WID[3:0]: length of length field in bits - * \endcode - */ -#define PCKTCTRL3_BASE ((uint8_t)0x31) /*!< packet format, RX mode, lenght of length field */ - -#define PCKTCTRL3_PCKT_FRMT_BASIC ((uint8_t)0x00) /*!< Basic Packet Format */ -#define PCKTCTRL3_PCKT_FRMT_MBUS ((uint8_t)0x80) /*!< Wireless M-BUS Packet Format */ -#define PCKTCTRL3_PCKT_FRMT_STACK ((uint8_t)0xC0) /*!< STack Packet Format */ - -#define PCKTCTRL3_RX_MODE_NORMAL ((uint8_t)0x00) /*!< Normal RX Mode */ -#define PCKTCTRL3_RX_MODE_DIRECT_FIFO ((uint8_t)0x10) /*!< RX Direct Mode; data available through FIFO */ -#define PCKTCTRL3_RX_MODE_DIRECT_GPIO ((uint8_t)0x20) /*!< RX Direct Mode; data available through selected GPIO */ - -#define PCKTCTRL3_PKT_FRMT_MASK ((uint8_t)0xC0) -#define PCKTCTRL3_RX_MODE_MASK ((uint8_t)0x30) -#define PCKTCTRL3_LEN_WID_MASK ((uint8_t)0x0F) - -/** - * @} - */ - -/** @defgroup PCKTCTRL2_Register - * @{ - */ - -/** - * \brief PCKTCTRL2 register - * \code - * Read Write - * Default value: 0x1E - * - * 7:3 PREAMBLE_LENGTH[4:0]: length of preamble field in bytes (0..31) - * - * - * 2:1 SYNC_LENGTH[1:0]: length of sync field in bytes - * - * - * 0 FIX_VAR_LEN: fixed/variable packet length - * 1 - Variable - * 0 - Fixed - * \endcode - */ -#define PCKTCTRL2_BASE ((uint8_t)0x32) /*!< length of preamble and sync fields (in bytes), fix or variable packet length */ - -#define PCKTCTRL2_FIX_VAR_LEN_MASK ((uint8_t)0x01) /*!< Enable/disable the length mode */ -#define PCKTCTRL2_PREAMBLE_LENGTH_MASK ((uint8_t)0xF8) -#define PCKTCTRL2_SYNC_LENGTH_MASK ((uint8_t)0x06) - -/** - * @} - */ - -/** @defgroup PCKTCTRL1_Register - * @{ - */ - -/** - * \brief PCKTCTRL1 register - * \code - * Read Write - * Default value: 0x20 - * - * 7:5 CRC_MODE[2:0]: CRC type (0, 8, 16, 24 bits) - * - * CRC_MODE2 | CRC_MODE1 | CRC_MODE0 | CRC Mode (n. bits - poly) - * ------------------------------------------------------------------------------------------------- - * 0 | 0 | 1 | 8 - 0x07 - * 0 | 1 | 0 | 16 - 0x8005 - * 0 | 1 | 1 | 16 - 0x1021 - * 1 | 0 | 0 | 24 - 0x864CBF - * - * 4 WHIT_EN[0]: Enable Whitening - * 1 - Enable - * 0 - Disable - * - * 3:2 TX_SOURCE[1:0]: length of sync field in bytes - * - * TX_SOURCE1 | TX_SOURCE0 | Tx Mode - * -------------------------------------------------------------------- - * 0 | 0 | normal - * 0 | 1 | direct through FIFO - * 1 | 0 | direct through GPIO - * 1 | 1 | pn9 - * - * 1 NOT_USED - * - * 0 FEC_EN: enable FEC - * 1 - FEC in TX , Viterbi decoding in RX - * 0 - Disabled - * \endcode - */ -#define PCKTCTRL1_BASE ((uint8_t)0x33) /*!< CRC type, whitening enable, TX mode */ - -#define PCKTCTRL1_FEC_MASK ((uint8_t)0x01) /*!< Enable/disable the Forward Error Correction */ -#define PCKTCTRL1_TX_SOURCE_MASK ((uint8_t)0x0C) /*!< TX source mode */ -#define PCKTCTRL1_CRC_MODE_MASK ((uint8_t)0xE0) /*!< CRC type */ -#define PCKTCTRL1_WHIT_MASK ((uint8_t)0x10) /*!< Enable/disable the Whitening */ - -/** - * @} - */ - - - -/** @defgroup PCKTLEN1_Register - * @{ - */ - -/** - * \brief PCKTLEN1 register - * \code - * Read Write - * Default value: 0x00 - * - * 7:0 pktlen1[7:0]: lenght of packet in bytes (upper field) LENGHT/256 - * \endcode - */ -#define PCKTLEN1_BASE ((uint8_t)0x34) /*!< lenght of packet in bytes (upper field) */ - -/** - * @} - */ - -/** @defgroup PCKTLEN0_Register - * @{ - */ - -/** - * \brief PCKTLEN0 register - * \code - * Read Write - * Default value: 0x14 - * - * 7:0 pktlen0[7:0]: lenght of packet in bytes (lower field) LENGHT%256 - * \endcode - */ -#define PCKTLEN0_BASE ((uint8_t)0x35) /*!< lenght of packet in bytes (lower field) [PCKTLEN=PCKTLEN1x256+PCKTLEN0]*/ - -/** - * @} - */ - -/** @defgroup SYNCx_Registers - * @{ - */ -/** - * \brief SYNCx[4:1] Registers - * \code - * Read Write - * Default value: 0x88 - * - * 7:0 SYNCx[7:0]: xth sync word - * \endcode - */ -#define SYNC4_BASE ((uint8_t)0x36) /*!< Sync word 4 */ -#define SYNC3_BASE ((uint8_t)0x37) /*!< Sync word 3 */ -#define SYNC2_BASE ((uint8_t)0x38) /*!< Sync word 2 */ -#define SYNC1_BASE ((uint8_t)0x39) /*!< Sync word 1 */ - -/** - * @} - */ - - -/** @defgroup MBUS_PRMBL_Register - * @{ - */ - -/** - * \brief MBUS_PRMBL register - * \code - * Read Write - * Default value: 0x20 - * - * 7:0 MBUS_PRMBL[7:0]: MBUS preamble control - * \endcode - */ -#define MBUS_PRMBL_BASE ((uint8_t)0x3B) /*!< MBUS preamble lenght (in 01 bit pairs) */ - -/** - * @} - */ - - -/** @defgroup MBUS_PSTMBL_Register - * @{ - */ - -/** - * \brief MBUS_PSTMBL register - * \code - * Read Write - * Default value: 0x20 - * - * 7:0 MBUS_PSTMBL[7:0]: MBUS postamble control - * \endcode - */ -#define MBUS_PSTMBL_BASE ((uint8_t)0x3C) /*!< MBUS postamble length (in 01 bit pairs) */ - -/** - * @} - */ - -/** @defgroup MBUS_CTRL_Register - * @{ - */ - -/** - * \brief MBUS_CTRL register - * \code - * Read Write - * Default value: 0x00 - * - * 7:4 NOT_USED - * - * 3:1 MBUS_SUBMODE[2:0]: MBUS submode (allowed values are 0,1,3,5) - * - * 0 NOT_USED - * \endcode - */ -#define MBUS_CTRL_BASE ((uint8_t)0x3D) /*!< MBUS sub-modes (S1, S2 short/long header, T1, T2, R2) */ - -#define MBUS_CTRL_MBUS_SUBMODE_S1_S2L ((uint8_t)0x00) /*!< MBUS sub-modes S1 & S2L, header lenght min 279, sync 0x7696, Manchester */ -#define MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER ((uint8_t)0x02) /*!< MBUS sub-modes S2, S1-m, T2 (only other to meter) short header, header lenght min 15, sync 0x7696, Manchester */ -#define MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER ((uint8_t)0x06) /*!< MBUS sub-modes T1, T2 (only meter to other), header lenght min 19, sync 0x3D, 3 out of 6 */ -#define MBUS_CTRL_MBUS_SUBMODE_R2 ((uint8_t)0x0A) /*!< MBUS sub-mode R2, header lenght min 39, sync 0x7696, Manchester */ - -/** - * @} - */ - - - -/** @defgroup PCKT_FLT_GOALS_CONTROLx_MASK_Registers - * @{ - */ - -/** - * \brief PCKT_FLT_GOALS_CONTROLx_MASK registers - * \code - * Default value: 0x00 - * Read Write - * 7:0 CONTROLx_MASK[7:0]: All 0s - no filtering - * - * \endcode - */ -#define PCKT_FLT_GOALS_CONTROL0_MASK_BASE ((uint8_t)0x42) /*!< Packet control field #3 mask, all 0s -> no filtering */ - -#define PCKT_FLT_GOALS_CONTROL1_MASK_BASE ((uint8_t)0x43) /*!< Packet control field #2 mask, all 0s -> no filtering */ - -#define PCKT_FLT_GOALS_CONTROL2_MASK_BASE ((uint8_t)0x44) /*!< Packet control field #1 mask, all 0s -> no filtering */ - -#define PCKT_FLT_GOALS_CONTROL3_MASK_BASE ((uint8_t)0x45) /*!< Packet control field #0 mask, all 0s -> no filtering */ - -/** - * @} - */ - -/** @defgroup PCKT_FLT_GOALS_CONTROLx_FIELD_Registers - * @{ - */ - -/** - * \brief PCKT_FLT_GOALS_CONTROLx_FIELD registers - * \code - * Default value: 0x00 - * Read Write - * 7:0 CONTROLx_FIELD[7:0]: Control field (byte x) to be used as reference - * - * \endcode - */ -#define PCKT_FLT_GOALS_CONTROL0_FIELD_BASE ((uint8_t)0x46) /*!< Control field (byte #3) */ - -#define PCKT_FLT_GOALS_CONTROL1_FIELD_BASE ((uint8_t)0x47) /*!< Control field (byte #2) */ - -#define PCKT_FLT_GOALS_CONTROL2_FIELD_BASE ((uint8_t)0x48) /*!< Control field (byte #1) */ - -#define PCKT_FLT_GOALS_CONTROL3_FIELD_BASE ((uint8_t)0x49) /*!< Control field (byte #0) */ - -/** - * @} - */ - -/** @defgroup PCKT_FLT_GOALS_SOURCE_MASK_Register - * @{ - */ - -/** - * \brief PCKT_FLT_GOALS_SOURCE_MASK register - * \code - * Default value: 0x00 - * Read Write - * 7:0 RX_SOURCE_MASK[7:0]: For received packet only: all 0s - no filtering - * - * \endcode - */ -#define PCKT_FLT_GOALS_SOURCE_MASK_BASE ((uint8_t)0x4A) /*!< Source address mask, valid in RX mode */ - -/** - * @} - */ - -/** @defgroup PCKT_FLT_GOALS_SOURCE_ADDR_Register - * @{ - */ -/** - * \brief PCKT_FLT_GOALS_SOURCE_ADDR register - * \code - * Default value: 0x00 - * Read Write - * 7:0 RX_SOURCE_ADDR[7:0]: RX packet source / TX packet destination fields - * - * \endcode - */ -#define PCKT_FLT_GOALS_SOURCE_ADDR_BASE ((uint8_t)0x4B) /*!< Source address */ - -/** - * @} - */ - -/** @defgroup PCKT_FLT_GOALS_BROADCAST_Register - * @{ - */ - -/** - * \brief PCKT_FLT_GOALS_BROADCAST register - * \code - * Default value: 0x00 - * Read Write - * 7:0 BROADCAST[7:0]: Address shared for broadcast communication link - * - * \endcode - */ -#define PCKT_FLT_GOALS_BROADCAST_BASE ((uint8_t)0x4C) /*!< Address shared for broadcast communication links */ - -/** - * @} - */ - -/** @defgroup PCKT_FLT_GOALS_MULTICAST_Register - * @{ - */ - -/** - * \brief PCKT_FLT_GOALS_MULTICAST register - * \code - * Default value: 0x00 - * Read Write - * 7:0 MULTICAST[7:0]: Address shared for multicast communication links - * - * \endcode - */ -#define PCKT_FLT_GOALS_MULTICAST_BASE ((uint8_t)0x4D) /*!< Address shared for multicast communication links */ - -/** - * @} - */ - -/** @defgroup PCKT_FLT_GOALS_TX_SOURCE_ADDR_Register - * @{ - */ - -/** - * \brief PCKT_FLT_GOALS_TX_SOURCE_ADDR register - * \code - * Default value: 0x00 - * Read Write - * 7:0 TX_SOURCE_ADDR[7:0]: TX packet source / RX packet destination fields - * - * \endcode - */ -#define PCKT_FLT_GOALS_TX_ADDR_BASE ((uint8_t)0x4E) /*!< Address of the destination (also device own address) */ - -/** - * @} - */ - -/** @defgroup PCKT_FLT_OPTIONS_Register - * @{ - */ - -/** - * \brief PCKT_FLT_OPTIONS register - * \code - * Default value: 0x70 - * Read Write - * 7 Reserved. - * - * 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - ‘OR’ logical function applied to CS/SQI/PQI - * values (masked by 7:5 bits in PROTOCOL register) - * 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control fields matches - * with masked CONTROLx_FIELD registers. - * 4 SOURCE_FILTERING[0]: 1 - RX packet accepted if its source field - * matches w/ masked RX_SOURCE_ADDR register. - * 3 DEST_VS_ SOURCE _ADDR[0]: 1 - RX packet accepted if its destination - * address matches with TX_SOURCE_ADDR reg. - * 2 DEST_VS_MULTICAST_ADDR[0]: 1 - RX packet accepted if its destination - * address matches with MULTICAST register - * 1 DEST_VS_BROADCAST_ADDR[0]: 1 - RX packet accepted if its destination - * address matches with BROADCAST register. - * 0 CRC_CHECK[0]: 1 - packet discarded if CRC not valid. - * - * \endcode - */ -#define PCKT_FLT_OPTIONS_BASE ((uint8_t)0x4F) /*!< Options relative to packet filtering */ - -#define PCKT_FLT_OPTIONS_CRC_CHECK_MASK ((uint8_t)0x01) /*!< Enable/disable of CRC check: packet is discarded if CRC is not valid [RX] */ -#define PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK ((uint8_t)0x02) /*!< Packet discarded if destination address differs from BROADCAST register [RX] */ -#define PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK ((uint8_t)0x04) /*!< Packet discarded if destination address differs from MULTICAST register [RX] */ -#define PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK ((uint8_t)0x08) /*!< Packet discarded if destination address differs from TX_ADDR register [RX] */ -#define PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK ((uint8_t)0x10) /*!< Packet discarded if source address (masked by the SOURCE_MASK register) - differs from SOURCE_ADDR register [RX] */ -#define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20) /*!< Packet discarded if the x-byte (x=1¸4) control field (masked by the CONTROLx_MASK register) - differs from CONTROLx_FIELD register [RX] */ -#define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40) /*!< Logical function applied to CS/SQI/PQI values (masked by [7:5] bits in PROTOCOL[2] - register) */ - -/** - * @} - */ - -/** @defgroup TX_CTRL_FIELD_Registers - * @{ - */ - -/** - * \brief TX_CTRL_FIELDx registers - * \code - * Default value: 0x00 - * Read Write - * 7:0 TX_CTRLx[7:0]: Control field value to be used in TX packet as byte n.x - * \endcode - */ -#define TX_CTRL_FIELD3_BASE ((uint8_t)0x68) /*!< Control field value to be used in TX packet as byte n.3 */ - -#define TX_CTRL_FIELD2_BASE ((uint8_t)0x69) /*!< Control field value to be used in TX packet as byte n.2 */ - -#define TX_CTRL_FIELD1_BASE ((uint8_t)0x6A) /*!< Control field value to be used in TX packet as byte n.1 */ - -#define TX_CTRL_FIELD0_BASE ((uint8_t)0x6B) /*!< Control field value to be used in TX packet as byte n.0 */ - -/** - * @} - */ - - -/** @defgroup TX_PCKT_INFO_Register - * @{ - */ - -/** - * \brief TX_PCKT_INFO registers - * \code - * Default value: 0x00 - * Read - * - * 7:6 Not used. - * - * 5:4 TX_SEQ_NUM: Current TX packet sequence number - * - * 0 N_RETX[3:0]: Number of retransmissions done on the - * last TX packet - * \endcode - */ -#define TX_PCKT_INFO_BASE ((uint8_t)(0xC2)) /*!< Current TX packet sequence number [5:4]; - Number of retransmissions done on the last TX packet [3:0]*/ -/** - * @} - */ - -/** @defgroup RX_PCKT_INFO_Register - * @{ - */ - -/** - * \brief RX_PCKT_INFO registers - * \code - * Default value: 0x00 - * Read - * - * 7:3 Not used. - * - * 2 NACK_RX: NACK field of the received packet - * - * 1:0 RX_SEQ_NUM[1:0]: Sequence number of the received packet - * \endcode - */ -#define RX_PCKT_INFO_BASE ((uint8_t)(0xC3)) /*!< NO_ACK field of the received packet [2]; - sequence number of the received packet [1:0]*/ - -#define TX_PCKT_INFO_NACK_RX ((uint8_t)(0x04)) /*!< NACK field of the received packet */ - -/** - * @} - */ - -/** @defgroup RX_PCKT_LEN1 - * @{ - */ - -/** - * \brief RX_PCKT_LEN1 registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 - * This value is packet_length/256 - * \endcode - */ -#define RX_PCKT_LEN1_BASE ((uint8_t)(0xC9)) /*!< Length (number of bytes) of the received packet: */ - -/** - * @} - */ - -/** @defgroup RX_PCKT_LEN0 - * @{ - */ - -/** - * \brief RX_PCKT_LEN0 registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 - * This value is packet_length%256 - * \endcode - */ -#define RX_PCKT_LEN0_BASE ((uint8_t)(0xCA)) /*!< RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 */ - -/** - * @} - */ - - -/** @defgroup CRC_FIELD_Register - * @{ - */ - -/** - * \brief CRC_FIELD[2:0] registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 CRC_FIELDx[7:0]: upper(x=2), middle(x=1) and lower(x=0) part of the crc field of the received packet - * \endcode - */ -#define CRC_FIELD2_BASE ((uint8_t)(0xCB)) /*!< CRC2 field of the received packet */ - -#define CRC_FIELD1_BASE ((uint8_t)(0xCC)) /*!< CRC1 field of the received packet */ - -#define CRC_FIELD0_BASE ((uint8_t)(0xCD)) /*!< CRC0 field of the received packet */ - -/** - * @} - */ - -/** @defgroup RX_CTRL_FIELD_Register - * @{ - */ - -/** - * \brief RX_CTRL_FIELD[3:0] registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 RX_CTRL_FIELDx[7:0]: upper(x=3), middle(x=2), middle(x=1) and lower(x=0) part of the control field of the received packet - * \endcode - */ -#define RX_CTRL_FIELD0_BASE ((uint8_t)(0xCE)) /*!< CRTL3 Control field of the received packet */ - -#define RX_CTRL_FIELD1_BASE ((uint8_t)(0xCF)) /*!< CRTL2 Control field of the received packet */ - -#define RX_CTRL_FIELD2_BASE ((uint8_t)(0xD0)) /*!< CRTL1 Control field of the received packet */ - -#define RX_CTRL_FIELD3_BASE ((uint8_t)(0xD1)) /*!< CRTL0 Control field of the received packet */ - -/** - * @} - */ - -/** @defgroup RX_ADDR_FIELD_Register - * @{ - */ - -/** - * \brief RX_ADDR_FIELD[1:0] registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 RX_ADDR_FIELDx[7:0]: source(x=1) and destination(x=0) address field of the received packet - * \endcode - */ -#define RX_ADDR_FIELD1_BASE ((uint8_t)(0xD2)) /*!< ADDR1 Address field of the received packet */ - -#define RX_ADDR_FIELD0_BASE ((uint8_t)(0xD3)) /*!< ADDR0 Address field of the received packet */ - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup Protocol_Registers - * @{ - */ - -/** @defgroup PROTOCOL2_Register - * @{ - */ - -/** - * \brief PROTOCOL2 register - * \code - * Default value: 0x06 - * Read Write - * 7 CS_TIMEOUT_MASK: 1 - CS value contributes to timeout disabling - * - * 6 SQI_TIMEOUT_MASK: 1 - SQI value contributes to timeout disabling - * - * 5 PQI_TIMEOUT_MASK: 1 - PQI value contributes to timeout disabling - * - * 4:3 TX_SEQ_NUM_RELOAD[1:0]: TX sequence number to be used when counting reset is required using the related command. - * - * 2 RCO_CALIBRATION[0]: 1 - Enables the automatic RCO calibration - * - * 1 VCO_CALIBRATION[0]: 1 - Enables the automatic VCO calibration - * - * 0 LDCR_MODE[0]: 1 - LDCR mode enabled - * - * \endcode - */ -#define PROTOCOL2_BASE ((uint8_t)0x50) /*!< Protocol2 regisetr address */ - -#define PROTOCOL2_LDC_MODE_MASK ((uint8_t)0x01) /*!< Enable/disable Low duty Cycle mode */ -#define PROTOCOL2_VCO_CALIBRATION_MASK ((uint8_t)0x02) /*!< Enable/disable VCO automatic calibration */ -#define PROTOCOL2_RCO_CALIBRATION_MASK ((uint8_t)0x04) /*!< Enable/disable RCO automatic calibration */ -#define PROTOCOL2_PQI_TIMEOUT_MASK ((uint8_t)0x20) /*!< PQI value contributes to timeout disabling */ -#define PROTOCOL2_SQI_TIMEOUT_MASK ((uint8_t)0x40) /*!< SQI value contributes to timeout disabling */ -#define PROTOCOL2_CS_TIMEOUT_MASK ((uint8_t)0x80) /*!< CS value contributes to timeout disabling */ - -/** - * @} - */ - -/** @defgroup PROTOCOL1_Register - * @{ - */ - -/** - * \brief PROTOCOL1 register - * \code - * Default value: 0x00 - * Read Write - * 7 LDCR_RELOAD_ON_SYNC: 1 - LDCR timer will be reloaded with the value stored in the LDCR_RELOAD registers - * - * 6 PIGGYBACKING: 1 - PIGGYBACKING enabled - * - * 5:4 Reserved. - * - * 3 SEED_RELOAD[0]: 1 - Reload the back-off random generator - * seed using the value written in the - * BU_COUNTER_SEED_MSByte / LSByte registers - * - * 2 CSMA_ON [0]: 1 - CSMA channel access mode enabled - * - * 1 CSMA_PERS_ON[0]: 1 - CSMA persistent (no back-off) enabled - * - * 0 AUTO_PCKT_FLT[0]: 1 - automatic packet filtering mode enabled - * - * \endcode - */ -#define PROTOCOL1_BASE ((uint8_t)0x51) /*!< Protocol1 regisetr address */ - -#define PROTOCOL1_AUTO_PCKT_FLT_MASK ((uint8_t)0x01) /*!< Enable/disable automatic packet filtering mode */ -#define PROTOCOL1_CSMA_PERS_ON_MASK ((uint8_t)0x02) /*!< Enable/disable CSMA persistent (no back-off) */ -#define PROTOCOL1_CSMA_ON_MASK ((uint8_t)0x04) /*!< Enable/disable CSMA channel access mode */ -#define PROTOCOL1_SEED_RELOAD_MASK ((uint8_t)0x08) /*!< Reloads the seed of the PN generator for CSMA procedure */ -#define PROTOCOL1_PIGGYBACKING_MASK ((uint8_t)0x40) /*!< Enable/disable Piggybacking */ -#define PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK ((uint8_t)0x80) /*!< LDC timer will be reloaded with the value stored in the LDC_RELOAD registers */ - -/** - * @} - */ - -/** @defgroup PROTOCOL0_Register - * @{ - */ - -/** - * \brief PROTOCOL0 register - * \code - * Default value: 0x08 - * Read Write - * 7:4 NMAX_RETX[3:0]: Max number of re-TX. 0 - re-transmission is not performed - * - * 3 NACK_TX[0]: 1 - field NO_ACK=1 on transmitted packet - * - * 2 AUTO_ACK[0]: 1 - automatic ack after RX - * - * 1 PERS_RX[0]: 1 - persistent reception enabled - * - * 0 PERS_TX[0]: 1 - persistent transmission enabled - * - * \endcode - */ -#define PROTOCOL0_BASE ((uint8_t)0x52) /*!< Persistent RX/TX, autoack, Max number of retransmissions */ - -#define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /*!< Enables persistent transmission */ -#define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /*!< Enables persistent reception */ -#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /*!< Enables auto acknowlegment */ -#define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /*!< Writes field NO_ACK=1 on transmitted packet */ -#define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xF0) /*!< Retransmission mask */ - -/** - * @} - */ - -/** @defgroup TIMERS5_Register - * @{ - */ - -/** - * \brief TIMERS5 register - * \code - * Default value: 0x00 - * Read Write - * 7:0 RX_TIMEOUT_PRESCALER[7:0] : RX operation timeout: prescaler value - * \endcode - */ -#define TIMERS5_RX_TIMEOUT_PRESCALER_BASE ((uint8_t)0x53) /*!< RX operation timeout: prescaler value */ - -/** - * @} - */ - -/** @defgroup TIMERS4_Register - * @{ - */ - -/** - * \brief TIMERS4 register - * \code - * Default value: 0x00 - * Read Write - * 7:0 RX_TIMEOUT_COUNTER[7:0] : RX operation timeout: counter value - * \endcode - */ -#define TIMERS4_RX_TIMEOUT_COUNTER_BASE ((uint8_t)0x54) /*!< RX operation timeout: counter value */ - -/** - * @} - */ - -/** @defgroup TIMERS3_Register - * @{ - */ - -/** - * \brief TIMERS3 register - * \code - * Default value: 0x00 - * Read Write - * 7:0 LDCR_PRESCALER[7:0] : LDC Mode: Prescaler part of the wake-up value - * \endcode - */ -#define TIMERS3_LDC_PRESCALER_BASE ((uint8_t)0x55) /*!< LDC Mode: Prescaler of the wake-up timer */ - -/** - * @} - */ - -/** @defgroup TIMERS2_Register - * @{ - */ - -/** - * \brief TIMERS2 register - * \code - * Default value: 0x00 - * Read Write - * 7:0 LDCR_COUNTER[7:0] : LDC Mode: counter part of the wake-up value - * \endcode - */ -#define TIMERS2_LDC_COUNTER_BASE ((uint8_t)0x56) /*!< LDC Mode: counter of the wake-up timer */ - -/** - * @} - */ - -/** @defgroup TIMERS1_Register - * @{ - */ - -/** - * \brief TIMERS1 register - * \code - * Default value: 0x00 - * Read Write - * 7:0 LDCR_RELOAD_PRESCALER[7:0] : LDC Mode: Prescaler part of the reload value - * \endcode - */ -#define TIMERS1_LDC_RELOAD_PRESCALER_BASE ((uint8_t)0x57) /*!< LDC Mode: Prescaler part of the reload value */ - -/** - * @} - */ - -/** @defgroup TIMERS0_Register - * @{ - */ - -/** - * \brief TIMERS0 register - * \code - * Default value: 0x00 - * Read Write - * 7:0 LDCR_RELOAD_COUNTER[7:0] : LDC Mode: Counter part of the reload value - * \endcode - */ -#define TIMERS0_LDC_RELOAD_COUNTER_BASE ((uint8_t)0x58) /*!< LDC Mode: Counter part of the reload value */ - -/** - * @} - */ - - -/** @defgroup CSMA_CONFIG3_Register - * @{ - */ - -/** - * \brief CSMA_CONFIG3 registers - * \code - * Default value: 0xFF - * Read Write - * 7:0 BU_COUNTER_SEED_MSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) - * \endcode - */ -#define CSMA_CONFIG3_BASE ((uint8_t)0x64) /*!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) */ - -/** - * @} - */ - -/** @defgroup CSMA_CONFIG2_Register - * @{ - */ - -/** - * \brief CSMA_CONFIG2 registers - * \code - * Default value: 0x00 - * Read Write - * 7:0 BU_COUNTER_SEED_LSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) - * \endcode - */ -#define CSMA_CONFIG2_BASE ((uint8_t)0x65) /*!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) */ - -/** - * @} - */ - -/** @defgroup CSMA_CONFIG1_Register - * @{ - */ - -/** - * \brief CSMA_CONFIG1 registers - * \code - * Default value: 0x04 - * Read Write - * 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU - * - * 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time (64 / 128 /256 / 512 × Tbit. - * \endcode - */ -#define CSMA_CONFIG1_BASE ((uint8_t)0x66) /*!< CSMA/CA: Prescaler of the back-off time unit (BU); CCA period */ - -#define CSMA_CCA_PERIOD_64TBIT ((uint8_t)0x00) /*!< CSMA/CA: Sets CCA period to 64*TBIT */ -#define CSMA_CCA_PERIOD_128TBIT ((uint8_t)0x01) /*!< CSMA/CA: Sets CCA period to 128*TBIT */ -#define CSMA_CCA_PERIOD_256TBIT ((uint8_t)0x02) /*!< CSMA/CA: Sets CCA period to 256*TBIT */ -#define CSMA_CCA_PERIOD_512TBIT ((uint8_t)0x03) /*!< CSMA/CA: Sets CCA period to 512*TBIT */ - -/** - * @} - */ - -/** @defgroup CSMA_CONFIG0_Register - * @{ - */ - -/** - * \brief CSMA_CONFIG0 registers - * \code - * Default value: 0x00 - * Read Write - * 7:4 CCA_LENGTH[3:0]: Used to program the Tlisten time - * - * 3 Reserved. - * - * 2:0 NBACKOFF_MAX[2:0]: Max number of back-off cycles. - * \endcode - */ -#define CSMA_CONFIG0_BASE ((uint8_t)0x67) /*!< CSMA/CA: CCA lenght; Max number of backoff cycles */ - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup Link_Quality_Registers - * @{ - */ - -/** @defgroup QI_Register - * @{ - */ - -/** - * \brief QI register - * \code - * Read Write - * Default value: 0x02 - * - * 7:6 SQI_TH[1:0]: SQI threshold according to the formula: 8*SYNC_LEN - 2*SQI_TH - * - * 5:2 PQI_TH[3:0]: PQI threshold according to the formula: 4*PQI_THR - * - * - * 1 SQI_EN[0]: SQI enable - * 1 - Enable - * 0 - Disable - * - * 0 PQI_EN[0]: PQI enable - * 1 - Enable - * 0 - Disable - * \endcode - */ -#define QI_BASE ((uint8_t)0x3A) /*!< QI register */ - -#define QI_PQI_MASK ((uint8_t)0x01) /*!< PQI enable/disable */ -#define QI_SQI_MASK ((uint8_t)0x02) /*!< SQI enable/disable */ - -/** - * @} - */ - -/** @defgroup LINK_QUALIF2 - * @{ - */ - -/** - * \brief LINK_QUALIF2 registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 PQI[7:0]: PQI value of the received packet - * \endcode - */ -#define LINK_QUALIF2_BASE ((uint8_t)(0xC5)) /*!< PQI value of the received packet */ - -/** - * @} - */ - -/** @defgroup LINK_QUALIF1 - * @{ - */ - -/** - * \brief LINK_QUALIF1 registers - * \code - * Default value: 0x00 - * Read - * - * 7 CS: Carrier Sense indication - * - * 6:0 SQI[6:0]: SQI value of the received packet - * \endcode - */ -#define LINK_QUALIF1_BASE ((uint8_t)(0xC6)) /*!< Carrier sense indication [7]; SQI value of the received packet */ - -#define LINK_QUALIF1_CS ((uint8_t)(0x80)) /*!< Carrier sense indication [7] */ - -/** - * @} - */ - -/** @defgroup LINK_QUALIF0 - * @{ - */ - -/** - * \brief LINK_QUALIF0 registers - * \code - * Default value: 0x00 - * Read - * - * 7:4 LQI [3:0]: LQI value of the received packet - * - * 3:0 AGC_WORD[3:0]: AGC word of the received packet - * \endcode - */ -#define LINK_QUALIF0_BASE ((uint8_t)(0xC7)) /*!< LQI value of the received packet [7:4]; AGC word of the received packet [3:0] */ - -/** - * @} - */ - -/** @defgroup RSSI_LEVEL - * @{ - */ - -/** - * \brief RSSI_LEVEL registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 RSSI_LEVEL[7:0]: RSSI level of the received packet - * \endcode - */ -#define RSSI_LEVEL_BASE ((uint8_t)(0xC8)) /*!< RSSI level of the received packet */ - -/** - * @} - */ - -/** @defgroup RSSI_FLT_Register - * @{ - */ - -/** - * \brief RSSI register - * \code - * Read Write - * Default value: 0xF3 - * 7:4 RSSI_FLT[3:0]: Gain of the RSSI filter - * - * 3:2 CS_MODE[1:0]: AFC loop gain in slow mode (2's log) - * - * CS_MODE1 | CS_MODE0 | CS Mode - * ----------------------------------------------------------------------------------------- - * 0 | 0 | Static CS - * 0 | 1 | Dynamic CS with 6dB dynamic threshold - * 1 | 0 | Dynamic CS with 12dB dynamic threshold - * 1 | 1 | Dynamic CS with 18dB dynamic threshold - * - * 1:0 OOK_PEAK_DECAY[1:0]: Peak decay control for OOK: 3 slow decay; 0 fast decay - * - * \endcode - */ -#define RSSI_FLT_BASE ((uint8_t)0x21) /*!< Gain of the RSSI filter; lower value is fast but inaccurate, - higher value is slow and more accurate */ -#define RSSI_FLT_CS_MODE_MASK ((uint8_t)0x0C) /*!< Carrier sense mode mask */ -#define RSSI_FLT_CS_MODE_STATIC ((uint8_t)0x00) /*!< Carrier sense mode; static carrier sensing */ -#define RSSI_FLT_CS_MODE_DYNAMIC_6 ((uint8_t)0x04) /*!< Carrier sense mode; dynamic carrier sensing with 6dB threshold */ -#define RSSI_FLT_CS_MODE_DYNAMIC_12 ((uint8_t)0x08) /*!< Carrier sense mode; dynamic carrier sensing with 12dB threshold */ -#define RSSI_FLT_CS_MODE_DYNAMIC_18 ((uint8_t)0x0C) /*!< Carrier sense mode; dynamic carrier sensing with 18dB threshold */ -#define RSSI_FLT_OOK_PEAK_DECAY_MASK ((uint8_t)0x03) /*!< Peak decay control for OOK mask */ -#define RSSI_FLT_OOK_PEAK_DECAY_FAST ((uint8_t)0x00) /*!< Peak decay control for OOK: fast decay */ -#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_FAST ((uint8_t)0x01) /*!< Peak decay control for OOK: medium_fast decay */ -#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_SLOW ((uint8_t)0x02) /*!< Peak decay control for OOK: medium_fast decay */ -#define RSSI_FLT_OOK_PEAK_DECAY_SLOW ((uint8_t)0x03) /*!< Peak decay control for OOK: slow decay */ - -/** - * @} - */ - -/** @defgroup RSSI_TH_Register - * @{ - */ - -/** - * \brief RSSI_TH register - * \code - * Read Write - * Default value: 0x24 - * - * 7:0 RSSI_THRESHOLD [7:0]: Signal detect threshold in 0.5dB. -120dBm corresponds to 20 - * \endcode - */ -#define RSSI_TH_BASE ((uint8_t)0x22) /*!< Signal detect threshold in 0.5dB stp. 20 correspond to -120 dBm */ - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup FIFO_Registers - * @{ - */ - -/** @defgroup FIFO_CONFIG3_Register - * @{ - */ - -/** - * \brief FIFO_CONFIG3 registers - * \code - * Default value: 0x30 - * Read Write - * 7 Reserved. - * - * 6:0 rxafthr [6:0]: FIFO Almost Full threshold for rx fifo. - * - * \endcode - */ -#define FIFO_CONFIG3_RXAFTHR_BASE ((uint8_t)0x3E) /*!< FIFO Almost Full threshold for rx fifo [6:0] */ - -/** - * @} - */ - -/** @defgroup FIFO_CONFIG2_Register - * @{ - */ - -/** - * \brief FIFO_CONFIG2 registers - * \code - * Default value: 0x30 - * Read Write - * 7 Reserved. - * - * 6:0 rxaethr [6:0]: FIFO Almost Empty threshold for rx fifo. - * - * \endcode - */ -#define FIFO_CONFIG2_RXAETHR_BASE ((uint8_t)0x3F) /*!< FIFO Almost Empty threshold for rx fifo [6:0] */ - -/** - * @} - */ - -/** @defgroup FIFO_CONFIG1_Register - * @{ - */ - -/** - * \brief FIFO_CONFIG1 registers - * \code - * Default value: 0x30 - * Read Write - * 7 Reserved. - * - * 6:0 txafthr [6:0]: FIFO Almost Full threshold for tx fifo. - * - * \endcode - */ -#define FIFO_CONFIG1_TXAFTHR_BASE ((uint8_t)0x40) /*!< FIFO Almost Full threshold for tx fifo [6:0] */ - -/** - * @} - */ - -/** @defgroup FIFO_CONFIG0_Register - * @{ - */ - -/** - * \brief FIFO_CONFIG0 registers - * \code - * Default value: 0x30 - * Read Write - * 7 Reserved. - * - * 6:0 txaethr [6:0]: FIFO Almost Empty threshold for tx fifo. - * - * \endcode - */ -#define FIFO_CONFIG0_TXAETHR_BASE ((uint8_t)0x41) /*!< FIFO Almost Empty threshold for tx fifo [6:0] */ - -/** - * @} - */ - -/** @defgroup LINEAR_FIFO_STATUS1_Register - * @{ - */ - -/** - * \brief LINEAR_FIFO_STATUS1 registers - * \code - * Default value: 0x00 - * Read - * - * 7 Reserved. - * - * 6:0 elem_txfifo[6:0]: Number of elements in the linear TXFIFO (<=96) - * \endcode - */ -#define LINEAR_FIFO_STATUS1_BASE ((uint8_t)(0xE6)) /*!< Number of elements in the linear TX FIFO [6:0] (<=96) */ - -/** - * @} - */ - -/** @defgroup LINEAR_FIFO_STATUS0_Register - * @{ - */ - -/** - * \brief LINEAR_FIFO_STATUS0 registers - * \code - * Default value: 0x00 - * Read - * - * 7 Reserved. - * - * 6:0 elem_rxfifo[6:0]: Number of elements in the linear RXFIFO (<=96) - * \endcode - */ -#define LINEAR_FIFO_STATUS0_BASE ((uint8_t)(0xE7)) /*!< Number of elements in the linear RX FIFO [6:0] (<=96) */ - -/** - * @} - */ - - -/** - * @} - */ - - -/** @defgroup Calibration_Registers - * @{ - */ - -/** @defgroup RCO_VCO_CALIBR_IN2_Register - * @{ - */ - -/** - * \brief RCO_VCO_CALIBR_IN2 registers - * \code - * Default value: 0x70 - * Read Write - * 7:4 RWT_IN[3:0]: RaWThermometric word value for the RCO [7:4] - * - * 3:0 RFB_IN[4:1]: ResistorFineBit word value for the RCO (first 4 bits) - * \endcode - */ -#define RCO_VCO_CALIBR_IN2_BASE ((uint8_t)0x6D) /*!< RaWThermometric word value for the RCO [7:4]; ResistorFineBit word value for the RCO [3:0] */ - -/** - * @} - */ - -/** @defgroup RCO_VCO_CALIBR_IN1_Register - * @{ - */ - -/** - * \brief RCO_VCO_CALIBR_IN1 registers - * \code - * Default value: 0x48 - * Read Write - * - * 7 RFB_IN[0]: ResistorFineBit word value for the RCO (LSb) - * - * 6:0 VCO_CALIBR_TX[6:0]: Word value for the VCO to be used in TX mode - * \endcode - */ -#define RCO_VCO_CALIBR_IN1_BASE ((uint8_t)0x6E) /*!< ResistorFineBit word value for the RCO [7]; Word value for the VCO to be used in TX mode [6:0]*/ - -/** - * @} - */ - -/** @defgroup RCO_VCO_CALIBR_IN0_Register - * @{ - */ - -/** - * \brief RCO_VCO_CALIBR_IN0 registers - * \code - * Default value: 0x48 - * Read Write - * - * 7 Reserved. - * - * 6:0 VCO_CALIBR_RX[6:0]: Word value for the VCO to be used in RX mode - * \endcode - */ -#define RCO_VCO_CALIBR_IN0_BASE ((uint8_t)0x6F) /*!< Word value for the VCO to be used in RX mode [6:0] */ - -/** - * @} - */ - -/** @defgroup RCO_VCO_CALIBR_OUT1_Register - * @{ - */ - -/** - * \brief RCO_VCO_CALIBR_OUT1 registers - * \code - * Default value: 0x00 - * Read - * - * 7:4 RWT_OUT[3:0]: RWT word from internal RCO calibrator - * - * 3:0 RFB_OUT[4:1]: RFB word from internal RCO calibrator (upper part) - * \endcode - */ -#define RCO_VCO_CALIBR_OUT1_BASE ((uint8_t)(0xE4)) /*!< RaWThermometric RWT word from internal RCO calibrator [7]; - ResistorFineBit RFB word from internal RCO oscillator [6:0] */ -/** - * @} - */ - -/** @defgroup RCO_VCO_CALIBR_OUT0_Register - * @{ - */ - -/** - * \brief RCO_VCO_CALIBR_OUT0 registers - * \code - * Default value: 0x00 - * Read - * - * 7 RFB_OUT[0]: RFB word from internal RCO calibrator (last bit LSB) - * - * 6:0 VCO_CALIBR_DATA[6:0]: Output word from internal VCO calibrator - * \endcode - */ -#define RCO_VCO_CALIBR_OUT0_BASE ((uint8_t)(0xE5)) /*!< ResistorFineBit RFB word from internal RCO oscillator [0]; - Output word from internal calibrator [6:0]; */ -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup AES_Registers - * @{ - */ - -/** @defgroup AES_KEY_IN_Register - * @{ - */ - -/** - * \brief AES_KEY_INx registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 AES_KEY_INx[7:0]: AES engine key input (total - 128 bits) - * \endcode - */ -#define AES_KEY_IN_15_BASE ((uint8_t)0x70) /*!< AES engine key input 15 */ - -#define AES_KEY_IN_14_BASE ((uint8_t)0x71) /*!< AES engine key input 14 */ - -#define AES_KEY_IN_13_BASE ((uint8_t)0x72) /*!< AES engine key input 13 */ - -#define AES_KEY_IN_12_BASE ((uint8_t)0x73) /*!< AES engine key input 12 */ - -#define AES_KEY_IN_11_BASE ((uint8_t)0x74) /*!< AES engine key input 11 */ - -#define AES_KEY_IN_10_BASE ((uint8_t)0x75) /*!< AES engine key input 10 */ - -#define AES_KEY_IN_9_BASE ((uint8_t)0x76) /*!< AES engine key input 9 */ - -#define AES_KEY_IN_8_BASE ((uint8_t)0x77) /*!< AES engine key input 8 */ - -#define AES_KEY_IN_7_BASE ((uint8_t)0x78) /*!< AES engine key input 7 */ - -#define AES_KEY_IN_6_BASE ((uint8_t)0x79) /*!< AES engine key input 6 */ - -#define AES_KEY_IN_5_BASE ((uint8_t)0x7A) /*!< AES engine key input 5 */ - -#define AES_KEY_IN_4_BASE ((uint8_t)0x7B) /*!< AES engine key input 4 */ - -#define AES_KEY_IN_3_BASE ((uint8_t)0x7C) /*!< AES engine key input 3 */ - -#define AES_KEY_IN_2_BASE ((uint8_t)0x7D) /*!< AES engine key input 2 */ - -#define AES_KEY_IN_1_BASE ((uint8_t)0x7E) /*!< AES engine key input 1 */ - -#define AES_KEY_IN_0_BASE ((uint8_t)0x7F) /*!< AES engine key input 0 */ - -/** - * @} - */ - -/** @defgroup AES_DATA_IN_Register - * @{ - */ - -/** - * \brief AES_DATA_INx registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 AES_DATA_INx[7:0]: AES engine data input (total - 128 bits) - * \endcode - */ -#define AES_DATA_IN_15_BASE ((uint8_t)0x80) /*!< AES engine data input 15 - Take care: Address is in reverse order respect data numbering; eg.: 0x81 -> AES_data14[7:0] */ -#define AES_DATA_IN_14_BASE ((uint8_t)0x81) /*!< AES engine data input 14 */ - -#define AES_DATA_IN_13_BASE ((uint8_t)0x82) /*!< AES engine data input 13 */ - -#define AES_DATA_IN_12_BASE ((uint8_t)0x83) /*!< AES engine data input 12 */ - -#define AES_DATA_IN_11_BASE ((uint8_t)0x84) /*!< AES engine data input 11 */ - -#define AES_DATA_IN_10_BASE ((uint8_t)0x85) /*!< AES engine data input 10 */ - -#define AES_DATA_IN_9_BASE ((uint8_t)0x86) /*!< AES engine data input 9 */ - -#define AES_DATA_IN_8_BASE ((uint8_t)0x87) /*!< AES engine data input 8 */ - -#define AES_DATA_IN_7_BASE ((uint8_t)0x88) /*!< AES engine data input 7 */ - -#define AES_DATA_IN_6_BASE ((uint8_t)0x89) /*!< AES engine data input 6 */ - -#define AES_DATA_IN_5_BASE ((uint8_t)0x8A) /*!< AES engine data input 5 */ - -#define AES_DATA_IN_4_BASE ((uint8_t)0x8B) /*!< AES engine data input 4 */ - -#define AES_DATA_IN_3_BASE ((uint8_t)0x8C) /*!< AES engine data input 3 */ - -#define AES_DATA_IN_2_BASE ((uint8_t)0x8D) /*!< AES engine data input 2 */ - -#define AES_DATA_IN_1_BASE ((uint8_t)0x8E) /*!< AES engine data input 1 */ - -#define AES_DATA_IN_0_BASE ((uint8_t)0x8F) /*!< AES engine data input 0 */ - -/** - * @} - */ - -/** @defgroup AES_DATA_OUT_Register - * @{ - */ - -/** - * \brief AES_DATA_OUT[15:0] registers - * \code - * Default value: 0x00 - * Read - * - * 7:0 AES_DATA_OUTx[7:0]: AES engine data output (128 bits) - * \endcode - */ -#define AES_DATA_OUT_15_BASE ((uint8_t)(0xD4)) /*!< AES engine data output 15 */ - -#define AES_DATA_OUT_14_BASE ((uint8_t)(0xD5)) /*!< AES engine data output 14 */ - -#define AES_DATA_OUT_13_BASE ((uint8_t)(0xD6)) /*!< AES engine data output 13 */ - -#define AES_DATA_OUT_12_BASE ((uint8_t)(0xD7)) /*!< AES engine data output 12 */ - -#define AES_DATA_OUT_11_BASE ((uint8_t)(0xD8)) /*!< AES engine data output 11 */ - -#define AES_DATA_OUT_10_BASE ((uint8_t)(0xD9)) /*!< AES engine data output 10 */ - -#define AES_DATA_OUT_9_BASE ((uint8_t)(0xDA)) /*!< AES engine data output 9 */ - -#define AES_DATA_OUT_8_BASE ((uint8_t)(0xDB)) /*!< AES engine data output 8 */ - -#define AES_DATA_OUT_7_BASE ((uint8_t)(0xDC)) /*!< AES engine data output 7 */ - -#define AES_DATA_OUT_6_BASE ((uint8_t)(0xDD)) /*!< AES engine data output 6 */ - -#define AES_DATA_OUT_5_BASE ((uint8_t)(0xDE)) /*!< AES engine data output 5 */ - -#define AES_DATA_OUT_4_BASE ((uint8_t)(0xDF)) /*!< AES engine data output 4 */ - -#define AES_DATA_OUT_3_BASE ((uint8_t)(0xE0)) /*!< AES engine data output 3 */ - -#define AES_DATA_OUT_2_BASE ((uint8_t)(0xE1)) /*!< AES engine data output 2 */ - -#define AES_DATA_OUT_1_BASE ((uint8_t)(0xE2)) /*!< AES engine data output 1 */ - -#define AES_DATA_OUT_0_BASE ((uint8_t)(0xE3)) /*!< AES engine data output 0 */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IRQ_Registers - * @{ - */ - -/** @defgroup IRQ_MASK0_Register - * @{ - */ - -/** - * \brief IRQ_MASK0 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_MASK0: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 0 | RX data ready - * 1 | RX data discarded (upon filtering) - * 2 | TX data sent - * 3 | Max re-TX reached - * 4 | CRC error - * 5 | TX FIFO underflow/overflow error - * 6 | RX FIFO underflow/overflow error - * 7 | TX FIFO almost full - * \endcode - */ - - -#define IRQ_MASK0_BASE ((uint8_t)0x93) /*!< IRQ_MASK is split into 4 registers*/ - -#define IRQ_MASK0_RX_DATA_READY ((uint8_t)0x01) /*!< IRQ: RX data ready */ -#define IRQ_MASK0_RX_DATA_DISC ((uint8_t)0x02) /*!< IRQ: RX data discarded (upon filtering) */ -#define IRQ_MASK0_TX_DATA_SENT ((uint8_t)0x04) /*!< IRQ: TX data sent */ -#define IRQ_MASK0_MAX_RE_TX_REACH ((uint8_t)0x08) /*!< IRQ: Max re-TX reached */ -#define IRQ_MASK0_CRC_ERROR ((uint8_t)0x10) /*!< IRQ: CRC error */ -#define IRQ_MASK0_TX_FIFO_ERROR ((uint8_t)0x20) /*!< IRQ: TX FIFO underflow/overflow error */ -#define IRQ_MASK0_RX_FIFO_ERROR ((uint8_t)0x40) /*!< IRQ: RX FIFO underflow/overflow error */ -#define IRQ_MASK0_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /*!< IRQ: TX FIFO almost full */ - -/** - * @} - */ - -/** @defgroup IRQ_MASK1_Register - * @{ - */ - -/** - * \brief IRQ_MASK1 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_MASK1: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 8 | TX FIFO almost empty - * 9 | RX FIFO almost full - * 10 | RX FIFO almost empty - * 11 | Max number of back-off during CCA - * 12 | Valid preamble detected - * 13 | Sync word detected - * 14 | RSSI above threshold (Carrier Sense) - * 15 | Wake-up timeout in LDCR mode13 - * \endcode - */ - -#define IRQ_MASK1_BASE ((uint8_t)0x92) /*!< IRQ_MASK is split into 4 registers*/ - -#define IRQ_MASK1_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /*!< IRQ: TX FIFO almost empty */ -#define IRQ_MASK1_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /*!< IRQ: RX FIFO almost full */ -#define IRQ_MASK1_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /*!< IRQ: RX FIFO almost empty */ -#define IRQ_MASK1_MAX_BO_CCA_REACH ((uint8_t)0x08) /*!< IRQ: Max number of back-off during CCA */ -#define IRQ_MASK1_VALID_PREAMBLE ((uint8_t)0x10) /*!< IRQ: Valid preamble detected */ -#define IRQ_MASK1_VALID_SYNC ((uint8_t)0x20) /*!< IRQ: Sync word detected */ -#define IRQ_MASK1_RSSI_ABOVE_TH ((uint8_t)0x40) /*!< IRQ: RSSI above threshold */ -#define IRQ_MASK1_WKUP_TOUT_LDC ((uint8_t)0x80) /*!< IRQ: Wake-up timeout in LDC mode */ - -/** - * @} - */ - -/** @defgroup IRQ_MASK2_Register - * @{ - */ - -/** - * \brief IRQ_MASK2 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_MASK2: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 16 | READY state in steady condition14 - * 17 | STANDBY state switching in progress - * 18 | Low battery level - * 19 | Power-On reset - * 20 | Brown-Out event - * 21 | LOCK state in steady condition - * 22 | PM start-up timer expiration - * 23 | XO settling timeout - * \endcode - */ -#define IRQ_MASK2_BASE ((uint8_t)0x91) /*!< IRQ_MASK is split into 4 registers*/ - -#define IRQ_MASK2_READY ((uint8_t)0x01) /*!< IRQ: READY state */ -#define IRQ_MASK2_STANDBY_DELAYED ((uint8_t)0x02) /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ -#define IRQ_MASK2_LOW_BATT_LVL ((uint8_t)0x04) /*!< IRQ: Battery level below threshold*/ -#define IRQ_MASK2_POR ((uint8_t)0x08) /*!< IRQ: Power On Reset */ -#define IRQ_MASK2_BOR ((uint8_t)0x10) /*!< IRQ: Brown out event (both accurate and inaccurate)*/ -#define IRQ_MASK2_LOCK ((uint8_t)0x20) /*!< IRQ: LOCK state */ -#define IRQ_MASK2_PM_COUNT_EXPIRED ((uint8_t)0x40) /*!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ -#define IRQ_MASK2_XO_COUNT_EXPIRED ((uint8_t)0x80) /*!< IRQ: only for debug; Crystal oscillator settling time counter expired */ - -/** - * @} - */ - -/** @defgroup IRQ_MASK3_Register - * @{ - */ - -/** - * \brief IRQ_MASK3 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_MASK3: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 24 | SYNTH locking timeout - * 25 | SYNTH calibration start-up time - * 26 | SYNTH calibration timeout - * 27 | TX circuitry start-up time - * 28 | RX circuitry start-up time - * 29 | RX operation timeout - * 30 | Others AES End–of –Operation - * 31 | Reserved - * \endcode - */ -#define IRQ_MASK3_BASE ((uint8_t)0x90) /*!< IRQ_MASK is split into 4 registers*/ - -#define IRQ_MASK3_SYNTH_LOCK_TIMEOUT ((uint8_t)0x01) /*!< IRQ: only for debug; LOCK state timeout */ -#define IRQ_MASK3_SYNTH_LOCK_STARTUP ((uint8_t)0x02) /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ -#define IRQ_MASK3_SYNTH_CAL_TIMEOUT ((uint8_t)0x04) /*!< IRQ: only for debug; SYNTH calibration timeout */ -#define IRQ_MASK3_TX_START_TIME ((uint8_t)0x08) /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ -#define IRQ_MASK3_RX_START_TIME ((uint8_t)0x10) /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ -#define IRQ_MASK3_RX_TIMEOUT ((uint8_t)0x20) /*!< IRQ: RX operation timeout */ -#define IRQ_MASK3_AES_END ((uint8_t)0x40) /*!< IRQ: AES End of operation */ - -/** - * @} - */ - - -/** @defgroup IRQ_STATUS0_Register - * @{ - */ - -/** - * \brief IRQ_STATUS0 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_STATUS0: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 0 | RX data ready - * 1 | RX data discarded (upon filtering) - * 2 | TX data sent - * 3 | Max re-TX reached - * 4 | CRC error - * 5 | TX FIFO underflow/overflow error - * 6 | RX FIFO underflow/overflow error - * 7 | TX FIFO almost full - * \endcode - */ - -#define IRQ_STATUS0_BASE ((uint8_t)(0xFD)) /*!< IRQ Events(RR, split into 4 registers) */ - -#define IRQ_STATUS0_SYNTH_LOCK_TIMEOUT ((uint8_t)(0x01)) /*!< IRQ: LOCK state timeout */ -#define IRQ_STATUS0_SYNTH_LOCK_STARTUP ((uint8_t)(0x02)) /*!< IRQ: only for debug; see CALIBR_START_COUNTER */ -#define IRQ_STATUS0_SYNTH_CAL_TIMEOUT ((uint8_t)(0x04)) /*!< IRQ: SYNTH locking timeout */ -#define IRQ_STATUS0_TX_START_TIME ((uint8_t)(0x08)) /*!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER */ -#define IRQ_STATUS0_RX_START_TIME ((uint8_t)(0x10)) /*!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER */ -#define IRQ_STATUS0_RX_TIMEOUT ((uint8_t)(0x20)) /*!< IRQ: RX operation timeout expiration */ -#define IRQ_STATUS0_AES_END ((uint8_t)(0x40)) /*!< IRQ: AES End of operation */ - -/** - * @} - */ - -/** @defgroup IRQ_STATUS1_Register - * @{ - */ - -/** - * \brief IRQ_STATUS1 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_STATUS1: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 8 | TX FIFO almost empty - * 9 | RX FIFO almost full - * 10 | RX FIFO almost empty - * 11 | Max number of back-off during CCA - * 12 | Valid preamble detected - * 13 | Sync word detected - * 14 | RSSI above threshold (Carrier Sense) - * 15 | Wake-up timeout in LDCR mode13 - * \endcode - */ - -#define IRQ_STATUS1_BASE ((uint8_t)(0xFC)) /*!< IRQ Events(RR, split into 4 registers) */ - -#define IRQ_STATUS1_READY ((uint8_t)(0x01)) /*!< IRQ: READY state in steady condition*/ -#define IRQ_STATUS1_STANDBY_DELAYED ((uint8_t)(0x02)) /*!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles */ -#define IRQ_STATUS1_LOW_BATT_LVL ((uint8_t)(0x04)) /*!< IRQ: Battery level below threshold*/ -#define IRQ_STATUS1_POR ((uint8_t)(0x08)) /*!< IRQ: Power On Reset */ -#define IRQ_STATUS1_BOR ((uint8_t)(0x10)) /*!< IRQ: Brown out event (both accurate and inaccurate)*/ -#define IRQ_STATUS1_LOCK ((uint8_t)(0x20)) /*!< IRQ: LOCK state in steady condition */ -#define IRQ_STATUS1_PM_COUNT_EXPIRED ((uint8_t)(0x40)) /*!< IRQ: Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) */ -#define IRQ_STATUS1_XO_COUNT_EXPIRED ((uint8_t)(0x80)) /*!< IRQ: Crystal oscillator settling time counter expired */ - -/** - * @} - */ - -/** @defgroup IRQ_STATUS2_Register - * @{ - */ - -/** - * \brief IRQ_STATUS2 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_STATUS2: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 16 | READY state in steady condition14 - * 17 | STANDBY state switching in progress - * 18 | Low battery level - * 19 | Power-On reset - * 20 | Brown-Out event - * 21 | LOCK state in steady condition - * 22 | PM start-up timer expiration - * 23 | XO settling timeout - * \endcode - */ - -#define IRQ_STATUS2_BASE ((uint8_t)0xFB) /*!< IRQ Events(RR, split into 4 registers) */ - -#define IRQ_STATUS2_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /*!< IRQ: TX FIFO almost empty */ -#define IRQ_STATUS2_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /*!< IRQ: RX FIFO almost full */ -#define IRQ_STATUS2_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /*!< IRQ: RX FIFO almost empty */ -#define IRQ_STATUS2_MAX_BO_CCA_REACH ((uint8_t)0x08) /*!< IRQ: Max number of back-off during CCA */ -#define IRQ_STATUS2_VALID_PREAMBLE ((uint8_t)0x10) /*!< IRQ: Valid preamble detected */ -#define IRQ_STATUS2_VALID_SYNC ((uint8_t)0x20) /*!< IRQ: Sync word detected */ -#define IRQ_STATUS2_RSSI_ABOVE_TH ((uint8_t)(0x40)) /*!< IRQ: RSSI above threshold */ -#define IRQ_STATUS2_WKUP_TOUT_LDC ((uint8_t)(0x80)) /*!< IRQ: Wake-up timeout in LDC mode */ - -/** - * @} - */ - -/** @defgroup IRQ_STATUS3_Register - * @{ - */ - -/** - * \brief IRQ_STATUS3 registers - * \code - * Default value: 0x00 - * Read Write - * - * 7:0 INT_STATUS3: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table) - * - * Bit | Events Group Interrupt Event - * ------------------------------------------------------- - * 24 | SYNTH locking timeout - * 25 | SYNTH calibration start-up time - * 26 | SYNTH calibration timeout - * 27 | TX circuitry start-up time - * 28 | RX circuitry start-up time - * 29 | RX operation timeout - * 30 | Others AES End–of –Operation - * 31 | Reserved - * \endcode - */ -#define IRQ_STATUS3_BASE ((uint8_t)0xFA) /*!< IRQ Events(RR, split into 4 registers) */ - -#define IRQ_STATUS3_RX_DATA_READY ((uint8_t)0x01) /*!< IRQ: RX data ready */ -#define IRQ_STATUS3_RX_DATA_DISC ((uint8_t)0x02) /*!< IRQ: RX data discarded (upon filtering) */ -#define IRQ_STATUS3_TX_DATA_SENT ((uint8_t)0x04) /*!< IRQ: TX data sent */ -#define IRQ_STATUS3_MAX_RE_TX_REACH ((uint8_t)0x08) /*!< IRQ: Max re-TX reached */ -#define IRQ_STATUS3_CRC_ERROR ((uint8_t)0x10) /*!< IRQ: CRC error */ -#define IRQ_STATUS3_TX_FIFO_ERROR ((uint8_t)0x20) /*!< IRQ: TX FIFO underflow/overflow error */ -#define IRQ_STATUS3_RX_FIFO_ERROR ((uint8_t)0x40) /*!< IRQ: RX FIFO underflow/overflow error */ -#define IRQ_STATUS3_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /*!< IRQ: TX FIFO almost full */ - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup MC_STATE_Registers - * @{ - */ - -/** @defgroup MC_STATE1_Register - * @{ - */ - -/** - * \brief MC_STATE1 registers - * \code - * Default value: 0x50 - * Read - * - * 7:4 Reserved. - * - * 3 ANT_SELECT: Currently selected antenna - * - * 2 TX_FIFO_Full: 1 - TX FIFO is full - * - * 1 RX_FIFO_Empty: 1 - RX FIFO is empty - * - * 0 ERROR_LOCK: 1 - RCO calibrator error - * \endcode - */ -#define MC_STATE1_BASE ((uint8_t)(0xC0)) /*!< MC_STATE1 register address (see the SpiritStatus struct */ - - -/** - * @} - */ - - -/** @defgroup MC_STATE0_Register - * @{ - */ - -/** - * \brief MC_STATE0 registers - * \code - * Default value: 0x00 - * Read - * - * 7:1 STATE[6:0]: Current MC state. - * - * REGISTER VALUE | STATE - * -------------------------------------------- - * 0x40 | STANDBY - * 0x36 | SLEEP - * 0x03 | READY - * 0x3B | PM setup - * 0x23 | XO settling - * 0x53 | SYNTH setup - * 0x1F | PROTOCOL - * 0x4F | SYNTH calibration - * 0x0F | LOCK - * 0x33 | RX - * 0x5F | TX - * - * 0 XO_ON: 1 - XO is operating - * \endcode - */ -#define MC_STATE0_BASE ((uint8_t)(0xC1)) /*!< MC_STATE0 register address. In this version ALL existing states have been inserted - and are still to be verified */ -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup Engineering-Test_Registers - * @{ - */ - -#define SYNTH_CONFIG1_BASE ((uint8_t)(0x9E)) /*!< Synthesizier registers: M, A, K data sync on positive/negative clock edges [4], - Enable Linearization of the charge pump [3], split time 1.75/3.45ns [2], VCO calibration window 16,32,64,128 clock cycles [1:0]*/ -#define SYNTH_CONFIG0_BASE ((uint8_t)(0x9F)) /*!< Enable DSM randomizer [7], Window width 1.2-7.5ns (Down-up) of lock detector*/ -#define VCOTH_BASE ((uint8_t)(0xA0)) /*!< Controls the threshold frequency between VCO low and VCO high [7:0] - VCOth frequency=2*fXO*(96+VCO_TH/16), fmin=4992 MHz, fmax=5820 MHz*/ -#define PM_CONFIG2_BASE ((uint8_t)(0xA4)) /*!< Enables high current buffer on Temperature sensor, sets SMPS options */ -#define PM_CONFIG1_BASE ((uint8_t)(0xA5)) /*!< Set SMPS options */ -#define PM_CONFIG0_BASE ((uint8_t)(0xA6)) /*!< Set SMPS options */ -#define VCO_CONFIG_BASE ((uint8_t)(0xA1)) /*!< Set VCO current [5:2]part and [1:0] part */ -#define XO_CONFIG_BASE ((uint8_t)(0xA7)) /*!< Clock management options from XO to digital part */ - -#define XO_RCO_TEST_BASE ((uint8_t)(0xB4)) /*!< Test of XO and RCO */ - -/** - * @} - */ - - -/** @addtogroup Commands - * @{ - */ - -#define COMMAND_TX ((uint8_t)(0x60)) /*!< Start to transmit; valid only from READY */ -#define COMMAND_RX ((uint8_t)(0x61)) /*!< Start to receive; valid only from READY */ -#define COMMAND_READY ((uint8_t)(0x62)) /*!< Go to READY; valid only from STANDBY or SLEEP or LOCK */ -#define COMMAND_STANDBY ((uint8_t)(0x63)) /*!< Go to STANDBY; valid only from READY */ -#define COMMAND_SLEEP ((uint8_t)(0x64)) /*!< Go to SLEEP; valid only from READY */ -#define COMMAND_LOCKRX ((uint8_t)(0x65)) /*!< Go to LOCK state by using the RX configuration of the synth; valid only from READY */ -#define COMMAND_LOCKTX ((uint8_t)(0x66)) /*!< Go to LOCK state by using the TX configuration of the synth; valid only from READY */ -#define COMMAND_SABORT ((uint8_t)(0x67)) /*!< Force exit form TX or RX states and go to READY state; valid only from TX or RX */ -#define COMMAND_LDC_RELOAD ((uint8_t)(0x68)) /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER - registers; valid from all states */ -#define COMMAND_SEQUENCE_UPDATE ((uint8_t)(0x69)) /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register - valid from all states */ -#define COMMAND_AES_ENC ((uint8_t)(0x6A)) /*!< AES: Start the encryption routine; valid from all states; valid from all states */ -#define COMMAND_AES_KEY ((uint8_t)(0x6B)) /*!< AES: Start the procedure to compute the key for the decryption; valid from all states */ -#define COMMAND_AES_DEC ((uint8_t)(0x6C)) /*!< AES: Start the decryption routine using the current key; valid from all states */ -#define COMMAND_AES_KEY_DEC ((uint8_t)(0x6D)) /*!< AES: Compute the key and start the decryption; valid from all states */ -#define COMMAND_SRES ((uint8_t)(0x70)) /*!< Reset of all digital part, except SPI registers */ -#define COMMAND_FLUSHRXFIFO ((uint8_t)(0x71)) /*!< Clean the RX FIFO; valid from all states */ -#define COMMAND_FLUSHTXFIFO ((uint8_t)(0x72)) /*!< Clean the TX FIFO; valid from all states */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Timer.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Timer.h deleted file mode 100644 index d9e5e408f..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Timer.h +++ /dev/null @@ -1,239 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Timer.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT timers. - * @details - * - * This module provides API to configure the Spirit timing mechanisms. - * They allow the user to set the timer registers using raw values or - * compute them since the desired timer value is expressed in ms. - * Moreover the management of the Spirit LDCR mode can be done using - * these API. - * - * Example: - * @code - * ... - * - * SpiritTimerSetRxTimeoutMs(50.0); - * SpiritTimerSetWakeUpTimerMs(150.0); - * - * // IRQ configuration for RX_TIMEOUT and WAKEUP_TIMEOUT - * ... - * - * SpiritTimerLdcrMode(S_ENABLE); - * - * ... - * - * @endcode - * - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT1_TIMER_H -#define __SPIRIT1_TIMER_H - - -/* Includes ------------------------------------------------------------------*/ - -#include "SPIRIT_Regs.h" -#include "SPIRIT_Types.h" - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Timer Timer - * @brief Configuration and management of SPIRIT Timers. - * @details See the file @ref SPIRIT_Timer.h for more details. - * @{ - */ - - -/** - * @defgroup Timer_Exported_Types Timer Exported Types - * @{ - */ - -/** - * @brief All the possible RX timeout stop conditions enumeration. - */ -typedef enum{ - - NO_TIMEOUT_STOP = 0x00, /*!< Timeout never stopped */ - TIMEOUT_ALWAYS_STOPPED = 0x08, /*!< Timeout always stopped (default) */ - RSSI_ABOVE_THRESHOLD = 0x04, /*!< Timeout stopped on RSSI above threshold */ - SQI_ABOVE_THRESHOLD = 0x02, /*!< Timeout stopped on SQI above threshold */ - PQI_ABOVE_THRESHOLD = 0x01, /*!< Timeout stopped on PQI above threshold */ - RSSI_AND_SQI_ABOVE_THRESHOLD = 0x06, /*!< Timeout stopped on both RSSI and SQI above threshold */ - RSSI_AND_PQI_ABOVE_THRESHOLD = 0x05, /*!< Timeout stopped on both RSSI and PQI above threshold */ - SQI_AND_PQI_ABOVE_THRESHOLD = 0x03, /*!< Timeout stopped on both SQI and PQI above threshold */ - ALL_ABOVE_THRESHOLD = 0x07, /*!< Timeout stopped only if RSSI, SQI and PQI are above threshold */ - RSSI_OR_SQI_ABOVE_THRESHOLD = 0x0E, /*!< Timeout stopped if one between RSSI or SQI are above threshold */ - RSSI_OR_PQI_ABOVE_THRESHOLD = 0x0D, /*!< Timeout stopped if one between RSSI or PQI are above threshold */ - SQI_OR_PQI_ABOVE_THRESHOLD = 0x0B, /*!< Timeout stopped if one between SQI or PQI are above threshold */ - ANY_ABOVE_THRESHOLD = 0x0F /*!< Timeout stopped if one among RSSI, SQI or SQI are above threshold */ - -} RxTimeoutStopCondition; - - -#define IS_RX_TIMEOUT_STOP_CONDITION(COND) ( COND == NO_TIMEOUT_STOP || \ - COND == TIMEOUT_ALWAYS_STOPPED || \ - COND == RSSI_ABOVE_THRESHOLD || \ - COND == SQI_ABOVE_THRESHOLD || \ - COND == PQI_ABOVE_THRESHOLD || \ - COND == RSSI_AND_SQI_ABOVE_THRESHOLD || \ - COND == RSSI_AND_PQI_ABOVE_THRESHOLD || \ - COND == SQI_AND_PQI_ABOVE_THRESHOLD || \ - COND == ALL_ABOVE_THRESHOLD || \ - COND == RSSI_OR_SQI_ABOVE_THRESHOLD || \ - COND == RSSI_OR_PQI_ABOVE_THRESHOLD || \ - COND == SQI_OR_PQI_ABOVE_THRESHOLD || \ - COND == ANY_ABOVE_THRESHOLD ) - - - -/** - * @} - */ - - -/** - * @defgroup Timer_Exported_Constants Timer Exported Constants - * @{ - */ - -/** - * @brief It represents the Time Step for RX_Timeout timer in case of 24 MHz Crystal, expressed in us. - * It is equal to 1210/(24*10^6). With this time step it is possible to fix the RX_Timeout to - * a minimum value of 50.417us to a maximum value of about 3.278 s. - * Remember that it is possible to have infinite RX_Timeout writing 0 in the RX_Timeout_Counter and/or RX_Timeout_Prescaler registers. - */ -#define RX_TCLK_24MHz 50.417f -#define IS_RX_TIMEOUT_24MHz(TIMEOUT) (TIMEOUT*1000)>=RX_TCLK_24MHz - -/** - * @brief It represents the Time Step for RX_Timeout timer in case of 26 MHz Crystal, expressed in us. - * It is equal to 1210/(26*10^6). With this time step it is possible to fix the RX_Timeout to - * a minimum value of 46.538us to a maximum value of about 3.026 s. - * Remember that it is possible to have infinite RX_Timeout writing 0 in the RX_Timeout_Counter register. - */ -#define RX_TCLK_26MHz 46.538f -#define IS_RX_TIMEOUT_26MHz(TIMEOUT) (TIMEOUT*1000)>=RX_TCLK_26MHz - -/** - * @brief It represents the Time Step for RX_Wakeup timer expressed in us. This timer is based on RCO (about 34.7 kHZ). - * With this time step it is possible to fix the Wakeup_Timeout to a minimum value of 28.818us to a maximum - * value of about 1.888 s. - */ -#define WAKEUP_TCLK 28.818f -#define IS_WKUP_TIMEOUT(TIMEOUT) (TIMEOUT*1000)>=WAKEUP_TCLK - - - -/** - * @} - */ - - -/** - * @defgroup Timer_Exported_Macros Timer Exported Macros - * @{ - */ - -#define SET_INFINITE_RX_TIMEOUT() SpiritTimerSetRxTimeoutCounter(0) - -/** - * @} - */ - - -/** - * @defgroup Timer_Exported_Functions Timer Exported Functions - * @{ - */ - -void SpiritTimerLdcrMode(SpiritFunctionalState xNewState); -void SpiritTimerLdcrAutoReload(SpiritFunctionalState xNewState); -SpiritFunctionalState SpiritTimerLdcrGetAutoReload(void); -void SpiritTimerSetRxTimeout(uint8_t cCounter , uint8_t cPrescaler); -void SpiritTimerSetRxTimeoutMs(float fDesiredMsec); -void SpiritTimerSetRxTimeoutCounter(uint8_t cCounter); -void SpiritTimerSetRxTimeoutPrescaler(uint8_t cPrescaler); -void SpiritTimerGetRxTimeout(float* pfTimeoutMsec, uint8_t* pcCounter , uint8_t* pcPrescaler); -void SpiritTimerSetWakeUpTimer(uint8_t cCounter , uint8_t cPrescaler); -void SpiritTimerSetWakeUpTimerMs(float fDesiredMsec); -void SpiritTimerSetWakeUpTimerCounter(uint8_t cCounter); -void SpiritTimerSetWakeUpTimerPrescaler(uint8_t cPrescaler); -void SpiritTimerSetWakeUpTimerReloadMs(float fDesiredMsec); -void SpiritTimerGetWakeUpTimer(float* pfWakeUpMsec, uint8_t* pcCounter , uint8_t* pcPrescaler); -void SpiritTimerSetWakeUpTimerReload(uint8_t cCounter , uint8_t cPrescaler); -void SpiritTimerSetWakeUpTimerReloadCounter(uint8_t cCounter); -void SpiritTimerSetWakeUpTimerReloadPrescaler(uint8_t cPrescaler); -void SpiritTimerGetWakeUpTimerReload(float* pfWakeUpReloadMsec, uint8_t* pcCounter , uint8_t* pcPrescaler); -void SpiritTimerComputeWakeUpValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler); -void SpiritTimerComputeRxTimeoutValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler); -void SpiritTimerSetRxTimeoutStopCondition(RxTimeoutStopCondition xStopCondition); -void SpiritTimerReloadStrobe(void); -uint16_t SpiritTimerGetRcoFrequency(void); - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ - diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Types.h b/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Types.h deleted file mode 100644 index ceba82b48..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/inc/SPIRIT_Types.h +++ /dev/null @@ -1,276 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Types.h - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Header file for SPIRIT types. - * @details - * - * This module provide some types definitions which will be used in - * all the modules of this library. Here is defined also the global - * variable @ref g_xStatus which contains the status of Spirit and - * is updated every time an SPI transaction occurs. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT_GENERICTYPES_H -#define __SPIRIT_GENERICTYPES_H - - -/* Includes ------------------------------------------------------------------*/ - -/* Include all integer types definitions */ -#include -#include -#include "SPIRIT_Regs.h" - - - -#ifdef __cplusplus - extern "C" { -#endif - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @defgroup SPIRIT_Types Types - * @brief Module for SPIRIT types definition. - * * @details See the file @ref SPIRIT_Types.h for more details. - * @{ - */ - -/** - * @defgroup Types_Exported_Types Types Exported Types - * @{ - */ - -/** - * @brief Spirit Functional state. Used to enable or disable a specific option. - */ -typedef enum -{ - S_DISABLE = 0, - S_ENABLE = !S_DISABLE - -} SpiritFunctionalState; - -#define IS_SPIRIT_FUNCTIONAL_STATE(STATE) (STATE == S_DISABLE || STATE == S_ENABLE) - -/** - * @brief Spirit Flag status. Used to control the state of a flag. - */ -typedef enum -{ - S_RESET = 0, - S_SET = !S_RESET - -} SpiritFlagStatus; - -#define IS_SPIRIT_FLAG_STATUS(STATUS) (STATUS == S_RESET || STATUS == S_SET) - - -/** - * @brief boolean type enumeration. - */ -typedef enum -{ - S_FALSE = 0, - S_TRUE = !S_FALSE - -} SpiritBool; - - -/** - * @brief SPIRIT States enumeration. - */ -typedef enum -{ - MC_STATE_STANDBY =0x40, /*!< STANDBY */ - MC_STATE_SLEEP =0x36, /*!< SLEEP */ - MC_STATE_READY =0x03, /*!< READY */ - MC_STATE_PM_SETUP =0x3D, /*!< PM_SETUP */ - MC_STATE_XO_SETTLING =0x23, /*!< XO_SETTLING */ - MC_STATE_SYNTH_SETUP =0x53, /*!< SYNT_SETUP */ - MC_STATE_PROTOCOL =0x1F, /*!< PROTOCOL */ - MC_STATE_SYNTH_CALIBRATION =0x4F, /*!< SYNTH */ - MC_STATE_LOCK =0x0F, /*!< LOCK */ - MC_STATE_RX =0x33, /*!< RX */ - MC_STATE_TX =0x5F /*!< TX */ - -} SpiritState; - - - -/** - * @brief SPIRIT Status. This definition represents the single field of the SPIRIT - * status returned on each SPI transaction, equal also to the MC_STATE registers. - * This field-oriented structure allows user to address in simple way the single - * field of the SPIRIT status. - * The user shall define a variable of SpiritStatus type to access on SPIRIT status fields. - * @note The fields order in the structure depends on used endianness (little or big - * endian). The actual definition is valid ONLY for LITTLE ENDIAN mode. Be sure to - * change opportunely the fields order when use a different endianness. - */ - -typedef struct -{ - uint8_t XO_ON:1; /*!< This one bit field notifies if XO is operating - (XO_ON is 1) or not (XO_On is 0) */ - SpiritState MC_STATE: 7; /*!< This 7 bits field indicates the state of the - Main Controller of SPIRIT. The possible states - and their corresponding values are defined in - @ref SpiritState */ - uint8_t ERROR_LOCK: 1; /*!< This one bit field notifies if there is an - error on RCO calibration (ERROR_LOCK is 1) or - not (ERROR_LOCK is 0) */ - uint8_t RX_FIFO_EMPTY: 1; /*!< This one bit field notifies if RX FIFO is empty - (RX_FIFO_EMPTY is 1) or not (RX_FIFO_EMPTY is 0) */ - uint8_t TX_FIFO_FULL: 1; /*!< This one bit field notifies if TX FIFO is full - (TX_FIFO_FULL is 1) or not (TX_FIFO_FULL is 0) */ - uint8_t ANT_SELECT: 1; /*!< This one bit field notifies the currently selected - antenna */ - uint8_t : 4; /*!< This 4 bits field are reserved and equal to 5 */ - -}SpiritStatus; - - - -/** - * @} - */ - - -/** - * @defgroup Types_Exported_Constants Types Exported Constants - * @{ - */ - - -/** - * @} - */ - -/** - * @defgroup Types_Exported_Variables Types Exported Variables - * @{ - */ - -extern volatile SpiritStatus g_xStatus; - -/** - * @} - */ - -/** - * @defgroup Types_Exported_Macros Types Exported Macros - * @{ - */ - -#ifdef SPIRIT_USE_FULL_ASSERT - /** - * @brief The s_assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ - #define s_assert_param(expr) ((expr) ? (void)0 : s_assert_failed((uint8_t *)__FILE__, __LINE__)) - void s_assert_failed(uint8_t* file, uint32_t line); -#elif SPIRIT_USE_VCOM_ASSERT - /** - * @brief The s_assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ - #define s_assert_param(expr) ((expr) ? (void)0 : s_assert_failed((uint8_t *)__FILE__, __LINE__,#expr)) - void s_assert_failed(uint8_t* file, uint32_t line, char* expression); - -#elif SPIRIT_USE_FRAME_ASSERT - /** - * @brief The s_assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ -#define s_assert_param(expr) ((expr) ? (void)0 : s_assert_failed(#expr)) - void s_assert_failed(char* expression); -#else -#define s_assert_param(expr) {} -#endif - -/** - * @brief Returns the absolute value. - */ -#define S_ABS(a) ((a)>0?(a):-(a)) - - -/** - * @} - */ - - -/** - * @defgroup Types_Exported_Functions Types Exported Functions - * @{ - */ - -void SpiritRefreshStatus(void); - -/** - *@} - */ - -/** - * @} - */ - - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT1_Util.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT1_Util.c deleted file mode 100644 index 7ce878a93..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT1_Util.c +++ /dev/null @@ -1,652 +0,0 @@ -/** -* @file SPIRIT1_Util.c -* @author High End Analog & RF BU - AMS / ART Team IMS-Systems Lab -* @version V3.0.1 -* @date November 19, 2012 -* @brief Identification functions for SPIRIT DK. -* @details -* -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE -* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY -* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING -* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE -* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -* -* THIS SOURCE CODE IS PROTECTED BY A LICENSE. -* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED -* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. -* -*

© COPYRIGHT 2012 STMicroelectronics

-*/ - - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT1_Util.h" -#include "SPIRIT_Config.h" -#include "spirit1-config.h" -#if defined(P2P_DEMO) -#include "spirit1_appli.h" -#endif -/** -* @addtogroup ST_SPIRIT1 -* @{ -*/ - - -/** -* @addtogroup SPIRIT1_Util -* @{ -*/ - - -/** -* @defgroup SPIRIT1_Util_Private_TypesDefinitions SPIRIT1_Util Private Types Definitions -* @{ -*/ - -/** -* @} -*/ - - -/** -* @defgroup SPIRIT1_Util_Private_Defines SPIRIT1_Util Private Defines -* @{ -*/ - -/** -* @} -*/ - - -/** -* @defgroup SPIRIT1_Util_Private_Macros SPIRIT1_Util Private Macros -* @{ -*/ -#define SPIRIT_VERSION SPIRIT_VERSION_3_0 -#define RANGE_TYPE RANGE_EXT_NONE /*RANGE_EXT_SKYWORKS*/ -/** -* @} -*/ - - -/** -* @defgroup SPIRIT1_Util_Private_Variables SPIRIT1_Util Private Variables -* @{ -*/ - -/** -* @brief A map that contains the SPIRIT version -*/ -const SpiritVersionMap xSpiritVersionMap[] = -{ - /* The Control Board frame handler functions */ - {CUT_2_1v4, SPIRIT_VERSION_2_1}, - {CUT_2_1v3, SPIRIT_VERSION_2_1}, - {CUT_3_0, SPIRIT_VERSION_3_0}, -}; -static RangeExtType xRangeExtType = RANGE_EXT_NONE; - -static uint8_t s_RfModuleBand = 0; -static uint8_t s_eeprom = 0; -/** -* @} -*/ - - -/** -* @defgroup SPIRIT1_Util_Private_FunctionPrototypes SPIRIT1_Util Private Function Prototypes -* @{ -*/ - -/** -* @} -*/ - - -/** -* @defgroup SPIRIT1_Util_Private_Functions SPIRIT1_Util Private Functions -* @{ -*/ - -/** -* @brief Read the status register. -* @param None -* @retval Status -*/ -void Spirit1InterfaceInit(void) -{ - /* Initialize the SDN pin micro side */ - RadioGpioInit(RADIO_GPIO_SDN,RADIO_MODE_GPIO_OUT); - - SpiritSpiInit(); - -#if defined(SPIRIT1_HAS_EEPROM) - EepromSpiInitialization(); -#endif - - /* Board management */ - SpiritEnterShutdown(); - SpiritExitShutdown(); - - SpiritManagementIdentificationRFBoard(); - - /* Initialize the signals to drive the range extender application board */ - SpiritManagementRangeExtInit(); - - /* Micro EXTI config */ - RadioGpioInit(RADIO_GPIO_IRQ,RADIO_MODE_EXTI_IN); - RadioGpioInterruptCmd(RADIO_GPIO_IRQ,0x04,0x04,DISABLE); - RadioGpioInterruptCmd(RADIO_GPIO_IRQ,0x04,0x04,ENABLE); -} - -#if defined(SPIRIT1_HAS_EEPROM) -/** -* @brief Read the status register. -* @param None -* @retval Status -*/ -uint8_t EepromIdentification(void) -{ - uint8_t status; - status = EepromSetSrwd(); - status = EepromStatus(); - if((status&0xF0) == EEPROM_STATUS_SRWD) - { - /*0xF0 mask [SRWD 0 0 0]*/ - status = 1; - EepromResetSrwd(); - } - else - status = 0; - - return status; -} -#endif - -#if defined(SPIRIT1_HAS_EEPROM) - -/** -* @brief Identifies the SPIRIT1 Xtal frequency and version. -* @param None -* @retval Status -*/ -void SpiritManagementIdentificationRFBoard(void) -{ - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - }while(g_xStatus.MC_STATE!=MC_STATE_READY); - - SdkEvalSetHasEeprom(EepromIdentification()); - - if(!SdkEvalGetHasEeprom()) /* EEPROM is not present*/ - { - SpiritManagementComputeSpiritVersion(); - SpiritManagementComputeXtalFrequency(); - } - else /* EEPROM found*/ - { - /*read the memory and set the variable*/ - EepromRead(0x0000, 32, tmpBuffer); - uint32_t xtal; - if(tmpBuffer[0]==0 || tmpBuffer[0]==0xFF) { - SpiritManagementComputeSpiritVersion(); - SpiritManagementComputeXtalFrequency(); - return; - } - switch(tmpBuffer[1]) { - case 0: - xtal = 24000000; - SpiritRadioSetXtalFrequency(xtal); - break; - case 1: - xtal = 25000000; - SpiritRadioSetXtalFrequency(xtal); - break; - case 2: - xtal = 26000000; - SpiritRadioSetXtalFrequency(xtal); - break; - case 3: - xtal = 48000000; - SpiritRadioSetXtalFrequency(xtal); - break; - case 4: - xtal = 50000000; - SpiritRadioSetXtalFrequency(xtal); - break; - case 5: - xtal = 52000000; - SpiritRadioSetXtalFrequency(xtal); - break; - default: - SpiritManagementComputeXtalFrequency(); - break; - } - - SpiritVersion spiritVersion; - if(tmpBuffer[2]==0 || tmpBuffer[2]==1) { - spiritVersion = SPIRIT_VERSION_2_1; - //SpiritGeneralSetSpiritVersion(spiritVersion); - } - else if(tmpBuffer[2]==2) { - spiritVersion = SPIRIT_VERSION_3_0; - //SpiritGeneralSetSpiritVersion(spiritVersion); - } - else { - SpiritManagementComputeSpiritVersion(); - } - if(tmpBuffer[14]==1) { - spiritVersion = SPIRIT_VERSION_3_0_D1; - // SpiritGeneralSetSpiritVersion(spiritVersion); - } - - RangeExtType range; - if(tmpBuffer[5]==0) { - range = RANGE_EXT_NONE; - } - else if(tmpBuffer[5]==1) { - range = RANGE_EXT_SKYWORKS_169; - } - else if(tmpBuffer[5]==2) { - range = RANGE_EXT_SKYWORKS_868; - } - else { - range = RANGE_EXT_NONE; - } - SpiritManagementSetRangeExtender(range); - - SpiritManagementSetBand(tmpBuffer[3]); - - } -} -#endif - -#if defined(NO_EEPROM) -/** -* @brief Identifies the SPIRIT1 Xtal frequency and version. -* @param None -* @retval Status -*/ -void SpiritManagementIdentificationRFBoard(void) -{ - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - }while(g_xStatus.MC_STATE!=MC_STATE_READY); - - SpiritRadioSetXtalFrequency(XTAL_FREQUENCY); - //SpiritGeneralSetSpiritVersion(SPIRIT_VERSION); -} -#endif - - -/** -* @brief Sets the SPIRIT frequency band -* @param uint8_t value: RF FREQUENCY -* @retval None -*/ -void SpiritManagementSetBand(uint8_t value) -{ - s_RfModuleBand = value; -} - - -/** -* @brief returns the SPIRIT frequency band -* @param None -* @retval uint8_t value: RF FREQUENCY -*/ -uint8_t SpiritManagementGetBand(void) -{ - return s_RfModuleBand; -} - -/** -* @defgroup RANGE_EXT_MANAGEMENT_FUNCTIONS SDK SPIRIT Management Range Extender Functions -* @{ -*/ -void SpiritManagementRangeExtInit(void) -{ - RangeExtType range_type = SpiritManagementGetRangeExtender(); - - if(range_type==RANGE_EXT_SKYWORKS_169) { - /* TCXO optimization power consumption */ - SpiritGeneralSetExtRef(MODE_EXT_XIN); - uint8_t tmp = 0x01; SpiritSpiWriteRegisters(0xB6,1,&tmp); - - /* CSD control */ - SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_0, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_RX_MODE}); - - /* CTX/BYP control */ - SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_1, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_STATE}); - - /* Vcont control */ - SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_2, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_RX_STATE}); - } - else if(range_type==RANGE_EXT_SKYWORKS_868) { - /* CSD control */ - SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_0, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_RX_MODE}); - - /* CTX/BYP control */ - SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_1, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_RX_STATE}); - - /* Vcont control */ - SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_2, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP, SPIRIT_GPIO_DIG_OUT_TX_STATE}); - } -} - -/** -* @brief returns the spirit1 range extender type -* @param None -* @retval RangeExtType -*/ -RangeExtType SpiritManagementGetRangeExtender(void) -{ - return xRangeExtType; -} - -/** -* @brief Sets the spirit1 range extender type -* @param RangeExtType -* @retval None -*/ -void SpiritManagementSetRangeExtender(RangeExtType xRangeType) -{ - xRangeExtType = xRangeType; -} - -/** -* @brief this function returns the value to indicate that EEPROM is present or not -* @param None -* @retval uint8_t: 0 or 1 -*/ -uint8_t SdkEvalGetHasEeprom(void) -{ - return s_eeprom; -} - -/** -* @brief this function setc the value to indicate that EEPROM is present or not -* @param None -* @retval uint8_t: 0 or 1 -*/ -void SdkEvalSetHasEeprom(uint8_t eeprom) -{ - s_eeprom = eeprom; -} - -/** -* @brief this function intializes the spirit1 gpio irq for TX and Rx -* @param None -* @retval None -*/ -void Spirit1GpioIrqInit(SGpioInit *pGpioIRQ) -{ - /* Spirit IRQ config */ - SpiritGpioInit(pGpioIRQ); -} - -/** -* @brief this function used to receive RX packet -* @param None -* @retval None -*/ -void Spirit1RadioInit(SRadioInit *pRadioInit) -{ - /* Spirit Radio config */ - SpiritRadioInit(pRadioInit); - -} - -/** -* @brief this function sets the radio power -* @param uint8_t cIndex, float fPowerdBm -* @retval None -*/ -void Spirit1SetPower(uint8_t cIndex, float fPowerdBm) -{ - /* Spirit Radio set power */ - SpiritRadioSetPALeveldBm(cIndex,fPowerdBm); - SpiritRadioSetPALevelMaxIndex(cIndex); -} - -/** -* @brief this function sets the packet configuration according to the protocol used -* @param None -* @retval None -*/ -void Spirit1PacketConfig(void) -{ - BasicProtocolInit(); -} - -/** -* @brief this function sets the payload length -* @param uint8_t length -* @retval None -*/ -void Spirit1SetPayloadlength(uint8_t length) -{ -#if defined(USE_STack_PROTOCOL) - /* Payload length config */ - SpiritPktStackSetPayloadLength(length); - -#elif defined(USE_BASIC_PROTOCOL) - /* payload length config */ - SpiritPktBasicSetPayloadLength(length); -#endif -} - -/** -* @brief this function sets the destination address -* @param uint8_t adress -* @retval None -*/ -void Spirit1SetDestinationAddress(uint8_t address) -{ -#if defined(USE_STack_PROTOCOL) - /* Destination address */ - SpiritPktStackSetDestinationAddress(address); -#elif defined(USE_BASIC_PROTOCOL) - /* destination address */ - SpiritPktBasicSetDestinationAddress(address); -#endif -} - -/** -* @brief this function enables the Tx IRQ -* @param None -* @retval None -*/ -void Spirit1EnableTxIrq(void) -{ - /* Spirit IRQs enable */ - SpiritIrq(TX_DATA_SENT, S_ENABLE); -#if defined(USE_STack_PROTOCOL) - SpiritIrq(MAX_RE_TX_REACH, S_ENABLE); -#elif defined(USE_BASIC_PROTOCOL) //added inadr - SpiritIrq(VALID_SYNC,S_ENABLE); - SpiritIrq(TX_FIFO_ERROR, S_ENABLE); - -#endif -} - -/** -* @brief this function enables the Rx IRQ -* @param None -* @retval None -*/ -void Spirit1EnableRxIrq(void) -{ - /* Spirit IRQs enable */ - SpiritIrq(RX_DATA_READY, S_ENABLE); - SpiritIrq(RX_DATA_DISC, S_ENABLE); - SpiritIrq(RX_TIMEOUT, S_ENABLE); -#ifdef USE_BASIC_PROTOCOL //added inadr - SpiritIrq(RX_FIFO_ERROR, S_ENABLE); -#endif - -} - -/** -* @brief this function disable IRQs -* @param None -* @retval None -*/ -void Spirit1DisableIrq(void) -{ - /* Spirit IRQs enable */ - SpiritIrqDeInit(NULL); -} -/** -* @brief this function set the receive timeout period -* @param None -* @retval None -*/ -void Spirit1SetRxTimeout(float cRxTimeOut) -{ - if(cRxTimeOut == 0) - { - /* rx timeout config */ - SET_INFINITE_RX_TIMEOUT(); - SpiritTimerSetRxTimeoutStopCondition(ANY_ABOVE_THRESHOLD); - } - else - { - /* RX timeout config */ - SpiritTimerSetRxTimeoutMs(cRxTimeOut); - Spirit1EnableSQI(); - SpiritTimerSetRxTimeoutStopCondition(RSSI_AND_SQI_ABOVE_THRESHOLD); } -} - -/** -* @brief this function sets the RSSI threshold -* @param int dbmValue -* @retval None -*/ -void Spirit1SetRssiTH(int dbmValue) -{ - SpiritQiSetRssiThresholddBm(dbmValue); -} - -/** -* @brief this function sets the RSSI threshold -* @param int dbmValue -* @retval None -*/ -float Spirit1GetRssiTH(void) -{ - float dbmValue=0; - dbmValue = SpiritQiGetRssidBm(); - return dbmValue; -} - -/** -* @brief this function enables SQI check -* @param None -* @retval None -*/ -void Spirit1EnableSQI(void) -{ - /* enable SQI check */ - SpiritQiSetSqiThreshold(SQI_TH_0); - SpiritQiSqiCheck(S_ENABLE); -} - -/** -* @brief this function starts the RX process -* @param None -* @retval None -*/ -void Spirit1StartRx(void) -{ - /* RX command */ - SpiritCmdStrobeRx(); -#if 0 - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - } - while(g_xStatus.MC_STATE!=MC_STATE_RX); -#endif -} - -/** -* @brief this function receives the data -* @param None -* @retval None -*/ -void Spirit1GetRxPacket(uint8_t *buffer, uint8_t cRxData ) -{ - /* when rx data ready read the number of received bytes */ - cRxData=SpiritLinearFifoReadNumElementsRxFifo(); - - /* read the RX FIFO */ - SpiritSpiReadLinearFifo(cRxData, buffer); - - SpiritCmdStrobeFlushRxFifo(); -} - -/** -* @brief this function starts the TX process -* @param None -* @retval None -*/ -void Spirit1StartTx(uint8_t *buffer, uint8_t size ) -{ - /* fit the TX FIFO */ - SpiritCmdStrobeFlushTxFifo(); - - SpiritSpiWriteLinearFifo(size, buffer); - - /* send the TX command */ - SpiritCmdStrobeTx(); -#if 0 - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - } - while(g_xStatus.MC_STATE!=MC_STATE_TX); -#endif -#if defined(P2P_DEMO) - - /* wait for TX done */ - while(!xTxDoneFlag); - xTxDoneFlag = RESET; -#endif -} - -/** -* @brief this function clear the IRQ status -* @param None -* @retval None -*/ -void Spirit1ClearIRQ(void) -{ - SpiritIrqClearStatus(); -} -/** -* @} -*/ - -/** -* @} -*/ - - -/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Aes.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Aes.c deleted file mode 100644 index 469b3d399..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Aes.c +++ /dev/null @@ -1,319 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Aes.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT AES Engine. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Aes.h" -#include "MCU_Interface.h" - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_Aes - * @{ - */ - - -/** - * @defgroup Aes_Private_TypesDefinitions AES Private Types Definitions - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Aes_Private_Defines AES Private Defines - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Aes_Private_Macros AES Private Macros - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Aes_Private_Variables AES Private Variables - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Aes_Private_FunctionPrototypes AES Private Function Prototypes - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Aes_Private_Functions AES Private Functions - * @{ - */ - - -/** - * @brief Enables or Disables the AES engine. - * @param xNewState new state for AES engine. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None - */ -void SpiritAesMode(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Modifies the register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= AES_MASK; - } - else - { - tempRegValue &= ~AES_MASK; - } - - /* Writes the ANA_FUNC_CONF0 register to enable or disable the AES engine */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Writes the data to encrypt or decrypt, or the encryption key for the - * derive decryption key operation into the AES_DATA_IN registers. - * @param pcBufferDataIn pointer to the user data buffer. The first byte of the array - * shall be the MSB byte and it will be put in the AES_DATA_IN[0] register, while - * the last one shall be the LSB and it will be put in the AES_DATA_IN[cDataLength-1] - * register. If data to write are less than 16 bytes the remaining AES_DATA_IN registers - * will be filled with bytes equal to 0. This parameter is an uint8_t*. - * @param cDataLength length of data in bytes. - * This parameter is an uint8_t. - * @retval None - */ -void SpiritAesWriteDataIn(uint8_t* pcBufferDataIn, uint8_t cDataLength) -{ - uint8_t i, dataInArray[16]; - - /* Verifies that there are no more than 16 bytes */ - (cDataLength>16) ? (cDataLength=16) : cDataLength; - - /* Fill the dataInArray with the data buffer, using padding */ - for(i=0;i<16;i++) - { - (i<(16 - cDataLength)) ? (dataInArray[i]=0):(dataInArray[i]=pcBufferDataIn[15-i]); - - } - - /* Writes the AES_DATA_IN registers */ - g_xStatus = SpiritSpiWriteRegisters(AES_DATA_IN_15_BASE, 16, dataInArray); - -} - - -/** - * @brief Returns the encrypted or decrypted data or the decription key from the AES_DATA_OUT register. - * @param pcBufferDataOut pointer to the user data buffer. The AES_DATA_OUT[0] - * register value will be put as first element of the buffer (MSB), while the - * AES_DAT_OUT[cDataLength-1] register value will be put as last element of the buffer (LSB). - * This parameter is a uint8_t*. - * @param cDataLength length of data to read in bytes. - * This parameter is a uint8_t. - * @retval None - */ -void SpiritAesReadDataOut(uint8_t* pcBufferDataOut, uint8_t cDataLength) -{ - uint8_t address, dataOutArray[16]; - - /* Verifies that there are no more than 16 bytes */ - (cDataLength>16) ? (cDataLength=16) : cDataLength; - - /* Evaluates the address of AES_DATA_OUT from which start to read */ - address = AES_DATA_OUT_15_BASE+16-cDataLength; - - /* Reads the exact number of AES_DATA_OUT registers */ - g_xStatus = (SpiritSpiReadRegisters(address, cDataLength, dataOutArray)); - - /* Copy in the user buffer the read values changing the order */ - for(int i = (cDataLength-1); i>=0; i--) - { - *pcBufferDataOut = dataOutArray[i]; - pcBufferDataOut++; - } - -} - - -/** - * @brief Writes the encryption key into the AES_KEY_IN register. - * @param pcKey pointer to the buffer of 4 words containing the AES key. - * The first byte of the buffer shall be the most significant byte AES_KEY_0 of the AES key. - * The last byte of the buffer shall be the less significant byte AES_KEY_15 of the AES key. - * This parameter is an uint8_t*. - * @retval None - */ -void SpiritAesWriteKey(uint8_t* pcKey) -{ - uint8_t pcTempKey[16]; - for (uint8_t i = 0; i < 16; i++) - { - pcTempKey[15-i] = pcKey[i]; - } - - /* Writes the AES_DATA_IN registers */ - g_xStatus = SpiritSpiWriteRegisters(AES_KEY_IN_15_BASE, 16, pcTempKey); - -} - -/** - * @brief Returns the encryption/decryption key from the AES_KEY_IN register. - * @param pcKey pointer to the buffer of 4 words (16 bytes) containing the AES key. - * The first byte of the buffer shall be the most significant byte AES_KEY_0 of the AES key. - * The last byte of the buffer shall be the less significant byte AES_KEY_15 of the AES key. - * This parameter is an uint8_t*. - * @retval None - */ -void SpiritAesReadKey(uint8_t* pcKey) -{ - uint8_t pcTempKey[16]; - - /* Reads the AES_DATA_IN registers */ - g_xStatus = SpiritSpiReadRegisters(AES_KEY_IN_15_BASE, 16, pcTempKey); - - - for (uint8_t i = 0; i < 16; i++) - pcKey[i] = pcTempKey[15-i]; - -} - - - -/** - * @brief Derives the decryption key from a given encryption key. - * @param None. - * @retval None. - */ -void SpiritAesDeriveDecKeyFromEnc(void) -{ - /* Sends the COMMAND_AES_KEY command */ - g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_KEY); - -} - - -/** - * @brief Executes the encryption operation. - * @param None. - * @retval None. - */ -void SpiritAesExecuteEncryption(void) -{ - /* Sends the COMMAND_AES_ENC command */ - g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_ENC); - -} - - -/** - * @brief Executes the decryption operation. - * @param None. - * @retval None. - */ -void SpiritAesExecuteDecryption(void) -{ - /* Sends the COMMAND_AES_DEC command */ - g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_DEC); - -} - - -/** - * @brief Executes the key derivation and the decryption operation. - * @param None. - * @retval None. - */ -void SpiritAesDeriveDecKeyExecuteDec(void) -{ - /* Sends the COMMAND_AES_KEY_DEC command */ - g_xStatus = SpiritSpiCommandStrobes(COMMAND_AES_KEY_DEC); - -} - - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Calibration.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Calibration.c deleted file mode 100644 index 698a9de47..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Calibration.c +++ /dev/null @@ -1,491 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Calibration.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT VCO-RCO calibration. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Calibration.h" -#include "MCU_Interface.h" - - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_Calibration - * @{ - */ - - -/** - * @defgroup Calibration_Private_TypesDefinitions Calibration Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Calibration_Private_Defines Calibration Private Defines - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup Calibration_Private_Macros Calibration Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Calibration_Private_Variables Calibration Private Variables - * @{ - */ - -/** - *@} - */ - - - -/** - * @defgroup Calibration_Private_FunctionPrototypes Calibration Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Calibration_Private_Functions Calibration Private Functions - * @{ - */ - -/** - * @brief Enables or Disables the RCO calibration. - * @param xNewState new state for RCO calibration. - This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritCalibrationRco(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - - /* Build new value for the register */ - if(xNewState==S_ENABLE) - { - tempRegValue |= PROTOCOL2_RCO_CALIBRATION_MASK; - } - else - { - tempRegValue &= ~PROTOCOL2_RCO_CALIBRATION_MASK; - } - - /* Writes register to enable or disable the RCO calibration */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Enables or Disables the VCO calibration. - * @param xNewState new state for VCO calibration. - This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritCalibrationVco(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - - /* Build new value for the register */ - if(xNewState==S_ENABLE) - tempRegValue |= PROTOCOL2_VCO_CALIBRATION_MASK; - else - tempRegValue &= ~PROTOCOL2_VCO_CALIBRATION_MASK; - - /* Writes register to enable or disable the VCO calibration */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets the RCO calibration words. - * @param cRwt RWT word for RCO calibration. - * This parameter can be a value of uint8_t. - * @param cRfb RFB word for RCO calibration. - * This parameter can be a value of uint8_t. - * @retval None. - */ -void SpiritCalibrationSetRcoCalWords(uint8_t cRwt, uint8_t cRfb) -{ - uint8_t tempRegValue[2]; - - /* Build the value of RWT and the MSbits of the RFB word */ - tempRegValue[0] = (cRwt << 4) | (cRfb >> 1); - - /* Reads the register value to update the LSbit of RFB */ - g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue[1]); - - /* Build new value for the register */ - tempRegValue[1] = (tempRegValue[1] & 0x7F) | (cRfb<<7); - - /* Writes the new value for RCO calibration words */ - g_xStatus = SpiritSpiWriteRegisters(RCO_VCO_CALIBR_IN2_BASE, 2, tempRegValue); - -} - - -/** - * @brief Returns the RCO calibration words. - * @param pcRwt pointer to the variable in which the RWT word has to be stored. - * This parameter is a variable of uint8_t*. - * @param pcRfb pointer to the variable in which the RFB word has to be stored. - * This parameter is a variable of uint8_t*. - * @retval None. - */ -void SpiritCalibrationGetRcoCalWords(uint8_t* pcRwt, uint8_t* pcRfb) -{ - uint8_t tempRegValue[2]; - - /* Reads the registers values */ - g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_OUT1_BASE, 2, tempRegValue); - - /* Build the RWT value */ - (*pcRwt) = tempRegValue[0] >> 4; - /* Build the RFB value */ - (*pcRfb) = (tempRegValue[0] & 0x0F)<<1 | (tempRegValue[1]>>7); - -} - - -/** - * @brief Returns the VCO calibration data from internal VCO calibrator. - * @param None. - * @retval uint8_t VCO calibration data word. - */ -uint8_t SpiritCalibrationGetVcoCalData(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_OUT0_BASE, 1, &tempRegValue); - - /* Build and returns the VCO calibration data value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Sets the VCO calibration data to be used in TX mode. - * @param cVcoCalData calibration data word to be set. - * This parameter is a variable of uint8_t. - * @retval None. - */ -void SpiritCalibrationSetVcoCalDataTx(uint8_t cVcoCalData) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue); - - /* Build the value to be written */ - tempRegValue &= 0x80; - tempRegValue |= cVcoCalData; - - /* Writes the new value of calibration data in TX */ - g_xStatus = SpiritSpiWriteRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the actual VCO calibration data used in TX mode. - * @param None. - * @retval uint8_t Calibration data word used in TX mode. - */ -uint8_t SpiritCalibrationGetVcoCalDataTx(void) -{ - uint8_t tempRegValue; - - /* Reads the register containing the calibration data word used in TX mode */ - g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN1_BASE, 1, &tempRegValue); - - /* Mask the VCO_CALIBR_TX field and returns the value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Sets the VCO calibration data to be used in RX mode. - * @param cVcoCalData calibration data word to be set. - * This parameter is a variable of uint8_t. - * @retval None. - */ -void SpiritCalibrationSetVcoCalDataRx(uint8_t cVcoCalData) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN0_BASE, 1, &tempRegValue); - - /* Build the value to be written */ - tempRegValue &= 0x80; - tempRegValue |= cVcoCalData; - - /* Writes the new value of calibration data in RX */ - g_xStatus = SpiritSpiWriteRegisters(RCO_VCO_CALIBR_IN0_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the actual VCO calibration data used in RX mode. - * @param None. - * @retval uint8_t Calibration data word used in RX mode. - */ -uint8_t SpiritCalibrationGetVcoCalDataRx(void) -{ - uint8_t tempRegValue; - - /* Reads the register containing the calibration data word used in TX mode */ - g_xStatus = SpiritSpiReadRegisters(RCO_VCO_CALIBR_IN0_BASE, 1, &tempRegValue); - - /* Mask the VCO_CALIBR_RX field and returns the value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Sets the VCO calibration window. - * @param xRefWord value of REFWORD corresponding to the Ref_period according to the formula: CALIBRATION_WIN = 11*Ref_period/fxo. - This parameter can be a value of @ref VcoWin. - * @retval None. - */ -void SpiritCalibrationSetVcoWindow(VcoWin xRefWord) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_VCO_WIN(xRefWord)); - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - - /* Build the values to be written */ - tempRegValue &= 0xFC; - tempRegValue |= xRefWord; - - /* Writes the new value of VCO calibration window */ - g_xStatus = SpiritSpiWriteRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the VCO calibration window. - * @param None. - * @retval VcoWin Value of REFWORD corresponding to the Ref_period according to the formula: CALIBRATION_WIN = 11*Ref_period/fxo. - * This parameter can be a value of @ref VcoWin. - */ -VcoWin SpiritCalibrationGetVcoWindow(void) -{ - uint8_t tempRegValue1, tempRegValue2; - VcoWin refWord; - - /* Reads the register containing the REFWORD value */ - g_xStatus = SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue1); - - /* Reads the Xtal configuration */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue2); - - /* Mask the REFWORD field */ - tempRegValue1 &= 0x03; - - /* Mask the 24_26_MHz_SELECT field */ - tempRegValue2 = ((tempRegValue2 & 0x40)>>6); - - /* In case of 26 MHz crystal */ - if(tempRegValue2) - { - switch(tempRegValue1) - { - case 0: - refWord = CALIB_TIME_6_77_US_26MHZ; - break; - case 1: - refWord = CALIB_TIME_13_54_US_26MHZ; - break; - case 2: - refWord = CALIB_TIME_27_08_US_26MHZ; - break; - case 3: - refWord = CALIB_TIME_54_15_US_26MHZ; - break; - } - } - - /* In case of 24 MHz crystal */ - else - { - switch(tempRegValue1) - { - case 0: - refWord = CALIB_TIME_7_33_US_24MHZ; - break; - case 1: - refWord = CALIB_TIME_14_67_US_24MHZ; - break; - case 2: - refWord = CALIB_TIME_29_33_US_24MHZ; - break; - case 3: - refWord = CALIB_TIME_58_67_US_24MHZ; - break; - } - } - - return refWord; - -} - -/** - * @brief Selects a VCO. - * @param xVco can be VCO_H or VCO_L according to which VCO select. - * This parameter can be a value of @ref VcoSel. - * @retval None. - */ -void SpiritCalibrationSelectVco(VcoSel xVco) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_VCO_SEL(xVco)); - - SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - - tempRegValue &= 0xF9; - - if(xVco == VCO_H) - { - tempRegValue |= 0x02; - - } - else - { - tempRegValue |= 0x04; - } - SpiritSpiWriteRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - -} - - - -/** - * @brief Returns the VCO selected. - * @param void. - * @retval VCO_H or VCO_L according to which VCO selected. - * This parameter can be a value of @ref VcoSel. - */ -VcoSel SpiritCalibrationGetVcoSelecttion(void) -{ - uint8_t tempRegValue; - - SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - - tempRegValue = (tempRegValue>>1)&0x3; - - if(tempRegValue == 0x01) - { - return VCO_H; - - } - else - { - return VCO_L; - } - -} - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Commands.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Commands.c deleted file mode 100644 index fe10f8022..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Commands.c +++ /dev/null @@ -1,144 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Commands.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Management of SPIRIT Commands. - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Commands.h" -#include "MCU_Interface.h" - - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_Commands - * @{ - */ - - -/** - * @defgroup Commands_Private_TypesDefinitions Commands Private TypesDefinitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Commands_Private_Defines Commands Private Defines - * @{ - */ - -/** - *@} - */ - -/** - * @defgroup Commands_Private_Macros Commands Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Commands_Private_Variables Commands Private Variables - * @{ - */ - -/** - *@} - */ - - - -/** - * @defgroup Commands_Private_FunctionPrototypes Commands Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Commands_Private_Functions Commands Private Functions - * @{ - */ - -/** - * @brief Sends a specific command to SPIRIT. - * @param xCommandCode code of the command to send. - This parameter can be any value of @ref SpiritCmd. - * @retval None. - */ -void SpiritCmdStrobeCommand(SpiritCmd xCommandCode) -{ - /* Check the parameters */ - s_assert_param(IS_SPIRIT_CMD(xCommandCode)); - - g_xStatus = SpiritSpiCommandStrobes((uint8_t) xCommandCode); -} - - -/** - *@} - */ - - -/** - *@} - */ - - -/** - *@} - */ - - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Csma.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Csma.c deleted file mode 100644 index c5f3b55f2..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Csma.c +++ /dev/null @@ -1,600 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Csma.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT CSMA. - * @details - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Csma.h" -#include "MCU_Interface.h" - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_Csma - * @{ - */ - - -/** - * @defgroup Csma_Private_TypesDefinitions CSMA Private TypesDefinitions - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup Csma_Private_Defines CSMA Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Csma_Private_Macros CSMA Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Csma_Private_Variables CSMA Private Variables - * @{ - */ - -/** - *@} - */ - - - -/** - * @defgroup Csma_Private_FunctionPrototypes CSMA Private FunctionPrototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Csma_Private_Functions CSMA Private Functions - * @{ - */ - - -/** - * @brief Initializes the SPIRIT CSMA according to the specified parameters in the CsmaInit. - * @param pxCsmaInit Csma init structure. - * This parameter is a pointer to @ref CsmaInit. - * @retval None. - */ -void SpiritCsmaInit(CsmaInit* pxCsmaInit) -{ - uint8_t tempRegValue[5]; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxCsmaInit->xCsmaPersistentMode)); - s_assert_param(IS_CCA_PERIOD(pxCsmaInit->xMultiplierTbit)); - s_assert_param(IS_CSMA_LENGTH(pxCsmaInit->xCcaLength)); - s_assert_param(IS_BU_COUNTER_SEED(pxCsmaInit->nBuCounterSeed)); - s_assert_param(IS_BU_PRESCALER(pxCsmaInit->cBuPrescaler)); - s_assert_param(IS_CMAX_NB(pxCsmaInit->cMaxNb)); - - /* CSMA BU counter seed (MSB) config */ - tempRegValue[0] = (uint8_t)(pxCsmaInit->nBuCounterSeed >> 8); - - /* CSMA BU counter seed (LSB) config */ - tempRegValue[1] = (uint8_t) pxCsmaInit->nBuCounterSeed; - - /* CSMA BU prescaler config and CCA period config */ - tempRegValue[2] = (pxCsmaInit->cBuPrescaler << 2) | pxCsmaInit->xMultiplierTbit; - - /* CSMA CCA length config and max number of back-off */ - tempRegValue[3] = (pxCsmaInit->xCcaLength | pxCsmaInit->cMaxNb); - - /* Reads the PROTOCOL1_BASE register value, to write the SEED_RELOAD and CSMA_PERS_ON fields */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[4]); - - /* Writes the new value for persistent mode */ - if(pxCsmaInit->xCsmaPersistentMode==S_ENABLE) - { - tempRegValue[4] |= PROTOCOL1_CSMA_PERS_ON_MASK; - } - else - { - tempRegValue[4] &= ~PROTOCOL1_CSMA_PERS_ON_MASK; - } - - /* Writes PROTOCOL1_BASE register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue[4]); - - /* Writes CSMA_CONFIGx_BASE registers */ - g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG3_BASE, 4, tempRegValue); - -} - - - /** - * @brief Returns the fitted structure CsmaInit starting from the registers values. - * @param pxCsmaInit Csma structure to be fitted. - * This parameter is a pointer to @ref CsmaInit. - * @retval None. - */ -void SpiritCsmaGetInfo(CsmaInit* pxCsmaInit) -{ - uint8_t tempRegValue[5]; - - /* Reads PROTOCOL1_BASE register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[4]); - - /* Reads CSMA_CONFIGx_BASE registers */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG3_BASE, 4, tempRegValue); - - /* Reads the bu counter seed */ - pxCsmaInit->nBuCounterSeed = (uint16_t)tempRegValue[1] | ((uint16_t)(tempRegValue[0] << 8)); - - /* Reads the bu prescaler */ - pxCsmaInit->cBuPrescaler = tempRegValue[2]>>2; - - /* Reads the Cca period */ - pxCsmaInit->xMultiplierTbit = (CcaPeriod)(tempRegValue[2] & 0x03); - - /* Reads the Cca length */ - pxCsmaInit->xCcaLength = (CsmaLength)(tempRegValue[3]&0xF0); - - /* Reads the max number of back off */ - pxCsmaInit->cMaxNb = tempRegValue[3] & 0x07; - - /* Reads the persistent mode enable bit */ - pxCsmaInit->xCsmaPersistentMode = (SpiritFunctionalState)((tempRegValue[4]>>1) & 0x01); - -} - - -/** - * @brief Enables or Disables the CSMA. - * @param xNewState the state of the CSMA mode. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritCsma(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PROTOCOL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Sets or resets the CSMA enable bit */ - if(xNewState==S_ENABLE) - { - tempRegValue |= PROTOCOL1_CSMA_ON_MASK; - } - else - { - tempRegValue &= ~PROTOCOL1_CSMA_ON_MASK; - } - - /* Writes the new value on the PROTOCOL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - -} - -/** - * @brief Gets the CSMA mode. Says if it is enabled or disabled. - * @param None. - * @retval SpiritFunctionalState: CSMA mode. - */ -SpiritFunctionalState SpiritCsmaGetCsma(void) -{ - uint8_t tempRegValue; - - /* Reads the PROTOCOL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Return if set or reset */ - if(tempRegValue & PROTOCOL1_CSMA_ON_MASK) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - -/** - * @brief Enables or Disables the persistent CSMA mode. - * @param xNewState the state of the persistent CSMA mode. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritCsmaPersistentMode(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PROTOCOL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Enables/disables the CSMA persistent mode */ - if(xNewState==S_ENABLE) - { - tempRegValue |= PROTOCOL1_CSMA_PERS_ON_MASK; - } - else - { - tempRegValue &= ~PROTOCOL1_CSMA_PERS_ON_MASK; - } - - /* Writes the new vaue on the PROTOCOL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Gets the persistent CSMA mode. - * @param None. - * @retval SpiritFunctionalState: CSMA persistent mode. - */ -SpiritFunctionalState SpiritCsmaGetPersistentMode(void) -{ - uint8_t tempRegValue; - - /* Reads the PROTOCOL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Return if set or reset */ - if(tempRegValue & PROTOCOL1_CSMA_PERS_ON_MASK) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - - -/** - * @brief Enables or Disables the seed reload mode (if enabled it reloads the back-off generator seed using the value written in the BU_COUNTER_SEED register). - * @param xNewState the state of the seed reload mode. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritCsmaSeedReloadMode(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PROTOCOL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Enables/disables the seed reload mode */ - if(xNewState==S_ENABLE) - { - tempRegValue |= PROTOCOL1_SEED_RELOAD_MASK; - } - else - { - tempRegValue &= ~PROTOCOL1_SEED_RELOAD_MASK; - } - - /* Writes the new value on the PROTOCOL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Gets the seed reload mode. - * @param None. - * @retval SpiritFunctionalState: CSMA seed reload mode. - */ -SpiritFunctionalState SpiritCsmaGetSeedReloadMode(void) -{ - uint8_t tempRegValue; - - /* Reads the PROTOCOL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Return if set or reset */ - if(tempRegValue & PROTOCOL1_SEED_RELOAD_MASK) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } -} - - -/** - * @brief Sets the BU counter seed (BU_COUNTER_SEED register). The CSMA back off time is given by the formula: BO = rand(2^NB)*BU. - * @param nBuCounterSeed seed of the random number generator used to apply the BBE algorithm. - * This parameter is an uint16_t. - * @retval None. - */ -void SpiritCsmaSetBuCounterSeed(uint16_t nBuCounterSeed) -{ - uint8_t tempRegValue[2]; - - /* Check parameters */ - s_assert_param(IS_BU_COUNTER_SEED(nBuCounterSeed)); - - /* Build value (MSB)*/ - tempRegValue[0]=(uint8_t)(nBuCounterSeed>>8); - /* Build value (LSB) */ - tempRegValue[1]=(uint8_t)nBuCounterSeed; - - /* Writes the CSMA_CONFIG3 registers */ - g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG3_BASE, 2, tempRegValue); - -} - -/** - * @brief Returns the BU counter seed (BU_COUNTER_SEED register). - * @param None. - * @retval uint16_t Seed of the random number generator used to apply the BBE algorithm. - */ -uint16_t SpiritCsmaGetBuCounterSeed(void) -{ - uint8_t tempRegValue[2]; - - /* Reads the CSMA_CONFIGx registers value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG3_BASE, 2, tempRegValue); - - /* Build the counter seed and return it */ - return ((uint16_t)tempRegValue[1] + (((uint16_t)tempRegValue[0])<<8)); - -} - - -/** - * @brief Sets the BU prescaler. The CSMA back off time is given by the formula: BO = rand(2^NB)*BU. - * @param cBuPrescaler used to program the back-off unit BU. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritCsmaSetBuPrescaler(uint8_t cBuPrescaler) -{ - uint8_t tempRegValue; - - /* Check parameters */ - s_assert_param(IS_BU_PRESCALER(cBuPrescaler)); - - /* Reads the CSMA_CONFIG1 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); - - /* Build the new value for the BU prescaler */ - tempRegValue &= 0x03; - tempRegValue |= (cBuPrescaler<<2); - - /* Writes the new value on the CSMA_CONFIG1_BASE register */ - g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the BU prescaler. - * @param None. - * @retval uint8_t Value back-off unit (BU). - */ -uint8_t SpiritCsmaGetBuPrescaler(void) -{ - uint8_t tempRegValue; - - /* Reads the CSMA_CONFIG1 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); - - /* Build and return the BU prescaler value */ - return (tempRegValue >> 2); - -} - - -/** - * @brief Sets the CCA period. - * @param xMultiplierTbit value of CCA period to store. - * This parameter can be a value of @ref CcaPeriod. - * @retval None. - */ -void SpiritCsmaSetCcaPeriod(CcaPeriod xMultiplierTbit) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_CCA_PERIOD(xMultiplierTbit)); - - /* Reads the CSMA_CONFIG1 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); - - /* Build the new value setting the the CCA period */ - tempRegValue &= 0xFC; - tempRegValue |= xMultiplierTbit; - - /* Writes the new value on the CSMA_CONFIG1 register */ - g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the CCA period. - * @param None. - * @retval CcaPeriod CCA period. - */ -CcaPeriod SpiritCsmaGetCcaPeriod(void) -{ - uint8_t tempRegValue; - - /* Reads the CSMA_CONFIG1 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG1_BASE, 1, &tempRegValue); - - /* Build and return the CCA period value */ - return (CcaPeriod)(tempRegValue & 0x03); - -} - - -/** - * @brief Sets the CCA length. - * @param xCcaLength the CCA length (a value between 1 and 15 that multiplies the CCA period). - * This parameter can be any value of @ref CsmaLength. - * @retval None. - */ -void SpiritCsmaSetCcaLength(CsmaLength xCcaLength) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_CSMA_LENGTH(xCcaLength)); - - /* Reads the CSMA_CONFIG0 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); - - /* Build the value of CCA length to be set */ - tempRegValue &= 0x0F; - tempRegValue |= xCcaLength; - - /* Writes the new value on the CSMA_CONFIG0 register */ - g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the CCA length. - * @param None. - * @retval uint8_t CCA length. - */ -uint8_t SpiritCsmaGetCcaLength(void) -{ - uint8_t tempRegValue; - - /* Reads the CSMA_CONFIG0 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); - - /* Build and return the CCA length */ - return tempRegValue >> 4; - -} - - -/** - * @brief Sets the max number of back-off. If reached Spirit stops the transmission. - * @param cMaxNb the max number of back-off. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritCsmaSetMaxNumberBackoff(uint8_t cMaxNb) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_CMAX_NB(cMaxNb)); - - /* Reads the CSMA_CONFIG0 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); - - /* Build the value of max back off to be set */ - tempRegValue &= 0xF8; - tempRegValue |= cMaxNb; - - /* Writes the new value on the CSMA_CONFIG0 register */ - g_xStatus = SpiritSpiWriteRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); -} - -/** - * @brief Returns the max number of back-off. - * @param None. - * @retval uint8_t Max number of back-off. - */ -uint8_t SpiritCsmaGetMaxNumberBackoff(void) -{ - uint8_t tempRegValue; - - /* Reads the CSMA_CONFIG0 register value */ - g_xStatus = SpiritSpiReadRegisters(CSMA_CONFIG0_BASE, 1, &tempRegValue); - - /* Build and return the max number of back-off */ - return (tempRegValue & 0x07); - -} - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_DirectRF.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_DirectRF.c deleted file mode 100644 index 38e7fcdbf..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_DirectRF.c +++ /dev/null @@ -1,215 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_DirectRF.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT direct transmission / receive modes. - * @details - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_DirectRF.h" -#include "MCU_Interface.h" - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_DirectRf - * @{ - */ - - -/** - * @defgroup DirectRf_Private_TypesDefinitions Direct RF Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup DirectRf_Private_Defines Direct RF Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup DirectRf_Private_Macros Direct RF Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup DirectRf_Private_Variables Direct RF Private Variables - * @{ - */ - -/** - *@} - */ - - - -/** - * @defgroup DirectRf_Private_FunctionPrototypes Direct RF Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup DirectRf_Private_Functions Direct RF Private Functions - * @{ - */ - -/** - * @brief Sets the DirectRF RX mode of SPIRIT. - * @param xDirectRx code of the desired mode. - * This parameter can be any value of @ref DirectRx. - * @retval None. - */ -void SpiritDirectRfSetRxMode(DirectRx xDirectRx) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_DIRECT_RX(xDirectRx)); - - /* Reads the register value */ - SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Build the value to be stored */ - tempRegValue &= ~PCKTCTRL3_RX_MODE_MASK; - tempRegValue |= (uint8_t)xDirectRx; - - /* Writes value on register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the DirectRF RX mode of SPIRIT. - * @param None. - * @retval DirectRx Direct Rx mode. - */ -DirectRx SpiritDirectRfGetRxMode(void) -{ - uint8_t tempRegValue; - - /* Reads the register value and mask the RX_Mode field */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Rebuild and return value */ - return (DirectRx)(tempRegValue & 0x30); - -} - - -/** - * @brief Sets the TX mode of SPIRIT. - * @param xDirectTx code of the desired source. - * This parameter can be any value of @ref DirectTx. - * @retval None. - */ -void SpiritDirectRfSetTxMode(DirectTx xDirectTx) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_DIRECT_TX(xDirectTx)); - - /* Reads the register value */ - SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Build the value to be stored */ - tempRegValue &= ~PCKTCTRL1_TX_SOURCE_MASK; - tempRegValue |= (uint8_t)xDirectTx; - - /* Writes value on register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the DirectRF TX mode of SPIRIT. - * @param None. - * @retval DirectTx Direct Tx mode. - */ -DirectTx SpiritDirectRfGetTxMode(void) -{ - uint8_t tempRegValue; - - /* Reads the register value and mask the RX_Mode field */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Returns value */ - return (DirectTx)(tempRegValue & 0x0C); - -} - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_General.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_General.c deleted file mode 100644 index 8bcb4337b..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_General.c +++ /dev/null @@ -1,449 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_General.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT General functionalities. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_General.h" -#include "MCU_Interface.h" - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_General - * @{ - */ - - -/** - * @defgroup General_Private_TypesDefinitions General Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup General_Private_Defines General Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup General_Private_Macros General Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup General_Private_Variables General Private Variables - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup General_Private_FunctionPrototypes General Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup General_Private_Functions General Private Functions - * @{ - */ - -/** - * @brief Enables or Disables the output of battery level detector. - * @param xNewState new state for battery level detector. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None - */ -void SpiritGeneralBatteryLevel(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the ANA_FUNC_CONF0_BASE register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - - /* Build the value to be stored */ - if(xNewState == S_ENABLE) - { - tempRegValue |= BATTERY_LEVEL_MASK; - } - else - { - tempRegValue &= ~BATTERY_LEVEL_MASK; - } - - /* Writes the new value */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets the battery level. - * @param xBatteryLevel new state for battery level. - * This parameter can be a value of @ref BatteryLevel. - * @retval None. - */ -void SpiritGeneralSetBatteryLevel(BatteryLevel xBatteryLevel) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_BLD_LVL(xBatteryLevel)); - - /* Reads the ANA_FUNC_CONF1_BASE register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); - - /* Build the value to be stored */ - tempRegValue &= ~ANA_FUNC_CONF1_SET_BLD_LVL_MASK; - switch(xBatteryLevel) - { - case BLD_LVL_2_7_V: - tempRegValue |= BLD_LVL_2_7; - break; - case BLD_LVL_2_5_V: - tempRegValue |= BLD_LVL_2_5; - break; - case BLD_LVL_2_3_V: - tempRegValue |= BLD_LVL_2_3; - break; - case BLD_LVL_2_1_V: - tempRegValue |= BLD_LVL_2_1; - break; - } - - /* Writes the new value */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the settled battery level. - * @param None. - * @retval BatteryLevel Settled battery level. This parameter can be a value of @ref BatteryLevel. - */ -BatteryLevel SpiritGeneralGetBatteryLevel(void) -{ - uint8_t tempRegValue; - - /* Reads the ANA_FUNC_CONF1_BASE register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); - - /* Mask the battery level field and returns the settled battery level */ - return ((BatteryLevel)(tempRegValue & ANA_FUNC_CONF1_SET_BLD_LVL_MASK)); - -} - - -/** - * @brief Enables or Disables the output of brown out detector. - * @param xNewState new state for brown out detector. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritGeneralBrownOut(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the ANA_FUNC_CONF0_BASE register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - - /* Build the value to be stored */ - if(xNewState == S_ENABLE) - { - tempRegValue |= BROWN_OUT_MASK; - } - else - { - tempRegValue &= ~BROWN_OUT_MASK; - } - - /* Writes value on register */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets High Power Mode. - * @param xNewState new state for High Power Mode. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritGeneralHighPwr(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the ANA_FUNC_CONF0_BASE register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - - /* Build the value to write */ - if(xNewState == S_ENABLE) - { - tempRegValue |= HIGH_POWER_MODE_MASK; - } - else - { - tempRegValue &= ~HIGH_POWER_MODE_MASK; - } - - /* Writes the new value on register */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets External Reference. - * @param xExtMode new state for the external reference. - * This parameter can be: MODE_EXT_XO or MODE_EXT_XIN. - * @retval None. - */ -void SpiritGeneralSetExtRef(ModeExtRef xExtMode) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_MODE_EXT(xExtMode)); - - /* Reads the ANA_FUNC_CONF0_BASE register value */ - SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - - /* Build the value to write */ - if(xExtMode == MODE_EXT_XO) - { - tempRegValue &= ~EXT_REF_MASK; - } - else - { - tempRegValue |= EXT_REF_MASK; - } - - /* Writes value on register */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns External Reference. - * @param None. - * @retval ModeExtRef Settled external reference. - * This parameter can be: MODE_EXT_XO or MODE_EXT_XIN. - */ -ModeExtRef SpiritGeneralGetExtRef(void) -{ - uint8_t tempRegValue; - - /* Reads the ANA_FUNC_CONF0_BASE register value and return the result */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - - /* Mask the EXT_REF field field and returns the settled reference signal */ - return ((ModeExtRef)((tempRegValue & 0x10)>>4)); - -} - - -/** - * @brief Sets XO gm at startup. - * @param xGm transconductance value of XO at startup. - * This parameter can be a value of @ref GmConf. - * @retval None. - */ -void SpiritGeneralSetXoGm(GmConf xGm) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_GM_CONF(xGm)); - - /* Reads the ANA_FUNC_CONF1_BASE register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); - - /* Build the value to write */ - tempRegValue &= ~ANA_FUNC_CONF1_GMCONF_MASK; - switch(xGm) - { - case GM_SU_13_2: - tempRegValue |= GM_13_2; - break; - case GM_SU_18_2: - tempRegValue |= GM_18_2; - break; - case GM_SU_21_5: - tempRegValue |= GM_21_5; - break; - case GM_SU_25_6: - tempRegValue |= GM_25_6; - break; - case GM_SU_28_8: - tempRegValue |= GM_28_8; - break; - case GM_SU_33_9: - tempRegValue |= GM_33_9; - break; - case GM_SU_38_5: - tempRegValue |= GM_38_5; - break; - case GM_SU_43_0: - tempRegValue |= GM_43_0; - break; - } - - /* Writes new value on register */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the configured XO gm at startup. - * @param None. - * @retval GmConf Settled XO gm. This parameter can be a value of @ref GmConf. - */ -GmConf SpiritGeneralGetXoGm(void) -{ - uint8_t tempRegValue; - - /* Reads the ANA_FUNC_CONF1_BASE register value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF1_BASE, 1, &tempRegValue); - - /* Mask the GM_CONF field field and returns the settled transconductance of the XO at startup */ - return ((GmConf)((tempRegValue & 0x1C)>>2)); - -} - - -/** - * @brief Returns the settled packet format. - * @param None. - * @retval PacketType Settled packet type. This parameter can be a value of @ref PacketType. - */ -PacketType SpiritGeneralGetPktType(void) -{ - uint8_t tempRegValue; - - /* Reads the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* cast and return value */ - return (PacketType)(tempRegValue>>6); - -} - - - -/** - * @brief Returns device part number. - * @param None. - * @retval uint16_t Device part number. - */ -uint16_t SpiritGeneralGetDevicePartNumber(void) -{ - uint8_t tempRegValue[2]; - - /* Reads the register value containing the device part number */ - g_xStatus = SpiritSpiReadRegisters(DEVICE_INFO1_PARTNUM, 2, tempRegValue); - - return ((((uint16_t)tempRegValue[0])<<8) | ((uint16_t)tempRegValue[1])); - -} - -/** - * @brief Returns SPIRIT RF board version. - * @param None. - * @retval SPIRIT RF board version: 0x30 is the only admitted value - */ -uint8_t SpiritGeneralGetSpiritVersion(void) -{ - uint8_t ver; - SpiritSpiReadRegisters(DEVICE_INFO0_VERSION, 1, &ver); - return ver; -} - -/** - *@} - */ - - -/** - *@} - */ - - -/** - *@} - */ - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Gpio.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Gpio.c deleted file mode 100644 index d2a15dd96..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Gpio.c +++ /dev/null @@ -1,458 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Gpio.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief This file provides all the low level API to manage SPIRIT GPIO. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Gpio.h" -#include "MCU_Interface.h" - - -/** @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** @addtogroup SPIRIT_Gpio - * @{ - */ - - -/** @defgroup Gpio_Private_TypesDefinitions GPIO Private Types Definitions - * @{ - */ - - -/** - * @} - */ - - -/** @defgroup Gpio_Private_Defines GPIO Private Defines - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Gpio_Private_Macros GPIO Private Macros - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Gpio_Private_Variables GPIO Private Variables - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Gpio_Private_FunctionPrototypes GPIO Private Function Prototypes - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Gpio_Private_Functions GPIO Private Functions - * @{ - */ - -/** - * @brief Initializes the SPIRIT GPIOx according to the specified - * parameters in the pxGpioInitStruct. - * @param pxGpioInitStruct pointer to a SGpioInit structure that - * contains the configuration information for the specified SPIRIT GPIO. - * @retval None. - */ -void SpiritGpioInit(SGpioInit* pxGpioInitStruct) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_GPIO(pxGpioInitStruct->xSpiritGpioPin)); - s_assert_param(IS_SPIRIT_GPIO_MODE(pxGpioInitStruct->xSpiritGpioMode)); - s_assert_param(IS_SPIRIT_GPIO_IO(pxGpioInitStruct->xSpiritGpioIO)); - - tempRegValue = ((uint8_t)(pxGpioInitStruct->xSpiritGpioMode) | (uint8_t)(pxGpioInitStruct->xSpiritGpioIO)); - - g_xStatus = SpiritSpiWriteRegisters(pxGpioInitStruct->xSpiritGpioPin, 1, &tempRegValue); - -} - - -/** - * @brief Enables or Disables the output of temperature sensor on SPIRIT GPIO_0. - * @param xNewState new state for temperature sensor. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritGpioTemperatureSensor(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - uint8_t gpio0tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the ANA_FUNC_CONF0 register and mask the result to enable or disable the - temperature sensor */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= TEMPERATURE_SENSOR_MASK; - } - else - { - tempRegValue &= (~TEMPERATURE_SENSOR_MASK); - gpio0tempRegValue = 0x0A; /* Default value */ - } - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - - /* Sets the SPIRIT GPIO_0 according to input request */ - g_xStatus = SpiritSpiWriteRegisters(GPIO0_CONF_BASE, 1, &gpio0tempRegValue); - -} - - -/** - * @brief Forces SPIRIT GPIO_x configured as digital output, to VDD or GND. - * @param xGpioX Specifies the GPIO to be configured. - * This parameter can be one of following parameters: - * @arg SPIRIT_GPIO_0: SPIRIT GPIO_0 - * @arg SPIRIT_GPIO_1: SPIRIT GPIO_1 - * @arg SPIRIT_GPIO_2: SPIRIT GPIO_2 - * @arg SPIRIT_GPIO_3: SPIRIT GPIO_3 - * @param xLevel Specifies the level. - * This parameter can be: HIGH or LOW. - * @retval None. - */ -void SpiritGpioSetLevel(SpiritGpioPin xGpioX, OutputLevel xLevel) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_GPIO(xGpioX)); - s_assert_param(IS_SPIRIT_GPIO_LEVEL(xLevel)); - - /* Reads the SPIRIT_GPIOx register and mask the GPIO_SELECT field */ - g_xStatus = SpiritSpiReadRegisters(xGpioX, 1, &tempRegValue); - tempRegValue &= 0x04; - - /* Sets the value of the SPIRIT GPIO register according to the specified level */ - if(xLevel == HIGH) - { - tempRegValue |= (uint8_t)SPIRIT_GPIO_DIG_OUT_VDD | (uint8_t)SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP; - } - else - { - tempRegValue |= (uint8_t)SPIRIT_GPIO_DIG_OUT_GND | (uint8_t)SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_HP; - } - - /* Writes the SPIRIT GPIO register */ - g_xStatus = SpiritSpiWriteRegisters(xGpioX, 1, &tempRegValue); - -} - - -/** - * @brief Returns output value (VDD or GND) of SPIRIT GPIO_x, when it is configured as digital output. - * @param xGpioX Specifies the GPIO to be read. - * This parameter can be one of following parameters: - * @arg SPIRIT_GPIO_0: SPIRIT GPIO_0 - * @arg SPIRIT_GPIO_1: SPIRIT GPIO_1 - * @arg SPIRIT_GPIO_2: SPIRIT GPIO_2 - * @arg SPIRIT_GPIO_3: SPIRIT GPIO_3 - * @retval OutputLevel Logical level of selected GPIO configured as digital output. - * This parameter can be: HIGH or LOW. - */ -OutputLevel SpiritGpioGetLevel(SpiritGpioPin xGpioX) -{ - uint8_t tempRegValue = 0x00; - OutputLevel level; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_GPIO(xGpioX)); - - /* Reads the SPIRIT_GPIOx register */ - g_xStatus = SpiritSpiReadRegisters(xGpioX, 1, &tempRegValue); - - /* Mask the GPIO_SELECT field and returns the value according */ - tempRegValue &= 0xF8; - if(tempRegValue == SPIRIT_GPIO_DIG_OUT_VDD) - { - level = HIGH; - } - else - { - level = LOW; - } - - return level; - -} - - -/** - * @brief Enables or Disables the MCU clock output. - * @param xNewState new state for the MCU clock output. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritGpioClockOutput(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the MCU_CK_CONF register and mask the result to enable or disable the clock output */ - g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - - if(xNewState) - { - tempRegValue |= MCU_CK_ENABLE; - } - else - { - tempRegValue &= (~MCU_CK_ENABLE); - } - - /* Writes the MCU_CK_CONF register */ - g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Initializes the SPIRIT Clock Output according to the specified - * parameters in the xClockOutputInitStruct. - * @param pxClockOutputInitStruct pointer to a ClockOutputInit structure that - * contains the configuration information for the SPIRIT Clock Output. - * @retval None. - * @note The function SpiritGpioClockOutput() must be called in order to enable - * or disable the MCU clock dividers. - */ -void SpiritGpioClockOutputInit(ClockOutputInit* pxClockOutputInitStruct) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_XO(pxClockOutputInitStruct->xClockOutputXOPrescaler)); - s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_RCO(pxClockOutputInitStruct->xClockOutputRCOPrescaler)); - s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_EXTRA_CYCLES(pxClockOutputInitStruct->xExtraClockCycles)); - - /* Calculates the register value to write according to the specified configuration */ - tempRegValue = ((uint8_t)(pxClockOutputInitStruct->xClockOutputXOPrescaler) | (uint8_t)(pxClockOutputInitStruct->xClockOutputRCOPrescaler) | \ - (uint8_t)(pxClockOutputInitStruct->xExtraClockCycles)); - - /* Writes the MCU_CLOCK register */ - g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets the XO ratio as clock output. - * @param xXOPrescaler the XO prescaler to be used as clock output. - * This parameter can be any value of @ref ClockOutputXOPrescaler . - * @retval None - */ -void SpiritGpioSetXOPrescaler(ClockOutputXOPrescaler xXOPrescaler) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_XO(xXOPrescaler)); - - /* Reads the MCU_CLK_CONFIG register */ - g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - - /* Mask the XO_RATIO field and writes the new value */ - tempRegValue &= 0x61; - tempRegValue |= ((uint8_t)xXOPrescaler); - - /* Writes the new XO prescaler in the MCU_CLOCK register */ - g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the settled XO prescaler as clock output. - * @param None. - * @retval ClockOutputXOPrescaler Settled XO prescaler used for clock - * output. This parameter can be a value of @ref ClockOutputXOPrescaler . - */ -ClockOutputXOPrescaler SpiritGpioGetXOPrescaler(void) -{ - uint8_t tempRegValue = 0x00; - - /* Reads the MCU_CLK_CONFIG register */ - g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - - /* Mask the XO_RATIO field and return the value */ - return ((ClockOutputXOPrescaler)(tempRegValue & 0x1E)); - -} - - -/** - * @brief Sets the RCO ratio as clock output - * @param xRCOPrescaler the RCO prescaler to be used as clock output. - * This parameter can be any value of @ref ClockOutputRCOPrescaler . - * @retval None. - */ -void SpiritGpioSetRCOPrescaler(ClockOutputRCOPrescaler xRCOPrescaler) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_RCO(xRCOPrescaler)); - - /* Reads the MCU_CLK_CONFIG register */ - g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - - /* Mask the RCO_RATIO field and writes the new value */ - tempRegValue &= 0xFE; - tempRegValue |= ((uint8_t)xRCOPrescaler); - - /* Writes the new RCO prescaler in the MCU_CLOCK register */ - g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the settled RCO prescaler as clock output. - * @param None. - * @retval ClockOutputRCOPrescaler Settled RCO prescaler used for clock - * output. This parameter can be a value of @ref ClockOutputRCOPrescaler. - */ -ClockOutputRCOPrescaler SpiritGpioGetRCOPrescaler(void) -{ - uint8_t tempRegValue = 0x00; - - /* Reads the MCU_CLK_CONFIG register */ - g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - - /* Mask the RCO_RATIO field and returns the value */ - return ((ClockOutputRCOPrescaler)(tempRegValue & 0x01)); - -} - - -/** - * @brief Sets the RCO ratio as clock output. - * @param xExtraCycles the number of extra clock cycles provided before switching - * to STANDBY state. This parameter can be any value of @ref ExtraClockCycles . - * @retval None. - */ -void SpiritGpioSetExtraClockCycles(ExtraClockCycles xExtraCycles) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_CLOCK_OUTPUT_EXTRA_CYCLES(xExtraCycles)); - - /* Reads the MCU_CLK_CONFIG register */ - g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - - /* Mask the CLOCK_TAIL field and writes the new value */ - tempRegValue &= 0x9F; - tempRegValue |= ((uint8_t)xExtraCycles); - - /* Writes the new number of extra clock cycles in the MCU_CLOCK register */ - g_xStatus = SpiritSpiWriteRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the settled RCO prescaler as clock output. - * @param None. - * @retval ExtraClockCycles Settled number of extra clock cycles - * provided before switching to STANDBY state. This parameter can be - * any value of @ref ExtraClockCycles . - */ -ExtraClockCycles SpiritGpioGetExtraClockCycles(void) -{ - uint8_t tempRegValue = 0x00; - - /* Reads the MCU_CLK_CONFIG register */ - g_xStatus = SpiritSpiReadRegisters(MCU_CK_CONF_BASE, 1, &tempRegValue); - - /* Mask the CLOCK_TAIL field and returns the value */ - return ((ExtraClockCycles)(tempRegValue & 0x60)); - -} - - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Irq.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Irq.c deleted file mode 100644 index 8ef9d9061..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Irq.c +++ /dev/null @@ -1,353 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Irq.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT IRQs. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Irq.h" -#include "MCU_Interface.h" - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_Irq - * @{ - */ - - -/** - * @defgroup Irq_Private_TypesDefinitions IRQ Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Irq_Private_Defines IRQ Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Irq_Private_Macros IRQ Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Irq_Private_Variables IRQ Private Variables - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup Irq_Private_FunctionPrototypes IRQ Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Irq_Private_Functions IRQ Private Functions - * @{ - */ - - -/** - * @brief De initializate the SpiritIrqs structure setting all the bitfield to 0. - * Moreover, it sets the IRQ mask registers to 0x00000000, disabling all IRQs. - * @param pxIrqInit pointer to a variable of type @ref SpiritIrqs, in which all the - * bitfields will be settled to zero. - * @retval None. - */ -void SpiritIrqDeInit(SpiritIrqs* pxIrqInit) -{ - uint8_t tempRegValue[4]={0x00,0x00,0x00,0x00}; - - if(pxIrqInit!=NULL) - { - uint32_t tempValue = 0x00000000; - - /* Sets the bitfields of passed structure to one */ - *pxIrqInit = (*(SpiritIrqs*)&tempValue); - } - - /* Writes the IRQ_MASK registers */ - g_xStatus = SpiritSpiWriteRegisters(IRQ_MASK3_BASE, 4, tempRegValue); -} - - -/** - * @brief Enables all the IRQs according to the user defined pxIrqInit structure. - * @param pxIrqInit pointer to a variable of type @ref SpiritIrqs, through which the - * user enable specific IRQs. This parameter is a pointer to a SpiritIrqs. - * For example suppose to enable only the two IRQ Low Battery Level and Tx Data Sent: - * @code - * SpiritIrqs myIrqInit = {0}; - * myIrqInit.IRQ_LOW_BATT_LVL = 1; - * myIrqInit.IRQ_TX_DATA_SENT = 1; - * SpiritIrqInit(&myIrqInit); - * @endcode - * @retval None. - */ -void SpiritIrqInit(SpiritIrqs* pxIrqInit) -{ - uint8_t tempRegValue[4]; - uint8_t* tmpPoint; - - /* Cast the bitfields structure in an array of char using */ - tmpPoint = (uint8_t*)(pxIrqInit); - for(char i=0; i<4; i++) - { - tempRegValue[3-i]= tmpPoint[i]; - } - - /* Writes the IRQ_MASK registers */ - g_xStatus = SpiritSpiWriteRegisters(IRQ_MASK3_BASE, 4, tempRegValue); - -} - - -/** - * @brief Enables or disables a specific IRQ. - * @param xIrq IRQ to enable or disable. - * This parameter can be any value of @ref IrqList. - * @param xNewState new state for the IRQ. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritIrq(IrqList xIrq, SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue[4]; - uint32_t tempValue = 0; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_IRQ_LIST(xIrq)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the IRQ_MASK registers */ - g_xStatus = SpiritSpiReadRegisters(IRQ_MASK3_BASE, 4, tempRegValue); - - /* Build the IRQ mask word */ - for(char i=0; i<4; i++) - { - tempValue += ((uint32_t)tempRegValue[i])<<(8*(3-i)); - } - - /* Rebuild the new mask according to user request */ - if(xNewState == S_DISABLE) - { - tempValue &= (~xIrq); - } - else - { - tempValue |= (xIrq); - } - - /* Build the array of bytes to write in the IRQ_MASK registers */ - for(char j=0; j<4; j++) - { - tempRegValue[j] = (uint8_t)(tempValue>>(8*(3-j))); - } - - /* Writes the new IRQ mask in the corresponding registers */ - g_xStatus = SpiritSpiWriteRegisters(IRQ_MASK3_BASE, 4, tempRegValue); - -} - - -/** - * @brief Fills a pointer to a structure of SpiritIrqs type reading the IRQ_MASK registers. - * @param pxIrqMask pointer to a variable of type @ref SpiritIrqs, through which the - * user can read which IRQs are enabled. All the bitfields equals to zero correspond - * to enabled IRQs, while all the bitfields equals to one correspond to disabled IRQs. - * This parameter is a pointer to a SpiritIrqs. - * For example suppose that the Power On Reset and RX Data ready are the only enabled IRQs. - * @code - * SpiritIrqs myIrqMask; - * SpiritIrqGetStatus(&myIrqMask); - * @endcode - * Then - * myIrqMask.IRQ_POR and myIrqMask.IRQ_RX_DATA_READY are equal to 0 - * while all the other bitfields are equal to one. - * @retval None. - */ -void SpiritIrqGetMask(SpiritIrqs* pxIrqMask) -{ - uint8_t tempRegValue[4]; - uint8_t* pIrqPointer = (uint8_t*)pxIrqMask; - - /* Reads IRQ_MASK registers */ - g_xStatus = SpiritSpiReadRegisters(IRQ_MASK3_BASE, 4, tempRegValue); - - /* Build the IRQ mask word */ - for(char i=0; i<4; i++) - { - *pIrqPointer = tempRegValue[3-i]; - pIrqPointer++; - } - -} - - -/** - * @brief Filla a pointer to a structure of SpiritIrqs type reading the IRQ_STATUS registers. - * @param pxIrqStatus pointer to a variable of type @ref SpiritIrqs, through which the - * user can read the status of all the IRQs. All the bitfields equals to one correspond - * to the raised interrupts. This parameter is a pointer to a SpiritIrqs. - * For example suppose that the XO settling timeout is raised as well as the Sync word - * detection. - * @code - * SpiritIrqs myIrqStatus; - * SpiritIrqGetStatus(&myIrqStatus); - * @endcode - * Then - * myIrqStatus.IRQ_XO_COUNT_EXPIRED and myIrqStatus.IRQ_VALID_SYNC are equals to 1 - * while all the other bitfields are equals to zero. - * @retval None. - */ -void SpiritIrqGetStatus(SpiritIrqs* pxIrqStatus) -{ - uint8_t tempRegValue[4]; - uint8_t* pIrqPointer = (uint8_t*)pxIrqStatus; - - /* Reads IRQ_STATUS registers */ - g_xStatus = SpiritSpiReadRegisters(IRQ_STATUS3_BASE, 4, tempRegValue); - - /* Build the IRQ Status word */ - for(uint8_t i=0; i<4; i++) - { - *pIrqPointer = tempRegValue[3-i]; - pIrqPointer++; - } -} - - -/** - * @brief Clear the IRQ status registers. - * @param None. - * @retval None. - */ -void SpiritIrqClearStatus(void) -{ - uint8_t tempRegValue[4]; - - /* Reads the IRQ_STATUS registers clearing all the flags */ - g_xStatus = SpiritSpiReadRegisters(IRQ_STATUS3_BASE, 4, tempRegValue); - -} - - -/** - * @brief Verifies if a specific IRQ has been generated. - * The call resets all the IRQ status, so it can't be used in case of multiple raising interrupts. - * @param xFlag IRQ flag to be checked. - * This parameter can be any value of @ref IrqList. - * @retval SpiritBool S_TRUE or S_FALSE. - */ -SpiritBool SpiritIrqCheckFlag(IrqList xFlag) -{ - uint8_t tempRegValue[4]; - uint32_t tempValue = 0; - SpiritBool flag; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_IRQ_LIST(xFlag)); - - /* Reads registers and build the status word */ - g_xStatus = SpiritSpiReadRegisters(IRQ_STATUS3_BASE, 4, tempRegValue); - for(uint8_t i=0; i<4; i++) - { - tempValue += ((uint32_t)tempRegValue[i])<<(8*(3-i)); - } - - if(tempValue & xFlag) - { - flag = S_TRUE; - } - else - { - flag = S_FALSE; - } - - return flag; - -} - - -/** - *@} - */ - - -/** - *@} - */ - - -/** - *@} - */ - - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_LinearFifo.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_LinearFifo.c deleted file mode 100644 index 755b76652..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_LinearFifo.c +++ /dev/null @@ -1,338 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_LinearFifo.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT Fifo. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_LinearFifo.h" -#include "MCU_Interface.h" - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_LinearFifo - * @{ - */ - - -/** - * @defgroup LinearFifo_Private_TypesDefinitions Linear FIFO Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup LinearFifo_Private_Defines Linear FIFO Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup LinearFifo_Private_Macros Linear FIFO Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup LinearFifo_Private_Variables Linear FIFO Private Variables - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup LinearFifo_Private_FunctionPrototypes Linear FIFO Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup LinearFifo_Private_Functions Linear FIFO Private Functions - * @{ - */ - -/** - * @brief Returns the number of elements in the Rx FIFO. - * @param None. - * @retval uint8_t Number of elements in the Rx FIFO. - */ -uint8_t SpiritLinearFifoReadNumElementsRxFifo(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(LINEAR_FIFO_STATUS0_BASE, 1, &tempRegValue); - - /* Build and return value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Returns the number of elements in the Tx FIFO. - * @param None. - * @retval uint8_t Number of elements in the Tx FIFO. - */ -uint8_t SpiritLinearFifoReadNumElementsTxFifo(void) -{ - uint8_t tempRegValue; - - /* Reads the number of elements in TX FIFO and return the value */ - g_xStatus = SpiritSpiReadRegisters(LINEAR_FIFO_STATUS1_BASE, 1, &tempRegValue); - - /* Build and return value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Sets the almost full threshold for the Rx FIFO. When the number of elements in RX FIFO reaches this value an interrupt can be generated to the MCU. - * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is set to 7 the almost - * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. - * @param cThrRxFifo almost full threshold. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritLinearFifoSetAlmostFullThresholdRx(uint8_t cThrRxFifo) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_FIFO_THR(cThrRxFifo)); - - /* Build the register value */ - tempRegValue = cThrRxFifo & 0x7F; - - /* Writes the Almost Full threshold for RX in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG3_RXAFTHR_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the almost full threshold for RX FIFO. - * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is 7 the almost - * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. - * @param None. - * @retval uint8_t Almost full threshold for Rx FIFO. - */ -uint8_t SpiritLinearFifoGetAlmostFullThresholdRx(void) -{ - uint8_t tempRegValue; - - /* Reads the almost full threshold for RX FIFO and return the value */ - g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG3_RXAFTHR_BASE, 1, &tempRegValue); - - /* Build and return value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Sets the almost empty threshold for the Rx FIFO. When the number of elements in RX FIFO reaches this value an interrupt can be generated to the MCU. - * @param cThrRxFifo almost empty threshold. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritLinearFifoSetAlmostEmptyThresholdRx(uint8_t cThrRxFifo) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_FIFO_THR(cThrRxFifo)); - - /* Build the register value */ - tempRegValue = cThrRxFifo & 0x7F; - - /* Writes the Almost Empty threshold for RX in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG2_RXAETHR_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the almost empty threshold for Rx FIFO. - * @param None. - * @retval uint8_t Almost empty threshold for Rx FIFO. - */ -uint8_t SpiritLinearFifoGetAlmostEmptyThresholdRx(void) -{ - uint8_t tempRegValue; - - /* Reads the almost empty threshold for RX FIFO and returns the value */ - g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG2_RXAETHR_BASE, 1, &tempRegValue); - - /* Build and return value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Sets the almost full threshold for the Tx FIFO. When the number of elements in TX FIFO reaches this value an interrupt can be generated to the MCU. - * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is set to 7 the almost - * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. - * @param cThrTxFifo almost full threshold. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritLinearFifoSetAlmostFullThresholdTx(uint8_t cThrTxFifo) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_FIFO_THR(cThrTxFifo)); - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG1_TXAFTHR_BASE, 1, &tempRegValue); - - /* Build the register value */ - tempRegValue &= 0x80; - tempRegValue |= cThrTxFifo; - - /* Writes the Almost Full threshold for Tx in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG1_TXAFTHR_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the almost full threshold for Tx FIFO. - * @note The almost full threshold is encountered from the top of the FIFO. For example, if it is set to 7 the almost - * full FIFO irq will be raised when the number of elements is equals to 96-7 = 89. - * @param None. - * @retval uint8_t Almost full threshold for Tx FIFO. - */ -uint8_t SpiritLinearFifoGetAlmostFullThresholdTx(void) -{ - uint8_t tempRegValue; - - /* Reads the almost full threshold for Tx FIFO and returns the value */ - g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG1_TXAFTHR_BASE, 1, &tempRegValue); - - /* Build and returns value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Sets the almost empty threshold for the Tx FIFO. When the number of elements in Tx FIFO reaches this value an interrupt can can be generated to the MCU. - * @param cThrTxFifo: almost empty threshold. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritLinearFifoSetAlmostEmptyThresholdTx(uint8_t cThrTxFifo) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_FIFO_THR(cThrTxFifo)); - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG0_TXAETHR_BASE, 1, &tempRegValue); - - /* Build the register value */ - tempRegValue &= 0x80; - tempRegValue |= cThrTxFifo; - - /* Writes the Almost Empty threshold for Tx in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(FIFO_CONFIG0_TXAETHR_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the almost empty threshold for Tx FIFO. - * @param None. - * @retval uint8_t Almost empty threshold for Tx FIFO. - */ -uint8_t SpiritLinearFifoGetAlmostEmptyThresholdTx(void) -{ - uint8_t tempRegValue; - - /* Reads the almost empty threshold for TX FIFO and returns the value */ - g_xStatus = SpiritSpiReadRegisters(FIFO_CONFIG0_TXAETHR_BASE, 1, &tempRegValue); - - /* Build and return value */ - return (tempRegValue & 0x7F); - -} - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Management.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Management.c deleted file mode 100644 index f851c1944..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Management.c +++ /dev/null @@ -1,364 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Management.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief The management layer for SPIRIT1 library. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Management.h" - -/** -* @addtogroup SPIRIT_Libraries -* @{ -*/ - - -/** -* @defgroup SPIRIT_MANAGEMENT SPIRIT Management -* @{ -*/ - -/** -* @brief BS value to write in the SYNT0 register according to the selected band -*/ -static const uint8_t s_vectcBandRegValue[4]={SYNT0_BS_6, SYNT0_BS_12, SYNT0_BS_16, SYNT0_BS_32}; - -#define COMMUNICATION_STATE_TX 0 -#define COMMUNICATION_STATE_RX 1 -#define COMMUNICATION_STATE_NONE 2 - -static uint32_t s_nDesiredFrequency; - -volatile static uint8_t s_cCommunicationState = COMMUNICATION_STATE_NONE; - - -/** -* @brief Factor is: B/2 used in the formula for SYNTH word calculation -*/ -static const uint8_t s_vectcBHalfFactor[4]={(HIGH_BAND_FACTOR/2), (MIDDLE_BAND_FACTOR/2), (LOW_BAND_FACTOR/2), (VERY_LOW_BAND_FACTOR/2)}; - - -/** -* @defgroup SPIRIT_MANAGEMENT_FUNCTIONS SPIRIT Management Functions -* @{ -*/ - - -/** -* @defgroup WORKAROUND_FUNCTIONS SPIRIT Management Workaround Functions -* @{ -*/ - -/** -* @brief Private SpiritRadioSetFrequencyBase function only used in SpiritManagementWaVcoCalibration. -* @param lFBase the base carrier frequency expressed in Hz as unsigned word. -* @retval None. -*/ -void SpiritManagementSetFrequencyBase(uint32_t lFBase) -{ - uint32_t synthWord, Fc; - uint8_t band, anaRadioRegArray[4], wcp; - - /* Check the parameter */ - s_assert_param(IS_FREQUENCY_BAND(lFBase)); - - /* Search the operating band */ - if(IS_FREQUENCY_BAND_HIGH(lFBase)) - { - band = HIGH_BAND; - } - else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) - { - band = MIDDLE_BAND; - } - else if(IS_FREQUENCY_BAND_LOW(lFBase)) - { - band = LOW_BAND; - } - else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) - { - band = VERY_LOW_BAND; - } - - int32_t FOffset = SpiritRadioGetFrequencyOffset(); - uint32_t lChannelSpace = SpiritRadioGetChannelSpace(); - uint8_t cChannelNum = SpiritRadioGetChannel(); - - /* Calculates the channel center frequency */ - Fc = lFBase + FOffset + lChannelSpace*cChannelNum; - - /* Reads the reference divider */ - uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; - - switch(band) - { - case VERY_LOW_BAND: - if(Fc<161281250) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - break; - - case LOW_BAND: - if(Fc<322562500) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - break; - - case MIDDLE_BAND: - if(Fc<430083334) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - break; - - case HIGH_BAND: - if(Fc<860166667) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - } - - /* Search the VCO charge pump word and set the corresponding register */ - wcp = SpiritRadioSearchWCP(Fc); - - synthWord = (uint32_t)(lFBase*(((double)(FBASE_DIVIDER*cRefDiv*s_vectcBHalfFactor[band]))/SpiritRadioGetXtalFrequency())); - - /* Build the array of registers values for the analog part */ - anaRadioRegArray[0] = (uint8_t)(((synthWord>>21)&(0x0000001F))|(wcp<<5)); - anaRadioRegArray[1] = (uint8_t)((synthWord>>13)&(0x000000FF)); - anaRadioRegArray[2] = (uint8_t)((synthWord>>5)&(0x000000FF)); - anaRadioRegArray[3] = (uint8_t)(((synthWord&0x0000001F)<<3)| s_vectcBandRegValue[band]); - - /* Configures the needed Analog Radio registers */ - g_xStatus = SpiritSpiWriteRegisters(SYNT3_BASE, 4, anaRadioRegArray); -} - -uint8_t SpiritManagementWaVcoCalibration(void) -{ - uint8_t s_cVcoWordRx; - uint8_t s_cVcoWordTx; - uint32_t nFreq; - uint8_t cRestore = 0; - uint8_t cStandby = 0; - uint32_t xtal_frequency = SpiritRadioGetXtalFrequency(); - - /* Enable the reference divider if the XTAL is between 48 and 52 MHz */ - if(xtal_frequency>DOUBLE_XTAL_THR) - { - if(!SpiritRadioGetRefDiv()) - { - cRestore = 1; - nFreq = SpiritRadioGetFrequencyBase(); - SpiritRadioSetRefDiv(S_ENABLE); - SpiritManagementSetFrequencyBase(nFreq); - } - } - nFreq = SpiritRadioGetFrequencyBase(); - - /* Increase the VCO current */ - uint8_t tmp = 0x19; SpiritSpiWriteRegisters(0xA1,1,&tmp); - - SpiritCalibrationVco(S_ENABLE); - - SpiritRefreshStatus(); - if(g_xStatus.MC_STATE == MC_STATE_STANDBY) - { - cStandby = 1; - SpiritCmdStrobeReady(); - do{ - SpiritRefreshStatus(); - if(g_xStatus.MC_STATE == 0x13) - { - return 1; - } - }while(g_xStatus.MC_STATE != MC_STATE_READY); - } - - SpiritCmdStrobeLockTx(); - - do{ - SpiritRefreshStatus(); - if(g_xStatus.MC_STATE == 0x13) - { - return 1; - } - }while(g_xStatus.MC_STATE != MC_STATE_LOCK); - - s_cVcoWordTx = SpiritCalibrationGetVcoCalData(); - - SpiritCmdStrobeReady(); - - do{ - SpiritRefreshStatus(); - }while(g_xStatus.MC_STATE != MC_STATE_READY); - - - SpiritCmdStrobeLockRx(); - - do{ - SpiritRefreshStatus(); - if(g_xStatus.MC_STATE == 0x13) - { - return 1; - } - }while(g_xStatus.MC_STATE != MC_STATE_LOCK); - - s_cVcoWordRx = SpiritCalibrationGetVcoCalData(); - - SpiritCmdStrobeReady(); - - do{ - SpiritRefreshStatus(); - if(g_xStatus.MC_STATE == 0x13) - { - return 1; - } - }while(g_xStatus.MC_STATE != MC_STATE_READY); - - if(cStandby == 1) - { - SpiritCmdStrobeStandby(); - } - SpiritCalibrationVco(S_DISABLE); - - /* Disable the reference divider if the XTAL is between 48 and 52 MHz */ - if(cRestore) - { - SpiritRadioSetRefDiv(S_DISABLE); - SpiritManagementSetFrequencyBase(nFreq); - } - - /* Restore the VCO current */ - tmp = 0x11; SpiritSpiWriteRegisters(0xA1,1,&tmp); - - SpiritCalibrationSetVcoCalDataTx(s_cVcoWordTx); - SpiritCalibrationSetVcoCalDataRx(s_cVcoWordRx); - - return 0; -} - - -void SpiritManagementWaCmdStrobeTx(void) -{ - if(s_cCommunicationState != COMMUNICATION_STATE_TX) - { - uint32_t xtal_frequency = SpiritRadioGetXtalFrequency(); - - /* To achive the max output power */ - if(s_nDesiredFrequency>=150000000 && s_nDesiredFrequency<=470000000) - { - /* Optimal setting for Tx mode only */ - SpiritRadioSetPACwc(LOAD_3_6_PF); - } - else - { - /* Optimal setting for Tx mode only */ - SpiritRadioSetPACwc(LOAD_0_PF); - } - - uint8_t tmp = 0x11; SpiritSpiWriteRegisters(0xa9, 1, &tmp); /* Enable VCO_L buffer */ - tmp = 0x20; SpiritSpiWriteRegisters(PM_CONFIG1_BASE, 1, &tmp); /* Set SMPS switching frequency */ - - s_cCommunicationState = COMMUNICATION_STATE_TX; - } -} - - -void SpiritManagementWaCmdStrobeRx(void) -{ - if(s_cCommunicationState != COMMUNICATION_STATE_RX) - { - uint8_t tmp = 0x98; SpiritSpiWriteRegisters(PM_CONFIG1_BASE, 1, &tmp); /* Set SMPS switching frequency */ - SpiritRadioSetPACwc(LOAD_0_PF); /* Set the correct CWC parameter */ - - s_cCommunicationState = COMMUNICATION_STATE_RX; - } -} - -void SpiritManagementWaTRxFcMem(uint32_t nDesiredFreq) -{ - s_cCommunicationState = COMMUNICATION_STATE_NONE; - s_nDesiredFrequency = nDesiredFreq; -} - - -void SpiritManagementWaExtraCurrent(void) -{ - uint8_t tmp= 0xCA;SpiritSpiWriteRegisters(0xB2, 1, &tmp); - tmp= 0x04;SpiritSpiWriteRegisters(0xA8, 1, &tmp); - /* just a read to loose some microsecs more */ - SpiritSpiReadRegisters(0xA8, 1, &tmp); - tmp= 0x00;SpiritSpiWriteRegisters(0xA8, 1, &tmp); -} - -/** -* @} -*/ - - - -/** -* @} -*/ - - -/** -* @} -*/ - -/** -* @} -*/ - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktBasic.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktBasic.c deleted file mode 100644 index d113f87f3..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktBasic.c +++ /dev/null @@ -1,617 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktBasic.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT Basic packets. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_PktBasic.h" -#include "MCU_Interface.h" - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_PktBasic - * @{ - */ - - -/** - * @defgroup PktBasic_Private_TypesDefinitions Pkt Basic Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktBasic_Private_Defines Pkt Basic Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktBasic_Private_Macros Pkt Basic Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktBasic_Private_Variables Pkt Basic Private Variables - * @{ - */ - -/** - *@} - */ - - - -/** - * @defgroup PktBasic_Private_FunctionPrototypes Pkt Basic Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktBasic_Private_Functions Pkt Basic Private Functions - * @{ - */ - -/** - * @brief Initializes the SPIRIT Basic packet according to the specified parameters in the PktBasicInit struct. - * Notice that this function sets the autofiltering option on CRC if it is set to any value different from BASIC_NO_CRC. - * @param pxPktBasicInit Basic packet init structure. - * This parameter is a pointer to @ref PktBasicInit. - * @retval None. - */ -void SpiritPktBasicInit(PktBasicInit* pxPktBasicInit) -{ - uint8_t tempRegValue[4], i; - - /* Check the parameters */ - s_assert_param(IS_BASIC_PREAMBLE_LENGTH(pxPktBasicInit->xPreambleLength)); - s_assert_param(IS_BASIC_SYNC_LENGTH(pxPktBasicInit->xSyncLength)); - s_assert_param(IS_BASIC_CRC_MODE(pxPktBasicInit->xCrcMode)); - s_assert_param(IS_BASIC_LENGTH_WIDTH_BITS(pxPktBasicInit->cPktLengthWidth)); - s_assert_param(IS_BASIC_FIX_VAR_LENGTH(pxPktBasicInit->xFixVarLength)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicInit->xAddressField)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicInit->xFec)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicInit->xDataWhitening)); - s_assert_param(IS_BASIC_CONTROL_LENGTH(pxPktBasicInit->xControlLength)); - - /* Reads the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); - - /* Mask a reserved bit */ - tempRegValue[0] &= ~0x20; - - /* Always set the automatic packet filtering */ - tempRegValue[0] |= PROTOCOL1_AUTO_PCKT_FLT_MASK; - - /* Writes the value on register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); - - /* Reads the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Always reset the control and source filtering (also if it is not present in basic) */ - tempRegValue[0] &= ~(PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK | PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK); - - /* Writes the value on register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - if(pxPktBasicInit->xAddressField == S_ENABLE) - { - tempRegValue[0]=0x08; - } - else - { - tempRegValue[0]=0x00; - } - /* Address and control length setting */ - tempRegValue[0] |= ((uint8_t) pxPktBasicInit->xControlLength); - - /* Packet format and width length setting */ - pxPktBasicInit->cPktLengthWidth == 0 ? pxPktBasicInit->cPktLengthWidth=1 : pxPktBasicInit->cPktLengthWidth; - tempRegValue[1] = ((uint8_t) PCKTCTRL3_PCKT_FRMT_BASIC) | ((uint8_t)(pxPktBasicInit->cPktLengthWidth-1)); - - /* Preamble, sync and fixed or variable length setting */ - tempRegValue[2] = ((uint8_t) pxPktBasicInit->xPreambleLength) | ((uint8_t) pxPktBasicInit->xSyncLength) | - ((uint8_t) pxPktBasicInit->xFixVarLength); - - /* CRC length, whitening and FEC setting */ - tempRegValue[3] = (uint8_t) pxPktBasicInit->xCrcMode; - - if(pxPktBasicInit->xDataWhitening == S_ENABLE) - { - tempRegValue[3] |= PCKTCTRL1_WHIT_MASK; - } - - if(pxPktBasicInit->xFec == S_ENABLE) - { - tempRegValue[3] |= PCKTCTRL1_FEC_MASK; - } - - /* Writes registers */ - SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 4, tempRegValue); - - /* Sync words setting */ - for(i=0;i<4;i++) - { - if(i<3-(pxPktBasicInit->xSyncLength >>1)) - { - tempRegValue[i]=0; - } - else - { - tempRegValue[i] = (uint8_t)(pxPktBasicInit->lSyncWords>>(8*i)); - } - } - - /* Sets CRC check bit */ - if(pxPktBasicInit->xCrcMode == PKT_NO_CRC) - { - SpiritPktBasicFilterOnCrc(S_DISABLE); - } - else - { - SpiritPktBasicFilterOnCrc(S_ENABLE); - } - - - g_xStatus = SpiritSpiWriteRegisters(SYNC4_BASE, 4, tempRegValue); - -} - - -/** - * @brief Returns the SPIRIT Basic packet structure according to the specified parameters in the registers. - * @param pxPktBasicInit Basic packet init structure. - * This parameter is a pointer to @ref PktBasicInit. - * @retval None. - */ -void SpiritPktBasicGetInfo(PktBasicInit* pxPktBasicInit) -{ - uint8_t tempRegValue[10]; - - /* Reads registers */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 10, tempRegValue); - - /* Length width */ - pxPktBasicInit->cPktLengthWidth=(tempRegValue[1] & 0x0F)+1; - - /* Address field */ - pxPktBasicInit->xAddressField=(SpiritFunctionalState)((tempRegValue[0]>>3) & 0x01); - - /* Control length */ - pxPktBasicInit->xControlLength=(BasicControlLength)(tempRegValue[0] & 0x07); - - /* CRC mode */ - pxPktBasicInit->xCrcMode=(BasicCrcMode)(tempRegValue[3] & 0xE0); - - /* Whitening */ - pxPktBasicInit->xDataWhitening=(SpiritFunctionalState)((tempRegValue[3] >> 4) & 0x01); - - /* FEC */ - pxPktBasicInit->xFec=(SpiritFunctionalState)(tempRegValue[3] & 0x01); - - /* FIX or VAR bit */ - pxPktBasicInit->xFixVarLength=(BasicFixVarLength)(tempRegValue[2] & 0x01); - - /* Preamble length */ - pxPktBasicInit->xPreambleLength=(BasicPreambleLength)(tempRegValue[2] & 0xF8); - - /* Sync length */ - pxPktBasicInit->xSyncLength=(BasicSyncLength)(tempRegValue[2] & 0x06); - - /* sync Words */ - pxPktBasicInit->lSyncWords=0; - for(uint8_t i=0 ; i<4 ; i++) - { - if(i>2-(((uint8_t)pxPktBasicInit->xSyncLength) >>1)) - { - pxPktBasicInit->lSyncWords |= (uint32_t)(tempRegValue[i+6])<<(8*i); - } - } - -} - - -/** - * @brief Initializes the SPIRIT Basic packet addresses according to the specified - * parameters in the PktBasicAddressesInit struct. - * @param pxPktBasicAddresses Basic packet addresses init structure. - * This parameter is a pointer to @ref PktBasicAddresses. - * @retval None. - */ -void SpiritPktBasicAddressesInit(PktBasicAddressesInit* pxPktBasicAddresses) -{ - uint8_t tempRegValue[3]; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicAddresses->xFilterOnMyAddress)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicAddresses->xFilterOnMulticastAddress)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktBasicAddresses->xFilterOnBroadcastAddress)); - - - /* Reads the PCKT_FLT_OPTIONS ragister */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Enables or disables filtering on my address */ - if(pxPktBasicAddresses->xFilterOnMyAddress == S_ENABLE) - { - tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; - } - else - { - tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; - } - - /* Enables or disables filtering on multicast address */ - if(pxPktBasicAddresses->xFilterOnMulticastAddress == S_ENABLE) - { - tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; - } - else - { - tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; - } - - /* Enables or disables filtering on broadcast address */ - if(pxPktBasicAddresses->xFilterOnBroadcastAddress == S_ENABLE) - { - tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; - } - else - { - tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; - } - - /* Writes the new value on the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Fills the array with the addresses passed in the structure */ - tempRegValue[0] = pxPktBasicAddresses->cBroadcastAddress; - tempRegValue[1] = pxPktBasicAddresses->cMulticastAddress; - tempRegValue[2] = pxPktBasicAddresses->cMyAddress; - - /* Writes values on the PCKT_FLT_GOALS registers */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); - - -} - - -/** - * @brief Returns the SPIRIT Basic packet addresses structure according to the specified - * parameters in the registers. - * @param pxPktBasicAddresses Basic packet addresses init structure. - * This parameter is a pointer to @ref PktBasicAddresses. - * @retval None. - */ -void SpiritPktBasicGetAddressesInfo(PktBasicAddressesInit* pxPktBasicAddresses) -{ - uint8_t tempRegValue[3]; - - /* Reads values on the PCKT_FLT_GOALS registers */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); - - /* Fit the structure with the read addresses */ - pxPktBasicAddresses->cBroadcastAddress = tempRegValue[0]; - pxPktBasicAddresses->cMulticastAddress = tempRegValue[1]; - pxPktBasicAddresses->cMyAddress = tempRegValue[2]; - - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Fit the structure with the read filtering bits */ - pxPktBasicAddresses->xFilterOnBroadcastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 1) & 0x01); - pxPktBasicAddresses->xFilterOnMulticastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 2) & 0x01); - pxPktBasicAddresses->xFilterOnMyAddress = (SpiritFunctionalState)((tempRegValue[0] >> 3) & 0x01); - -} - - -/** - * @brief Configures the Basic packet format as packet used by SPIRIT. - * @param None. - * @retval None. - */ -void SpiritPktBasicSetFormat(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Build the new value. Also set to 0 the direct RX mode bits */ - tempRegValue &= 0x0F; - tempRegValue |= (uint8_t)PCKTCTRL3_PCKT_FRMT_BASIC; - - /* Writes the value on the PCKTCTRL3 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Reads the PCKTCTRL1_BASE register */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Build the new value. Set to 0 the direct TX mode bits */ - tempRegValue &= 0xF3; - - /* Writes the value on the PCKTCTRL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Reads the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Mask a reserved bit */ - tempRegValue &= ~0x20; - - /* Writes the value on register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); -} - - -/** - * @brief Sets the address length for SPIRIT Basic packets. - * @param xAddressField length of ADDRESS in bytes. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritPktBasicAddressField(SpiritFunctionalState xAddressField) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xAddressField)); - - /* Reads the PCKTCTRL4 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - - /* Build the address length for the register */ - if(xAddressField==S_ENABLE) - { - tempRegValue |= 0x08; - } - else - { - tempRegValue &= 0x07; - } - - /* Writes the new value on the PCKTCTRL4 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Specifies if the Address field for SPIRIT Basic packets is enabled or disabled. - * @param None. - * @retval SpiritFunctionalState Notifies if the address field is enabled or disabled. - */ -SpiritFunctionalState SpiritPktBasicGetAddressField(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL4 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - - /* Returns the address field value */ - if(tempRegValue & PCKTCTRL4_ADDRESS_LEN_MASK) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - - -/** - * @brief Sets the payload length for SPIRIT Basic packets. Since the packet length - * depends from the address and the control field size, this - * function reads the correspondent registers in order to determine - * the correct packet length to be written. - * @param nPayloadLength payload length in bytes. - * This parameter is an uint16_t. - * @retval None. - */ -void SpiritPktBasicSetPayloadLength(uint16_t nPayloadLength) -{ - uint8_t tempRegValue[2]; - uint16_t overSize=0; - - /* Computes the oversize (address + control) size */ - if(SpiritPktBasicGetAddressField()) - { - overSize=1; - } - overSize += (uint16_t) SpiritPktBasicGetControlLength(); - - /* Computes PCKTLEN0 value from nPayloadLength */ - tempRegValue[1]=BASIC_BUILD_PCKTLEN0(nPayloadLength+overSize); - /* Computes PCKTLEN1 value from nPayloadLength */ - tempRegValue[0]=BASIC_BUILD_PCKTLEN1(nPayloadLength+overSize); - - /* Writes data on the PCKTLEN1/0 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTLEN1_BASE, 2, tempRegValue); - -} - - -/** - * @brief Returns the payload length for SPIRIT Basic packets. Since the - * packet length depends from the address and the control - * field size, this function reads the correspondent - * registers in order to determine the correct payload length - * to be returned. - * @param None. - * @retval uint16_t Payload length in bytes. - */ -uint16_t SpiritPktBasicGetPayloadLength(void) -{ - uint8_t tempRegValue[2]; - uint16_t overSize=0; - - /* Computes the oversize (address + control) size */ - if(SpiritPktBasicGetAddressField()) - { - overSize=1; - } - overSize += (uint16_t) SpiritPktBasicGetControlLength(); - - /* Reads the packet length registers */ - g_xStatus = SpiritSpiReadRegisters(PCKTLEN1_BASE, 2, tempRegValue); - - /* Returns the packet length */ - return ((((uint16_t)tempRegValue[0])<<8) + (uint16_t) tempRegValue[1]) - overSize; - -} - -/** - * @brief Returns the packet length field of the received packet. - * @param None. - * @retval uint16_t Packet length. - */ -uint16_t SpiritPktBasicGetReceivedPktLength(void) -{ - uint8_t tempRegValue[2]; - uint16_t overSize=0; - - /* Computes the oversize (address + control) size */ - if(SpiritPktBasicGetAddressField()) - { - overSize=1; - } - overSize += (uint16_t) SpiritPktBasicGetControlLength(); - - /* Reads the RX_PCKT_LENx registers value */ - g_xStatus = SpiritSpiReadRegisters(RX_PCKT_LEN1_BASE, 2, tempRegValue); - - /* Rebuild and return the the length field */ - return ((((uint16_t) tempRegValue[0]) << 8) + (uint16_t) tempRegValue[1] - overSize); - -} - -/** - * @brief Computes and sets the variable payload length for SPIRIT Basic packets. - * @param nMaxPayloadLength payload length in bytes. - * This parameter is an uint16_t. - * @param xAddressField Enable or Disable Address Field. - * This parameter can be S_ENABLE or S_DISABLE. - * @param xControlLength Control length in bytes. - * This parameter can be any value of @ref BasicControlLength. - * @retval None. - */ -void SpiritPktBasicSetVarLengthWidth(uint16_t nMaxPayloadLength, SpiritFunctionalState xAddressField, BasicControlLength xControlLength) -{ - uint8_t tempRegValue, - addressLength, - i; - uint32_t packetLength; - - /* Sets the address length according to xAddressField */ - if(xAddressField == S_ENABLE) - { - addressLength=1; - } - else - { - addressLength=0; - } - - /* packet length = payload length + address length + control length */ - packetLength=nMaxPayloadLength+addressLength+xControlLength; - - /* Computes the number of bits */ - for(i=0;i<16;i++) - { - if(packetLength == 0) break; - { - packetLength >>= 1; - } - } - i==0 ? i=1 : i; - - /* Reads the PCKTCTRL3 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Build value for the length width */ - tempRegValue &= ~PCKTCTRL3_LEN_WID_MASK; - tempRegValue |= (uint8_t)(i-1); - - /* Writes the PCKTCTRL3 register value */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - -} - - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktCommon.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktCommon.c deleted file mode 100644 index b29084b78..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktCommon.c +++ /dev/null @@ -1,1453 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktCommon.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of the common features of SPIRIT packets. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_PktCommon.h" -#include "MCU_Interface.h" - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_PktCommon - * @{ - */ - - -/** - * @defgroup PktCommon_Private_TypesDefinitions Pkt Common Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktCommon_Private_Defines Pkt Common Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktCommon_Private_Macros Pkt Common Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktCommon_Private_Variables Pkt Common Private Variables - * @{ - */ - -/** - *@} - */ - - - -/** - * @defgroup PktCommon_Private_FunctionPrototypes Pkt Common Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktCommon_Private_Functions Pkt Common Private Functions - * @{ - */ - -/** - * @brief Sets the CONTROL field length for SPIRIT packets. - * @param xControlLength length of CONTROL field in bytes. - * This parameter can be any value of @ref PktControlLength. - * @retval None. - */ -void SpiritPktCommonSetControlLength(PktControlLength xControlLength) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PKT_CONTROL_LENGTH(xControlLength)); - - /* Reads the PCKTCTRL4 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - - /* Set the control length */ - tempRegValue &= ~PCKTCTRL4_CONTROL_LEN_MASK; - tempRegValue |= (uint8_t)xControlLength; - - /* Writes the new value on the PCKTCTRL4 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the CONTROL field length for SPIRIT packets. - * @param None. - * @retval uint8_t Control field length. - */ -uint8_t SpiritPktCommonGetControlLength(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL4 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - - /* Rebuild and return value */ - return (tempRegValue & PCKTCTRL4_CONTROL_LEN_MASK); - -} - - -/** - * @brief Sets the PREAMBLE field Length mode for SPIRIT packets. - * @param xPreambleLength length of PREAMBLE field in bytes. - * This parameter can be any value of @ref PktPreambleLength. - * @retval None. - */ -void SpiritPktCommonSetPreambleLength(PktPreambleLength xPreambleLength) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PKT_PREAMBLE_LENGTH(xPreambleLength)); - - /* Reads the PCKTCTRL2 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); - - /* Set the preamble length */ - tempRegValue &= ~PCKTCTRL2_PREAMBLE_LENGTH_MASK; - tempRegValue |= (uint8_t)xPreambleLength; - - /* Writes the new value on the PCKTCTRL2 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the PREAMBLE field Length mode for SPIRIT packets. - * @param None. - * @retval uint8_t Preamble field length in bytes. - */ -uint8_t SpiritPktCommonGetPreambleLength(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL2 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); - - /* Rebuild and return value */ - return ((tempRegValue & PCKTCTRL2_PREAMBLE_LENGTH_MASK)>>3) + 1; - -} - - -/** - * @brief Sets the SYNC field Length for SPIRIT packets. - * @param xSyncLength length of SYNC field in bytes. - * This parameter can be any value of @ref PktSyncLength. - * @retval None. - */ -void SpiritPktCommonSetSyncLength(PktSyncLength xSyncLength) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PKT_SYNC_LENGTH(xSyncLength)); - - /* Reads the PCKTCTRL2 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); - - /* Set the sync length */ - tempRegValue &= ~PCKTCTRL2_SYNC_LENGTH_MASK; - tempRegValue |= (uint8_t)xSyncLength; - - /* Writes the new value on the PCKTCTRL2 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the SYNC field Length for SPIRIT packets. - * @param None. - * @retval uint8_t Sync field length in bytes. - */ -uint8_t SpiritPktCommonGetSyncLength(void) -{ - uint8_t tempRetValue; - - /* Reads the PCKTCTRL2 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRetValue); - - /* Rebuild and return value */ - return ((tempRetValue & PCKTCTRL2_SYNC_LENGTH_MASK)>>1) + 1; - -} - - -/** - * @brief Sets fixed or variable payload length mode for SPIRIT packets. - * @param xFixVarLength variable or fixed length. - * PKT_FIXED_LENGTH_VAR -> variable (the length is extracted from the received packet). - * PKT_FIXED_LENGTH_FIX -> fix (the length is set by PCKTLEN0 and PCKTLEN1). - * @retval None. - */ -void SpiritPktCommonSetFixVarLength(PktFixVarLength xFixVarLength) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PKT_FIX_VAR_LENGTH(xFixVarLength)); - - /* Reads the PCKTCTRL2 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); - - /* Set fixed or variable address mode */ - tempRegValue &= ~PCKTCTRL2_FIX_VAR_LEN_MASK; - tempRegValue |= (uint8_t)xFixVarLength; - - /* Writes the new value on the PCKTCTRL2 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Enables or Disables the filtering on CRC. - * @param xNewState new state for CRC_CHECK. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritPktCommonFilterOnCrc(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PCKT_FLT_OPTIONS register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Modify the register value: enable or disable the CRC filtering */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKT_FLT_OPTIONS_CRC_CHECK_MASK; - } - else - { - tempRegValue &= ~PCKT_FLT_OPTIONS_CRC_CHECK_MASK; - } - - /* Writes the PCKT_FLT_OPTIONS register value */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the CRC filtering enable bit. - * @param None. - * @retval SpiritFunctionalState CRC filtering. - */ -SpiritFunctionalState SpiritPktCommonGetFilterOnCrc(void) -{ - uint8_t tempRegValue; - - - /* Reads the PCKT_FLT_OPTIONS register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Check the CRC filtering bit */ - if(tempRegValue & PCKT_FLT_OPTIONS_CRC_CHECK_MASK) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - - -/** - * @brief Sets the CRC mode for SPIRIT packets. - * @param xCrcMode length of CRC field in bytes. - * This parameter can be any value of @ref PktCrcMode. - * @retval None. - */ -void SpiritPktCommonSetCrcMode(PktCrcMode xCrcMode) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PKT_CRC_MODE(xCrcMode)); - - /* Reads the PCKTCTRL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Build data to write setting the CRC mode */ - tempRegValue &= ~PCKTCTRL1_CRC_MODE_MASK; - tempRegValue |= (uint8_t)xCrcMode; - - /* Writes the new value on the PCKTCTRL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the CRC mode for SPIRIT packets. - * @param None. - * @retval PktCrcMode Crc mode. - */ -PktCrcMode SpiritPktCommonGetCrcMode(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL1 register */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Rebuild and return value */ - return (PktCrcMode)(tempRegValue & 0xE0); - -} - - -/** - * @brief Enables or Disables WHITENING for SPIRIT packets. - * @param xNewState new state for WHITENING mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritPktCommonWhitening(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PCKTCTRL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Build data to write: set or reset the whitening enable bit */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKTCTRL1_WHIT_MASK; - } - else - { - tempRegValue &= ~PCKTCTRL1_WHIT_MASK; - } - - /* Writes the new value on the PCKTCTRL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Enables or Disables FEC for SPIRIT packets. - * @param xNewState new state for FEC mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritPktCommonFec(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PCKTCTRL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Build data to write: set or reset the FEC enable bit */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKTCTRL1_FEC_MASK; - } - else - { - tempRegValue &= ~PCKTCTRL1_FEC_MASK; - } - - /* Writes data on the PCKTCTRL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets a specific SYNC word for SPIRIT packets. - * @param xSyncX SYNC word number to be set. - * This parameter can be any value of @ref PktSyncX. - * @param cSyncWord SYNC word. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktCommonSetSyncxWord(PktSyncX xSyncX , uint8_t cSyncWord) -{ - uint8_t tempRegAddress; - - /* Check the parameters */ - s_assert_param(IS_PKT_SYNCx(xSyncX)); - - /* Set the specified address */ - switch(xSyncX) - { - case PKT_SYNC_WORD_1: - tempRegAddress=SYNC1_BASE; - break; - case PKT_SYNC_WORD_2: - tempRegAddress=SYNC2_BASE; - break; - case PKT_SYNC_WORD_3: - tempRegAddress=SYNC3_BASE; - break; - case PKT_SYNC_WORD_4: - tempRegAddress=SYNC4_BASE; - break; - } - - /* Writes value on the selected register */ - g_xStatus = SpiritSpiWriteRegisters(tempRegAddress, 1, &cSyncWord); - -} - - -/** - * @brief Returns a specific SYNC word for SPIRIT packets. - * @param xSyncX SYNC word number to be get. - * This parameter can be any value of @ref PktSyncX. - * @retval uint8_t Sync word x. - */ -uint8_t SpiritPktCommonGetSyncxWord(PktSyncX xSyncX) -{ - uint8_t tempRegAddress, tempRegValue; - - /* Set the specified address */ - switch(xSyncX) - { - case PKT_SYNC_WORD_1: - tempRegAddress=SYNC1_BASE; - break; - case PKT_SYNC_WORD_2: - tempRegAddress=SYNC2_BASE; - break; - case PKT_SYNC_WORD_3: - tempRegAddress=SYNC3_BASE; - break; - case PKT_SYNC_WORD_4: - tempRegAddress=SYNC4_BASE; - break; - } - - /* Reads the selected register value */ - g_xStatus = SpiritSpiReadRegisters(tempRegAddress, 1, &tempRegValue); - - /* Returns the read value */ - return tempRegValue; - -} - - -/** - * @brief Sets multiple SYNC words for SPIRIT packets. - * @param lSyncWords SYNC words to be set with format: 0x|SYNC1|SYNC2|SYNC3|SYNC4|. - * This parameter is a uint32_t. - * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb - * until the number of bytes in xSyncLength has been stored. - * This parameter is a @ref PktSyncLength. - * @retval None. - */ -void SpiritPktCommonSetSyncWords(uint32_t lSyncWords, PktSyncLength xSyncLength) -{ - uint8_t tempRegValue[4]; - - /* Split the 32-bit value in 4 8-bit values */ - for(uint8_t i=0 ; i<4 ; i++) - { - if(i<3-xSyncLength>>1) - { - tempRegValue[i]=0; - } - else - { - tempRegValue[i]=(uint8_t)(lSyncWords>>(8*i)); - } - } - - /* Writes SYNC value on the SYNCx registers */ - g_xStatus = SpiritSpiWriteRegisters(SYNC4_BASE, 4, tempRegValue); - -} - - -/** - * @brief Returns multiple SYNC words for SPIRIT packets. - * @param xSyncLength SYNC length in bytes. The 32bit word passed will be stored in the SYNCx registers from the MSb - * until the number of bytes in xSyncLength has been stored. - * This parameter is a pointer to @ref PktSyncLength. - * @retval uint32_t Sync words. The format of the read 32 bit word is 0x|SYNC1|SYNC2|SYNC3|SYNC4|. - */ -uint32_t SpiritPktCommonGetSyncWords(PktSyncLength xSyncLength) -{ - uint8_t tempRegValue[4]; - uint32_t tempRetValue=0; - - /* Reads the SYNCx registers value */ - g_xStatus = SpiritSpiReadRegisters(SYNC4_BASE, 4, tempRegValue); - - /* Rebuild the SYNC words */ - for(uint8_t i=0 ; i<4 ; i++) - { - if(i>2-(xSyncLength >>1)) - { - tempRetValue |= tempRegValue[i]<<(8*i); - } - } - - /* Return SYNC words */ - return tempRetValue; - -} - - -/** - * @brief Returns the variable length width (in number of bits). - * @param None. - * @retval uint8_t Variable length width in bits. - */ -uint8_t SpiritPktCommonGetVarLengthWidth(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL3 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Rebuild and return value */ - return (tempRegValue & PCKTCTRL3_LEN_WID_MASK)+1; - -} - - -/** - * @brief Sets the destination address for the Tx packet. - * @param cAddress Destination address. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktCommonSetDestinationAddress(uint8_t cAddress) -{ - /* Writes value on PCKT_FLT_GOALS_SOURCE_ADDR register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_SOURCE_ADDR_BASE, 1, &cAddress); - -} - - -/** - * @brief Returns the settled destination address. - * @param None. - * @retval uint8_t Transmitted destination address. - */ -uint8_t SpiritPktCommonGetTransmittedDestAddress(void) -{ - uint8_t tempRegValue; - - /* Reads value on the PCKT_FLT_GOALS_SOURCE_ADDR register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_SOURCE_ADDR_BASE, 1, &tempRegValue); - - /* Return value */ - return tempRegValue; - -} - - -/** - * @brief Sets the node my address. When the filtering on my address is on, if the destination address extracted from the received packet is equal to the content of the - * my address, then the packet is accepted (this is the address of the node). - * @param cAddress Address of the present node. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktCommonSetMyAddress(uint8_t cAddress) -{ - /* Writes value on the PCKT_FLT_GOALS_TX_ADDR register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_TX_ADDR_BASE, 1, &cAddress); - -} - - -/** - * @brief Returns the address of the present node. - * @param None. - * @retval uint8_t My address (address of this node). - */ -uint8_t SpiritPktCommonGetMyAddress(void) -{ - uint8_t tempRegValue; - - /* Reads value on the PCKT_FLT_GOALS_TX_ADDR register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_TX_ADDR_BASE, 1, &tempRegValue); - - /* Return value */ - return tempRegValue; - -} - - -/** - * @brief Sets the broadcast address. If the destination address extracted from the received packet is equal to the content of the - * BROADCAST_ADDR register, then the packet is accepted. - * @param cAddress Broadcast address. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktCommonSetBroadcastAddress(uint8_t cAddress) -{ - /* Writes value on the PCKT_FLT_GOALS_BROADCAST register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 1, &cAddress); - -} - - -/** - * @brief Returns the broadcast address. - * @param None. - * @retval uint8_t Broadcast address. - */ -uint8_t SpiritPktCommonGetBroadcastAddress(void) -{ - uint8_t tempRegValue; - - /* Reads value on the PCKT_FLT_GOALS_BROADCAST register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 1, &tempRegValue); - - /* Return value */ - return tempRegValue; - -} - - -/** - * @brief Sets the multicast address. When the multicast filtering is on, if the destination address extracted from the received packet is equal to the content of the - * MULTICAST_ADDR register, then the packet is accepted. - * @param cAddress Multicast address. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktCommonSetMulticastAddress(uint8_t cAddress) -{ - /* Writes value on the PCKT_FLT_GOALS_MULTICAST register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_MULTICAST_BASE, 1, &cAddress); - -} - - -/** - * @brief Returns the multicast address. - * @param None. - * @retval uint8_t Multicast address. - */ -uint8_t SpiritPktCommonGetMulticastAddress(void) -{ - uint8_t tempRegValue; - - /* Reads value on the PCKT_FLT_GOALS_MULTICAST register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_MULTICAST_BASE, 1, &tempRegValue); - - /* Return value */ - return tempRegValue; - -} - - -/** - * @brief Sets the control mask. The 1 bits of the CONTROL_MASK indicate the - * bits to be used in filtering. (All 0s no filtering) - * @param lMask Control mask. - * This parameter is an uint32_t. - * @retval None. - */ -void SpiritPktCommonSetCtrlMask(uint32_t lMask) -{ - uint8_t tempRegValue[4]; - - /* Split the 32-bit value in 4 8-bit values */ - tempRegValue[0] = (uint8_t) lMask; - tempRegValue[1] = (uint8_t)(lMask >> 8); - tempRegValue[2] = (uint8_t)(lMask >> 16); - tempRegValue[3] = (uint8_t)(lMask >> 24); - - /* Writes values on the CKT_FLT_GOALS_CONTROLx_MASK registers */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_CONTROL0_MASK_BASE, 4, tempRegValue); - -} - - -/** - * @brief Returns the control mask. The 1 bits of the CONTROL_MASK indicate the - * bits to be used in filtering. (All 0s no filtering) - * @param None. - * @retval uint32_t Control mask. - */ -uint32_t SpiritPktCommonGetCtrlMask(void) -{ - uint8_t tempRegValue[4]; - uint32_t tempRetValue=0; - - /* Reads the PCKT_FLT_GOALS_CONTROLx_MASK registers */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_CONTROL0_MASK_BASE, 4, tempRegValue); - - /* Rebuild the control mask value on a 32-bit integer variable */ - for(uint8_t i=0 ; i<4 ; i++) - { - tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*i); - } - - /* Return value */ - return tempRetValue; -} - -/** - * @brief Sets the control field reference. If the bits enabled by the CONTROL_MASK - * match the ones of the control fields extracted from the received packet - * then the packet is accepted. - * @param lReference Control reference. - * This parameter is an uint32_t. - * @retval None. - */ -void SpiritPktCommonSetCtrlReference(uint32_t lReference) -{ - uint8_t tempRegValue[4]; - - /* Split the 32-bit value in 4 8-bit values */ - tempRegValue[0] = (uint8_t) lReference; - tempRegValue[1] = (uint8_t)(lReference >> 8); - tempRegValue[2] = (uint8_t)(lReference >> 16); - tempRegValue[3] = (uint8_t)(lReference >> 24); - - /* Writes values on the CKT_FLT_GOALS_CONTROLx_FIELD registers */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_CONTROL0_FIELD_BASE, 4, tempRegValue); - -} - - -/** - * @brief Returns the control field reference. - * @param None. - * @retval uint32_t Control reference. - */ -uint32_t SpiritPktCommonGetCtrlReference(void) -{ - uint8_t tempRegValue[4]; - uint32_t tempRetValue=0; - - /* Reads the PCKT_FLT_GOALS_CONTROLx_FIELD registers */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_CONTROL0_FIELD_BASE, 4, tempRegValue); - - /* Rebuild the control mask value on a 32-bit integer variable */ - for(uint8_t i=0 ; i<4 ; i++) - { - tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*i); - } - - /* Return value */ - return tempRetValue; -} - - -/** - * @brief Sets the TX control field. - * @param lField Tx contro field. - * This parameter is an uint32_t. - * @retval None. - */ -void SpiritPktCommonSetTransmittedCtrlField(uint32_t lField) -{ - uint8_t tempRegValue[4]; - - /* Split the 32-bit value in 4 8-bit values */ - tempRegValue[3] = (uint8_t) lField; - tempRegValue[2] = (uint8_t)(lField >> 8); - tempRegValue[1] = (uint8_t)(lField >> 16); - tempRegValue[0] = (uint8_t)(lField >> 24); - - /* Writes value on the TX_CTRL_FIELDx register */ - g_xStatus = SpiritSpiWriteRegisters(TX_CTRL_FIELD3_BASE, 4, tempRegValue); - -} - - -/** - * @brief Returns the Tx control field. - * @param None. - * @retval uint32_t Control field of the transmitted packet. - */ -uint32_t SpiritPktCommonGetTransmittedCtrlField(void) -{ - uint8_t tempRegValue[4]; - uint32_t tempRetValue=0; - - /* Reads the TX_CTRL_FIELDx registers */ - g_xStatus = SpiritSpiReadRegisters(TX_CTRL_FIELD3_BASE, 4, tempRegValue); - - /* Rebuild value: build a 32-bit value from the read bytes */ - for(uint8_t i=0 ; i<4 ; i++) - { - tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*(3-i)); - } - - /* Return value */ - return tempRetValue; - -} - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with My address. - * @param xNewState new state for DEST_VS_SOURCE_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritPktCommonFilterOnMyAddress(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - - /* Modify the register value: set or reset the TX source address control */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Set or reset the DESTINATION vs TX enabling bit */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; - } - else - { - tempRegValue &= ~PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; - } - - /* Writes the new value on the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - -} - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with multicast address. - * @param xNewState new state for DEST_VS_MULTICAST_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritPktCommonFilterOnMulticastAddress(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PCKT_FLT_OPTIONS register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Enable or disable the filtering option */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; - } - else - { - tempRegValue &= ~PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; - } - - /* Writes the new value on the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - -} - - -/** - * @brief If enabled RX packet is accepted if its destination address matches with broadcast address. - * @param xNewState new state for DEST_VS_BROADCAST_ADDRESS. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritPktCommonFilterOnBroadcastAddress(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Enable or disable the filtering option */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; - } - else - { - tempRegValue &= ~PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; - } - - /* Writes the new value on the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the enable bit of the my address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -SpiritFunctionalState SpiritPktCommonGetFilterOnMyAddress(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Gets the enable/disable bit in form of SpiritFunctionalState type */ - if(tempRegValue & 0x08) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - -/** - * @brief Returns the enable bit of the multicast address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -SpiritFunctionalState SpiritPktCommonGetFilterOnMulticastAddress(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Get the enable/disable bit in form of SpiritFunctionalState type */ - if(tempRegValue & 0x04) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - -/** - * @brief Returns the enable bit of the broadcast address filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -SpiritFunctionalState SpiritPktCommonGetFilterOnBroadcastAddress(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Get the enable/disable bit in form of SpiritFunctionalState type */ - if(tempRegValue & 0x02) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - - -/** - * @brief Returns the destination address of the received packet. - * @param None. - * @retval uint8_t Destination address of the received address. - */ -uint8_t SpiritPktCommonGetReceivedDestAddress(void) -{ - uint8_t tempRegValue; - - /* Reads the RX_ADDR_FIELD0 register value */ - g_xStatus = SpiritSpiReadRegisters(RX_ADDR_FIELD0_BASE, 1, &tempRegValue); - - /* Return value */ - return tempRegValue; - -} - - -/** - * @brief Returns the control field of the received packet. - * @param None. - * @retval uint32_t Received control field. - */ -uint32_t SpiritPktCommonGetReceivedCtrlField(void) -{ - uint8_t tempRegValue[4]; - uint32_t tempRetValue=0; - - /* Reads the PCKT_FLT_GOALS_CONTROLx_MASK registers */ - g_xStatus = SpiritSpiReadRegisters(RX_CTRL_FIELD0_BASE, 4, tempRegValue); - - /* Rebuild the control mask value on a 32-bit integer variable */ - for(uint8_t i=0 ; i<4 ; i++) - { - tempRetValue |= ((uint32_t)tempRegValue[i])<<(8*i); - } - - /* Returns value */ - return tempRetValue; -} - - -/** - * @brief Returns the CRC field of the received packet. - * @param cCrcFieldVect array in which the CRC field has to be stored. - * This parameter is an uint8_t array of 3 elements. - * @retval None. - */ -void SpiritPktCommonGetReceivedCrcField(uint8_t* cCrcFieldVect) -{ - uint8_t tempRegValue[3],crcLength; - PktCrcMode crcMode; - - /* Gets the CRC mode in PktCrcMode enum */ - crcMode=SpiritPktCommonGetCrcMode(); - - /* Cast to uint8_t */ - crcLength = (uint8_t)crcMode; - - /* Obtains the real length: see the @ref PktCrcMode enumeration */ - crcLength >>= 5; - if(crcLength>=3) crcLength--; - - /* Reads the CRC_FIELDx registers value */ - g_xStatus = SpiritSpiReadRegisters(CRC_FIELD2_BASE, 3,tempRegValue); - - /* Sets the array to be returned */ - for(uint8_t i=0 ; i<3 ; i++) - { - if(i>4); - -} - -/** - * @brief Returns the TX ACK request - * @param None. - * @retval uint8_t Max number of retransmissions. - * This parameter is an uint8_t. - */ -SpiritFunctionalState SpiritPktCommonGetTxAckRequest(void) -{ - uint8_t tempRegValue; - - /* Reads the PROTOCOL0 register value */ - g_xStatus = SpiritSpiReadRegisters(RX_PCKT_INFO_BASE, 1, &tempRegValue); - - /* Build the value to be written */ - return (SpiritFunctionalState)((tempRegValue & TX_PCKT_INFO_NACK_RX)>>2); - -} - - -/** - * @brief Returns the source address of the received packet. - * @param None. - * @retval uint8_t Source address of the received packet. - */ -uint8_t SpiritPktCommonGetReceivedSourceAddress(void) -{ - uint8_t tempRegValue; - - /* Reads the RX_ADDR_FIELD1 register value */ - g_xStatus = SpiritSpiReadRegisters(RX_ADDR_FIELD1_BASE, 1, &tempRegValue); - - /* Returns value */ - return tempRegValue; - -} - - -/** - * @brief Returns the sequence number of the received packet. - * @param None. - * @retval uint8_t Received Sequence number. - */ -uint8_t SpiritPktCommonGetReceivedSeqNumber(void) -{ - uint8_t tempRegValue; - - /* Reads the RX_PCKT_INFO register value */ - g_xStatus = SpiritSpiReadRegisters(RX_PCKT_INFO_BASE, 1, &tempRegValue); - - /* Obtains and returns the sequence number */ - return tempRegValue & 0x03; - -} - - -/** - * @brief Returns the Nack bit of the received packet - * @param None. - * @retval uint8_t Value of the Nack bit. - */ -uint8_t SpiritPktCommonGetReceivedNackRx(void) -{ - uint8_t tempRegValue; - - /* Reads the RX_PCKT_INFO register value */ - g_xStatus = SpiritSpiReadRegisters(RX_PCKT_INFO_BASE, 1, &tempRegValue); - - /* Obtains and returns the RX nack bit */ - return (tempRegValue >> 2) & 0x01; - -} - - -/** - * @brief Returns the sequence number of the transmitted packet. - * @param None. - * @retval uint8_t Sequence number of the transmitted packet. - */ -uint8_t SpiritPktCommonGetTransmittedSeqNumber(void) -{ - uint8_t tempRegValue; - - /* Reads the TX_PCKT_INFO register value */ - g_xStatus = SpiritSpiReadRegisters(TX_PCKT_INFO_BASE, 1, &tempRegValue); - - /* Obtains and returns the TX sequence number */ - return (tempRegValue >> 4) & 0x07; - -} - - -/** - * @brief Returns the number of retransmission done on the transmitted packet. - * @param None. - * @retval uint8_t Number of retransmissions done until now. - */ -uint8_t SpiritPktCommonGetNReTx(void) -{ - uint8_t tempRetValue; - - /* Reads the TX_PCKT_INFO register value */ - g_xStatus = SpiritSpiReadRegisters(TX_PCKT_INFO_BASE, 1, &tempRetValue); - - /* Obtains and returns the number of retransmission done */ - return (tempRetValue & 0x0F); - -} - - -/** - * @brief If enabled RX packet is accepted only if the masked control field matches the - * masked control field reference (CONTROL_MASK & CONTROL_FIELD_REF == CONTROL_MASK & RX_CONTROL_FIELD). - * @param xNewState new state for Control filtering enable bit. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - * @note This filtering control is enabled by default but the control mask is by default set to 0. - * As a matter of fact the user has to enable the control filtering bit after the packet initialization - * because the PktInit routine disables it. - */ -void SpiritPktCommonFilterOnControlField(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - - /* Modify the register value: set or reset the control bit filtering */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Set or reset the CONTROL filtering enabling bit */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK; - } - else - { - tempRegValue &= ~PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK; - } - - /* Writes the new value on the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the enable bit of the control field filtering. - * @param None. - * @retval SpiritFunctionalState This parameter can be S_ENABLE or S_DISABLE. - */ -SpiritFunctionalState SpiritPktCommonGetFilterOnControlField(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Gets the enable/disable bit in form of SpiritFunctionalState type */ - if(tempRegValue & PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktMbus.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktMbus.c deleted file mode 100644 index f1aa9d49a..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktMbus.c +++ /dev/null @@ -1,354 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktMbus.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT MBUS packets. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_PktMbus.h" -#include "SPIRIT_Radio.h" -#include "MCU_Interface.h" - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_PktMbus - * @{ - */ - - -/** - * @defgroup PktMbus_Private_TypesDefinitions Pkt MBUS Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Private_Defines Pkt MBUS Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Private_Macros Pkt MBUS Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Private_Variables Pkt MBUS Private Variables - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Private_FunctionPrototypes Pkt MBUS Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktMbus_Private_Functions Pkt MBUS Private Functions - * @{ - */ - - -/** - * @brief Initializes the SPIRIT MBUS packet according to the specified parameters in the PktMbusInit struct. - * @param pxPktMbusInit pointer to a PktMbusInit structure that contains the configuration information for the specified SPIRIT MBUS PACKET FORMAT. - * This parameter is a pointer to @ref PktMbusInit. - * @retval None. - */ -void SpiritPktMbusInit(PktMbusInit* pxPktMbusInit) -{ - uint8_t tempRegValue[3]; - - /* Check the parameters */ - s_assert_param(IS_MBUS_SUBMODE(pxPktMbusInit->xMbusSubmode)); - - /* Packet format config */ - SpiritPktMbusSetFormat(); - SpiritPktCommonFilterOnCrc(S_DISABLE); - SpiritRadioCsBlanking(S_ENABLE); - - /* Preamble, postamble and submode config */ - tempRegValue[0] = pxPktMbusInit->cPreambleLength; - tempRegValue[1] = pxPktMbusInit->cPostambleLength; - tempRegValue[2] = (uint8_t) pxPktMbusInit->xMbusSubmode; - - /* Writes the new values on the MBUS_PRMBL registers */ - g_xStatus = SpiritSpiWriteRegisters(MBUS_PRMBL_BASE, 3, tempRegValue); - -} - -/** - * @brief Returns the SPIRIT MBUS packet structure according to the specified parameters in the registers. - * @param pxPktMbusInit MBUS packet init structure. - * This parameter is a pointer to @ref PktMbusInit. - * @retval None. - */ -void SpiritPktMbusGetInfo(PktMbusInit* pxPktMbusInit) -{ - uint8_t tempRegValue[3]; - - /* Reads the MBUS regs value */ - g_xStatus = SpiritSpiReadRegisters(MBUS_PRMBL_BASE, 3, tempRegValue); - - /* Fit the structure */ - pxPktMbusInit->cPreambleLength = tempRegValue[0]; - pxPktMbusInit->cPostambleLength = tempRegValue[1]; - pxPktMbusInit->xMbusSubmode = (MbusSubmode) (tempRegValue[2]&0x0E); - -} - - -/** - * @brief Configures the MBUS packet format as the one used by SPIRIT. - * @param None. - * @retval None. - */ -void SpiritPktMbusSetFormat(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL3 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Sets format bits. Also set to 0 the direct RX mode bits */ - tempRegValue &= 0x0F; - tempRegValue |= ((uint8_t)PCKTCTRL3_PCKT_FRMT_MBUS); - - /* Writes value on the PCKTCTRL3 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Reads the PCKTCTRL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Build the new value. Set to 0 the direct TX mode bits */ - tempRegValue &= 0xF3; - - /* Writes the value on the PCKTCTRL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Reads the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Mask a reserved bit */ - tempRegValue &= ~0x20; - - /* Writes the value on the PROTOCOL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets how many chip sequence “01” shall be added in the preamble - * respect to the minimum value as defined according to the specified sub-mode. - * @param cPreamble the number of chip sequence. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktMbusSetPreamble(uint8_t cPreamble) -{ - /* Modifies the MBUS_PRMBL register value */ - g_xStatus = SpiritSpiWriteRegisters(MBUS_PRMBL_BASE, 1, &cPreamble); - -} - - -/** - * @brief Returns how many chip sequence "01" are added in the preamble - * respect to the minimum value as defined according to the specified sub-mode. - * @param None. - * @retval uint8_t Preable in number of "01" chip sequences. - */ -uint8_t SpiritPktMbusGetPreamble(void) -{ - uint8_t tempRegValue; - - /* Modifies the MBUS_PRMBL register value */ - g_xStatus = SpiritSpiReadRegisters(MBUS_PRMBL_BASE, 1, &tempRegValue); - - /* Return value */ - return tempRegValue; - -} - - -/** - * @brief Sets how many chip sequence “01” will be used in postamble - * @param cPostamble the number of chip sequence. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktMbusSetPostamble(uint8_t cPostamble) -{ - /* Modifies the MBUS_PSTMBL register value */ - g_xStatus = SpiritSpiWriteRegisters(MBUS_PSTMBL_BASE, 1, &cPostamble); - -} - - -/** - * @brief Returns how many chip sequence "01" are used in the postamble - * @param None. - * @retval uint8_t Postamble in number of "01" chip sequences. - */ -uint8_t SpiritPktMbusGetPostamble(void) -{ - uint8_t tempRegValue; - - /* Reads the MBUS_PSTMBL register */ - g_xStatus = SpiritSpiReadRegisters(MBUS_PSTMBL_BASE, 1, &tempRegValue); - - /* Returns value */ - return tempRegValue; - -} - - -/** - * @brief Sets the MBUS submode used. - * @param xMbusSubmode the submode used. - * This parameter can be any value of @ref MbusSubmode. - * @retval None. - */ -void SpiritPktMbusSetSubmode(MbusSubmode xMbusSubmode) -{ - /* Modifies the MBUS_CTRL register value */ - g_xStatus = SpiritSpiWriteRegisters(MBUS_CTRL_BASE, 1, (uint8_t*)xMbusSubmode); - -} - - -/** - * @brief Returns the MBUS submode used. - * @param None. - * @retval MbusSubmode MBUS submode. - */ -MbusSubmode SpiritPktMbusGetSubmode(void) -{ - uint8_t tempRegValue; - - /* Reads the MBUS_CTRL register value */ - g_xStatus = SpiritSpiReadRegisters(MBUS_CTRL_BASE, 1, &tempRegValue); - - /* Returns value */ - return (MbusSubmode) tempRegValue; - -} - - -/** - * @brief Sets the payload length for SPIRIT MBUS packets. - * @param nPayloadLength payload length in bytes. - * This parameter is an uint16_t. - * @retval None. - */ -void SpiritPktMbusSetPayloadLength(uint16_t nPayloadLength) -{ - uint8_t tempRegValue[2]; - - /* Computes PCKTLEN0 value from nPayloadLength */ - tempRegValue[1]=BUILD_PCKTLEN0(nPayloadLength);//(uint8_t)nPayloadLength; - /* Computes PCKTLEN1 value from nPayloadLength */ - tempRegValue[0]=BUILD_PCKTLEN1(nPayloadLength);//(uint8_t)(nPayloadLength>>8); - - /* Writes data on the PCKTLEN1/0 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTLEN1_BASE, 2, tempRegValue); - -} - - -/** - * @brief Returns the payload length for SPIRIT MBUS packets. - * @param None. - * @retval uint16_t Payload length in bytes. - */ -uint16_t SpiritPktMbusGetPayloadLength(void) -{ - uint8_t tempRegValue[2]; - - /* Reads the packet length registers */ - g_xStatus = SpiritSpiReadRegisters(PCKTLEN1_BASE, 2, tempRegValue); - - /* Returns the packet length */ - return ((((uint16_t)tempRegValue[0])<<8) + (uint16_t) tempRegValue[1]); - -} - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktStack.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktStack.c deleted file mode 100644 index 55d11a6f6..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_PktStack.c +++ /dev/null @@ -1,687 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_PktStack.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT STack packets. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_PktStack.h" -#include "MCU_Interface.h" - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_PktStack - * @{ - */ - - -/** - * @defgroup PktStack_Private_TypesDefinitions Pkt STack Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktStack_Private_Defines Pkt STack Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktStack_Private_Macros Pkt STack Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktStack_Private_Variables Pkt STack Private Variables - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktStack_Private_FunctionPrototypes Pkt STack Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup PktStack_Private_Functions Pkt STack Private Functions - * @{ - */ - - -/** - * @brief Initializes the SPIRIT STack packet according to the specified - * parameters in the PktStackInit. - * @param pxPktStackInit STack packet init structure. - * This parameter is a pointer to @ref PktStackInit. - * @retval None. - */ -void SpiritPktStackInit(PktStackInit* pxPktStackInit) -{ - uint8_t tempRegValue[4], i; - - /* Check the parameters */ - s_assert_param(IS_STACK_PREAMBLE_LENGTH(pxPktStackInit->xPreambleLength)); - s_assert_param(IS_STACK_SYNC_LENGTH(pxPktStackInit->xSyncLength)); - s_assert_param(IS_STACK_CRC_MODE(pxPktStackInit->xCrcMode)); - s_assert_param(IS_STACK_LENGTH_WIDTH_BITS(pxPktStackInit->cPktLengthWidth)); - s_assert_param(IS_STACK_FIX_VAR_LENGTH(pxPktStackInit->xFixVarLength)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackInit->xFec)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackInit->xDataWhitening)); - s_assert_param(IS_STACK_CONTROL_LENGTH(pxPktStackInit->xControlLength)); - - - /* Reads the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); - - /* Mask a reserved bit */ - tempRegValue[0] &= ~0x20; - - /* Always (!) set the automatic packet filtering */ - tempRegValue[0] |= PROTOCOL1_AUTO_PCKT_FLT_MASK; - - /* Writes the value on register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue[0]); - - /* Reads the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Always reset the control and source filtering */ - tempRegValue[0] &= ~(PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK | PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK); - - /* Writes the value on register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - - /* Address and control length setting: source and destination address are always present so ADDRESS_LENGTH=2 */ - tempRegValue[0] = 0x10 | ((uint8_t) pxPktStackInit->xControlLength); - - - /* Packet format and width length setting */ - pxPktStackInit->cPktLengthWidth == 0 ? pxPktStackInit->cPktLengthWidth=1 : pxPktStackInit->cPktLengthWidth; - tempRegValue[1] = ((uint8_t) PCKTCTRL3_PCKT_FRMT_STACK) | ((uint8_t)(pxPktStackInit->cPktLengthWidth-1)); - - /* Preamble, sync and fixed or variable length setting */ - tempRegValue[2] = ((uint8_t) pxPktStackInit->xPreambleLength) | ((uint8_t) pxPktStackInit->xSyncLength) | - ((uint8_t) pxPktStackInit->xFixVarLength); - - /* CRC length, whitening and FEC setting */ - tempRegValue[3] = (uint8_t) pxPktStackInit->xCrcMode; - - if(pxPktStackInit->xDataWhitening == S_ENABLE) - { - tempRegValue[3] |= PCKTCTRL1_WHIT_MASK; - } - - if(pxPktStackInit->xFec == S_ENABLE) - { - tempRegValue[3] |= PCKTCTRL1_FEC_MASK; - } - - /* Writes registers */ - SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 4, tempRegValue); - - /* Sync words setting */ - for(i=0;i<4;i++) - { - if(i<3-(pxPktStackInit->xSyncLength >>1)) - { - tempRegValue[i]=0; - } - else - { - tempRegValue[i] = (uint8_t)(pxPktStackInit->lSyncWords>>(8*i)); - } - } - - /* Enables or disables the CRC check */ - if(pxPktStackInit->xCrcMode == PKT_NO_CRC) - { - SpiritPktStackFilterOnCrc(S_DISABLE); - } - else - { - SpiritPktStackFilterOnCrc(S_ENABLE); - } - - /* Writes registers */ - g_xStatus = SpiritSpiWriteRegisters(SYNC4_BASE, 4, tempRegValue); - -} - - -/** - * @brief Returns the SPIRIT STack packet structure according to the specified parameters in the registers. - * @param pxPktStackInit STack packet init structure. - * This parameter is a pointer to @ref PktStackInit. - * @retval None. - */ -void SpiritPktStackGetInfo(PktStackInit* pxPktStackInit) -{ - uint8_t tempRegValue[10]; - - /* Reads registers */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 10, tempRegValue); - - /* Length width */ - pxPktStackInit->cPktLengthWidth=(tempRegValue[1] & 0x0F)+1; - - /* Control length */ - pxPktStackInit->xControlLength=(StackControlLength)(tempRegValue[0] & 0x07); - - /* CRC mode */ - pxPktStackInit->xCrcMode=(StackCrcMode)(tempRegValue[3] & 0xE0); - - /* Whitening */ - pxPktStackInit->xDataWhitening=(SpiritFunctionalState)((tempRegValue[3] >> 4) & 0x01); - - /* FEC */ - pxPktStackInit->xFec=(SpiritFunctionalState)(tempRegValue[3] & 0x01); - - /* FIX or VAR bit */ - pxPktStackInit->xFixVarLength=(StackFixVarLength)(tempRegValue[2] & 0x01); - - /* Preamble length */ - pxPktStackInit->xPreambleLength=(StackPreambleLength)(tempRegValue[2] & 0xF8); - - /* Sync length */ - pxPktStackInit->xSyncLength=(StackSyncLength)(tempRegValue[2] & 0x06); - - /* sync Words */ - pxPktStackInit->lSyncWords=0; - for(uint8_t i=0 ; i<4 ; i++) - { - if(i>2-(pxPktStackInit->xSyncLength >>1)) - { - pxPktStackInit->lSyncWords |= tempRegValue[i+6]<<(8*i); - } - } - -} - - -/** - * @brief Initializes the SPIRIT STack packet addresses according to the specified - * parameters in the PktStackAddresses struct. - * @param pxPktStackAddresses STack packet addresses init structure. - * This parameter is a pointer to @ref PktStackAddressesInit . - * @retval None. - */ -void SpiritPktStackAddressesInit(PktStackAddressesInit* pxPktStackAddresses) -{ - uint8_t tempRegValue[3]; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackAddresses->xFilterOnMyAddress)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackAddresses->xFilterOnMulticastAddress)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackAddresses->xFilterOnBroadcastAddress)); - - /* Reads the filtering options ragister */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Enables or disables filtering on my address */ - if(pxPktStackAddresses->xFilterOnMyAddress == S_ENABLE) - { - tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; - } - else - { - tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK; - } - - /* Enables or disables filtering on multicast address */ - if(pxPktStackAddresses->xFilterOnMulticastAddress == S_ENABLE) - { - tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; - } - else - { - tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK; - } - - /* Enables or disables filtering on broadcast address */ - if(pxPktStackAddresses->xFilterOnBroadcastAddress == S_ENABLE) - { - tempRegValue[0] |= PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; - } - else - { - tempRegValue[0] &= ~PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK; - } - - /* Writes value on the register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Fills array with the addresses passed in the structure */ - tempRegValue[0] = pxPktStackAddresses->cBroadcastAddress; - tempRegValue[1] = pxPktStackAddresses->cMulticastAddress; - tempRegValue[2] = pxPktStackAddresses->cMyAddress; - - /* Writes them on the addresses registers */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); - -} - - -/** -* @brief Returns the SPIRIT STack packet addresses structure according to the specified -* parameters in the registers. -* @param pxPktStackAddresses STack packet addresses init structure. -* This parameter is a pointer to @ref PktStackAddresses. -* @retval None. -*/ -void SpiritPktStackGetAddressesInfo(PktStackAddressesInit* pxPktStackAddresses) -{ - uint8_t tempRegValue[3]; - - /* Reads values on the PCKT_FLT_GOALS registers */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_BROADCAST_BASE, 3, tempRegValue); - - /* Fit the structure with the read addresses */ - pxPktStackAddresses->cBroadcastAddress = tempRegValue[0]; - pxPktStackAddresses->cMulticastAddress = tempRegValue[1]; - pxPktStackAddresses->cMyAddress = tempRegValue[2]; - - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue[0]); - - /* Fit the structure with the read filtering bits */ - pxPktStackAddresses->xFilterOnBroadcastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 1) & 0x01); - pxPktStackAddresses->xFilterOnMulticastAddress = (SpiritFunctionalState)((tempRegValue[0] >> 2) & 0x01); - pxPktStackAddresses->xFilterOnMyAddress = (SpiritFunctionalState)((tempRegValue[0] >> 3) & 0x01); - -} - - -/** -* @brief Initializes the SPIRIT STack packet LLP options according to the specified -* parameters in the PktStackLlpInit struct. -* @param pxPktStackLlpInit STack packet LLP init structure. -* This parameter is a pointer to @ref PktStackLlpInit. -* @retval None. -*/ -void SpiritPktStackLlpInit(PktStackLlpInit* pxPktStackLlpInit) -{ - uint8_t tempRegValue[2]; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackLlpInit->xPiggybacking)); - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(pxPktStackLlpInit->xAutoAck)); - s_assert_param(IS_STACK_NMAX_RETX(pxPktStackLlpInit->xNMaxRetx)); - /* check if piggybacking is enabled and autoack is disabled */ - s_assert_param(!(pxPktStackLlpInit->xPiggybacking==S_ENABLE && pxPktStackLlpInit->xAutoAck==S_DISABLE)); - - /* Piggybacking mechanism setting on the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 2, tempRegValue); - if(pxPktStackLlpInit->xPiggybacking == S_ENABLE) - { - tempRegValue[0] |= PROTOCOL1_PIGGYBACKING_MASK; - } - else - { - tempRegValue[0] &= ~PROTOCOL1_PIGGYBACKING_MASK; - } - - /* RX and TX autoack mechanisms setting on the PROTOCOL0 register */ - if(pxPktStackLlpInit->xAutoAck == S_ENABLE) - { - tempRegValue[1] |= PROTOCOL0_AUTO_ACK_MASK; - } - else - { - tempRegValue[1] &= ~PROTOCOL0_AUTO_ACK_MASK; - } - - /* Max number of retransmission setting */ - tempRegValue[1] &= ~PROTOCOL0_NMAX_RETX_MASK; - tempRegValue[1] |= pxPktStackLlpInit->xNMaxRetx; - - /* Writes registers */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 2, tempRegValue); - -} - - -/** - * @brief Returns the SPIRIT STack packet LLP options according to the specified - * values in the registers. - * @param pxPktStackLlpInit STack packet LLP structure. - * This parameter is a pointer to @ref PktStackLlpInit. - * @retval None. - */ -void SpiritPktStackLlpGetInfo(PktStackLlpInit* pxPktStackLlpInit) -{ - uint8_t tempRegValue[2]; - - /* Piggybacking mechanism setting on the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 2, tempRegValue); - - /* Fit the structure with the read values */ - pxPktStackLlpInit->xPiggybacking = (SpiritFunctionalState)((tempRegValue[0] >> 6) & 0x01); - pxPktStackLlpInit->xAutoAck = (SpiritFunctionalState)((tempRegValue[1] >> 2) & 0x01); - pxPktStackLlpInit->xNMaxRetx = (StackNMaxReTx)(tempRegValue[1] & PROTOCOL0_NMAX_RETX_MASK); - -} - - -/** - * @brief Configures the STack packet format for SPIRIT. - * @param None. - * @retval None. - */ -void SpiritPktStackSetFormat(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL3 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Build value to be written. Also set to 0 the direct RX mode bits */ - tempRegValue &= 0x0F; - tempRegValue |= ((uint8_t)PCKTCTRL3_PCKT_FRMT_STACK); - - /* Writes the value on the PCKTCTRL3 register. */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Reads the PCKTCTRL1 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Build the new value. Set to 0 the direct TX mode bits */ - tempRegValue &= 0xF3; - - /* Writes the PCKTCTRL1 value on register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL1_BASE, 1, &tempRegValue); - - /* Reads the PROTOCOL1 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Mask a reserved bit */ - tempRegValue &= ~0x20; - - /* Writes the value on the PROTOCOL1 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets the address length for SPIRIT STack packets (always 2). - * @param None. - * @retval None. - */ -void SpiritPktStackSetAddressLength(void) -{ - uint8_t tempRegValue; - - /* Reads the PCKTCTRL4 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - - /* Build the new value */ - tempRegValue &= ~PCKTCTRL4_ADDRESS_LEN_MASK; - tempRegValue |= ((uint8_t)0x10); - - /* Writes the value on the PCKTCTRL4 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL4_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets the payload length for SPIRIT STack packets. Since the packet length - * depends from the address (always 2 for this packet format) - * and the control field size, this function reads the control length register - * content in order to determine the correct packet length to be written. - * @param nPayloadLength payload length in bytes. - * This parameter can be any value of uint16_t. - * @retval None. - */ -void SpiritPktStackSetPayloadLength(uint16_t nPayloadLength) -{ - uint8_t tempRegValue[2]; - - /* Computes the oversize (address + control) size */ - uint16_t overSize = 2 + (uint16_t) SpiritPktStackGetControlLength(); - - /* Computes PCKTLEN0 value from lPayloadLength */ - tempRegValue[1]=STACK_BUILD_PCKTLEN0(nPayloadLength+overSize); - /* Computes PCKTLEN1 value from lPayloadLength */ - tempRegValue[0]=STACK_BUILD_PCKTLEN1(nPayloadLength+overSize); - - /* Writes the value on the PCKTLENx registers */ - g_xStatus = SpiritSpiWriteRegisters(PCKTLEN1_BASE, 2, tempRegValue); - -} - - -/** - * @brief Returns the payload length for SPIRIT STack packets. Since the - * packet length depends from the address and the control - * field size, this function reads the correspondent - * registers in order to determine the correct payload length - * to be returned. - * @param None. - * @retval uint16_t Payload length. - */ -uint16_t SpiritPktStackGetPayloadLength(void) -{ - uint8_t tempRegValue[2]; - /* Computes the oversize (address + control) size */ - uint16_t overSize = 2 + (uint16_t) SpiritPktStackGetControlLength(); - - /* Reads the PCKTLEN1 registers value */ - g_xStatus = SpiritSpiReadRegisters(PCKTLEN1_BASE, 2, tempRegValue); - - /* Rebuild and return the payload length value */ - return (((uint16_t) tempRegValue[1])<<8 + (uint16_t) tempRegValue[0] - overSize); - -} - - -/** - * @brief Computes and sets the variable payload length for SPIRIT STack packets. - * @param nMaxPayloadLength payload length in bytes. - * This parameter is an uint16_t. - * @param xControlLength control length in bytes. - * This parameter can be any value of @ref StackControlLength. - * @retval None. - */ -void SpiritPktStackSetVarLengthWidth(uint16_t nMaxPayloadLength, StackControlLength xControlLength) -{ - uint8_t tempRegValue, - i; - uint32_t packetLength; - - - /* packet length = payload length + address length (2) + control length */ - packetLength=nMaxPayloadLength+2+xControlLength; - - /* Computes the number of bits */ - for(i=0;i<16;i++) - { - if(packetLength == 0) - { - break; - } - packetLength >>= 1; - } - i==0 ? i=1 : i; - - /* Reads the PCKTCTRL3 register value */ - g_xStatus = SpiritSpiReadRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - - /* Build the register value */ - tempRegValue &= ~PCKTCTRL3_LEN_WID_MASK; - tempRegValue |= ((uint8_t)(i-1)); - - /* Writes the PCKTCTRL3 register value */ - g_xStatus = SpiritSpiWriteRegisters(PCKTCTRL3_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Rx packet source mask. Used to mask the address of the accepted packets. If 0 -> no filtering. - * @param cMask Rx source mask. - * This parameter is an uint8_t. - * @retval None. - */ -void SpiritPktStackSetRxSourceMask(uint8_t cMask) -{ - /* Writes value on the register PCKT_FLT_GOALS_SOURCE_MASK */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_GOALS_SOURCE_MASK_BASE, 1, &cMask); - -} - - -/** - * @brief Returns the Rx packet source mask. Used to mask the address of the accepted packets. If 0 -> no filtering. - * @param None. - * @retval uint8_t Rx source mask. - */ -uint8_t SpiritPktStackGetRxSourceMask(void) -{ - uint8_t tempRegValue; - - /* Writes value on the PCKT_FLT_GOALS_SOURCE_MASK register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_GOALS_SOURCE_MASK_BASE, 1, &tempRegValue); - - /* Return the read value */ - return tempRegValue; - -} - -/** - * @brief Returns the packet length field of the received packet. - * @param None. - * @retval uint16_t Packet length. - */ -uint16_t SpiritPktStackGetReceivedPktLength(void) -{ - uint8_t tempRegValue[2]; - uint16_t tempLength; - - /* Reads the RX_PCKT_LENx registers value */ - g_xStatus = SpiritSpiReadRegisters(RX_PCKT_LEN1_BASE, 2, tempRegValue); - - /* Rebuild and return the the length field */ - tempLength = ((((uint16_t) tempRegValue[0]) << 8) + (uint16_t) tempRegValue[1]); - - /* Computes the oversize (address + control) size */ - tempLength -= 2 + (uint16_t) SpiritPktStackGetControlLength(); - - return tempLength; - -} - - -/** - * @brief If enabled RX packet is accepted only if the masked source address field matches the - * masked source address field reference (SOURCE_MASK & SOURCE_FIELD_REF == SOURCE_MASK & RX_SOURCE_FIELD). - * @param xNewState new state for Source address filtering enable bit. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - * @note This filtering control is enabled by default but the source address mask is by default set to 0. - * As a matter of fact the user has to enable the source filtering bit after the packet initialization - * because the PktInit routine disables it. - */ -void SpiritPktStackFilterOnSourceAddress(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - - /* Modify the register value: set or reset the source bit filtering */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - - /* Set or reset the SOURCE ADDRESS filtering enabling bit */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK; - } - else - { - tempRegValue &= ~PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK; - } - - /* Writes the new value on the PCKT_FLT_OPTIONS register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 1, &tempRegValue); - -} - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Qi.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Qi.c deleted file mode 100644 index 8d042675f..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Qi.c +++ /dev/null @@ -1,636 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Qi.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT QI. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Qi.h" -#include "MCU_Interface.h" - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_Qi - * @{ - */ - - -/** - * @defgroup Qi_Private_TypesDefinitions QI Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Qi_Private_Defines QI Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Qi_Private_Macros QI Private Macros - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Qi_Private_Variables QI Private Variables - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Qi_Private_FunctionPrototypes QI Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Qi_Private_Functions QI Private Functions - * @{ - */ - -/** - * @brief Enables/Disables the PQI Preamble Quality Indicator check. The running peak PQI is - * compared to a threshold value and the preamble valid IRQ is asserted as soon as the threshold is passed. - * @param xNewState new state for PQI check. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritQiPqiCheck(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the QI register value */ - g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); - - /* Enables or disables the PQI Check bit on the QI_BASE register */ - if(xNewState == S_ENABLE) - { - tempRegValue |= QI_PQI_MASK; - } - else - { - tempRegValue &= ~QI_PQI_MASK; - } - - /* Writes value on the QI register */ - g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Enables/Disables the Synchronization Quality Indicator check. The running peak SQI is - * compared to a threshold value and the sync valid IRQ is asserted as soon as the threshold is passed. - * @param xNewState new state for SQI check. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritQiSqiCheck(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the QI register value */ - g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); - - /* Enables or disables the SQI Check bit on the QI_BASE register */ - if(xNewState == S_ENABLE) - { - tempRegValue |= QI_SQI_MASK; - } - else - { - tempRegValue &= ~QI_SQI_MASK; - } - - /* Writes value on the QI register */ - g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Sets the PQI threshold. The preamble quality threshold is 4*PQI_TH (PQI_TH = 0..15). - * @param xPqiThr parameter of the formula above. - * This variable is a @ref PqiThreshold. - * @retval None. - */ -void SpiritQiSetPqiThreshold(PqiThreshold xPqiThr) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PQI_THR(xPqiThr)); - - /* Reads the QI register value */ - g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); - - /* Build the PQI threshold value to be written */ - tempRegValue &= 0xC3; - tempRegValue |= ((uint8_t)xPqiThr); - - /* Writes value on the QI register */ - g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the PQI threshold. The preamble quality threshold is 4*PQI_TH (PQI_TH = 0..15). - * @param None. - * @retval PqiThreshold PQI threshold (PQI_TH of the formula above). - */ -PqiThreshold SpiritQiGetPqiThreshold(void) -{ - uint8_t tempRegValue; - - /* Reads the QI register value */ - g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); - - /* Rebuild and return the PQI threshold value */ - return (PqiThreshold)(tempRegValue & 0x3C); - -} - - -/** - * @brief Sets the SQI threshold. The synchronization quality - * threshold is equal to 8 * SYNC_LEN - 2 * SQI_TH with SQI_TH = 0..3. When SQI_TH is 0 perfect match is required; when - * SQI_TH = 1, 2, 3 then 1, 2, or 3 bit errors are respectively accepted. It is recommended that the SQI check is always - * enabled. - * @param xSqiThr parameter of the formula above. - * This parameter is a @ref SqiThreshold. - * @retval None. - */ -void SpiritQiSetSqiThreshold(SqiThreshold xSqiThr) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SQI_THR(xSqiThr)); - - /* Reads the QI register value */ - g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); - - /* Build the SQI threshold value to be written */ - tempRegValue &= 0x3F; - tempRegValue |= ((uint8_t)xSqiThr); - - /* Writes the new value on the QI register */ - g_xStatus = SpiritSpiWriteRegisters(QI_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the SQI threshold. The synchronization quality threshold is equal to 8 * SYNC_LEN - 2 * SQI_TH with SQI_TH = 0..3. - * @param None. - * @retval SqiThreshold SQI threshold (SQI_TH of the formula above). - */ -SqiThreshold SpiritQiGetSqiThreshold(void) -{ - uint8_t tempRegValue; - - /* Reads the QI register value */ - g_xStatus = SpiritSpiReadRegisters(QI_BASE, 1, &tempRegValue); - - /* Rebuild and return the SQI threshold value */ - return (SqiThreshold)(tempRegValue & 0xC0); - -} - - -/** - * @brief Returns the PQI value. - * @param None. - * @retval uint8_t PQI value. - */ -uint8_t SpiritQiGetPqi(void) -{ - uint8_t tempRegValue; - - /* Reads the LINK_QUALIF2 register value */ - g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF2_BASE, 1, &tempRegValue); - - /* Returns the PQI value */ - return tempRegValue; - -} - - -/** - * @brief Returns the SQI value. - * @param None. - * @retval uint8_t SQI value. - */ -uint8_t SpiritQiGetSqi(void) -{ - uint8_t tempRegValue; - - /* Reads the register LINK_QUALIF1 value */ - g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF1_BASE, 1, &tempRegValue); - - /* Rebuild and return the SQI value */ - return (tempRegValue & 0x7F); - -} - - -/** - * @brief Returns the LQI value. - * @param None. - * @retval uint8_t LQI value. - */ -uint8_t SpiritQiGetLqi(void) -{ - uint8_t tempRegValue; - - /* Reads the LINK_QUALIF0 register value */ - g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF0_BASE, 1, &tempRegValue); - - /* Rebuild and return the LQI value */ - return ((tempRegValue & 0xF0)>> 4); - -} - - -/** - * @brief Returns the CS status. - * @param None. - * @retval SpiritFlagStatus CS value (S_SET or S_RESET). - */ -SpiritFlagStatus SpiritQiGetCs(void) -{ - uint8_t tempRegValue; - - /* Reads the LINK_QUALIF1 register value */ - g_xStatus = SpiritSpiReadRegisters(LINK_QUALIF1_BASE, 1, &tempRegValue); - - /* Rebuild and returns the CS status value */ - if((tempRegValue & 0x80) == 0) - { - return S_RESET; - } - else - { - return S_SET; - } - -} - - -/** - * @brief Returns the RSSI value. The measured power is reported in steps of half a dB from 0 to 255 and is offset in such a way that -120 dBm corresponds - * to 20. - * @param None. - * @retval uint8_t RSSI value. - */ -uint8_t SpiritQiGetRssi(void) -{ - uint8_t tempRegValue; - - /* Reads the RSSI_LEVEL register value */ - g_xStatus = SpiritSpiReadRegisters(RSSI_LEVEL_BASE, 1, &tempRegValue); - - /* Returns the RSSI value */ - return tempRegValue; - -} - - -/** - * @brief Sets the RSSI threshold. - * @param cRssiThr RSSI threshold reported in steps of half a dBm with a -130 dBm offset. - * This parameter must be a uint8_t. - * @retval None. - */ -void SpiritQiSetRssiThreshold(uint8_t cRssiThr) -{ - /* Writes the new value on the RSSI_TH register */ - g_xStatus = SpiritSpiWriteRegisters(RSSI_TH_BASE, 1, &cRssiThr); - -} - - -/** - * @brief Returns the RSSI threshold. - * @param None. - * @retval uint8_t RSSI threshold. - */ -uint8_t SpiritQiGetRssiThreshold(void) -{ - uint8_t tempRegValue; - - /* Reads the RSSI_TH register value */ - g_xStatus = SpiritSpiReadRegisters(RSSI_TH_BASE, 1, &tempRegValue); - - /* Returns RSSI threshold */ - return tempRegValue; - -} - - -/** - * @brief Computes the RSSI threshold from its dBm value according to the formula: (RSSI[Dbm] + 130)/0.5 - * @param nDbmValue RSSI threshold reported in dBm. - * This parameter must be a sint16_t. - * @retval uint8_t RSSI threshold corresponding to dBm value. - */ -uint8_t SpiritQiComputeRssiThreshold(int nDbmValue) -{ - /* Check the parameters */ - s_assert_param(IS_RSSI_THR_DBM(nDbmValue)); - - /* Computes the RSSI threshold for register */ - return 2*(nDbmValue+130); - -} - -/** - * @brief Sets the RSSI threshold from its dBm value according to the formula: (RSSI[Dbm] + 130)/0.5. - * @param nDbmValue RSSI threshold reported in dBm. - * This parameter must be a sint16_t. - * @retval None. - */ -void SpiritQiSetRssiThresholddBm(int nDbmValue) -{ - uint8_t tempRegValue=2*(nDbmValue+130); - - /* Check the parameters */ - s_assert_param(IS_RSSI_THR_DBM(nDbmValue)); - - /* Writes the new value on the RSSI_TH register */ - g_xStatus = SpiritSpiWriteRegisters(RSSI_TH_BASE, 1, &tempRegValue); - -} - -/** - * @brief Sets the RSSI filter gain. This parameter sets the bandwidth of a low pass IIR filter (RSSI_FLT register, allowed values 0..15), a - * lower values gives a faster settling of the measurements but lower precision. The recommended value for such parameter is 14. - * @param xRssiFg RSSI filter gain value. - * This parameter can be any value of @ref RssiFilterGain. - * @retval None. - */ -void SpiritQiSetRssiFilterGain(RssiFilterGain xRssiFg) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_RSSI_FILTER_GAIN(xRssiFg)); - - /* Reads the RSSI_FLT register */ - g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - - /* Sets the specified filter gain */ - tempRegValue &= 0x0F; - tempRegValue |= ((uint8_t)xRssiFg); - - /* Writes the new value on the RSSI_FLT register */ - g_xStatus = SpiritSpiWriteRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the RSSI filter gain. - * @param None. - * @retval RssiFilterGain RSSI filter gain. - */ -RssiFilterGain SpiritQiGetRssiFilterGain(void) -{ - uint8_t tempRegValue; - - /* Reads the RSSI_FLT register */ - g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - - /* Rebuild and returns the filter gain value */ - return (RssiFilterGain)(tempRegValue & 0xF0); - -} - - -/** - * @brief Sets the CS Mode. When static carrier sensing is used (cs_mode = 0), the carrier sense signal is asserted when the measured RSSI is above the - * value specified in the RSSI_TH register and is deasserted when the RSSI falls 3 dB below the same threshold. - * When dynamic carrier sense is used (cs_mode = 1, 2, 3), the carrier sense signal is asserted if the signal is above the - * threshold and a fast power increase of 6, 12 or 18 dB is detected; it is deasserted if a power fall of the same amplitude is - * detected. - * @param xCsMode CS mode selector. - * This parameter can be any value of @ref CSMode. - * @retval None. - */ -void SpiritQiSetCsMode(CSMode xCsMode) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_CS_MODE(xCsMode)); - - /* Reads the RSSI_FLT register */ - g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - - /* Sets bit to select the CS mode */ - tempRegValue &= ~0x0C; - tempRegValue |= ((uint8_t)xCsMode); - - /* Writes the new value on the RSSI_FLT register */ - g_xStatus = SpiritSpiWriteRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the CS Mode. - * @param None. - * @retval CSMode CS mode. - */ -CSMode SpiritQiGetCsMode(void) -{ - uint8_t tempRegValue; - - /* Reads the RSSI_FLT register */ - g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - - /* Rebuild and returns the CS mode value */ - return (CSMode)(tempRegValue & 0x0C); - -} - -/** - * @brief Enables/Disables the CS Timeout Mask. If enabled CS value contributes to timeout disabling. - * @param xNewState new state for CS Timeout Mask. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritQiCsTimeoutMask(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PROTOCOL2 register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - - /* Enables or disables the CS timeout mask */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PROTOCOL2_CS_TIMEOUT_MASK; - } - else - { - tempRegValue &= ~PROTOCOL2_CS_TIMEOUT_MASK; - } - - /* Writes the new value on the PROTOCOL2 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Enables/Disables the PQI Timeout Mask. If enabled PQI value contributes to timeout disabling. - * @param xNewState new state for PQI Timeout Mask. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritQiPqiTimeoutMask(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PROTOCOL2 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - - /* Enables or disables the PQI timeout mask */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PROTOCOL2_PQI_TIMEOUT_MASK; - } - else - { - tempRegValue &= ~PROTOCOL2_PQI_TIMEOUT_MASK; - } - - /* Writes the new value on the PROTOCOL2 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Enables/Disables the SQI Timeout Mask. If enabled SQI value contributes to timeout disabling. - * @param xNewState new state for SQI Timeout Mask. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritQiSqiTimeoutMask(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PROTOCOL2 register */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - - /* Enables or disables the SQI timeout mask */ - if(xNewState == S_ENABLE) - { - tempRegValue |= PROTOCOL2_SQI_TIMEOUT_MASK; - } - else - { - tempRegValue &= ~PROTOCOL2_SQI_TIMEOUT_MASK; - } - - /* Writes the new value on the PROTOCOL2 register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - -} - - -/** - *@} - */ - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Radio.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Radio.c deleted file mode 100644 index 8a129c003..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Radio.c +++ /dev/null @@ -1,3144 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Radio.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief This file provides all the low level API to manage Analog and Digital - * radio part of SPIRIT. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Radio.h" -#include "MCU_Interface.h" -#include - -/** @addtogroup SPIRIT_Libraries -* @{ -*/ - - -/** @addtogroup SPIRIT_Radio -* @{ -*/ - - -/** @defgroup Radio_Private_TypesDefinitions Radio Private Types Definitions -* @{ -*/ - - -/** -* @} -*/ - - -/** @defgroup Radio_Private_Defines Radio Private Defines -* @{ -*/ - - - - -/** -* @} -*/ - - -/** @defgroup Radio_Private_Macros Radio Private Macros -* @{ -*/ -#define XTAL_FLAG(xtalFrequency) (xtalFrequency>=25e6) ? XTAL_FLAG_26_MHz:XTAL_FLAG_24_MHz - -#define ROUND(A) (((A-(uint32_t)A)> 0.5)? (uint32_t)A+1:(uint32_t)A) -/** -* @} -*/ - - -/** @defgroup Radio_Private_Variables Radio Private Variables -* @{ -*/ -/** -* @brief The Xtal frequency. To be set by the user (see SetXtalFreq() function) -*/ -static uint32_t s_lXtalFrequency; - -/** -* @brief Factor is: B/2 used in the formula for SYNTH word calculation -*/ -static const uint8_t s_vectcBHalfFactor[4]={(HIGH_BAND_FACTOR/2), (MIDDLE_BAND_FACTOR/2), (LOW_BAND_FACTOR/2), (VERY_LOW_BAND_FACTOR/2)}; - -/** -* @brief BS value to write in the SYNT0 register according to the selected band -*/ -static const uint8_t s_vectcBandRegValue[4]={SYNT0_BS_6, SYNT0_BS_12, SYNT0_BS_16, SYNT0_BS_32}; - - -/** -* @brief It represents the available channel bandwidth times 10 for 26 Mhz xtal. -* @note The channel bandwidth for others xtal frequencies can be computed since this table -* multiplying the current table by a factor xtal_frequency/26e6. -*/ -static const uint16_t s_vectnBandwidth26M[90]= -{ - 8001, 7951, 7684, 7368, 7051, 6709, 6423, 5867, 5414, \ - 4509, 4259, 4032, 3808, 3621, 3417, 3254, 2945, 2703, \ - 2247, 2124, 2015, 1900, 1807, 1706, 1624, 1471, 1350, \ - 1123, 1062, 1005, 950, 903, 853, 812, 735, 675, \ - 561, 530, 502, 474, 451, 426, 406, 367, 337, \ - 280, 265, 251, 237, 226, 213, 203, 184, 169, \ - 140, 133, 126, 119, 113, 106, 101, 92, 84, \ - 70, 66, 63, 59, 56, 53, 51, 46, 42, \ - 35, 33, 31, 30, 28, 27, 25, 23, 21, \ - 18, 17, 16, 15, 14, 13, 13, 12, 11 -}; - -/** -* @brief It represents the available VCO frequencies -*/ -static const uint16_t s_vectnVCOFreq[16]= -{ - 4644, 4708, 4772, 4836, 4902, 4966, 5030, 5095, \ - 5161, 5232, 5303, 5375, 5448, 5519, 5592, 5663 -}; - -/** -* @brief This variable is used to enable or disable -* the VCO calibration WA called at the end of the SpiritRadioSetFrequencyBase fcn. -* Default is enabled. -*/ -static SpiritFunctionalState xDoVcoCalibrationWA=S_ENABLE; - - -/** -* @brief These values are used to interpolate the power curves. -* Interpolation curves are linear in the following 3 regions: -* - reg value: 1 to 13 (up region) -* - reg value: 13 to 40 (mid region) -* - reg value: 41 to 90 (low region) -* power_reg = m*power_dBm + q -* For each band the order is: {m-up, q-up, m-mid, q-mid, m-low, q-low}. -* @note The power interpolation curves have been extracted -* by measurements done on the divisional evaluation boards. -*/ -static const float fPowerFactors[5][6]={ - {-2.11,25.66,-2.11,25.66,-2.00,31.28}, /* 915 */ - {-2.04,23.45,-2.04,23.45,-1.95,27.66}, /* 868 */ - {-3.48,38.45,-1.89,27.66,-1.92,30.23}, /* 433 */ - {-3.27,35.43,-1.80,26.31,-1.89,29.61}, /* 315 */ - {-4.18,50.66,-1.80,30.04,-1.86,32.22}, /* 169 */ -}; - -/** -* @} -*/ - - -/** @defgroup Radio_Private_FunctionPrototypes Radio Private Function Prototypes -* @{ -*/ - - -/** -* @} -*/ - - -/** @defgroup Radio_Private_Functions Radio Private Functions -* @{ -*/ - -/** -* @brief Initializes the SPIRIT analog and digital radio part according to the specified -* parameters in the pxSRadioInitStruct. -* @param pxSRadioInitStruct pointer to a SRadioInit structure that -* contains the configuration information for the analog radio part of SPIRIT. -* @retval Error code: 0=no error, 1=error during calibration of VCO. -*/ -uint8_t SpiritRadioInit(SRadioInit* pxSRadioInitStruct) -{ - int32_t FOffsetTmp; - uint8_t anaRadioRegArray[8], digRadioRegArray[4]; - int16_t xtalOffsetFactor; - uint8_t drM, drE, FdevM, FdevE, bwM, bwE; - - /* Workaround for Vtune */ - uint8_t value = 0xA0; SpiritSpiWriteRegisters(0x9F, 1, &value); - - /* Calculates the offset respect to RF frequency and according to xtal_ppm parameter: (xtal_ppm*FBase)/10^6 */ - FOffsetTmp = (int32_t)(((float)pxSRadioInitStruct->nXtalOffsetPpm*pxSRadioInitStruct->lFrequencyBase)/PPM_FACTOR); - - /* Check the parameters */ - s_assert_param(IS_FREQUENCY_BAND(pxSRadioInitStruct->lFrequencyBase)); - s_assert_param(IS_MODULATION_SELECTED(pxSRadioInitStruct->xModulationSelect)); - s_assert_param(IS_DATARATE(pxSRadioInitStruct->lDatarate)); - s_assert_param(IS_FREQUENCY_OFFSET(FOffsetTmp,s_lXtalFrequency)); - s_assert_param(IS_CHANNEL_SPACE(pxSRadioInitStruct->nChannelSpace,s_lXtalFrequency)); - s_assert_param(IS_F_DEV(pxSRadioInitStruct->lFreqDev,s_lXtalFrequency)); - - /* Disable the digital, ADC, SMPS reference clock divider if fXO>24MHz or fXO<26MHz */ - SpiritSpiCommandStrobes(COMMAND_STANDBY); - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - }while(g_xStatus.MC_STATE!=MC_STATE_STANDBY); - - if(s_lXtalFrequencylBandwidth,s_lXtalFrequency)); - } - else - { - SpiritRadioSetDigDiv(S_ENABLE); - s_assert_param(IS_CH_BW(pxSRadioInitStruct->lBandwidth,(s_lXtalFrequency>>1))); - } - - /* Goes in READY state */ - SpiritSpiCommandStrobes(COMMAND_READY); - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - }while(g_xStatus.MC_STATE!=MC_STATE_READY); - - /* Calculates the FC_OFFSET parameter and cast as signed int: FOffsetTmp = (Fxtal/2^18)*FC_OFFSET */ - xtalOffsetFactor = (int16_t)(((float)FOffsetTmp*FBASE_DIVIDER)/s_lXtalFrequency); - anaRadioRegArray[2] = (uint8_t)((((uint16_t)xtalOffsetFactor)>>8)&0x0F); - anaRadioRegArray[3] = (uint8_t)(xtalOffsetFactor); - - /* Calculates the channel space factor */ - anaRadioRegArray[0] =((uint32_t)pxSRadioInitStruct->nChannelSpace<<9)/(s_lXtalFrequency>>6)+1; - - SpiritManagementWaTRxFcMem(pxSRadioInitStruct->lFrequencyBase); - - /* 2nd order DEM algorithm enabling */ - uint8_t tmpreg; SpiritSpiReadRegisters(0xA3, 1, &tmpreg); - tmpreg &= ~0x02; SpiritSpiWriteRegisters(0xA3, 1, &tmpreg); - - /* Check the channel center frequency is in one of the possible range */ - s_assert_param(IS_FREQUENCY_BAND((pxSRadioInitStruct->lFrequencyBase + ((xtalOffsetFactor*s_lXtalFrequency)/FBASE_DIVIDER) + pxSRadioInitStruct->nChannelSpace * pxSRadioInitStruct->cChannelNumber))); - - /* Calculates the datarate mantissa and exponent */ - SpiritRadioSearchDatarateME(pxSRadioInitStruct->lDatarate, &drM, &drE); - digRadioRegArray[0] = (uint8_t)(drM); - digRadioRegArray[1] = (uint8_t)(0x00 | pxSRadioInitStruct->xModulationSelect |drE); - - /* Read the fdev register to preserve the clock recovery algo bit */ - SpiritSpiReadRegisters(0x1C, 1, &tmpreg); - - /* Calculates the frequency deviation mantissa and exponent */ - SpiritRadioSearchFreqDevME(pxSRadioInitStruct->lFreqDev, &FdevM, &FdevE); - digRadioRegArray[2] = (uint8_t)((FdevE<<4) | (tmpreg&0x08) | FdevM); - - /* Calculates the channel filter mantissa and exponent */ - SpiritRadioSearchChannelBwME(pxSRadioInitStruct->lBandwidth, &bwM, &bwE); - - digRadioRegArray[3] = (uint8_t)((bwM<<4) | bwE); - - float if_off=(3.0*480140)/(s_lXtalFrequency>>12)-64; - - uint8_t ifOffsetAna = ROUND(if_off); - - if(s_lXtalFrequency>13)-64; - - /* ... otherwise recompute it */ - anaRadioRegArray[1] = ROUND(if_off); - } -// if(s_lXtalFrequency==24000000) { -// ifOffsetAna = 0xB6; -// anaRadioRegArray[1] = 0xB6; -// } -// if(s_lXtalFrequency==25000000) { -// ifOffsetAna = 0xAC; -// anaRadioRegArray[1] = 0xAC; -// } -// if(s_lXtalFrequency==26000000) { -// ifOffsetAna = 0xA3; -// anaRadioRegArray[1] = 0xA3; -// } -// if(s_lXtalFrequency==48000000) { -// ifOffsetAna = 0x3B; -// anaRadioRegArray[1] = 0xB6; -// } -// if(s_lXtalFrequency==50000000) { -// ifOffsetAna = 0x36; -// anaRadioRegArray[1] = 0xAC; -// } -// if(s_lXtalFrequency==52000000) { -// ifOffsetAna = 0x31; -// anaRadioRegArray[1] = 0xA3; -// } - - g_xStatus = SpiritSpiWriteRegisters(IF_OFFSET_ANA_BASE, 1, &ifOffsetAna); - - - /* Sets Xtal configuration */ - if(s_lXtalFrequency>DOUBLE_XTAL_THR) - { - SpiritRadioSetXtalFlag(XTAL_FLAG((s_lXtalFrequency/2))); - } - else - { - SpiritRadioSetXtalFlag(XTAL_FLAG(s_lXtalFrequency)); - } - - /* Sets the channel number in the corresponding register */ - SpiritSpiWriteRegisters(CHNUM_BASE, 1, &pxSRadioInitStruct->cChannelNumber); - - /* Configures the Analog Radio registers */ - SpiritSpiWriteRegisters(CHSPACE_BASE, 4, anaRadioRegArray); - - /* Configures the Digital Radio registers */ - g_xStatus = SpiritSpiWriteRegisters(MOD1_BASE, 4, digRadioRegArray); - - /* Enable the freeze option of the AFC on the SYNC word */ - SpiritRadioAFCFreezeOnSync(S_ENABLE); - - /* Set the IQC correction optimal value */ - anaRadioRegArray[0]=0x80; - anaRadioRegArray[1]=0xE3; - g_xStatus = SpiritSpiWriteRegisters(0x99, 2, anaRadioRegArray); - - return SpiritRadioSetFrequencyBase(pxSRadioInitStruct->lFrequencyBase); - -} - - -/** -* @brief Returns the SPIRIT analog and digital radio structure according to the registers value. -* @param pxSRadioInitStruct pointer to a SRadioInit structure that -* contains the configuration information for the analog radio part of SPIRIT. -* @retval None. -*/ -void SpiritRadioGetInfo(SRadioInit* pxSRadioInitStruct) -{ - uint8_t anaRadioRegArray[8], digRadioRegArray[4]; - BandSelect band; - int16_t xtalOffsetFactor; - - /* Get the RF board version */ - //SpiritVersion xSpiritVersion = SpiritGeneralGetSpiritVersion(); - - /* Reads the Analog Radio registers */ - SpiritSpiReadRegisters(SYNT3_BASE, 8, anaRadioRegArray); - - /* Reads the Digital Radio registers */ - g_xStatus = SpiritSpiReadRegisters(MOD1_BASE, 4, digRadioRegArray); - - /* Reads the operating band masking the Band selected field */ - if((anaRadioRegArray[3] & 0x07) == SYNT0_BS_6) - { - band = HIGH_BAND; - } - else if ((anaRadioRegArray[3] & 0x07) == SYNT0_BS_12) - { - band = MIDDLE_BAND; - } - else if ((anaRadioRegArray[3] & 0x07) == SYNT0_BS_16) - { - band = LOW_BAND; - } - else if ((anaRadioRegArray[3] & 0x07) == SYNT0_BS_32) - { - band = VERY_LOW_BAND; - } - else - { - /* if it is another value, set it to a valid one in order to avoid access violation */ - uint8_t tmp=(anaRadioRegArray[3]&0xF8)|SYNT0_BS_6; - SpiritSpiWriteRegisters(SYNT0_BASE,1,&tmp); - band = HIGH_BAND; - } - - /* Computes the synth word */ - uint32_t synthWord = (uint32_t)((((uint32_t)(anaRadioRegArray[0]&0x1F))<<21)+(((uint32_t)(anaRadioRegArray[1]))<<13)+\ - (((uint32_t)(anaRadioRegArray[2]))<<5)+(((uint32_t)(anaRadioRegArray[3]))>>3)); - - /* Calculates the frequency base */ - uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; - pxSRadioInitStruct->lFrequencyBase = (uint32_t)round(synthWord*(((double)s_lXtalFrequency)/(FBASE_DIVIDER*cRefDiv*s_vectcBHalfFactor[band]))); - - /* Calculates the Offset Factor */ - uint16_t xtalOffTemp = ((((uint16_t)anaRadioRegArray[6])<<8)+((uint16_t)anaRadioRegArray[7])); - - /* If a negative number then convert the 12 bit 2-complement in a 16 bit number */ - if(xtalOffTemp & 0x0800) - { - xtalOffTemp = xtalOffTemp | 0xF000; - } - else - { - xtalOffTemp = xtalOffTemp & 0x0FFF; - } - - xtalOffsetFactor = *((int16_t*)(&xtalOffTemp)); - - /* Calculates the frequency offset in ppm */ - pxSRadioInitStruct->nXtalOffsetPpm =(int16_t)((uint32_t)xtalOffsetFactor*s_lXtalFrequency*PPM_FACTOR)/((uint32_t)FBASE_DIVIDER*pxSRadioInitStruct->lFrequencyBase); - - /* Channel space */ - pxSRadioInitStruct->nChannelSpace = anaRadioRegArray[4]*(s_lXtalFrequency>>15); - - /* Channel number */ - pxSRadioInitStruct->cChannelNumber = SpiritRadioGetChannel(); - - /* Modulation select */ - pxSRadioInitStruct->xModulationSelect = (ModulationSelect)(digRadioRegArray[1] & 0x70); - - /* Reads the frequency deviation for mantissa and exponent */ - uint8_t FDevM = digRadioRegArray[2]&0x07; - uint8_t FDevE = (digRadioRegArray[2]&0xF0)>>4; - - /* Reads the channel filter register for mantissa and exponent */ - uint8_t bwM = (digRadioRegArray[3]&0xF0)>>4; - uint8_t bwE = digRadioRegArray[3]&0x0F; - - uint8_t cDivider = 0; - cDivider = SpiritRadioGetDigDiv(); - - /* Calculates the datarate */ - pxSRadioInitStruct->lDatarate = ((s_lXtalFrequency>>(5+cDivider))*(256+digRadioRegArray[0]))>>(23-(digRadioRegArray[1]&0x0F)); - - /* Calculates the frequency deviation */ - // (((s_lXtalFrequency>>6)*(8+FDevM))>>(12-FDevE+cCorrection)); - pxSRadioInitStruct->lFreqDev =(uint32_t)((float)s_lXtalFrequency/(((uint32_t)1)<<18)*(uint32_t)((8.0+FDevM)/2*(1<lBandwidth = (uint32_t)(100.0*s_vectnBandwidth26M[bwM+(bwE*9)]*((s_lXtalFrequency>>cDivider)/26e6)); - -} - - -/** -* @brief Sets the Xtal configuration in the ANA_FUNC_CONF0 register. -* @param xXtal one of the possible value of the enum type XtalFrequency. -* @arg XTAL_FLAG_24_MHz: in case of 24 MHz crystal -* @arg XTAL_FLAG_26_MHz: in case of 26 MHz crystal -* @retval None. -*/ -void SpiritRadioSetXtalFlag(XtalFlag xXtal) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_XTAL_FLAG(xXtal)); - - /* Reads the ANA_FUNC_CONF_0 register */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - if(xXtal == XTAL_FLAG_26_MHz) - { - tempRegValue|=SELECT_24_26_MHZ_MASK; - } - else - { - tempRegValue &= (~SELECT_24_26_MHZ_MASK); - } - - /* Sets the 24_26MHz_SELECT field in the ANA_FUNC_CONF_0 register */ - g_xStatus = SpiritSpiWriteRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the Xtal configuration in the ANA_FUNC_CONF0 register. -* @param None. -* @retval XtalFrequency Settled Xtal configuration. -*/ -XtalFlag SpiritRadioGetXtalFlag(void) -{ - uint8_t tempRegValue; - - /* Reads the Xtal configuration in the ANA_FUNC_CONF_0 register and return the value */ - g_xStatus = SpiritSpiReadRegisters(ANA_FUNC_CONF0_BASE, 1, &tempRegValue); - - return (XtalFlag)((tempRegValue & 0x40)>>6); - -} - - -/** -* @brief Returns the charge pump word for a given VCO frequency. -* @param lFc channel center frequency expressed in Hz. -* This parameter can be a value in one of the following ranges:
    -*
  • High_Band: from 779 MHz to 915 MHz
    • -*
  • Middle Band: from 387 MHz to 470 MHz
    • -*
  • Low Band: from 300 MHz to 348 MHz
    • -*
  • Very low Band: from 150 MHz to 174 MHz
-* @retval uint8_t Charge pump word. -*/ -uint8_t SpiritRadioSearchWCP(uint32_t lFc) -{ - int8_t i; - uint32_t vcofreq; - uint8_t BFactor; - - /* Check the channel center frequency is in one of the possible range */ - s_assert_param(IS_FREQUENCY_BAND(lFc)); - - /* Search the operating band */ - if(IS_FREQUENCY_BAND_HIGH(lFc)) - { - BFactor = HIGH_BAND_FACTOR; - } - else if(IS_FREQUENCY_BAND_MIDDLE(lFc)) - { - BFactor = MIDDLE_BAND_FACTOR; - } - else if(IS_FREQUENCY_BAND_LOW(lFc)) - { - BFactor = LOW_BAND_FACTOR; - } - else if(IS_FREQUENCY_BAND_VERY_LOW(lFc)) - { - BFactor = VERY_LOW_BAND_FACTOR; - } - - /* Calculates the VCO frequency VCOFreq = lFc*B */ - vcofreq = (lFc/1000000)*BFactor; - - /* Search in the vco frequency array the charge pump word */ - if(vcofreq>=s_vectnVCOFreq[15]) - { - i=15; - } - else - { - /* Search the value */ - for(i=0 ; i<15 && vcofreq>s_vectnVCOFreq[i] ; i++); - - /* Be sure that it is the best approssimation */ - if (i!=0 && s_vectnVCOFreq[i]-vcofreq>vcofreq-s_vectnVCOFreq[i-1]) - i--; - } - - /* Return index */ - return (i%8); - -} - -/** -* @brief Returns the synth word. -* @param None. -* @retval uint32_t Synth word. -*/ -uint32_t SpiritRadioGetSynthWord(void) -{ - uint8_t regArray[4]; - - /* Reads the SYNTH registers, build the synth word and return it */ - g_xStatus = SpiritSpiReadRegisters(SYNT3_BASE, 4, regArray); - return ((((uint32_t)(regArray[0]&0x1F))<<21)+(((uint32_t)(regArray[1]))<<13)+\ - (((uint32_t)(regArray[2]))<<5)+(((uint32_t)(regArray[3]))>>3)); - -} - - -/** -* @brief Sets the SYNTH registers. -* @param lSynthWord the synth word to write in the SYNTH[3:0] registers. -* @retval None. -*/ -void SpiritRadioSetSynthWord(uint32_t lSynthWord) -{ - uint8_t tempArray[4]; - uint8_t tempRegValue; - - /* Reads the SYNT0 register */ - g_xStatus = SpiritSpiReadRegisters(SYNT0_BASE, 1, &tempRegValue); - - /* Mask the Band selected field */ - tempRegValue &= 0x07; - - /* Build the array for SYNTH registers */ - tempArray[0] = (uint8_t)((lSynthWord>>21)&(0x0000001F)); - tempArray[1] = (uint8_t)((lSynthWord>>13)&(0x000000FF)); - tempArray[2] = (uint8_t)((lSynthWord>>5)&(0x000000FF)); - tempArray[3] = (uint8_t)(((lSynthWord&0x0000001F)<<3)| tempRegValue); - - /* Writes the synth word in the SYNTH registers */ - g_xStatus = SpiritSpiWriteRegisters(SYNT3_BASE, 4, tempArray); - -} - - -/** -* @brief Sets the operating band. -* @param xBand the band to set. -* This parameter can be one of following parameters: -* @arg HIGH_BAND High_Band selected: from 779 MHz to 915 MHz -* @arg MIDDLE_BAND: Middle Band selected: from 387 MHz to 470 MHz -* @arg LOW_BAND: Low Band selected: from 300 MHz to 348 MHz -* @arg VERY_LOW_BAND: Very low Band selected: from 150 MHz to 174 MHz -* @retval None. -*/ -void SpiritRadioSetBand(BandSelect xBand) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_BAND_SELECTED(xBand)); - - /* Reads the SYNT0 register*/ - g_xStatus = SpiritSpiReadRegisters(SYNT0_BASE, 1, &tempRegValue); - - /* Mask the SYNTH[4;0] field and write the BS value */ - tempRegValue &= 0xF8; - tempRegValue |= s_vectcBandRegValue[xBand]; - - /* Configures the SYNT0 register setting the operating band */ - g_xStatus = SpiritSpiWriteRegisters(SYNT0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the operating band. -* @param None. -* @retval BandSelect Settled band. -* This returned value can be one of the following parameters: -* @arg HIGH_BAND High_Band selected: from 779 MHz to 915 MHz -* @arg MIDDLE_BAND: Middle Band selected: from 387 MHz to 470 MHz -* @arg LOW_BAND: Low Band selected: from 300 MHz to 348 MHz -* @arg VERY_LOW_BAND: Very low Band selected: from 150 MHz to 174 MHz -*/ -BandSelect SpiritRadioGetBand(void) -{ - uint8_t tempRegValue; - - /* Reads the SYNT0 register */ - g_xStatus = SpiritSpiReadRegisters(SYNT0_BASE, 1, &tempRegValue); - - /* Mask the Band selected field */ - if((tempRegValue & 0x07) == SYNT0_BS_6) - { - return HIGH_BAND; - } - else if ((tempRegValue & 0x07) == SYNT0_BS_12) - { - return MIDDLE_BAND; - } - else if ((tempRegValue & 0x07) == SYNT0_BS_16) - { - return LOW_BAND; - } - else - { - return VERY_LOW_BAND; - } - -} - - -/** -* @brief Sets the channel number. -* @param cChannel the channel number. -* @retval None. -*/ -void SpiritRadioSetChannel(uint8_t cChannel) -{ - /* Writes the CHNUM register */ - g_xStatus = SpiritSpiWriteRegisters(CHNUM_BASE, 1, &cChannel); - -} - - -/** -* @brief Returns the actual channel number. -* @param None. -* @retval uint8_t Actual channel number. -*/ -uint8_t SpiritRadioGetChannel(void) -{ - uint8_t tempRegValue; - - /* Reads the CHNUM register and return the value */ - g_xStatus = SpiritSpiReadRegisters(CHNUM_BASE, 1, &tempRegValue); - - return tempRegValue; - -} - - -/** -* @brief Sets the channel space factor in channel space register. -* The channel spacing step is computed as F_Xo/32768. -* @param fChannelSpace the channel space expressed in Hz. -* @retval None. -*/ -void SpiritRadioSetChannelSpace(uint32_t fChannelSpace) -{ - uint8_t cChannelSpaceFactor; - - /* Round to the nearest integer */ - cChannelSpaceFactor = ((uint32_t)fChannelSpace*CHSPACE_DIVIDER)/s_lXtalFrequency; - - /* Write value into the register */ - g_xStatus = SpiritSpiWriteRegisters(CHSPACE_BASE, 1, &cChannelSpaceFactor); - -} - - -/** -* @brief Returns the channel space register. -* @param None. -* @retval uint32_t Channel space. The channel space is: CS = channel_space_factor x XtalFrequency/2^15 -* where channel_space_factor is the CHSPACE register value. -*/ -uint32_t SpiritRadioGetChannelSpace(void) -{ - uint8_t channelSpaceFactor; - - /* Reads the CHSPACE register, calculate the channel space and return it */ - g_xStatus = SpiritSpiReadRegisters(CHSPACE_BASE, 1, &channelSpaceFactor); - - /* Compute the Hertz value and return it */ - return ((channelSpaceFactor*s_lXtalFrequency)/CHSPACE_DIVIDER); - -} - - -/** -* @brief Sets the FC OFFSET register starting from xtal ppm value. -* @param nXtalPpm the xtal offset expressed in ppm. -* @retval None. -*/ -void SpiritRadioSetFrequencyOffsetPpm(int16_t nXtalPpm) -{ - uint8_t tempArray[2]; - int16_t xtalOffsetFactor; - uint32_t synthWord, fBase; - int32_t FOffsetTmp; - BandSelect band; - - /* Reads the synth word */ - synthWord = SpiritRadioGetSynthWord(); - - /* Reads the operating band */ - band = SpiritRadioGetBand(); - - /* Calculates the frequency base */ - uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; - fBase = synthWord*(s_lXtalFrequency/(s_vectcBHalfFactor[band]*cRefDiv)/FBASE_DIVIDER); - - /* Calculates the offset respect to RF frequency and according to xtal_ppm parameter */ - FOffsetTmp = (int32_t)(((float)nXtalPpm*fBase)/PPM_FACTOR); - - /* Check the Offset is in the correct range */ - s_assert_param(IS_FREQUENCY_OFFSET(FOffsetTmp,s_lXtalFrequency)); - - /* Calculates the FC_OFFSET value to write in the corresponding register */ - xtalOffsetFactor = (int16_t)(((float)FOffsetTmp*FBASE_DIVIDER)/s_lXtalFrequency); - - /* Build the array related to the FC_OFFSET_1 and FC_OFFSET_0 register */ - tempArray[0]=(uint8_t)((((uint16_t)xtalOffsetFactor)>>8)&0x0F); - tempArray[1]=(uint8_t)(xtalOffsetFactor); - - /* Writes the FC_OFFSET registers */ - g_xStatus = SpiritSpiWriteRegisters(FC_OFFSET1_BASE, 2, tempArray); - -} - - -/** -* @brief Sets the FC OFFSET register starting from frequency offset expressed in Hz. -* @param lFOffset frequency offset expressed in Hz as signed word. -* @retval None. -*/ -void SpiritRadioSetFrequencyOffset(int32_t lFOffset) -{ - uint8_t tempArray[2]; - int16_t offset; - - /* Check that the Offset is in the correct range */ - s_assert_param(IS_FREQUENCY_OFFSET(lFOffset,s_lXtalFrequency)); - - /* Calculates the offset value to write in the FC_OFFSET register */ - offset = (int16_t)(((float)lFOffset*FBASE_DIVIDER)/s_lXtalFrequency); - - /* Build the array related to the FC_OFFSET_1 and FC_OFFSET_0 register */ - tempArray[0]=(uint8_t)((((uint16_t)offset)>>8)&0x0F); - tempArray[1]=(uint8_t)(offset); - - /* Writes the FC_OFFSET registers */ - g_xStatus = SpiritSpiWriteRegisters(FC_OFFSET1_BASE, 2, tempArray); - -} - - -/** -* @brief Returns the actual frequency offset. -* @param None. -* @retval int32_t Frequency offset expressed in Hz as signed word. -*/ -int32_t SpiritRadioGetFrequencyOffset(void) -{ - uint8_t tempArray[2]; - int16_t xtalOffsetFactor; - - /* Reads the FC_OFFSET registers */ - g_xStatus = SpiritSpiReadRegisters(FC_OFFSET1_BASE, 2, tempArray); - - /* Calculates the Offset Factor */ - uint16_t xtalOffTemp = ((((uint16_t)tempArray[0])<<8)+((uint16_t)tempArray[1])); - - if(xtalOffTemp & 0x0800) - { - xtalOffTemp = xtalOffTemp | 0xF000; - } - else - { - xtalOffTemp = xtalOffTemp & 0x0FFF; - } - - xtalOffsetFactor = *((int16_t*)(&xtalOffTemp)); - - /* Calculates the frequency offset and return it */ - return ((int32_t)(xtalOffsetFactor*s_lXtalFrequency)/FBASE_DIVIDER); - -} - - - -/** -* @brief Sets the Synth word and the Band Select register according to desired base carrier frequency. -* In this API the Xtal configuration is read out from -* the corresponding register. The user shall fix it before call this API. -* @param lFBase the base carrier frequency expressed in Hz as unsigned word. -* @retval Error code: 0=no error, 1=error during calibration of VCO. -*/ -uint8_t SpiritRadioSetFrequencyBase(uint32_t lFBase) -{ - uint32_t synthWord, Fc; - uint8_t band, anaRadioRegArray[4], wcp; - - /* Check the parameter */ - s_assert_param(IS_FREQUENCY_BAND(lFBase)); - - /* Search the operating band */ - if(IS_FREQUENCY_BAND_HIGH(lFBase)) - { - band = HIGH_BAND; - } - else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) - { - band = MIDDLE_BAND; - } - else if(IS_FREQUENCY_BAND_LOW(lFBase)) - { - band = LOW_BAND; - } - else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) - { - band = VERY_LOW_BAND; - } - - int32_t FOffset = SpiritRadioGetFrequencyOffset(); - uint32_t lChannelSpace = SpiritRadioGetChannelSpace(); - uint8_t cChannelNum = SpiritRadioGetChannel(); - - /* Calculates the channel center frequency */ - Fc = lFBase + FOffset + lChannelSpace*cChannelNum; - - /* Reads the reference divider */ - uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv()+1; - - /* Selects the VCO */ - switch(band) - { - case VERY_LOW_BAND: - if(Fc<161281250) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - break; - - case LOW_BAND: - if(Fc<322562500) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - break; - - case MIDDLE_BAND: - if(Fc<430083334) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - break; - - case HIGH_BAND: - if(Fc<860166667) - { - SpiritCalibrationSelectVco(VCO_L); - } - else - { - SpiritCalibrationSelectVco(VCO_H); - } - } - - /* Search the VCO charge pump word and set the corresponding register */ - wcp = SpiritRadioSearchWCP(Fc); - - synthWord = (uint32_t)(lFBase*s_vectcBHalfFactor[band]*(((double)(FBASE_DIVIDER*cRefDiv))/s_lXtalFrequency)); - - /* Build the array of registers values for the analog part */ - anaRadioRegArray[0] = (uint8_t)(((synthWord>>21)&(0x0000001F))|(wcp<<5)); - anaRadioRegArray[1] = (uint8_t)((synthWord>>13)&(0x000000FF)); - anaRadioRegArray[2] = (uint8_t)((synthWord>>5)&(0x000000FF)); - anaRadioRegArray[3] = (uint8_t)(((synthWord&0x0000001F)<<3)| s_vectcBandRegValue[band]); - - /* Configures the needed Analog Radio registers */ - g_xStatus = SpiritSpiWriteRegisters(SYNT3_BASE, 4, anaRadioRegArray); - - if(xDoVcoCalibrationWA==S_ENABLE) - return SpiritManagementWaVcoCalibration(); - - return 0; -} - -/** -* @brief To say to the set frequency base if do or not the VCO calibration WA. -* @param S_ENABLE or S_DISABLE the WA procedure. -* @retval None. -*/ -void SpiritRadioVcoCalibrationWAFB(SpiritFunctionalState xNewstate) -{ - xDoVcoCalibrationWA=xNewstate; -} - -/** -* @brief Returns the base carrier frequency. -* @param None. -* @retval uint32_t Base carrier frequency expressed in Hz as unsigned word. -*/ -uint32_t SpiritRadioGetFrequencyBase(void) -{ - uint32_t synthWord; - BandSelect band; - - /* Reads the synth word */ - synthWord = SpiritRadioGetSynthWord(); - - /* Reads the operating band */ - band = SpiritRadioGetBand(); - - uint8_t cRefDiv = (uint8_t)SpiritRadioGetRefDiv() + 1; - - /* Calculates the frequency base and return it */ - return (uint32_t)round(synthWord*(((double)s_lXtalFrequency)/(FBASE_DIVIDER*cRefDiv*s_vectcBHalfFactor[band]))); -} - - -/** -* @brief Returns the actual channel center frequency. -* @param None. -* @retval uint32_t Actual channel center frequency expressed in Hz. -*/ -uint32_t SpiritRadioGetCenterFrequency(void) -{ - int32_t offset; - uint8_t channel; - uint32_t fBase; - uint32_t channelSpace; - - /* Reads the frequency base */ - fBase = SpiritRadioGetFrequencyBase(); - - /* Reads the frequency offset */ - offset = SpiritRadioGetFrequencyOffset(); - - /* Reads the channel space */ - channelSpace = SpiritRadioGetChannelSpace(); - - /* Reads the channel number */ - channel = SpiritRadioGetChannel(); - - /* Calculates the channel center frequency and return it */ - return (uint32_t)(fBase + offset + (uint32_t)(channelSpace*channel)); - -} - - -/** -* @brief Returns the mantissa and exponent, whose value used in the datarate formula -* will give the datarate value closer to the given datarate. -* @param fDatarate datarate expressed in bps. This parameter ranging between 100 and 500000. -* @param pcM pointer to the returned mantissa value. -* @param pcE pointer to the returned exponent value. -* @retval None. -*/ -void SpiritRadioSearchDatarateME(uint32_t lDatarate, uint8_t* pcM, uint8_t* pcE) -{ - volatile SpiritBool find = S_FALSE; - int8_t i=15; - uint8_t cMantissaTmp; - uint8_t cDivider = 0; - - /* Check the parameters */ - s_assert_param(IS_DATARATE(lDatarate)); - - cDivider = (uint8_t)SpiritRadioGetDigDiv(); - - /* Search in the datarate array the exponent value */ - while(!find && i>=0) - { - if(lDatarate>=(s_lXtalFrequency>>(20-i+cDivider))) - { - find = S_TRUE; - } - else - { - i--; - } - } - i<0 ? i=0 : i; - *pcE = i; - - /* Calculates the mantissa value according to the datarate formula */ - cMantissaTmp = (lDatarate*((uint32_t)1<<(23-i)))/(s_lXtalFrequency>>(5+cDivider))-256; - - /* Finds the mantissa value with less approximation */ - int16_t mantissaCalculation[3]; - for(uint8_t j=0;j<3;j++) - { - if((cMantissaTmp+j-1)) - { - mantissaCalculation[j]=lDatarate-(((256+cMantissaTmp+j-1)*(s_lXtalFrequency>>(5+cDivider)))>>(23-i)); - } - else - { - mantissaCalculation[j]=0x7FFF; - } - } - uint16_t mantissaCalculationDelta = 0xFFFF; - for(uint8_t j=0;j<3;j++) - { - if(S_ABS(mantissaCalculation[j])=0) || ((i_tmp+j-1)<=89)) - { - chfltCalculation[j] = lBandwidth - (uint32_t)((s_vectnBandwidth26M[i_tmp+j-1]*lChfltFactor)/2600); - } - else - { - chfltCalculation[j] = 0x7FFF; - } - } - uint16_t chfltDelta = 0xFFFF; - - for(uint8_t j=0;j<3;j++) - { - if(S_ABS(chfltCalculation[j])>(5+cDivider))*(256+tempRegValue[0]))>>(23-(tempRegValue[1]&0x0F))); -} - - -/** -* @brief Sets the frequency deviation. -* @param fFDev frequency deviation expressed in Hz. Be sure that this value -* is in the correct range [F_Xo*8/2^18, F_Xo*7680/2^18] Hz. -* @retval None. -*/ -void SpiritRadioSetFrequencyDev(uint32_t lFDev) -{ - uint8_t FDevM, FDevE, tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_F_DEV(lFDev, s_lXtalFrequency)); - - /* Calculates the frequency deviation mantissa and exponent */ - SpiritRadioSearchFreqDevME(lFDev, &FDevM, &FDevE); - - /* Reads the FDEV0 register */ - SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); - - /* Mask the other fields and set the frequency deviation mantissa and exponent */ - tempRegValue &= 0x08; - tempRegValue |= ((FDevE<<4)|(FDevM)); - - /* Writes the Frequency deviation register */ - g_xStatus = SpiritSpiWriteRegisters(FDEV0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the frequency deviation. -* @param None. -* @retval uint32_t Frequency deviation value expressed in Hz. -* This value will be in the range [F_Xo*8/2^18, F_Xo*7680/2^18] Hz. -*/ -uint32_t SpiritRadioGetFrequencyDev(void) -{ - uint8_t tempRegValue, FDevM, FDevE; - - - /* Reads the frequency deviation register for mantissa and exponent */ - g_xStatus = SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); - FDevM = tempRegValue&0x07; - FDevE = (tempRegValue&0xF0)>>4; - - /* Calculates the frequency deviation and return it */ - //return (((s_lXtalFrequency>>6)*(8+FDevM))>>(13-FDevE)); - - return (uint32_t)((float)s_lXtalFrequency/(((uint32_t)1)<<18)*(uint32_t)((8.0+FDevM)/2*(1<>4; - bwE = tempRegValue&0x0F; - - /* Reads the channel filter bandwidth from the look-up table and return it */ - return (uint32_t)(100.0*s_vectnBandwidth26M[bwM+(bwE*9)]*s_lXtalFrequency/26e6); - -} - - -/** -* @brief Sets the modulation type. -* @param xModulation modulation to set. -* This parameter shall be of type @ref ModulationSelect . -* @retval None. -*/ -void SpiritRadioSetModulation(ModulationSelect xModulation) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_MODULATION_SELECTED(xModulation)); - - /* Reads the modulation register */ - SpiritSpiReadRegisters(MOD0_BASE, 1, &tempRegValue); - - /* Mask the other fields and set the modulation type */ - tempRegValue &=0x8F; - tempRegValue |= xModulation; - - /* Writes the modulation register */ - g_xStatus = SpiritSpiWriteRegisters(MOD0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the modulation type used. -* @param None. -* @retval ModulationSelect Settled modulation type. -*/ -ModulationSelect SpiritRadioGetModulation(void) -{ - uint8_t tempRegValue; - - /* Reads the modulation register MOD0*/ - g_xStatus = SpiritSpiReadRegisters(MOD0_BASE, 1, &tempRegValue); - - /* Return the modulation type */ - return (ModulationSelect)(tempRegValue&0x70); - -} - - -/** -* @brief Enables or Disables the Continuous Wave transmit mode. -* @param xNewState new state for power ramping. -* This parameter can be: S_ENABLE or S_DISABLE . -* @retval None. -*/ -void SpiritRadioCWTransmitMode(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the modulation register MOD0 and mask the CW field */ - SpiritSpiReadRegisters(MOD0_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |=MOD0_CW; - } - else - { - tempRegValue &= (~MOD0_CW); - } - - /* Writes the new value in the MOD0 register */ - g_xStatus = SpiritSpiWriteRegisters(MOD0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Sets the OOK Peak Decay. -* @param xOokDecay Peak decay control for OOK. -* This parameter shall be of type @ref OokPeakDecay . -* @retval None. -*/ -void SpiritRadioSetOokPeakDecay(OokPeakDecay xOokDecay) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_OOK_PEAK_DECAY(xOokDecay)); - - /* Reads the RSSI_FLT register */ - SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - - /* Mask the other fields and set OOK Peak Decay */ - tempRegValue &= 0xFC; - tempRegValue |= xOokDecay; - - /* Writes the RSSI_FLT register to set the new OOK peak dacay value */ - g_xStatus = SpiritSpiWriteRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the OOK Peak Decay. -* @param None -* @retval OokPeakDecay Ook peak decay value. -*/ -OokPeakDecay SpiritRadioGetOokPeakDecay(void) -{ - uint8_t tempRegValue; - - /* Reads the OOK peak decay register RSSI_FLT_BASE*/ - g_xStatus = SpiritSpiReadRegisters(RSSI_FLT_BASE, 1, &tempRegValue); - - /* Returns the OOK peak decay */ - return (OokPeakDecay) (tempRegValue & 0x03); - -} - -/** -* @brief Returns the PA register value that corresponds to the passed dBm power. -* @param lFbase Frequency base expressed in Hz. -* @param fPowerdBm Desired power in dBm. -* @retval Register value as byte. -* @note The power interpolation curves used by this function have been extracted -* by measurements done on the divisional evaluation boards. -*/ -uint8_t SpiritRadioGetdBm2Reg(uint32_t lFBase, float fPowerdBm) -{ - uint8_t i; - uint8_t j=0; - float fReg; - - if(IS_FREQUENCY_BAND_HIGH(lFBase)) - { - i=0; - if(lFBase<900000000) i=1;// 868 - } - else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) - { - i=2; - } - else if(IS_FREQUENCY_BAND_LOW(lFBase)) - { - i=3; - } - else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) - { - i=4; - } - - j=1; - if(fPowerdBm>0 && 13.0/fPowerFactors[i][2]-fPowerFactors[i][3]/fPowerFactors[i][2]fPowerdBm) - j=2; - - fReg=fPowerFactors[i][2*j]*fPowerdBm+fPowerFactors[i][2*j+1]; - - if(fReg<1) - fReg=1; - else if(fReg>90) - fReg=90; - - return ((uint8_t)fReg); -} - - -/** -* @brief Returns the dBm power that corresponds to the value of PA register. -* @param lFbase Frequency base expressed in Hz. -* @param cPowerReg Register value of the PA. -* @retval Power in dBm as float. -* @note The power interpolation curves used by this function have been extracted -* by measurements done on the divisional evaluation boards. -*/ -float SpiritRadioGetReg2dBm(uint32_t lFBase, uint8_t cPowerReg) -{ - uint8_t i; - uint8_t j=0; - float fPower; - - if(cPowerReg==0 || cPowerReg>90) - return (-130.0); - - if(IS_FREQUENCY_BAND_HIGH(lFBase)) - { - i=0; - if(lFBase<900000000) i=1;// 868 - } - else if(IS_FREQUENCY_BAND_MIDDLE(lFBase)) - { - i=2; - } - else if(IS_FREQUENCY_BAND_LOW(lFBase)) - { - i=3; - } - else if(IS_FREQUENCY_BAND_VERY_LOW(lFBase)) - { - i=4; - } - - j=1; - if(cPowerReg<13) j=0; - else if(cPowerReg>40) j=2; - - fPower=(((float)cPowerReg)/fPowerFactors[i][2*j]-fPowerFactors[i][2*j+1]/fPowerFactors[i][2*j]); - - return fPower; -} - -/** -* @brief Configures the Power Amplifier Table and registers with value expressed in dBm. -* @param cPALevelMaxIndex number of levels to set. This parameter shall be in the range [0:7]. -* @param cWidth step width expressed in terms of bit period units Tb/8. -* This parameter shall be in the range [1:4]. -* @param xCLoad one of the possible value of the enum type PALoadCapacitor. -* @arg LOAD_0_PF No additional PA load capacitor -* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor -* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor -* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor -* @param pfPAtabledBm pointer to an array of PA values in dbm between [-PA_LOWER_LIMIT: PA_UPPER_LIMIT] dbm. -* The first element shall be the lower level (PA_LEVEL[0]) value and the last element -* the higher level one (PA_LEVEL[paLevelMaxIndex]). -* @retval None. -*/ -void SpiritRadioSetPATabledBm(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, float* pfPAtabledBm) -{ - uint8_t palevel[9], address, paLevelValue; - uint32_t lFBase=SpiritRadioGetFrequencyBase(); - - /* Check the parameters */ - s_assert_param(IS_PA_MAX_INDEX(cPALevelMaxIndex)); - s_assert_param(IS_PA_STEP_WIDTH(cWidth)); - s_assert_param(IS_PA_LOAD_CAP(xCLoad)); - - /* Check the PA level in dBm is in the range and calculate the PA_LEVEL value - to write in the corresponding register using the linearization formula */ - for(int i=0; i<=cPALevelMaxIndex; i++) - { - s_assert_param(IS_PAPOWER_DBM(*pfPAtabledBm)); - paLevelValue=SpiritRadioGetdBm2Reg(lFBase,(*pfPAtabledBm)); - palevel[cPALevelMaxIndex-i]=paLevelValue; - pfPAtabledBm++; - } - - /* Sets the PA_POWER[0] register */ - palevel[cPALevelMaxIndex+1]=xCLoad|(cWidth-1)<<3|cPALevelMaxIndex; - - /* Sets the base address */ - address=PA_POWER8_BASE+7-cPALevelMaxIndex; - - /* Configures the PA_POWER registers */ - g_xStatus = SpiritSpiWriteRegisters(address, cPALevelMaxIndex+2, palevel); - -} - - -/** -* @brief Returns the Power Amplifier Table and registers, returning values in dBm. -* @param pcPALevelMaxIndex pointer to the number of levels settled. -* This parameter will be in the range [0:7]. -* @param pfPAtabledBm pointer to an array of 8 elements containing the PA value in dbm. -* The first element will be the PA_LEVEL_0 and the last element -* will be PA_LEVEL_7. Any value higher than PA_UPPER_LIMIT implies no output -* power (output stage is in high impedance). -* @retval None. -*/ -void SpiritRadioGetPATabledBm(uint8_t* pcPALevelMaxIndex, float* pfPAtabledBm) -{ - uint8_t palevelvect[9]; - uint32_t lFBase=SpiritRadioGetFrequencyBase(); - - /* Reads the PA_LEVEL_x registers and the PA_POWER_0 register */ - g_xStatus = SpiritSpiReadRegisters(PA_POWER8_BASE, 9, palevelvect); - - /* Fill the PAtable */ - for(int i=7; i>=0; i--) - { - (*pfPAtabledBm)=SpiritRadioGetReg2dBm(lFBase,palevelvect[i]); - pfPAtabledBm++; - } - - /* Return the settled index */ - *pcPALevelMaxIndex = palevelvect[8]&0x07; - -} - - - - - - -/** -* @brief Sets a specific PA_LEVEL register, with a value given in dBm. -* @param cIndex PA_LEVEL to set. This parameter shall be in the range [0:7]. -* @param fPowerdBm PA value to write expressed in dBm . Be sure that this values is in the -* correct range [-PA_LOWER_LIMIT: PA_UPPER_LIMIT] dBm. -* @retval None. -* @note This function makes use of the @ref SpiritRadioGetdBm2Reg fcn to interpolate the -* power value. -*/ -void SpiritRadioSetPALeveldBm(uint8_t cIndex, float fPowerdBm) -{ - uint8_t address, paLevelValue; - - /* Check the parameters */ - s_assert_param(IS_PA_MAX_INDEX(cIndex)); - s_assert_param(IS_PAPOWER_DBM(fPowerdBm)); - - /* interpolate the power level */ - paLevelValue=SpiritRadioGetdBm2Reg(SpiritRadioGetFrequencyBase(),fPowerdBm); - - /* Sets the base address */ - address=PA_POWER8_BASE+7-cIndex; - - /* Configures the PA_LEVEL register */ - g_xStatus = SpiritSpiWriteRegisters(address, 1, &paLevelValue); - -} - - -/** -* @brief Returns a specific PA_LEVEL register, returning a value in dBm. -* @param cIndex PA_LEVEL to read. This parameter shall be in the range [0:7] -* @retval float Settled power level expressed in dBm. A value -* higher than PA_UPPER_LIMIT dBm implies no output power -* (output stage is in high impedance). -* @note This function makes use of the @ref SpiritRadioGetReg2dBm fcn to interpolate the -* power value. -*/ -float SpiritRadioGetPALeveldBm(uint8_t cIndex) -{ - uint8_t address, paLevelValue; - - /* Check the parameters */ - s_assert_param(IS_PA_MAX_INDEX(cIndex)); - - /* Sets the base address */ - address=PA_POWER8_BASE+7-cIndex; - - /* Reads the PA_LEVEL[cIndex] register */ - g_xStatus = SpiritSpiReadRegisters(address, 1, &paLevelValue); - - return SpiritRadioGetReg2dBm(SpiritRadioGetFrequencyBase(),paLevelValue); -} - - -/** -* @brief Configures the Power Amplifier Table and registers. -* @param cPALevelMaxIndex number of levels to set. This parameter shall be in the range [0:7]. -* @param cWidth step width expressed in terms of bit period units Tb/8. -* This parameter shall be in the range [1:4]. -* @param xCLoad one of the possible value of the enum type PALoadCapacitor. -* @arg LOAD_0_PF No additional PA load capacitor -* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor -* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor -* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor -* @param pcPAtable pointer to an array of PA values in the range [0: 90], where 0 implies no -* output power, 1 will be the maximum level and 90 the minimum one -* The first element shall be the lower level (PA_LEVEL[0]) value and the last element -* the higher level one (PA_LEVEL[paLevelMaxIndex]). -* @retval None. -*/ -void SpiritRadioSetPATable(uint8_t cPALevelMaxIndex, uint8_t cWidth, PALoadCapacitor xCLoad, uint8_t* pcPAtable) -{ - uint8_t palevel[9], address; - - /* Check the parameters */ - s_assert_param(IS_PA_MAX_INDEX(cPALevelMaxIndex)); - s_assert_param(IS_PA_STEP_WIDTH(cWidth)); - s_assert_param(IS_PA_LOAD_CAP(xCLoad)); - - /* Check the PA levels are in the range */ - for(int i=0; i<=cPALevelMaxIndex; i++) - { - s_assert_param(IS_PAPOWER(*pcPAtable)); - palevel[cPALevelMaxIndex-i]=*pcPAtable; - pcPAtable++; - } - - /* Sets the PA_POWER[0] register */ - palevel[cPALevelMaxIndex+1]=xCLoad|((cWidth-1)<<3)|cPALevelMaxIndex; - - /* Sets the base address */ - address=PA_POWER8_BASE+7-cPALevelMaxIndex; - - /* Configures the PA_POWER registers */ - g_xStatus = SpiritSpiWriteRegisters(address, cPALevelMaxIndex+2, palevel); - -} - - -/** -* @brief Returns the Power Amplifier Table and registers. -* @param pcPALevelMaxIndex pointer to the number of levels settled. -* This parameter shall be in the range [0:7]. -* @param pcPAtable pointer to an array of 8 elements containing the PA value. -* The first element will be the PA_LEVEL_0 and the last element -* will be PA_LEVEL_7. Any value equals to 0 implies that level has -* no output power (output stage is in high impedance). -* @retval None -*/ -void SpiritRadioGetPATable(uint8_t* pcPALevelMaxIndex, uint8_t* pcPAtable) -{ - uint8_t palevelvect[9]; - - /* Reads the PA_LEVEL_x registers and the PA_POWER_0 register */ - g_xStatus = SpiritSpiReadRegisters(PA_POWER8_BASE, 9, palevelvect); - - /* Fill the PAtable */ - for(int i=7; i>=0; i--) - { - *pcPAtable = palevelvect[i]; - pcPAtable++; - } - - /* Return the settled index */ - *pcPALevelMaxIndex = palevelvect[8]&0x07; - -} - - -/** -* @brief Sets a specific PA_LEVEL register. -* @param cIndex PA_LEVEL to set. This parameter shall be in the range [0:7]. -* @param cPower PA value to write in the register. Be sure that this values is in the -* correct range [0 : 90]. -* @retval None. -*/ -void SpiritRadioSetPALevel(uint8_t cIndex, uint8_t cPower) -{ - uint8_t address; - - /* Check the parameters */ - s_assert_param(IS_PA_MAX_INDEX(cIndex)); - s_assert_param(IS_PAPOWER(cPower)); - - /* Sets the base address */ - address=PA_POWER8_BASE+7-cIndex; - - /* Configures the PA_LEVEL register */ - g_xStatus = SpiritSpiWriteRegisters(address, 1, &cPower); - -} - - -/** -* @brief Returns a specific PA_LEVEL register. -* @param cIndex PA_LEVEL to read. This parameter shall be in the range [0:7]. -* @retval uint8_t PA_LEVEL value. A value equal to zero -* implies no output power (output stage is in high impedance). -*/ -uint8_t SpiritRadioGetPALevel(uint8_t cIndex) -{ - uint8_t address, tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PA_MAX_INDEX(cIndex)); - - /* Sets the base address */ - address=PA_POWER8_BASE+7-cIndex; - - /* Reads the PA_LEVEL[cIndex] register and return the value */ - g_xStatus = SpiritSpiReadRegisters(address, 1, &tempRegValue); - return tempRegValue; - -} - - -/** -* @brief Sets the output stage additional load capacitor bank. -* @param xCLoad one of the possible value of the enum type PALoadCapacitor. -* @arg LOAD_0_PF No additional PA load capacitor -* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor -* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor -* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor -* @retval None. -*/ -void SpiritRadioSetPACwc(PALoadCapacitor xCLoad) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PA_LOAD_CAP(xCLoad)); - - /* Reads the PA_POWER_0 register */ - SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - - /* Mask the CWC[1:0] field and write the new value */ - tempRegValue &= 0x3F; - tempRegValue |= xCLoad; - - /* Configures the PA_POWER_0 register */ - g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the output stage additional load capacitor bank. -* @param None. -* @retval PALoadCapacitor Output stage additional load capacitor bank. -* This parameter can be: -* @arg LOAD_0_PF No additional PA load capacitor -* @arg LOAD_1_2_PF 1.2pF additional PA load capacitor -* @arg LOAD_2_4_PF 2.4pF additional PA load capacitor -* @arg LOAD_3_6_PF 3.6pF additional PA load capacitor -*/ -PALoadCapacitor SpiritRadioGetPACwc(void) -{ - uint8_t tempRegValue; - - /* Reads the PA_POWER_0 register */ - g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - - /* Mask the CWC[1:0] field and return the value*/ - return (PALoadCapacitor)(tempRegValue & 0xC0); - -} - - -/** -* @brief Sets a specific PA_LEVEL_MAX_INDEX. -* @param cIndex PA_LEVEL_MAX_INDEX to set. This parameter shall be in the range [0:7]. -* @retval None -*/ -void SpiritRadioSetPALevelMaxIndex(uint8_t cIndex) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PA_MAX_INDEX(cIndex)); - - /* Reads the PA_POWER_0 register */ - SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - - /* Mask the PA_LEVEL_MAX_INDEX[1:0] field and write the new value */ - tempRegValue &= 0xF8; - tempRegValue |= cIndex; - - /* Configures the PA_POWER_0 register */ - g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the actual PA_LEVEL_MAX_INDEX. -* @param None. -* @retval uint8_t Actual PA_LEVEL_MAX_INDEX. This parameter will be in the range [0:7]. -*/ -uint8_t SpiritRadioGetPALevelMaxIndex(void) -{ - uint8_t tempRegValue; - - /* Reads the PA_POWER_0 register */ - g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - - /* Mask the PA_LEVEL_MAX_INDEX[1:0] field and return the value */ - return (tempRegValue & 0x07); - -} - - -/** -* @brief Sets a specific PA_RAMP_STEP_WIDTH. -* @param cWidth step width expressed in terms of bit period units Tb/8. -* This parameter shall be in the range [1:4]. -* @retval None. -*/ -void SpiritRadioSetPAStepWidth(uint8_t cWidth) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_PA_STEP_WIDTH(cWidth)); - - /* Reads the PA_POWER_0 register */ - SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - - /* Mask the PA_RAMP_STEP_WIDTH[1:0] field and write the new value */ - tempRegValue &= 0xE7; - tempRegValue |= (cWidth-1)<<3; - - /* Configures the PA_POWER_0 register */ - g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the actual PA_RAMP_STEP_WIDTH. -* @param None. -* @retval uint8_t Step width value expressed in terms of bit period units Tb/8. -* This parameter will be in the range [1:4]. -*/ -uint8_t SpiritRadioGetPAStepWidth(void) -{ - uint8_t tempRegValue; - - /* Reads the PA_POWER_0 register */ - g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - - /* Mask the PA_RAMP_STEP_WIDTH[1:0] field and return the value */ - tempRegValue &= 0x18; - return ((tempRegValue>>3)+1); - -} - - -/** -* @brief Enables or Disables the Power Ramping. -* @param xNewState new state for power ramping. -* This parameter can be: S_ENABLE or S_DISABLE. -* @retval None. -*/ -void SpiritRadioPARamping(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PA_POWER_0 register and configure the PA_RAMP_ENABLE field */ - SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= PA_POWER0_PA_RAMP_MASK; - } - else - { - tempRegValue &= (~PA_POWER0_PA_RAMP_MASK); - } - - /* Sets the PA_POWER_0 register */ - g_xStatus = SpiritSpiWriteRegisters(PA_POWER0_BASE, 1, &tempRegValue); - -} - -/** -* @brief Returns the Power Ramping enable bit. -* @param xNewState new state for power ramping. -* This parameter can be: S_ENABLE or S_DISABLE. -* @retval None. -*/ -SpiritFunctionalState SpiritRadioGetPARamping(void) -{ - uint8_t tempRegValue; - - /* Reads the PA_POWER_0 register and configure the PA_RAMP_ENABLE field */ - g_xStatus = SpiritSpiReadRegisters(PA_POWER0_BASE, 1, &tempRegValue); - - /* Mask and return data */ - return (SpiritFunctionalState)((tempRegValue>>5) & 0x01); - -} - - -/** -* @brief Enables or Disables the AFC. -* @param xNewState new state for AFC. -* This parameter can be: S_ENABLE or S_DISABLE. -* @retval None. -*/ -void SpiritRadioAFC(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the AFC_2 register and configure the AFC Enabled field */ - SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= AFC2_AFC_MASK; - } - else - { - tempRegValue &= (~AFC2_AFC_MASK); - } - - /* Sets the AFC_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Enables or Disables the AFC freeze on sync word detection. -* @param xNewState new state for AFC freeze on sync word detection. -* This parameter can be: S_ENABLE or S_DISABLE. -* @retval None. -*/ -void SpiritRadioAFCFreezeOnSync(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the AFC_2 register and configure the AFC Freeze on Sync field */ - SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= AFC2_AFC_FREEZE_ON_SYNC_MASK; - } - else - { - tempRegValue &= (~AFC2_AFC_FREEZE_ON_SYNC_MASK); - } - - /* Sets the AFC_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Sets the AFC working mode. -* @param xMode the AFC mode. This parameter can be one of the values defined in @ref AFCMode : -* @arg AFC_SLICER_CORRECTION AFC loop closed on slicer -* @arg AFC_2ND_IF_CORRECTION AFC loop closed on 2nd conversion stage -* @retval None. -*/ -void SpiritRadioSetAFCMode(AFCMode xMode) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_AFC_MODE(xMode)); - - /* Reads the AFC_2 register and configure the AFC Mode field */ - SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); - if(xMode == AFC_2ND_IF_CORRECTION) - { - tempRegValue |= AFC_2ND_IF_CORRECTION; - } - else - { - tempRegValue &= (~AFC_2ND_IF_CORRECTION); - } - - /* Sets the AFC_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AFC working mode. -* @param None. -* @retval AFCMode Settled AFC mode. This parameter will be one of the values defined in @ref AFCMode : -* @arg AFC_SLICER_CORRECTION AFC loop closed on slicer -* @arg AFC_2ND_IF_CORRECTION AFC loop closed on 2nd conversion stage -*/ -AFCMode SpiritRadioGetAFCMode(void) -{ - uint8_t tempRegValue; - - /* Reads the AFC_2 register */ - g_xStatus = SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); - - /* Mask the AFC Mode field and returns the value */ - return (AFCMode)(tempRegValue & 0x20); - -} - - -/** -* @brief Sets the AFC peak detector leakage. -* @param cLeakage the peak detector leakage. This parameter shall be in the range: -* [0:31]. -* @retval None. -*/ -void SpiritRadioSetAFCPDLeakage(uint8_t cLeakage) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_AFC_PD_LEAKAGE(cLeakage)); - - /* Reads the AFC_2 register and configure the AFC PD leakage field */ - SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); - tempRegValue &= 0xE0; - tempRegValue |= cLeakage; - - /* Sets the AFC_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AFC2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AFC peak detector leakage. -* @param None. -* @retval uint8_t Peak detector leakage value. This parameter will be in the range: -* [0:31]. -*/ -uint8_t SpiritRadioGetAFCPDLeakage(void) -{ - uint8_t tempRegValue; - - /* Reads the AFC_2 register */ - g_xStatus = SpiritSpiReadRegisters(AFC2_BASE, 1, &tempRegValue); - - /* Mask the AFC PD leakage field and return the value */ - return (tempRegValue & 0x1F); - -} - - -/** -* @brief Sets the length of the AFC fast period expressed as number of samples. -* @param cLength length of the fast period in number of samples. -* @retval None. -*/ -void SpiritRadioSetAFCFastPeriod(uint8_t cLength) -{ - /* Sets the AFC_1 register */ - g_xStatus = SpiritSpiWriteRegisters(AFC1_BASE, 1, &cLength); - -} - - -/** -* @brief Returns the AFC fast period expressed as number of samples. -* @param None. -* @retval uint8_t Length of the fast period in number of samples. -*/ -uint8_t SpiritRadioGetAFCFastPeriod(void) -{ - uint8_t tempRegValue; - - /* Reads the AFC 1 register and return the value */ - g_xStatus = SpiritSpiReadRegisters(AFC1_BASE, 1, &tempRegValue); - - return tempRegValue; - -} - - -/** -* @brief Sets the AFC loop gain in fast mode. -* @param cGain AFC loop gain in fast mode. This parameter shall be in the range: -* [0:15]. -* @retval None. -*/ -void SpiritRadioSetAFCFastGain(uint8_t cGain) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_AFC_FAST_GAIN(cGain)); - - /* Reads the AFC_0 register and configure the AFC Fast Gain field */ - SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); - tempRegValue &= 0x0F; - tempRegValue |= cGain<<4; - - /* Sets the AFC_0 register */ - g_xStatus = SpiritSpiWriteRegisters(AFC0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AFC loop gain in fast mode. -* @param None. -* @retval uint8_t AFC loop gain in fast mode. This parameter will be in the range: -* [0:15]. -*/ -uint8_t SpiritRadioGetAFCFastGain(void) -{ - uint8_t tempRegValue; - - /* Reads the AFC_0 register, mask the AFC Fast Gain field and return the value */ - g_xStatus = SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); - - return ((tempRegValue & 0xF0)>>4); - -} - - -/** -* @brief Sets the AFC loop gain in slow mode. -* @param cGain AFC loop gain in slow mode. This parameter shall be in the range: -* [0:15]. -* @retval None. -*/ -void SpiritRadioSetAFCSlowGain(uint8_t cGain) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_AFC_SLOW_GAIN(cGain)); - - /* Reads the AFC_0 register and configure the AFC Slow Gain field */ - SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); - tempRegValue &= 0xF0; - tempRegValue |= cGain; - - /* Sets the AFC_0 register */ - g_xStatus = SpiritSpiWriteRegisters(AFC0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AFC loop gain in slow mode. -* @param None. -* @retval uint8_t AFC loop gain in slow mode. This parameter will be in the range: -* [0:15]. -*/ -uint8_t SpiritRadioGetAFCSlowGain(void) -{ - uint8_t tempRegValue; - - /* Reads the AFC_0 register, mask the AFC Slow Gain field and return the value */ - g_xStatus = SpiritSpiReadRegisters(AFC0_BASE, 1, &tempRegValue); - - return (tempRegValue & 0x0F); - -} - - -/** -* @brief Returns the AFC correction from the corresponding register. -* @param None. -* @retval int8_t AFC correction, read from the corresponding register. -* This parameter will be in the range [-128:127]. -*/ -int8_t SpiritRadioGetAFCCorrectionReg(void) -{ - uint8_t tempRegValue; - - /* Reads the AFC_CORR register, cast the read value as signed char and return it */ - g_xStatus = SpiritSpiReadRegisters(AFC_CORR_BASE, 1, &tempRegValue); - - return (int8_t)tempRegValue; - -} - - -/** -* @brief Returns the AFC correction expressed in Hz. -* @param None. -* @retval int32_t AFC correction expressed in Hz -* according to the following formula:
    -*
  • Fafc[Hz]= (Fdig/(12*2^10))*AFC_CORR where
    • -*
  • AFC_CORR is the value read in the AFC_CORR register
-*/ -int32_t SpiritRadioGetAFCCorrectionHz(void) -{ - int8_t correction; - uint32_t xtal = s_lXtalFrequency; - - /* Reads the AFC correction register */ - correction = SpiritRadioGetAFCCorrectionReg(); - - if(xtal>DOUBLE_XTAL_THR) - { - xtal /= 2; - } - - /* Calculates and return the Frequency Correction */ - return (int32_t)(xtal/(12*pow(2,10))*correction); - -} - - -/** -* @brief Enables or Disables the AGC. -* @param xNewState new state for AGC. -* This parameter can be: S_ENABLE or S_DISABLE -* @retval None. -*/ -void SpiritRadioAGC(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the AGCCTRL_0 register and configure the AGC Enabled field */ - SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= AGCCTRL0_AGC_MASK; - } - else - { - tempRegValue &= (~AGCCTRL0_AGC_MASK); - } - - /* Sets the AGCCTRL_0 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Sets the AGC working mode. -* @param xMode the AGC mode. This parameter can be one of the values defined in @ref AGCMode : -* @arg AGC_LINEAR_MODE AGC works in linear mode -* @arg AGC_BINARY_MODE AGC works in binary mode -* @retval None. -*/ -void SpiritRadioSetAGCMode(AGCMode xMode) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_AGC_MODE(xMode)); - - /* Reads the AGCCTRL_0 register and configure the AGC Mode field */ - SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - if(xMode == AGC_BINARY_MODE) - { - tempRegValue |= AGC_BINARY_MODE; - } - else - { - tempRegValue &= (~AGC_BINARY_MODE); - } - - /* Sets the AGCCTRL_0 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AGC working mode. -* @param None. -* @retval AGCMode Settled AGC mode. This parameter can be one of the values defined in @ref AGCMode : -* @arg AGC_LINEAR_MODE AGC works in linear mode -* @arg AGC_BINARY_MODE AGC works in binary mode -*/ -AGCMode SpiritRadioGetAGCMode(void) -{ - uint8_t tempRegValue; - - /* Reads the AGCCTRL_0 register, mask the AGC Mode field and return the value */ - g_xStatus = SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - - return (AGCMode)(tempRegValue & 0x40); - -} - - -/** -* @brief Enables or Disables the AGC freeze on steady state. -* @param xNewState new state for AGC freeze on steady state. -* This parameter can be: S_ENABLE or S_DISABLE. -* @retval None. -*/ -void SpiritRadioAGCFreezeOnSteady(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the AGCCTRL_2 register and configure the AGC Freeze On Steady field */ - SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= AGCCTRL2_FREEZE_ON_STEADY_MASK; - } - else - { - tempRegValue &= (~AGCCTRL2_FREEZE_ON_STEADY_MASK); - } - - /* Sets the AGCCTRL_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Enable or Disable the AGC freeze on sync detection. -* @param xNewState new state for AGC freeze on sync detection. -* This parameter can be: S_ENABLE or S_DISABLE. -* @retval None. -*/ -void SpiritRadioAGCFreezeOnSync(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the AGCCTRL_2 register and configure the AGC Freeze On Sync field */ - SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= AGCCTRL2_FREEZE_ON_SYNC_MASK; - } - else - { - tempRegValue &= (~AGCCTRL2_FREEZE_ON_SYNC_MASK); - } - - /* Sets the AGCCTRL_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Enable or Disable the AGC to start with max attenuation. -* @param xNewState new state for AGC start with max attenuation mode. -* This parameter can be: S_ENABLE or S_DISABLE. -* @retval None. -*/ -void SpiritRadioAGCStartMaxAttenuation(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue = 0x00; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the AGCCTRL_2 register and configure the AGC Start Max Attenuation field */ - SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - if(xNewState == S_ENABLE) - { - tempRegValue |= AGCCTRL2_START_MAX_ATTENUATION_MASK; - } - else - { - tempRegValue &= (~AGCCTRL2_START_MAX_ATTENUATION_MASK); - } - - /* Sets the AGCCTRL_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Sets the AGC measure time. -* @param nTime AGC measure time expressed in us. This parameter shall be in the range [0, 393216/F_Xo]. -* @retval None. -*/ -void SpiritRadioSetAGCMeasureTimeUs(uint16_t nTime) -{ - uint8_t tempRegValue, measure; - - /* Check the parameter */ - s_assert_param(IS_AGC_MEASURE_TIME_US(nTime,s_lXtalFrequency)); - - /* Reads the AGCCTRL_2 register */ - SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - - /* Calculates the measure time value to write in the register */ - measure = (uint8_t)lroundf(log2((float)nTime/1e6 * s_lXtalFrequency/12)); - (measure>15) ? (measure=15):(measure); - - /* Mask the MEAS_TIME field and write the new value */ - tempRegValue &= 0xF0; - tempRegValue |= measure; - - /* Sets the AGCCTRL_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AGC measure time. -* @param None. -* @retval uint16_t AGC measure time expressed in us. This parameter will be in the range [0, 393216/F_Xo]. -*/ -uint16_t SpiritRadioGetAGCMeasureTimeUs(void) -{ - uint8_t measure; - - /* Reads the AGCCTRL_2 register */ - g_xStatus = SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &measure); - - /* Mask the MEAS_TIME field */ - measure &= 0x0F; - - /* Calculates the measure time value to write in the register */ - return (uint16_t)((12.0/s_lXtalFrequency)*(float)pow(2,measure)*1e6); - -} - - -/** -* @brief Sets the AGC measure time. -* @param cTime AGC measure time to write in the MEAS_TIME field of AGCCTRL_2 register. -* This parameter shall be in the range [0:15]. -* @retval None. -*/ -void SpiritRadioSetAGCMeasureTime(uint8_t cTime) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_AGC_MEASURE_TIME(cTime)); - - /* Reads the AGCCTRL_2 register */ - SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - - /* Mask the MEAS_TIME field and write the new value */ - tempRegValue &= 0xF0; - tempRegValue |= cTime; - - /* Sets the AGCCTRL_2 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AGC measure time. -* @param None. -* @retval uint8_t AGC measure time read from the MEAS_TIME field of AGCCTRL_2 register. -* This parameter will be in the range [0:15]. -*/ -uint8_t SpiritRadioGetAGCMeasureTime(void) -{ - uint8_t tempRegValue; - - /* Reads the AGCCTRL_2 register, mask the MEAS_TIME field and return the value */ - g_xStatus = SpiritSpiReadRegisters(AGCCTRL2_BASE, 1, &tempRegValue); - - return (tempRegValue & 0x0F); - -} - - -/** -* @brief Sets the AGC hold time. -* @param cTime AGC hold time expressed in us. This parameter shall be in the range[0, 756/F_Xo]. -* @retval None. -*/ -void SpiritRadioSetAGCHoldTimeUs(uint8_t cTime) -{ - uint8_t tempRegValue, hold; - - /* Check the parameter */ - s_assert_param(IS_AGC_HOLD_TIME_US(cTime,s_lXtalFrequency)); - - /* Reads the AGCCTRL_0 register */ - SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - - /* Calculates the hold time value to write in the register */ - hold = (uint8_t)lroundf(((float)cTime/1e6 * s_lXtalFrequency)/12); - (hold>63) ? (hold=63):(hold); - - /* Mask the HOLD_TIME field and write the new value */ - tempRegValue &= 0xC0; - tempRegValue |= hold; - - /* Sets the AGCCTRL_0 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AGC hold time. -* @param None. -* @retval uint8_t AGC hold time expressed in us. This parameter will be in the range: -* [0, 756/F_Xo]. -*/ -uint8_t SpiritRadioGetAGCHoldTimeUs(void) -{ - uint8_t tempRegValue; - - /* Reads the AGCCTRL_0 register */ - g_xStatus = SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - - /* Mask the HOLD_TIME field */ - tempRegValue &= 0x3F; - - /* Calculates the hold time value and return it */ - return (uint8_t)lroundf ((12.0/s_lXtalFrequency)*(tempRegValue*1e6)); - -} - - -/** -* @brief Sets the AGC hold time. -* @param cTime AGC hold time to write in the HOLD_TIME field of AGCCTRL_0 register. -* This parameter shall be in the range [0:63]. -* @retval None. -*/ -void SpiritRadioSetAGCHoldTime(uint8_t cTime) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_AGC_HOLD_TIME(cTime)); - - /* Reads the AGCCTRL_0 register */ - SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - - /* Mask the HOLD_TIME field and write the new value */ - tempRegValue &= 0xC0; - tempRegValue |= cTime; - - /* Sets the AGCCTRL_0 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AGC hold time. -* @param None. -* @retval uint8_t AGC hold time read from the HOLD_TIME field of AGCCTRL_0 register. -* This parameter will be in the range [0:63]. -*/ -uint8_t SpiritRadioGetAGCHoldTime(void) -{ - uint8_t tempRegValue; - - /* Reads the AGCCTRL_0 register, mask the MEAS_TIME field and return the value */ - g_xStatus = SpiritSpiReadRegisters(AGCCTRL0_BASE, 1, &tempRegValue); - - return (tempRegValue & 0x3F); - -} - - -/** -* @brief Sets the AGC high threshold. -* @param cHighThreshold AGC high threshold to write in the THRESHOLD_HIGH field of AGCCTRL_1 register. -* This parameter shall be in the range [0:15]. -* @retval None. -*/ -void SpiritRadioSetAGCHighThreshold(uint8_t cHighThreshold) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_AGC_THRESHOLD(cHighThreshold)); - - /* Reads the AGCCTRL_1 register */ - SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); - - /* Mask the THRESHOLD_HIGH field and write the new value */ - tempRegValue &= 0x0F; - tempRegValue |= cHighThreshold<<4; - - /* Sets the AGCCTRL_1 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL1_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AGC high threshold. -* @param None. -* @retval uint8_t AGC high threshold read from the THRESHOLD_HIGH field of AGCCTRL_1 register. -* This parameter will be in the range [0:15]. -*/ -uint8_t SpiritRadioGetAGCHighThreshold(void) -{ - uint8_t tempRegValue; - - /* Reads the AGCCTRL_1 register, mask the THRESHOLD_HIGH field and return the value */ - g_xStatus = SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); - - return ((tempRegValue & 0xF0)>>4); - -} - - -/** -* @brief Sets the AGC low threshold. -* @param cLowThreshold AGC low threshold to write in the THRESHOLD_LOW field of AGCCTRL_1 register. -* This parameter shall be in the range [0:15]. -* @retval None. -*/ -void SpiritRadioSetAGCLowThreshold(uint8_t cLowThreshold) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_AGC_THRESHOLD(cLowThreshold)); - - /* Reads the AGCCTRL_1 register */ - SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); - - /* Mask the THRESHOLD_LOW field and write the new value */ - tempRegValue &= 0xF0; - tempRegValue |= cLowThreshold; - - /* Sets the AGCCTRL_1 register */ - g_xStatus = SpiritSpiWriteRegisters(AGCCTRL1_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the AGC low threshold. -* @param None. -* @retval uint8_t AGC low threshold read from the THRESHOLD_LOW field of AGCCTRL_1 register. -* This parameter will be in the range [0:15]. -*/ -uint8_t SpiritRadioGetAGCLowThreshold(void) -{ - uint8_t tempRegValue; - - /* Reads the AGCCTRL_1 register, mask the THRESHOLD_LOW field and return the value */ - g_xStatus = SpiritSpiReadRegisters(AGCCTRL1_BASE, 1, &tempRegValue); - - return (tempRegValue & 0x0F); - -} - - -/** -* @brief Sets the clock recovery algorithm. -* @param xMode the Clock Recovery mode. This parameter can be one of the values defined in @ref ClkRecMode : -* @arg CLK_REC_PLL PLL alogrithm for clock recovery -* @arg CLK_REC_DLL DLL alogrithm for clock recovery -* @retval None. -*/ -void SpiritRadioSetClkRecMode(ClkRecMode xMode) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_CLK_REC_MODE(xMode)); - - /* Reads the FDEV_0 register */ - SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); - - /* Mask the CLOCK_REC_ALGO_SEL field and write the new value */ - tempRegValue &= 0xF7; - tempRegValue |= (uint8_t)xMode; - - /* Sets the FDEV_0 register */ - g_xStatus = SpiritSpiWriteRegisters(FDEV0_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the Clock Recovery working mode. -* @param None. -* @retval ClkRecMode Clock Recovery mode. This parameter can be one of the values defined in @ref ClkRecMode : -* @arg CLK_REC_PLL PLL alogrithm for clock recovery -* @arg CLK_REC_DLL DLL alogrithm for clock recovery -*/ -ClkRecMode SpiritRadioGetClkRecMode(void) -{ - uint8_t tempRegValue; - - /* Reads the FDEV_0 register, mask the CLOCK_REC_ALGO_SEL field and return the value */ - g_xStatus = SpiritSpiReadRegisters(FDEV0_BASE, 1, &tempRegValue); - - return (ClkRecMode)(tempRegValue & 0x08); - -} - - -/** -* @brief Sets the clock recovery proportional gain. -* @param cPGain the Clock Recovery proportional gain to write in the CLK_REC_P_GAIN field of CLOCKREC register. -* It represents is log2 value of the clock recovery proportional gain. -* This parameter shall be in the range [0:7]. -* @retval None. -*/ -void SpiritRadioSetClkRecPGain(uint8_t cPGain) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_CLK_REC_P_GAIN(cPGain)); - - /* Reads the CLOCKREC register */ - SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); - - /* Mask the CLK_REC_P_GAIN field and write the new value */ - tempRegValue &= 0x1F; - tempRegValue |= (cPGain<<5); - - /* Sets the CLOCKREC register */ - g_xStatus = SpiritSpiWriteRegisters(CLOCKREC_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the log2 of the clock recovery proportional gain. -* @param None. -* @retval uint8_t Clock Recovery proportional gain read from the CLK_REC_P_GAIN field of CLOCKREC register. -* This parameter will be in the range [0:7]. -*/ -uint8_t SpiritRadioGetClkRecPGain(void) -{ - uint8_t tempRegValue; - - /* Reads the CLOCKREC register, mask the CLK_REC_P_GAIN field and return the value */ - g_xStatus = SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); - - return ((tempRegValue & 0xEF)>>5); - -} - - -/** -* @brief Sets the clock recovery integral gain. -* @param cIGain the Clock Recovery integral gain to write in the CLK_REC_I_GAIN field of CLOCKREC register. -* This parameter shall be in the range [0:15]. -* @retval None. -*/ -void SpiritRadioSetClkRecIGain(uint8_t cIGain) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_CLK_REC_I_GAIN(cIGain)); - - /* Reads the CLOCKREC register */ - SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); - - /* Mask the CLK_REC_P_GAIN field and write the new value */ - tempRegValue &= 0xF0; - tempRegValue |= cIGain; - - /* Sets the CLOCKREC register */ - g_xStatus = SpiritSpiWriteRegisters(CLOCKREC_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the clock recovery integral gain. -* @param None. -* @retval uint8_t Clock Recovery integral gain read from the -* CLK_REC_I_GAIN field of CLOCKREC register. -* This parameter will be in the range [0:15]. -*/ -uint8_t SpiritRadioGetClkRecIGain(void) -{ - uint8_t tempRegValue; - - /* Reads the CLOCKREC register, mask the CLK_REC_I_GAIN field and return the value */ - g_xStatus = SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); - - return (tempRegValue & 0x0F); - -} - - -/** -* @brief Sets the postfilter length for clock recovery algorithm. -* @param xLength the postfilter length in symbols. This parameter can be one of the values defined in @ref PstFltLength : -* @arg PSTFLT_LENGTH_8 Postfilter length is 8 symbols -* @arg PSTFLT_LENGTH_16 Postfilter length is 16 symbols -* @retval None. -*/ -void SpiritRadioSetClkRecPstFltLength(PstFltLength xLength) -{ - uint8_t tempRegValue; - - /* Check the parameter */ - s_assert_param(IS_PST_FLT_LENGTH(xLength)); - - /* Reads the CLOCKREC register */ - SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); - - /* Mask the PSTFLT_LEN field and write the new value */ - tempRegValue &= 0xEF; - tempRegValue |= (uint8_t)xLength; - - /* Sets the CLOCKREC register */ - g_xStatus = SpiritSpiWriteRegisters(CLOCKREC_BASE, 1, &tempRegValue); - -} - - -/** -* @brief Returns the postfilter length for clock recovery algorithm. -* @param None. -* @retval PstFltLength Postfilter length in symbols. This parameter can be one of the values defined in @ref PstFltLength : -* @arg PSTFLT_LENGTH_8 Postfilter length is 8 symbols -* @arg PSTFLT_LENGTH_16 Postfilter length is 16 symbols -*/ -PstFltLength SpiritRadioGetClkRecPstFltLength(void) -{ - uint8_t tempRegValue; - - /* Reads the CLOCKREC register, mask the PSTFLT_LEN field and return the value */ - g_xStatus = SpiritSpiReadRegisters(CLOCKREC_BASE, 1, &tempRegValue); - - return (PstFltLength)(tempRegValue & 0x10); - -} - - -/** -* @brief Enables or Disables the received data blanking when the CS is under the threshold. -* @param xNewState new state of this mode. -* This parameter can be: S_ENABLE or S_DISABLE . -* @retval None. -*/ -void SpiritRadioCsBlanking(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the ANT_SELECT_CONF_BASE and mask the CS_BLANKING BIT field */ - SpiritSpiReadRegisters(ANT_SELECT_CONF_BASE, 1, &tempRegValue); - - if(xNewState == S_ENABLE) - { - tempRegValue |= ANT_SELECT_CS_BLANKING_MASK; - } - else - { - tempRegValue &= (~ANT_SELECT_CS_BLANKING_MASK); - } - - /* Writes the new value in the ANT_SELECT_CONF register */ - g_xStatus = SpiritSpiWriteRegisters(ANT_SELECT_CONF_BASE, 1, &tempRegValue); - - -} - -/** -* @brief Enables or Disables the persistent RX mode. -* @param xNewState new state of this mode. -* This parameter can be: S_ENABLE or S_DISABLE . -* @retval None. -*/ -void SpiritRadioPersistenRx(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the PROTOCOL0_BASE and mask the PROTOCOL0_PERS_RX_MASK bitfield */ - SpiritSpiReadRegisters(PROTOCOL0_BASE, 1, &tempRegValue); - - if(xNewState == S_ENABLE) - { - tempRegValue |= PROTOCOL0_PERS_RX_MASK; - } - else - { - tempRegValue &= (~PROTOCOL0_PERS_RX_MASK); - } - - /* Writes the new value in the PROTOCOL0_BASE register */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL0_BASE, 1, &tempRegValue); - -} - -/** -* @brief Enables or Disables the synthesizer reference divider. -* @param xNewState new state for synthesizer reference divider. -* This parameter can be: S_ENABLE or S_DISABLE . -* @retval None. -*/ -void SpiritRadioSetRefDiv(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the SYNTH_CONFIG1_BASE and mask the REFDIV bit field */ - SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - - if(xNewState == S_ENABLE) - { - tempRegValue |= 0x80; - } - else - { - tempRegValue &= 0x7F; - } - - /* Writes the new value in the SYNTH_CONFIG1_BASE register */ - g_xStatus = SpiritSpiWriteRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - -} - -/** -* @brief Get the the synthesizer reference divider state. -* @param void. -* @retval None. -*/ -SpiritFunctionalState SpiritRadioGetRefDiv(void) -{ - uint8_t tempRegValue; - - g_xStatus = SpiritSpiReadRegisters(SYNTH_CONFIG1_BASE, 1, &tempRegValue); - - if(((tempRegValue>>7)&0x1)) - { - return S_ENABLE; - } - else - { - return S_DISABLE; - } - -} - -/** -* @brief Enables or Disables the synthesizer reference divider. -* @param xNewState new state for synthesizer reference divider. -* This parameter can be: S_ENABLE or S_DISABLE . -* @retval None. -*/ -void SpiritRadioSetDigDiv(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Check the parameters */ - s_assert_param(IS_SPIRIT_FUNCTIONAL_STATE(xNewState)); - - /* Reads the XO_RCO_TEST_BASE and mask the PD_CLKDIV bit field */ - SpiritSpiReadRegisters(XO_RCO_TEST_BASE, 1, &tempRegValue); - - if(xNewState == S_ENABLE) - { - tempRegValue &= 0xf7; - } - else - { - - tempRegValue |= 0x08; - } - - /* Writes the new value in the XO_RCO_TEST_BASE register */ - g_xStatus = SpiritSpiWriteRegisters(XO_RCO_TEST_BASE, 1, &tempRegValue); - -} - -/** -* @brief Get the the synthesizer reference divider state. -* @param void. -* @retval None. -*/ -SpiritFunctionalState SpiritRadioGetDigDiv(void) -{ - uint8_t tempRegValue; - - g_xStatus = SpiritSpiReadRegisters(XO_RCO_TEST_BASE, 1, &tempRegValue); - - if(((tempRegValue>>3)&0x1)) - { - return S_DISABLE; - } - else - { - return S_ENABLE; - } - -} - -/** -* @brief Returns the XTAL frequency. -* @param void. -* @retval uint32_t XTAL frequency. -*/ -uint32_t SpiritRadioGetXtalFrequency(void) -{ - return s_lXtalFrequency; -} - -/** -* @brief Sets the XTAL frequency. -* @param uint32_t XTAL frequency. -* @retval void. -*/ -void SpiritRadioSetXtalFrequency(uint32_t lXtalFrequency) -{ - s_lXtalFrequency = lXtalFrequency; -} - -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ - diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Timer.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Timer.c deleted file mode 100644 index b51f2466d..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Timer.c +++ /dev/null @@ -1,700 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Timer.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief Configuration and management of SPIRIT timers. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Timer.h" -#include "SPIRIT_Radio.h" -#include "MCU_Interface.h" - - - - -/** - * @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** - * @addtogroup SPIRIT_Timer - * @{ - */ - - -/** - * @defgroup Timer_Private_TypesDefinitions Timer Private Types Definitions - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Timer_Private_Defines Timer Private Defines - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Timer_Private_Macros Timer Private Macros - * @{ - */ - - -/** - *@} - */ - - -/** - * @defgroup Timer_Private_Variables Timer Private Variables - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Timer_Private_FunctionPrototypes Timer Private Function Prototypes - * @{ - */ - -/** - *@} - */ - - -/** - * @defgroup Timer_Private_Functions Timer Private Functions - * @{ - */ - -/** - * @brief Enables or Disables the LDCR mode. - * @param xNewState new state for LDCR mode. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritTimerLdcrMode(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - - /* Mask the read value to enable or disable the LDC mode */ - if(xNewState==S_ENABLE) - { - tempRegValue |= PROTOCOL2_LDC_MODE_MASK; - } - else - { - tempRegValue &= ~PROTOCOL2_LDC_MODE_MASK; - } - - /* Writes the register to Enable or Disable the LDCR mode */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL2_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Enables or Disables the LDCR timer reloading with the value stored in the LDCR_RELOAD registers. - * @param xNewState new state for LDCR reloading. - * This parameter can be: S_ENABLE or S_DISABLE. - * @retval None. - */ -void SpiritTimerLdcrAutoReload(SpiritFunctionalState xNewState) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - /* Mask te read value to enable or disable the reload on sync mode */ - if(xNewState==S_ENABLE) - { - tempRegValue |= PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK; - } - else - { - tempRegValue &= ~PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK; - } - - /* Writes the register to Enable or Disable the Auto Reload */ - g_xStatus = SpiritSpiWriteRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - -} - - -/** - * @brief Returns the LDCR timer reload bit. - * @param None. - * @retval SpiritFunctionalState: value of the reload bit. - */ -SpiritFunctionalState SpiritTimerLdcrGetAutoReload(void) -{ - uint8_t tempRegValue; - - /* Reads the register value */ - g_xStatus = SpiritSpiReadRegisters(PROTOCOL1_BASE, 1, &tempRegValue); - - return (SpiritFunctionalState)(tempRegValue & 0x80); - -} - -/** - * @brief Sets the RX timeout timer initialization registers with the values of COUNTER and PRESCALER according to the formula: Trx=PRESCALER*COUNTER*Tck. - * Remember that it is possible to have infinite RX_Timeout writing 0 in the RX_Timeout_Counter and/or RX_Timeout_Prescaler registers. - * @param cCounter value for the timer counter. - * This parameter must be an uint8_t. - * @param cPrescaler value for the timer prescaler. - * This parameter must be an uint8_t. - * @retval None. - */ -void SpiritTimerSetRxTimeout(uint8_t cCounter , uint8_t cPrescaler) -{ - uint8_t tempRegValue[2]={cPrescaler,cCounter}; - - /* Writes the prescaler and counter value for RX timeout in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 2, tempRegValue); - -} - - -/** - * @brief Sets the RX timeout timer counter and prescaler from the desired value in ms. it is possible to fix the RX_Timeout to - * a minimum value of 50.417us to a maximum value of about 3.28 s. - * @param fDesiredMsec desired timer value. - * This parameter must be a float. - * @retval None - */ - -void SpiritTimerSetRxTimeoutMs(float fDesiredMsec) -{ - uint8_t tempRegValue[2]; - - /* Computes the counter and prescaler value */ - SpiritTimerComputeRxTimeoutValues(fDesiredMsec , &tempRegValue[1] , &tempRegValue[0]); - - /* Writes the prescaler and counter value for RX timeout in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 2, tempRegValue); - -} - - -/** - * @brief Sets the RX timeout timer counter. If it is equal to 0 the timeout is infinite. - * @param cCounter value for the timer counter. - * This parameter must be an uint8_t. - * @retval None. - */ -void SpiritTimerSetRxTimeoutCounter(uint8_t cCounter) -{ - /* Writes the counter value for RX timeout in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS4_RX_TIMEOUT_COUNTER_BASE, 1, &cCounter); - -} - - -/** - * @brief Sets the RX timeout timer prescaler. If it is equal to 0 the timeout is infinite. - * @param cPrescaler value for the timer prescaler. - * This parameter must be an uint8_t. - * @retval None - */ -void SpiritTimerSetRxTimeoutPrescaler(uint8_t cPrescaler) -{ - /* Writes the prescaler value for RX timeout in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 1, &cPrescaler); - -} - - -/** - * @brief Returns the RX timeout timer. - * @param pfTimeoutMsec pointer to the variable in which the timeout expressed in milliseconds has to be stored. - * If the returned value is 0, it means that the RX_Timeout is infinite. - * This parameter must be a float*. - * @param pcCounter pointer to the variable in which the timer counter has to be stored. - * This parameter must be an uint8_t*. - * @param pcPrescaler pointer to the variable in which the timer prescaler has to be stored. - * This parameter must be an uint8_t*. - * @retval None. - */ -void SpiritTimerGetRxTimeout(float* pfTimeoutMsec, uint8_t* pcCounter , uint8_t* pcPrescaler) -{ - uint8_t tempRegValue[2]; - - /* Reads the RX timeout registers value */ - g_xStatus = SpiritSpiReadRegisters(TIMERS5_RX_TIMEOUT_PRESCALER_BASE, 2, tempRegValue); - - /* Returns values */ - (*pcPrescaler) = tempRegValue[0]; - (*pcCounter) = tempRegValue[1]; - - float nXtalFrequency = (float)SpiritRadioGetXtalFrequency(); - if(nXtalFrequency>DOUBLE_XTAL_THR) { - nXtalFrequency /= 2.0; - } - nXtalFrequency /= 1000.0; - *pfTimeoutMsec = (float)((tempRegValue[0]+1)*tempRegValue[1]*(1210.0/nXtalFrequency)); - - -} - - -/** - * @brief Sets the LDCR wake up timer initialization registers with the values of - * COUNTER and PRESCALER according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where - * Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us (PRESCALER and - * COUNTER equals to 0) and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals - * to 255). - * @param cCounter value for the timer counter. - * This parameter must be an uint8_t. - * @param cPrescaler value for the timer prescaler. - * This parameter must be an uint8_t. - * @retval None. - */ -void SpiritTimerSetWakeUpTimer(uint8_t cCounter , uint8_t cPrescaler) -{ - uint8_t tempRegValue[2]={cPrescaler,cCounter}; - - /* Writes the counter and prescaler value of wake-up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS3_LDC_PRESCALER_BASE, 2, tempRegValue); - -} - - -/** - * @brief Sets the LDCR wake up timer counter and prescaler from the desired value in ms, - * according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. - * The minimum vale of the wakeup timeout is 28.818us (PRESCALER and COUNTER equals to 0) - * and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals to 255). - * @param fDesiredMsec desired timer value. - * This parameter must be a float. - * @retval None. - */ -void SpiritTimerSetWakeUpTimerMs(float fDesiredMsec) -{ - uint8_t tempRegValue[2]; - - /* Computes counter and prescaler */ - SpiritTimerComputeWakeUpValues(fDesiredMsec , &tempRegValue[1] , &tempRegValue[0]); - - /* Writes the counter and prescaler value of wake-up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS3_LDC_PRESCALER_BASE, 2, tempRegValue); - -} - - -/** - * @brief Sets the LDCR wake up timer counter. Remember that this value is incresead by one in the Twu calculation. - * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us - * @param cCounter value for the timer counter. - * This parameter must be an uint8_t. - * @retval None. - */ -void SpiritTimerSetWakeUpTimerCounter(uint8_t cCounter) -{ - /* Writes the counter value for Wake_Up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS2_LDC_COUNTER_BASE, 1, &cCounter); - -} - - -/** - * @brief Sets the LDCR wake up timer prescaler. Remember that this value is incresead by one in the Twu calculation. - * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us - * @param cPrescaler value for the timer prescaler. - * This parameter must be an uint8_t. - * @retval None. - */ -void SpiritTimerSetWakeUpTimerPrescaler(uint8_t cPrescaler) -{ - /* Writes the prescaler value for Wake_Up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS3_LDC_PRESCALER_BASE, 1, &cPrescaler); - -} - - -/** - * @brief Returns the LDCR wake up timer, according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. - * @param pfWakeUpMsec pointer to the variable in which the wake-up time expressed in milliseconds has to be stored. - * This parameter must be a float*. - * @param pcCounter pointer to the variable in which the timer counter has to be stored. - * This parameter must be an uint8_t*. - * @param pcPrescaler pointer to the variable in which the timer prescaler has to be stored. - * This parameter must be an uint8_t*. - * @retval None. - */ -void SpiritTimerGetWakeUpTimer(float* pfWakeUpMsec, uint8_t* pcCounter , uint8_t* pcPrescaler) -{ - uint8_t tempRegValue[2]; - uint32_t xtal=SpiritRadioGetXtalFrequency(); - float rco_freq; - - rco_freq=(float)SpiritTimerGetRcoFrequency(); - - /* Reads the Wake_Up timer registers value */ - g_xStatus = SpiritSpiReadRegisters(TIMERS3_LDC_PRESCALER_BASE, 2, tempRegValue); - - /* Returns values */ - (*pcPrescaler)=tempRegValue[0]; - (*pcCounter)=tempRegValue[1]; - *pfWakeUpMsec = (float)((((*pcPrescaler)+1)*((*pcCounter)+1)*(1000.0/rco_freq))); - -} - - -/** - * @brief Sets the LDCR wake up timer reloading registers with the values of - * COUNTER and PRESCALER according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where - * Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us (PRESCALER and - * COUNTER equals to 0) and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals - * to 255). - * @param cCounter reload value for the timer counter. - * This parameter must be an uint8_t. - * @param cPrescaler reload value for the timer prescaler. - * This parameter must be an uint8_t. - * @retval None. - */ -void SpiritTimerSetWakeUpTimerReload(uint8_t cCounter , uint8_t cPrescaler) -{ - uint8_t tempRegValue[2]={cPrescaler,cCounter}; - - /* Writes the counter and prescaler value of reload wake-up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 2, tempRegValue); - -} - - -/** - * @brief Sets the LDCR wake up reload timer counter and prescaler from the desired value in ms, - * according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. - * The minimum vale of the wakeup timeout is 28.818us (PRESCALER and COUNTER equals to 0) - * and the maximum value is about 1.89 s (PRESCALER anc COUNTER equals to 255). - * @param fDesiredMsec desired timer value. - * This parameter must be a float. - * @retval None. - */ -void SpiritTimerSetWakeUpTimerReloadMs(float fDesiredMsec) -{ - uint8_t tempRegValue[2]; - - /* Computes counter and prescaler */ - SpiritTimerComputeWakeUpValues(fDesiredMsec , &tempRegValue[1] , &tempRegValue[0]); - - /* Writes the counter and prescaler value of reload wake-up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 2, tempRegValue); - -} - - -/** - * @brief Sets the LDCR wake up timer reload counter. Remember that this value is incresead by one in the Twu calculation. - * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us - * @param cCounter value for the timer counter. - * This parameter must be an uint8_t. - * @retval None - */ -void SpiritTimerSetWakeUpTimerReloadCounter(uint8_t cCounter) -{ - /* Writes the counter value for reload Wake_Up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS0_LDC_RELOAD_COUNTER_BASE, 1, &cCounter); - -} - - -/** - * @brief Sets the LDCR wake up timer reload prescaler. Remember that this value is incresead by one in the Twu calculation. - * Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us - * @param cPrescaler value for the timer prescaler. - * This parameter must be an uint8_t. - * @retval None - */ -void SpiritTimerSetWakeUpTimerReloadPrescaler(uint8_t cPrescaler) -{ - /* Writes the prescaler value for reload Wake_Up timer in the corresponding register */ - g_xStatus = SpiritSpiWriteRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 1, &cPrescaler); - -} - - -/** - * @brief Returns the LDCR wake up reload timer, according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck, where Tck = 28.818 us. - * @param pfWakeUpReloadMsec pointer to the variable in which the wake-up reload time expressed in milliseconds has to be stored. - * This parameter must be a float*. - * @param pcCounter pointer to the variable in which the timer counter has to be stored. - * This parameter must be an uint8_t*. - * @param pcPrescaler pointer to the variable in which the timer prescaler has to be stored. - * This parameter must be an uint8_t*. - * @retval None. - */ -void SpiritTimerGetWakeUpTimerReload(float* pfWakeUpReloadMsec, uint8_t* pcCounter , uint8_t* pcPrescaler) -{ - uint8_t tempRegValue[2]; - uint32_t xtal=SpiritRadioGetXtalFrequency(); - float rco_freq; - - rco_freq=(float)SpiritTimerGetRcoFrequency(); - - /* Reads the reload Wake_Up timer registers value */ - g_xStatus = SpiritSpiReadRegisters(TIMERS1_LDC_RELOAD_PRESCALER_BASE, 2, tempRegValue); - - /* Returns values */ - (*pcPrescaler)=tempRegValue[0]; - (*pcCounter)=tempRegValue[1]; - *pfWakeUpReloadMsec = (float)((((*pcPrescaler)+1)*((*pcCounter)+1)*(1000.0/rco_freq))); - -} - -/** - * @brief Computes and returns the RCO frequency. - * This frequency depends on the xtal frequency and the XTAL bit in register 0x01. - * @retval RCO frequency in Hz as an uint16_t. - */ -uint16_t SpiritTimerGetRcoFrequency(void) -{ - uint16_t rco_freq=34700; - uint32_t xtal=SpiritRadioGetXtalFrequency(); - - if(xtal>30000000) xtal/=2; - - if(xtal==25000000) - { - uint8_t xtal_flag; - SpiritSpiReadRegisters(0x01, 1, &xtal_flag); - xtal_flag=(xtal_flag&0x40); - - if(xtal_flag==0) - { - rco_freq=36100; - } - else - { - rco_freq=33300; - } - } - - return rco_freq; -} - -/** - * @brief Computes the values of the wakeup timer counter and prescaler from the user time expressed in millisecond. - * The prescaler and the counter values are computed maintaining the prescaler value as - * small as possible in order to obtain the best resolution, and in the meantime minimizing the error. - * @param fDesiredMsec desired wakeup timeout in millisecs. - * This parameter must be a float. Since the counter and prescaler are 8 bit registers the maximum - * reachable value is maxTime = fTclk x 256 x 256. - * @param pcCounter pointer to the variable in which the value for the wakeup timer counter has to be stored. - * This parameter must be a uint8_t*. - * @param pcPrescaler pointer to the variable in which the value for the wakeup timer prescaler has to be stored. - * This parameter must be an uint8_t*. - * @retval None - */ -void SpiritTimerComputeWakeUpValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler) -{ - float rco_freq,err; - uint32_t n; - - rco_freq=((float)SpiritTimerGetRcoFrequency())/1000; - - /* N cycles in the time base of the timer: - - clock of the timer is RCO frequency - - divide times 1000 more because we have an input in ms (variable rco_freq is already this frequency divided by 1000) - */ - n=(uint32_t)(fDesiredMsec*rco_freq); - - /* check if it is possible to reach that target with prescaler and counter of spirit1 */ - if(n/0xFF>0xFD) - { - /* if not return the maximum possible value */ - (*pcCounter) = 0xFF; - (*pcPrescaler) = 0xFF; - return; - } - - /* prescaler is really 2 as min value */ - (*pcPrescaler)=(n/0xFF)+2; - (*pcCounter) = n / (*pcPrescaler); - - /* check if the error is minimum */ - err=S_ABS((float)(*pcCounter)*(*pcPrescaler)/rco_freq-fDesiredMsec); - - if((*pcCounter)<=254) - { - if(S_ABS((float)((*pcCounter)+1)*(*pcPrescaler)/rco_freq-fDesiredMsec)1) - (*pcCounter)--; - else - (*pcCounter)=1; -} - - -/** - * @brief Computes the values of the rx_timeout timer counter and prescaler from the user time expressed in millisecond. - * The prescaler and the counter values are computed maintaining the prescaler value as - * small as possible in order to obtain the best resolution, and in the meantime minimizing the error. - * @param fDesiredMsec desired rx_timeout in millisecs. - * This parameter must be a float. Since the counter and prescaler are 8 bit registers the maximum - * reachable value is maxTime = fTclk x 255 x 255. - * @param pcCounter pointer to the variable in which the value for the rx_timeout counter has to be stored. - * This parameter must be a uint8_t*. - * @param pcPrescaler pointer to the variable in which the value for the rx_timeout prescaler has to be stored. - * This parameter must be an uint8_t*. - * @retval None - */ -void SpiritTimerComputeRxTimeoutValues(float fDesiredMsec , uint8_t* pcCounter , uint8_t* pcPrescaler) -{ - uint32_t nXtalFrequency = SpiritRadioGetXtalFrequency(); - uint32_t n; - float err; - - /* if xtal is doubled divide it by 2 */ - if(nXtalFrequency>DOUBLE_XTAL_THR) { - nXtalFrequency >>= 1; - } - - /* N cycles in the time base of the timer: - - clock of the timer is xtal/1210 - - divide times 1000 more because we have an input in ms - */ - n=(uint32_t)(fDesiredMsec*nXtalFrequency/1210000); - - /* check if it is possible to reach that target with prescaler and counter of spirit1 */ - if(n/0xFF>0xFD) - { - /* if not return the maximum possible value */ - (*pcCounter) = 0xFF; - (*pcPrescaler) = 0xFF; - return; - } - - /* prescaler is really 2 as min value */ - (*pcPrescaler)=(n/0xFF)+2; - (*pcCounter) = n / (*pcPrescaler); - - /* check if the error is minimum */ - err=S_ABS((float)(*pcCounter)*(*pcPrescaler)*1210000/nXtalFrequency-fDesiredMsec); - - if((*pcCounter)<=254) - { - if(S_ABS((float)((*pcCounter)+1)*(*pcPrescaler)*1210000/nXtalFrequency-fDesiredMsec)1) - (*pcCounter)--; - else - (*pcCounter)=1; -} - - -/** - * @brief Sets the RX timeout stop conditions. - * @param xStopCondition new stop condition. - * This parameter can be any value of @ref RxTimeoutStopCondition. - * @retval None - */ -void SpiritTimerSetRxTimeoutStopCondition(RxTimeoutStopCondition xStopCondition) -{ - uint8_t tempRegValue[2]; - - /* Check the parameters */ - s_assert_param(IS_RX_TIMEOUT_STOP_CONDITION(xStopCondition)); - - /* Reads value on the PKT_FLT_OPTIONS and PROTOCOL2 register */ - g_xStatus = SpiritSpiReadRegisters(PCKT_FLT_OPTIONS_BASE, 2, tempRegValue); - - tempRegValue[0] &= 0xBF; - tempRegValue[0] |= ((xStopCondition & 0x08) << 3); - - tempRegValue[1] &= 0x1F; - tempRegValue[1] |= (xStopCondition << 5); - - /* Writes value on the PKT_FLT_OPTIONS and PROTOCOL2 register */ - g_xStatus = SpiritSpiWriteRegisters(PCKT_FLT_OPTIONS_BASE, 2, tempRegValue); - -} - -/** - * @brief Sends the LDC_RELOAD command to SPIRIT. Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER registers. - * @param None. - * @retval None - */ -void SpiritTimerReloadStrobe(void) -{ - /* Sends the CMD_LDC_RELOAD command */ - g_xStatus = SpiritSpiCommandStrobes(COMMAND_LDC_RELOAD); - -} - - -/** - *@} - */ - - -/** - *@} - */ - - -/** - *@} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Types.c b/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Types.c deleted file mode 100644 index 66a9d9339..000000000 --- a/platform/stm32nucleo-spirit1/drivers/spirit1/src/SPIRIT_Types.c +++ /dev/null @@ -1,226 +0,0 @@ -/** - ****************************************************************************** - * @file SPIRIT_Types.c - * @author VMA division - AMS - * @version 3.2.2 - * @date 08-July-2015 - * @brief File for SPIRIT types. - * @details - * - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "SPIRIT_Types.h" -#include "MCU_Interface.h" - - -/** @addtogroup SPIRIT_Libraries - * @{ - */ - - -/** @addtogroup SPIRIT_Types - * @{ - */ - - -/** @defgroup Types_Private_TypesDefinitions Types Private Types Definitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Types_Private_Defines Types Private Defines - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Types_Private_Macros Types Private Macros - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup Types_Private_Variables Types Private Variables - * @{ - */ - -/** - * @brief Spirit Status global variable. - * This global variable of @ref SpiritStatus type is updated on every SPI transaction - * to maintain memory of Spirit Status. - */ - -volatile SpiritStatus g_xStatus; - -/** - * @} - */ - - - -/** @defgroup Types_Private_FunctionPrototypes Types Private FunctionPrototypes - * @{ - */ - - - -/** - * @} - */ - - - -/** @defgroup Types_Private_Functions Types Private Functions - * @{ - */ - -#ifdef SPIRIT_USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file pointer to the source file name - * @param line assert_param error line source number - * @retval : None - */ -void s_assert_failed(uint8_t* file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number */ - printf("Wrong parameters value: file %s on line %d\r\n", file, line); - - /* Infinite loop */ - while (1) - { - } -} -#elif SPIRIT_USE_VCOM_ASSERT - -#include "SDK_EVAL_VC_General.h" - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file pointer to the source file name - * @param line assert_param error line source number - * @param expression: string representing the assert failed expression - * @retval : None - */ -void s_assert_failed(uint8_t* file, uint32_t line, char* expression) -{ - - printf("\n\rVCOM DEBUG: Incorrect parameter. Please reboot.\n\r"); - printf("%s:%d \n\r",file,line); - printf("The expression %s returned FALSE.\n\r", expression); - - /* Infinite loop */ - while (1) - { - } -} - -#elif SPIRIT_USE_FRAME_ASSERT - -#include "SdkUsbProtocol.h" - -/** - * @brief Sends a notify frame with a payload indicating the name - * of the assert failed. - * @param expression: string representing the assert failed expression - * @retval : None - */ -void s_assert_failed(char* expression) -{ - char pcPayload[100]; - uint16_t i; - - for(i = 0 ; expression[i]!='(' ; i++); - expression[i]='\0'; - - strcpy(pcPayload, &expression[3]); - - //sprintf(pcPayload, "The expression %s returned FALSE.\n\r", expression); - SpiritNotifyAssertFailed(pcPayload); - -} - -#endif - - -/** - * @brief Updates the gState (the global variable used to maintain memory of Spirit Status) - * reading the MC_STATE register of SPIRIT. - * @param None - * @retval None - */ -void SpiritRefreshStatus(void) -{ - uint8_t tempRegValue; - - /* Reads the MC_STATUS register to update the g_xStatus */ - g_xStatus = SpiritSpiReadRegisters(MC_STATE1_BASE, 1, &tempRegValue); - -} - - -/** - * @} - */ - - - -/** - * @} - */ - - - -/** - * @} - */ - - - -/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/Release_Notes.html deleted file mode 100644 index 402f5716d..000000000 --- a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/Release_Notes.html +++ /dev/null @@ -1,159 +0,0 @@ - - - - - - - - -Release Notes for STM32L1xx-Nucleo Board Drivers - - -
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Release -Notes for STM32L1xx-Nucleo  Board Drivers

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Copyright -2014 STMicroelectronics

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Update History

1.0.0 -/ 05-September-2014

Main -Changes

-
  • First -official release dedicated to STM32CubeL1 based development. Supported devices is STM32L152RE.
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License

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Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
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  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
    2. -
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
    3. -
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived
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    4. -
-       -from this software without specific prior written permission.
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-THIS -SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGE.
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For -complete documentation on STM32 Microcontrollers -visit www.st.com/STM32

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- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.c b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.c deleted file mode 100644 index c51c045bb..000000000 --- a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.c +++ /dev/null @@ -1,844 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_nucleo.c - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file provides set of firmware functions to manage: - * - LEDs and push-button available on STM32L1XX-Nucleo Kit - * from STMicroelectronics - * - LCD, joystick and microSD available on Adafruit 1.8" TFT LCD - * shield (reference ID 802) - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_nucleo.h" - -/** @addtogroup BSP - * @{ - */ - -/** @defgroup STM32L1XX_NUCLEO STM32L152RE-Nucleo - * @brief This file provides set of firmware functions to manage Leds and push-button - * available on STM32L1XX-Nucleo Kit from STMicroelectronics. - * It provides also LCD, joystick and uSD functions to communicate with - * Adafruit 1.8" TFT LCD shield (reference ID 802) - * @{ - */ - - -/** @defgroup STM32L1XX_NUCLEO_Private_Defines Private Defines - * @{ - */ - -/** -* @brief STM32L152RE NUCLEO BSP Driver version -*/ -#define __STM32L1XX_NUCLEO_BSP_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L1XX_NUCLEO_BSP_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1XX_NUCLEO_BSP_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1XX_NUCLEO_BSP_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1XX_NUCLEO_BSP_VERSION ((__STM32L1XX_NUCLEO_BSP_VERSION_MAIN << 24)\ - |(__STM32L1XX_NUCLEO_BSP_VERSION_SUB1 << 16)\ - |(__STM32L1XX_NUCLEO_BSP_VERSION_SUB2 << 8 )\ - |(__STM32L1XX_NUCLEO_BSP_VERSION_RC)) - -/** - * @brief LINK SD Card - */ -#define SD_DUMMY_BYTE 0xFF -#define SD_NO_RESPONSE_EXPECTED 0x80 - -/** - * @} - */ - - -/** @defgroup STM32L1XX_NUCLEO_Private_Variables Private Variables - * @{ - */ -//GPIO_TypeDef* GPIO_PORT[LEDn] = {LED2_GPIO_PORT}; -//const uint16_t GPIO_PIN[LEDn] = {LED2_PIN}; -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT, LED5_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, - LED4_PIN, LED5_PIN}; - - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT}; -const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN}; -const uint16_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn}; - -/** - * @brief BUS variables - */ - -#ifdef HAL_SPI_MODULE_ENABLED -uint32_t SpixTimeout = NUCLEO_SPIx_TIMEOUT_MAX; /* success, 1=> fail) - */ -uint8_t BSP_JOY_Init(void) -{ - ADCx_Init(); - - /* Select Channel 8 to be converted */ - sConfig.Channel = ADC_CHANNEL_8; - sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES; - sConfig.Rank = 1; - - /* Return Joystick initialization status */ - return HAL_ADC_ConfigChannel(&hnucleo_Adc, &sConfig); -} - -/** - * @brief Returns the Joystick key pressed. - * @note To know which Joystick key is pressed we need to detect the voltage - * level on each key output - * - None : 3.3 V / 4095 - * - SEL : 1.055 V / 1308 - * - DOWN : 0.71 V / 88 - * - LEFT : 3.0 V / 3720 - * - RIGHT : 0.595 V / 737 - * - UP : 1.65 V / 2046 - * @retval JOYState_TypeDef: Code of the Joystick key pressed. - */ -JOYState_TypeDef BSP_JOY_GetState(void) -{ - JOYState_TypeDef state = JOY_NONE; - uint16_t keyconvertedvalue = 0; - - /* Start the conversion process */ - HAL_ADC_Start(&hnucleo_Adc); - - /* Wait for the end of conversion */ - HAL_ADC_PollForConversion(&hnucleo_Adc, 10); - - /* Check if the continous conversion of regular channel is finished */ - if(HAL_ADC_GetState(&hnucleo_Adc) == HAL_ADC_STATE_EOC_REG) - { - /* Get the converted value of regular channel */ - keyconvertedvalue = HAL_ADC_GetValue(&hnucleo_Adc); - } - - if((keyconvertedvalue > 2010) && (keyconvertedvalue < 2090)) - { - state = JOY_UP; - } - else if((keyconvertedvalue > 680) && (keyconvertedvalue < 780)) - { - state = JOY_RIGHT; - } - else if((keyconvertedvalue > 1270) && (keyconvertedvalue < 1350)) - { - state = JOY_SEL; - } - else if((keyconvertedvalue > 50) && (keyconvertedvalue < 130)) - { - state = JOY_DOWN; - } - else if((keyconvertedvalue > 3680) && (keyconvertedvalue < 3760)) - { - state = JOY_LEFT; - } - else - { - state = JOY_NONE; - } - - /* Return the code of the Joystick key pressed*/ - return state; -} - -#endif /* HAL_ADC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup STM32L1XX_NUCLEO_Private_Functions - * @{ - */ - -#ifdef HAL_SPI_MODULE_ENABLED -/****************************************************************************** - BUS OPERATIONS -*******************************************************************************/ -/** - * @brief Initializes SPI MSP. - * @retval None - */ -static void SPIx_MspInit(void) -{ - GPIO_InitTypeDef gpioinitstruct = {0}; - - /*** Configure the GPIOs ***/ - /* Enable GPIO clock */ - NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE(); - NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE(); - - /* Configure SPI SCK */ - gpioinitstruct.Pin = NUCLEO_SPIx_SCK_PIN; - gpioinitstruct.Mode = GPIO_MODE_AF_PP; - gpioinitstruct.Pull = GPIO_PULLUP; - gpioinitstruct.Speed = GPIO_SPEED_HIGH; - gpioinitstruct.Alternate = NUCLEO_SPIx_SCK_AF; - HAL_GPIO_Init(NUCLEO_SPIx_SCK_GPIO_PORT, &gpioinitstruct); - - /* Configure SPI MISO and MOSI */ - gpioinitstruct.Pin = NUCLEO_SPIx_MOSI_PIN; - gpioinitstruct.Alternate = NUCLEO_SPIx_MISO_MOSI_AF; - gpioinitstruct.Pull = GPIO_PULLDOWN; - HAL_GPIO_Init(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, &gpioinitstruct); - - gpioinitstruct.Pin = NUCLEO_SPIx_MISO_PIN; - HAL_GPIO_Init(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, &gpioinitstruct); - - /*** Configure the SPI peripheral ***/ - /* Enable SPI clock */ - NUCLEO_SPIx_CLK_ENABLE(); -} - -/** - * @brief Initializes SPI HAL. - * @retval None - */ -static void SPIx_Init(void) -{ - if(HAL_SPI_GetState(&hnucleo_Spi) == HAL_SPI_STATE_RESET) - { - /* SPI Config */ - hnucleo_Spi.Instance = NUCLEO_SPIx; - /* SPI baudrate is set to 8 MHz maximum (PCLK2/SPI_BaudRatePrescaler = 32/4 = 8 MHz) - to verify these constraints: - - ST7735 LCD SPI interface max baudrate is 15MHz for write and 6.66MHz for read - Since the provided driver doesn't use read capability from LCD, only constraint - on write baudrate is considered. - - SD card SPI interface max baudrate is 25MHz for write/read - - PCLK2 max frequency is 32 MHz - */ - hnucleo_Spi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; - hnucleo_Spi.Init.Direction = SPI_DIRECTION_2LINES; - hnucleo_Spi.Init.CLKPhase = SPI_PHASE_2EDGE; - hnucleo_Spi.Init.CLKPolarity = SPI_POLARITY_HIGH; - hnucleo_Spi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - hnucleo_Spi.Init.CRCPolynomial = 7; - hnucleo_Spi.Init.DataSize = SPI_DATASIZE_8BIT; - hnucleo_Spi.Init.FirstBit = SPI_FIRSTBIT_MSB; - hnucleo_Spi.Init.NSS = SPI_NSS_SOFT; - hnucleo_Spi.Init.TIMode = SPI_TIMODE_DISABLED; - hnucleo_Spi.Init.Mode = SPI_MODE_MASTER; - - SPIx_MspInit(); - HAL_SPI_Init(&hnucleo_Spi); - } -} - -/** - * @brief SPI Read 4 bytes from device - * @retval Read data -*/ -static uint32_t SPIx_Read(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t readvalue = 0; - uint32_t writevalue = 0xFFFFFFFF; - - status = HAL_SPI_TransmitReceive(&hnucleo_Spi, (uint8_t*) &writevalue, (uint8_t*) &readvalue, 1, SpixTimeout); - - /* Check the communication status */ - if(status != HAL_OK) - { - /* Execute user timeout callback */ - SPIx_Error(); - } - - return readvalue; -} - -/** - * @brief SPI Write a byte to device - * @param Value: value to be written - * @retval None - */ -static void SPIx_Write(uint8_t Value) -{ - HAL_StatusTypeDef status = HAL_OK; - - status = HAL_SPI_Transmit(&hnucleo_Spi, (uint8_t*) &Value, 1, SpixTimeout); - - /* Check the communication status */ - if(status != HAL_OK) - { - /* Execute user timeout callback */ - SPIx_Error(); - } -} - -/** - * @brief SPI error treatment function - * @retval None - */ -static void SPIx_Error (void) -{ - /* De-initialize the SPI communication BUS */ - HAL_SPI_DeInit(&hnucleo_Spi); - - /* Re-Initiaize the SPI communication BUS */ - SPIx_Init(); -} - -/****************************************************************************** - LINK OPERATIONS -*******************************************************************************/ - -/********************************* LINK SD ************************************/ -/** - * @brief Initializes the SD Card and put it into StandBy State (Ready for - * data transfer). - * @retval None - */ -void SD_IO_Init(void) -{ - GPIO_InitTypeDef gpioinitstruct = {0}; - uint8_t counter = 0; - - /* SD_CS_GPIO Periph clock enable */ - SD_CS_GPIO_CLK_ENABLE(); - - /* Configure SD_CS_PIN pin: SD Card CS pin */ - gpioinitstruct.Pin = SD_CS_PIN; - gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; - gpioinitstruct.Pull = GPIO_PULLUP; - gpioinitstruct.Speed = GPIO_SPEED_HIGH; - HAL_GPIO_Init(SD_CS_GPIO_PORT, &gpioinitstruct); - - /*------------Put SD in SPI mode--------------*/ - /* SD SPI Config */ - SPIx_Init(); - - /* SD chip select high */ - SD_CS_HIGH(); - - /* Send dummy byte 0xFF, 10 times with CS high */ - /* Rise CS and MOSI for 80 clocks cycles */ - for (counter = 0; counter <= 9; counter++) - { - /* Send dummy byte 0xFF */ - SD_IO_WriteByte(SD_DUMMY_BYTE); - } -} - -/** - * @brief Writes a byte on the SD. - * @param Data: byte to send. - * @retval None - */ -void SD_IO_WriteByte(uint8_t Data) -{ - /* Send the byte */ - SPIx_Write(Data); -} - -/** - * @brief Reads a byte from the SD. - * @retval The received byte. - */ -uint8_t SD_IO_ReadByte(void) - { - uint8_t data = 0; - - /* Get the received data */ - data = SPIx_Read(); - - /* Return the shifted data */ - return data; -} - -/** - * @brief Sends 5 bytes command to the SD card and get response - * @param Cmd: The user expected command to send to SD card. - * @param Arg: The command argument. - * @param Crc: The CRC. - * @param Response: Expected response from the SD card - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef SD_IO_WriteCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc, uint8_t Response) -{ - uint32_t counter = 0x00; - uint8_t frame[6] = {0}; - - /* Prepare Frame to send */ - frame[0] = (Cmd | 0x40); /* Construct byte 1 */ - frame[1] = (uint8_t)(Arg >> 24); /* Construct byte 2 */ - frame[2] = (uint8_t)(Arg >> 16); /* Construct byte 3 */ - frame[3] = (uint8_t)(Arg >> 8); /* Construct byte 4 */ - frame[4] = (uint8_t)(Arg); /* Construct byte 5 */ - frame[5] = (Crc); /* Construct byte 6 */ - - /* SD chip select low */ - SD_CS_LOW(); - - /* Send Frame */ - for (counter = 0; counter < 6; counter++) - { - SD_IO_WriteByte(frame[counter]); /* Send the Cmd bytes */ - } - - if(Response != SD_NO_RESPONSE_EXPECTED) - { - return SD_IO_WaitResponse(Response); - } - - return HAL_OK; -} - -/** - * @brief Waits response from the SD card - * @param Response: Expected response from the SD card - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef SD_IO_WaitResponse(uint8_t Response) -{ - uint32_t timeout = 0xFFFF; - - /* Check if response is got or a timeout is happen */ - while ((SD_IO_ReadByte() != Response) && timeout) - { - timeout--; - } - - if (timeout == 0) - { - /* After time out */ - return HAL_TIMEOUT; - } - else - { - /* Right response got */ - return HAL_OK; - } - } - -/** - * @brief Sends dummy byte with CS High - * @retval None - */ -void SD_IO_WriteDummy(void) -{ - /* SD chip select high */ - SD_CS_HIGH(); - - /* Send Dummy byte 0xFF */ - SD_IO_WriteByte(SD_DUMMY_BYTE); -} - -/********************************* LINK LCD ***********************************/ -/** - * @brief Initializes the LCD - * @retval None - */ -void LCD_IO_Init(void) -{ - GPIO_InitTypeDef gpioinitstruct = {0}; - - /* LCD_CS_GPIO and LCD_DC_GPIO Periph clock enable */ - LCD_CS_GPIO_CLK_ENABLE(); - LCD_DC_GPIO_CLK_ENABLE(); - - /* Configure LCD_CS_PIN pin: LCD Card CS pin */ - gpioinitstruct.Pin = LCD_CS_PIN; - gpioinitstruct.Mode = GPIO_MODE_OUTPUT_PP; - gpioinitstruct.Pull = GPIO_NOPULL; - gpioinitstruct.Speed = GPIO_SPEED_HIGH; - HAL_GPIO_Init(SD_CS_GPIO_PORT, &gpioinitstruct); - - /* Configure LCD_DC_PIN pin: LCD Card DC pin */ - gpioinitstruct.Pin = LCD_DC_PIN; - HAL_GPIO_Init(LCD_DC_GPIO_PORT, &gpioinitstruct); - - /* LCD chip select high */ - LCD_CS_HIGH(); - - /* LCD SPI Config */ - SPIx_Init(); -} - -/** - * @brief Writes command to select the LCD register. - * @param LCDReg: Address of the selected register. - * @retval None - */ -void LCD_IO_WriteReg(uint8_t LCDReg) -{ - /* Reset LCD control line CS */ - LCD_CS_LOW(); - - /* Set LCD data/command line DC to Low */ - LCD_DC_LOW(); - - /* Send Command */ - SPIx_Write(LCDReg); - - /* Deselect : Chip Select high */ - LCD_CS_HIGH(); -} - -/** -* @brief Write register value. -* @param pData Pointer on the register value -* @param Size Size of byte to transmit to the register -* @retval None -*/ -void LCD_IO_WriteMultipleData(uint8_t *pData, uint32_t Size) -{ - uint32_t counter = 0; - - /* Reset LCD control line CS */ - LCD_CS_LOW(); - - /* Set LCD data/command line DC to High */ - LCD_DC_HIGH(); - - if (Size == 1) - { - /* Only 1 byte to be sent to LCD - general interface can be used */ - /* Send Data */ - SPIx_Write(*pData); - } - else - { - /* Several data should be sent in a raw */ - /* Direct SPI accesses for optimization */ - for (counter = Size; counter != 0; counter--) - { - while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE) - { - } - /* Need to invert bytes for LCD*/ - *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *(pData+1); - - while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_TXE) != SPI_FLAG_TXE) - { - } - *((__IO uint8_t*)&hnucleo_Spi.Instance->DR) = *pData; - counter--; - pData += 2; - } - - /* Wait until the bus is ready before releasing Chip select */ - while(((hnucleo_Spi.Instance->SR) & SPI_FLAG_BSY) != RESET) - { - } - } - /* Deselect : Chip Select high */ - LCD_CS_HIGH(); -} - -/** - * @brief Wait for loop in ms. - * @param Delay in ms. - * @retval None - */ -void LCD_Delay(uint32_t Delay) -{ - HAL_Delay(Delay); -} - -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED -/******************************* LINK JOYSTICK ********************************/ -/** - * @brief Initializes ADC MSP. - * @retval None - */ -static void ADCx_MspInit(ADC_HandleTypeDef *hadc) -{ - GPIO_InitTypeDef gpioinitstruct = {0}; - - /*** Configure the GPIOs ***/ - /* Enable GPIO clock */ - NUCLEO_ADCx_GPIO_CLK_ENABLE(); - - /* Configure ADC1 Channel8 as analog input */ - gpioinitstruct.Pin = NUCLEO_ADCx_GPIO_PIN ; - gpioinitstruct.Mode = GPIO_MODE_ANALOG; - gpioinitstruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(NUCLEO_ADCx_GPIO_PORT, &gpioinitstruct); - - /*** Configure the ADC peripheral ***/ - /* Enable ADC clock */ - NUCLEO_ADCx_CLK_ENABLE(); -} - -/** - * @brief Initializes ADC HAL. - * @retval None - */ -static void ADCx_Init(void) -{ - if(HAL_ADC_GetState(&hnucleo_Adc) == HAL_ADC_STATE_RESET) - { - /* ADC Config */ - hnucleo_Adc.Instance = NUCLEO_ADCx; - hnucleo_Adc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; /* (must not exceed 16MHz) */ - hnucleo_Adc.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_DISABLE; - hnucleo_Adc.Init.LowPowerAutoWait = ADC_AUTOWAIT_UNTIL_DATA_READ; - hnucleo_Adc.Init.Resolution = ADC_RESOLUTION12b; - hnucleo_Adc.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hnucleo_Adc.Init.ContinuousConvMode = DISABLE; - hnucleo_Adc.Init.ScanConvMode = DISABLE; - hnucleo_Adc.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hnucleo_Adc.Init.EOCSelection = EOC_SINGLE_CONV; - hnucleo_Adc.Init.DMAContinuousRequests = DISABLE; - - ADCx_MspInit(&hnucleo_Adc); - HAL_ADC_Init(&hnucleo_Adc); - } -} - -#endif /* HAL_ADC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.h b/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.h deleted file mode 100644 index ef185dc2d..000000000 --- a/platform/stm32nucleo-spirit1/drivers/stm32l1xx_nucleo/stm32l1xx_nucleo.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_nucleo.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains definitions for: - * - LEDs and push-button available on STM32L1XX-Nucleo Kit - * from STMicroelectronics - * - LCD, joystick and microSD available on Adafruit 1.8" TFT LCD - * shield (reference ID 802) - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup STM32L1XX_NUCLEO - * @{ - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1XX_NUCLEO_H -#define __STM32L1XX_NUCLEO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - - -/** @defgroup STM32L1XX_NUCLEO_Exported_Types Exported Types - * @{ - */ - -typedef enum -{ - BUTTON_USER = 0, -} Button_TypeDef; - -typedef enum -{ - BUTTON_MODE_GPIO = 0, - BUTTON_MODE_EXTI = 1 -} ButtonMode_TypeDef; - -typedef enum -{ - JOY_NONE = 0, - JOY_SEL = 1, - JOY_DOWN = 2, - JOY_LEFT = 3, - JOY_RIGHT = 4, - JOY_UP = 5 -} JOYState_TypeDef; - -/** - * @} - */ - -/** @defgroup STM32L1XX_NUCLEO_Exported_Constants Exported Constants - * @{ - */ - -/** - * @brief Define for STM32L1xx_NUCLEO board - */ -#if !defined (USE_STM32L1xx_NUCLEO) - #define USE_STM32L1xx_NUCLEO -#endif - -/** @defgroup STM32L1XX_NUCLEO_LED LED Constants - * @{ - */ - -typedef enum -{ - LED1 = 0, - LED2 = 1, - LED3 = 2, - LED4 = 3, - LED5 = 4 -} Led_TypeDef; - - - -#define LEDn 5 - -#define LED2_PIN GPIO_PIN_5 -#define LED2_GPIO_PORT GPIOA -#define LED2_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() -#define LED2_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() - - -#define LED1_PIN GPIO_PIN_4 -#define LED1_GPIO_PORT GPIOB -#define LED1_GPIO_CLK RCC_AHBPeriph_GPIOB - -#define LED3_PIN GPIO_PIN_14 -#define LED3_GPIO_PORT GPIOB -#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOB - -#define LED4_PIN GPIO_PIN_14 -#define LED4_GPIO_PORT GPIOB -#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOB - -#define LED5_PIN GPIO_PIN_14 -#define LED5_GPIO_PORT GPIOB -#define LED5_GPIO_CLK RCC_AHBPeriph_GPIOB - -#define LEDx_GPIO_CLK_ENABLE(__INDEX__) (LED2_GPIO_CLK_ENABLE()) - -#define LEDx_GPIO_CLK_DISABLE(__INDEX__) (LED2_GPIO_CLK_DISABLE()) - -/** - * @} - */ - -/** @defgroup STM32L1XX_NUCLEO_BUTTON BUTTON Constants - * @{ - */ -#define BUTTONn 1 - -/** - * @brief Key push-button - */ -#define USER_BUTTON_PIN GPIO_PIN_13 -#define USER_BUTTON_GPIO_PORT GPIOC -#define USER_BUTTON_GPIO_CLK_ENABLE() __GPIOC_CLK_ENABLE() -#define USER_BUTTON_GPIO_CLK_DISABLE() __GPIOC_CLK_DISABLE() -#define USER_BUTTON_EXTI_IRQn EXTI15_10_IRQn - -#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) (USER_BUTTON_GPIO_CLK_ENABLE()) - -#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) (USER_BUTTON_GPIO_CLK_DISABLE()) -/** - * @} - */ - -/** @addtogroup STM32L1XX_NUCLEO_BUS BUS Constants - * @{ - */ -/*###################### SPI1 ###################################*/ -#define NUCLEO_SPIx SPI1 -#define NUCLEO_SPIx_CLK_ENABLE() __SPI1_CLK_ENABLE() - -#define NUCLEO_SPIx_SCK_AF GPIO_AF5_SPI1 -#define NUCLEO_SPIx_SCK_GPIO_PORT GPIOA -#define NUCLEO_SPIx_SCK_PIN GPIO_PIN_5 -#define NUCLEO_SPIx_SCK_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() -#define NUCLEO_SPIx_SCK_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() - -#define NUCLEO_SPIx_MISO_MOSI_AF GPIO_AF5_SPI1 -#define NUCLEO_SPIx_MISO_MOSI_GPIO_PORT GPIOA -#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() -#define NUCLEO_SPIx_MISO_MOSI_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() -#define NUCLEO_SPIx_MISO_PIN GPIO_PIN_6 -#define NUCLEO_SPIx_MOSI_PIN GPIO_PIN_7 -/* Maximum Timeout values for flags waiting loops. These timeouts are not based - on accurate values, they just guarantee that the application will not remain - stuck if the SPI communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define NUCLEO_SPIx_TIMEOUT_MAX 1000 - -#define NUCLEO_I2C_SHIELDS_EV_IRQn I2C1_EV_IRQn -/** - * @brief SD Control Lines management - */ -#define SD_CS_LOW() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_RESET) -#define SD_CS_HIGH() HAL_GPIO_WritePin(SD_CS_GPIO_PORT, SD_CS_PIN, GPIO_PIN_SET) - -/** - * @brief LCD Control Lines management - */ -#define LCD_CS_LOW() HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_RESET) -#define LCD_CS_HIGH() HAL_GPIO_WritePin(LCD_CS_GPIO_PORT, LCD_CS_PIN, GPIO_PIN_SET) -#define LCD_DC_LOW() HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_RESET) -#define LCD_DC_HIGH() HAL_GPIO_WritePin(LCD_DC_GPIO_PORT, LCD_DC_PIN, GPIO_PIN_SET) - -/** - * @brief SD Control Interface pins - */ -#define SD_CS_PIN GPIO_PIN_5 -#define SD_CS_GPIO_PORT GPIOB -#define SD_CS_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -#define SD_CS_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() - -/** - * @brief LCD Control Interface pins - */ -#define LCD_CS_PIN GPIO_PIN_6 -#define LCD_CS_GPIO_PORT GPIOB -#define LCD_CS_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -#define LCD_CS_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() - -/** - * @brief LCD Data/Command Interface pins - */ -#define LCD_DC_PIN GPIO_PIN_9 -#define LCD_DC_GPIO_PORT GPIOA -#define LCD_DC_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() -#define LCD_DC_GPIO_CLK_DISABLE() __GPIOA_CLK_DISABLE() - -/*##################### ADC1 ###################################*/ -/** - * @brief ADC Interface pins - * used to detect motion of Joystick available on Adafruit 1.8" TFT shield - */ -#define NUCLEO_ADCx ADC1 -#define NUCLEO_ADCx_CLK_ENABLE() __ADC1_CLK_ENABLE() - -#define NUCLEO_ADCx_GPIO_PORT GPIOB -#define NUCLEO_ADCx_GPIO_PIN GPIO_PIN_0 -#define NUCLEO_ADCx_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -#define NUCLEO_ADCx_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() - - -/** @defgroup STM32L1XX_NUCLEO_Exported_Functions - * @{ - */ -uint32_t BSP_GetVersion(void); -/** @addtogroup STM32L1XX_NUCLEO_LED_Functions - * @{ - */ - -void BSP_LED_Init(Led_TypeDef Led); -void BSP_LED_On(Led_TypeDef Led); -void BSP_LED_Off(Led_TypeDef Led); -void BSP_LED_Toggle(Led_TypeDef Led); - -/** - * @} - */ - -/** @addtogroup STM32L1XX_NUCLEO_BUTTON_Functions - * @{ - */ - -void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); -uint32_t BSP_PB_GetState(Button_TypeDef Button); - -#ifdef HAL_ADC_MODULE_ENABLED -uint8_t BSP_JOY_Init(void); -JOYState_TypeDef BSP_JOY_GetState(void); -#endif /* HAL_ADC_MODULE_ENABLED */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1XX_NUCLEO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/Release_Notes.html deleted file mode 100644 index 25cf4ea92..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/Release_Notes.html +++ /dev/null @@ -1,171 +0,0 @@ - - - - - -Release Notes for X-NUCLEO-IDS02Ax(x=3,4,5) STM Shield - - - - - -
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Release -Notes for X-NUCLEO-IDS02Ax(x=3,4,5) STM Shield

-

Copyright -2014 STMicroelectronics

-

-
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- - - - - - -
- - -

Update History

- -

V1.0.0/ 10-Oct-2014

-

Main -Changes

- - - - - - - - - -
    -
  • First -official release.
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License
-

-
Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
    -
  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
    2. -
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
    3. -
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived
    -
    4. -
-       -from this software without specific prior written permission.
-
-THIS -SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGE.
-

- -
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For -complete documentation on SPIRIT1 Shields -visit www.st.com/STM32

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-
- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.c deleted file mode 100644 index c499372c3..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.c +++ /dev/null @@ -1,353 +0,0 @@ -/** -****************************************************************************** -* @file radio_gpio.c -* @author System Lab - NOIDA -* @version V1.0.0 -* @date 15-May-2014 -* @brief This file provides code for the configuration of all used GPIO pins - for Radio inetrface. -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "radio_gpio.h" - -/** - * @addtogroup BSP - * @{ - */ - - -/** - * @addtogroup X-NUCLEO-IDS02Ax - * @{ - */ - - -/** - * @defgroup Radio_Gpio_Private_TypesDefinitions Radio_Gpio Private Types Definitions - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Radio_Gpio_Private_Defines Radio_Gpio Private Defines - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Radio_Gpio_Private_Macros Radio_Gpio Private Macros - * @{ - */ -#define POR_TIME ((uint16_t)0x1E00) - -/** - * @} - */ - - -/** - * @defgroup Radio_Gpio_Private_Variables Radio_Gpio Private Variables - * @{ - */ - -/** -* @brief Radio_Gpio Port array -*/ -GPIO_TypeDef* aRADIO_GPIO_PORT[RADIO_GPIO_NUMBER] = { - RADIO_GPIO_0_PORT, - RADIO_GPIO_1_PORT, - RADIO_GPIO_2_PORT, - RADIO_GPIO_3_PORT, - RADIO_GPIO_SDN_PORT -}; - - -/** -* @brief Radio_Gpio Pin array -*/ -static const uint16_t aRADIO_GPIO_PIN[RADIO_GPIO_NUMBER] = { - RADIO_GPIO_0_PIN, - RADIO_GPIO_1_PIN, - RADIO_GPIO_2_PIN, - RADIO_GPIO_3_PIN, - RADIO_GPIO_SDN_PIN -}; - - -/** -* @brief Radio_Gpio Speed array -*/ -static const uint32_t aRADIO_GPIO_SPEED[RADIO_GPIO_NUMBER] = { - RADIO_GPIO_0_SPEED, - RADIO_GPIO_1_SPEED, - RADIO_GPIO_2_SPEED, - RADIO_GPIO_3_SPEED, - RADIO_GPIO_SDN_SPEED -}; - - -/** -* @brief Radio_Gpio PuPd array -*/ -static const uint32_t aRADIO_GPIO_PUPD[RADIO_GPIO_NUMBER] = { - RADIO_GPIO_0_PUPD, - RADIO_GPIO_1_PUPD, - RADIO_GPIO_2_PUPD, - RADIO_GPIO_3_PUPD, - RADIO_GPIO_SDN_PUPD -}; - - -/** -* @brief Exti Mode array -*/ -static const uint32_t aRADIO_GPIO_EXTI_MODE[RADIO_GPIO_NUMBER-1] = { - RADIO_GPIO_0_EXTI_MODE, - RADIO_GPIO_1_EXTI_MODE, - RADIO_GPIO_2_EXTI_MODE, - RADIO_GPIO_3_EXTI_MODE -}; - - -/** -* @brief Exti IRQn array -*/ -static const uint8_t aRADIO_GPIO_IRQn[RADIO_GPIO_NUMBER-1] = { - RADIO_GPIO_0_EXTI_IRQN, - RADIO_GPIO_1_EXTI_IRQN, - RADIO_GPIO_2_EXTI_IRQN, - RADIO_GPIO_3_EXTI_IRQN -}; - - -/** - * @} - */ - - -/** - * @defgroup Radio_Gpio_Private_FunctionPrototypes Radio_Gpio Private Function Prototypes - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup Radio_Gpio_Private_Functions Radio_Gpio Private Functions - * @{ - */ - - -/** -* @brief Configures MCU GPIO and EXTI Line for GPIOs. -* @param xGpio Specifies the GPIO to be configured. -* This parameter can be one of following parameters: -* @arg GPIO_0 -* @arg GPIO_1 -* @arg GPIO_2 -* @arg GPIO_3 -* @param xGpioMode Specifies GPIO mode. -* This parameter can be one of following parameters: -* @arg RADIO_MODE_GPIO_IN: MCU GPIO will be used as simple input. -* @argRADIO_MODE_GPIO_OUT: MCU GPIO will be used as simple output. -* @arg RADIO_MODE_EXTI_IN: MCU GPIO will be connected to EXTI line with interrupt -* generation capability. -* @retval None. -*/ -void RadioGpioInit(RadioGpioPin xGpio, RadioGpioMode xGpioMode) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /* Check the parameters */ - assert_param(IS_RADIO_GPIO_PIN(xGpio)); - assert_param(IS_RADIO_GPIO_MODE(xGpioMode)); - - /* GPIO Ports Clock Enable */ - __GPIOA_CLK_ENABLE(); - __GPIOC_CLK_ENABLE(); - __GPIOB_CLK_ENABLE(); - - /* Configures MCU GPIO */ - if (xGpioMode == RADIO_MODE_GPIO_OUT) - { - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - } - else - { - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - } - - GPIO_InitStruct.Pin = aRADIO_GPIO_PIN[xGpio]; - GPIO_InitStruct.Pull = aRADIO_GPIO_PUPD[xGpio]; - GPIO_InitStruct.Speed = aRADIO_GPIO_SPEED[xGpio]; - HAL_GPIO_Init(aRADIO_GPIO_PORT[xGpio], &GPIO_InitStruct); - - if (xGpioMode == RADIO_MODE_EXTI_IN) - { - GPIO_InitStruct.Pin = aRADIO_GPIO_PIN[xGpio]; - GPIO_InitStruct.Pull = aRADIO_GPIO_PUPD[xGpio]; - GPIO_InitStruct.Speed = aRADIO_GPIO_SPEED[xGpio]; - GPIO_InitStruct.Mode = aRADIO_GPIO_EXTI_MODE[xGpio]; - HAL_GPIO_Init(aRADIO_GPIO_PORT[xGpio], &GPIO_InitStruct); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - /* NVIC_SetPriority((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio]), 0x02); */ - /* HAL_NVIC_EnableIRQ((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio])); */ - } -} - - -/** -* @brief Enables or disables the interrupt on GPIO . -* @param xGpio Specifies the GPIO whose priority shall be changed. -* This parameter can be one of following parameters: -* @arg GPIO_0 -* @arg GPIO_1 -* @arg GPIO_2 -* @arg GPIO_3 -* @param nPreemption Specifies Preemption Priority. -* @param nSubpriority Specifies Subgroup Priority. -* @param xNewState Specifies the State. -* This parameter can be one of following parameters: -* @arg ENABLE: Interrupt is enabled -* @arg DISABLE: Interrupt is disabled -* @retval None. -*/ -void RadioGpioInterruptCmd(RadioGpioPin xGpio, uint8_t nPreemption, uint8_t nSubpriority, FunctionalState xNewState) -{ - HAL_NVIC_SetPriority((IRQn_Type) (aRADIO_GPIO_IRQn[xGpio]), nPreemption, nSubpriority); - if (!xNewState) - { - HAL_NVIC_DisableIRQ((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio])); - } - else - { - HAL_NVIC_EnableIRQ((IRQn_Type)(aRADIO_GPIO_IRQn[xGpio])); - } -} - - -/** -* @brief Returns the level of a specified GPIO. -* @param xGpio Specifies the GPIO to be read. -* This parameter can be one of following parameters: -* @arg GPIO_0 -* @arg GPIO_1 -* @arg GPIO_2 -* @arg GPIO_3 -* @retval FlagStatus Level of the GPIO. This parameter can be: -* SET or RESET. -*/ -FlagStatus RadioGpioGetLevel(RadioGpioPin xGpio) -{ - /* Gets the GPIO level */ - uint16_t nDataPort = HAL_GPIO_ReadPin(aRADIO_GPIO_PORT[xGpio], aRADIO_GPIO_PIN[xGpio]); - if (nDataPort & aRADIO_GPIO_PIN[xGpio]) - { - return SET; - } - else - { - return RESET; - } -} - - -/** -* @brief Sets the level of a specified GPIO. -* @param xGpio Specifies the GPIO to be set. -* This parameter can be one of following parameters: -* @arg GPIO_0 -* @arg GPIO_1 -* @arg GPIO_2 -* @arg GPIO_3 -* @param GPIO_PinState Level of the GPIO. This parameter can be: -* GPIO_PIN_SET or GPIO_PIN_RESET. -* @retval None. -*/ -void RadioGpioSetLevel(RadioGpioPin xGpio, GPIO_PinState xState) -{ - /* Sets the GPIO level */ - HAL_GPIO_WritePin(aRADIO_GPIO_PORT[xGpio], aRADIO_GPIO_PIN[xGpio], xState); -} - - -/** -* @brief Puts at logic 1 the SDN pin. -* @param None. -* @retval None. -*/ -void SdkEvalEnterShutdown(void) -{ - /* Puts high the GPIO connected to shutdown pin */ - /* Check the parameters */ - RadioGpioSetLevel(RADIO_GPIO_SDN, GPIO_PIN_SET); -} - - -/** -* @brief Put at logic 0 the SDN pin. -* @param None. -* @retval None. -*/ -void SdkEvalExitShutdown(void) -{ - /* Puts low the GPIO connected to shutdown pin */ - RadioGpioSetLevel(RADIO_GPIO_SDN, GPIO_PIN_RESET); - - /* Delay to allow the circuit POR, about 700 us */ - for (volatile uint32_t Index = 0; Index < POR_TIME; Index++); -} - - -/** -* @brief check the logic(0 or 1) at the SDN pin. -* @param None. -* @retval FlagStatus. -*/ -SpiritFlagStatus SdkEvalCheckShutdown(void) -{ - return RadioGpioGetLevel(RADIO_GPIO_SDN); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.h deleted file mode 100644 index 1af00edb7..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_gpio.h +++ /dev/null @@ -1,218 +0,0 @@ -/** -****************************************************************************** -* @file radio_gpio.h -* @author System Lab - NOIDA -* @version V1.0.0 -* @date 15-May-2014 -* @brief This file contains all the functions prototypes for the gpio -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported Variables ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __RADIO_GPIO_H -#define __RADIO_GPIO_H -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" -#include "SPIRIT_Types.h" - -/** - * @addtogroup BSP - * @{ - */ - - -/* Exported types ------------------------------------------------------------*/ - /* MCU GPIO pin working mode for GPIO */ -typedef enum -{ - RADIO_MODE_GPIO_IN = 0x00, /*!< Work as GPIO input */ - RADIO_MODE_EXTI_IN, /*!< Work as EXTI */ - RADIO_MODE_GPIO_OUT, /*!< Work as GPIO output */ -}RadioGpioMode; - - /* MCU GPIO pin enumeration for GPIO */ -typedef enum -{ - RADIO_GPIO_0 = 0x00, /*!< GPIO_0 selected */ - RADIO_GPIO_1 = 0x01, /*!< GPIO_1 selected */ - RADIO_GPIO_2 = 0x02, /*!< GPIO_2 selected */ - RADIO_GPIO_3 = 0x03, /*!< GPIO_3 selected */ - RADIO_GPIO_SDN = 0x04, /*!< GPIO_SDN selected */ -} -RadioGpioPin; - - -/* Exported constants --------------------------------------------------------*/ - - -/* Exported macro ------------------------------------------------------------*/ - /* MCU GPIO pin working mode for GPIO */ -#define IS_RADIO_GPIO_MODE(MODE) (((MODE) == RADIO_MODE_GPIO_IN) || \ - ((MODE) == RADIO_MODE_EXTI_IN) || \ - ((MODE) == RADIO_MODE_GPIO_OUT)) - -/* Number of Arduino pins used for RADIO GPIO interface */ -#define RADIO_GPIO_NUMBER ((uint8_t)5) - -/* MCU GPIO pin enumeration for GPIO */ -#define IS_RADIO_GPIO_PIN(PIN) (((PIN) == RADIO_GPIO_0) || \ - ((PIN) == RADIO_GPIO_1) || \ - ((PIN) == RADIO_GPIO_2) || \ - ((PIN) == RADIO_GPIO_3) || \ - ((PIN) == RADIO_GPIO_SDN)) - -/* Define for RADIO board */ -#if !defined (USE_SPIRIT1_DEFAULT) - #define USE_SPIRIT1_DEFAULT -#endif - -/* @defgroup Radio_Gpio_config_Define */ -/*NOTE: GPIO0, GPIO1, GPIO2 of SPIRIT1 is not used in the shield*/ - -#define RADIO_GPIO_0_PORT GPIOC -#define RADIO_GPIO_0_PIN GPIO_PIN_1 -#define RADIO_GPIO_0_CLOCK_ENABLE() __GPIOC_CLK_ENABLE() -#define RADIO_GPIO_0_CLOCK_DISABLE() __GPIOC_CLK_ENABLE() -#define RADIO_GPIO_0_SPEED GPIO_SPEED_HIGH -#define RADIO_GPIO_0_PUPD GPIO_NOPULL -#define RADIO_GPIO_0_EXTI_LINE GPIO_PIN_1 -#define RADIO_GPIO_0_EXTI_MODE GPIO_MODE_IT_FALLING -#define RADIO_GPIO_0_EXTI_IRQN EXTI1_IRQn -#define RADIO_GPIO_0_EXTI_PREEMPTION_PRIORITY 2 -#define RADIO_GPIO_0_EXTI_SUB_PRIORITY 2 -#define RADIO_GPIO_0_EXTI_IRQ_HANDLER EXTI1_IRQHandler - -#define RADIO_GPIO_1_PORT GPIOB -#define RADIO_GPIO_1_PIN GPIO_PIN_0 -#define RADIO_GPIO_1_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() -#define RADIO_GPIO_1_CLOCK_DISABLE() __GPIOB_CLK_ENABLE() -#define RADIO_GPIO_1_SPEED GPIO_SPEED_HIGH -#define RADIO_GPIO_1_PUPD GPIO_NOPULL -#define RADIO_GPIO_1_EXTI_LINE GPIO_PIN_0 -#define RADIO_GPIO_1_EXTI_MODE GPIO_MODE_IT_FALLING -#define RADIO_GPIO_1_EXTI_IRQN EXTI0_IRQn -#define RADIO_GPIO_1_EXTI_PREEMPTION_PRIORITY 2 -#define RADIO_GPIO_1_EXTI_SUB_PRIORITY 2 -#define RADIO_GPIO_1_EXTI_IRQ_HANDLER EXTI0_IRQHandler - -#define RADIO_GPIO_2_PORT GPIOA -#define RADIO_GPIO_2_PIN GPIO_PIN_4 -#define RADIO_GPIO_2_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() -#define RADIO_GPIO_2_CLOCK_DISABLE() __GPIOA_CLK_ENABLE() -#define RADIO_GPIO_2_SPEED GPIO_SPEED_HIGH -#define RADIO_GPIO_2_PUPD GPIO_NOPULL -#define RADIO_GPIO_2_EXTI_LINE GPIO_PIN_4 -#define RADIO_GPIO_2_EXTI_MODE GPIO_MODE_IT_FALLING -#define RADIO_GPIO_2_EXTI_IRQN EXTI4_IRQn -#define RADIO_GPIO_2_EXTI_PREEMPTION_PRIORITY 2 -#define RADIO_GPIO_2_EXTI_SUB_PRIORITY 2 -#define RADIO_GPIO_2_EXTI_IRQ_HANDLER EXTI4_IRQHandler - - -#if defined (USE_SPIRIT1_DEFAULT) - - -#define RADIO_GPIO_3_PORT GPIOC -#define RADIO_GPIO_3_PIN GPIO_PIN_7 -#define RADIO_GPIO_3_CLOCK_ENABLE() __GPIOC_CLK_ENABLE() -#define RADIO_GPIO_3_CLOCK_DISABLE() __GPIOC_CLK_DISABLE() -#define RADIO_GPIO_3_SPEED GPIO_SPEED_HIGH -#define RADIO_GPIO_3_PUPD GPIO_NOPULL -#define RADIO_GPIO_3_EXTI_LINE GPIO_PIN_7 -#define RADIO_GPIO_3_EXTI_MODE GPIO_MODE_IT_FALLING -#define RADIO_GPIO_3_EXTI_IRQN EXTI9_5_IRQn -#define RADIO_GPIO_3_EXTI_PREEMPTION_PRIORITY 2 -#define RADIO_GPIO_3_EXTI_SUB_PRIORITY 2 -#define RADIO_GPIO_3_EXTI_IRQ_HANDLER EXTI9_5_IRQHandler - -#else - -#define RADIO_GPIO_3_PORT GPIOA -#define RADIO_GPIO_3_PIN GPIO_PIN_0 -#define RADIO_GPIO_3_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() -#define RADIO_GPIO_3_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() -#define RADIO_GPIO_3_SPEED GPIO_SPEED_HIGH -#define RADIO_GPIO_3_PUPD GPIO_NOPULL -#define RADIO_GPIO_3_EXTI_LINE GPIO_PIN_0 -#define RADIO_GPIO_3_EXTI_MODE GPIO_MODE_IT_FALLING -#define RADIO_GPIO_3_EXTI_IRQN EXTI0_IRQn -#define RADIO_GPIO_3_EXTI_PREEMPTION_PRIORITY 2 -#define RADIO_GPIO_3_EXTI_SUB_PRIORITY 2 -#define RADIO_GPIO_3_EXTI_IRQ_HANDLER EXTI0_IRQHandler - -#endif - -#define RADIO_GPIO_SDN_PORT GPIOA -#define RADIO_GPIO_SDN_PIN GPIO_PIN_10 -#define RADIO_GPIO_SDN_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() -#define RADIO_GPIO_SDN_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() -#define RADIO_GPIO_SDN_SPEED GPIO_SPEED_HIGH -#define RADIO_GPIO_SDN_PUPD GPIO_PULLUP - - -#define RADIO_GPIO_IRQ RADIO_GPIO_3 -#define SPIRIT_GPIO_IRQ SPIRIT_GPIO_3 - -/* Exported Variables ------------------------------------------------------------*/ - - -/* Exported functions ------------------------------------------------------- */ -FlagStatus RadioGpioGetLevel(RadioGpioPin xGpio); -void RadioGpioSetLevel(RadioGpioPin xGpio, GPIO_PinState xState); -void SdkEvalEnterShutdown(void); -void SdkEvalExitShutdown(void); -SpiritFlagStatus SdkEvalCheckShutdown(void); -void RadioGpioInit(RadioGpioPin xGpio, RadioGpioMode xGpioMode); -void RadioGpioInterruptCmd(RadioGpioPin xGpio, uint8_t nPreemption, uint8_t nSubpriority, FunctionalState xNewState); - - -#ifdef __cplusplus -} -#endif -#endif /*__RADIO_GPIO_H */ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.c deleted file mode 100644 index 96d0983d1..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.c +++ /dev/null @@ -1,139 +0,0 @@ -/** -****************************************************************************** -* @file radio_shield_config.c -* @author System Lab - NOIDA -* @version V1.0.0 -* @date 15-May-2014 -* @brief This file provides set of firmware functions to manage: -* - LEDs and push-button available on radio Shield -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "radio_shield_config.h" - -/** @addtogroup BSP -* @{ -*/ - -/** @addtogroup RADIO_SHILED -* @{ -*/ - - -/** @addtogroup RADIO_SHILED_LOW_LEVEL -* @brief This file provides set of firmware functions to manage -* manage Leds and push-button available on Radio shield. -* @{ -*/ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -GPIO_TypeDef* aLED_GPIO_PORT[RADIO_SHIELD_LEDn] = {RADIO_SHIELD_LED_GPIO_PORT}; -const uint16_t aLED_GPIO_PIN[RADIO_SHIELD_LEDn] = {RADIO_SHIELD_LED_GPIO_PIN}; - -/* Private function prototypes -----------------------------------------------*/ -void RadioShieldLedOn(Led_t Led); -void Spirit1_LED_Toggle(Led_t Led); -void Spirit1_LED_Off(Led_t Led); -void RadioShieldLedInit(Led_t Led); -void RadioShieldLedOff(Led_t Led); -void RadioShieldLedToggle(Led_t Led); - -/* Private functions ---------------------------------------------------------*/ - - -/** -* @brief Configures LED GPIO. -* @param Led: LED to be configured. -* This parameter can be one of the following values: -* @arg Led_t Led -* @retval None -*/ -void RadioShieldLedInit(Led_t Led) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /* Enable the GPIO_LED Clock */ - __GPIOB_CLK_ENABLE(); - - /* Configure the GPIO_LED pin */ - GPIO_InitStruct.Pin = aLED_GPIO_PIN[Led]; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_MEDIUM; - - HAL_GPIO_Init(aLED_GPIO_PORT[Led], &GPIO_InitStruct); -} - - -/** -* @brief Turns selected LED On. -* @param Led: Specifies the Led to be set on. -* This parameter can be one of following parameters: -* @arg Led_t Led -* @retval None -*/ -void RadioShieldLedOn(Led_t Led) -{ - HAL_GPIO_WritePin(aLED_GPIO_PORT[Led], aLED_GPIO_PIN[Led], GPIO_PIN_SET); -} - - -/** -* @brief Turns selected LED Off. -* @param Led: Specifies the Led to be set off. -* This parameter can be one of following parameters: -* @arg Led_t Led -* @retval None -*/ -void RadioShieldLedOff(Led_t Led) -{ - HAL_GPIO_WritePin(aLED_GPIO_PORT[Led], aLED_GPIO_PIN[Led], GPIO_PIN_RESET); -} - - -/** -* @brief Toggles the selected LED. -* @param Led: Specifies the Led to be toggled. -* This parameter can be one of following parameters: -* @arg Led_t Led -* @retval None -*/ -void RadioShieldLedToggle(Led_t Led) -{ - HAL_GPIO_TogglePin(aLED_GPIO_PORT[Led], aLED_GPIO_PIN[Led]); -} - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.h deleted file mode 100644 index 7fd44474a..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_shield_config.h +++ /dev/null @@ -1,114 +0,0 @@ -/** -****************************************************************************** -* @file radio_shield_config.h -* @author System Lab - NOIDA -* @version V1.0.0 -* @date 15-May-2014 -* @brief This file contains definitions for: -* - LEDs and push-button available on RF shields -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __RADIO_SHIELD_CONFIG_H -#define __RADIO_SHIELD_CONFIG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X-NUCLEO-IDS02Ax - * @{ - */ - -/** @addtogroup RADIO_SHILED_LOW_LEVEL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef enum -{ - RADIO_SHIELD_LED = 0 -} Led_t; - - - -/* Exported constants --------------------------------------------------------*/ - - -/* Exported macro ------------------------------------------------------------*/ - /** @addtogroup RF_SHIELD_CONFIG_LOW_LEVEL_LED - * @{ - */ -#define RADIO_SHIELD_LEDn ((uint8_t)1) - -#define RADIO_SHIELD_LED_GPIO_PIN GPIO_PIN_4 /*Rx Indicator LED*/ -#define RADIO_SHIELD_LED_GPIO_PORT GPIOB -#define RADIO_SHIELD_LED_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -#define RADIO_SHIELD_LED_GPIO_CLK_DISABLE() __GPIOB_CLK_DISABLE() - - -/* Exported Variables ------------------------------------------------------------*/ - - -/* Exported functions ------------------------------------------------------- */ -void RadioShieldLedInit(Led_t Led); -void RadioShieldLedOn(Led_t Led); -void RadioShieldLedOff(Led_t Led); -void RadioShieldLedToggle(Led_t Led); - - - -#ifdef __cplusplus -} -#endif - -#endif /* __RADIO_SHIELD_CONFIG_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.c deleted file mode 100644 index dd6c1f34b..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.c +++ /dev/null @@ -1,482 +0,0 @@ -/** -****************************************************************************** -* @file radio_spi.c -* @author System Lab - NOIDA -* @version V1.0.0 -* @date 15-May-2014 -* @brief This file provides code for the configuration of the SPI instances. -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ - - -/* Includes ------------------------------------------------------------------*/ -#include "radio_spi.h" - -/** - * @addtogroup BSP - * @{ - */ - - -/** - * @addtogroup X-NUCLEO-IDS02Ax - * @{ - */ - - -/** - * @defgroup RADIO_SPI_Private_TypesDefinitions RADIO_SPI Private Types Definitions - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup RADIO_SPI_Private_Defines RADIO_SPI Private Defines - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup RADIO_SPI_Private_Macros RADIO_SPI Private Macros - * @{ - */ - -/** - * @} - */ - - -/** - * @defgroup RADIO_SPI_Private_Variables RADIO_SPI Private Variables - * @{ - */ -SPI_HandleTypeDef pSpiHandle; -uint32_t SpiTimeout = RADIO_SPI_TIMEOUT_MAX; /*Instance==RADIO_SPI) - { - /*** Configure the GPIOs ***/ - /* Enable GPIO clock */ - RADIO_SPI_SCK_CLOCK_ENABLE(); - RADIO_SPI_MISO_CLOCK_ENABLE(); - RADIO_SPI_MOSI_CLOCK_ENABLE(); - - /**SPI1 GPIO Configuration */ - - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; - - GPIO_InitStruct.Pin = RADIO_SPI_SCK_PIN; - HAL_GPIO_Init(RADIO_SPI_SCK_PORT, &GPIO_InitStruct); - - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; - - GPIO_InitStruct.Pin = RADIO_SPI_MISO_PIN; - HAL_GPIO_Init(RADIO_SPI_MISO_PORT, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = RADIO_SPI_MOSI_PIN; - HAL_GPIO_Init(RADIO_SPI_MOSI_PORT, &GPIO_InitStruct); - - RADIO_SPI_CS_CLOCK_ENABLE(); - - /* Configure SPI pin: CS */ - GPIO_InitStruct.Pin = RADIO_SPI_CS_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - HAL_GPIO_Init(RADIO_SPI_CS_PORT, &GPIO_InitStruct); - - RADIO_SPI_CLK_ENABLE(); - } -} - -/** -* @} -*/ - - -/** - * @brief SPI Write a byte to device - * @param Value: value to be written - * @retval None - */ -static void SPI_Write(uint8_t Value) -{ - HAL_StatusTypeDef status = HAL_OK; - - while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); - status = HAL_SPI_Transmit(&pSpiHandle, (uint8_t*) &Value, 1, SpiTimeout); - - /* Check the communication status */ - if (status != HAL_OK) - { - /* Execute user timeout callback */ - SPI_Error(); - } -} - - -/** - * @brief SPI error treatment function - * @param None - * @retval None - */ -static void SPI_Error(void) -{ - /* De-initialize the SPI communication BUS */ - HAL_SPI_DeInit(&pSpiHandle); - - /* Re-Initiaize the SPI communication BUS */ - SdkEvalSpiInit(); -} - - -/** -* @brief Write single or multiple RF Transceivers register -* @param cRegAddress: base register's address to be write -* @param cNbBytes: number of registers and bytes to be write -* @param pcBuffer: pointer to the buffer of values have to be written into registers -* @retval StatusBytes -*/ -StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer) -{ - uint8_t aHeader[2] = {0}; - uint16_t tmpstatus = 0x0000; - StatusBytes *pStatus=(StatusBytes *)&tmpstatus; - - /* Built the aHeader bytes */ - aHeader[0] = WRITE_HEADER; - aHeader[1] = cRegAddress; - - SPI_ENTER_CRITICAL(); - - /* Puts the SPI chip select low to start the transaction */ - RadioSpiCSLow(); - - for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&(tmpstatus), 1, SpiTimeout); - tmpstatus = tmpstatus << 8; - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); - - /* Writes the registers according to the number of bytes */ - for (int index = 0; index < cNbBytes; index++) - { - SPI_Write(pcBuffer[index]); - } - - /* To be sure to don't rise the Chip Select before the end of last sending */ - while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); - /* Puts the SPI chip select high to end the transaction */ - RadioSpiCSHigh(); - - SPI_EXIT_CRITICAL(); - - return *pStatus; - - -} - - -/** -* @brief Read single or multiple SPIRIT1 register -* @param cRegAddress: base register's address to be read -* @param cNbBytes: number of registers and bytes to be read -* @param pcBuffer: pointer to the buffer of registers' values read -* @retval StatusBytes -*/ -StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer) -{ - uint16_t tmpstatus = 0x00; - StatusBytes *pStatus = (StatusBytes *)&tmpstatus; - - uint8_t aHeader[2] = {0}; - uint8_t dummy = 0xFF; - - /* Built the aHeader bytes */ - aHeader[0] = READ_HEADER; - aHeader[1] = cRegAddress; - - SPI_ENTER_CRITICAL(); - - /* Put the SPI chip select low to start the transaction */ - RadioSpiCSLow(); - - for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&(tmpstatus), 1, SpiTimeout); - tmpstatus = tmpstatus << 8; - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); - - for (int index = 0; index < cNbBytes; index++) - { - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&dummy, (uint8_t *)&(pcBuffer)[index], 1, SpiTimeout); - } - - /* To be sure to don't rise the Chip Select before the end of last sending */ - while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); - - /* Put the SPI chip select high to end the transaction */ - RadioSpiCSHigh(); - - SPI_EXIT_CRITICAL(); - - return *pStatus; - -} - - -/** -* @brief Send a command -* @param cCommandCode: command code to be sent -* @retval StatusBytes -*/ -StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode) -{ - uint8_t aHeader[2] = {0}; - uint16_t tmpstatus = 0x0000; - - StatusBytes *pStatus = (StatusBytes *)&tmpstatus; - - - /* Built the aHeader bytes */ - aHeader[0] = COMMAND_HEADER; - aHeader[1] = cCommandCode; - - SPI_ENTER_CRITICAL(); - - /* Puts the SPI chip select low to start the transaction */ - RadioSpiCSLow(); - - for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&tmpstatus, 1, SpiTimeout); - tmpstatus = tmpstatus<<8; - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); - - /* To be sure to don't rise the Chip Select before the end of last sending */ - while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); - - /* Puts the SPI chip select high to end the transaction */ - RadioSpiCSHigh(); - - SPI_EXIT_CRITICAL(); - - return *pStatus; - -} - - -/** -* @brief Write data into TX FIFO -* @param cNbBytes: number of bytes to be written into TX FIFO -* @param pcBuffer: pointer to data to write -* @retval StatusBytes -*/ -StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer) -{ - uint16_t tmpstatus = 0x0000; - StatusBytes *pStatus = (StatusBytes *)&tmpstatus; - - uint8_t aHeader[2] = {0}; - - /* Built the aHeader bytes */ - aHeader[0] = WRITE_HEADER; - aHeader[1] = LINEAR_FIFO_ADDRESS; - - SPI_ENTER_CRITICAL(); - - /* Put the SPI chip select low to start the transaction */ - RadioSpiCSLow(); - - for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&tmpstatus, 1, SpiTimeout); - tmpstatus = tmpstatus<<8; - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); - - /* Writes the registers according to the number of bytes */ - for (int index = 0; index < cNbBytes; index++) - { - SPI_Write(pcBuffer[index]); - } - - /* To be sure to don't rise the Chip Select before the end of last sending */ - while (__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); - - /* Put the SPI chip select high to end the transaction */ - RadioSpiCSHigh(); - - SPI_EXIT_CRITICAL(); - - return *pStatus; -} - -/** -* @brief Read data from RX FIFO -* @param cNbBytes: number of bytes to read from RX FIFO -* @param pcBuffer: pointer to data read from RX FIFO -* @retval StatusBytes -*/ -StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer) -{ - uint16_t tmpstatus = 0x0000; - StatusBytes *pStatus = (StatusBytes *)&tmpstatus; - - uint8_t aHeader[2]; - uint8_t dummy=0xFF; - - /* Built the aHeader bytes */ - aHeader[0]=READ_HEADER; - aHeader[1]=LINEAR_FIFO_ADDRESS; - - SPI_ENTER_CRITICAL(); - - /* Put the SPI chip select low to start the transaction */ - RadioSpiCSLow(); - - for (volatile uint16_t Index = 0; Index < CS_TO_SCLK_DELAY; Index++); - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[0], (uint8_t *)&tmpstatus, 1, SpiTimeout); - tmpstatus = tmpstatus<<8; - - /* Write the aHeader bytes and read the SPIRIT1 status bytes */ - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&aHeader[1], (uint8_t *)&tmpstatus, 1, SpiTimeout); - - for (int index = 0; index < cNbBytes; index++) - { - HAL_SPI_TransmitReceive(&pSpiHandle, (uint8_t *)&dummy, (uint8_t *)&pcBuffer[index], 1, SpiTimeout); - } - - /* To be sure to don't rise the Chip Select before the end of last sending */ - while(__HAL_SPI_GET_FLAG(&pSpiHandle, SPI_FLAG_TXE) == RESET); - - /* Put the SPI chip select high to end the transaction */ - RadioSpiCSHigh(); - - SPI_EXIT_CRITICAL(); - - return *pStatus; -} - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.h deleted file mode 100644 index 9073f50f6..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/radio_spi.h +++ /dev/null @@ -1,177 +0,0 @@ -/** -****************************************************************************** -* @file radio_spi.h -* @author System Lab - NOIDA -* @version V1.0.0 -* @date 15-May-2014 -* @brief This file contains all the functions prototypes for SPI . -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __RADIO_SPI_H -#define __RADIO_SPI_H -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" -#include "SPIRIT_Config.h" -#include "radio_spi.h" -/** - * @addtogroup BSP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - -/* Exported constants --------------------------------------------------------*/ - - -/* Exported macro ------------------------------------------------------------*/ - /* Define for SPIRIT1 board */ - #if !defined (USE_SPIRIT1_DEFAULT) - #define USE_SPIRIT1_DEFAULT -#endif - -/* SPIRIT1_Spi_config */ -/* SPI1 */ -#define RADIO_SPI SPI1 -#define RADIO_SPI_CLK_ENABLE() __SPI1_CLK_ENABLE() -#define RADIO_SPI_CLK_DISABLE() __SPI1_CLK_DISABLE() - -#define RADIO_SPI_MISO_PORT GPIOA -#define RADIO_SPI_MISO_PIN GPIO_PIN_6 -#define RADIO_SPI_MISO_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() -#define RADIO_SPI_MISO_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() - -#define RADIO_SPI_MOSI_PORT GPIOA -#define RADIO_SPI_MOSI_PIN GPIO_PIN_7 -#define RADIO_SPI_MOSI_CLOCK_ENABLE() __GPIOA_CLK_ENABLE() -#define RADIO_SPI_MOSI_CLOCK_DISABLE() __GPIOA_CLK_DISABLE() - - - -#ifdef USE_SPIRIT1_DEFAULT - -#define RADIO_SPI_SCK_PORT GPIOB -#define RADIO_SPI_SCK_PIN GPIO_PIN_3 -#define RADIO_SPI_SCK_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() -#define RADIO_SPI_SCK_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() - - -#define RADIO_SPI_CS_PORT GPIOB -#define RADIO_SPI_CS_PIN GPIO_PIN_6 -#define RADIO_SPI_CS_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() -#define RADIO_SPI_CS_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() - -#else - -#define RADIO_SPI_SCK_PORT GPIOB -#define RADIO_SPI_SCK_PIN GPIO_PIN_3 -#define RADIO_SPI_SCK_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() -#define RADIO_SPI_SCK_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() - - -#define RADIO_SPI_CS_PORT GPIOB -#define RADIO_SPI_CS_PIN GPIO_PIN_6 -#define RADIO_SPI_CS_CLOCK_ENABLE() __GPIOB_CLK_ENABLE() -#define RADIO_SPI_CS_CLOCK_DISABLE() __GPIOB_CLK_DISABLE() - -#endif - -/* Maximum Timeout values for flags waiting loops. These timeouts are not based - on accurate values, they just guarantee that the application will not remain - stuck if the SPI communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...) */ -#define RADIO_SPI_TIMEOUT_MAX ((uint32_t)1000) - -/* SPIRIT1_Spi_config_Private_Defines */ -#define CS_TO_SCLK_DELAY 0x0100 -#define CLK_TO_CS_DELAY 0x0001 - -/* SPIRIT1_Spi_config_Headers */ -#define HEADER_WRITE_MASK 0x00 /*!< Write mask for header byte*/ -#define HEADER_READ_MASK 0x01 /*!< Read mask for header byte*/ -#define HEADER_ADDRESS_MASK 0x00 /*!< Address mask for header byte*/ -#define HEADER_COMMAND_MASK 0x80 /*!< Command mask for header byte*/ - -#define LINEAR_FIFO_ADDRESS 0xFF /*!< Linear FIFO address*/ - -/* SPIRIT1_Spi_config_Private_FunctionPrototypes */ -#define SPI_ENTER_CRITICAL() __disable_irq() -#define SPI_EXIT_CRITICAL() __enable_irq() - -/* SPIRIT1_Spi_config_Private_Functions */ -#define RadioSpiCSLow() HAL_GPIO_WritePin(RADIO_SPI_CS_PORT, RADIO_SPI_CS_PIN, GPIO_PIN_RESET) -#define RadioSpiCSHigh() HAL_GPIO_WritePin(RADIO_SPI_CS_PORT, RADIO_SPI_CS_PIN, GPIO_PIN_SET) - -/* SPIRIT1_Spi_config_Private_Macros */ -#define BUILT_HEADER(add_comm, w_r) (add_comm | w_r) /*!< macro to build the header byte*/ -#define WRITE_HEADER BUILT_HEADER(HEADER_ADDRESS_MASK, HEADER_WRITE_MASK) /*!< macro to build the write - header byte*/ -#define READ_HEADER BUILT_HEADER(HEADER_ADDRESS_MASK, HEADER_READ_MASK) /*!< macro to build the read - header byte*/ -#define COMMAND_HEADER BUILT_HEADER(HEADER_COMMAND_MASK, HEADER_WRITE_MASK) /*!< macro to build the command - header byte*/ - - - -/* Exported Variables --------------------------------------------------------*/ - - -/* Exported functions ------------------------------------------------------- */ -void SdkEvalSpiInit(void); -void SpiCSGpioSetLevel(GPIO_PinState xState); -StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); -StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer); -StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode); -StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer); -StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer); - - -#ifdef __cplusplus -} -#endif -#endif /*__RADIO_SPI_H */ - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/readme.txt b/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/readme.txt deleted file mode 100644 index 00b9b3591..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_ids01ax/readme.txt +++ /dev/null @@ -1,50 +0,0 @@ -/** - @verbatim - ******************** (C) COPYRIGHT 2014 STMicroelectronics ******************* - * @file readme.txt - * @author System LAB - NOIDA - * @version V1.0.0 - * @date 22-June-2014 - * @brief Description of the X-NUCLEO-IDS02Ax - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - * - ****************************************************************************** - @endverbatim - -@par Description - -This directory provides source files for SPIRIT1 nucleo shield BSP. - -This BSP supports: - - - X-NUCLEO-IDS02A3 (SPIRIT1-433MHz) - - X-NUCLEO-IDS02A4 (SPIRIT1-868MHz) - - X-NUCLEO-IDS02A5 (SPIRIT1-915MHz) - - - - *

© COPYRIGHT STMicroelectronics

- */ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/Release_Notes.html b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/Release_Notes.html deleted file mode 100644 index 6d5847de6..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/Release_Notes.html +++ /dev/null @@ -1,221 +0,0 @@ - - - - - -Release Notes for STM32 BlueEnergy Library - - - - - -
-


-

-
- - - - - - -
- - - - - - - - - -
-

Back to Release page

-
-

Release Notes for X-NUCLEO-IKS01A1 STM32 Expansion Board

-

Copyright -2015 STMicroelectronics

-

-
-

 

- - - - - - -
- - -

Update History

- - -

V1.3.0 -/ 28-May-2015

-

Main -Changes

- - - - - - - - - -
    -
  • Add support for NUCLEO-L152RE -
    • -
  • Add output data rate and full scale settings APIs for IMU 6-axis components -
    • -
  • Add BSP_IMU_6AXES_X_GetAxes, BSP_IMU_6AXES_G_GetAxes and BSP_MAGNETO_M_GetAxes APIs -
    • -
- -

V1.2.0 -/ 11-February-2015

-

Main -Changes

- - - - - - - - - -
    -
  • Add support for LPS25HB sensor via DIL24 interface -
    • -
  • Add auto-discovery of components attached via DIL24 interface -
    • -
  • Add extended features support for the components at BSP/driver level -
    • -
  • Add support for free fall detection feature for LSM6DS3 sensor -
    • -
- -

V1.1.0 -/ 12-December-2014

-

Main -Changes

- - - - - - - - - -
    -
  • Add support for LSM6DS3 sensor via DIL24 interface -
    • -
  • Add error control in BSP and Components API -
    • -
- -

V1.0.0 -/ 10-September-2014

-

Main -Changes

- - - - - - - - - -
    -
  • First -official release
    • -
- - -

License
-

- - -Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"). You may not use this file except in compliance with the License. You may obtain a copy of the License at:

- - -
- http://www.st.com/software_license_agreement_liberty_v2


- -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - - - - - -

- -
-
-

For -complete documentation on STM32 STM BlueNRG -visit www.st.com/BlueNRG

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1.c deleted file mode 100644 index 7c4a873e1..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1.c +++ /dev/null @@ -1,872 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1.c - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file provides X_NUCLEO_IKS01A1 MEMS shield board specific functions - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "x_nucleo_iks01a1.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @defgroup X_NUCLEO_IKS01A1_Private_Defines X_NUCLEO_IKS01A1_Private_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_Private_Variables X_NUCLEO_IKS01A1_Private_Variables - * @{ - */ - -uint32_t I2C_EXPBD_Timeout = NUCLEO_I2C_EXPBD_TIMEOUT_MAX; /*
© COPYRIGHT(c) 2015 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __X_NUCLEO_IKS01A1_H -#define __X_NUCLEO_IKS01A1_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#ifdef USE_STM32F4XX_NUCLEO -#include "stm32f4xx_hal.h" -#endif - -#ifdef USE_STM32L0XX_NUCLEO -#include "stm32l0xx_hal.h" -#endif - -#ifdef USE_STM32L1XX_NUCLEO -#include "stm32l1xx_hal.h" -#endif - -#include "hum_temp.h" -#include "imu_6axes.h" -#include "magneto.h" -#include "pressure.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @defgroup X_NUCLEO_IKS01A1_Exported_Types X_NUCLEO_IKS01A1_Exported_Types - * @{ - */ -/** - * @brief Axes raw structure definition - */ -typedef struct -{ - int16_t AXIS_X; - int16_t AXIS_Y; - int16_t AXIS_Z; -} AxesRaw_TypeDef; - -/** - * @brief Axes raw structure definition - */ -typedef struct -{ - int32_t AXIS_X; - int32_t AXIS_Y; - int32_t AXIS_Z; -} Axes_TypeDef; - -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_Exported_Defines X_NUCLEO_IKS01A1_Exported_Defines - * @{ - */ - -/* I2C clock speed configuration (in Hz) */ -#if (defined (USE_STM32F4XX_NUCLEO)) -#define NUCLEO_I2C_EXPBD_SPEED 400000 -#endif /* USE_STM32F4XX_NUCLEO */ - -/* Timing samples for L0 with SYSCLK 32MHz set in SystemClock_Config() */ -#if (defined (USE_STM32L0XX_NUCLEO)) -#define NUCLEO_I2C_EXPBD_TIMING_100KHZ 0x10A13E56 /* Analog Filter ON, Rise Time 400ns, Fall Time 100ns */ -#define NUCLEO_I2C_EXPBD_TIMING_400KHZ 0x00B1112E /* Analog Filter ON, Rise Time 250ns, Fall Time 100ns */ -#endif /* USE_STM32L0XX_NUCLEO */ - -#if (defined (USE_STM32L1XX_NUCLEO)) -#define NUCLEO_I2C_EXPBD_SPEED 100000 -#endif /* USE_STM32L1XX_NUCLEO */ - -/* I2C peripheral configuration defines */ -#define NUCLEO_I2C_EXPBD I2C1 -#define NUCLEO_I2C_EXPBD_CLK_ENABLE() __I2C1_CLK_ENABLE() -#define NUCLEO_I2C_EXPBD_SCL_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -#define NUCLEO_I2C_EXPBD_SCL_SDA_AF GPIO_AF4_I2C1 -#define NUCLEO_I2C_EXPBD_SCL_SDA_GPIO_PORT GPIOB -#define NUCLEO_I2C_EXPBD_SCL_PIN GPIO_PIN_8 -#define NUCLEO_I2C_EXPBD_SDA_PIN GPIO_PIN_9 - -#define NUCLEO_I2C_EXPBD_FORCE_RESET() __I2C1_FORCE_RESET() -#define NUCLEO_I2C_EXPBD_RELEASE_RESET() __I2C1_RELEASE_RESET() - -/* I2C interrupt requests */ -#if ((defined (USE_STM32F4XX_NUCLEO)) || (defined (USE_STM32L1XX_NUCLEO))) -#define NUCLEO_I2C_EXPBD_EV_IRQn I2C1_EV_IRQn -#define NUCLEO_I2C_EXPBD_ER_IRQn I2C1_ER_IRQn -#endif - -#if (defined (USE_STM32L0XX_NUCLEO)) -#define NUCLEO_I2C_EXPBD_EV_IRQn I2C1_IRQn -#endif - -/* Maximum Timeout values for flags waiting loops. These timeouts are not based - on accurate values, they just guarantee that the application will not remain - stuck if the SPI communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define NUCLEO_I2C_EXPBD_TIMEOUT_MAX 0x1000 /*
© COPYRIGHT(c) 2015 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "x_nucleo_iks01a1_hum_temp.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_HUM_TEMP - * @{ - */ - - -/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Private_Defines X_NUCLEO_IKS01A1_HUM_TEMP_Private_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif -/** - * @} - */ - - -/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Private_Variables X_NUCLEO_IKS01A1_HUM_TEMP_Private_Variables - * @{ - */ -static HUM_TEMP_DrvTypeDef *Hum_tempDrv = NULL; -static uint8_t HumTempInitialized = 0; -/** - * @} - */ - - -/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions - * @{ - */ - -/** - * @brief Initialize the humidity and temperature sensor - * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise - */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Init(void) -{ - uint8_t ht_id = 0; - HUM_TEMP_InitTypeDef InitStructure; - - if(!HumTempInitialized) - { - /* Initialize the hum_temp driver structure */ - Hum_tempDrv = &Hts221Drv; - - /* Configure sensor */ - InitStructure.OutputDataRate = HTS221_ODR_12_5Hz; - - /* Hts221 Init */ - if ( Hum_tempDrv->Init == NULL ) - { - Hum_tempDrv = NULL; - return HUM_TEMP_ERROR; - } - - if(Hum_tempDrv->Init(&InitStructure) != HUM_TEMP_OK) - { - Hum_tempDrv = NULL; - return HUM_TEMP_ERROR; - } - - if ( Hum_tempDrv->ReadID == NULL ) - { - Hum_tempDrv = NULL; - return HUM_TEMP_ERROR; - } - - if(Hum_tempDrv->ReadID(&ht_id) != HUM_TEMP_OK) - { - Hum_tempDrv = NULL; - return HUM_TEMP_ERROR; - } - - if(ht_id == I_AM_HTS221) - { - Hum_tempDrv->extData = (HUM_TEMP_DrvExtTypeDef *)&Hts221Drv_ext; - HumTempInitialized = 1; - } - } - - return HUM_TEMP_OK; -} - -/** - * @brief Check if the humidity and temperature sensor is initialized - * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized - */ -uint8_t BSP_HUM_TEMP_isInitialized(void) -{ - return HumTempInitialized; -} - -/** - * @brief Read the ID of the humidity and temperature component - * @param ht_id the pointer where the who_am_i of the device is stored - * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise - */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_ReadID(uint8_t *ht_id) -{ - if ( Hum_tempDrv->ReadID == NULL ) - { - return HUM_TEMP_ERROR; - } - - return Hum_tempDrv->ReadID(ht_id); -} - - -/** - * @brief Check the ID of the humidity and temperature sensor - * @retval HUM_TEMP_OK if the ID matches, HUM_TEMP_ERROR if the ID does not match or error occurs - */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_CheckID(void) -{ - uint8_t ht_id; - - if(BSP_HUM_TEMP_ReadID(&ht_id) != HUM_TEMP_OK) - { - return HUM_TEMP_ERROR; - } - - if(ht_id == I_AM_HTS221) - { - return HUM_TEMP_OK; - } - else - { - return HUM_TEMP_ERROR; - } -} - - -/** - * @brief Reboot memory content of humidity and temperature sensor - * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise - */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Reset(void) -{ - if ( Hum_tempDrv->Reset == NULL ) - { - return HUM_TEMP_ERROR; - } - - return Hum_tempDrv->Reset(); -} - - -/** - * @brief Power off the humidity and temperature sensor - * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise - */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_PowerOFF() -{ - if ( Hum_tempDrv->PowerOFF == NULL ) - { - return HUM_TEMP_ERROR; - } - - return Hum_tempDrv->PowerOFF(); -} - - -/** - * @brief Get the humidity value - * @param pfData the pointer to floating data - * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise - */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetHumidity(float* pfData) -{ - if ( Hum_tempDrv->GetHumidity == NULL ) - { - return HUM_TEMP_ERROR; - } - - return Hum_tempDrv->GetHumidity(pfData); -} - -/** - * @brief Get the temperature value - * @param pfData the pointer to floating data - * @retval HUM_TEMP_OK in case of success, HUM_TEMP_ERROR otherwise - */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetTemperature(float* pfData) -{ - if ( Hum_tempDrv->GetTemperature == NULL ) - { - return HUM_TEMP_ERROR; - } - - return Hum_tempDrv->GetTemperature(pfData); -} - -/** - * @brief Get component type currently used - * @retval HUM_TEMP_NONE_COMPONENT if none component is currently used, the component unique id otherwise - */ -HUM_TEMP_ComponentTypeDef BSP_HUM_TEMP_GetComponentType( void ) -{ - if( Hum_tempDrv == NULL ) - { - return HUM_TEMP_NONE_COMPONENT; - } - - if( Hum_tempDrv == &Hts221Drv ) - { - return HUM_TEMP_HTS221_COMPONENT; - } - - return HUM_TEMP_NONE_COMPONENT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_hum_temp.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_hum_temp.h deleted file mode 100644 index 311cde9d9..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_hum_temp.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1_hum_temp.h - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file contains definitions for x_nucleo_iks01a1_hum_temp.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __X_NUCLEO_IKS01A1_HUM_TEMP_H -#define __X_NUCLEO_IKS01A1_HUM_TEMP_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -//#include "x_nucleo_iks01a1.h" -/* Include HUM_TEMP sensor component driver */ -#include "hts221.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_HUM_TEMP - * @{ - */ - - -/** @defgroup X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions X_NUCLEO_IKS01A1_HUM_TEMP_Exported_Functions - * @{ - */ -/* Sensor Configuration Functions */ -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Init(void); -uint8_t BSP_HUM_TEMP_isInitialized(void); -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_ReadID(uint8_t *); -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_CheckID(void); -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_Reset(void); -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_PowerOFF(void); -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetHumidity(float* pfData); -HUM_TEMP_StatusTypeDef BSP_HUM_TEMP_GetTemperature(float* pfData); -HUM_TEMP_ComponentTypeDef BSP_HUM_TEMP_GetComponentType(void); - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __X_NUCLEO_IKS01A1_HUM_TEMP_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.c deleted file mode 100644 index b6d711da4..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.c +++ /dev/null @@ -1,599 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1_imu_6axes.c - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file provides a set of functions needed to manage the lsm6ds0 and lsm6ds3 sensors. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "x_nucleo_iks01a1_imu_6axes.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_IMU_6AXES - * @{ - */ - -/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Private_Defines X_NUCLEO_IKS01A1_IMU_6AXES_Private_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Private_Variables X_NUCLEO_IKS01A1_IMU_6AXES_Private_Variables - * @{ - */ -static IMU_6AXES_DrvTypeDef *Imu6AxesDrv = NULL; -static uint8_t Imu6AxesInitialized = 0; -static uint8_t imu_6axes_sensor_type = 1; /* 1 activates LSM6DS3, 0 activates LSM6DS0 */ - -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions - * @{ - */ - -/** - * @brief Initialize the IMU 6 axes sensor - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Init(void) -{ - IMU_6AXES_InitTypeDef InitStructure; - uint8_t xg_id = 0; - int done = 0; - - if(!Imu6AxesInitialized) - { - do - { - switch(imu_6axes_sensor_type) - { - case 1: /* Try to initialized LSM6DS3 */ - { - /* Initialize the six axes driver structure */ - Imu6AxesDrv = &LSM6DS3Drv; - - /* Configure sensor */ - InitStructure.G_FullScale = 2000.0f; /* 2000DPS */ - InitStructure.G_OutputDataRate = 104.0f; /* 104HZ */ - InitStructure.G_X_Axis = 1; /* Enable */ - InitStructure.G_Y_Axis = 1; /* Enable */ - InitStructure.G_Z_Axis = 1; /* Enable */ - - InitStructure.X_FullScale = 2.0f; /* 2G */ - InitStructure.X_OutputDataRate = 104.0f; /* 104HZ */ - InitStructure.X_X_Axis = 1; /* Enable */ - InitStructure.X_Y_Axis = 1; /* Enable */ - InitStructure.X_Z_Axis = 1; /* Enable */ - - if( Imu6AxesDrv->Init == NULL ) - { - Imu6AxesDrv = NULL; - imu_6axes_sensor_type--; - break; - } - - if( Imu6AxesDrv->Init(&InitStructure) != IMU_6AXES_OK) - { - Imu6AxesDrv = NULL; - imu_6axes_sensor_type--; - break; - } - - if ( Imu6AxesDrv->Read_XG_ID == NULL ) - { - Imu6AxesDrv = NULL; - imu_6axes_sensor_type--; - break; - } - - if(Imu6AxesDrv->Read_XG_ID(&xg_id) != IMU_6AXES_OK) - { - Imu6AxesDrv = NULL; - imu_6axes_sensor_type--; - break; - } - - if(xg_id == I_AM_LSM6DS3_XG) - { - Imu6AxesDrv->extData = (IMU_6AXES_DrvExtTypeDef *)&LSM6DS3Drv_ext; - Imu6AxesInitialized = 1; - done = 1; - break; - } - else - { - Imu6AxesDrv = NULL; - imu_6axes_sensor_type--; - break; - } - } - case 0: /* Try to initialized LSM6DS0 */ - default: - { - imu_6axes_sensor_type = 0; - /* Initialize the six axes driver structure */ - Imu6AxesDrv = &LSM6DS0Drv; - - /* Configure sensor */ - InitStructure.G_FullScale = 2000.0f; /* 2000DPS */ - InitStructure.G_OutputDataRate = 119.0f; /* 119HZ */ - InitStructure.G_X_Axis = 1; /* Enable */ - InitStructure.G_Y_Axis = 1; /* Enable */ - InitStructure.G_Z_Axis = 1; /* Enable */ - - InitStructure.X_FullScale = 2.0f; /* 2G */ - InitStructure.X_OutputDataRate = 119.0f; /* 119HZ */ - InitStructure.X_X_Axis = 1; /* Enable */ - InitStructure.X_Y_Axis = 1; /* Enable */ - InitStructure.X_Z_Axis = 1; /* Enable */ - - if( Imu6AxesDrv->Init == NULL ) - { - Imu6AxesDrv = NULL; - return IMU_6AXES_ERROR; - } - - if( Imu6AxesDrv->Init(&InitStructure) != IMU_6AXES_OK) - { - Imu6AxesDrv = NULL; - return IMU_6AXES_ERROR; - } - - if ( Imu6AxesDrv->Read_XG_ID == NULL ) - { - Imu6AxesDrv = NULL; - return IMU_6AXES_ERROR; - } - - if(Imu6AxesDrv->Read_XG_ID(&xg_id) != IMU_6AXES_OK) - { - Imu6AxesDrv = NULL; - return IMU_6AXES_ERROR; - } - - if(xg_id == I_AM_LSM6DS0_XG) - { - Imu6AxesDrv->extData = (IMU_6AXES_DrvExtTypeDef *)&LSM6DS0Drv_ext; - Imu6AxesInitialized = 1; - done = 1; - break; - } - } - } - } - while(!done); - } - - return IMU_6AXES_OK; -} - -/** - * @brief Check if the IMU 6 axes sensor is initialized - * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized - */ -uint8_t BSP_IMU_6AXES_isInitialized(void) -{ - return Imu6AxesInitialized; -} - - -/** - * @brief Read the ID of the IMU 6 axes sensor - * @param xg_id the pointer where the who_am_i of the device is stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Read_XG_ID(uint8_t *xg_id) -{ - if ( Imu6AxesDrv->Read_XG_ID == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Read_XG_ID(xg_id); -} - - -/** - * @brief Check the ID of the IMU 6 axes sensor - * @retval IMU_6AXES_OK if the ID matches, IMU_6AXES_ERROR if the ID does not match or error occurs - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Check_XG_ID(void) -{ - uint8_t xg_id; - - if(BSP_IMU_6AXES_Read_XG_ID(&xg_id) != IMU_6AXES_OK) - { - return IMU_6AXES_ERROR; - } - - switch(imu_6axes_sensor_type) - { - case 1: - { - if(xg_id == I_AM_LSM6DS3_XG) - { - return IMU_6AXES_OK; - } - else - { - return IMU_6AXES_ERROR; - } - } - case 0: - default: - { - if(xg_id == I_AM_LSM6DS0_XG) - { - return IMU_6AXES_OK; - } - else - { - return IMU_6AXES_ERROR; - } - } - } -} - -/** - * @brief Get the accelerometer axes of the IMU 6 axes sensor - * @param pData the pointer where the output data are stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxes(Axes_TypeDef *pData) -{ - if ( Imu6AxesDrv->Get_X_Axes == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_X_Axes((int32_t *)pData); -} - -/** - * @brief Get the accelerometer raw axes of the IMU 6 axes sensor - * @param pData the pointer where the output data are stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxesRaw(AxesRaw_TypeDef *pData) -{ - if ( Imu6AxesDrv->Get_X_AxesRaw == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_X_AxesRaw((int16_t *)pData); -} - -/** - * @brief Get the gyroscope axes of the IMU 6 axes sensor - * @param pData the pointer where the output data are stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxes(Axes_TypeDef *pData) -{ - if ( Imu6AxesDrv->Get_G_Axes == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_G_Axes((int32_t *)pData); -} - -/** - * @brief Get the gyroscope raw axes of the IMU 6 axes sensor - * @param pData the pointer where the output data are stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxesRaw(AxesRaw_TypeDef *pData) -{ - if ( Imu6AxesDrv->Get_G_AxesRaw == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_G_AxesRaw((int16_t *)pData); -} - -/** - * @brief Get the accelerometer output data rate - * @param odr the pointer where the accelerometer output data rate is stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_ODR(float *odr) -{ - if( Imu6AxesDrv->Get_X_ODR == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_X_ODR( odr ); -} - -/** - * @brief Set the accelerometer output data rate - * @param odr the accelerometer output data rate to be set - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_ODR(float odr) -{ - if( Imu6AxesDrv->Set_X_ODR == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Set_X_ODR( odr ); -} - -/** - * @brief Get accelerometer sensitivity - * @param pfData the pointer where accelerometer sensitivity is stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetSensitivity( float *pfData ) -{ - if( Imu6AxesDrv->Get_X_Sensitivity == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_X_Sensitivity( pfData ); -} - -/** - * @brief Get the accelerometer full scale - * @param fullScale the pointer where the accelerometer full scale is stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_FS(float *fullScale) -{ - if( Imu6AxesDrv->Get_X_FS == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_X_FS( fullScale ); -} - -/** - * @brief Set the accelerometer full scale - * @param fullScale the accelerometer full scale to be set - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_FS(float fullScale) -{ - if( Imu6AxesDrv->Set_X_FS == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Set_X_FS( fullScale ); -} - -/** - * @brief Get the gyroscope output data rate - * @param odr the pointer where the gyroscope output data rate is stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_ODR(float *odr) -{ - if( Imu6AxesDrv->Get_G_ODR == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_G_ODR( odr ); -} - -/** - * @brief Set the gyroscope output data rate - * @param odr the gyroscope output data rate to be set - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_ODR(float odr) -{ - if( Imu6AxesDrv->Set_G_ODR == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Set_G_ODR( odr ); -} - -/** - * @brief Get gyroscope sensitivity - * @param pfData the pointer where the gyroscope sensitivity is stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetSensitivity( float *pfData ) -{ - if( Imu6AxesDrv->Get_G_Sensitivity == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_G_Sensitivity( pfData ); -} - -/** - * @brief Get the gyroscope full scale - * @param fullScale the pointer where the gyroscope full scale is stored - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_FS(float *fullScale) -{ - if( Imu6AxesDrv->Get_G_FS == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Get_G_FS( fullScale ); -} - -/** - * @brief Set the gyroscope full scale - * @param fullScale the gyroscope full scale to be set - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_FS(float fullScale) -{ - if( Imu6AxesDrv->Set_G_FS == NULL ) - { - return IMU_6AXES_ERROR; - } - - return Imu6AxesDrv->Set_G_FS( fullScale ); -} - -/** - * @brief Get component type currently used - * @retval IMU_6AXES_NONE_COMPONENT if none component is currently used, the component unique id otherwise - */ -IMU_6AXES_ComponentTypeDef BSP_IMU_6AXES_GetComponentType( void ) -{ - if( Imu6AxesDrv == NULL ) - { - return IMU_6AXES_NONE_COMPONENT; - } - - if( Imu6AxesDrv == &LSM6DS0Drv ) - { - return IMU_6AXES_LSM6DS0_COMPONENT; - } - - if( Imu6AxesDrv == &LSM6DS3Drv ) - { - return IMU_6AXES_LSM6DS3_DIL24_COMPONENT; - } - - return IMU_6AXES_NONE_COMPONENT; -} - -/** - * @brief Enable free fall detection (available only for LSM6DS3 sensor) - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_NOT_IMPLEMENTED if the feature is not supported, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Enable_Free_Fall_Detection_Ext(void) -{ - /* At the moment this feature is only implemented for LSM6DS3 */ - if( Imu6AxesDrv->extData == NULL || Imu6AxesDrv->extData->id != IMU_6AXES_LSM6DS3_DIL24_COMPONENT - || Imu6AxesDrv->extData->pData == NULL) - { - return IMU_6AXES_NOT_IMPLEMENTED; - } - - if(((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Enable_Free_Fall_Detection == NULL) - { - return IMU_6AXES_NOT_IMPLEMENTED; - } - - return ((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Enable_Free_Fall_Detection(); -} - -/** - * @brief Disable free fall detection (available only for LSM6DS3 sensor) - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_NOT_IMPLEMENTED if the feature is not supported, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Disable_Free_Fall_Detection_Ext(void) -{ - /* At the moment this feature is only implemented for LSM6DS3 */ - if( Imu6AxesDrv->extData == NULL || Imu6AxesDrv->extData->id != IMU_6AXES_LSM6DS3_DIL24_COMPONENT - || Imu6AxesDrv->extData->pData == NULL) - { - return IMU_6AXES_NOT_IMPLEMENTED; - } - - if(((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Disable_Free_Fall_Detection == NULL) - { - return IMU_6AXES_NOT_IMPLEMENTED; - } - - return ((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Disable_Free_Fall_Detection(); -} - -/** - * @brief Get status of free fall detection (available only for LSM6DS3 sensor) - * @param status the pointer where the status of free fall detection is stored; 0 means no detection, 1 means detection happened - * @retval IMU_6AXES_OK in case of success, IMU_6AXES_NOT_IMPLEMENTED if the feature is not supported, IMU_6AXES_ERROR otherwise - */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Get_Status_Free_Fall_Detection_Ext(uint8_t *status) -{ - /* At the moment this feature is only implemented for LSM6DS3 */ - if( Imu6AxesDrv->extData == NULL || Imu6AxesDrv->extData->id != IMU_6AXES_LSM6DS3_DIL24_COMPONENT - || Imu6AxesDrv->extData->pData == NULL) - { - return IMU_6AXES_NOT_IMPLEMENTED; - } - - if(((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Get_Status_Free_Fall_Detection == NULL) - { - return IMU_6AXES_NOT_IMPLEMENTED; - } - - if(status == NULL) - { - return IMU_6AXES_ERROR; - } - - return ((LSM6DS3_DrvExtTypeDef *)(Imu6AxesDrv->extData->pData))->Get_Status_Free_Fall_Detection(status); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.h deleted file mode 100644 index d7a211da7..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_imu_6axes.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1_imu_6axes.h - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file contains definitions for the x_nucleo_iks01a1_imu_6axes.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __X_NUCLEO_IKS01A1_IMU_6AXES_H -#define __X_NUCLEO_IKS01A1_IMU_6AXES_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "x_nucleo_iks01a1.h" -/* Include nine axes sensor component driver */ -#include "lsm6ds3.h" -#include "lsm6ds0.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_IMU_6AXES - * @{ - */ - - -/** @defgroup X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions X_NUCLEO_IKS01A1_IMU_6AXES_Exported_Functions - * @{ - */ - -/* Sensor Configuration Functions */ -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Init(void); -uint8_t BSP_IMU_6AXES_isInitialized(void); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Read_XG_ID(uint8_t *); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Check_XG_ID(void); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxes(Axes_TypeDef *pData); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetAxesRaw(AxesRaw_TypeDef *pData); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxes(Axes_TypeDef *pData); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetAxesRaw(AxesRaw_TypeDef *pData); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_ODR(float *odr); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_ODR(float odr); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_GetSensitivity(float *pfData); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Get_FS(float *fullScale); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_X_Set_FS(float fullScale); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_ODR(float *odr); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_ODR(float odr); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_GetSensitivity(float *pfData); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Get_FS(float *fullScale); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_G_Set_FS(float fullScale); -IMU_6AXES_ComponentTypeDef BSP_IMU_6AXES_GetComponentType(void); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Enable_Free_Fall_Detection_Ext(void); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Disable_Free_Fall_Detection_Ext(void); -IMU_6AXES_StatusTypeDef BSP_IMU_6AXES_Get_Status_Free_Fall_Detection_Ext(uint8_t *status); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __X_NUCLEO_IKS01A1_IMU_6AXES_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.c deleted file mode 100644 index f6b7031e8..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.c +++ /dev/null @@ -1,245 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1_magneto.c - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file provides a set of functions needed to manage the lis3mdl sensor. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "x_nucleo_iks01a1_magneto.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_MAGNETO - * @{ - */ - -/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Private_Defines X_NUCLEO_IKS01A1_MAGNETO_Private_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Private_Variables X_NUCLEO_IKS01A1_MAGNETO_Private_Variables - * @{ - */ -static MAGNETO_DrvTypeDef *MagnetoDrv = NULL; -static uint8_t MagnetoInitialized = 0; - -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions - * @{ - */ - -/** - * @brief Initialize the magneto sensor - * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise - */ -MAGNETO_StatusTypeDef BSP_MAGNETO_Init(void) -{ - uint8_t m_id = 0; - MAGNETO_InitTypeDef InitStructure; - - if(!MagnetoInitialized) - { - /* Initialize the magneto driver structure */ - MagnetoDrv = &LIS3MDLDrv; - - /* Configure sensor */ - InitStructure.M_FullScale = LIS3MDL_M_FS_4; - InitStructure.M_OperatingMode = LIS3MDL_M_MD_CONTINUOUS; - InitStructure.M_XYOperativeMode = LIS3MDL_M_OM_HP; - InitStructure.M_OutputDataRate = LIS3MDL_M_DO_80; - - /* magneto sensor init */ - if ( MagnetoDrv->Init == NULL ) - { - MagnetoDrv = NULL; - return MAGNETO_ERROR; - } - - if(MagnetoDrv->Init(&InitStructure) != MAGNETO_OK) - { - MagnetoDrv = NULL; - return MAGNETO_ERROR; - } - - if ( MagnetoDrv->Read_M_ID == NULL ) - { - MagnetoDrv = NULL; - return MAGNETO_ERROR; - } - - if(MagnetoDrv->Read_M_ID(&m_id) != MAGNETO_OK) - { - MagnetoDrv = NULL; - return MAGNETO_ERROR; - } - - if(m_id == I_AM_LIS3MDL_M) - { - MagnetoDrv->extData = (MAGNETO_DrvExtTypeDef *)&LIS3MDLDrv_ext; - MagnetoInitialized = 1; - } - } - - return MAGNETO_OK; -} - -/** - * @brief Check if the magnetic sensor is initialized - * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized - */ -uint8_t BSP_MAGNETO_isInitialized(void) -{ - return MagnetoInitialized; -} - - -/** - * @brief Read the ID of the magnetic sensor - * @param m_id the pointer where the who_am_i of the device is stored - * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise - */ -MAGNETO_StatusTypeDef BSP_MAGNETO_Read_M_ID(uint8_t *m_id) -{ - if ( MagnetoDrv->Read_M_ID == NULL ) - { - return MAGNETO_ERROR; - } - - return MagnetoDrv->Read_M_ID(m_id); -} - - -/** - * @brief Check the ID of the magnetic sensor - * @retval MAGNETO_OK if the ID matches, MAGNETO_ERROR if the ID does not match or error occurs - */ -MAGNETO_StatusTypeDef BSP_MAGNETO_Check_M_ID(void) -{ - uint8_t m_id; - - if(BSP_MAGNETO_Read_M_ID(&m_id) != MAGNETO_OK) - { - return MAGNETO_ERROR; - } - - if(m_id == I_AM_LIS3MDL_M) - { - return MAGNETO_OK; - } - else - { - return MAGNETO_ERROR; - } -} - -/** - * @brief Get the magnetic sensor axes - * @param pData the pointer where the output data are stored - * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise - */ -MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxes(Axes_TypeDef *pData) -{ - if ( MagnetoDrv->Get_M_Axes == NULL ) - { - return MAGNETO_ERROR; - } - - return MagnetoDrv->Get_M_Axes((int32_t *)pData); -} - -/** - * @brief Get the magnetic sensor raw axes - * @param pData the pointer where the output data are stored - * @retval MAGNETO_OK in case of success, MAGNETO_ERROR otherwise - */ -MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxesRaw(AxesRaw_TypeDef *pData) -{ - if ( MagnetoDrv->Get_M_AxesRaw == NULL ) - { - return MAGNETO_ERROR; - } - - return MagnetoDrv->Get_M_AxesRaw((int16_t *)pData); -} - -/** - * @brief Get component type currently used - * @retval MAGNETO_NONE_COMPONENT if none component is currently used, the component unique id otherwise - */ -MAGNETO_ComponentTypeDef BSP_MAGNETO_GetComponentType( void ) -{ - if( MagnetoDrv == NULL ) - { - return MAGNETO_NONE_COMPONENT; - } - - if( MagnetoDrv == &LIS3MDLDrv ) - { - return MAGNETO_LIS3MDL_COMPONENT; - } - - return MAGNETO_NONE_COMPONENT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.h deleted file mode 100644 index cfa7e3efe..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_magneto.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1_magneto.h - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file contains definitions for the x_nucleo_iks01a1_magneto.c - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __X_NUCLEO_IKS01A1_MAGNETO_H -#define __X_NUCLEO_IKS01A1_MAGNETO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "x_nucleo_iks01a1.h" -/* Include nine axes sensor component driver */ -#include "lis3mdl.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_MAGNETO - * @{ - */ - -/** @defgroup X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions X_NUCLEO_IKS01A1_MAGNETO_Exported_Functions - * @{ - */ -/* Sensor Configuration Functions */ -MAGNETO_StatusTypeDef BSP_MAGNETO_Init(void); -uint8_t BSP_MAGNETO_isInitialized(void); -MAGNETO_StatusTypeDef BSP_MAGNETO_Read_M_ID(uint8_t *m_id); -MAGNETO_StatusTypeDef BSP_MAGNETO_Check_M_ID(void); -MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxes(Axes_TypeDef *pData); -MAGNETO_StatusTypeDef BSP_MAGNETO_M_GetAxesRaw(AxesRaw_TypeDef *pData); -MAGNETO_ComponentTypeDef BSP_MAGNETO_GetComponentType(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __X_NUCLEO_IKS01A1_MAGNETO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.c b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.c deleted file mode 100644 index 44ff946af..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.c +++ /dev/null @@ -1,357 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1_pressure.c - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file provides a set of functions needed to manage the lps25h and lps25hb sensors. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "x_nucleo_iks01a1_pressure.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_PRESSURE - * @{ - */ - - -/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Private_Defines X_NUCLEO_IKS01A1_PRESSURE_Private_Defines - * @{ - */ -#ifndef NULL -#define NULL (void *) 0 -#endif -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Private_Variables X_NUCLEO_IKS01A1_PRESSURE_Private_Variables - * @{ - */ -static PRESSURE_DrvTypeDef *PressureDrv = NULL; -static uint8_t PressureInitialized = 0; -static uint8_t pressure_sensor_type = 1; /* 1 activates LPS25HB, 0 activates LPS25H */ - -/** - * @} - */ - -/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions - * @{ - */ - -/** - * @brief Initialize the pressure sensor - * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise - */ -PRESSURE_StatusTypeDef BSP_PRESSURE_Init(void) -{ - uint8_t p_id = 0; - PRESSURE_InitTypeDef InitStructure; - int done = 0; - - if(!PressureInitialized) - { - do - { - switch(pressure_sensor_type) - { - case 1: - { - /* Initialize the pressure driver structure */ - PressureDrv = &LPS25HBDrv; - - /* Configure sensor */ - InitStructure.OutputDataRate = LPS25HB_ODR_1Hz; - InitStructure.BlockDataUpdate = LPS25HB_BDU_CONT; - InitStructure.DiffEnable = LPS25HB_DIFF_ENABLE; - InitStructure.SPIMode = LPS25HB_SPI_SIM_3W; - InitStructure.PressureResolution = LPS25HB_P_RES_AVG_32; - InitStructure.TemperatureResolution = LPS25HB_T_RES_AVG_16; - - /* Pressure sensor init */ - if ( PressureDrv->Init == NULL ) - { - PressureDrv = NULL; - pressure_sensor_type--; - break; - } - - if(PressureDrv->Init(&InitStructure) != PRESSURE_OK) - { - PressureDrv = NULL; - pressure_sensor_type--; - break; - } - - if ( PressureDrv->ReadID == NULL ) - { - PressureDrv = NULL; - pressure_sensor_type--; - break; - } - - if(PressureDrv->ReadID(&p_id) != PRESSURE_OK) - { - PressureDrv = NULL; - pressure_sensor_type--; - break; - } - - if(p_id == I_AM_LPS25HB) - { - PressureDrv->extData = (PRESSURE_DrvExtTypeDef *)&LPS25HBDrv_ext; - PressureInitialized = 1; - done = 1; - break; - } - else - { - PressureDrv = NULL; - pressure_sensor_type--; - break; - } - } - case 0: - default: - { - /* Initialize the pressure driver structure */ - PressureDrv = &LPS25HDrv; - - /* Configure sensor */ - InitStructure.OutputDataRate = LPS25H_ODR_1Hz; - InitStructure.BlockDataUpdate = LPS25H_BDU_CONT; - InitStructure.DiffEnable = LPS25H_DIFF_ENABLE; - InitStructure.SPIMode = LPS25H_SPI_SIM_3W; - InitStructure.PressureResolution = LPS25H_P_RES_AVG_32; - InitStructure.TemperatureResolution = LPS25H_T_RES_AVG_16; - - /* Pressure sensor init */ - if ( PressureDrv->Init == NULL ) - { - PressureDrv = NULL; - return PRESSURE_ERROR; - } - - if(PressureDrv->Init(&InitStructure) != PRESSURE_OK) - { - PressureDrv = NULL; - return PRESSURE_ERROR; - } - - if ( PressureDrv->ReadID == NULL ) - { - PressureDrv = NULL; - return PRESSURE_ERROR; - } - - if(PressureDrv->ReadID(&p_id) != PRESSURE_OK) - { - PressureDrv = NULL; - return PRESSURE_ERROR; - } - - if(p_id == I_AM_LPS25H) - { - PressureDrv->extData = (PRESSURE_DrvExtTypeDef *)&LPS25HDrv_ext; - PressureInitialized = 1; - done = 1; - break; - } - } - } - } - while(!done); - } - - return PRESSURE_OK; -} - -/** - * @brief Check if the pressure sensor is initialized - * @retval 0 if the sensor is not initialized, 1 if the sensor is already initialized - */ -uint8_t BSP_PRESSURE_isInitialized(void) -{ - return PressureInitialized; -} - -/** - * @brief Read the ID of the pressure sensor - * @param p_id the pointer where the who_am_i of the device is stored - * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise - */ -PRESSURE_StatusTypeDef BSP_PRESSURE_ReadID(uint8_t *p_id) -{ - if ( PressureDrv->ReadID == NULL ) - { - return PRESSURE_ERROR; - } - - return PressureDrv->ReadID(p_id); -} - - -/** - * @brief Check the ID of the pressure sensor - * @retval PRESSURE_OK if the ID matches, PRESSURE_ERROR if the ID does not match or error occurs - */ -PRESSURE_StatusTypeDef BSP_PRESSURE_CheckID(void) -{ - uint8_t p_id; - - if(BSP_PRESSURE_ReadID(&p_id) != PRESSURE_OK) - { - return PRESSURE_ERROR; - } - - switch(pressure_sensor_type) - { - case 1: - { - if(p_id == I_AM_LPS25HB) - { - return PRESSURE_OK; - } - else - { - return PRESSURE_ERROR; - } - } - case 0: - default: - { - if(p_id == I_AM_LPS25H) - { - return PRESSURE_OK; - } - else - { - return PRESSURE_ERROR; - } - } - } -} - - -/** - * @brief Reboot the memory content of the pressure sensor - * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise - */ -PRESSURE_StatusTypeDef BSP_PRESSURE_Reset(void) -{ - if ( PressureDrv->Reset == NULL ) - { - return PRESSURE_ERROR; - } - - return PressureDrv->Reset(); -} - - -/** - * @brief Get the pressure - * @param pfData the pointer where the output data are stored - * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise - */ -PRESSURE_StatusTypeDef BSP_PRESSURE_GetPressure(float* pfData) -{ - if ( PressureDrv->GetPressure == NULL ) - { - return PRESSURE_ERROR; - } - - return PressureDrv->GetPressure(pfData); -} - -/** - * @brief Get the temperature - * @param pfData the pointer where the output data are stored - * @retval PRESSURE_OK in case of success, PRESSURE_ERROR otherwise - */ -PRESSURE_StatusTypeDef BSP_PRESSURE_GetTemperature(float* pfData) -{ - if ( PressureDrv->GetTemperature == NULL ) - { - return PRESSURE_ERROR; - } - - return PressureDrv->GetTemperature(pfData); -} - -/** - * @brief Get component type currently used - * @retval PRESSURE_NONE_COMPONENT if none component is currently used, the component unique id otherwise - */ -PRESSURE_ComponentTypeDef BSP_PRESSURE_GetComponentType( void ) -{ - if( PressureDrv == NULL ) - { - return PRESSURE_NONE_COMPONENT; - } - - if( PressureDrv == &LPS25HDrv ) - { - return PRESSURE_LPS25H_COMPONENT; - } - - if( PressureDrv == &LPS25HBDrv ) - { - return PRESSURE_LPS25HB_DIL24_COMPONENT; - } - - return PRESSURE_NONE_COMPONENT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.h b/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.h deleted file mode 100644 index 975020ea6..000000000 --- a/platform/stm32nucleo-spirit1/drivers/x_nucleo_iks01a1/x_nucleo_iks01a1_pressure.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - ****************************************************************************** - * @file x_nucleo_iks01a1_pressure.h - * @author CL - * @version V1.3.0 - * @date 28-May-2015 - * @brief This file contains definitions for x_nucleo_iks01a1_pressure.c - * firmware driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __X_NUCLEO_IKS01A1_PRESSURE_H -#define __X_NUCLEO_IKS01A1_PRESSURE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -//#include "x_nucleo_iks01a1.h" -/* Include Pressure sensor component driver */ -#include "lps25h.h" -#include "lps25hb.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1 - * @{ - */ - -/** @addtogroup X_NUCLEO_IKS01A1_PRESSURE - * @{ - */ - -/** @defgroup X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions X_NUCLEO_IKS01A1_PRESSURE_Exported_Functions - * @{ - */ -/* Sensor Configuration Functions */ -PRESSURE_StatusTypeDef BSP_PRESSURE_Init(void); -uint8_t BSP_PRESSURE_isInitialized(void); -PRESSURE_StatusTypeDef BSP_PRESSURE_Reset(void); -PRESSURE_StatusTypeDef BSP_PRESSURE_ReadID(uint8_t *p_id); -PRESSURE_StatusTypeDef BSP_PRESSURE_CheckID(void); -PRESSURE_StatusTypeDef BSP_PRESSURE_GetPressure(float* pfData); -PRESSURE_StatusTypeDef BSP_PRESSURE_GetTemperature(float* pfData); -PRESSURE_ComponentTypeDef BSP_PRESSURE_GetComponentType(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __X_NUCLEO_IKS01A1_PRESSURE_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/hw-config.h b/platform/stm32nucleo-spirit1/hw-config.h index 3a5d35243..951704b64 100644 --- a/platform/stm32nucleo-spirit1/hw-config.h +++ b/platform/stm32nucleo-spirit1/hw-config.h @@ -34,28 +34,22 @@ * ****************************************************************************** */ -/* Define to prevent recursive inclusion -------------------------------------*/ +/*---------------------------------------------------------------------------*/ #ifndef __HW_CONFIG_H #define __HW_CONFIG_H - -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ #include "stm32l-spirit1-config.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported define -----------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ #define UART_RxBufferSize 512 - - +/*---------------------------------------------------------------------------*/ #define I2Cx I2C1 #define I2Cx_CLK_ENABLE() __I2C1_CLK_ENABLE() #define I2Cx_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() #define I2Cx_SCL_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() - +/*---------------------------------------------------------------------------*/ #define I2Cx_FORCE_RESET() __I2C1_FORCE_RESET() #define I2Cx_RELEASE_RESET() __I2C1_RELEASE_RESET() - +/*---------------------------------------------------------------------------*/ /* Definition for I2Cx Pins */ #define I2Cx_SCL_PIN GPIO_PIN_8 #define I2Cx_SCL_GPIO_PORT GPIOB @@ -91,9 +85,6 @@ #define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler #define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler - - - /* User can use this section to tailor USARTx/UARTx instance used and associated resources */ /* Definition for USARTx clock resources */ @@ -113,7 +104,7 @@ #define USARTx_RX_PIN GPIO_PIN_3 #define USARTx_RX_GPIO_PORT GPIOA -// /* Definition for USARTx's NVIC */ + /* Definition for USARTx's NVIC */ #define USARTx_IRQn USART2_IRQn #define USARTx_IRQHandler USART2_IRQHandler @@ -121,7 +112,7 @@ #define USARTx_RX_AF GPIO_AF7_USART2 - // Enalble sensor mask + /* Enable sensor mask */ #define PRESSURE_SENSOR 0x00000001 #define TEMPERATURE_SENSOR 0x00000002 #define HUMIDITY_SENSOR 0x00000004 @@ -129,8 +120,6 @@ #define ACCELEROMETER_SENSOR 0x00000010 #define GYROSCOPE_SENSOR 0x00000020 #define MAGNETIC_SENSOR 0x00000040 -/* Exported functions ------------------------------------------------------- */ -/* External variables --------------------------------------------------------*/ - +/*---------------------------------------------------------------------------*/ #endif /*__HW_CONFIG_H*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/node-id.c b/platform/stm32nucleo-spirit1/node-id.c index 24b7d6af5..ab6286791 100644 --- a/platform/stm32nucleo-spirit1/node-id.c +++ b/platform/stm32nucleo-spirit1/node-id.c @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file node-id.c +* @file platform/stm32nucleo-spirit1/node-id.c * @author System LAB * @version V1.0.0 * @date 17-June-2015 @@ -34,20 +34,18 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ #include "node-id.h" #include "contiki-conf.h" - #include - +/*---------------------------------------------------------------------------*/ unsigned short node_id = 0; unsigned char node_mac[8]; volatile uint32_t device_id[3]; - +/*---------------------------------------------------------------------------*/ #define DEVICE_ID_REG0 (*((volatile uint32_t *) 0x1FF80050)) #define DEVICE_ID_REG1 (*((volatile uint32_t *) 0x1FF80054)) #define DEVICE_ID_REG2 (*((volatile uint32_t *) 0x1FF80064)) - /*---------------------------------------------------------------------------*/ void node_id_restore(void) { @@ -59,3 +57,4 @@ void node_id_restore(void) (*(((uint32_t*)node_mac)+1))=DEVICE_ID_REG2+DEVICE_ID_REG0; node_id = (unsigned short) DEVICE_ID_REG2; } +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/platform-conf.h b/platform/stm32nucleo-spirit1/platform-conf.h index 273f61fc8..513b8feed 100644 --- a/platform/stm32nucleo-spirit1/platform-conf.h +++ b/platform/stm32nucleo-spirit1/platform-conf.h @@ -1,6 +1,6 @@ /** ****************************************************************************** -* @file platform-conf.h +* @file platform/stm32nucleo-spirit1/platform-conf.h * @author System LAB * @version V1.0.0 * @date 17-May-2015 @@ -34,13 +34,26 @@ * ****************************************************************************** */ - +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1 + * @{ + * + * \defgroup stm32nucleo-spirit1-peripherals User Button on STM32 Nucleo + * + * Defines some of the platforms capabilities + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 platform configuration + */ +/*---------------------------------------------------------------------------*/ #ifndef __PLATFORM_CONF_H__ #define __PLATFORM_CONF_H__ - +/*---------------------------------------------------------------------------*/ #include #include - +/*---------------------------------------------------------------------------*/ #define PLATFORM_HAS_LEDS 1 #define PLATFORM_HAS_BUTTON 1 @@ -52,11 +65,10 @@ #else #define LEDS_CONF_ALL 3 /*No sensors -> we can use SPIRIT1 LED in this case*/ #endif /*COMPILE_SENSORS*/ - +/*---------------------------------------------------------------------------*/ #define F_CPU 32000000ul #define RTIMER_ARCH_SECOND 32768 #define PRESCALER ((F_CPU / (RTIMER_ARCH_SECOND*2))) - #define UART1_CONF_TX_WITH_INTERRUPT 0 #define WITH_SERIAL_LINE_INPUT 1 @@ -64,17 +76,18 @@ #define NETSTACK_CONF_RADIO spirit_radio_driver #define NETSTACK_RADIO_MAX_PAYLOAD_LEN 96 /* spirit1-config.h */ +/*---------------------------------------------------------------------------*/ /* define ticks/second for slow and fast clocks. Notice that these should be a power of two, eg 64,128,256,512 etc, for efficiency as POT's can be optimized well. */ - #define CLOCK_CONF_SECOND 128 -// One tick: 62.5 ms +/* One tick: 62.5 ms */ #define RTIMER_CLOCK_LT(a,b) ((signed short)((a)-(b)) < 0) +/*---------------------------------------------------------------------------*/ typedef unsigned long clock_time_t; typedef unsigned long long rtimer_clock_t; - +/*---------------------------------------------------------------------------*/ #define CC_CONF_REGISTER_ARGS 0 #define CC_CONF_FUNCTION_POINTER_ARGS 1 #define CC_CONF_FASTCALL @@ -83,14 +96,19 @@ typedef unsigned long long rtimer_clock_t; #define CCIF #define CLIF - +/*---------------------------------------------------------------------------*/ typedef uint8_t u8_t; typedef uint16_t u16_t; typedef uint32_t u32_t; typedef int32_t s32_t; typedef unsigned short uip_stats_t; - +/*---------------------------------------------------------------------------*/ #define MULTICHAN_CONF_SET_CHANNEL(x) #define MULTICHAN_CONF_READ_RSSI(x) 0 - +/*---------------------------------------------------------------------------*/ #endif /* __PLATFORM_CONF_H__ */ +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/spirit1-arch.c b/platform/stm32nucleo-spirit1/spirit1-arch.c index 2d3a9218f..762399d11 100644 --- a/platform/stm32nucleo-spirit1/spirit1-arch.c +++ b/platform/stm32nucleo-spirit1/spirit1-arch.c @@ -34,47 +34,48 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ #include "stm32l1xx.h" #include "spirit1-arch.h" #include "spirit1.h" - -extern void spirit1_interrupt_callback(void); -SpiritBool spiritdk_timer_expired = S_FALSE; +#include "st-lib.h" /*---------------------------------------------------------------------------*/ +extern void spirit1_interrupt_callback(void); +st_lib_spirit_bool spiritdk_timer_expired = S_FALSE; /*---------------------------------------------------------------------------*/ /* use the SPI-port to acquire the status bytes from the radio. */ #define CS_TO_SCLK_DELAY 0x0100 -extern SPI_HandleTypeDef pSpiHandle; +/*---------------------------------------------------------------------------*/ +extern st_lib_spi_handle_typedef st_lib_p_spi_handle; +/*---------------------------------------------------------------------------*/ uint16_t spirit1_arch_refresh_status(void) { - volatile uint16_t mcstate = 0x0000; uint8_t header[2]; header[0]=0x01; header[1]=MC_STATE1_BASE; - uint32_t SpiTimeout = ((uint32_t)1000); /*IDR & RADIO_SPI_CS_PIN)) +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +#define IRQ_ENABLE() st_lib_radio_gpio_interrupt_cmd(RADIO_GPIO_IRQ,0x0F,0x0F,ENABLE); +#define IRQ_DISABLE() st_lib_radio_gpio_interrupt_cmd(RADIO_GPIO_IRQ,0x0F,0x0F,DISABLE); +#define spirit_spi_busy() (!(RADIO_SPI_CS_PORT->IDR & RADIO_SPI_CS_PIN)) #define SPIRIT1_STATUS() (spirit1_arch_refresh_status() & SPIRIT1_STATE_STATEBITS) - +/*---------------------------------------------------------------------------*/ uint16_t spirit1_arch_refresh_status(void); - - - +/*---------------------------------------------------------------------------*/ #endif /* __SPIRIT1_ARCH_H__ */ diff --git a/platform/stm32nucleo-spirit1/spirit1-config.h b/platform/stm32nucleo-spirit1/spirit1-config.h index a4e93f3d2..44ba6ac52 100644 --- a/platform/stm32nucleo-spirit1/spirit1-config.h +++ b/platform/stm32nucleo-spirit1/spirit1-config.h @@ -29,28 +29,18 @@ * This file is part of the Contiki operating system. * */ -/* - * \file - * spirit1-config.h - * \author - * Marcus Lunden > - * \desc - * configuration for the Spirit1 radio transceiver - * - */ - +/*---------------------------------------------------------------------------*/ #ifndef __SPIRIT1_CONFIG_H__ #define __SPIRIT1_CONFIG_H__ - +/*---------------------------------------------------------------------------*/ #include "radio.h" #include "SPIRIT_Config.h" #include "spirit1-const.h" - +/*---------------------------------------------------------------------------*/ #define CCA_THRESHOLD -98.0 /* dBm */ #define XTAL_FREQUENCY 50000000 /* Hz */ #define SPIRIT_MAX_FIFO_LEN 96 - - +/*---------------------------------------------------------------------------*/ /** * The MAX_PACKET_LEN is an arbitrary value used to define the two array @@ -59,12 +49,11 @@ * and in direct mode (without packet handler) there is no limit of data. */ #define MAX_PACKET_LEN SPIRIT_MAX_FIFO_LEN - +/*---------------------------------------------------------------------------*/ /** * Spirit1 IC version */ #define SPIRIT1_VERSION SPIRIT_VERSION_3_0 - - +/*---------------------------------------------------------------------------*/ #endif /* __SPIRIT1_CONFIG_H__ */ - +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/spirit1-const.h b/platform/stm32nucleo-spirit1/spirit1-const.h index a6555097c..e1ab6cd5d 100644 --- a/platform/stm32nucleo-spirit1/spirit1-const.h +++ b/platform/stm32nucleo-spirit1/spirit1-const.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, Thingsquare, http://www.thingsquare.com/. + * Copyright (c) 2012, STMicroelectronics. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,25 +28,14 @@ * OF THE POSSIBILITY OF SUCH DAMAGE. * */ - -/* - * \file - * spirit1-const.h - * \author - * Marcus Lunden > - * \desc - * Spirit1 constants - * - * - */ - +/*---------------------------------------------------------------------------*/ #ifndef __SPIRIT1_CONST_H__ #define __SPIRIT1_CONST_H__ - - +/*---------------------------------------------------------------------------*/ /* The state bitfield and values for different states, as read from MC_STATE[1:0] registers, which are returned on any SPI read or write operation. */ #define SPIRIT1_STATE_STATEBITS (0x00FE) +/*---------------------------------------------------------------------------*/ #define SPIRIT1_STATE_STANDBY ((0x0040)<<1) #define SPIRIT1_STATE_SLEEP ((0x0036)<<1) @@ -60,8 +49,7 @@ which are returned on any SPI read or write operation. */ #define SPIRIT1_STATE_SYNTH_SETUP ((0x0053)<<1) #define SPIRIT1_STATE_PROTOCOL ((0x001F)<<1) #define SPIRIT1_STATE_SYNTH_CALIBRATION ((0x004F)<<1) - - +/*---------------------------------------------------------------------------*/ /* strobe commands */ #define SPIRIT1_STROBE_TX 0x60 #define SPIRIT1_STROBE_RX 0x61 @@ -72,7 +60,6 @@ which are returned on any SPI read or write operation. */ #define SPIRIT1_STROBE_SRES 0x70 #define SPIRIT1_STROBE_FRX 0x71 #define SPIRIT1_STROBE_FTX 0x72 - - +/*---------------------------------------------------------------------------*/ #endif /* __SPIRIT1_CONST_H__ */ - +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/spirit1.c b/platform/stm32nucleo-spirit1/spirit1.c index e8c9abed5..3c9cc679e 100644 --- a/platform/stm32nucleo-spirit1/spirit1.c +++ b/platform/stm32nucleo-spirit1/spirit1.c @@ -34,8 +34,7 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/*---------------------------------------------------------------------------*/ #include "spirit1.h" #include "spirit1-arch.h" #include "stm32l1xx.h" @@ -46,9 +45,11 @@ #include "net/rime/rimestats.h" #include "spirit1-arch.h" #include - -extern SpiritIrqs xIrqStatus; -extern volatile FlagStatus rx_timeout; +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +//MGR extern st_lib_spirit_irqs st_lib_x_irq_status; +extern volatile st_lib_spirit_flag_status rx_timeout; +/*---------------------------------------------------------------------------*/ #define XXX_ACK_WORKAROUND 1 /*---------------------------------------------------------------------------*/ #define DEBUG 0 @@ -59,6 +60,7 @@ extern volatile FlagStatus rx_timeout; #define PRINTF(...) #endif +/*---------------------------------------------------------------------------*/ #define BUSYWAIT_UNTIL(cond, max_time) \ do { \ rtimer_clock_t t0; \ @@ -72,15 +74,14 @@ extern volatile FlagStatus rx_timeout; #define IS_TXBUF_EMPTY() (spirit_txbuf[0] == 0) #define IS_RXBUF_EMPTY() (spirit_rxbuf[0] == 0) #define IS_RXBUF_FULL() (spirit_rxbuf[0] != 0) - +/*---------------------------------------------------------------------------*/ /* transceiver state. */ #define ON 0 #define OFF 1 - - /*---------------------------------------------------------------------------*/ static volatile unsigned int spirit_on = OFF; static volatile uint8_t receiving_packet = 0; +/*---------------------------------------------------------------------------*/ /* * The buffers which hold incoming data. * The +1 because of the first byte, @@ -88,8 +89,8 @@ static volatile uint8_t receiving_packet = 0; */ static uint8_t spirit_rxbuf[MAX_PACKET_LEN+1]; static uint8_t spirit_txbuf[MAX_PACKET_LEN+1-SPIRIT_MAX_FIFO_LEN]; -void SpiritManagementSetFrequencyBase(uint32_t lFBase); - +void st_lib_spirit_management_set_frequency_base(uint32_t); +/*---------------------------------------------------------------------------*/ static int just_got_an_ack = 0; /* Interrupt callback just detected an ack */ #if NULLRDC_CONF_802154_AUTOACK #define ACK_LEN 3 @@ -98,9 +99,7 @@ static int wants_an_ack = 0; /* The packet sent expects an ack */ //#define ACKPRINTF printf #define ACKPRINTF(...) #endif /* NULLRDC_CONF_802154_AUTOACK */ - /*---------------------------------------------------------------------------*/ - static int packet_is_prepared = 0; /*---------------------------------------------------------------------------*/ PROCESS(spirit_radio_process, "SPIRIT radio driver"); @@ -129,14 +128,6 @@ const struct radio_driver spirit_radio_driver = spirit_radio_on, spirit_radio_off, }; -/*---------------------------------------------------------------------------*/ -/* convienience macro for reading the MC_STATE[1] register from Spirit1, to be used like eg - if(SPIRIT1_STATUS() == SPIRIT1_STATE_READY) { - } - or - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, RTIMER_SECOND/1000); -*/ - /*---------------------------------------------------------------------------*/ void spirit1_printstatus(void) @@ -159,28 +150,21 @@ spirit1_printstatus(void) static void spirit1_strobe(uint8_t s) { - SpiritCmdStrobeCommand(s); + st_lib_spirit_cmd_strobe_command(s); } /*---------------------------------------------------------------------------*/ -/** -* @brief Puts the SPIRIT1 in READY state. -* @param None -* @retval None -*/ -void SpiritSetReadyState(void) +void spirit_set_ready_state(void) { PRINTF("READY IN\n"); - SpiritIrqClearStatus(); + st_lib_spirit_irq_clear_status(); IRQ_DISABLE(); if(SPIRIT1_STATUS() == SPIRIT1_STATE_STANDBY) { spirit1_strobe(SPIRIT1_STROBE_READY); -/* SpiritCmdStrobeReady();*/ } else if(SPIRIT1_STATUS() == SPIRIT1_STATE_RX) { spirit1_strobe(SPIRIT1_STROBE_SABORT); -/* SpiritCmdStrobeSabort();*/ - SpiritIrqClearStatus(); + st_lib_spirit_irq_clear_status(); } IRQ_ENABLE(); @@ -194,19 +178,19 @@ spirit_radio_init(void) PRINTF("RADIO INIT IN\n"); - SpiritSpiInit(); + st_lib_spirit_spi_init(); /* Configure radio shut-down (SDN) pin and activate radio */ - RadioGpioInit(RADIO_GPIO_SDN, RADIO_MODE_GPIO_OUT); + st_lib_radio_gpio_init(RADIO_GPIO_SDN, RADIO_MODE_GPIO_OUT); /* Configures the SPIRIT1 library */ - SpiritRadioSetXtalFrequency(XTAL_FREQUENCY); - SpiritManagementSetFrequencyBase(XTAL_FREQUENCY); + st_lib_spirit_radio_set_xtal_frequency(XTAL_FREQUENCY); + st_lib_spirit_management_set_frequency_base(XTAL_FREQUENCY); /* wake up to READY state */ /* weirdly enough, this *should* actually *set* the pin, not clear it! The pins is declared as GPIO_pin13 == 0x2000 */ RADIO_GPIO_SDN_PORT->BSRR = RADIO_GPIO_SDN_PIN; - HAL_GPIO_WritePin(RADIO_GPIO_SDN_PORT, RADIO_GPIO_SDN_PIN,GPIO_PIN_RESET); + st_lib_hal_gpio_write_pin(RADIO_GPIO_SDN_PORT, RADIO_GPIO_SDN_PIN,GPIO_PIN_RESET); /* wait minimum 1.5 ms to allow SPIRIT1 a proper boot-up sequence */ BUSYWAIT_UNTIL(0, 3 * RTIMER_SECOND/2000); @@ -215,7 +199,7 @@ spirit_radio_init(void) spirit1_strobe(SPIRIT1_STROBE_SRES); /* Configures the SPIRIT1 radio part */ - SRadioInit xRadioInit = { + st_lib_s_radio_init x_radio_init = { // XTAL_FREQUENCY, XTAL_OFFSET_PPM, BASE_FREQUENCY, @@ -226,13 +210,13 @@ spirit_radio_init(void) FREQ_DEVIATION, BANDWIDTH }; - SpiritRadioInit(&xRadioInit); - SpiritRadioSetXtalFrequency(XTAL_FREQUENCY); - SpiritRadioSetPALeveldBm(0,POWER_DBM); - SpiritRadioSetPALevelMaxIndex(0); + st_lib_spirit_radio_init(&x_radio_init); + st_lib_spirit_radio_set_xtal_frequency(XTAL_FREQUENCY); + st_lib_spirit_radio_set_pa_level_dbm(0,POWER_DBM); + st_lib_spirit_radio_set_pa_level_max_index(0); /* Configures the SPIRIT1 packet handler part*/ - PktBasicInit xBasicInit = { + st_lib_pkt_basic_init x_basic_init = { PREAMBLE_LENGTH, SYNC_LENGTH, SYNC_WORD, @@ -244,26 +228,26 @@ spirit_radio_init(void) EN_FEC, EN_WHITENING }; - SpiritPktBasicInit(&xBasicInit); + st_lib_spirit_pkt_basic_init(&x_basic_init); /* Enable the following interrupt sources, routed to GPIO */ - SpiritIrqDeInit(NULL); - SpiritIrqClearStatus(); - SpiritIrq(TX_DATA_SENT, S_ENABLE); - SpiritIrq(RX_DATA_READY,S_ENABLE); - SpiritIrq(VALID_SYNC,S_ENABLE); - SpiritIrq(RX_DATA_DISC, S_ENABLE); - SpiritIrq(TX_FIFO_ERROR, S_ENABLE); - SpiritIrq(RX_FIFO_ERROR, S_ENABLE); + st_lib_spirit_irq_de_init(NULL); + st_lib_spirit_irq_clear_status(); + st_lib_spirit_irq(TX_DATA_SENT, S_ENABLE); + st_lib_spirit_irq(RX_DATA_READY,S_ENABLE); + st_lib_spirit_irq(VALID_SYNC,S_ENABLE); + st_lib_spirit_irq(RX_DATA_DISC, S_ENABLE); + st_lib_spirit_irq(TX_FIFO_ERROR, S_ENABLE); + st_lib_spirit_irq(RX_FIFO_ERROR, S_ENABLE); /* Configure Spirit1 */ - SpiritRadioPersistenRx(S_ENABLE); - SpiritQiSetSqiThreshold(SQI_TH_0); - SpiritQiSqiCheck(S_ENABLE); - SpiritQiSetRssiThresholddBm(CCA_THRESHOLD); - SpiritTimerSetRxTimeoutStopCondition(SQI_ABOVE_THRESHOLD); + st_lib_spirit_radio_persisten_rx(S_ENABLE); + st_lib_spirit_qi_set_sqi_threshold(SQI_TH_0); + st_lib_spirit_qi_sqi_check(S_ENABLE); + st_lib_spirit_qi_set_rssi_threshold_dbm(CCA_THRESHOLD); + st_lib_spirit_timer_set_rx_timeout_stop_condition(SQI_ABOVE_THRESHOLD); SET_INFINITE_RX_TIMEOUT(); - SpiritRadioAFCFreezeOnSync(S_ENABLE); + st_lib_spirit_radio_afc_freeze_on_sync(S_ENABLE); /* Puts the SPIRIT1 in STANDBY mode (125us -> rx/tx) */ spirit1_strobe(SPIRIT1_STROBE_STANDBY); @@ -272,18 +256,16 @@ spirit_radio_init(void) CLEAR_TXBUF(); /* Initializes the mcu pin as input, used for IRQ */ - RadioGpioInit(RADIO_GPIO_IRQ, RADIO_MODE_EXTI_IN); + st_lib_radio_gpio_init(RADIO_GPIO_IRQ, RADIO_MODE_EXTI_IN); /* Configure the radio to route the IRQ signal to its GPIO 3 */ - SpiritGpioInit(&(SGpioInit){SPIRIT_GPIO_IRQ, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, SPIRIT_GPIO_DIG_OUT_IRQ}); + st_lib_spirit_gpio_init(&(st_lib_s_gpio_init){SPIRIT_GPIO_IRQ, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, SPIRIT_GPIO_DIG_OUT_IRQ}); process_start(&spirit_radio_process, NULL); PRINTF("Spirit1 init done\n"); return 0; } - - /*---------------------------------------------------------------------------*/ static int spirit_radio_prepare(const void *payload, unsigned short payload_len) @@ -312,8 +294,8 @@ spirit_radio_prepare(const void *payload, unsigned short payload_len) /* Sets the length of the packet to send */ IRQ_DISABLE(); spirit1_strobe(SPIRIT1_STROBE_FTX); - SpiritPktBasicSetPayloadLength(payload_len); - SpiritSpiWriteLinearFifo(payload_len, (uint8_t *)payload); + st_lib_spirit_pkt_basic_set_payload_length(payload_len); + st_lib_spirit_spi_write_linear_fifo(payload_len, (uint8_t *)payload); IRQ_ENABLE(); PRINTF("PREPARE OUT\n"); @@ -339,7 +321,7 @@ spirit_radio_transmit(unsigned short payload_len) /* Puts the SPIRIT1 in TX state */ receiving_packet = 0; - SpiritSetReadyState(); + spirit_set_ready_state(); spirit1_strobe(SPIRIT1_STROBE_TX); just_got_an_ack = 0; BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); @@ -350,7 +332,7 @@ spirit_radio_transmit(unsigned short payload_len) CLEAR_TXBUF(); CLEAR_RXBUF(); IRQ_DISABLE(); - SpiritIrqClearStatus(); + st_lib_spirit_irq_clear_status(); spirit1_strobe(SPIRIT1_STROBE_SABORT); BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); spirit1_strobe(SPIRIT1_STROBE_READY); @@ -454,20 +436,20 @@ spirit_radio_channel_clear(void) IRQ_DISABLE(); spirit1_strobe(SPIRIT1_STROBE_SABORT); /* SpiritCmdStrobeSabort();*/ - SpiritIrqClearStatus(); + st_lib_spirit_irq_clear_status(); IRQ_ENABLE(); { rtimer_clock_t timeout = RTIMER_NOW() + 5 * RTIMER_SECOND/1000; do { - SpiritRefreshStatus(); - } while((g_xStatus.MC_STATE != MC_STATE_READY) && (RTIMER_NOW() < timeout)); + st_lib_spirit_refresh_status(); + } while((st_lib_g_x_status.MC_STATE != MC_STATE_READY) && (RTIMER_NOW() < timeout)); if(RTIMER_NOW() < timeout) { return 1; } } /* Stores the RSSI value */ - rssi_value = SpiritQiGetRssidBm(); + rssi_value = st_lib_spirit_qi_get_rssi_dbm(); /* Puts the SPIRIT1 in its previous state */ if(spirit_state==OFF) { @@ -513,7 +495,7 @@ spirit_radio_off(void) spirit1_strobe(SPIRIT1_STROBE_SABORT); /* Clear any pending irqs */ - SpiritIrqClearStatus(); + st_lib_spirit_irq_clear_status(); BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND/1000); if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) { @@ -537,21 +519,18 @@ spirit_radio_off(void) return 0; } /*---------------------------------------------------------------------------*/ - static int spirit_radio_on(void) { PRINTF("Spirit1: on\n"); spirit1_strobe(SPIRIT1_STROBE_SABORT); BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); - if(spirit_on == OFF) - { + if(spirit_on == OFF) { IRQ_DISABLE(); /* ensure we are in READY state as we go from there to Rx */ spirit1_strobe(SPIRIT1_STROBE_READY); BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND/1000); - if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) - { + if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) { PRINTF("Spirit1: failed to turn on\n"); while(1); //return 1; @@ -560,8 +539,7 @@ static int spirit_radio_on(void) /* now we go to Rx */ spirit1_strobe(SPIRIT1_STROBE_RX); BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 5 * RTIMER_SECOND/1000); - if(SPIRIT1_STATUS() != SPIRIT1_STATE_RX) - { + if(SPIRIT1_STATUS() != SPIRIT1_STATE_RX) { PRINTF("Spirit1: failed to enter rx\n"); while(1); //return 1; @@ -613,10 +591,10 @@ PROCESS_THREAD(spirit_radio_process, ev, data) }; IRQ_DISABLE(); spirit1_strobe(SPIRIT1_STROBE_FTX); - SpiritPktBasicSetPayloadLength((uint16_t) ACK_LEN); - SpiritSpiWriteLinearFifo((uint16_t) ACK_LEN, (uint8_t *) ack_frame); + st_lib_spirit_pkt_basic_set_payload_length((uint16_t) ACK_LEN); + st_lib_spirit_spi_write_linear_fifo((uint16_t) ACK_LEN, (uint8_t *) ack_frame); - SpiritSetReadyState(); + spirit_set_ready_state(); IRQ_ENABLE(); spirit1_strobe(SPIRIT1_STROBE_TX); BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); @@ -630,7 +608,8 @@ PROCESS_THREAD(spirit_radio_process, ev, data) packetbuf_set_datalen(len); NETSTACK_RDC.input(); } - if(!IS_RXBUF_EMPTY()){ + + if(!IS_RXBUF_EMPTY()) { process_poll(&spirit_radio_process); } @@ -641,7 +620,6 @@ PROCESS_THREAD(spirit_radio_process, ev, data) spirit1_strobe(SPIRIT1_STROBE_RX); BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND/1000); } - } } @@ -652,9 +630,8 @@ void spirit1_interrupt_callback(void) { #define INTPRINTF(...) // PRINTF - SpiritIrqs xIrqStatus; - if (SpiritSPIBusy() || interrupt_callback_in_progress) - { + st_lib_spirit_irqs x_irq_status; + if (spirit_spi_busy() || interrupt_callback_in_progress) { process_poll(&spirit_radio_process); interrupt_callback_wants_poll = 1; return; @@ -664,18 +641,17 @@ spirit1_interrupt_callback(void) interrupt_callback_in_progress = 1; /* get interrupt source from radio */ - SpiritIrqGetStatus(&xIrqStatus); - SpiritIrqClearStatus(); + st_lib_spirit_irq_get_status(&x_irq_status); + st_lib_spirit_irq_clear_status(); - if(xIrqStatus.IRQ_RX_FIFO_ERROR) - { + if(x_irq_status.IRQ_RX_FIFO_ERROR) { receiving_packet = 0; interrupt_callback_in_progress = 0; spirit1_strobe(SPIRIT1_STROBE_FRX); return; } - if(xIrqStatus.IRQ_TX_FIFO_ERROR) - { + + if(x_irq_status.IRQ_TX_FIFO_ERROR) { receiving_packet = 0; interrupt_callback_in_progress = 0; spirit1_strobe(SPIRIT1_STROBE_FTX); @@ -683,15 +659,13 @@ spirit1_interrupt_callback(void) } /* The IRQ_VALID_SYNC is used to notify a new packet is coming */ - if(xIrqStatus.IRQ_VALID_SYNC) - { + if(x_irq_status.IRQ_VALID_SYNC) { INTPRINTF("SYNC\n"); receiving_packet = 1; } /* The IRQ_TX_DATA_SENT notifies the packet received. Puts the SPIRIT1 in RX */ - if(xIrqStatus.IRQ_TX_DATA_SENT) - { + if(x_irq_status.IRQ_TX_DATA_SENT) { spirit1_strobe(SPIRIT1_STROBE_RX); /* SpiritCmdStrobeRx();*/ INTPRINTF("SENT\n"); @@ -701,14 +675,15 @@ spirit1_interrupt_callback(void) } /* The IRQ_RX_DATA_READY notifies a new packet arrived */ - if(xIrqStatus.IRQ_RX_DATA_READY) { - SpiritSpiReadLinearFifo(SpiritLinearFifoReadNumElementsRxFifo(), &spirit_rxbuf[1]); - spirit_rxbuf[0] = SpiritPktBasicGetReceivedPktLength(); + if(x_irq_status.IRQ_RX_DATA_READY) { + st_lib_spirit_spi_read_linear_fifo(st_lib_spirit_linear_fifo_read_num_elements_rx_fifo(), + &spirit_rxbuf[1]); + spirit_rxbuf[0] = st_lib_spirit_pkt_basic_get_received_pkt_length(); spirit1_strobe(SPIRIT1_STROBE_FRX); INTPRINTF("RECEIVED\n"); - process_poll(&spirit_radio_process); + process_poll(&spirit_radio_process); receiving_packet = 0; @@ -723,18 +698,15 @@ spirit1_interrupt_callback(void) return; } - if(xIrqStatus.IRQ_RX_DATA_DISC) + if(x_irq_status.IRQ_RX_DATA_DISC) { /* RX command - to ensure the device will be ready for the next reception */ - if(xIrqStatus.IRQ_RX_TIMEOUT) - { - SpiritCmdStrobeFlushRxFifo(); + if(x_irq_status.IRQ_RX_TIMEOUT) { + st_lib_spirit_cmd_strobe_flush_rx_fifo(); rx_timeout = SET; } - } interrupt_callback_in_progress = 0; } - /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/spirit1.h b/platform/stm32nucleo-spirit1/spirit1.h index 3c29abbf7..5f151846b 100644 --- a/platform/stm32nucleo-spirit1/spirit1.h +++ b/platform/stm32nucleo-spirit1/spirit1.h @@ -29,30 +29,18 @@ * This file is part of the Contiki operating system. * */ - -/* - * \file - * spirit1.h - * \author - * Marcus Lunden > - * \desc - * Spirit1 radio driver - * - * - */ - - - +/*---------------------------------------------------------------------------*/ #ifndef __SPIRIT_H__ #define __SPIRIT_H__ - +/*---------------------------------------------------------------------------*/ #include "radio.h" #include "SPIRIT_Config.h" #include "spirit1-config.h" #include "spirit1_appli.h" #include "spirit1-const.h" - +/*---------------------------------------------------------------------------*/ extern const struct radio_driver spirit_radio_driver; void spirit1_interrupt_callback(void); - +/*---------------------------------------------------------------------------*/ #endif /* __SPIRIT_H__ */ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/st-lib.h b/platform/stm32nucleo-spirit1/st-lib.h new file mode 100644 index 000000000..cf6930110 --- /dev/null +++ b/platform/stm32nucleo-spirit1/st-lib.h @@ -0,0 +1,357 @@ +/** +****************************************************************************** +* @file st-lib.h +* @author System LAB +* @version V1.0.0 +* @date 30-July-2015 +* @brief Contiki style wrapping library for STM32Cube HAL APIs +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/*---------------------------------------------------------------------------*/ +/** + * \defgroup stm32nucleo-spirit1 STM32Cube HAL APIs + * + * Abstraction of STM32Cube HAL APIs as per Contiki coding rules + * @{ + * + * \file + * Header file for the STM32Cube HAL APIs + */ +/*---------------------------------------------------------------------------*/ +#ifndef ST_LIB_H_ +#define ST_LIB_H_ + +/*---------------------------------------------------------------------------*/ +/* extern global varialbles */ +#define st_lib_uart_handle UartHandle + +#define st_lib_g_x_status g_xStatus + +#define st_lib_p_spi_handle pSpiHandle +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* misc */ +#define st_lib_tim2_irq_handler(...) TIM2_IRQHandler(__VA_ARGS__) +#define st_lib_spirit_management_set_frequency_base(...) SpiritManagementSetFrequencyBase(__VA_ARGS__) +#define st_lib_sys_tick_handler(...) SysTick_Handler(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* MCU_Interface.h */ +#include "MCU_Interface.h" + +#define st_lib_spirit_spi_init(...) SpiritSpiInit(__VA_ARGS__) +#define st_lib_spirit_spi_read_linear_fifo(...) SpiritSpiReadLinearFifo(__VA_ARGS__) +#define st_lib_spirit_spi_write_linear_fifo(...) SpiritSpiWriteLinearFifo(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------*/ +/* radio_gpio.h */ +#include "radio_gpio.h" + +#define st_lib_radio_gpio_interrupt_cmd(...) RadioGpioInterruptCmd(__VA_ARGS__) +#define st_lib_radio_gpio_init(...) RadioGpioInit(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* radio_shield_config.h */ +#include "radio_shield_config.h" + +#define st_lib_a_led_gpio_port aLED_GPIO_PORT +#define st_lib_a_led_gpio_pin aLED_GPIO_PIN + +#define st_lib_radio_shield_led_init(...) RadioShieldLedInit(__VA_ARGS__) +#define st_lib_radio_shield_led_off(...) RadioShieldLedOff(__VA_ARGS__) +#define st_lib_radio_shield_led_on(...) RadioShieldLedOn(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* radio_spi.h */ +#include "radio_spi.h" + +#define st_lib_radio_spi_cs_high(...) RadioSpiCSHigh(__VA_ARGS__) +#define st_lib_radio_spi_cs_low(...) RadioSpiCSLow(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_Commands.h */ +#include "SPIRIT_Commands.h" + +#define st_lib_spirit_cmd_strobe_flush_rx_fifo(...) SpiritCmdStrobeFlushRxFifo(__VA_ARGS__) +#define st_lib_spirit_cmd_strobe_command(...) SpiritCmdStrobeCommand(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_Gpio.h */ +#include "SPIRIT_Gpio.h" + +#define st_lib_s_gpio_init SGpioInit + +#define st_lib_spirit_gpio_init(...) SpiritGpioInit(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_Irq.h */ +#include "SPIRIT_Irq.h" + +#define st_lib_spirit_irqs SpiritIrqs + +#define st_lib_spirit_irq(...) SpiritIrq(__VA_ARGS__) +#define st_lib_spirit_irq_de_init(...) SpiritIrqDeInit(__VA_ARGS__) +#define st_lib_spirit_irq_init(...) SpiritIrqInit(__VA_ARGS__) +#define st_lib_spirit_irq_get_mask(...) SpiritIrqGetMask(__VA_ARGS__) +#define st_lib_spirit_irq_get_status(...) SpiritIrqGetStatus(__VA_ARGS__) +#define st_lib_spirit_irq_clear_status(...) SpiritIrqClearStatus(__VA_ARGS__) +#define st_lib_spirit_irq_chack_flag(...) SpiritIrqCheckFlag(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_LinearFifo.h */ +#include "SPIRIT_LinearFifo.h" + +#define st_lib_spirit_linear_fifo_read_num_elements_rx_fifo(...) SpiritLinearFifoReadNumElementsRxFifo(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_PktBasic.h */ +#include "SPIRIT_PktBasic.h" + +#define st_lib_pkt_basic_init PktBasicInit + +#define st_lib_spirit_pkt_basic_init(...) SpiritPktBasicInit(__VA_ARGS__) +#define st_lib_spirit_pkt_basic_get_received_pkt_length(...) SpiritPktBasicGetReceivedPktLength(__VA_ARGS__) +#define st_lib_spirit_pkt_basic_set_payload_length(...) SpiritPktBasicSetPayloadLength(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_Qi.h */ +#include "SPIRIT_Qi.h" + +#define st_lib_spirit_qi_get_rssi_dbm(...) SpiritQiGetRssidBm(__VA_ARGS__) +#define st_lib_spirit_qi_pqi_check(...) SpiritQiPqiCheck(__VA_ARGS__) +#define st_lib_spirit_qi_sqi_check(...) SpiritQiSqiCheck(__VA_ARGS__) +#define st_lib_spirit_qi_set_pqi_threshold(...) SpiritQiSetPqiThreshold(__VA_ARGS__) +#define st_lib_spirit_qi_get_pqi_threshold(...) SpiritQiGetPqiThreshold(__VA_ARGS__) +#define st_lib_spirit_qi_set_sqi_threshold(...) SpiritQiSetSqiThreshold(__VA_ARGS__) +#define st_lib_spirit_qi_get_sqi_threshold(...) SpiritQiGetSqiThreshold(__VA_ARGS__) +#define st_lib_spirit_qi_set_rssi_threshold(...) SpiritQiSetRssiThreshold(__VA_ARGS__) +#define st_lib_spirit_qi_get_rssi_threshold(...) SpiritQiGetRssiThreshold(__VA_ARGS__) +#define st_lib_spirit_qi_compute_rssi_threshold(...) SpiritQiComputeRssiThreshold(__VA_ARGS__) +#define st_lib_spirit_qi_set_rssi_threshold_dbm(...) SpiritQiSetRssiThresholddBm(__VA_ARGS__) +#define st_lib_spirit_qi_get_pqi(...) SpiritQiGetPqi(__VA_ARGS__) +#define st_lib_spirit_qi_get_sqi(...) SpiritQiGetSqi(__VA_ARGS__) +#define st_lib_spirit_qi_get_lqi(...) SpiritQiGetLqi(__VA_ARGS__) +#define st_lib_spirit_qi_get_cs(...) SpiritQiGetCs(__VA_ARGS__) +#define st_lib_spirit_qi_get_rssi(...) SpiritQiGetRssi(__VA_ARGS__) +#define st_lib_spirit_qi_set_rssi_filter_gain(...) SpiritQiSetRssiFilterGain(__VA_ARGS__) +#define st_lib_spirit_qi_get_rssi_filter_gain(...) SpiritQiGetRssiFilterGain(__VA_ARGS__) +#define st_lib_spirit_qi_set_cs_mode(...) SpiritQiSetCsMode(__VA_ARGS__) +#define st_lib_spirit_qi_get_cs_mode(...) SpiritQiGetCsMode(__VA_ARGS__) +#define st_lib_spirit_qi_cs_timeout_mask(...) SpiritQiCsTimeoutMask(__VA_ARGS__) +#define st_lib_spirit_qi_pqi_timeout_mask(...) SpiritQiPqiTimeoutMask(__VA_ARGS__) +#define st_lib_spirit_qi_sqi_timeout_mask(...) SpiritQiSqiTimeoutMask(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_Radio.h */ +#include "SPIRIT_Radio.h" + +#define st_lib_s_radio_init SRadioInit + +#define st_lib_spirit_radio_afc_freeze_on_sync(...) SpiritRadioAFCFreezeOnSync(__VA_ARGS__) +#define st_lib_spirit_radio_init(...) SpiritRadioInit(__VA_ARGS__) +#define st_lib_spirit_radio_persisten_rx(...) SpiritRadioPersistenRx(__VA_ARGS__) +#define st_lib_spirit_radio_set_pa_level_dbm(...) SpiritRadioSetPALeveldBm(__VA_ARGS__) +#define st_lib_spirit_radio_set_pa_level_max_index(...) SpiritRadioSetPALevelMaxIndex(__VA_ARGS__) +#define st_lib_spirit_radio_set_xtal_frequency(...) SpiritRadioSetXtalFrequency(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_Timer.h */ +#include "SPIRIT_Timer.h" + +#define st_lib_spirit_timer_set_rx_timeout_stop_condition(...) SpiritTimerSetRxTimeoutStopCondition(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* SPIRIT_Types.h */ +#include "SPIRIT_Types.h" + +#define st_lib_spirit_bool SpiritBool +#define st_lib_spirit_status SpiritStatus +#define st_lib_spirit_flag_status SpiritFlagStatus + +#define st_lib_spirit_refresh_status(...) SpiritRefreshStatus(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* stm32l152xe.h */ +#include "stm32l152xe.h" + +#define st_lib_irq_n_type IRQn_Type +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* stm32l1xx.h */ +#include "stm32l1xx.h" + +#define st_lib_flag_status FlagStatus +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* stm32l1xx_hal_cortex.h */ +#include "stm32l1xx_hal_cortex.h" + +#define st_lib_hal_nvic_enable_irq(...) HAL_NVIC_EnableIRQ(__VA_ARGS__) +#define st_lib_hal_nvic_set_priority(...) HAL_NVIC_SetPriority(__VA_ARGS__) +#define st_lib_hal_systick_clk_source_config(...) HAL_SYSTICK_CLKSourceConfig(__VA_ARGS__) +#define st_lib_hal_systick_config(...) HAL_SYSTICK_Config(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* stm32l1xx_hal_rcc.h */ +#include "stm32l1xx_hal_rcc.h" + + +#define st_lib_tim2_clk_enable(...) __TIM2_CLK_ENABLE(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* stm32l1xx_hal_spi.h */ +#include "stm32l1xx_hal_spi.h" + +#define st_lib_spi_handle_typedef SPI_HandleTypeDef + +#define st_lib_hal_spi_get_flag(...) __HAL_SPI_GET_FLAG(__VA_ARGS__) +#define st_lib_hal_spi_transmit_receive(...) HAL_SPI_TransmitReceive(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* stm32l1xx_hal_tim.h */ +#include "stm32l1xx_hal_tim.h" + +#define st_lib_tim_handle_typedef TIM_HandleTypeDef +#define st_lib_tim_clock_config_typedef TIM_ClockConfigTypeDef +#define st_lib_tim_oc_init_typedef TIM_OC_InitTypeDef + +#define st_lib_hal_tim_base_init(...) HAL_TIM_Base_Init(__VA_ARGS__) +#define st_lib_hal_tim_base_start_it(...) HAL_TIM_Base_Start_IT(__VA_ARGS__) +#define st_lib_hal_tim_config_clock_source(...) HAL_TIM_ConfigClockSource(__VA_ARGS__) +#define st_lib_hal_tim_clear_flag(...) __HAL_TIM_CLEAR_FLAG(__VA_ARGS__) +#define st_lib_hal_tim_clear_it(...) __HAL_TIM_CLEAR_IT(__VA_ARGS__) +#define st_lib_hal_tim_enable(...) __HAL_TIM_ENABLE(__VA_ARGS__) +#define st_lib_hal_tim_enable_it(...) __HAL_TIM_ENABLE_IT(__VA_ARGS__) +#define st_lib_hal_tim_oc_init(...) HAL_TIM_OC_Init(__VA_ARGS__) +#define st_lib_hal_tim_oc_config_channel(...) HAL_TIM_OC_ConfigChannel(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------*/ +/* stm32l1xx_hal_uart.h */ +#include "stm32l1xx_hal_uart.h" + +#define st_lib_uart_handle_typedef UART_HandleTypeDef + +#define st_lib_hal_uart_enable_it(...) __HAL_UART_ENABLE_IT(__VA_ARGS__) +#define st_lib_hal_uart_init(...) HAL_UART_Init(__VA_ARGS__) +#define st_lib_hal_uart_receive(...) HAL_UART_Receive(__VA_ARGS__) +#define st_lib_hal_uart_receive_it(...) HAL_UART_Receive_IT(__VA_ARGS__) +#define st_lib_hal_uart_rx_cplt_callback(...) HAL_UART_RxCpltCallback(__VA_ARGS__) +#define st_lib_hal_uart_transmit(...) HAL_UART_Transmit(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* stm32l1xx_nucleo.h */ +#include "stm32l1xx_nucleo.h" + +#define st_lib_gpio_typedef GPIO_TypeDef +#define st_lib_gpio_port GPIO_PORT +#define st_lib_gpio_pin GPIO_PIN + +#define st_lib_bsp_led_init(...) BSP_LED_Init(__VA_ARGS__) +#define st_lib_bsp_led_off(...) BSP_LED_Off(__VA_ARGS__) +#define st_lib_bsp_led_on(...) BSP_LED_On(__VA_ARGS__) +#define st_lib_bsp_pb_init(...) BSP_PB_Init(__VA_ARGS__) +#define st_lib_bsp_pb_get_state(...) BSP_PB_GetState(__VA_ARGS__) +#define st_lib_hal_gpio_read_pin(...) HAL_GPIO_ReadPin(__VA_ARGS__) +#define st_lib_hal_gpio_write_pin(...) HAL_GPIO_WritePin(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +#if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ +/* x_nucleo_iks01a1.h */ +#include "x_nucleo_iks01a1.h" + +#define st_lib_axes_raw_typedef AxesRaw_TypeDef +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* x_nucleo_iks01a1_hum_temp.h */ +#include "x_nucleo_iks01a1_hum_temp.h" + +#define st_lib_bsp_hum_temp_is_initialized(...) BSP_HUM_TEMP_isInitialized(__VA_ARGS__) +#define st_lib_bsp_hum_temp_init(...) BSP_HUM_TEMP_Init(__VA_ARGS__) +#define st_lib_bsp_hum_temp_get_humidity(...) BSP_HUM_TEMP_GetHumidity(__VA_ARGS__) +#define st_lib_bsp_hum_temp_get_temperature(...) BSP_HUM_TEMP_GetTemperature(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* x_nucleo_iks01a1_imu_6axes.h */ +#include "x_nucleo_iks01a1_imu_6axes.h" + +#define st_lib_bsp_imu_6axes_is_initialized(...) BSP_IMU_6AXES_isInitialized(__VA_ARGS__) +#define st_lib_bsp_imu_6axes_init(...) BSP_IMU_6AXES_Init(__VA_ARGS__) +#define st_lib_bsp_imu_6axes_g_get_axes_raw(...) BSP_IMU_6AXES_G_GetAxesRaw(__VA_ARGS__) +#define st_lib_bsp_imu_6axes_x_get_axes_raw(...) BSP_IMU_6AXES_X_GetAxesRaw(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* x_nucleo_iks01a1_magneto.h */ +#include "x_nucleo_iks01a1_magneto.h" + +#define st_lib_bsp_magneto_m_get_axes_raw(...) BSP_MAGNETO_M_GetAxesRaw(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* x_nucleo_iks01a1_pressure.h */ +#include "x_nucleo_iks01a1_pressure.h" + +#define st_lib_bsp_pressure_init(...) BSP_PRESSURE_Init(__VA_ARGS__) +#define st_lib_bsp_pressure_get_pressure(...) BSP_PRESSURE_GetPressure(__VA_ARGS__) +/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +#endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +#endif /*ST_LIB_H_*/ +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/spirit1_appli.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/spirit1_appli.h deleted file mode 100644 index 1d392e59b..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/spirit1_appli.h +++ /dev/null @@ -1,233 +0,0 @@ -/** - ****************************************************************************** - * @file spirit1_appli.h - * @author System Lab - NOIDA - * @version V1.1.0 - * @date 14-Aug-2014 - * @brief Header for spirit1_appli.c module - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SPIRIT1_APPLI_H -#define __SPIRIT1_APPLI_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" -#include "radio_shield_config.h" -#include "MCU_Interface.h" -#include "SPIRIT_Config.h" -#include "stm32l1xx_nucleo.h" - - -/* Exported macro ------------------------------------------------------------*/ - -#if defined(X_NUCLEO_IDS01A3) - #define USE_SPIRIT1_433MHz -#elif defined(X_NUCLEO_IDS01A4) - #define USE_SPIRIT1_868MHz -#elif defined(X_NUCLEO_IDS01A5) - #define USE_SPIRIT1_915MHz -#else -#error SPIRIT1 Nucleo Shield undefined or unsupported -#endif - -/* Uncomment the Link Layer features to be used */ -// #define USE_AUTO_ACK -// #define USE_AUTO_ACK_PIGGYBACKING -// #define USE_AUTO_RETRANSMISSION - -#if defined(USE_AUTO_ACK)&& defined(USE_AUTO_ACK_PIGGYBACKING)&& defined(USE_AUTO_RETRANSMISSION) -#define USE_STack_PROTOCOL - -/* LLP configuration parameters */ -#define EN_AUTOACK S_ENABLE -#define EN_PIGGYBACKING S_ENABLE -#define MAX_RETRANSMISSIONS PKT_N_RETX_2 - -#else -#define USE_BASIC_PROTOCOL - -#endif - -/* Uncomment the system Operating mode */ -//#define USE_LOW_POWER_MODE - -#if defined (USE_LOW_POWER_MODE) -#define LPM_ENABLE -#define MCU_STOP_MODE -//#define MCU_SLEEP_MODE -//#define RF_STANDBY -#endif - - -/* Exported constants --------------------------------------------------------*/ - -/* Radio configuration parameters */ -#define XTAL_OFFSET_PPM 0 -#define INFINITE_TIMEOUT 0.0 - -#ifdef USE_SPIRIT1_433MHz -#define BASE_FREQUENCY 433.0e6 -#endif - -#ifdef USE_SPIRIT1_868MHz -#define BASE_FREQUENCY 868.0e6 -#endif - -#ifdef USE_SPIRIT1_915MHz -//#define BASE_FREQUENCY 915.0e6 -#define BASE_FREQUENCY 902.0e6 -#endif - - -/* Addresses configuration parameters */ -#define EN_FILT_MY_ADDRESS S_DISABLE -#define MY_ADDRESS 0x34 -#define EN_FILT_MULTICAST_ADDRESS S_DISABLE -#define MULTICAST_ADDRESS 0xEE -#define EN_FILT_BROADCAST_ADDRESS S_DISABLE -#define BROADCAST_ADDRESS 0xFF -#define DESTINATION_ADDRESS 0x44 -#define EN_FILT_SOURCE_ADDRESS S_DISABLE -#define SOURCE_ADDR_MASK 0xf0 -#define SOURCE_ADDR_REF 0x37 - -#define APPLI_CMD 0x11 -#define NWK_CMD 0x22 -#define LED_TOGGLE 0xff -#define ACK_OK 0x01 -#define MAX_BUFFER_LEN 96 -#define TIME_TO_EXIT_RX 3000 -#define DELAY_RX_LED_TOGGLE 200 -#define DELAY_TX_LED_GLOW 1000 -#define LPM_WAKEUP_TIME 100 -#define DATA_SEND_TIME 30 - -#define PREAMBLE_LENGTH PKT_PREAMBLE_LENGTH_04BYTES -#define SYNC_LENGTH PKT_SYNC_LENGTH_4BYTES -#define CONTROL_LENGTH PKT_CONTROL_LENGTH_0BYTES -#define EN_ADDRESS S_DISABLE -#define EN_FEC S_DISABLE -#define CHANNEL_NUMBER 0 -#define LENGTH_TYPE PKT_LENGTH_VAR -#define POWER_INDEX 7 -#define RECEIVE_TIMEOUT 2000.0 /*change the value for required timeout period*/ -#define RSSI_THRESHOLD -120 - - - -#define POWER_DBM 11.6 -#define CHANNEL_SPACE 100e3 -#define FREQ_DEVIATION 127e3 -#define BANDWIDTH 540.0e3 -#define MODULATION_SELECT GFSK_BT1 -#define DATARATE 250000 -#define XTAL_OFFSET_PPM 0 -#define SYNC_WORD 0x88888888 -#define LENGTH_WIDTH 8 -#define CRC_MODE PKT_CRC_MODE_16BITS_2 -#define EN_WHITENING S_DISABLE -#define INFINITE_TIMEOUT 0.0 - - -/* Exported types ------------------------------------------------------------*/ -//extern LPTIM_HandleTypeDef LptimHandle; -extern volatile FlagStatus xRxDoneFlag, xTxDoneFlag; -extern volatile FlagStatus PushButtonStatusWakeup; -extern uint16_t wakeupCounter; -extern uint16_t dataSendCounter ; -extern volatile FlagStatus PushButtonStatusData, datasendFlag; - -typedef struct sRadioDriver -{ - void ( *Init )( void ); - void ( *GpioIrq )( SGpioInit *pGpioIRQ ); - void ( *RadioInit )( SRadioInit *pRadioInit ); - void ( *SetRadioPower )( uint8_t cIndex, float fPowerdBm ); - void ( *PacketConfig )( void ); - void ( *SetPayloadLen )( uint8_t length); - void ( *SetDestinationAddress )( uint8_t address); - void ( *EnableTxIrq )( void ); - void ( *EnableRxIrq )( void ); - void ( *DisableIrq )(void); - void ( *SetRxTimeout )( float cRxTimeout ); - void ( *EnableSQI )(void); - void ( *SetRssiThreshold)(int dbmValue); - void ( *ClearIrqStatus )(void); - void ( *StartRx )( void ); - void ( *StartTx )( uint8_t *buffer, uint8_t size ); - void ( *GetRxPacket )( uint8_t *buffer, uint8_t size ); -}RadioDriver_t; - -typedef struct sMCULowPowerMode -{ - void ( *McuStopMode )( void ); - void ( *McuStandbyMode )( void ); - void ( *McuSleepMode )( void ); -}MCULowPowerMode_t; - -typedef struct sRadioLowPowerMode -{ - void ( *RadioShutDown )( void ); - void ( *RadioStandBy )( void ); - void ( *RadioSleep ) ( void ); - void ( *RadioPowerON )( void ); -}RadioLowPowerMode_t; - -typedef struct -{ - uint8_t Cmdtag; - uint8_t CmdType; - uint8_t CmdLen; - uint8_t Cmd; - uint8_t DataLen; - uint8_t* DataBuff; -}AppliFrame_t; - - -/* Exported functions ------------------------------------------------------- */ -void HAL_Spirit1_Init(void); -void Enter_LP_mode(void); -void Exit_LP_mode(void); -void MCU_Enter_StopMode(void); -void MCU_Enter_StandbyMode(void); -void MCU_Enter_SleepMode(void); -void RadioPowerON(void); -void RadioPowerOFF(void); -void RadioStandBy(void); -void RadioSleep(void); -void SPIRIT1_Init(void); -void BasicProtocolInit(void); -void Set_KeyStatus(FlagStatus val); - -#endif /* __SPIRIT1_APPLI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32cube_hal_init.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32cube_hal_init.h deleted file mode 100644 index e6aefade6..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32cube_hal_init.h +++ /dev/null @@ -1,87 +0,0 @@ -/** -****************************************************************************** -* @file stm32cube_hal_init.h -* @author MCD Application Team -* @version V1.0.0 -* @date 18-February-2014 -* @brief This file contains all the functions prototypes for the -* stm32cube_hal_init.c file. -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); -* You may not use this file except in compliance with the License. -* You may obtain a copy of the License at: -* -* http://www.st.com/software_license_agreement_liberty_v2 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -* -****************************************************************************** -*/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32CUBE_HAL_INIT_H -#define __STM32CUBE_HAL_INIT_H - -#ifdef __cplusplus -extern "C" { -#endif - - /* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" -#include "stm32l1xx_nucleo.h" -#include "platform-conf.h" - -#if COMPILE_SENSORS -#include "x_nucleo_iks01a1_pressure.h" -#include "x_nucleo_iks01a1_imu_6axes.h" -#include "x_nucleo_iks01a1_magneto.h" -#include "x_nucleo_iks01a1_hum_temp.h" -#endif /*COMPILE_SENSORS*/ - - - /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ - - /* Uncomment to enable the adaquate RTC Clock Source */ - -#define RTC_CLOCK_SOURCE_LSI - - -#ifdef RTC_CLOCK_SOURCE_LSI - #define RTC_ASYNCH_PREDIV 0x7F - #define RTC_SYNCH_PREDIV 0x0130 -#endif - -#ifdef RTC_CLOCK_SOURCE_LSE - #define RTC_ASYNCH_PREDIV 0x7F - #define RTC_SYNCH_PREDIV 0x00FF -#endif - - - - /* Exported macro ------------------------------------------------------------*/ - - /* Exported functions ------------------------------------------------------- */ - -void stm32cube_hal_init(); -void RTC_TimeRegulate(uint8_t hh, uint8_t mm, uint8_t ss); - -#ifdef __cplusplus -} -#endif - - - -#endif /* __STM32CUBE_HAL_INIT */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_hal_conf.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_hal_conf.h deleted file mode 100644 index a1ad11636..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_hal_conf.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_conf.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CONF_H -#define __STM32L1xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -#define HAL_COMP_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_CRC_MODULE_ENABLED -#define HAL_CRYP_MODULE_ENABLED -#define HAL_DAC_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_I2S_MODULE_ENABLED -#define HAL_IRDA_MODULE_ENABLED -#define HAL_IWDG_MODULE_ENABLED -#define HAL_LCD_MODULE_ENABLED -#define HAL_NOR_MODULE_ENABLED -//#define HAL_OPAMP_MODULE_ENABLED -//#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -#define HAL_SD_MODULE_ENABLED -#define HAL_SMARTCARD_MODULE_ENABLED -#define HAL_SPI_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED -#define HAL_TIM_MODULE_ENABLED -#define HAL_UART_MODULE_ENABLED -#define HAL_USART_MODULE_ENABLED -#define HAL_WWDG_MODULE_ENABLED - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 -#define INSTRUCTION_CACHE_ENABLE 0 -#define DATA_CACHE_ENABLE 0 - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/*#define USE_FULL_ASSERT 1*/ - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l1xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l1xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l1xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l1xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l1xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l1xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l1xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l1xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l1xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l1xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l1xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l1xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l1xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32l1xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l1xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l1xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32l1xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l1xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l1xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l1xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l1xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l1xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l1xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l1xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l1xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l1xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l1xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l1xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_it.h b/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_it.h deleted file mode 100644 index 47c911392..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Inc/stm32l1xx_it.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - ****************************************************************************** - * @file Templates/Inc/stm32l1xx_it.h - * @author MCD Application Team - * @version V1.0.0 - * @date 5-September-2014 - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_IT_H -#define __STM32L1xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -void EXTI0_IRQHandler(void); -void EXTI1_IRQHandler(void); -void I2Cx_EV_IRQHandler(void); -void I2Cx_ER_IRQHandler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/spirit1_appli.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/spirit1_appli.c deleted file mode 100644 index c71c19105..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/spirit1_appli.c +++ /dev/null @@ -1,649 +0,0 @@ -/** -****************************************************************************** -* @file spirit1_appli.c -* @author System Lab - NOIDA -* @version V1.1.0 -* @date 14-Aug-2014 -* @brief user file to configure Spirit1 transceiver. -* -@verbatim -=============================================================================== -##### How to use this driver ##### -=============================================================================== -[..] -This file is generated automatically by STM32CubeMX and eventually modified -by the user - -@endverbatim -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l152xe.h" -#include "spirit1_appli.h" -#include "MCU_Interface.h" -#include "SPIRIT1_Util.h" - -#include "lib/sensors.h" -extern const struct sensors_sensor button_sensor; - -/** @addtogroup USER -* @{ -*/ - -/** @defgroup SPIRIT1_APPLI -* @brief User file to configure spirit1 tranceiver for desired frequency and -* @feature. -* @{ -*/ - -/* Private typedef -----------------------------------------------------------*/ - -/** -* @brief RadioDriver_t structure fitting -*/ -RadioDriver_t spirit_cb = -{ - .Init = Spirit1InterfaceInit, - .GpioIrq = Spirit1GpioIrqInit, - .RadioInit = Spirit1RadioInit, - .SetRadioPower = Spirit1SetPower, - .PacketConfig = Spirit1PacketConfig, - .SetPayloadLen = Spirit1SetPayloadlength, - .SetDestinationAddress = Spirit1SetDestinationAddress, - .EnableTxIrq = Spirit1EnableTxIrq, - .EnableRxIrq = Spirit1EnableRxIrq, - .DisableIrq = Spirit1DisableIrq, - .SetRxTimeout = Spirit1SetRxTimeout, - .EnableSQI = Spirit1EnableSQI, - .SetRssiThreshold = Spirit1SetRssiTH, - .ClearIrqStatus = Spirit1ClearIRQ, - .StartRx = Spirit1StartRx, - .StartTx = Spirit1StartTx, - .GetRxPacket = Spirit1GetRxPacket -}; - -/** -* @brief MCULowPowerMode_t structure fitting -*/ -MCULowPowerMode_t MCU_LPM_cb = -{ - .McuStopMode = MCU_Enter_StopMode, - .McuStandbyMode = MCU_Enter_StandbyMode, - .McuSleepMode = MCU_Enter_SleepMode -}; - -/** -* @brief RadioLowPowerMode_t structure fitting -*/ -RadioLowPowerMode_t Radio_LPM_cb = -{ - .RadioShutDown = RadioPowerOFF, - .RadioStandBy = RadioStandBy, - .RadioSleep = RadioSleep, - .RadioPowerON = RadioPowerON -}; - -/** -* @brief GPIO structure fitting -*/ -SGpioInit xGpioIRQ={ - SPIRIT_GPIO_IRQ, - SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, - SPIRIT_GPIO_DIG_OUT_IRQ -}; - -/** -* @brief Radio structure fitting -*/ -SRadioInit xRadioInit = { - XTAL_OFFSET_PPM, - BASE_FREQUENCY, - CHANNEL_SPACE, - CHANNEL_NUMBER, - MODULATION_SELECT, - DATARATE, - FREQ_DEVIATION, - BANDWIDTH -}; - - -#if defined(USE_STack_PROTOCOL) -/** -* @brief Packet Basic structure fitting -*/ -PktStackInit xStackInit={ - PREAMBLE_LENGTH, - SYNC_LENGTH, - SYNC_WORD, - LENGTH_TYPE, - LENGTH_WIDTH, - CRC_MODE, - CONTROL_LENGTH, - EN_FEC, - EN_WHITENING -}; - -/* LLP structure fitting */ -PktStackLlpInit xStackLLPInit ={ - EN_AUTOACK, - EN_PIGGYBACKING, - MAX_RETRANSMISSIONS -}; - -/** -* @brief Address structure fitting -*/ -PktStackAddressesInit xAddressInit={ - EN_FILT_MY_ADDRESS, - MY_ADDRESS, - EN_FILT_MULTICAST_ADDRESS, - MULTICAST_ADDRESS, - EN_FILT_BROADCAST_ADDRESS, - BROADCAST_ADDRESS -}; - -#elif defined(USE_BASIC_PROTOCOL) - -/** -* @brief Packet Basic structure fitting -*/ -PktBasicInit xBasicInit={ - PREAMBLE_LENGTH, - SYNC_LENGTH, - SYNC_WORD, - LENGTH_TYPE, - LENGTH_WIDTH, - CRC_MODE, - CONTROL_LENGTH, - EN_ADDRESS, - EN_FEC, - EN_WHITENING -}; - - -/** -* @brief Address structure fitting -*/ -PktBasicAddressesInit xAddressInit={ - EN_FILT_MY_ADDRESS, - MY_ADDRESS, - EN_FILT_MULTICAST_ADDRESS, - MULTICAST_ADDRESS, - EN_FILT_BROADCAST_ADDRESS, - BROADCAST_ADDRESS -}; -#endif - - -/* Private define ------------------------------------------------------------*/ -#define TIME_UP 0x01 - -/* Private macro -------------------------------------------------------------*/ - -/* Private variables ---------------------------------------------------------*/ -RadioDriver_t *pRadioDriver; -MCULowPowerMode_t *pMCU_LPM_Comm; -RadioLowPowerMode_t *pRadio_LPM_Comm; -/*Flags declarations*/ -volatile FlagStatus xRxDoneFlag = RESET, xTxDoneFlag=RESET, cmdFlag=RESET; -volatile FlagStatus xStartRx=RESET, rx_timeout=RESET, exitTime=RESET; -volatile FlagStatus datasendFlag=RESET, wakeupFlag=RESET; -volatile FlagStatus PushButtonStatusWakeup=RESET; -volatile FlagStatus PushButtonStatusData=RESET; -/*IRQ status struct declaration*/ -SpiritIrqs xIrqStatus; -static __IO uint32_t KEYStatusData = 0x00; -AppliFrame_t xTxFrame, xRxFrame; -uint8_t TxFrameBuff[MAX_BUFFER_LEN] = {0x00}; -uint16_t exitCounter = 0; -uint16_t txCounter = 0; -uint16_t wakeupCounter = 0; -uint16_t dataSendCounter = 0x00; - -/* Private function prototypes -----------------------------------------------*/ - -void HAL_Spirit1_Init(void); -void Data_Comm_On(uint8_t *pTxBuff, uint8_t cTxlen, uint8_t* pRxBuff, uint8_t cRxlen); -void Enter_LP_mode(void); -void Exit_LP_mode(void); -void MCU_Enter_StopMode(void); -void MCU_Enter_StandbyMode(void); -void MCU_Enter_SleepMode(void); -void RadioPowerON(void); -void RadioPowerOFF(void); -void RadioStandBy(void); -void RadioSleep(void); -void SPIRIT1_Init(void); -void STackProtocolInit(void); -void BasicProtocolInit(void); -void P2PInterruptHandler(void); -void Set_KeyStatus(FlagStatus val); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); -void HAL_SYSTICK_Callback(void); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPIRIT1_APPLI_Private_Functions -* @{ -*/ - -/** -* @brief Initializes RF Transceiver's HAL. -* @param None -* @retval None. -*/ -void HAL_Spirit1_Init(void) -{ - pRadioDriver = &spirit_cb; - pRadioDriver->Init( ); -} - - - -/** -* @brief This function initializes the protocol for point-to-point -* communication -* @param None -* @retval None -*/ -void SPIRIT1_Init(void) -{ - pRadioDriver = &spirit_cb; - - /* Spirit IRQ config */ - pRadioDriver->GpioIrq(&xGpioIRQ); - - /* Spirit Radio config */ - pRadioDriver->RadioInit(&xRadioInit); - - /* Spirit Radio set power */ - pRadioDriver->SetRadioPower(POWER_INDEX, POWER_DBM); - - /* Spirit Packet config */ - pRadioDriver->PacketConfig(); - - pRadioDriver->EnableSQI(); - - pRadioDriver->SetRssiThreshold(RSSI_THRESHOLD); -} - - -/** -* @brief This function initializes the BASIC Packet handler of spirit1 -* @param None -* @retval None -*/ -void BasicProtocolInit(void) -{ -#if defined(USE_BASIC_PROTOCOL) - /* Spirit Packet config */ - SpiritPktBasicInit(&xBasicInit); - SpiritPktBasicAddressesInit(&xAddressInit); -#endif -} - -/** -* @brief This routine will put the radio and mcu in LPM -* @param None -* @retval None -*/ -void Enter_LP_mode(void) -{ - - pMCU_LPM_Comm = &MCU_LPM_cb; - pRadio_LPM_Comm = &Radio_LPM_cb; - -#if defined(MCU_STOP_MODE)&&defined(RF_SHUTDOWN) - { - pRadio_LPM_Comm->RadioShutDown(); - pMCU_LPM_Comm->McuStopMode(); - } -#elif defined(MCU_STOP_MODE)&&defined(RF_STANDBY) - { - pRadio_LPM_Comm->RadioStandBy(); - pMCU_LPM_Comm->McuStopMode(); - } -#elif defined(MCU_STOP_MODE)&&defined(RF_SLEEP) - { - pRadio_LPM_Comm->RadioSleep(); - pMCU_LPM_Comm->McuStopMode(); - } -#elif defined(MCU_STANDBY_MODE)&&defined(RF_SHUTDOWN) - { - pRadio_LPM_Comm->RadioShutDown(); - pMCU_LPM_Comm->McuStandbyMode(); - } -#elif defined(MCU_STANDBY_MODE)&&defined(RF_STANDBY) - { - pRadio_LPM_Comm->RadioStandBy(); - pMCU_LPM_Comm->McuStandbyMode(); - } -#elif defined(MCU_STANDBY_MODE)&&defined(RF_SLEEP) - { - pRadio_LPM_Comm->RadioSleep(); - pMCU_LPM_Comm->McuStandbyMode(); - } -#elif defined(MCU_SLEEP_MODE)&&defined(RF_SHUTDOWN) - { - pRadio_LPM_Comm->RadioShutDown(); - pMCU_LPM_Comm->McuSleepMode(); - } -#elif defined(MCU_SLEEP_MODE)&&defined(RF_STANDBY) - { - pRadio_LPM_Comm->RadioStandBy(); - pMCU_LPM_Comm->McuSleepMode(); - } -#elif defined(MCU_SLEEP_MODE)&&defined(RF_SLEEP) - { - pRadio_LPM_Comm->RadioSleep(); - pMCU_LPM_Comm->McuSleepMode(); - } -#elif defined(MCU_STOP_MODE) - pMCU_LPM_Comm->McuStopMode(); - -#elif defined(MCU_STANDBY_MODE) - pMCU_LPM_Comm->McuStandbyMode(); - -#else - pMCU_LPM_Comm->McuSleepMode(); -#endif -} - -/** -* @brief This routine wake-up the mcu and radio from LPM -* @param None -* @retval None -*/ -void Exit_LP_mode(void) -{ - pRadio_LPM_Comm = &Radio_LPM_cb; - pRadio_LPM_Comm->RadioPowerON(); -} - -/** -* @brief This routine puts the MCU in stop mode -* @param None -* @retval None -*/ -void MCU_Enter_StopMode(void) -{ - HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); /* Infinite loop */ -} - -/** -* @brief This routine puts the MCU in standby mode -* @param None -* @retval None -*/ -void MCU_Enter_StandbyMode(void) -{ - HAL_PWR_EnterSTANDBYMode(); /* Infinite loop */ -} - -/** -* @brief This routine puts the MCU in sleep mode -* @param None -* @retval None -*/ -void MCU_Enter_SleepMode(void) -{ - /*Suspend Tick increment to prevent wakeup by Systick interrupt. - Otherwise the Systick interrupt will wake up the device within 1ms (HAL time base)*/ - HAL_SuspendTick(); - HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); /* Infinite loop */ -} - -/** -* @brief This function will turn on the radio and waits till it enters the Ready state. -* @param Param:None. -* @retval None -* -*/ -void RadioPowerON(void) -{ - SpiritCmdStrobeReady(); - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - } - while(g_xStatus.MC_STATE!=MC_STATE_READY); -} - - -/** -* @brief This function will Shut Down the radio. -* @param Param:None. -* @retval None -* -*/ -void RadioPowerOFF(void) -{ - SpiritEnterShutdown(); -} - - -/** -* @brief This function will put the radio in standby state. -* @param None. -* @retval None -* -*/ -void RadioStandBy(void) -{ - SpiritCmdStrobeStandby(); -#if 0 - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - } - while(g_xStatus.MC_STATE!=MC_STATE_STANDBY); -#endif -} - -/** -* @brief This function will put the radio in sleep state. -* @param None. -* @retval None -* -*/ -void RadioSleep(void) -{ - SpiritCmdStrobeSleep(); -#if 0 - do{ - /* Delay for state transition */ - for(volatile uint8_t i=0; i!=0xFF; i++); - - /* Reads the MC_STATUS register */ - SpiritRefreshStatus(); - } - while(g_xStatus.MC_STATE!=MC_STATE_SLEEP); -#endif -} - -/** -* @brief This routine updates the respective status for key press. -* @param None -* @retval None -*/ -void Set_KeyStatus(FlagStatus val) -{ - if(val==SET) - { - KEYStatusData = 1; - } - else - KEYStatusData = 0; -} - - -/** - * @brief SYSTICK callback. - * @param None - * @retval None - */ -void HAL_SYSTICK_Callback(void) -{ - if(exitTime) - { - /*Decreament the counter to check when 3 seconds has been elapsed*/ - exitCounter--; - /*3 seconds has been elapsed*/ - if(exitCounter <= TIME_UP) - { - exitTime = RESET; - } - } - -#if defined(RF_STANDBY) - /*Check if Push Button pressed for wakeup or to send data*/ - if(PushButtonStatusWakeup) - { - /*Decreament the counter to check when 5 seconds has been elapsed*/ - wakeupCounter--; - - /*5seconds has been elapsed*/ - if(wakeupCounter<=TIME_UP) - { - /*Perform wakeup opeartion*/ - wakeupFlag = SET; - Exit_LP_mode(); - BSP_LED_Toggle(LED2); - PushButtonStatusWakeup = RESET; - PushButtonStatusData = SET; - } - } - else if(PushButtonStatusData) - { - dataSendCounter--; - if(dataSendCounter<=TIME_UP) - { - datasendFlag = SET; - PushButtonStatusWakeup = RESET; - PushButtonStatusData = RESET; - } - } -#endif -} -/** -* @} -*/ -/** - * @brief GPIO EXTI callback - * @param uint16_t GPIO_Pin - * @retval None - */ -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ -#if defined(MCU_STOP_MODE)/*if MCU is in stop mode*/ - - /* Clear Wake Up Flag */ - __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); - - /* Configures system clock after wake-up from STOP: enable HSE, PLL and select - PLL as system clock source (HSE and PLL are disabled in STOP mode) */ - SystemClockConfig_STOP(); -#endif -#if defined(MCU_SLEEP_MODE) - /* Resume Tick interrupt if disabled prior to sleep mode entry*/ - HAL_ResumeTick(); -#endif - - /* Initialize LEDs*/ - RadioShieldLedInit(RADIO_SHIELD_LED); - //BSP_LED_Init(LED2); - - if (GPIO_Pin == USER_BUTTON_PIN) - { - sensors_changed(&button_sensor); - } - -} -/** -* @} -*/ -/** - * @brief Configures system clock after wake-up from STOP: enable HSI, PLL - * and select PLL as system clock source. - * @param None - * @retval None - */ -#if defined(MCU_STOP_MODE)/*if MCU is in stop mode*/ - -static void SystemClockConfig_STOP(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Get the Oscillators configuration according to the internal RCC registers */ - HAL_RCC_GetOscConfig(&RCC_OscInitStruct); - - /* After wake-up from STOP reconfigure the system clock: Enable HSI and PLL */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; - RCC_OscInitStruct.HSICalibrationValue = 0x10; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1); -} -#endif -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32cube_hal_init.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32cube_hal_init.c deleted file mode 100644 index 3dc4ea8b8..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32cube_hal_init.c +++ /dev/null @@ -1,334 +0,0 @@ -/** -****************************************************************************** -* @file stm32cube_hal_init.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief STM32 Cube HAL Init Source file -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/* Includes ------------------------------------------------------------------*/ - -#include "stdio.h" -#include "string.h" -#include "stdlib.h" -#include "stm32cube_hal_init.h" -#include "stm32l1xx_nucleo.h" -#include "radio_shield_config.h" -#include "spirit1_appli.h" - - -extern UART_HandleTypeDef UartHandle; -FlagStatus TamperStatus = RESET; -volatile uint8_t scheduler_started=0; -RTC_HandleTypeDef RtcHandle; -int dec_precision = 2; -volatile float UVI_Value; - -static void RTC_Config(void); -static void RTC_TimeStampConfig(void); -static void SystemClock_Config(void); -static void MX_GPIO_Init(void); - -void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -void BSP_LED_Init(Led_TypeDef Led); -void BSP_LED_Off(Led_TypeDef Led); -void BSP_LED_On(Led_TypeDef Led); -void BSP_LED_Toggle(Led_TypeDef Led); -void USARTConfig(void); -void Stack_6LoWPAN_Init(void); - -static void Error_Handler(); - -I2C_HandleTypeDef I2cHandle; -#define I2C_ADDRESS 0x30F - -/* I2C SPEEDCLOCK define to max value: 400 KHz on STM32L1xx*/ -#define I2C_SPEEDCLOCK 400000 -#define I2C_DUTYCYCLE I2C_DUTYCYCLE_2 - - -/** - * @brief stm32cube_hal_init() - * @param None - * @retval None - */ -void stm32cube_hal_init() -{ - HAL_Init(); - /* Configure the system clock */ - SystemClock_Config(); - - HAL_EnableDBGStopMode(); - - MX_GPIO_Init(); - HAL_Spirit1_Init(); - SPIRIT1_Init(); - - USARTConfig(); - /* Initialize RTC */ - - RTC_Config(); - RTC_TimeStampConfig(); -} - - - -/** - * @brief Configure the RTC peripheral by selecting the clock source. - * @param None - * @retval None - */ -void RTC_Config(void) -{ - /*##-1- Configure the RTC peripheral #######################################*/ - RtcHandle.Instance = RTC; - - /* Configure RTC prescaler and RTC data registers */ - /* RTC configured as follow: - - Hour Format = Format 12 - - Asynch Prediv = Value according to source clock - - Synch Prediv = Value according to source clock - - OutPut = Output Disable - - OutPutPolarity = High Polarity - - OutPutType = Open Drain */ - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_12; - RtcHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; - RtcHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if(HAL_RTC_Init(&RtcHandle) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } -} - - -/** - * @brief Configures the current time and date. - * @param None - * @retval None - */ -static void RTC_TimeStampConfig(void) -{ - RTC_DateTypeDef sdatestructure; - RTC_TimeTypeDef stimestructure; - - /*##-3- Configure the Date #################################################*/ - /* Set Date: Tuesday February 18th 2014 */ - sdatestructure.Year = 0x14; - sdatestructure.Month = RTC_MONTH_FEBRUARY; - sdatestructure.Date = 0x18; - sdatestructure.WeekDay = RTC_WEEKDAY_TUESDAY; - - if(HAL_RTC_SetDate(&RtcHandle,&sdatestructure,FORMAT_BCD) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } - - /*##-4- Configure the Time #################################################*/ - /* Set Time: 08:10:00 */ - stimestructure.Hours = 0x08; - stimestructure.Minutes = 0x10; - stimestructure.Seconds = 0x00; - stimestructure.TimeFormat = RTC_HOURFORMAT12_AM; - stimestructure.DayLightSaving = RTC_DAYLIGHTSAVING_NONE ; - stimestructure.StoreOperation = RTC_STOREOPERATION_RESET; - - if(HAL_RTC_SetTime(&RtcHandle,&stimestructure,FORMAT_BCD) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } -} - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * System Clock source = PLL (HSI) - * SYSCLK(Hz) = 32000000 - * HCLK(Hz) = 32000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 1 - * APB2 Prescaler = 1 - * HSI Frequency(Hz) = 16000000 - * PLL_MUL = 4 - * PLL_DIV = 2 - * Flash Latency(WS) = 1 - * Main regulator output voltage = Scale1 mode - * @param None - * @retval None - */ - -void SystemClock_Config(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - - /* Enable HSE Oscillator and Activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - - /* Set Voltage scale1 as MCU will run at 32MHz */ - __PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ - while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) - { - Error_Handler(); - } -} - - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -static void Error_Handler(void) -{ - /* User may add here some code to deal with this error */ - while(1) - { - } -} - -/** - * @brief RTC MSP Initialization - * This function configures the hardware resources used in this example - * @param hrtc: RTC handle pointer - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. - * - * @retval None - */ -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /*##-1- Configue LSE as RTC clock soucre ###################################*/ -#ifdef RTC_CLOCK_SOURCE_LSE - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } -#elif defined (RTC_CLOCK_SOURCE_LSI) - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } - - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; - if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } -#else -#error Please select the RTC Clock source inside the stm32cube_hal_init.h file -#endif /*RTC_CLOCK_SOURCE_LSE*/ - - /*##-2- Enable RTC peripheral Clocks #######################################*/ - /* Enable RTC Clock */ - __HAL_RCC_RTC_ENABLE(); - - /*##-3- Configure the NVIC for RTC TimeStamp ###################################*/ - HAL_NVIC_SetPriority(/*TAMP_STAMP_IRQn*/2, 0x0F, 0); - HAL_NVIC_EnableIRQ(/*TAMP_STAMP_IRQn*/2); -} - - -/** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI -*/ -void MX_GPIO_Init(void) -{ - - - /* GPIO Ports Clock Enable */ - __GPIOA_CLK_ENABLE(); - __GPIOC_CLK_ENABLE(); - __GPIOD_CLK_ENABLE(); -} - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_hal_msp.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_hal_msp.c deleted file mode 100644 index 71f9f6753..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_hal_msp.c +++ /dev/null @@ -1,319 +0,0 @@ -/** -****************************************************************************** -* @file stm32l1xx_hal_msp.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief HAL MSP file -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/* Includes ------------------------------------------------------------------*/ -#include "stm32cube_hal_init.h" -#include "stm32l1xx_hal.h" -#include "hw-config.h" -/** @addtogroup STM32L1xx_HAL_Examples - * @{ - */ - -/** @addtogroup Templates - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -volatile uint8_t UART_RxBuffer[UART_RxBufferSize]; -volatile uint32_t Usart_BaudRate = 115200; - -UART_HandleTypeDef UartHandle; -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HAL_MSP_Private_Functions - * @{ - */ - -/** - * @brief Initializes the Global MSP. - * @param None - * @retval None - */ -void HAL_MspInit(void) -{ - /* NOTE : This function is generated automatically by MicroXplorer and eventually - modified by the user - */ - - GPIO_InitTypeDef GPIO_InitStruct; - - /*##-2- Enable peripherals and GPIO Clocks #################################*/ - /* Enable GPIO TX/RX clock */ - /* GPIO Ports Clock Enable */ - __GPIOA_CLK_ENABLE(); - __GPIOC_CLK_ENABLE(); - __GPIOD_CLK_ENABLE(); - I2Cx_SCL_GPIO_CLK_ENABLE(); - I2Cx_SDA_GPIO_CLK_ENABLE(); - /* Enable I2Cx clock */ - I2Cx_CLK_ENABLE(); - - /*##-3- Configure peripheral GPIO ##########################################*/ - /* I2C TX GPIO pin configuration */ - GPIO_InitStruct.Pin = I2Cx_SCL_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Alternate = I2Cx_SCL_SDA_AF; - - HAL_GPIO_Init(I2Cx_SCL_GPIO_PORT, &GPIO_InitStruct); - - /* I2C RX GPIO pin configuration */ - GPIO_InitStruct.Pin = I2Cx_SDA_PIN; - GPIO_InitStruct.Alternate = I2Cx_SCL_SDA_AF; - - HAL_GPIO_Init(I2Cx_SDA_GPIO_PORT, &GPIO_InitStruct); - - /*##-4- Configure the NVIC for I2C ########################################*/ - /* NVIC for I2Cx */ - HAL_NVIC_SetPriority(I2Cx_ER_IRQn, 0, 1); - HAL_NVIC_EnableIRQ(I2Cx_ER_IRQn); - HAL_NVIC_SetPriority(I2Cx_EV_IRQn, 0, 2); - HAL_NVIC_EnableIRQ(I2Cx_EV_IRQn); - -} - -/** - * @brief DeInitializes the Global MSP. - * @param None - * @retval None - */ -void HAL_MspDeInit(void) -{ - /* NOTE : This function is generated automatically by MicroXplorer and eventually - modified by the user - */ - /*##-1- Reset peripherals ##################################################*/ - I2Cx_FORCE_RESET(); - I2Cx_RELEASE_RESET(); - - /*##-2- Disable peripherals and GPIO Clocks #################################*/ - /* Configure I2C Tx as alternate function */ - HAL_GPIO_DeInit(I2Cx_SCL_GPIO_PORT, I2Cx_SCL_PIN); - /* Configure I2C Rx as alternate function */ - HAL_GPIO_DeInit(I2Cx_SDA_GPIO_PORT, I2Cx_SDA_PIN); - - /*##-3- Disable the NVIC for I2C ##########################################*/ - HAL_NVIC_DisableIRQ(I2Cx_ER_IRQn); - HAL_NVIC_DisableIRQ(I2Cx_EV_IRQn); -} - - -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) -{ - - if(htim_base->Instance==TIM2) - { - /* Peripheral clock enable */ - __TIM2_CLK_ENABLE(); - - /**TIM2 GPIO Configuration - PA0-WKUP ------> TIM2_CH1 - */ - /* Peripheral interrupt init*/ - - HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(TIM2_IRQn); - } - -} - -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) -{ - - if(htim_base->Instance==TIM2) - { - /* Peripheral clock disable */ - __TIM2_CLK_DISABLE(); - - /**TIM2 GPIO Configuration - PA0-WKUP ------> TIM2_CH1 - */ - /* Peripheral interrupt Deinit*/ - HAL_NVIC_DisableIRQ(TIM2_IRQn); - } - -} - - -/** - * @brief UART MSP Initialization - * This function configures the hardware resources used in this example: - * - Peripheral's clock enable - * - Peripheral's GPIO Configuration - * - NVIC configuration for UART interrupt request enable - * @param huart: UART handle pointer - * @retval None - */ -void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /*##-1- Enable peripherals and GPIO Clocks #################################*/ - /* Enable GPIO TX/RX clock */ - USARTx_TX_GPIO_CLK_ENABLE(); - USARTx_RX_GPIO_CLK_ENABLE(); - - - /* Enable USARTx clock */ - USARTx_CLK_ENABLE(); - - /*##-2- Configure peripheral GPIO ##########################################*/ - /* UART TX GPIO pin configuration */ - GPIO_InitStruct.Pin = USARTx_TX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Alternate = USARTx_TX_AF; - - HAL_GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStruct); - - /* UART RX GPIO pin configuration */ - GPIO_InitStruct.Pin = USARTx_RX_PIN; - GPIO_InitStruct.Alternate = USARTx_RX_AF; - - - - - HAL_GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStruct); - - /*##-3- Configure the NVIC for UART ########################################*/ - /* NVIC for USART */ - HAL_NVIC_SetPriority(USARTx_IRQn, 0, 1); - HAL_NVIC_EnableIRQ(USARTx_IRQn); - -} - -/** - * @brief UART MSP De-Initialization - * This function frees the hardware resources used in this example: - * - Disable the Peripheral's clock - * - Revert GPIO and NVIC configuration to their default state - * @param huart: UART handle pointer - * @retval None - */ -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /*##-1- Reset peripherals ##################################################*/ - USARTx_FORCE_RESET(); - USARTx_RELEASE_RESET(); - - /*##-2- Disable peripherals and GPIO Clocks #################################*/ - /* Configure UART Tx as alternate function */ - HAL_GPIO_DeInit(USARTx_TX_GPIO_PORT, USARTx_TX_PIN); - /* Configure UART Rx as alternate function */ - HAL_GPIO_DeInit(USARTx_RX_GPIO_PORT, USARTx_RX_PIN); - - /*##-3- Disable the NVIC for UART ##########################################*/ - HAL_NVIC_DisableIRQ(USARTx_IRQn); -} - - -/** - * @brief Configure the USART - * @param None - * @retval None - */ -void USARTConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /*##-1- Enable peripherals and GPIO Clocks #################################*/ - /* Enable GPIO TX/RX clock */ - USARTx_TX_GPIO_CLK_ENABLE(); - USARTx_RX_GPIO_CLK_ENABLE(); - /* Enable USART2 clock */ - USARTx_CLK_ENABLE(); - /* Enable DMA1 clock */ - DMAx_CLK_ENABLE(); - - /*##-2- Configure peripheral GPIO ##########################################*/ - /* UART TX GPIO pin configuration */ - GPIO_InitStruct.Pin = USARTx_TX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Alternate = USARTx_TX_AF; - - HAL_GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStruct); - - /* UART RX GPIO pin configuration */ - GPIO_InitStruct.Pin = USARTx_RX_PIN; - GPIO_InitStruct.Alternate = USARTx_RX_AF; - - HAL_GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStruct); - - - /*##-1- Configure the UART peripheral ######################################*/ - /* Put the USART peripheral in the Asynchronous mode (UART Mode) */ - UartHandle.Instance = USARTx; - UartHandle.Init.BaudRate = Usart_BaudRate; - UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - UartHandle.Init.StopBits = UART_STOPBITS_1; - UartHandle.Init.Parity = UART_PARITY_NONE; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - UartHandle.Init.Mode = UART_MODE_TX_RX; - - if(HAL_UART_Init(&UartHandle) != HAL_OK) - { - // Error_Handler(); - while(1); - } - - UartHandle.pRxBuffPtr = (uint8_t*)UART_RxBuffer; - UartHandle.RxXferSize = UART_RxBufferSize; - UartHandle.ErrorCode = HAL_UART_ERROR_NONE; - //HAL_UART_Receive_IT(&UartHandle, (uint8_t*)UART_RxBuffer, UART_RxBufferSize); -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c b/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c deleted file mode 100644 index 4ad2038c0..000000000 --- a/platform/stm32nucleo-spirit1/stm32cube-hal/Src/stm32l1xx_it.c +++ /dev/null @@ -1,382 +0,0 @@ -/** -****************************************************************************** -* @file stm32l1xx_it.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Main Interrupt Service Routines -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/* Includes ------------------------------------------------------------------*/ -#include "stm32cube_hal_init.h" -#include "stm32l1xx_it.h" -#include "stm32l1xx_nucleo.h" -#include "radio_gpio.h" -#include "spirit1.h" - - -extern UART_HandleTypeDef UartHandle; -/** @addtogroup STM32L1xx_HAL_Examples -* @{ -*/ - -/** @addtogroup Templates -* @{ -*/ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************/ -/* Cortex-M3 Processor Exceptions Handlers */ -/******************************************************************************/ -extern I2C_HandleTypeDef I2cHandle; -/** -* @brief This function handles NMI exception. -* @param None -* @retval None -*/ -void NMI_Handler(void) -{ -} -void WWDG_IRQHandler(void) -{ - while(1); -} -/** -* @brief This function handles Hard Fault exception. -* @param None -* @retval None -*/ -void HardFault_Handler(void) -{ - /* Go to infinite loop when Hard Fault exception occurs */ - while (1) - { - } -} - -/** -* @brief This function handles Memory Manage exception. -* @param None -* @retval None -*/ -void MemManage_Handler(void) -{ - /* Go to infinite loop when Memory Manage exception occurs */ - while (1) - { - } -} - -/** -* @brief This function handles Bus Fault exception. -* @param None -* @retval None -*/ -void BusFault_Handler(void) -{ - /* Go to infinite loop when Bus Fault exception occurs */ - while (1) - { - } -} - -/** -* @brief This function handles Usage Fault exception. -* @param None -* @retval None -*/ -void UsageFault_Handler(void) -{ - /* Go to infinite loop when Usage Fault exception occurs */ - while (1) - { - } -} - -/** -* @brief This function handles SVCall exception. -* @param None -* @retval None -*/ -void SVC_Handler(void) -{ -} - -/** -* @brief This function handles Debug Monitor exception. -* @param None -* @retval None -*/ -void DebugMon_Handler(void) -{ -} - -/** -* @brief This function handles PendSVC exception. -* @param None -* @retval None -*/ -void PendSV_Handler(void) -{ -} - - -/******************************************************************************/ -/* STM32L1xx Peripherals Interrupt Handlers */ -/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ -/* available peripheral interrupt handler's name please refer to the startup */ -/* file (startup_stm32l1xx.s). */ -/******************************************************************************/ -/** -* @brief This function handles I2C event interrupt request. -* @param None -* @retval None -* @Note This function is redefined in "stm32cube_hal_init.h" and related to I2C data transmission -*/ -void I2Cx_EV_IRQHandler(void) -{ - HAL_I2C_EV_IRQHandler(& I2cHandle); -} - -/** -* @brief This function handles I2C error interrupt request. -* @param None -* @retval None -* @Note This function is redefined in "stm32cube_hal_init.h" and related to I2C error -*/ -void I2Cx_ER_IRQHandler(void) -{ - HAL_I2C_ER_IRQHandler(& I2cHandle); -} - - -/** -* @brief This function handles External lines 15 to 4 interrupt request. -* @param None -* @retval None -*/ -void EXTI0_IRQHandler(void) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_0) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0); - } - while(1); -} - -void EXTI1_IRQHandler(void) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_1) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_1); - } - while(1); -} - -void EXTI2_IRQHandler(void) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_2) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_2); - } - while(1); -} - -void EXTI3_IRQHandler(void) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_3) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_3); - } - while(1); -} - - -/** -* @brief This function handles External lines 15 to 4 interrupt request. -* @param None -* @retval None -*/ -void EXTI9_5_IRQHandler(void) -{ - /* EXTI line 7 interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(RADIO_GPIO_3_EXTI_LINE)) - { - __HAL_GPIO_EXTI_CLEAR_IT(RADIO_GPIO_3_EXTI_LINE); - - HAL_GPIO_EXTI_Callback(RADIO_GPIO_3_EXTI_LINE); - - spirit1_interrupt_callback(); - } - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_9); - - - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8); - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_7); - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_6); - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_5); - -#ifndef LPM_ENABLE - - // if(__HAL_GPIO_EXTI_GET_IT(KEY_BUTTON_EXTI_LINE) != RESET) - // { - // __HAL_GPIO_EXTI_CLEAR_IT(KEY_BUTTON_EXTI_LINE); - // - // Set_KeyStatus(SET); - // } - // -#else /*Low Power mode enabled*/ - -#if defined(RF_STANDBY)/*if spirit1 is in standby*/ - - if(EXTI->PR & KEY_BUTTON_EXTI_LINE) - { - HAL_GPIO_EXTI_Callback(KEY_BUTTON_EXTI_LINE); - /* EXTI line 13 interrupt detected */ - if(HAL_GPIO_ReadPin(KEY_BUTTON_GPIO_PORT, KEY_BUTTON_PIN) == 0x01) //0x00 - { - HAL_GPIO_EXTI_Callback(KEY_BUTTON_EXTI_LINE); - - PushButtonStatusWakeup = SET; - PushButtonStatusData = RESET; - wakeupCounter = LPM_WAKEUP_TIME; - dataSendCounter = DATA_SEND_TIME; - dataSendCounter++; - } - __HAL_GPIO_EXTI_CLEAR_IT(KEY_BUTTON_EXTI_LINE); - } -#else /*if spirit1 is not in standby or sleep mode but MCU is in LPM*/ - - if(__HAL_GPIO_EXTI_GET_IT(KEY_BUTTON_EXTI_LINE) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(KEY_BUTTON_EXTI_LINE); - - HAL_GPIO_EXTI_Callback(KEY_BUTTON_EXTI_LINE); - - Set_KeyStatus(SET); - } -#endif -#endif -} - - - -/** -* @brief This function handles EXTI15_10_IRQHandler -* @param None -* @retval None -*/ -void EXTI15_10_IRQHandler(void) -{ - HAL_GPIO_EXTI_IRQHandler(USER_BUTTON_PIN); -} - - -/** -* @brief This function handles UART interrupt request. -* @param None -* @retval None -* @Note This function is redefined in "stm32cube_hal_init.h" and related to DMA -* used for USART data transmission -*/ - -void USART2_IRQHandler() -{ - UART_HandleTypeDef *huart = &UartHandle; - - if(__HAL_UART_GET_FLAG(huart, UART_FLAG_PE)){ - __HAL_UART_CLEAR_PEFLAG(huart); - } - - if(__HAL_UART_GET_FLAG(huart, UART_FLAG_FE)){ - __HAL_UART_CLEAR_FEFLAG(huart); - } - - if(__HAL_UART_GET_FLAG(huart, UART_FLAG_NE)){ - __HAL_UART_CLEAR_NEFLAG(huart); - } - - if(__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE)){ - __HAL_UART_CLEAR_OREFLAG(&UartHandle); - } - - if(__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)){ - slip_input_byte(UartHandle.Instance->DR); - __HAL_UART_GET_IT_SOURCE(&UartHandle, UART_IT_RXNE); - } -} - -/** -* @brief UART error callbacks -* @param UartHandle: UART handle -* @note This example shows a simple way to report transfer error, and you can -* add your own implementation. -* @retval None -*/ -void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle) -{ - // Error_Handler(); -} - - -/** -* @brief Tx Transfer completed callback -* @param UartHandle: UART handle. -* @note This example shows a simple way to report end of IT Tx transfer, and -* you can add your own implementation. -* @retval None -*/ -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *UartHandle) -{ - - -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-lib b/platform/stm32nucleo-spirit1/stm32cube-lib new file mode 160000 index 000000000..6f7a7c0be --- /dev/null +++ b/platform/stm32nucleo-spirit1/stm32cube-lib @@ -0,0 +1 @@ +Subproject commit 6f7a7c0be1556bed60cf031eeb6231d3310ceba2 diff --git a/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h b/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h index de5f97558..f8d3a60ee 100644 --- a/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h +++ b/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file platform_config.h + * @file stm32l-spirit1-config.h * @author MCD Application Team * @version V3.4.0 * @date 29-June-2012 @@ -25,10 +25,9 @@ ****************************************************************************** */ - /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PLATFORM_CONFIG_H -#define __PLATFORM_CONFIG_H +#ifndef __STM32L_SPIRIT1_CONFIG_H +#define __STM32L_SPIRIT1_CONFIG_H /* Includes ------------------------------------------------------------------*/ @@ -85,16 +84,15 @@ #endif /* USB_USE_EXTERNAL_PULLUP */ #ifdef USE_STM32L152_EVAL - #define EVAL_COM1_IRQHandler USART2_IRQHandler + #define EVAL_COM1_IRQHandler USART2_IRQHandler #elif defined (USE_STM32L152D_EVAL) #define EVAL_COM1_IRQHandler USART1_IRQHandler -#endif +#endif /*USE_STM32L152_EVAL*/ #endif /* USE_STM3210B_EVAL */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ -#endif /* __PLATFORM_CONFIG_H */ - +#endif /* __STM32L_SPIRIT1_CONFIG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/uart-msg.c b/platform/stm32nucleo-spirit1/uart-msg.c index 831bd2079..84e552ea1 100644 --- a/platform/stm32nucleo-spirit1/uart-msg.c +++ b/platform/stm32nucleo-spirit1/uart-msg.c @@ -33,8 +33,7 @@ * ****************************************************************************** */ -/* Includes ------------------------------------------------------------------*/ - +/*---------------------------------------------------------------------------*/ #include "contiki.h" #include "dev/leds.h" #include "stm32l1xx_nucleo.h" @@ -43,53 +42,52 @@ #include "dev/slip.h" #include "hw-config.h" #include "stm32l1xx_hal.h" - -void UART_SendMsg(char *Msg); -extern UART_HandleTypeDef UartHandle; - +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +void uart_send_msg(char *); +extern st_lib_uart_handle_typedef st_lib_uart_handle; +/*---------------------------------------------------------------------------*/ +static unsigned char databyte[1] = {0}; +/*---------------------------------------------------------------------------*/ /** * @brief Rx Transfer completed callbacks. -* @param huart: Pointer to a UART_HandleTypeDef structure that contains +* @param huart: Pointer to a st_lib_uart_handle_typedef structure that contains * the configuration information for the specified UART module. * @retval None */ - -static unsigned char databyte[1] = {0}; -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +void st_lib_hal_uart_rx_cplt_callback(st_lib_uart_handle_typedef *huart) { slip_input_byte(databyte[0]); - HAL_UART_Receive_IT(&UartHandle, databyte, 1); + st_lib_hal_uart_receive_it(&st_lib_uart_handle, databyte, 1); } - /*---------------------------------------------------------------------------*/ void uart1_set_input(int (*input) (unsigned char c)) { - HAL_UART_Receive_IT(&UartHandle, databyte, 1); + st_lib_hal_uart_receive_it(&st_lib_uart_handle, databyte, 1); } - /*--------------------------------------------------------------------------*/ void slip_arch_init(unsigned long ubr) { - __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE); + st_lib_hal_uart_enable_it(&st_lib_uart_handle, UART_IT_RXNE); //uart1_set_input(slip_input_byte); } /*--------------------------------------------------------------------------*/ void slip_arch_writeb(unsigned char c) { - UART_SendMsg(&c); + uart_send_msg(&c); } /*--------------------------------------------------------------------------*/ /** * @brief Send a message via UART - * @param Msg the pointer to the message to be sent + * @param msg the pointer to the message to be sent * @retval None */ -void UART_SendMsg(char *Msg) +void uart_send_msg(char *msg) { - HAL_UART_Transmit(&UartHandle, (uint8_t*)Msg, 1, 5000); + st_lib_hal_uart_transmit(&st_lib_uart_handle, (uint8_t*)msg, 1, 5000); } /*--------------------------------------------------------------------------*/ From 49b24e6f53b026edaf484e68664d0d3448e22ae5 Mon Sep 17 00:00:00 2001 From: Fabien Castanier Date: Wed, 5 Aug 2015 13:59:08 +0200 Subject: [PATCH 11/23] Modified the parameter name of clock_wait function --- cpu/arm/stm32l152/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/arm/stm32l152/clock.c b/cpu/arm/stm32l152/clock.c index a38248de7..57ed8eba4 100644 --- a/cpu/arm/stm32l152/clock.c +++ b/cpu/arm/stm32l152/clock.c @@ -95,10 +95,10 @@ void clock_delay(unsigned int i) /** * Wait for a multiple of clock ticks (7.8 ms at 128 Hz). */ -void clock_wait(clock_time_t i) +void clock_wait(clock_time_t t) { clock_time_t start; start = clock_time(); - while(clock_time() - start < (clock_time_t)i); + while(clock_time() - start < (clock_time_t)t); } /*---------------------------------------------------------------------------*/ From 913ef068bed7714f0f8ab19bc32dc63de85035ca Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Tue, 1 Sep 2015 15:34:34 +0200 Subject: [PATCH 12/23] Updated submodule stm32cube-lib --- platform/stm32nucleo-spirit1/stm32cube-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/stm32nucleo-spirit1/stm32cube-lib b/platform/stm32nucleo-spirit1/stm32cube-lib index 6f7a7c0be..25a065a28 160000 --- a/platform/stm32nucleo-spirit1/stm32cube-lib +++ b/platform/stm32nucleo-spirit1/stm32cube-lib @@ -1 +1 @@ -Subproject commit 6f7a7c0be1556bed60cf031eeb6231d3310ceba2 +Subproject commit 25a065a28e4b1e05adb92df834939271fe6a700c From a627a542240429434cf110dd874f38c8cbd5be29 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Thu, 3 Sep 2015 18:02:15 +0200 Subject: [PATCH 13/23] Fixes to README.md instructions --- platform/stm32nucleo-spirit1/README.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index 313a8d3c0..e81672a69 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -63,7 +63,16 @@ Software Requirements The following software are needed: * ST port of Contiki for STM32 Nucleo and expansion boards. - >The port is installed automatically when the Contiki repository is cloned. + >The port is installed automatically when both the Contiki and the submodule repository are cloned: the former hosts the Contiki distribution and the ST platform interface, the latter hosts the actual library. +The following commands are needed to download the full porting: + + git clone https://github.com/STclab/contiki.git (*) + cd contiki/ + git checkout stm32nucleo-spirit1 (*) + git submodule init + git submodule update +(*): required only if using the STclab GitHub repository, these steps won't be needed once the Pull Request will be accepted + The platform name is: stm32nucleo-spirit1 * A toolchain to build the firmware: The port has been developed and tested with GNU Tools @@ -131,7 +140,6 @@ This jumper provides the required voltage to the devices on the board. 5. Program the firmware on the STM32 Nucleo board. This can be done by copying the binary file on the USB mass storage that is automatically created when plugging the STM32 Nucleo board to the PC. -On Linux machines the serial port device is located in /dev/ttyACMx (x depends on the PC). 6. Reset the MCU by using the reset button on the STM32 Nucleo board From b7459a12c1b667707b0bd3988148122dfe3e30cb Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Mon, 7 Sep 2015 19:59:03 +0200 Subject: [PATCH 14/23] Added radio sensor. --- .../sensor-demo/sensor-demo.c | 19 ++- .../Makefile.stm32nucleo-spirit1 | 2 +- .../contiki-spirit1-main.c | 5 +- .../stm32nucleo-spirit1/dev/radio-sensor.c | 125 ++++++++++++++++++ .../stm32nucleo-spirit1/dev/sensor-common.h | 3 + platform/stm32nucleo-spirit1/platform-conf.h | 1 + platform/stm32nucleo-spirit1/spirit1.c | 7 + 7 files changed, 157 insertions(+), 5 deletions(-) create mode 100644 platform/stm32nucleo-spirit1/dev/radio-sensor.c diff --git a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c index 779092199..49ff705f9 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c +++ b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c @@ -49,6 +49,10 @@ #include "dev/button-sensor.h" #include "dev/leds.h" +#include "dev/radio-sensor.h" +#include "dev/sensor-common.h" + +#include "st-lib.h" #ifdef COMPILE_SENSORS #include "dev/temperature-sensor.h" @@ -72,12 +76,15 @@ PROCESS_THREAD(sensor_demo_process, ev, data) { static struct etimer etimer; static unsigned long _button_pressed; + static int sensor_value = 0; PROCESS_BEGIN(); PROCESS_PAUSE(); SENSORS_ACTIVATE(button_sensor); + SENSORS_ACTIVATE(radio_sensor); + #ifdef COMPILE_SENSORS SENSORS_ACTIVATE(temperature_sensor); SENSORS_ACTIVATE(humidity_sensor); @@ -110,13 +117,19 @@ PROCESS_THREAD(sensor_demo_process, ev, data) printf("LEDs status:\tRED:%s GREEN:%s\n", leds_get()&LEDS_RED?"on":"off", leds_get()&LEDS_GREEN?"on":"off"); #endif /*COMPILE_SENSORS*/ + sensor_value = radio_sensor.value(RADIO_SENSOR_LAST_PACKET); + printf("Radio (RSSI):\t%d.%d dBm\n", sensor_value/10, ABS_VALUE(sensor_value)%10); + printf("Radio (LQI):\t%d\n", radio_sensor.value(RADIO_SENSOR_LAST_VALUE)); #ifdef COMPILE_SENSORS - printf("Temperature:\t%d.%d C\n", temperature_sensor.value(0)/10, temperature_sensor.value(0)%10); + sensor_value = temperature_sensor.value(0); + printf("Temperature:\t%d.%d C\n", sensor_value/10, ABS_VALUE(sensor_value)%10); - printf("Humidity:\t%d.%d rH\n", humidity_sensor.value(0)/10, humidity_sensor.value(0)%10); + sensor_value = humidity_sensor.value(0); + printf("Humidity:\t%d.%d rH\n", sensor_value/10, ABS_VALUE(sensor_value)%10); - printf("Pressure:\t%d.%d mbar\n", pressure_sensor.value(0)/10, pressure_sensor.value(0)%10); + sensor_value = pressure_sensor.value(0); + printf("Pressure:\t%d.%d mbar\n", sensor_value/10, ABS_VALUE(sensor_value)%10); printf("Magneto:\t%d/%d/%d (X/Y/Z) mgauss\n", magneto_sensor.value(X_AXIS), magneto_sensor.value(Y_AXIS), diff --git a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 index fc6c50f6a..c24b0b4c2 100644 --- a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 +++ b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 @@ -48,7 +48,7 @@ CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/sensors/hts221 stm32cube-lib/driver endif -ARCH_DEV = button-sensor.c leds-arch.c +ARCH_DEV = button-sensor.c leds-arch.c radio-sensor.c ARCH_DEV_SENSORS = temperature-sensor.c humidity-sensor.c pressure-sensor.c magneto-sensor.c acceleration-sensor.c gyroscope-sensor.c diff --git a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c index c8ab0edf9..237e8e101 100644 --- a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c +++ b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c @@ -67,6 +67,7 @@ #include "hw-config.h" #include "stdbool.h" #include "dev/button-sensor.h" +#include "dev/radio-sensor.h" /*---------------------------------------------------------------------------*/ #if NETSTACK_CONF_WITH_IPV6 #include "net/ipv6/uip-ds6.h" @@ -80,6 +81,7 @@ extern const struct sensors_sensor magneto_sensor; extern const struct sensors_sensor acceleration_sensor; extern const struct sensors_sensor gyroscope_sensor; SENSORS(&button_sensor, + &radio_sensor, &temperature_sensor, &humidity_sensor, &pressure_sensor, @@ -87,7 +89,8 @@ SENSORS(&button_sensor, &acceleration_sensor, &gyroscope_sensor); #else /*COMPILE_SENSORS*/ -SENSORS(&button_sensor); +SENSORS(&button_sensor, + &radio_sensor); #endif /*COMPILE_SENSORS*/ /*---------------------------------------------------------------------------*/ extern unsigned char node_mac[8]; diff --git a/platform/stm32nucleo-spirit1/dev/radio-sensor.c b/platform/stm32nucleo-spirit1/dev/radio-sensor.c new file mode 100644 index 000000000..34a0f3b98 --- /dev/null +++ b/platform/stm32nucleo-spirit1/dev/radio-sensor.c @@ -0,0 +1,125 @@ +/** +****************************************************************************** +* @file platform/stm32nucleo-spirit1/dev/radio-sensor.c +* @author System LAB +* @version V1.0.0 +* @date 7-September-2015 +* @brief Enable radio sensor functionality +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2014 STMicroelectronics

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Radio Sensor (RSSI, LQI, ...) + */ +/*---------------------------------------------------------------------------*/ +#include "dev/radio-sensor.h" +#include "dev/sensor-common.h" +#include "lib/sensors.h" +#include "net/packetbuf.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +static int _active; +/*---------------------------------------------------------------------------*/ +static void init(void) +{ + /*Nothing to do at the moment, can be used in the future.*/ +} +/*---------------------------------------------------------------------------*/ +static void activate(void) +{ + _active = 1; +} +/*---------------------------------------------------------------------------*/ +static void deactivate(void) +{ + _active = 0; +} +/*---------------------------------------------------------------------------*/ +static int active(void) +{ + return _active; +} +/*---------------------------------------------------------------------------*/ +static int value(int type) +{ + int32_t radio_sensor; + float radio_sensor_value; + + switch(type) { + case RADIO_SENSOR_LAST_PACKET: + /*TODO: check which method of getting these value is more appropriate */ + radio_sensor_value = DBM_VALUE(packetbuf_attr(PACKETBUF_ATTR_RSSI)); + //radio_sensor_value = st_lib_spirit_qi_get_rssi_dbm(); + radio_sensor = (int32_t) (radio_sensor_value * 10); + break; + case RADIO_SENSOR_LAST_VALUE: + default: + /*TODO: check which method of getting these value is more appropriate */ + radio_sensor = packetbuf_attr(PACKETBUF_ATTR_LINK_QUALITY); + //radio_sensor = (int32_t) st_lib_spirit_qi_get_lqi(); + } + + return radio_sensor; +} +/*---------------------------------------------------------------------------*/ +static int configure(int type, int value) +{ + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +static int status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(radio_sensor, RADIO_SENSOR, value, configure, status); +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/sensor-common.h b/platform/stm32nucleo-spirit1/dev/sensor-common.h index 0b1368203..dad78cac9 100644 --- a/platform/stm32nucleo-spirit1/dev/sensor-common.h +++ b/platform/stm32nucleo-spirit1/dev/sensor-common.h @@ -50,6 +50,9 @@ #define X_AXIS 0x00 #define Y_AXIS 0x01 #define Z_AXIS 0x02 + +#define ABS_VALUE(x) (((x)>0)?(x):(-(x))) +#define DBM_VALUE(x) (-120.0+((float)((x)-20))/2) /*---------------------------------------------------------------------------*/ #endif /*SENSOR_COMMON_H_*/ /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/platform-conf.h b/platform/stm32nucleo-spirit1/platform-conf.h index 513b8feed..ed80ca010 100644 --- a/platform/stm32nucleo-spirit1/platform-conf.h +++ b/platform/stm32nucleo-spirit1/platform-conf.h @@ -56,6 +56,7 @@ /*---------------------------------------------------------------------------*/ #define PLATFORM_HAS_LEDS 1 #define PLATFORM_HAS_BUTTON 1 +#define PLATFORM_HAS_RADIO 1 #define LEDS_GREEN 1 /*Nucleo LED*/ #define LEDS_RED 2 /*SPIRIT1 LED*/ diff --git a/platform/stm32nucleo-spirit1/spirit1.c b/platform/stm32nucleo-spirit1/spirit1.c index 3c9cc679e..0006bb993 100644 --- a/platform/stm32nucleo-spirit1/spirit1.c +++ b/platform/stm32nucleo-spirit1/spirit1.c @@ -81,6 +81,8 @@ extern volatile st_lib_spirit_flag_status rx_timeout; /*---------------------------------------------------------------------------*/ static volatile unsigned int spirit_on = OFF; static volatile uint8_t receiving_packet = 0; +static packetbuf_attr_t last_rssi = 0 ; //MGR +static packetbuf_attr_t last_lqi = 0 ; //MGR /*---------------------------------------------------------------------------*/ /* * The buffers which hold incoming data. @@ -407,6 +409,8 @@ static int spirit_radio_read(void *buf, unsigned short bufsize) /* Copies the packet received */ memcpy(buf, spirit_rxbuf + 1, spirit_rxbuf[0]); + packetbuf_set_attr(PACKETBUF_ATTR_RSSI, last_rssi); //MGR + packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, last_lqi); //MGR bufsize = spirit_rxbuf[0]; CLEAR_RXBUF(); @@ -685,6 +689,9 @@ spirit1_interrupt_callback(void) process_poll(&spirit_radio_process); + last_rssi = (packetbuf_attr_t) st_lib_spirit_qi_get_rssi(); //MGR + last_lqi = (packetbuf_attr_t) st_lib_spirit_qi_get_lqi(); //MGR + receiving_packet = 0; #if NULLRDC_CONF_802154_AUTOACK From 87970a88a4b103eb19b635291994e17dcecbe734 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Thu, 10 Sep 2015 14:28:08 +0200 Subject: [PATCH 15/23] Comments and documentation fixes. --- cpu/arm/stm32l152/clock.c | 4 +--- examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c | 5 +++++ platform/stm32nucleo-spirit1/README.md | 9 +++++---- platform/stm32nucleo-spirit1/dev/acceleration-sensor.c | 5 +++++ platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c | 5 +++++ platform/stm32nucleo-spirit1/dev/magneto-sensor.c | 5 +++++ 6 files changed, 26 insertions(+), 7 deletions(-) diff --git a/cpu/arm/stm32l152/clock.c b/cpu/arm/stm32l152/clock.c index 57ed8eba4..d45b054ff 100644 --- a/cpu/arm/stm32l152/clock.c +++ b/cpu/arm/stm32l152/clock.c @@ -92,9 +92,7 @@ void clock_delay(unsigned int i) } } /*---------------------------------------------------------------------------*/ -/** - * Wait for a multiple of clock ticks (7.8 ms at 128 Hz). - */ +/* Wait for a multiple of clock ticks (7.8 ms at 128 Hz). */ void clock_wait(clock_time_t t) { clock_time_t start; diff --git a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c index 49ff705f9..0884e3da8 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c +++ b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c @@ -131,6 +131,11 @@ PROCESS_THREAD(sensor_demo_process, ev, data) sensor_value = pressure_sensor.value(0); printf("Pressure:\t%d.%d mbar\n", sensor_value/10, ABS_VALUE(sensor_value)%10); + /* NOTE: this demo uses the mapping of ST Nucleo sensors on Contiki sensor API. + * For a real use case of sensors like acceleration, magneto and gyroscope, + * it is better to directly call the ST lib to get the three value (X/Y/Z) + * at once. + */ printf("Magneto:\t%d/%d/%d (X/Y/Z) mgauss\n", magneto_sensor.value(X_AXIS), magneto_sensor.value(Y_AXIS), magneto_sensor.value(Z_AXIS)); diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index e81672a69..f004b32d2 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -63,15 +63,16 @@ Software Requirements The following software are needed: * ST port of Contiki for STM32 Nucleo and expansion boards. - >The port is installed automatically when both the Contiki and the submodule repository are cloned: the former hosts the Contiki distribution and the ST platform interface, the latter hosts the actual library. + >The port is automatically installed when both the Contiki and the submodule repository are cloned: the former hosts the Contiki distribution and the ST platform interface, the latter hosts the actual library. The following commands are needed to download the full porting: - git clone https://github.com/STclab/contiki.git (*) + git clone https://github.com/STclab/contiki.git cd contiki/ - git checkout stm32nucleo-spirit1 (*) + git checkout stm32nucleo-spirit1 git submodule init git submodule update -(*): required only if using the STclab GitHub repository, these steps won't be needed once the Pull Request will be accepted + +Note: the first and third steps are required only if using the STclab GitHub repository, they won't be needed any more once the Pull Request is accepted. The platform name is: stm32nucleo-spirit1 diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c index 288faab98..e41761dea 100644 --- a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c @@ -80,6 +80,11 @@ static int value(int type) int32_t ret_val = 0; volatile st_lib_axes_raw_typedef axes_raw_data; + /* NOTE: this is a demo of mapping ST Nucleo sensors on Contiki sensor API. + * For a real use case of sensors like acceleration, magneto and gyroscope, + * it is better to directly call the ST lib to get the three value (X/Y/Z) + * at once. + */ st_lib_bsp_imu_6axes_x_get_axes_raw(&axes_raw_data); switch (type) { diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c index 34ea00139..485a98120 100644 --- a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c @@ -80,6 +80,11 @@ static int value(int type) int32_t ret_val = 0; volatile st_lib_axes_raw_typedef axes_raw_data; + /* NOTE: this is a demo of mapping ST Nucleo sensors on Contiki sensor API. + * For a real use case of sensors like acceleration, magneto and gyroscope, + * it is better to directly call the ST lib to get the three value (X/Y/Z) + * at once. + */ st_lib_bsp_imu_6axes_g_get_axes_raw(&axes_raw_data); switch (type) { diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c index 6535b37b4..deda61954 100644 --- a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c @@ -76,6 +76,11 @@ static int value(int type) int32_t ret_val = 0; volatile st_lib_axes_raw_typedef axes_raw_data; + /* NOTE: this is a demo of mapping ST Nucleo sensors on Contiki sensor API. + * For a real use case of sensors like acceleration, magneto and gyroscope, + * it is better to directly call the ST lib to get the three value (X/Y/Z) + * at once. + */ st_lib_bsp_magneto_m_get_axes_raw(&axes_raw_data); switch (type) { From 875bfd0a1a77431987c06a4f01db5f55ac2caa59 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 11 Sep 2015 15:56:12 +0200 Subject: [PATCH 16/23] Updates of REAME files (main and submodule). --- platform/stm32nucleo-spirit1/README.md | 18 ++++++++++-------- platform/stm32nucleo-spirit1/stm32cube-lib | 2 +- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index f004b32d2..d94771eca 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -7,7 +7,7 @@ Port Feature ============ The port supports the following boards from ST: -- NUCLEO-L152RE board, based on the STM32L152RET6 ultra-low power microcontroller +- NUCLEO-L152RE board, based on the STM32L152RET6 ultra-low power microcontroller - X-NUCLEO-IDS01A4 based on sub-1GHz SPSGRF-868 SPIRIT1 module (operating at 868 MHz) - X-NUCLEO-IDS01A5 based on sub-1GHz SPSGRF-915 SPIRIT1 module (operating at 915 MHz) - X-NUCLEO-IKS01A1 featuring motion MEMS and environmental sensors (optional) @@ -63,14 +63,15 @@ Software Requirements The following software are needed: * ST port of Contiki for STM32 Nucleo and expansion boards. - >The port is automatically installed when both the Contiki and the submodule repository are cloned: the former hosts the Contiki distribution and the ST platform interface, the latter hosts the actual library. -The following commands are needed to download the full porting: + + >The port is automatically installed when both the Contiki and the submodule repository are cloned: the former hosts the Contiki distribution and the ST platform interface, the latter hosts the actual library. The following commands are needed to download the full porting: + + git clone https://github.com/STclab/contiki.git + cd contiki/ + git checkout stm32nucleo-spirit1 + git submodule init + git submodule update - git clone https://github.com/STclab/contiki.git - cd contiki/ - git checkout stm32nucleo-spirit1 - git submodule init - git submodule update Note: the first and third steps are required only if using the STclab GitHub repository, they won't be needed any more once the Pull Request is accepted. @@ -151,3 +152,4 @@ automatically created when plugging the STM32 Nucleo board to the PC. + diff --git a/platform/stm32nucleo-spirit1/stm32cube-lib b/platform/stm32nucleo-spirit1/stm32cube-lib index 25a065a28..6ff4221d0 160000 --- a/platform/stm32nucleo-spirit1/stm32cube-lib +++ b/platform/stm32nucleo-spirit1/stm32cube-lib @@ -1 +1 @@ -Subproject commit 25a065a28e4b1e05adb92df834939271fe6a700c +Subproject commit 6ff4221d03963844364616e6499e9401c0321c28 From fc6575711486a79b372f395da525a0b3195a50b6 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Fri, 9 Oct 2015 19:40:39 +0200 Subject: [PATCH 17/23] License headers and code style fixes. --- cpu/arm/stm32l152/Makefile.stm32l152 | 2 +- cpu/arm/stm32l152/clock.c | 211 +- cpu/arm/stm32l152/console.c | 378 +- cpu/arm/stm32l152/console.h | 64 +- cpu/arm/stm32l152/crt.c | 106 +- cpu/arm/stm32l152/mtarch.h | 89 +- cpu/arm/stm32l152/regs.h | 17160 ++++++++-------- cpu/arm/stm32l152/rtimer-arch.c | 209 +- cpu/arm/stm32l152/rtimer-arch.h | 90 +- cpu/arm/stm32l152/syscalls.c | 66 + cpu/arm/stm32l152/sysmem.c | 67 - cpu/arm/stm32l152/uart.c | 70 +- cpu/arm/stm32l152/watchdog.c | 127 +- .../sensor-demo/sensor-demo.c | 127 +- platform/stm32nucleo-spirit1/contiki-conf.h | 292 +- .../contiki-spirit1-main.c | 393 +- .../dev/acceleration-sensor.c | 144 +- .../dev/acceleration-sensor.h | 66 +- .../stm32nucleo-spirit1/dev/button-sensor.c | 220 +- .../dev/gyroscope-sensor.c | 144 +- .../dev/gyroscope-sensor.h | 66 +- .../stm32nucleo-spirit1/dev/humidity-sensor.c | 242 +- .../stm32nucleo-spirit1/dev/humidity-sensor.h | 66 +- platform/stm32nucleo-spirit1/dev/leds-arch.c | 92 +- .../stm32nucleo-spirit1/dev/magneto-sensor.c | 140 +- .../stm32nucleo-spirit1/dev/magneto-sensor.h | 66 +- .../stm32nucleo-spirit1/dev/pressure-sensor.c | 120 +- .../stm32nucleo-spirit1/dev/pressure-sensor.h | 66 +- .../stm32nucleo-spirit1/dev/radio-sensor.c | 141 +- .../stm32nucleo-spirit1/dev/sensor-common.h | 70 +- .../dev/temperature-sensor.c | 240 +- .../dev/temperature-sensor.h | 66 +- platform/stm32nucleo-spirit1/dev/uart1.h | 102 +- platform/stm32nucleo-spirit1/hw-config.h | 242 +- platform/stm32nucleo-spirit1/node-id.c | 115 +- platform/stm32nucleo-spirit1/platform-conf.h | 224 +- platform/stm32nucleo-spirit1/spirit1-arch.c | 164 +- platform/stm32nucleo-spirit1/spirit1-arch.h | 98 +- platform/stm32nucleo-spirit1/spirit1-config.h | 118 +- platform/stm32nucleo-spirit1/spirit1-const.h | 130 +- platform/stm32nucleo-spirit1/spirit1.c | 1432 +- platform/stm32nucleo-spirit1/spirit1.h | 92 +- platform/stm32nucleo-spirit1/st-lib.h | 69 +- .../stm32l-spirit1-config.h | 200 +- platform/stm32nucleo-spirit1/uart-msg.c | 183 +- 45 files changed, 12232 insertions(+), 12337 deletions(-) create mode 100644 cpu/arm/stm32l152/syscalls.c delete mode 100644 cpu/arm/stm32l152/sysmem.c diff --git a/cpu/arm/stm32l152/Makefile.stm32l152 b/cpu/arm/stm32l152/Makefile.stm32l152 index c0ac54a43..4d461df0c 100644 --- a/cpu/arm/stm32l152/Makefile.stm32l152 +++ b/cpu/arm/stm32l152/Makefile.stm32l152 @@ -25,7 +25,7 @@ CONTIKI_CPU_ARCH= watchdog.c \ clock.c ifdef GCC -CONTIKI_CPU_PORT= sysmem.c \ +CONTIKI_CPU_PORT= syscalls.c \ console.c \ crt.c \ uart.c diff --git a/cpu/arm/stm32l152/clock.c b/cpu/arm/stm32l152/clock.c index d45b054ff..a2a48e44b 100644 --- a/cpu/arm/stm32l152/clock.c +++ b/cpu/arm/stm32l152/clock.c @@ -1,102 +1,109 @@ -/* -* Copyright (c) 2012, STMicroelectronics. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the Institute nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -* -*/ -/*---------------------------------------------------------------------------*/ -#include -#include "contiki.h" -#include "platform-conf.h" -#include "contiki-conf.h" -#include "dev/leds.h" -#include "stm32l1xx.h" -#include "stm32l1xx_hal_rcc.h" -#include "stm32l1xx_hal_cortex.h" -#include "stm32l1xx_hal.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -#define RELOAD_VALUE ((F_CPU/CLOCK_CONF_SECOND) - 1) -/*---------------------------------------------------------------------------*/ -static volatile unsigned long seconds = 0; -static volatile clock_time_t ticks; -void st_lib_sys_tick_handler(void); -/*---------------------------------------------------------------------------*/ -void st_lib_sys_tick_handler(void) -{ - ticks++; - if((ticks % CLOCK_SECOND) == 0) { - seconds++; - energest_flush(); - } - HAL_IncTick(); - - if(etimer_pending()) { - etimer_request_poll(); - } -} -/*---------------------------------------------------------------------------*/ -void clock_init(void) -{ - ticks = 0; - st_lib_hal_systick_clk_source_config(SYSTICK_CLKSOURCE_HCLK); - st_lib_hal_systick_config(RELOAD_VALUE); -} -/*---------------------------------------------------------------------------*/ -unsigned long clock_seconds(void) -{ - return seconds; -} -/*---------------------------------------------------------------------------*/ -void clock_set_seconds(unsigned long sec) -{ - seconds = sec; -} -/*---------------------------------------------------------------------------*/ -clock_time_t clock_time(void) -{ - return ticks; -} -/*---------------------------------------------------------------------------*/ -void clock_delay(unsigned int i) -{ - for(; i > 0; i--) { - unsigned int j; - for(j = 50; j > 0; j--) { - asm ("nop"); - } - } -} -/*---------------------------------------------------------------------------*/ -/* Wait for a multiple of clock ticks (7.8 ms at 128 Hz). */ -void clock_wait(clock_time_t t) -{ - clock_time_t start; - start = clock_time(); - while(clock_time() - start < (clock_time_t)t); -} -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#include +#include "contiki.h" +#include "platform-conf.h" +#include "contiki-conf.h" +#include "dev/leds.h" +#include "stm32l1xx.h" +#include "stm32l1xx_hal_rcc.h" +#include "stm32l1xx_hal_cortex.h" +#include "stm32l1xx_hal.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +#define RELOAD_VALUE ((F_CPU / CLOCK_CONF_SECOND) - 1) +/*---------------------------------------------------------------------------*/ +static volatile unsigned long seconds = 0; +static volatile clock_time_t ticks; +void st_lib_sys_tick_handler(void); +/*---------------------------------------------------------------------------*/ +void +st_lib_sys_tick_handler(void) +{ + ticks++; + if((ticks % CLOCK_SECOND) == 0) { + seconds++; + energest_flush(); + } + HAL_IncTick(); + + if(etimer_pending()) { + etimer_request_poll(); + } +} +/*---------------------------------------------------------------------------*/ +void +clock_init(void) +{ + ticks = 0; + st_lib_hal_systick_clk_source_config(SYSTICK_CLKSOURCE_HCLK); + st_lib_hal_systick_config(RELOAD_VALUE); +} +/*---------------------------------------------------------------------------*/ +unsigned long +clock_seconds(void) +{ + return seconds; +} +/*---------------------------------------------------------------------------*/ +void +clock_set_seconds(unsigned long sec) +{ + seconds = sec; +} +/*---------------------------------------------------------------------------*/ +clock_time_t +clock_time(void) +{ + return ticks; +} +/*---------------------------------------------------------------------------*/ +void +clock_delay(unsigned int i) +{ + for(; i > 0; i--) { + unsigned int j; + for(j = 50; j > 0; j--) { + asm ("nop"); + } + } +} +/*---------------------------------------------------------------------------*/ +/* Wait for a multiple of clock ticks (7.8 ms at 128 Hz). */ +void +clock_wait(clock_time_t t) +{ + clock_time_t start; + start = clock_time(); + while(clock_time() - start < (clock_time_t)t) ; +} +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/console.c b/cpu/arm/stm32l152/console.c index f3b2896f4..6a619a5c1 100644 --- a/cpu/arm/stm32l152/console.c +++ b/cpu/arm/stm32l152/console.c @@ -1,189 +1,189 @@ -/** - ****************************************************************************** - * @file console.c - * @author AST - * @version V1.0.0 - * @date 26-Aug-2014 - * @brief This file provides implementation of standard input/output - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/*---------------------------------------------------------------------------*/ -#include -#include -#include "console.h" -#include "stm32l1xx.h" -#include "stm32l1xx_hal_dma.h" -#include "stm32l1xx_hal_uart.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -extern st_lib_uart_handle_typedef st_lib_uart_handle; -/*---------------------------------------------------------------------------*/ -/** - * @brief Initialises Nucleo UART port for user IO - * @retval 0 - */ -int console_init(void) -{ - st_lib_uart_handle.Instance = USART2; - - st_lib_uart_handle.Init.BaudRate = 115200; - st_lib_uart_handle.Init.WordLength = UART_WORDLENGTH_8B; - st_lib_uart_handle.Init.StopBits = UART_STOPBITS_1; - st_lib_uart_handle.Init.Parity = UART_PARITY_NONE; - st_lib_uart_handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - st_lib_uart_handle.Init.Mode = UART_MODE_TX_RX; - - st_lib_hal_uart_init(&st_lib_uart_handle); - - return 0; -} -/*---------------------------------------------------------------------------*/ -/** @brief Sends a character to serial port - * @param ch Character to send - * @retval Character sent - */ -int uart_send_char(int ch) -{ - st_lib_hal_uart_transmit(&st_lib_uart_handle, (uint8_t *)&ch, 1, HAL_MAX_DELAY); - return ch; -} -/*---------------------------------------------------------------------------*/ -/** @brief Receives a character from serial port - * @retval Character received - */ -int uart_receive_char(void) -{ - uint8_t ch; - st_lib_hal_uart_receive(&st_lib_uart_handle, &ch, 1, HAL_MAX_DELAY); - - /* Echo character back to console */ - st_lib_hal_uart_transmit(&st_lib_uart_handle, &ch, 1, HAL_MAX_DELAY); - - /* And cope with Windows */ - if(ch == '\r'){ - uint8_t ret = '\n'; - st_lib_hal_uart_transmit(&st_lib_uart_handle, &ret, 1, HAL_MAX_DELAY); - } - - return ch; -} -/*---------------------------------------------------------------------------*/ -#if defined (__IAR_SYSTEMS_ICC__) - -size_t __write(int Handle, const unsigned char * Buf, size_t Bufsize); -size_t __read(int Handle, unsigned char *Buf, size_t Bufsize); - -/** @brief IAR specific low level standard input - * @param handle IAR internal handle - * @param buf Buffer where to store characters read from stdin - * @param bufsize Number of characters to read - * @retval Number of characters read - */ -size_t __read(int handle, unsigned char *buf, size_t bufsize) -{ - int i; - - if (handle != 0){ - return -1; - } - - for(i=0; i +#include +#include "console.h" +#include "stm32l1xx.h" +#include "stm32l1xx_hal_dma.h" +#include "stm32l1xx_hal_uart.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +extern st_lib_uart_handle_typedef st_lib_uart_handle; +/*---------------------------------------------------------------------------*/ +/** + * @brief Initialises Nucleo UART port for user IO + * @retval 0 + */ +int +console_init(void) +{ + st_lib_uart_handle.Instance = USART2; + + st_lib_uart_handle.Init.BaudRate = 115200; + st_lib_uart_handle.Init.WordLength = UART_WORDLENGTH_8B; + st_lib_uart_handle.Init.StopBits = UART_STOPBITS_1; + st_lib_uart_handle.Init.Parity = UART_PARITY_NONE; + st_lib_uart_handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + st_lib_uart_handle.Init.Mode = UART_MODE_TX_RX; + + st_lib_hal_uart_init(&st_lib_uart_handle); + + return 0; +} +/*---------------------------------------------------------------------------*/ +/** @brief Sends a character to serial port + * @param ch Character to send + * @retval Character sent + */ +int +uart_send_char(int ch) +{ + st_lib_hal_uart_transmit(&st_lib_uart_handle, (uint8_t *)&ch, 1, HAL_MAX_DELAY); + return ch; +} +/*---------------------------------------------------------------------------*/ +/** @brief Receives a character from serial port + * @retval Character received + */ +int +uart_receive_char(void) +{ + uint8_t ch; + st_lib_hal_uart_receive(&st_lib_uart_handle, &ch, 1, HAL_MAX_DELAY); + + /* Echo character back to console */ + st_lib_hal_uart_transmit(&st_lib_uart_handle, &ch, 1, HAL_MAX_DELAY); + + /* And cope with Windows */ + if(ch == '\r') { + uint8_t ret = '\n'; + st_lib_hal_uart_transmit(&st_lib_uart_handle, &ret, 1, HAL_MAX_DELAY); + } + + return ch; +} +/*---------------------------------------------------------------------------*/ +#if defined(__IAR_SYSTEMS_ICC__) + +size_t __write(int Handle, const unsigned char *Buf, size_t Bufsize); +size_t __read(int Handle, unsigned char *Buf, size_t Bufsize); + +/** @brief IAR specific low level standard input + * @param handle IAR internal handle + * @param buf Buffer where to store characters read from stdin + * @param bufsize Number of characters to read + * @retval Number of characters read + */ +size_t +__read(int handle, unsigned char *buf, size_t bufsize) +{ + int i; + + if(handle != 0) { + return -1; + } + + for(i = 0; i < bufsize; i++) { + buf[i] = uart_receive_char(); + } + + return bufsize; +} +/** @brief IAR specific low level standard output + * @param handle IAR internal handle + * @param buf Buffer containing characters to be written to stdout + * @param bufsize Number of characters to write + * @retval Number of characters read + */ +size_t +__write(int handle, const unsigned char *buf, size_t bufsize) +{ + int i; + + if(handle != 1 && handle != 2) { + return -1; + } + + for(i = 0; i < bufsize; i++) { + uart_send_char(buf[i]); + } + + return bufsize; +} +/*---------------------------------------------------------------------------*/ +#elif defined(__CC_ARM) +/** + * @brief fputc call for standard output implementation + * @param ch Character to print + * @param f File pointer + * @retval Character printed + */ +int +fputc(int ch, FILE *f) +{ + return uart_send_char(ch); +} +/** @brief fgetc call for standard input implementation + * @param f File pointer + * @retval Character acquired from standard input + */ +int +fgetc(FILE *f) +{ + return uart_receive_char(); +} +/*---------------------------------------------------------------------------*/ +#elif defined(__GNUC__) + +/** @brief putchar call for standard output implementation + * @param ch Character to print + * @retval Character printed + */ +int +__io_putchar(int ch) +{ + return uart_send_char(ch); +} +/** @brief getchar call for standard input implementation + * @param None + * @retval Character acquired from standard input + */ +int +__io_getchar(void) +{ + return uart_receive_char(); +} +/*---------------------------------------------------------------------------*/ +#else +#error "Toolchain not supported" +#endif +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/console.h b/cpu/arm/stm32l152/console.h index 2df903d61..20a04ec8e 100644 --- a/cpu/arm/stm32l152/console.h +++ b/cpu/arm/stm32l152/console.h @@ -1,45 +1,39 @@ -/** - ****************************************************************************** - * @file console.h - * @author AST - * @version V1.0.0 - * @date 26-Aug-2014 - * @brief This file provides implementation of standard input/output - ****************************************************************************** - * @attention +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * * - ****************************************************************************** */ /*---------------------------------------------------------------------------*/ -#if defined (__IAR_SYSTEMS_ICC__) -size_t __write(int handle, const unsigned char * buf, size_t bufsize); +#if defined(__IAR_SYSTEMS_ICC__) +size_t __write(int handle, const unsigned char *buf, size_t bufsize); size_t __read(int handle, unsigned char *buf, size_t bufsize); /*---------------------------------------------------------------------------*/ -#elif defined (__CC_ARM) +#elif defined(__CC_ARM) /** * @brief fputc call for standard output implementation * @param ch Character to print @@ -54,7 +48,7 @@ int fputc(int ch, FILE *f); */ int fgetc(FILE *f); /*---------------------------------------------------------------------------*/ -#elif defined (__GNUC__) +#elif defined(__GNUC__) /** @brief putchar call for standard output implementation * @param ch Character to print * @retval Character printed diff --git a/cpu/arm/stm32l152/crt.c b/cpu/arm/stm32l152/crt.c index 30f68a845..0022eff66 100644 --- a/cpu/arm/stm32l152/crt.c +++ b/cpu/arm/stm32l152/crt.c @@ -1,84 +1,86 @@ -/** -****************************************************************************** -* @file main.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief source file -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ #include #include /*---------------------------------------------------------------------------*/ -int _lseek (int file, - int ptr, - int dir) +int +_lseek(int file, + int ptr, + int dir) { return 0; } /*---------------------------------------------------------------------------*/ -int _close (int file) +int +_close(int file) { return -1; } /*---------------------------------------------------------------------------*/ -void _exit (int n) +void +_exit(int n) { /* FIXME: return code is thrown away. */ - while(1); + while(1) ; } /*---------------------------------------------------------------------------*/ -int _kill (int n, int m) +int +_kill(int n, int m) { - return -1; + return -1; } /*---------------------------------------------------------------------------*/ -int _fstat(int file, struct stat *st) +int +_fstat(int file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } /*---------------------------------------------------------------------------*/ -int _isatty (int fd) +int +_isatty(int fd) { return 1; fd = fd; } /*---------------------------------------------------------------------------*/ -int _getpid (int n) -{ - return -1; -} -/*---------------------------------------------------------------------------*/ -int _open (const char * path, int flags, ...) +int +_getpid(int n) +{ + return -1; +} +/*---------------------------------------------------------------------------*/ +int +_open(const char *path, int flags, ...) { return -1; } diff --git a/cpu/arm/stm32l152/mtarch.h b/cpu/arm/stm32l152/mtarch.h index b8792fb7e..0f18b4015 100644 --- a/cpu/arm/stm32l152/mtarch.h +++ b/cpu/arm/stm32l152/mtarch.h @@ -1,47 +1,42 @@ -/** - ****************************************************************************** - * @file console.c - * @author AST - * @version V1.0.0 - * @date 26-Aug-2014 - * @brief This file provides implementation of standard input/output - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* - * Implementation of multithreading in ARM Cortex-M3. To be done. - */ -#ifndef __MTARCH_H__ -#define __MTARCH_H__ -/*---------------------------------------------------------------------------*/ -struct mtarch_thread { - short mt_thread; -}; -/*---------------------------------------------------------------------------*/ -#endif /* __MTARCH_H__ */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/* + * Implementation of multithreading in ARM Cortex-M3. To be done. + */ +#ifndef __MTARCH_H__ +#define __MTARCH_H__ +/*---------------------------------------------------------------------------*/ +struct mtarch_thread { + short mt_thread; +}; +/*---------------------------------------------------------------------------*/ +#endif /* __MTARCH_H__ */ diff --git a/cpu/arm/stm32l152/regs.h b/cpu/arm/stm32l152/regs.h index 6d570f31c..6d80c3622 100644 --- a/cpu/arm/stm32l152/regs.h +++ b/cpu/arm/stm32l152/regs.h @@ -1,33 +1,33 @@ /* -* Copyright (c) 2012, STMicroelectronics. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the Institute nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -* -*/ + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ #ifndef REGS_H_ #define REGS_H_ 1 @@ -74,341 +74,341 @@ #define HV_SPARE_REG *((volatile uint32_t *)0x40000000u) #define HV_SPARE_ADDR (0x40000000u) #define HV_SPARE_RESET (0x00000000u) - /* HV_SPARE field */ - #define HV_SPARE_HV_SPARE (0x000000FFu) - #define HV_SPARE_HV_SPARE_MASK (0x000000FFu) - #define HV_SPARE_HV_SPARE_BIT (0) - #define HV_SPARE_HV_SPARE_BITS (8) +/* HV_SPARE field */ +#define HV_SPARE_HV_SPARE (0x000000FFu) +#define HV_SPARE_HV_SPARE_MASK (0x000000FFu) +#define HV_SPARE_HV_SPARE_BIT (0) +#define HV_SPARE_HV_SPARE_BITS (8) #define EVENT_CTRL *((volatile uint32_t *)0x40000004u) #define EVENT_CTRL_REG *((volatile uint32_t *)0x40000004u) #define EVENT_CTRL_ADDR (0x40000004u) #define EVENT_CTRL_RESET (0x00000000u) - /* LV_FREEZE field */ - #define LV_FREEZE (0x00000002u) - #define LV_FREEZE_MASK (0x00000002u) - #define LV_FREEZE_BIT (1) - #define LV_FREEZE_BITS (1) +/* LV_FREEZE field */ +#define LV_FREEZE (0x00000002u) +#define LV_FREEZE_MASK (0x00000002u) +#define LV_FREEZE_BIT (1) +#define LV_FREEZE_BITS (1) #define SLEEPTMR_CLKEN *((volatile uint32_t *)0x40000008u) #define SLEEPTMR_CLKEN_REG *((volatile uint32_t *)0x40000008u) #define SLEEPTMR_CLKEN_ADDR (0x40000008u) #define SLEEPTMR_CLKEN_RESET (0x00000002u) - /* SLEEPTMR_CLK10KEN field */ - #define SLEEPTMR_CLK10KEN (0x00000002u) - #define SLEEPTMR_CLK10KEN_MASK (0x00000002u) - #define SLEEPTMR_CLK10KEN_BIT (1) - #define SLEEPTMR_CLK10KEN_BITS (1) - /* SLEEPTMR_CLK32KEN field */ - #define SLEEPTMR_CLK32KEN (0x00000001u) - #define SLEEPTMR_CLK32KEN_MASK (0x00000001u) - #define SLEEPTMR_CLK32KEN_BIT (0) - #define SLEEPTMR_CLK32KEN_BITS (1) +/* SLEEPTMR_CLK10KEN field */ +#define SLEEPTMR_CLK10KEN (0x00000002u) +#define SLEEPTMR_CLK10KEN_MASK (0x00000002u) +#define SLEEPTMR_CLK10KEN_BIT (1) +#define SLEEPTMR_CLK10KEN_BITS (1) +/* SLEEPTMR_CLK32KEN field */ +#define SLEEPTMR_CLK32KEN (0x00000001u) +#define SLEEPTMR_CLK32KEN_MASK (0x00000001u) +#define SLEEPTMR_CLK32KEN_BIT (0) +#define SLEEPTMR_CLK32KEN_BITS (1) #define CLKRC_TUNE *((volatile uint32_t *)0x4000000Cu) #define CLKRC_TUNE_REG *((volatile uint32_t *)0x4000000Cu) #define CLKRC_TUNE_ADDR (0x4000000Cu) #define CLKRC_TUNE_RESET (0x00000000u) - /* CLKRC_TUNE_FIELD field */ - #define CLKRC_TUNE_FIELD (0x0000000Fu) - #define CLKRC_TUNE_FIELD_MASK (0x0000000Fu) - #define CLKRC_TUNE_FIELD_BIT (0) - #define CLKRC_TUNE_FIELD_BITS (4) +/* CLKRC_TUNE_FIELD field */ +#define CLKRC_TUNE_FIELD (0x0000000Fu) +#define CLKRC_TUNE_FIELD_MASK (0x0000000Fu) +#define CLKRC_TUNE_FIELD_BIT (0) +#define CLKRC_TUNE_FIELD_BITS (4) #define CLK1K_CAL *((volatile uint32_t *)0x40000010u) #define CLK1K_CAL_REG *((volatile uint32_t *)0x40000010u) #define CLK1K_CAL_ADDR (0x40000010u) #define CLK1K_CAL_RESET (0x00005000u) - /* CLK1K_INTEGER field */ - #define CLK1K_INTEGER (0x0000F800u) - #define CLK1K_INTEGER_MASK (0x0000F800u) - #define CLK1K_INTEGER_BIT (11) - #define CLK1K_INTEGER_BITS (5) - /* CLK1K_FRACTIONAL field */ - #define CLK1K_FRACTIONAL (0x000007FFu) - #define CLK1K_FRACTIONAL_MASK (0x000007FFu) - #define CLK1K_FRACTIONAL_BIT (0) - #define CLK1K_FRACTIONAL_BITS (11) +/* CLK1K_INTEGER field */ +#define CLK1K_INTEGER (0x0000F800u) +#define CLK1K_INTEGER_MASK (0x0000F800u) +#define CLK1K_INTEGER_BIT (11) +#define CLK1K_INTEGER_BITS (5) +/* CLK1K_FRACTIONAL field */ +#define CLK1K_FRACTIONAL (0x000007FFu) +#define CLK1K_FRACTIONAL_MASK (0x000007FFu) +#define CLK1K_FRACTIONAL_BIT (0) +#define CLK1K_FRACTIONAL_BITS (11) #define REGEN_DSLEEP *((volatile uint32_t *)0x40000014u) #define REGEN_DSLEEP_REG *((volatile uint32_t *)0x40000014u) #define REGEN_DSLEEP_ADDR (0x40000014u) #define REGEN_DSLEEP_RESET (0x00000001u) - /* REGEN_DSLEEP_FIELD field */ - #define REGEN_DSLEEP_FIELD (0x00000001u) - #define REGEN_DSLEEP_FIELD_MASK (0x00000001u) - #define REGEN_DSLEEP_FIELD_BIT (0) - #define REGEN_DSLEEP_FIELD_BITS (1) +/* REGEN_DSLEEP_FIELD field */ +#define REGEN_DSLEEP_FIELD (0x00000001u) +#define REGEN_DSLEEP_FIELD_MASK (0x00000001u) +#define REGEN_DSLEEP_FIELD_BIT (0) +#define REGEN_DSLEEP_FIELD_BITS (1) #define VREG *((volatile uint32_t *)0x40000018u) #define VREG_REG *((volatile uint32_t *)0x40000018u) #define VREG_ADDR (0x40000018u) #define VREG_RESET (0x00000207u) - /* VREF_EN field */ - #define VREG_VREF_EN (0x00008000u) - #define VREG_VREF_EN_MASK (0x00008000u) - #define VREG_VREF_EN_BIT (15) - #define VREG_VREF_EN_BITS (1) - /* VREF_TEST field */ - #define VREG_VREF_TEST (0x00004000u) - #define VREG_VREF_TEST_MASK (0x00004000u) - #define VREG_VREF_TEST_BIT (14) - #define VREG_VREF_TEST_BITS (1) - /* VREG_1V8_EN field */ - #define VREG_VREG_1V8_EN (0x00000800u) - #define VREG_VREG_1V8_EN_MASK (0x00000800u) - #define VREG_VREG_1V8_EN_BIT (11) - #define VREG_VREG_1V8_EN_BITS (1) - /* VREG_1V8_TEST field */ - #define VREG_VREG_1V8_TEST (0x00000400u) - #define VREG_VREG_1V8_TEST_MASK (0x00000400u) - #define VREG_VREG_1V8_TEST_BIT (10) - #define VREG_VREG_1V8_TEST_BITS (1) - /* VREG_1V8_TRIM field */ - #define VREG_VREG_1V8_TRIM (0x00000380u) - #define VREG_VREG_1V8_TRIM_MASK (0x00000380u) - #define VREG_VREG_1V8_TRIM_BIT (7) - #define VREG_VREG_1V8_TRIM_BITS (3) - /* VREG_1V2_EN field */ - #define VREG_VREG_1V2_EN (0x00000010u) - #define VREG_VREG_1V2_EN_MASK (0x00000010u) - #define VREG_VREG_1V2_EN_BIT (4) - #define VREG_VREG_1V2_EN_BITS (1) - /* VREG_1V2_TEST field */ - #define VREG_VREG_1V2_TEST (0x00000008u) - #define VREG_VREG_1V2_TEST_MASK (0x00000008u) - #define VREG_VREG_1V2_TEST_BIT (3) - #define VREG_VREG_1V2_TEST_BITS (1) - /* VREG_1V2_TRIM field */ - #define VREG_VREG_1V2_TRIM (0x00000007u) - #define VREG_VREG_1V2_TRIM_MASK (0x00000007u) - #define VREG_VREG_1V2_TRIM_BIT (0) - #define VREG_VREG_1V2_TRIM_BITS (3) +/* VREF_EN field */ +#define VREG_VREF_EN (0x00008000u) +#define VREG_VREF_EN_MASK (0x00008000u) +#define VREG_VREF_EN_BIT (15) +#define VREG_VREF_EN_BITS (1) +/* VREF_TEST field */ +#define VREG_VREF_TEST (0x00004000u) +#define VREG_VREF_TEST_MASK (0x00004000u) +#define VREG_VREF_TEST_BIT (14) +#define VREG_VREF_TEST_BITS (1) +/* VREG_1V8_EN field */ +#define VREG_VREG_1V8_EN (0x00000800u) +#define VREG_VREG_1V8_EN_MASK (0x00000800u) +#define VREG_VREG_1V8_EN_BIT (11) +#define VREG_VREG_1V8_EN_BITS (1) +/* VREG_1V8_TEST field */ +#define VREG_VREG_1V8_TEST (0x00000400u) +#define VREG_VREG_1V8_TEST_MASK (0x00000400u) +#define VREG_VREG_1V8_TEST_BIT (10) +#define VREG_VREG_1V8_TEST_BITS (1) +/* VREG_1V8_TRIM field */ +#define VREG_VREG_1V8_TRIM (0x00000380u) +#define VREG_VREG_1V8_TRIM_MASK (0x00000380u) +#define VREG_VREG_1V8_TRIM_BIT (7) +#define VREG_VREG_1V8_TRIM_BITS (3) +/* VREG_1V2_EN field */ +#define VREG_VREG_1V2_EN (0x00000010u) +#define VREG_VREG_1V2_EN_MASK (0x00000010u) +#define VREG_VREG_1V2_EN_BIT (4) +#define VREG_VREG_1V2_EN_BITS (1) +/* VREG_1V2_TEST field */ +#define VREG_VREG_1V2_TEST (0x00000008u) +#define VREG_VREG_1V2_TEST_MASK (0x00000008u) +#define VREG_VREG_1V2_TEST_BIT (3) +#define VREG_VREG_1V2_TEST_BITS (1) +/* VREG_1V2_TRIM field */ +#define VREG_VREG_1V2_TRIM (0x00000007u) +#define VREG_VREG_1V2_TRIM_MASK (0x00000007u) +#define VREG_VREG_1V2_TRIM_BIT (0) +#define VREG_VREG_1V2_TRIM_BITS (3) #define WAKE_SEL *((volatile uint32_t *)0x40000020u) #define WAKE_SEL_REG *((volatile uint32_t *)0x40000020u) #define WAKE_SEL_ADDR (0x40000020u) #define WAKE_SEL_RESET (0x00000200u) - /* WAKE_CSYSPWRUPREQ field */ - #define WAKE_CSYSPWRUPREQ (0x00000200u) - #define WAKE_CSYSPWRUPREQ_MASK (0x00000200u) - #define WAKE_CSYSPWRUPREQ_BIT (9) - #define WAKE_CSYSPWRUPREQ_BITS (1) - /* WAKE_CDBGPWRUPREQ field */ - #define WAKE_CDBGPWRUPREQ (0x00000100u) - #define WAKE_CDBGPWRUPREQ_MASK (0x00000100u) - #define WAKE_CDBGPWRUPREQ_BIT (8) - #define WAKE_CDBGPWRUPREQ_BITS (1) - /* WAKE_WAKE_CORE field */ - #define WAKE_WAKE_CORE (0x00000080u) - #define WAKE_WAKE_CORE_MASK (0x00000080u) - #define WAKE_WAKE_CORE_BIT (7) - #define WAKE_WAKE_CORE_BITS (1) - /* WAKE_SLEEPTMRWRAP field */ - #define WAKE_SLEEPTMRWRAP (0x00000040u) - #define WAKE_SLEEPTMRWRAP_MASK (0x00000040u) - #define WAKE_SLEEPTMRWRAP_BIT (6) - #define WAKE_SLEEPTMRWRAP_BITS (1) - /* WAKE_SLEEPTMRCMPB field */ - #define WAKE_SLEEPTMRCMPB (0x00000020u) - #define WAKE_SLEEPTMRCMPB_MASK (0x00000020u) - #define WAKE_SLEEPTMRCMPB_BIT (5) - #define WAKE_SLEEPTMRCMPB_BITS (1) - /* WAKE_SLEEPTMRCMPA field */ - #define WAKE_SLEEPTMRCMPA (0x00000010u) - #define WAKE_SLEEPTMRCMPA_MASK (0x00000010u) - #define WAKE_SLEEPTMRCMPA_BIT (4) - #define WAKE_SLEEPTMRCMPA_BITS (1) - /* WAKE_IRQD field */ - #define WAKE_IRQD (0x00000008u) - #define WAKE_IRQD_MASK (0x00000008u) - #define WAKE_IRQD_BIT (3) - #define WAKE_IRQD_BITS (1) - /* WAKE_SC2 field */ - #define WAKE_SC2 (0x00000004u) - #define WAKE_SC2_MASK (0x00000004u) - #define WAKE_SC2_BIT (2) - #define WAKE_SC2_BITS (1) - /* WAKE_SC1 field */ - #define WAKE_SC1 (0x00000002u) - #define WAKE_SC1_MASK (0x00000002u) - #define WAKE_SC1_BIT (1) - #define WAKE_SC1_BITS (1) - /* GPIO_WAKE field */ - #define GPIO_WAKE (0x00000001u) - #define GPIO_WAKE_MASK (0x00000001u) - #define GPIO_WAKE_BIT (0) - #define GPIO_WAKE_BITS (1) +/* WAKE_CSYSPWRUPREQ field */ +#define WAKE_CSYSPWRUPREQ (0x00000200u) +#define WAKE_CSYSPWRUPREQ_MASK (0x00000200u) +#define WAKE_CSYSPWRUPREQ_BIT (9) +#define WAKE_CSYSPWRUPREQ_BITS (1) +/* WAKE_CDBGPWRUPREQ field */ +#define WAKE_CDBGPWRUPREQ (0x00000100u) +#define WAKE_CDBGPWRUPREQ_MASK (0x00000100u) +#define WAKE_CDBGPWRUPREQ_BIT (8) +#define WAKE_CDBGPWRUPREQ_BITS (1) +/* WAKE_WAKE_CORE field */ +#define WAKE_WAKE_CORE (0x00000080u) +#define WAKE_WAKE_CORE_MASK (0x00000080u) +#define WAKE_WAKE_CORE_BIT (7) +#define WAKE_WAKE_CORE_BITS (1) +/* WAKE_SLEEPTMRWRAP field */ +#define WAKE_SLEEPTMRWRAP (0x00000040u) +#define WAKE_SLEEPTMRWRAP_MASK (0x00000040u) +#define WAKE_SLEEPTMRWRAP_BIT (6) +#define WAKE_SLEEPTMRWRAP_BITS (1) +/* WAKE_SLEEPTMRCMPB field */ +#define WAKE_SLEEPTMRCMPB (0x00000020u) +#define WAKE_SLEEPTMRCMPB_MASK (0x00000020u) +#define WAKE_SLEEPTMRCMPB_BIT (5) +#define WAKE_SLEEPTMRCMPB_BITS (1) +/* WAKE_SLEEPTMRCMPA field */ +#define WAKE_SLEEPTMRCMPA (0x00000010u) +#define WAKE_SLEEPTMRCMPA_MASK (0x00000010u) +#define WAKE_SLEEPTMRCMPA_BIT (4) +#define WAKE_SLEEPTMRCMPA_BITS (1) +/* WAKE_IRQD field */ +#define WAKE_IRQD (0x00000008u) +#define WAKE_IRQD_MASK (0x00000008u) +#define WAKE_IRQD_BIT (3) +#define WAKE_IRQD_BITS (1) +/* WAKE_SC2 field */ +#define WAKE_SC2 (0x00000004u) +#define WAKE_SC2_MASK (0x00000004u) +#define WAKE_SC2_BIT (2) +#define WAKE_SC2_BITS (1) +/* WAKE_SC1 field */ +#define WAKE_SC1 (0x00000002u) +#define WAKE_SC1_MASK (0x00000002u) +#define WAKE_SC1_BIT (1) +#define WAKE_SC1_BITS (1) +/* GPIO_WAKE field */ +#define GPIO_WAKE (0x00000001u) +#define GPIO_WAKE_MASK (0x00000001u) +#define GPIO_WAKE_BIT (0) +#define GPIO_WAKE_BITS (1) #define WAKE_CORE *((volatile uint32_t *)0x40000024u) #define WAKE_CORE_REG *((volatile uint32_t *)0x40000024u) #define WAKE_CORE_ADDR (0x40000024u) #define WAKE_CORE_RESET (0x00000000u) - /* WAKE_CORE_FIELD field */ - #define WAKE_CORE_FIELD (0x00000020u) - #define WAKE_CORE_FIELD_MASK (0x00000020u) - #define WAKE_CORE_FIELD_BIT (5) - #define WAKE_CORE_FIELD_BITS (1) +/* WAKE_CORE_FIELD field */ +#define WAKE_CORE_FIELD (0x00000020u) +#define WAKE_CORE_FIELD_MASK (0x00000020u) +#define WAKE_CORE_FIELD_BIT (5) +#define WAKE_CORE_FIELD_BITS (1) #define PWRUP_EVENT *((volatile uint32_t *)0x40000028u) #define PWRUP_EVENT_REG *((volatile uint32_t *)0x40000028u) #define PWRUP_EVENT_ADDR (0x40000028u) #define PWRUP_EVENT_RESET (0x00000000u) - /* PWRUP_CSYSPWRUPREQ field */ - #define PWRUP_CSYSPWRUPREQ (0x00000200u) - #define PWRUP_CSYSPWRUPREQ_MASK (0x00000200u) - #define PWRUP_CSYSPWRUPREQ_BIT (9) - #define PWRUP_CSYSPWRUPREQ_BITS (1) - /* PWRUP_CDBGPWRUPREQ field */ - #define PWRUP_CDBGPWRUPREQ (0x00000100u) - #define PWRUP_CDBGPWRUPREQ_MASK (0x00000100u) - #define PWRUP_CDBGPWRUPREQ_BIT (8) - #define PWRUP_CDBGPWRUPREQ_BITS (1) - /* PWRUP_WAKECORE field */ - #define PWRUP_WAKECORE (0x00000080u) - #define PWRUP_WAKECORE_MASK (0x00000080u) - #define PWRUP_WAKECORE_BIT (7) - #define PWRUP_WAKECORE_BITS (1) - /* PWRUP_SLEEPTMRWRAP field */ - #define PWRUP_SLEEPTMRWRAP (0x00000040u) - #define PWRUP_SLEEPTMRWRAP_MASK (0x00000040u) - #define PWRUP_SLEEPTMRWRAP_BIT (6) - #define PWRUP_SLEEPTMRWRAP_BITS (1) - /* PWRUP_SLEEPTMRCOMPB field */ - #define PWRUP_SLEEPTMRCOMPB (0x00000020u) - #define PWRUP_SLEEPTMRCOMPB_MASK (0x00000020u) - #define PWRUP_SLEEPTMRCOMPB_BIT (5) - #define PWRUP_SLEEPTMRCOMPB_BITS (1) - /* PWRUP_SLEEPTMRCOMPA field */ - #define PWRUP_SLEEPTMRCOMPA (0x00000010u) - #define PWRUP_SLEEPTMRCOMPA_MASK (0x00000010u) - #define PWRUP_SLEEPTMRCOMPA_BIT (4) - #define PWRUP_SLEEPTMRCOMPA_BITS (1) - /* PWRUP_IRQD field */ - #define PWRUP_IRQD (0x00000008u) - #define PWRUP_IRQD_MASK (0x00000008u) - #define PWRUP_IRQD_BIT (3) - #define PWRUP_IRQD_BITS (1) - /* PWRUP_SC2 field */ - #define PWRUP_SC2 (0x00000004u) - #define PWRUP_SC2_MASK (0x00000004u) - #define PWRUP_SC2_BIT (2) - #define PWRUP_SC2_BITS (1) - /* PWRUP_SC1 field */ - #define PWRUP_SC1 (0x00000002u) - #define PWRUP_SC1_MASK (0x00000002u) - #define PWRUP_SC1_BIT (1) - #define PWRUP_SC1_BITS (1) - /* PWRUP_GPIO field */ - #define PWRUP_GPIO (0x00000001u) - #define PWRUP_GPIO_MASK (0x00000001u) - #define PWRUP_GPIO_BIT (0) - #define PWRUP_GPIO_BITS (1) +/* PWRUP_CSYSPWRUPREQ field */ +#define PWRUP_CSYSPWRUPREQ (0x00000200u) +#define PWRUP_CSYSPWRUPREQ_MASK (0x00000200u) +#define PWRUP_CSYSPWRUPREQ_BIT (9) +#define PWRUP_CSYSPWRUPREQ_BITS (1) +/* PWRUP_CDBGPWRUPREQ field */ +#define PWRUP_CDBGPWRUPREQ (0x00000100u) +#define PWRUP_CDBGPWRUPREQ_MASK (0x00000100u) +#define PWRUP_CDBGPWRUPREQ_BIT (8) +#define PWRUP_CDBGPWRUPREQ_BITS (1) +/* PWRUP_WAKECORE field */ +#define PWRUP_WAKECORE (0x00000080u) +#define PWRUP_WAKECORE_MASK (0x00000080u) +#define PWRUP_WAKECORE_BIT (7) +#define PWRUP_WAKECORE_BITS (1) +/* PWRUP_SLEEPTMRWRAP field */ +#define PWRUP_SLEEPTMRWRAP (0x00000040u) +#define PWRUP_SLEEPTMRWRAP_MASK (0x00000040u) +#define PWRUP_SLEEPTMRWRAP_BIT (6) +#define PWRUP_SLEEPTMRWRAP_BITS (1) +/* PWRUP_SLEEPTMRCOMPB field */ +#define PWRUP_SLEEPTMRCOMPB (0x00000020u) +#define PWRUP_SLEEPTMRCOMPB_MASK (0x00000020u) +#define PWRUP_SLEEPTMRCOMPB_BIT (5) +#define PWRUP_SLEEPTMRCOMPB_BITS (1) +/* PWRUP_SLEEPTMRCOMPA field */ +#define PWRUP_SLEEPTMRCOMPA (0x00000010u) +#define PWRUP_SLEEPTMRCOMPA_MASK (0x00000010u) +#define PWRUP_SLEEPTMRCOMPA_BIT (4) +#define PWRUP_SLEEPTMRCOMPA_BITS (1) +/* PWRUP_IRQD field */ +#define PWRUP_IRQD (0x00000008u) +#define PWRUP_IRQD_MASK (0x00000008u) +#define PWRUP_IRQD_BIT (3) +#define PWRUP_IRQD_BITS (1) +/* PWRUP_SC2 field */ +#define PWRUP_SC2 (0x00000004u) +#define PWRUP_SC2_MASK (0x00000004u) +#define PWRUP_SC2_BIT (2) +#define PWRUP_SC2_BITS (1) +/* PWRUP_SC1 field */ +#define PWRUP_SC1 (0x00000002u) +#define PWRUP_SC1_MASK (0x00000002u) +#define PWRUP_SC1_BIT (1) +#define PWRUP_SC1_BITS (1) +/* PWRUP_GPIO field */ +#define PWRUP_GPIO (0x00000001u) +#define PWRUP_GPIO_MASK (0x00000001u) +#define PWRUP_GPIO_BIT (0) +#define PWRUP_GPIO_BITS (1) #define RESET_EVENT *((volatile uint32_t *)0x4000002Cu) #define RESET_EVENT_REG *((volatile uint32_t *)0x4000002Cu) #define RESET_EVENT_ADDR (0x4000002Cu) #define RESET_EVENT_RESET (0x00000001u) - /* RESET_CPULOCKUP field */ - #define RESET_CPULOCKUP (0x00000080u) - #define RESET_CPULOCKUP_MASK (0x00000080u) - #define RESET_CPULOCKUP_BIT (7) - #define RESET_CPULOCKUP_BITS (1) - /* RESET_OPTBYTEFAIL field */ - #define RESET_OPTBYTEFAIL (0x00000040u) - #define RESET_OPTBYTEFAIL_MASK (0x00000040u) - #define RESET_OPTBYTEFAIL_BIT (6) - #define RESET_OPTBYTEFAIL_BITS (1) - /* RESET_DSLEEP field */ - #define RESET_DSLEEP (0x00000020u) - #define RESET_DSLEEP_MASK (0x00000020u) - #define RESET_DSLEEP_BIT (5) - #define RESET_DSLEEP_BITS (1) - /* RESET_SW field */ - #define RESET_SW (0x00000010u) - #define RESET_SW_MASK (0x00000010u) - #define RESET_SW_BIT (4) - #define RESET_SW_BITS (1) - /* RESET_WDOG field */ - #define RESET_WDOG (0x00000008u) - #define RESET_WDOG_MASK (0x00000008u) - #define RESET_WDOG_BIT (3) - #define RESET_WDOG_BITS (1) - /* RESET_NRESET field */ - #define RESET_NRESET (0x00000004u) - #define RESET_NRESET_MASK (0x00000004u) - #define RESET_NRESET_BIT (2) - #define RESET_NRESET_BITS (1) - /* RESET_PWRLV field */ - #define RESET_PWRLV (0x00000002u) - #define RESET_PWRLV_MASK (0x00000002u) - #define RESET_PWRLV_BIT (1) - #define RESET_PWRLV_BITS (1) - /* RESET_PWRHV field */ - #define RESET_PWRHV (0x00000001u) - #define RESET_PWRHV_MASK (0x00000001u) - #define RESET_PWRHV_BIT (0) - #define RESET_PWRHV_BITS (1) +/* RESET_CPULOCKUP field */ +#define RESET_CPULOCKUP (0x00000080u) +#define RESET_CPULOCKUP_MASK (0x00000080u) +#define RESET_CPULOCKUP_BIT (7) +#define RESET_CPULOCKUP_BITS (1) +/* RESET_OPTBYTEFAIL field */ +#define RESET_OPTBYTEFAIL (0x00000040u) +#define RESET_OPTBYTEFAIL_MASK (0x00000040u) +#define RESET_OPTBYTEFAIL_BIT (6) +#define RESET_OPTBYTEFAIL_BITS (1) +/* RESET_DSLEEP field */ +#define RESET_DSLEEP (0x00000020u) +#define RESET_DSLEEP_MASK (0x00000020u) +#define RESET_DSLEEP_BIT (5) +#define RESET_DSLEEP_BITS (1) +/* RESET_SW field */ +#define RESET_SW (0x00000010u) +#define RESET_SW_MASK (0x00000010u) +#define RESET_SW_BIT (4) +#define RESET_SW_BITS (1) +/* RESET_WDOG field */ +#define RESET_WDOG (0x00000008u) +#define RESET_WDOG_MASK (0x00000008u) +#define RESET_WDOG_BIT (3) +#define RESET_WDOG_BITS (1) +/* RESET_NRESET field */ +#define RESET_NRESET (0x00000004u) +#define RESET_NRESET_MASK (0x00000004u) +#define RESET_NRESET_BIT (2) +#define RESET_NRESET_BITS (1) +/* RESET_PWRLV field */ +#define RESET_PWRLV (0x00000002u) +#define RESET_PWRLV_MASK (0x00000002u) +#define RESET_PWRLV_BIT (1) +#define RESET_PWRLV_BITS (1) +/* RESET_PWRHV field */ +#define RESET_PWRHV (0x00000001u) +#define RESET_PWRHV_MASK (0x00000001u) +#define RESET_PWRHV_BIT (0) +#define RESET_PWRHV_BITS (1) #define DBG_MBOX *((volatile uint32_t *)0x40000030u) #define DBG_MBOX_REG *((volatile uint32_t *)0x40000030u) #define DBG_MBOX_ADDR (0x40000030u) #define DBG_MBOX_RESET (0x00000000u) - /* DBG_MBOX field */ - #define DBG_MBOX_DBG_MBOX (0x0000FFFFu) - #define DBG_MBOX_DBG_MBOX_MASK (0x0000FFFFu) - #define DBG_MBOX_DBG_MBOX_BIT (0) - #define DBG_MBOX_DBG_MBOX_BITS (16) +/* DBG_MBOX field */ +#define DBG_MBOX_DBG_MBOX (0x0000FFFFu) +#define DBG_MBOX_DBG_MBOX_MASK (0x0000FFFFu) +#define DBG_MBOX_DBG_MBOX_BIT (0) +#define DBG_MBOX_DBG_MBOX_BITS (16) #define CPWRUPREQ_STATUS *((volatile uint32_t *)0x40000034u) #define CPWRUPREQ_STATUS_REG *((volatile uint32_t *)0x40000034u) #define CPWRUPREQ_STATUS_ADDR (0x40000034u) #define CPWRUPREQ_STATUS_RESET (0x00000000u) - /* CPWRUPREQ field */ - #define CPWRUPREQ_STATUS_CPWRUPREQ (0x00000001u) - #define CPWRUPREQ_STATUS_CPWRUPREQ_MASK (0x00000001u) - #define CPWRUPREQ_STATUS_CPWRUPREQ_BIT (0) - #define CPWRUPREQ_STATUS_CPWRUPREQ_BITS (1) +/* CPWRUPREQ field */ +#define CPWRUPREQ_STATUS_CPWRUPREQ (0x00000001u) +#define CPWRUPREQ_STATUS_CPWRUPREQ_MASK (0x00000001u) +#define CPWRUPREQ_STATUS_CPWRUPREQ_BIT (0) +#define CPWRUPREQ_STATUS_CPWRUPREQ_BITS (1) #define CSYSPWRUPREQ_STATUS *((volatile uint32_t *)0x40000038u) #define CSYSPWRUPREQ_STATUS_REG *((volatile uint32_t *)0x40000038u) #define CSYSPWRUPREQ_STATUS_ADDR (0x40000038u) #define CSYSPWRUPREQ_STATUS_RESET (0x00000000u) - /* CSYSPWRUPREQ field */ - #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ (0x00000001u) - #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_MASK (0x00000001u) - #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT (0) - #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS (1) +/* CSYSPWRUPREQ field */ +#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ (0x00000001u) +#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_MASK (0x00000001u) +#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT (0) +#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS (1) #define CSYSPWRUPACK_STATUS *((volatile uint32_t *)0x4000003Cu) #define CSYSPWRUPACK_STATUS_REG *((volatile uint32_t *)0x4000003Cu) #define CSYSPWRUPACK_STATUS_ADDR (0x4000003Cu) #define CSYSPWRUPACK_STATUS_RESET (0x00000000u) - /* CSYSPWRUPACK field */ - #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK (0x00000001u) - #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_MASK (0x00000001u) - #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT (0) - #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS (1) +/* CSYSPWRUPACK field */ +#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK (0x00000001u) +#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_MASK (0x00000001u) +#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT (0) +#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS (1) #define CSYSPWRUPACK_INHIBIT *((volatile uint32_t *)0x40000040u) #define CSYSPWRUPACK_INHIBIT_REG *((volatile uint32_t *)0x40000040u) #define CSYSPWRUPACK_INHIBIT_ADDR (0x40000040u) #define CSYSPWRUPACK_INHIBIT_RESET (0x00000000u) - /* CSYSPWRUPACK_INHIBIT field */ - #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT (0x00000001u) - #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_MASK (0x00000001u) - #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT (0) - #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS (1) +/* CSYSPWRUPACK_INHIBIT field */ +#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT (0x00000001u) +#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_MASK (0x00000001u) +#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT (0) +#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS (1) #define OPT_ERR_MAINTAIN_WAKE *((volatile uint32_t *)0x40000044u) #define OPT_ERR_MAINTAIN_WAKE_REG *((volatile uint32_t *)0x40000044u) #define OPT_ERR_MAINTAIN_WAKE_ADDR (0x40000044u) #define OPT_ERR_MAINTAIN_WAKE_RESET (0x00000000u) - /* OPT_ERR_MAINTAIN_WAKE field */ - #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE (0x00000001u) - #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_MASK (0x00000001u) - #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BIT (0) - #define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BITS (1) +/* OPT_ERR_MAINTAIN_WAKE field */ +#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE (0x00000001u) +#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_MASK (0x00000001u) +#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BIT (0) +#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BITS (1) /* BASEBAND block */ #define DATA_BASEBAND_BASE (0x40001000u) @@ -419,1066 +419,1066 @@ #define MOD_CAL_CTRL_REG *((volatile uint32_t *)0x40001000u) #define MOD_CAL_CTRL_ADDR (0x40001000u) #define MOD_CAL_CTRL_RESET (0x00000000u) - /* MOD_CAL_GO field */ - #define MOD_CAL_CTRL_MOD_CAL_GO (0x00008000u) - #define MOD_CAL_CTRL_MOD_CAL_GO_MASK (0x00008000u) - #define MOD_CAL_CTRL_MOD_CAL_GO_BIT (15) - #define MOD_CAL_CTRL_MOD_CAL_GO_BITS (1) - /* MOD_CAL_DONE field */ - #define MOD_CAL_CTRL_MOD_CAL_DONE (0x00000010u) - #define MOD_CAL_CTRL_MOD_CAL_DONE_MASK (0x00000010u) - #define MOD_CAL_CTRL_MOD_CAL_DONE_BIT (4) - #define MOD_CAL_CTRL_MOD_CAL_DONE_BITS (1) - /* MOD_CAL_CYCLES field */ - #define MOD_CAL_CTRL_MOD_CAL_CYCLES (0x00000003u) - #define MOD_CAL_CTRL_MOD_CAL_CYCLES_MASK (0x00000003u) - #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT (0) - #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS (2) +/* MOD_CAL_GO field */ +#define MOD_CAL_CTRL_MOD_CAL_GO (0x00008000u) +#define MOD_CAL_CTRL_MOD_CAL_GO_MASK (0x00008000u) +#define MOD_CAL_CTRL_MOD_CAL_GO_BIT (15) +#define MOD_CAL_CTRL_MOD_CAL_GO_BITS (1) +/* MOD_CAL_DONE field */ +#define MOD_CAL_CTRL_MOD_CAL_DONE (0x00000010u) +#define MOD_CAL_CTRL_MOD_CAL_DONE_MASK (0x00000010u) +#define MOD_CAL_CTRL_MOD_CAL_DONE_BIT (4) +#define MOD_CAL_CTRL_MOD_CAL_DONE_BITS (1) +/* MOD_CAL_CYCLES field */ +#define MOD_CAL_CTRL_MOD_CAL_CYCLES (0x00000003u) +#define MOD_CAL_CTRL_MOD_CAL_CYCLES_MASK (0x00000003u) +#define MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT (0) +#define MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS (2) #define MOD_CAL_COUNT_H *((volatile uint32_t *)0x40001004u) #define MOD_CAL_COUNT_H_REG *((volatile uint32_t *)0x40001004u) #define MOD_CAL_COUNT_H_ADDR (0x40001004u) #define MOD_CAL_COUNT_H_RESET (0x00000000u) - /* MOD_CAL_COUNT_H field */ - #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H (0x000000FFu) - #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_MASK (0x000000FFu) - #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT (0) - #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS (8) +/* MOD_CAL_COUNT_H field */ +#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H (0x000000FFu) +#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_MASK (0x000000FFu) +#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT (0) +#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS (8) #define MOD_CAL_COUNT_L *((volatile uint32_t *)0x40001008u) #define MOD_CAL_COUNT_L_REG *((volatile uint32_t *)0x40001008u) #define MOD_CAL_COUNT_L_ADDR (0x40001008u) #define MOD_CAL_COUNT_L_RESET (0x00000000u) - /* MOD_CAL_COUNT_L field */ - #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L (0x0000FFFFu) - #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_MASK (0x0000FFFFu) - #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT (0) - #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS (16) +/* MOD_CAL_COUNT_L field */ +#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L (0x0000FFFFu) +#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_MASK (0x0000FFFFu) +#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT (0) +#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS (16) #define RSSI_ROLLING *((volatile uint32_t *)0x4000100Cu) #define RSSI_ROLLING_REG *((volatile uint32_t *)0x4000100Cu) #define RSSI_ROLLING_ADDR (0x4000100Cu) #define RSSI_ROLLING_RESET (0x00000000u) - /* RSSI_ROLLING field */ - #define RSSI_ROLLING_RSSI_ROLLING (0x00003FFFu) - #define RSSI_ROLLING_RSSI_ROLLING_MASK (0x00003FFFu) - #define RSSI_ROLLING_RSSI_ROLLING_BIT (0) - #define RSSI_ROLLING_RSSI_ROLLING_BITS (14) +/* RSSI_ROLLING field */ +#define RSSI_ROLLING_RSSI_ROLLING (0x00003FFFu) +#define RSSI_ROLLING_RSSI_ROLLING_MASK (0x00003FFFu) +#define RSSI_ROLLING_RSSI_ROLLING_BIT (0) +#define RSSI_ROLLING_RSSI_ROLLING_BITS (14) #define RSSI_PKT *((volatile uint32_t *)0x40001010u) #define RSSI_PKT_REG *((volatile uint32_t *)0x40001010u) #define RSSI_PKT_ADDR (0x40001010u) #define RSSI_PKT_RESET (0x00000000u) - /* RSSI_PKT field */ - #define RSSI_PKT_RSSI_PKT (0x000000FFu) - #define RSSI_PKT_RSSI_PKT_MASK (0x000000FFu) - #define RSSI_PKT_RSSI_PKT_BIT (0) - #define RSSI_PKT_RSSI_PKT_BITS (8) +/* RSSI_PKT field */ +#define RSSI_PKT_RSSI_PKT (0x000000FFu) +#define RSSI_PKT_RSSI_PKT_MASK (0x000000FFu) +#define RSSI_PKT_RSSI_PKT_BIT (0) +#define RSSI_PKT_RSSI_PKT_BITS (8) #define RX_ADC *((volatile uint32_t *)0x40001014u) #define RX_ADC_REG *((volatile uint32_t *)0x40001014u) #define RX_ADC_ADDR (0x40001014u) #define RX_ADC_RESET (0x00000024u) - /* RX_ADC field */ - #define RX_ADC_RX_ADC (0x0000007Fu) - #define RX_ADC_RX_ADC_MASK (0x0000007Fu) - #define RX_ADC_RX_ADC_BIT (0) - #define RX_ADC_RX_ADC_BITS (7) +/* RX_ADC field */ +#define RX_ADC_RX_ADC (0x0000007Fu) +#define RX_ADC_RX_ADC_MASK (0x0000007Fu) +#define RX_ADC_RX_ADC_BIT (0) +#define RX_ADC_RX_ADC_BITS (7) #define DEBUG_BB_MODE *((volatile uint32_t *)0x40001018u) #define DEBUG_BB_MODE_REG *((volatile uint32_t *)0x40001018u) #define DEBUG_BB_MODE_ADDR (0x40001018u) #define DEBUG_BB_MODE_RESET (0x00000000u) - /* DEBUG_BB_MODE_EN field */ - #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN (0x00008000u) - #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_MASK (0x00008000u) - #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BIT (15) - #define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BITS (1) - /* DEBUG_BB_MODE field */ - #define DEBUG_BB_MODE_DEBUG_BB_MODE (0x00000003u) - #define DEBUG_BB_MODE_DEBUG_BB_MODE_MASK (0x00000003u) - #define DEBUG_BB_MODE_DEBUG_BB_MODE_BIT (0) - #define DEBUG_BB_MODE_DEBUG_BB_MODE_BITS (2) +/* DEBUG_BB_MODE_EN field */ +#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN (0x00008000u) +#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_MASK (0x00008000u) +#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BIT (15) +#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BITS (1) +/* DEBUG_BB_MODE field */ +#define DEBUG_BB_MODE_DEBUG_BB_MODE (0x00000003u) +#define DEBUG_BB_MODE_DEBUG_BB_MODE_MASK (0x00000003u) +#define DEBUG_BB_MODE_DEBUG_BB_MODE_BIT (0) +#define DEBUG_BB_MODE_DEBUG_BB_MODE_BITS (2) #define BB_DEBUG *((volatile uint32_t *)0x4000101Cu) #define BB_DEBUG_REG *((volatile uint32_t *)0x4000101Cu) #define BB_DEBUG_ADDR (0x4000101Cu) #define BB_DEBUG_RESET (0x00000002u) - /* SYNC_REG_EN field */ - #define BB_DEBUG_SYNC_REG_EN (0x00008000u) - #define BB_DEBUG_SYNC_REG_EN_MASK (0x00008000u) - #define BB_DEBUG_SYNC_REG_EN_BIT (15) - #define BB_DEBUG_SYNC_REG_EN_BITS (1) - /* DEBUG_MUX_ADDR field */ - #define BB_DEBUG_DEBUG_MUX_ADDR (0x000000F0u) - #define BB_DEBUG_DEBUG_MUX_ADDR_MASK (0x000000F0u) - #define BB_DEBUG_DEBUG_MUX_ADDR_BIT (4) - #define BB_DEBUG_DEBUG_MUX_ADDR_BITS (4) - /* BB_DEBUG_SEL field */ - #define BB_DEBUG_BB_DEBUG_SEL (0x00000003u) - #define BB_DEBUG_BB_DEBUG_SEL_MASK (0x00000003u) - #define BB_DEBUG_BB_DEBUG_SEL_BIT (0) - #define BB_DEBUG_BB_DEBUG_SEL_BITS (2) +/* SYNC_REG_EN field */ +#define BB_DEBUG_SYNC_REG_EN (0x00008000u) +#define BB_DEBUG_SYNC_REG_EN_MASK (0x00008000u) +#define BB_DEBUG_SYNC_REG_EN_BIT (15) +#define BB_DEBUG_SYNC_REG_EN_BITS (1) +/* DEBUG_MUX_ADDR field */ +#define BB_DEBUG_DEBUG_MUX_ADDR (0x000000F0u) +#define BB_DEBUG_DEBUG_MUX_ADDR_MASK (0x000000F0u) +#define BB_DEBUG_DEBUG_MUX_ADDR_BIT (4) +#define BB_DEBUG_DEBUG_MUX_ADDR_BITS (4) +/* BB_DEBUG_SEL field */ +#define BB_DEBUG_BB_DEBUG_SEL (0x00000003u) +#define BB_DEBUG_BB_DEBUG_SEL_MASK (0x00000003u) +#define BB_DEBUG_BB_DEBUG_SEL_BIT (0) +#define BB_DEBUG_BB_DEBUG_SEL_BITS (2) #define BB_DEBUG_VIEW *((volatile uint32_t *)0x40001020u) #define BB_DEBUG_VIEW_REG *((volatile uint32_t *)0x40001020u) #define BB_DEBUG_VIEW_ADDR (0x40001020u) #define BB_DEBUG_VIEW_RESET (0x00000000u) - /* BB_DEBUG_VIEW field */ - #define BB_DEBUG_VIEW_BB_DEBUG_VIEW (0x0000FFFFu) - #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_MASK (0x0000FFFFu) - #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT (0) - #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS (16) +/* BB_DEBUG_VIEW field */ +#define BB_DEBUG_VIEW_BB_DEBUG_VIEW (0x0000FFFFu) +#define BB_DEBUG_VIEW_BB_DEBUG_VIEW_MASK (0x0000FFFFu) +#define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT (0) +#define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS (16) #define IF_FREQ *((volatile uint32_t *)0x40001024u) #define IF_FREQ_REG *((volatile uint32_t *)0x40001024u) #define IF_FREQ_ADDR (0x40001024u) #define IF_FREQ_RESET (0x00000155u) - /* TIMING_CORR_EN field */ - #define IF_FREQ_TIMING_CORR_EN (0x00008000u) - #define IF_FREQ_TIMING_CORR_EN_MASK (0x00008000u) - #define IF_FREQ_TIMING_CORR_EN_BIT (15) - #define IF_FREQ_TIMING_CORR_EN_BITS (1) - /* IF_FREQ field */ - #define IF_FREQ_IF_FREQ (0x000001FFu) - #define IF_FREQ_IF_FREQ_MASK (0x000001FFu) - #define IF_FREQ_IF_FREQ_BIT (0) - #define IF_FREQ_IF_FREQ_BITS (9) +/* TIMING_CORR_EN field */ +#define IF_FREQ_TIMING_CORR_EN (0x00008000u) +#define IF_FREQ_TIMING_CORR_EN_MASK (0x00008000u) +#define IF_FREQ_TIMING_CORR_EN_BIT (15) +#define IF_FREQ_TIMING_CORR_EN_BITS (1) +/* IF_FREQ field */ +#define IF_FREQ_IF_FREQ (0x000001FFu) +#define IF_FREQ_IF_FREQ_MASK (0x000001FFu) +#define IF_FREQ_IF_FREQ_BIT (0) +#define IF_FREQ_IF_FREQ_BITS (9) #define MOD_EN *((volatile uint32_t *)0x40001028u) #define MOD_EN_REG *((volatile uint32_t *)0x40001028u) #define MOD_EN_ADDR (0x40001028u) #define MOD_EN_RESET (0x00000001u) - /* MOD_EN field */ - #define MOD_EN_MOD_EN (0x00000001u) - #define MOD_EN_MOD_EN_MASK (0x00000001u) - #define MOD_EN_MOD_EN_BIT (0) - #define MOD_EN_MOD_EN_BITS (1) +/* MOD_EN field */ +#define MOD_EN_MOD_EN (0x00000001u) +#define MOD_EN_MOD_EN_MASK (0x00000001u) +#define MOD_EN_MOD_EN_BIT (0) +#define MOD_EN_MOD_EN_BITS (1) #define PRESCALE_CTRL *((volatile uint32_t *)0x4000102Cu) #define PRESCALE_CTRL_REG *((volatile uint32_t *)0x4000102Cu) #define PRESCALE_CTRL_ADDR (0x4000102Cu) #define PRESCALE_CTRL_RESET (0x00000000u) - /* PRESCALE_SET field */ - #define PRESCALE_CTRL_PRESCALE_SET (0x00008000u) - #define PRESCALE_CTRL_PRESCALE_SET_MASK (0x00008000u) - #define PRESCALE_CTRL_PRESCALE_SET_BIT (15) - #define PRESCALE_CTRL_PRESCALE_SET_BITS (1) - /* PRESCALE_VAL field */ - #define PRESCALE_CTRL_PRESCALE_VAL (0x00000007u) - #define PRESCALE_CTRL_PRESCALE_VAL_MASK (0x00000007u) - #define PRESCALE_CTRL_PRESCALE_VAL_BIT (0) - #define PRESCALE_CTRL_PRESCALE_VAL_BITS (3) +/* PRESCALE_SET field */ +#define PRESCALE_CTRL_PRESCALE_SET (0x00008000u) +#define PRESCALE_CTRL_PRESCALE_SET_MASK (0x00008000u) +#define PRESCALE_CTRL_PRESCALE_SET_BIT (15) +#define PRESCALE_CTRL_PRESCALE_SET_BITS (1) +/* PRESCALE_VAL field */ +#define PRESCALE_CTRL_PRESCALE_VAL (0x00000007u) +#define PRESCALE_CTRL_PRESCALE_VAL_MASK (0x00000007u) +#define PRESCALE_CTRL_PRESCALE_VAL_BIT (0) +#define PRESCALE_CTRL_PRESCALE_VAL_BITS (3) #define ADC_BYPASS_EN *((volatile uint32_t *)0x40001030u) #define ADC_BYPASS_EN_REG *((volatile uint32_t *)0x40001030u) #define ADC_BYPASS_EN_ADDR (0x40001030u) #define ADC_BYPASS_EN_RESET (0x00000000u) - /* ADC_BYPASS_EN field */ - #define ADC_BYPASS_EN_ADC_BYPASS_EN (0x00000001u) - #define ADC_BYPASS_EN_ADC_BYPASS_EN_MASK (0x00000001u) - #define ADC_BYPASS_EN_ADC_BYPASS_EN_BIT (0) - #define ADC_BYPASS_EN_ADC_BYPASS_EN_BITS (1) +/* ADC_BYPASS_EN field */ +#define ADC_BYPASS_EN_ADC_BYPASS_EN (0x00000001u) +#define ADC_BYPASS_EN_ADC_BYPASS_EN_MASK (0x00000001u) +#define ADC_BYPASS_EN_ADC_BYPASS_EN_BIT (0) +#define ADC_BYPASS_EN_ADC_BYPASS_EN_BITS (1) #define FIXED_CODE_EN *((volatile uint32_t *)0x40001034u) #define FIXED_CODE_EN_REG *((volatile uint32_t *)0x40001034u) #define FIXED_CODE_EN_ADDR (0x40001034u) #define FIXED_CODE_EN_RESET (0x00000000u) - /* FIXED_CODE_EN field */ - #define FIXED_CODE_EN_FIXED_CODE_EN (0x00000001u) - #define FIXED_CODE_EN_FIXED_CODE_EN_MASK (0x00000001u) - #define FIXED_CODE_EN_FIXED_CODE_EN_BIT (0) - #define FIXED_CODE_EN_FIXED_CODE_EN_BITS (1) +/* FIXED_CODE_EN field */ +#define FIXED_CODE_EN_FIXED_CODE_EN (0x00000001u) +#define FIXED_CODE_EN_FIXED_CODE_EN_MASK (0x00000001u) +#define FIXED_CODE_EN_FIXED_CODE_EN_BIT (0) +#define FIXED_CODE_EN_FIXED_CODE_EN_BITS (1) #define FIXED_CODE_H *((volatile uint32_t *)0x40001038u) #define FIXED_CODE_H_REG *((volatile uint32_t *)0x40001038u) #define FIXED_CODE_H_ADDR (0x40001038u) #define FIXED_CODE_H_RESET (0x00000000u) - /* FIXED_CODE_H field */ - #define FIXED_CODE_H_FIXED_CODE_H (0x0000FFFFu) - #define FIXED_CODE_H_FIXED_CODE_H_MASK (0x0000FFFFu) - #define FIXED_CODE_H_FIXED_CODE_H_BIT (0) - #define FIXED_CODE_H_FIXED_CODE_H_BITS (16) +/* FIXED_CODE_H field */ +#define FIXED_CODE_H_FIXED_CODE_H (0x0000FFFFu) +#define FIXED_CODE_H_FIXED_CODE_H_MASK (0x0000FFFFu) +#define FIXED_CODE_H_FIXED_CODE_H_BIT (0) +#define FIXED_CODE_H_FIXED_CODE_H_BITS (16) #define FIXED_CODE_L *((volatile uint32_t *)0x4000103Cu) #define FIXED_CODE_L_REG *((volatile uint32_t *)0x4000103Cu) #define FIXED_CODE_L_ADDR (0x4000103Cu) #define FIXED_CODE_L_RESET (0x00000000u) - /* FIXED_CODE_L field */ - #define FIXED_CODE_L_FIXED_CODE_L (0x0000FFFFu) - #define FIXED_CODE_L_FIXED_CODE_L_MASK (0x0000FFFFu) - #define FIXED_CODE_L_FIXED_CODE_L_BIT (0) - #define FIXED_CODE_L_FIXED_CODE_L_BITS (16) +/* FIXED_CODE_L field */ +#define FIXED_CODE_L_FIXED_CODE_L (0x0000FFFFu) +#define FIXED_CODE_L_FIXED_CODE_L_MASK (0x0000FFFFu) +#define FIXED_CODE_L_FIXED_CODE_L_BIT (0) +#define FIXED_CODE_L_FIXED_CODE_L_BITS (16) #define FIXED_CODE_L_SHADOW *((volatile uint32_t *)0x40001040u) #define FIXED_CODE_L_SHADOW_REG *((volatile uint32_t *)0x40001040u) #define FIXED_CODE_L_SHADOW_ADDR (0x40001040u) #define FIXED_CODE_L_SHADOW_RESET (0x00000000u) - /* FIXED_CODE_L_SHADOW field */ - #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW (0x0000FFFFu) - #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_MASK (0x0000FFFFu) - #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT (0) - #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS (16) +/* FIXED_CODE_L_SHADOW field */ +#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW (0x0000FFFFu) +#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_MASK (0x0000FFFFu) +#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT (0) +#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS (16) #define RX_GAIN_CTRL *((volatile uint32_t *)0x40001044u) #define RX_GAIN_CTRL_REG *((volatile uint32_t *)0x40001044u) #define RX_GAIN_CTRL_ADDR (0x40001044u) #define RX_GAIN_CTRL_RESET (0x00000000u) - /* RX_GAIN_MUX field */ - #define RX_GAIN_CTRL_RX_GAIN_MUX (0x00008000u) - #define RX_GAIN_CTRL_RX_GAIN_MUX_MASK (0x00008000u) - #define RX_GAIN_CTRL_RX_GAIN_MUX_BIT (15) - #define RX_GAIN_CTRL_RX_GAIN_MUX_BITS (1) - /* RX_RF_GAIN_TEST field */ - #define RX_GAIN_CTRL_RX_RF_GAIN_TEST (0x00000080u) - #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_MASK (0x00000080u) - #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BIT (7) - #define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BITS (1) - /* RX_MIXER_GAIN_TEST field */ - #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST (0x00000040u) - #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_MASK (0x00000040u) - #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BIT (6) - #define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BITS (1) - /* RX_FILTER_GAIN_TEST field */ - #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST (0x00000030u) - #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_MASK (0x00000030u) - #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BIT (4) - #define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BITS (2) - /* RX_IF_GAIN_TEST field */ - #define RX_GAIN_CTRL_RX_IF_GAIN_TEST (0x0000000Fu) - #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_MASK (0x0000000Fu) - #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT (0) - #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS (4) +/* RX_GAIN_MUX field */ +#define RX_GAIN_CTRL_RX_GAIN_MUX (0x00008000u) +#define RX_GAIN_CTRL_RX_GAIN_MUX_MASK (0x00008000u) +#define RX_GAIN_CTRL_RX_GAIN_MUX_BIT (15) +#define RX_GAIN_CTRL_RX_GAIN_MUX_BITS (1) +/* RX_RF_GAIN_TEST field */ +#define RX_GAIN_CTRL_RX_RF_GAIN_TEST (0x00000080u) +#define RX_GAIN_CTRL_RX_RF_GAIN_TEST_MASK (0x00000080u) +#define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BIT (7) +#define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BITS (1) +/* RX_MIXER_GAIN_TEST field */ +#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST (0x00000040u) +#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_MASK (0x00000040u) +#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BIT (6) +#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BITS (1) +/* RX_FILTER_GAIN_TEST field */ +#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST (0x00000030u) +#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_MASK (0x00000030u) +#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BIT (4) +#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BITS (2) +/* RX_IF_GAIN_TEST field */ +#define RX_GAIN_CTRL_RX_IF_GAIN_TEST (0x0000000Fu) +#define RX_GAIN_CTRL_RX_IF_GAIN_TEST_MASK (0x0000000Fu) +#define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT (0) +#define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS (4) #define PD_DITHER_EN *((volatile uint32_t *)0x40001048u) #define PD_DITHER_EN_REG *((volatile uint32_t *)0x40001048u) #define PD_DITHER_EN_ADDR (0x40001048u) #define PD_DITHER_EN_RESET (0x00000001u) - /* PD_DITHER_EN field */ - #define PD_DITHER_EN_PD_DITHER_EN (0x00000001u) - #define PD_DITHER_EN_PD_DITHER_EN_MASK (0x00000001u) - #define PD_DITHER_EN_PD_DITHER_EN_BIT (0) - #define PD_DITHER_EN_PD_DITHER_EN_BITS (1) +/* PD_DITHER_EN field */ +#define PD_DITHER_EN_PD_DITHER_EN (0x00000001u) +#define PD_DITHER_EN_PD_DITHER_EN_MASK (0x00000001u) +#define PD_DITHER_EN_PD_DITHER_EN_BIT (0) +#define PD_DITHER_EN_PD_DITHER_EN_BITS (1) #define RX_ERR_THRESH *((volatile uint32_t *)0x4000104Cu) #define RX_ERR_THRESH_REG *((volatile uint32_t *)0x4000104Cu) #define RX_ERR_THRESH_ADDR (0x4000104Cu) #define RX_ERR_THRESH_RESET (0x00004608u) - /* LPF_RX_ERR_COEFF field */ - #define RX_ERR_THRESH_LPF_RX_ERR_COEFF (0x0000E000u) - #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_MASK (0x0000E000u) - #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BIT (13) - #define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BITS (3) - /* LPF_RX_ERR_THRESH field */ - #define RX_ERR_THRESH_LPF_RX_ERR_THRESH (0x00001F00u) - #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_MASK (0x00001F00u) - #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BIT (8) - #define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BITS (5) - /* RX_ERR_THRESH field */ - #define RX_ERR_THRESH_RX_ERR_THRESH (0x0000001Fu) - #define RX_ERR_THRESH_RX_ERR_THRESH_MASK (0x0000001Fu) - #define RX_ERR_THRESH_RX_ERR_THRESH_BIT (0) - #define RX_ERR_THRESH_RX_ERR_THRESH_BITS (5) +/* LPF_RX_ERR_COEFF field */ +#define RX_ERR_THRESH_LPF_RX_ERR_COEFF (0x0000E000u) +#define RX_ERR_THRESH_LPF_RX_ERR_COEFF_MASK (0x0000E000u) +#define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BIT (13) +#define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BITS (3) +/* LPF_RX_ERR_THRESH field */ +#define RX_ERR_THRESH_LPF_RX_ERR_THRESH (0x00001F00u) +#define RX_ERR_THRESH_LPF_RX_ERR_THRESH_MASK (0x00001F00u) +#define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BIT (8) +#define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BITS (5) +/* RX_ERR_THRESH field */ +#define RX_ERR_THRESH_RX_ERR_THRESH (0x0000001Fu) +#define RX_ERR_THRESH_RX_ERR_THRESH_MASK (0x0000001Fu) +#define RX_ERR_THRESH_RX_ERR_THRESH_BIT (0) +#define RX_ERR_THRESH_RX_ERR_THRESH_BITS (5) #define CARRIER_THRESH *((volatile uint32_t *)0x40001050u) #define CARRIER_THRESH_REG *((volatile uint32_t *)0x40001050u) #define CARRIER_THRESH_ADDR (0x40001050u) #define CARRIER_THRESH_RESET (0x00002332u) - /* CARRIER_SPIKE_THRESH field */ - #define CARRIER_THRESH_CARRIER_SPIKE_THRESH (0x0000FF00u) - #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_MASK (0x0000FF00u) - #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BIT (8) - #define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BITS (8) - /* CARRIER_THRESH field */ - #define CARRIER_THRESH_CARRIER_THRESH (0x000000FFu) - #define CARRIER_THRESH_CARRIER_THRESH_MASK (0x000000FFu) - #define CARRIER_THRESH_CARRIER_THRESH_BIT (0) - #define CARRIER_THRESH_CARRIER_THRESH_BITS (8) +/* CARRIER_SPIKE_THRESH field */ +#define CARRIER_THRESH_CARRIER_SPIKE_THRESH (0x0000FF00u) +#define CARRIER_THRESH_CARRIER_SPIKE_THRESH_MASK (0x0000FF00u) +#define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BIT (8) +#define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BITS (8) +/* CARRIER_THRESH field */ +#define CARRIER_THRESH_CARRIER_THRESH (0x000000FFu) +#define CARRIER_THRESH_CARRIER_THRESH_MASK (0x000000FFu) +#define CARRIER_THRESH_CARRIER_THRESH_BIT (0) +#define CARRIER_THRESH_CARRIER_THRESH_BITS (8) #define RSSI_THRESH *((volatile uint32_t *)0x40001054u) #define RSSI_THRESH_REG *((volatile uint32_t *)0x40001054u) #define RSSI_THRESH_ADDR (0x40001054u) #define RSSI_THRESH_RESET (0x00000100u) - /* RSSI_THRESH field */ - #define RSSI_THRESH_RSSI_THRESH (0x0000FFFFu) - #define RSSI_THRESH_RSSI_THRESH_MASK (0x0000FFFFu) - #define RSSI_THRESH_RSSI_THRESH_BIT (0) - #define RSSI_THRESH_RSSI_THRESH_BITS (16) +/* RSSI_THRESH field */ +#define RSSI_THRESH_RSSI_THRESH (0x0000FFFFu) +#define RSSI_THRESH_RSSI_THRESH_MASK (0x0000FFFFu) +#define RSSI_THRESH_RSSI_THRESH_BIT (0) +#define RSSI_THRESH_RSSI_THRESH_BITS (16) #define SYNTH_START *((volatile uint32_t *)0x40001058u) #define SYNTH_START_REG *((volatile uint32_t *)0x40001058u) #define SYNTH_START_ADDR (0x40001058u) #define SYNTH_START_RESET (0x00006464u) - /* SYNTH_WARM_START field */ - #define SYNTH_START_SYNTH_WARM_START (0x0000FF00u) - #define SYNTH_START_SYNTH_WARM_START_MASK (0x0000FF00u) - #define SYNTH_START_SYNTH_WARM_START_BIT (8) - #define SYNTH_START_SYNTH_WARM_START_BITS (8) - /* SYNTH_COLD_START field */ - #define SYNTH_START_SYNTH_COLD_START (0x000000FFu) - #define SYNTH_START_SYNTH_COLD_START_MASK (0x000000FFu) - #define SYNTH_START_SYNTH_COLD_START_BIT (0) - #define SYNTH_START_SYNTH_COLD_START_BITS (8) +/* SYNTH_WARM_START field */ +#define SYNTH_START_SYNTH_WARM_START (0x0000FF00u) +#define SYNTH_START_SYNTH_WARM_START_MASK (0x0000FF00u) +#define SYNTH_START_SYNTH_WARM_START_BIT (8) +#define SYNTH_START_SYNTH_WARM_START_BITS (8) +/* SYNTH_COLD_START field */ +#define SYNTH_START_SYNTH_COLD_START (0x000000FFu) +#define SYNTH_START_SYNTH_COLD_START_MASK (0x000000FFu) +#define SYNTH_START_SYNTH_COLD_START_BIT (0) +#define SYNTH_START_SYNTH_COLD_START_BITS (8) #define IN_LOCK_EN *((volatile uint32_t *)0x4000105Cu) #define IN_LOCK_EN_REG *((volatile uint32_t *)0x4000105Cu) #define IN_LOCK_EN_ADDR (0x4000105Cu) #define IN_LOCK_EN_RESET (0x00000001u) - /* IN_LOCK_EN field */ - #define IN_LOCK_EN_IN_LOCK_EN (0x00000001u) - #define IN_LOCK_EN_IN_LOCK_EN_MASK (0x00000001u) - #define IN_LOCK_EN_IN_LOCK_EN_BIT (0) - #define IN_LOCK_EN_IN_LOCK_EN_BITS (1) +/* IN_LOCK_EN field */ +#define IN_LOCK_EN_IN_LOCK_EN (0x00000001u) +#define IN_LOCK_EN_IN_LOCK_EN_MASK (0x00000001u) +#define IN_LOCK_EN_IN_LOCK_EN_BIT (0) +#define IN_LOCK_EN_IN_LOCK_EN_BITS (1) #define DITHER_AMPLITUDE *((volatile uint32_t *)0x40001060u) #define DITHER_AMPLITUDE_REG *((volatile uint32_t *)0x40001060u) #define DITHER_AMPLITUDE_ADDR (0x40001060u) #define DITHER_AMPLITUDE_RESET (0x0000003Fu) - /* DITHER_AMP field */ - #define DITHER_AMPLITUDE_DITHER_AMP (0x0000003Fu) - #define DITHER_AMPLITUDE_DITHER_AMP_MASK (0x0000003Fu) - #define DITHER_AMPLITUDE_DITHER_AMP_BIT (0) - #define DITHER_AMPLITUDE_DITHER_AMP_BITS (6) +/* DITHER_AMP field */ +#define DITHER_AMPLITUDE_DITHER_AMP (0x0000003Fu) +#define DITHER_AMPLITUDE_DITHER_AMP_MASK (0x0000003Fu) +#define DITHER_AMPLITUDE_DITHER_AMP_BIT (0) +#define DITHER_AMPLITUDE_DITHER_AMP_BITS (6) #define TX_STEP_TIME *((volatile uint32_t *)0x40001064u) #define TX_STEP_TIME_REG *((volatile uint32_t *)0x40001064u) #define TX_STEP_TIME_ADDR (0x40001064u) #define TX_STEP_TIME_RESET (0x00000000u) - /* TX_STEP_TIME field */ - #define TX_STEP_TIME_TX_STEP_TIME (0x000000FFu) - #define TX_STEP_TIME_TX_STEP_TIME_MASK (0x000000FFu) - #define TX_STEP_TIME_TX_STEP_TIME_BIT (0) - #define TX_STEP_TIME_TX_STEP_TIME_BITS (8) +/* TX_STEP_TIME field */ +#define TX_STEP_TIME_TX_STEP_TIME (0x000000FFu) +#define TX_STEP_TIME_TX_STEP_TIME_MASK (0x000000FFu) +#define TX_STEP_TIME_TX_STEP_TIME_BIT (0) +#define TX_STEP_TIME_TX_STEP_TIME_BITS (8) #define GAIN_THRESH_MAX *((volatile uint32_t *)0x40001068u) #define GAIN_THRESH_MAX_REG *((volatile uint32_t *)0x40001068u) #define GAIN_THRESH_MAX_ADDR (0x40001068u) #define GAIN_THRESH_MAX_RESET (0x00000060u) - /* GAIN_THRESH_MAX field */ - #define GAIN_THRESH_MAX_GAIN_THRESH_MAX (0x000000FFu) - #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_MASK (0x000000FFu) - #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT (0) - #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS (8) +/* GAIN_THRESH_MAX field */ +#define GAIN_THRESH_MAX_GAIN_THRESH_MAX (0x000000FFu) +#define GAIN_THRESH_MAX_GAIN_THRESH_MAX_MASK (0x000000FFu) +#define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT (0) +#define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS (8) #define GAIN_THRESH_MID *((volatile uint32_t *)0x4000106Cu) #define GAIN_THRESH_MID_REG *((volatile uint32_t *)0x4000106Cu) #define GAIN_THRESH_MID_ADDR (0x4000106Cu) #define GAIN_THRESH_MID_RESET (0x00000030u) - /* GAIN_THRESH_MID field */ - #define GAIN_THRESH_MID_GAIN_THRESH_MID (0x000000FFu) - #define GAIN_THRESH_MID_GAIN_THRESH_MID_MASK (0x000000FFu) - #define GAIN_THRESH_MID_GAIN_THRESH_MID_BIT (0) - #define GAIN_THRESH_MID_GAIN_THRESH_MID_BITS (8) +/* GAIN_THRESH_MID field */ +#define GAIN_THRESH_MID_GAIN_THRESH_MID (0x000000FFu) +#define GAIN_THRESH_MID_GAIN_THRESH_MID_MASK (0x000000FFu) +#define GAIN_THRESH_MID_GAIN_THRESH_MID_BIT (0) +#define GAIN_THRESH_MID_GAIN_THRESH_MID_BITS (8) #define GAIN_THRESH_MIN *((volatile uint32_t *)0x40001070u) #define GAIN_THRESH_MIN_REG *((volatile uint32_t *)0x40001070u) #define GAIN_THRESH_MIN_ADDR (0x40001070u) #define GAIN_THRESH_MIN_RESET (0x00000018u) - /* GAIN_THRESH_MIN field */ - #define GAIN_THRESH_MIN_GAIN_THRESH_MIN (0x000000FFu) - #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_MASK (0x000000FFu) - #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT (0) - #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS (8) +/* GAIN_THRESH_MIN field */ +#define GAIN_THRESH_MIN_GAIN_THRESH_MIN (0x000000FFu) +#define GAIN_THRESH_MIN_GAIN_THRESH_MIN_MASK (0x000000FFu) +#define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT (0) +#define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS (8) #define GAIN_SETTING_0 *((volatile uint32_t *)0x40001074u) #define GAIN_SETTING_0_REG *((volatile uint32_t *)0x40001074u) #define GAIN_SETTING_0_ADDR (0x40001074u) #define GAIN_SETTING_0_RESET (0x00000000u) - /* RX_MIXER_GAIN_0 field */ - #define GAIN_SETTING_0_RX_MIXER_GAIN_0 (0x00000040u) - #define GAIN_SETTING_0_RX_MIXER_GAIN_0_MASK (0x00000040u) - #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BIT (6) - #define GAIN_SETTING_0_RX_MIXER_GAIN_0_BITS (1) - /* RX_FILTER_GAIN_0 field */ - #define GAIN_SETTING_0_RX_FILTER_GAIN_0 (0x00000030u) - #define GAIN_SETTING_0_RX_FILTER_GAIN_0_MASK (0x00000030u) - #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BIT (4) - #define GAIN_SETTING_0_RX_FILTER_GAIN_0_BITS (2) - /* RX_IF_GAIN_0 field */ - #define GAIN_SETTING_0_RX_IF_GAIN_0 (0x0000000Fu) - #define GAIN_SETTING_0_RX_IF_GAIN_0_MASK (0x0000000Fu) - #define GAIN_SETTING_0_RX_IF_GAIN_0_BIT (0) - #define GAIN_SETTING_0_RX_IF_GAIN_0_BITS (4) +/* RX_MIXER_GAIN_0 field */ +#define GAIN_SETTING_0_RX_MIXER_GAIN_0 (0x00000040u) +#define GAIN_SETTING_0_RX_MIXER_GAIN_0_MASK (0x00000040u) +#define GAIN_SETTING_0_RX_MIXER_GAIN_0_BIT (6) +#define GAIN_SETTING_0_RX_MIXER_GAIN_0_BITS (1) +/* RX_FILTER_GAIN_0 field */ +#define GAIN_SETTING_0_RX_FILTER_GAIN_0 (0x00000030u) +#define GAIN_SETTING_0_RX_FILTER_GAIN_0_MASK (0x00000030u) +#define GAIN_SETTING_0_RX_FILTER_GAIN_0_BIT (4) +#define GAIN_SETTING_0_RX_FILTER_GAIN_0_BITS (2) +/* RX_IF_GAIN_0 field */ +#define GAIN_SETTING_0_RX_IF_GAIN_0 (0x0000000Fu) +#define GAIN_SETTING_0_RX_IF_GAIN_0_MASK (0x0000000Fu) +#define GAIN_SETTING_0_RX_IF_GAIN_0_BIT (0) +#define GAIN_SETTING_0_RX_IF_GAIN_0_BITS (4) #define GAIN_SETTING_1 *((volatile uint32_t *)0x40001078u) #define GAIN_SETTING_1_REG *((volatile uint32_t *)0x40001078u) #define GAIN_SETTING_1_ADDR (0x40001078u) #define GAIN_SETTING_1_RESET (0x00000010u) - /* RX_MIXER_GAIN_1 field */ - #define GAIN_SETTING_1_RX_MIXER_GAIN_1 (0x00000040u) - #define GAIN_SETTING_1_RX_MIXER_GAIN_1_MASK (0x00000040u) - #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BIT (6) - #define GAIN_SETTING_1_RX_MIXER_GAIN_1_BITS (1) - /* RX_FILTER_GAIN_1 field */ - #define GAIN_SETTING_1_RX_FILTER_GAIN_1 (0x00000030u) - #define GAIN_SETTING_1_RX_FILTER_GAIN_1_MASK (0x00000030u) - #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BIT (4) - #define GAIN_SETTING_1_RX_FILTER_GAIN_1_BITS (2) - /* RX_IF_GAIN_1 field */ - #define GAIN_SETTING_1_RX_IF_GAIN_1 (0x0000000Fu) - #define GAIN_SETTING_1_RX_IF_GAIN_1_MASK (0x0000000Fu) - #define GAIN_SETTING_1_RX_IF_GAIN_1_BIT (0) - #define GAIN_SETTING_1_RX_IF_GAIN_1_BITS (4) +/* RX_MIXER_GAIN_1 field */ +#define GAIN_SETTING_1_RX_MIXER_GAIN_1 (0x00000040u) +#define GAIN_SETTING_1_RX_MIXER_GAIN_1_MASK (0x00000040u) +#define GAIN_SETTING_1_RX_MIXER_GAIN_1_BIT (6) +#define GAIN_SETTING_1_RX_MIXER_GAIN_1_BITS (1) +/* RX_FILTER_GAIN_1 field */ +#define GAIN_SETTING_1_RX_FILTER_GAIN_1 (0x00000030u) +#define GAIN_SETTING_1_RX_FILTER_GAIN_1_MASK (0x00000030u) +#define GAIN_SETTING_1_RX_FILTER_GAIN_1_BIT (4) +#define GAIN_SETTING_1_RX_FILTER_GAIN_1_BITS (2) +/* RX_IF_GAIN_1 field */ +#define GAIN_SETTING_1_RX_IF_GAIN_1 (0x0000000Fu) +#define GAIN_SETTING_1_RX_IF_GAIN_1_MASK (0x0000000Fu) +#define GAIN_SETTING_1_RX_IF_GAIN_1_BIT (0) +#define GAIN_SETTING_1_RX_IF_GAIN_1_BITS (4) #define GAIN_SETTING_2 *((volatile uint32_t *)0x4000107Cu) #define GAIN_SETTING_2_REG *((volatile uint32_t *)0x4000107Cu) #define GAIN_SETTING_2_ADDR (0x4000107Cu) #define GAIN_SETTING_2_RESET (0x00000030u) - /* RX_MIXER_GAIN_2 field */ - #define GAIN_SETTING_2_RX_MIXER_GAIN_2 (0x00000040u) - #define GAIN_SETTING_2_RX_MIXER_GAIN_2_MASK (0x00000040u) - #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BIT (6) - #define GAIN_SETTING_2_RX_MIXER_GAIN_2_BITS (1) - /* RX_FILTER_GAIN_2 field */ - #define GAIN_SETTING_2_RX_FILTER_GAIN_2 (0x00000030u) - #define GAIN_SETTING_2_RX_FILTER_GAIN_2_MASK (0x00000030u) - #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BIT (4) - #define GAIN_SETTING_2_RX_FILTER_GAIN_2_BITS (2) - /* RX_IF_GAIN_2 field */ - #define GAIN_SETTING_2_RX_IF_GAIN_2 (0x0000000Fu) - #define GAIN_SETTING_2_RX_IF_GAIN_2_MASK (0x0000000Fu) - #define GAIN_SETTING_2_RX_IF_GAIN_2_BIT (0) - #define GAIN_SETTING_2_RX_IF_GAIN_2_BITS (4) +/* RX_MIXER_GAIN_2 field */ +#define GAIN_SETTING_2_RX_MIXER_GAIN_2 (0x00000040u) +#define GAIN_SETTING_2_RX_MIXER_GAIN_2_MASK (0x00000040u) +#define GAIN_SETTING_2_RX_MIXER_GAIN_2_BIT (6) +#define GAIN_SETTING_2_RX_MIXER_GAIN_2_BITS (1) +/* RX_FILTER_GAIN_2 field */ +#define GAIN_SETTING_2_RX_FILTER_GAIN_2 (0x00000030u) +#define GAIN_SETTING_2_RX_FILTER_GAIN_2_MASK (0x00000030u) +#define GAIN_SETTING_2_RX_FILTER_GAIN_2_BIT (4) +#define GAIN_SETTING_2_RX_FILTER_GAIN_2_BITS (2) +/* RX_IF_GAIN_2 field */ +#define GAIN_SETTING_2_RX_IF_GAIN_2 (0x0000000Fu) +#define GAIN_SETTING_2_RX_IF_GAIN_2_MASK (0x0000000Fu) +#define GAIN_SETTING_2_RX_IF_GAIN_2_BIT (0) +#define GAIN_SETTING_2_RX_IF_GAIN_2_BITS (4) #define GAIN_SETTING_3 *((volatile uint32_t *)0x40001080u) #define GAIN_SETTING_3_REG *((volatile uint32_t *)0x40001080u) #define GAIN_SETTING_3_ADDR (0x40001080u) #define GAIN_SETTING_3_RESET (0x00000031u) - /* RX_MIXER_GAIN_3 field */ - #define GAIN_SETTING_3_RX_MIXER_GAIN_3 (0x00000040u) - #define GAIN_SETTING_3_RX_MIXER_GAIN_3_MASK (0x00000040u) - #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BIT (6) - #define GAIN_SETTING_3_RX_MIXER_GAIN_3_BITS (1) - /* RX_FILTER_GAIN_3 field */ - #define GAIN_SETTING_3_RX_FILTER_GAIN_3 (0x00000030u) - #define GAIN_SETTING_3_RX_FILTER_GAIN_3_MASK (0x00000030u) - #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BIT (4) - #define GAIN_SETTING_3_RX_FILTER_GAIN_3_BITS (2) - /* RX_IF_GAIN_3 field */ - #define GAIN_SETTING_3_RX_IF_GAIN_3 (0x0000000Fu) - #define GAIN_SETTING_3_RX_IF_GAIN_3_MASK (0x0000000Fu) - #define GAIN_SETTING_3_RX_IF_GAIN_3_BIT (0) - #define GAIN_SETTING_3_RX_IF_GAIN_3_BITS (4) +/* RX_MIXER_GAIN_3 field */ +#define GAIN_SETTING_3_RX_MIXER_GAIN_3 (0x00000040u) +#define GAIN_SETTING_3_RX_MIXER_GAIN_3_MASK (0x00000040u) +#define GAIN_SETTING_3_RX_MIXER_GAIN_3_BIT (6) +#define GAIN_SETTING_3_RX_MIXER_GAIN_3_BITS (1) +/* RX_FILTER_GAIN_3 field */ +#define GAIN_SETTING_3_RX_FILTER_GAIN_3 (0x00000030u) +#define GAIN_SETTING_3_RX_FILTER_GAIN_3_MASK (0x00000030u) +#define GAIN_SETTING_3_RX_FILTER_GAIN_3_BIT (4) +#define GAIN_SETTING_3_RX_FILTER_GAIN_3_BITS (2) +/* RX_IF_GAIN_3 field */ +#define GAIN_SETTING_3_RX_IF_GAIN_3 (0x0000000Fu) +#define GAIN_SETTING_3_RX_IF_GAIN_3_MASK (0x0000000Fu) +#define GAIN_SETTING_3_RX_IF_GAIN_3_BIT (0) +#define GAIN_SETTING_3_RX_IF_GAIN_3_BITS (4) #define GAIN_SETTING_4 *((volatile uint32_t *)0x40001084u) #define GAIN_SETTING_4_REG *((volatile uint32_t *)0x40001084u) #define GAIN_SETTING_4_ADDR (0x40001084u) #define GAIN_SETTING_4_RESET (0x00000032u) - /* RX_MIXER_GAIN_4 field */ - #define GAIN_SETTING_4_RX_MIXER_GAIN_4 (0x00000040u) - #define GAIN_SETTING_4_RX_MIXER_GAIN_4_MASK (0x00000040u) - #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BIT (6) - #define GAIN_SETTING_4_RX_MIXER_GAIN_4_BITS (1) - /* RX_FILTER_GAIN_4 field */ - #define GAIN_SETTING_4_RX_FILTER_GAIN_4 (0x00000030u) - #define GAIN_SETTING_4_RX_FILTER_GAIN_4_MASK (0x00000030u) - #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BIT (4) - #define GAIN_SETTING_4_RX_FILTER_GAIN_4_BITS (2) - /* RX_IF_GAIN_4 field */ - #define GAIN_SETTING_4_RX_IF_GAIN_4 (0x0000000Fu) - #define GAIN_SETTING_4_RX_IF_GAIN_4_MASK (0x0000000Fu) - #define GAIN_SETTING_4_RX_IF_GAIN_4_BIT (0) - #define GAIN_SETTING_4_RX_IF_GAIN_4_BITS (4) +/* RX_MIXER_GAIN_4 field */ +#define GAIN_SETTING_4_RX_MIXER_GAIN_4 (0x00000040u) +#define GAIN_SETTING_4_RX_MIXER_GAIN_4_MASK (0x00000040u) +#define GAIN_SETTING_4_RX_MIXER_GAIN_4_BIT (6) +#define GAIN_SETTING_4_RX_MIXER_GAIN_4_BITS (1) +/* RX_FILTER_GAIN_4 field */ +#define GAIN_SETTING_4_RX_FILTER_GAIN_4 (0x00000030u) +#define GAIN_SETTING_4_RX_FILTER_GAIN_4_MASK (0x00000030u) +#define GAIN_SETTING_4_RX_FILTER_GAIN_4_BIT (4) +#define GAIN_SETTING_4_RX_FILTER_GAIN_4_BITS (2) +/* RX_IF_GAIN_4 field */ +#define GAIN_SETTING_4_RX_IF_GAIN_4 (0x0000000Fu) +#define GAIN_SETTING_4_RX_IF_GAIN_4_MASK (0x0000000Fu) +#define GAIN_SETTING_4_RX_IF_GAIN_4_BIT (0) +#define GAIN_SETTING_4_RX_IF_GAIN_4_BITS (4) #define GAIN_SETTING_5 *((volatile uint32_t *)0x40001088u) #define GAIN_SETTING_5_REG *((volatile uint32_t *)0x40001088u) #define GAIN_SETTING_5_ADDR (0x40001088u) #define GAIN_SETTING_5_RESET (0x00000033u) - /* RX_MIXER_GAIN_5 field */ - #define GAIN_SETTING_5_RX_MIXER_GAIN_5 (0x00000040u) - #define GAIN_SETTING_5_RX_MIXER_GAIN_5_MASK (0x00000040u) - #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BIT (6) - #define GAIN_SETTING_5_RX_MIXER_GAIN_5_BITS (1) - /* RX_FILTER_GAIN_5 field */ - #define GAIN_SETTING_5_RX_FILTER_GAIN_5 (0x00000030u) - #define GAIN_SETTING_5_RX_FILTER_GAIN_5_MASK (0x00000030u) - #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BIT (4) - #define GAIN_SETTING_5_RX_FILTER_GAIN_5_BITS (2) - /* RX_IF_GAIN_5 field */ - #define GAIN_SETTING_5_RX_IF_GAIN_5 (0x0000000Fu) - #define GAIN_SETTING_5_RX_IF_GAIN_5_MASK (0x0000000Fu) - #define GAIN_SETTING_5_RX_IF_GAIN_5_BIT (0) - #define GAIN_SETTING_5_RX_IF_GAIN_5_BITS (4) +/* RX_MIXER_GAIN_5 field */ +#define GAIN_SETTING_5_RX_MIXER_GAIN_5 (0x00000040u) +#define GAIN_SETTING_5_RX_MIXER_GAIN_5_MASK (0x00000040u) +#define GAIN_SETTING_5_RX_MIXER_GAIN_5_BIT (6) +#define GAIN_SETTING_5_RX_MIXER_GAIN_5_BITS (1) +/* RX_FILTER_GAIN_5 field */ +#define GAIN_SETTING_5_RX_FILTER_GAIN_5 (0x00000030u) +#define GAIN_SETTING_5_RX_FILTER_GAIN_5_MASK (0x00000030u) +#define GAIN_SETTING_5_RX_FILTER_GAIN_5_BIT (4) +#define GAIN_SETTING_5_RX_FILTER_GAIN_5_BITS (2) +/* RX_IF_GAIN_5 field */ +#define GAIN_SETTING_5_RX_IF_GAIN_5 (0x0000000Fu) +#define GAIN_SETTING_5_RX_IF_GAIN_5_MASK (0x0000000Fu) +#define GAIN_SETTING_5_RX_IF_GAIN_5_BIT (0) +#define GAIN_SETTING_5_RX_IF_GAIN_5_BITS (4) #define GAIN_SETTING_6 *((volatile uint32_t *)0x4000108Cu) #define GAIN_SETTING_6_REG *((volatile uint32_t *)0x4000108Cu) #define GAIN_SETTING_6_ADDR (0x4000108Cu) #define GAIN_SETTING_6_RESET (0x00000034u) - /* RX_MIXER_GAIN_6 field */ - #define GAIN_SETTING_6_RX_MIXER_GAIN_6 (0x00000040u) - #define GAIN_SETTING_6_RX_MIXER_GAIN_6_MASK (0x00000040u) - #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BIT (6) - #define GAIN_SETTING_6_RX_MIXER_GAIN_6_BITS (1) - /* RX_FILTER_GAIN_6 field */ - #define GAIN_SETTING_6_RX_FILTER_GAIN_6 (0x00000030u) - #define GAIN_SETTING_6_RX_FILTER_GAIN_6_MASK (0x00000030u) - #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BIT (4) - #define GAIN_SETTING_6_RX_FILTER_GAIN_6_BITS (2) - /* RX_IF_GAIN_6 field */ - #define GAIN_SETTING_6_RX_IF_GAIN_6 (0x0000000Fu) - #define GAIN_SETTING_6_RX_IF_GAIN_6_MASK (0x0000000Fu) - #define GAIN_SETTING_6_RX_IF_GAIN_6_BIT (0) - #define GAIN_SETTING_6_RX_IF_GAIN_6_BITS (4) +/* RX_MIXER_GAIN_6 field */ +#define GAIN_SETTING_6_RX_MIXER_GAIN_6 (0x00000040u) +#define GAIN_SETTING_6_RX_MIXER_GAIN_6_MASK (0x00000040u) +#define GAIN_SETTING_6_RX_MIXER_GAIN_6_BIT (6) +#define GAIN_SETTING_6_RX_MIXER_GAIN_6_BITS (1) +/* RX_FILTER_GAIN_6 field */ +#define GAIN_SETTING_6_RX_FILTER_GAIN_6 (0x00000030u) +#define GAIN_SETTING_6_RX_FILTER_GAIN_6_MASK (0x00000030u) +#define GAIN_SETTING_6_RX_FILTER_GAIN_6_BIT (4) +#define GAIN_SETTING_6_RX_FILTER_GAIN_6_BITS (2) +/* RX_IF_GAIN_6 field */ +#define GAIN_SETTING_6_RX_IF_GAIN_6 (0x0000000Fu) +#define GAIN_SETTING_6_RX_IF_GAIN_6_MASK (0x0000000Fu) +#define GAIN_SETTING_6_RX_IF_GAIN_6_BIT (0) +#define GAIN_SETTING_6_RX_IF_GAIN_6_BITS (4) #define GAIN_SETTING_7 *((volatile uint32_t *)0x40001090u) #define GAIN_SETTING_7_REG *((volatile uint32_t *)0x40001090u) #define GAIN_SETTING_7_ADDR (0x40001090u) #define GAIN_SETTING_7_RESET (0x00000035u) - /* RX_MIXER_GAIN_7 field */ - #define GAIN_SETTING_7_RX_MIXER_GAIN_7 (0x00000040u) - #define GAIN_SETTING_7_RX_MIXER_GAIN_7_MASK (0x00000040u) - #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BIT (6) - #define GAIN_SETTING_7_RX_MIXER_GAIN_7_BITS (1) - /* RX_FILTER_GAIN_7 field */ - #define GAIN_SETTING_7_RX_FILTER_GAIN_7 (0x00000030u) - #define GAIN_SETTING_7_RX_FILTER_GAIN_7_MASK (0x00000030u) - #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BIT (4) - #define GAIN_SETTING_7_RX_FILTER_GAIN_7_BITS (2) - /* RX_IF_GAIN_7 field */ - #define GAIN_SETTING_7_RX_IF_GAIN_7 (0x0000000Fu) - #define GAIN_SETTING_7_RX_IF_GAIN_7_MASK (0x0000000Fu) - #define GAIN_SETTING_7_RX_IF_GAIN_7_BIT (0) - #define GAIN_SETTING_7_RX_IF_GAIN_7_BITS (4) +/* RX_MIXER_GAIN_7 field */ +#define GAIN_SETTING_7_RX_MIXER_GAIN_7 (0x00000040u) +#define GAIN_SETTING_7_RX_MIXER_GAIN_7_MASK (0x00000040u) +#define GAIN_SETTING_7_RX_MIXER_GAIN_7_BIT (6) +#define GAIN_SETTING_7_RX_MIXER_GAIN_7_BITS (1) +/* RX_FILTER_GAIN_7 field */ +#define GAIN_SETTING_7_RX_FILTER_GAIN_7 (0x00000030u) +#define GAIN_SETTING_7_RX_FILTER_GAIN_7_MASK (0x00000030u) +#define GAIN_SETTING_7_RX_FILTER_GAIN_7_BIT (4) +#define GAIN_SETTING_7_RX_FILTER_GAIN_7_BITS (2) +/* RX_IF_GAIN_7 field */ +#define GAIN_SETTING_7_RX_IF_GAIN_7 (0x0000000Fu) +#define GAIN_SETTING_7_RX_IF_GAIN_7_MASK (0x0000000Fu) +#define GAIN_SETTING_7_RX_IF_GAIN_7_BIT (0) +#define GAIN_SETTING_7_RX_IF_GAIN_7_BITS (4) #define GAIN_SETTING_8 *((volatile uint32_t *)0x40001094u) #define GAIN_SETTING_8_REG *((volatile uint32_t *)0x40001094u) #define GAIN_SETTING_8_ADDR (0x40001094u) #define GAIN_SETTING_8_RESET (0x00000036u) - /* RX_MIXER_GAIN_8 field */ - #define GAIN_SETTING_8_RX_MIXER_GAIN_8 (0x00000040u) - #define GAIN_SETTING_8_RX_MIXER_GAIN_8_MASK (0x00000040u) - #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BIT (6) - #define GAIN_SETTING_8_RX_MIXER_GAIN_8_BITS (1) - /* RX_FILTER_GAIN_8 field */ - #define GAIN_SETTING_8_RX_FILTER_GAIN_8 (0x00000030u) - #define GAIN_SETTING_8_RX_FILTER_GAIN_8_MASK (0x00000030u) - #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BIT (4) - #define GAIN_SETTING_8_RX_FILTER_GAIN_8_BITS (2) - /* RX_IF_GAIN_8 field */ - #define GAIN_SETTING_8_RX_IF_GAIN_8 (0x0000000Fu) - #define GAIN_SETTING_8_RX_IF_GAIN_8_MASK (0x0000000Fu) - #define GAIN_SETTING_8_RX_IF_GAIN_8_BIT (0) - #define GAIN_SETTING_8_RX_IF_GAIN_8_BITS (4) +/* RX_MIXER_GAIN_8 field */ +#define GAIN_SETTING_8_RX_MIXER_GAIN_8 (0x00000040u) +#define GAIN_SETTING_8_RX_MIXER_GAIN_8_MASK (0x00000040u) +#define GAIN_SETTING_8_RX_MIXER_GAIN_8_BIT (6) +#define GAIN_SETTING_8_RX_MIXER_GAIN_8_BITS (1) +/* RX_FILTER_GAIN_8 field */ +#define GAIN_SETTING_8_RX_FILTER_GAIN_8 (0x00000030u) +#define GAIN_SETTING_8_RX_FILTER_GAIN_8_MASK (0x00000030u) +#define GAIN_SETTING_8_RX_FILTER_GAIN_8_BIT (4) +#define GAIN_SETTING_8_RX_FILTER_GAIN_8_BITS (2) +/* RX_IF_GAIN_8 field */ +#define GAIN_SETTING_8_RX_IF_GAIN_8 (0x0000000Fu) +#define GAIN_SETTING_8_RX_IF_GAIN_8_MASK (0x0000000Fu) +#define GAIN_SETTING_8_RX_IF_GAIN_8_BIT (0) +#define GAIN_SETTING_8_RX_IF_GAIN_8_BITS (4) #define GAIN_SETTING_9 *((volatile uint32_t *)0x40001098u) #define GAIN_SETTING_9_REG *((volatile uint32_t *)0x40001098u) #define GAIN_SETTING_9_ADDR (0x40001098u) #define GAIN_SETTING_9_RESET (0x00000076u) - /* RX_MIXER_GAIN_9 field */ - #define GAIN_SETTING_9_RX_MIXER_GAIN_9 (0x00000040u) - #define GAIN_SETTING_9_RX_MIXER_GAIN_9_MASK (0x00000040u) - #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BIT (6) - #define GAIN_SETTING_9_RX_MIXER_GAIN_9_BITS (1) - /* RX_FILTER_GAIN_9 field */ - #define GAIN_SETTING_9_RX_FILTER_GAIN_9 (0x00000030u) - #define GAIN_SETTING_9_RX_FILTER_GAIN_9_MASK (0x00000030u) - #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BIT (4) - #define GAIN_SETTING_9_RX_FILTER_GAIN_9_BITS (2) - /* RX_IF_GAIN_9 field */ - #define GAIN_SETTING_9_RX_IF_GAIN_9 (0x0000000Fu) - #define GAIN_SETTING_9_RX_IF_GAIN_9_MASK (0x0000000Fu) - #define GAIN_SETTING_9_RX_IF_GAIN_9_BIT (0) - #define GAIN_SETTING_9_RX_IF_GAIN_9_BITS (4) +/* RX_MIXER_GAIN_9 field */ +#define GAIN_SETTING_9_RX_MIXER_GAIN_9 (0x00000040u) +#define GAIN_SETTING_9_RX_MIXER_GAIN_9_MASK (0x00000040u) +#define GAIN_SETTING_9_RX_MIXER_GAIN_9_BIT (6) +#define GAIN_SETTING_9_RX_MIXER_GAIN_9_BITS (1) +/* RX_FILTER_GAIN_9 field */ +#define GAIN_SETTING_9_RX_FILTER_GAIN_9 (0x00000030u) +#define GAIN_SETTING_9_RX_FILTER_GAIN_9_MASK (0x00000030u) +#define GAIN_SETTING_9_RX_FILTER_GAIN_9_BIT (4) +#define GAIN_SETTING_9_RX_FILTER_GAIN_9_BITS (2) +/* RX_IF_GAIN_9 field */ +#define GAIN_SETTING_9_RX_IF_GAIN_9 (0x0000000Fu) +#define GAIN_SETTING_9_RX_IF_GAIN_9_MASK (0x0000000Fu) +#define GAIN_SETTING_9_RX_IF_GAIN_9_BIT (0) +#define GAIN_SETTING_9_RX_IF_GAIN_9_BITS (4) #define GAIN_SETTING_10 *((volatile uint32_t *)0x4000109Cu) #define GAIN_SETTING_10_REG *((volatile uint32_t *)0x4000109Cu) #define GAIN_SETTING_10_ADDR (0x4000109Cu) #define GAIN_SETTING_10_RESET (0x00000077u) - /* RX_MIXER_GAIN_10 field */ - #define GAIN_SETTING_10_RX_MIXER_GAIN_10 (0x00000040u) - #define GAIN_SETTING_10_RX_MIXER_GAIN_10_MASK (0x00000040u) - #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BIT (6) - #define GAIN_SETTING_10_RX_MIXER_GAIN_10_BITS (1) - /* RX_FILTER_GAIN_10 field */ - #define GAIN_SETTING_10_RX_FILTER_GAIN_10 (0x00000030u) - #define GAIN_SETTING_10_RX_FILTER_GAIN_10_MASK (0x00000030u) - #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BIT (4) - #define GAIN_SETTING_10_RX_FILTER_GAIN_10_BITS (2) - /* RX_IF_GAIN_10 field */ - #define GAIN_SETTING_10_RX_IF_GAIN_10 (0x0000000Fu) - #define GAIN_SETTING_10_RX_IF_GAIN_10_MASK (0x0000000Fu) - #define GAIN_SETTING_10_RX_IF_GAIN_10_BIT (0) - #define GAIN_SETTING_10_RX_IF_GAIN_10_BITS (4) +/* RX_MIXER_GAIN_10 field */ +#define GAIN_SETTING_10_RX_MIXER_GAIN_10 (0x00000040u) +#define GAIN_SETTING_10_RX_MIXER_GAIN_10_MASK (0x00000040u) +#define GAIN_SETTING_10_RX_MIXER_GAIN_10_BIT (6) +#define GAIN_SETTING_10_RX_MIXER_GAIN_10_BITS (1) +/* RX_FILTER_GAIN_10 field */ +#define GAIN_SETTING_10_RX_FILTER_GAIN_10 (0x00000030u) +#define GAIN_SETTING_10_RX_FILTER_GAIN_10_MASK (0x00000030u) +#define GAIN_SETTING_10_RX_FILTER_GAIN_10_BIT (4) +#define GAIN_SETTING_10_RX_FILTER_GAIN_10_BITS (2) +/* RX_IF_GAIN_10 field */ +#define GAIN_SETTING_10_RX_IF_GAIN_10 (0x0000000Fu) +#define GAIN_SETTING_10_RX_IF_GAIN_10_MASK (0x0000000Fu) +#define GAIN_SETTING_10_RX_IF_GAIN_10_BIT (0) +#define GAIN_SETTING_10_RX_IF_GAIN_10_BITS (4) #define GAIN_SETTING_11 *((volatile uint32_t *)0x400010A0u) #define GAIN_SETTING_11_REG *((volatile uint32_t *)0x400010A0u) #define GAIN_SETTING_11_ADDR (0x400010A0u) #define GAIN_SETTING_11_RESET (0x00000078u) - /* RX_MIXER_GAIN_11 field */ - #define GAIN_SETTING_11_RX_MIXER_GAIN_11 (0x00000040u) - #define GAIN_SETTING_11_RX_MIXER_GAIN_11_MASK (0x00000040u) - #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BIT (6) - #define GAIN_SETTING_11_RX_MIXER_GAIN_11_BITS (1) - /* RX_FILTER_GAIN_11 field */ - #define GAIN_SETTING_11_RX_FILTER_GAIN_11 (0x00000030u) - #define GAIN_SETTING_11_RX_FILTER_GAIN_11_MASK (0x00000030u) - #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BIT (4) - #define GAIN_SETTING_11_RX_FILTER_GAIN_11_BITS (2) - /* RX_IF_GAIN_11 field */ - #define GAIN_SETTING_11_RX_IF_GAIN_11 (0x0000000Fu) - #define GAIN_SETTING_11_RX_IF_GAIN_11_MASK (0x0000000Fu) - #define GAIN_SETTING_11_RX_IF_GAIN_11_BIT (0) - #define GAIN_SETTING_11_RX_IF_GAIN_11_BITS (4) +/* RX_MIXER_GAIN_11 field */ +#define GAIN_SETTING_11_RX_MIXER_GAIN_11 (0x00000040u) +#define GAIN_SETTING_11_RX_MIXER_GAIN_11_MASK (0x00000040u) +#define GAIN_SETTING_11_RX_MIXER_GAIN_11_BIT (6) +#define GAIN_SETTING_11_RX_MIXER_GAIN_11_BITS (1) +/* RX_FILTER_GAIN_11 field */ +#define GAIN_SETTING_11_RX_FILTER_GAIN_11 (0x00000030u) +#define GAIN_SETTING_11_RX_FILTER_GAIN_11_MASK (0x00000030u) +#define GAIN_SETTING_11_RX_FILTER_GAIN_11_BIT (4) +#define GAIN_SETTING_11_RX_FILTER_GAIN_11_BITS (2) +/* RX_IF_GAIN_11 field */ +#define GAIN_SETTING_11_RX_IF_GAIN_11 (0x0000000Fu) +#define GAIN_SETTING_11_RX_IF_GAIN_11_MASK (0x0000000Fu) +#define GAIN_SETTING_11_RX_IF_GAIN_11_BIT (0) +#define GAIN_SETTING_11_RX_IF_GAIN_11_BITS (4) #define GAIN_CTRL_MIN_RF *((volatile uint32_t *)0x400010A4u) #define GAIN_CTRL_MIN_RF_REG *((volatile uint32_t *)0x400010A4u) #define GAIN_CTRL_MIN_RF_ADDR (0x400010A4u) #define GAIN_CTRL_MIN_RF_RESET (0x000000F0u) - /* GAIN_CTRL_MIN_RF field */ - #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF (0x000001FFu) - #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_MASK (0x000001FFu) - #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT (0) - #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS (9) +/* GAIN_CTRL_MIN_RF field */ +#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF (0x000001FFu) +#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_MASK (0x000001FFu) +#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT (0) +#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS (9) #define GAIN_CTRL_MAX_RF *((volatile uint32_t *)0x400010A8u) #define GAIN_CTRL_MAX_RF_REG *((volatile uint32_t *)0x400010A8u) #define GAIN_CTRL_MAX_RF_ADDR (0x400010A8u) #define GAIN_CTRL_MAX_RF_RESET (0x000000FCu) - /* GAIN_CTRL_MAX_RF field */ - #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF (0x000001FFu) - #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_MASK (0x000001FFu) - #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT (0) - #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS (9) +/* GAIN_CTRL_MAX_RF field */ +#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF (0x000001FFu) +#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_MASK (0x000001FFu) +#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT (0) +#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS (9) #define MIXER_GAIN_STEP *((volatile uint32_t *)0x400010ACu) #define MIXER_GAIN_STEP_REG *((volatile uint32_t *)0x400010ACu) #define MIXER_GAIN_STEP_ADDR (0x400010ACu) #define MIXER_GAIN_STEP_RESET (0x0000000Cu) - /* MIXER_GAIN_STEP field */ - #define MIXER_GAIN_STEP_MIXER_GAIN_STEP (0x0000000Fu) - #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_MASK (0x0000000Fu) - #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT (0) - #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS (4) +/* MIXER_GAIN_STEP field */ +#define MIXER_GAIN_STEP_MIXER_GAIN_STEP (0x0000000Fu) +#define MIXER_GAIN_STEP_MIXER_GAIN_STEP_MASK (0x0000000Fu) +#define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT (0) +#define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS (4) #define PREAMBLE_EVENT *((volatile uint32_t *)0x400010B0u) #define PREAMBLE_EVENT_REG *((volatile uint32_t *)0x400010B0u) #define PREAMBLE_EVENT_ADDR (0x400010B0u) #define PREAMBLE_EVENT_RESET (0x00005877u) - /* PREAMBLE_CONFIRM_THRESH field */ - #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH (0x0000FF00u) - #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_MASK (0x0000FF00u) - #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BIT (8) - #define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BITS (8) - /* PREAMBLE_EVENT_THRESH field */ - #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH (0x000000FFu) - #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_MASK (0x000000FFu) - #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT (0) - #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS (8) +/* PREAMBLE_CONFIRM_THRESH field */ +#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH (0x0000FF00u) +#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_MASK (0x0000FF00u) +#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BIT (8) +#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BITS (8) +/* PREAMBLE_EVENT_THRESH field */ +#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH (0x000000FFu) +#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_MASK (0x000000FFu) +#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT (0) +#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS (8) #define PREAMBLE_ABORT_THRESH *((volatile uint32_t *)0x400010B4u) #define PREAMBLE_ABORT_THRESH_REG *((volatile uint32_t *)0x400010B4u) #define PREAMBLE_ABORT_THRESH_ADDR (0x400010B4u) #define PREAMBLE_ABORT_THRESH_RESET (0x00000071u) - /* PREAMBLE_ABORT_THRESH field */ - #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH (0x000000FFu) - #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_MASK (0x000000FFu) - #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT (0) - #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS (8) +/* PREAMBLE_ABORT_THRESH field */ +#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH (0x000000FFu) +#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_MASK (0x000000FFu) +#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT (0) +#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS (8) #define PREAMBLE_ACCEPT_WINDOW *((volatile uint32_t *)0x400010B8u) #define PREAMBLE_ACCEPT_WINDOW_REG *((volatile uint32_t *)0x400010B8u) #define PREAMBLE_ACCEPT_WINDOW_ADDR (0x400010B8u) #define PREAMBLE_ACCEPT_WINDOW_RESET (0x00000003u) - /* PREAMBLE_ACCEPT_WINDOW field */ - #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW (0x0000007Fu) - #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_MASK (0x0000007Fu) - #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT (0) - #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS (7) +/* PREAMBLE_ACCEPT_WINDOW field */ +#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW (0x0000007Fu) +#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_MASK (0x0000007Fu) +#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT (0) +#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS (7) #define CCA_MODE *((volatile uint32_t *)0x400010BCu) #define CCA_MODE_REG *((volatile uint32_t *)0x400010BCu) #define CCA_MODE_ADDR (0x400010BCu) #define CCA_MODE_RESET (0x00000000u) - /* CCA_MODE field */ - #define CCA_MODE_CCA_MODE (0x00000003u) - #define CCA_MODE_CCA_MODE_MASK (0x00000003u) - #define CCA_MODE_CCA_MODE_BIT (0) - #define CCA_MODE_CCA_MODE_BITS (2) +/* CCA_MODE field */ +#define CCA_MODE_CCA_MODE (0x00000003u) +#define CCA_MODE_CCA_MODE_MASK (0x00000003u) +#define CCA_MODE_CCA_MODE_BIT (0) +#define CCA_MODE_CCA_MODE_BITS (2) #define TX_POWER_MAX *((volatile uint32_t *)0x400010C0u) #define TX_POWER_MAX_REG *((volatile uint32_t *)0x400010C0u) #define TX_POWER_MAX_ADDR (0x400010C0u) #define TX_POWER_MAX_RESET (0x00000000u) - /* MANUAL_POWER field */ - #define TX_POWER_MAX_MANUAL_POWER (0x00008000u) - #define TX_POWER_MAX_MANUAL_POWER_MASK (0x00008000u) - #define TX_POWER_MAX_MANUAL_POWER_BIT (15) - #define TX_POWER_MAX_MANUAL_POWER_BITS (1) - /* TX_POWER_MAX field */ - #define TX_POWER_MAX_TX_POWER_MAX (0x0000001Fu) - #define TX_POWER_MAX_TX_POWER_MAX_MASK (0x0000001Fu) - #define TX_POWER_MAX_TX_POWER_MAX_BIT (0) - #define TX_POWER_MAX_TX_POWER_MAX_BITS (5) +/* MANUAL_POWER field */ +#define TX_POWER_MAX_MANUAL_POWER (0x00008000u) +#define TX_POWER_MAX_MANUAL_POWER_MASK (0x00008000u) +#define TX_POWER_MAX_MANUAL_POWER_BIT (15) +#define TX_POWER_MAX_MANUAL_POWER_BITS (1) +/* TX_POWER_MAX field */ +#define TX_POWER_MAX_TX_POWER_MAX (0x0000001Fu) +#define TX_POWER_MAX_TX_POWER_MAX_MASK (0x0000001Fu) +#define TX_POWER_MAX_TX_POWER_MAX_BIT (0) +#define TX_POWER_MAX_TX_POWER_MAX_BITS (5) #define SYNTH_FREQ_H *((volatile uint32_t *)0x400010C4u) #define SYNTH_FREQ_H_REG *((volatile uint32_t *)0x400010C4u) #define SYNTH_FREQ_H_ADDR (0x400010C4u) #define SYNTH_FREQ_H_RESET (0x00000003u) - /* SYNTH_FREQ_H field */ - #define SYNTH_FREQ_H_SYNTH_FREQ_H (0x00000003u) - #define SYNTH_FREQ_H_SYNTH_FREQ_H_MASK (0x00000003u) - #define SYNTH_FREQ_H_SYNTH_FREQ_H_BIT (0) - #define SYNTH_FREQ_H_SYNTH_FREQ_H_BITS (2) +/* SYNTH_FREQ_H field */ +#define SYNTH_FREQ_H_SYNTH_FREQ_H (0x00000003u) +#define SYNTH_FREQ_H_SYNTH_FREQ_H_MASK (0x00000003u) +#define SYNTH_FREQ_H_SYNTH_FREQ_H_BIT (0) +#define SYNTH_FREQ_H_SYNTH_FREQ_H_BITS (2) #define SYNTH_FREQ_L *((volatile uint32_t *)0x400010C8u) #define SYNTH_FREQ_L_REG *((volatile uint32_t *)0x400010C8u) #define SYNTH_FREQ_L_ADDR (0x400010C8u) #define SYNTH_FREQ_L_RESET (0x00003800u) - /* SYNTH_FREQ_L field */ - #define SYNTH_FREQ_L_SYNTH_FREQ_L (0x0000FFFFu) - #define SYNTH_FREQ_L_SYNTH_FREQ_L_MASK (0x0000FFFFu) - #define SYNTH_FREQ_L_SYNTH_FREQ_L_BIT (0) - #define SYNTH_FREQ_L_SYNTH_FREQ_L_BITS (16) +/* SYNTH_FREQ_L field */ +#define SYNTH_FREQ_L_SYNTH_FREQ_L (0x0000FFFFu) +#define SYNTH_FREQ_L_SYNTH_FREQ_L_MASK (0x0000FFFFu) +#define SYNTH_FREQ_L_SYNTH_FREQ_L_BIT (0) +#define SYNTH_FREQ_L_SYNTH_FREQ_L_BITS (16) #define RSSI_INST *((volatile uint32_t *)0x400010CCu) #define RSSI_INST_REG *((volatile uint32_t *)0x400010CCu) #define RSSI_INST_ADDR (0x400010CCu) #define RSSI_INST_RESET (0x00000000u) - /* NEW_RSSI_INST field */ - #define RSSI_INST_NEW_RSSI_INST (0x00000200u) - #define RSSI_INST_NEW_RSSI_INST_MASK (0x00000200u) - #define RSSI_INST_NEW_RSSI_INST_BIT (9) - #define RSSI_INST_NEW_RSSI_INST_BITS (1) - /* RSSI_INST field */ - #define RSSI_INST_RSSI_INST (0x000001FFu) - #define RSSI_INST_RSSI_INST_MASK (0x000001FFu) - #define RSSI_INST_RSSI_INST_BIT (0) - #define RSSI_INST_RSSI_INST_BITS (9) +/* NEW_RSSI_INST field */ +#define RSSI_INST_NEW_RSSI_INST (0x00000200u) +#define RSSI_INST_NEW_RSSI_INST_MASK (0x00000200u) +#define RSSI_INST_NEW_RSSI_INST_BIT (9) +#define RSSI_INST_NEW_RSSI_INST_BITS (1) +/* RSSI_INST field */ +#define RSSI_INST_RSSI_INST (0x000001FFu) +#define RSSI_INST_RSSI_INST_MASK (0x000001FFu) +#define RSSI_INST_RSSI_INST_BIT (0) +#define RSSI_INST_RSSI_INST_BITS (9) #define FREQ_MEAS_CTRL1 *((volatile uint32_t *)0x400010D0u) #define FREQ_MEAS_CTRL1_REG *((volatile uint32_t *)0x400010D0u) #define FREQ_MEAS_CTRL1_ADDR (0x400010D0u) #define FREQ_MEAS_CTRL1_RESET (0x00000160u) - /* AUTO_TUNE_EN field */ - #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN (0x00008000u) - #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_MASK (0x00008000u) - #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BIT (15) - #define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BITS (1) - /* FREQ_MEAS_EN field */ - #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN (0x00004000u) - #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_MASK (0x00004000u) - #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BIT (14) - #define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BITS (1) - /* OPEN_LOOP_MANUAL field */ - #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL (0x00002000u) - #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_MASK (0x00002000u) - #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BIT (13) - #define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BITS (1) - /* OPEN_LOOP field */ - #define FREQ_MEAS_CTRL1_OPEN_LOOP (0x00001000u) - #define FREQ_MEAS_CTRL1_OPEN_LOOP_MASK (0x00001000u) - #define FREQ_MEAS_CTRL1_OPEN_LOOP_BIT (12) - #define FREQ_MEAS_CTRL1_OPEN_LOOP_BITS (1) - /* DELAY_FIRST_MEAS field */ - #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS (0x00000400u) - #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_MASK (0x00000400u) - #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BIT (10) - #define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BITS (1) - /* DELAY_ALL_MEAS field */ - #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS (0x00000200u) - #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_MASK (0x00000200u) - #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BIT (9) - #define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BITS (1) - /* BIN_SEARCH_MSB field */ - #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB (0x000001C0u) - #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_MASK (0x000001C0u) - #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BIT (6) - #define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BITS (3) - /* TUNE_VCO_INIT field */ - #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT (0x0000003Fu) - #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_MASK (0x0000003Fu) - #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT (0) - #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS (6) +/* AUTO_TUNE_EN field */ +#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN (0x00008000u) +#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_MASK (0x00008000u) +#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BIT (15) +#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BITS (1) +/* FREQ_MEAS_EN field */ +#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN (0x00004000u) +#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_MASK (0x00004000u) +#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BIT (14) +#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BITS (1) +/* OPEN_LOOP_MANUAL field */ +#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL (0x00002000u) +#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_MASK (0x00002000u) +#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BIT (13) +#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BITS (1) +/* OPEN_LOOP field */ +#define FREQ_MEAS_CTRL1_OPEN_LOOP (0x00001000u) +#define FREQ_MEAS_CTRL1_OPEN_LOOP_MASK (0x00001000u) +#define FREQ_MEAS_CTRL1_OPEN_LOOP_BIT (12) +#define FREQ_MEAS_CTRL1_OPEN_LOOP_BITS (1) +/* DELAY_FIRST_MEAS field */ +#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS (0x00000400u) +#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_MASK (0x00000400u) +#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BIT (10) +#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BITS (1) +/* DELAY_ALL_MEAS field */ +#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS (0x00000200u) +#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_MASK (0x00000200u) +#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BIT (9) +#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BITS (1) +/* BIN_SEARCH_MSB field */ +#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB (0x000001C0u) +#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_MASK (0x000001C0u) +#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BIT (6) +#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BITS (3) +/* TUNE_VCO_INIT field */ +#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT (0x0000003Fu) +#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_MASK (0x0000003Fu) +#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT (0) +#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS (6) #define FREQ_MEAS_CTRL2 *((volatile uint32_t *)0x400010D4u) #define FREQ_MEAS_CTRL2_REG *((volatile uint32_t *)0x400010D4u) #define FREQ_MEAS_CTRL2_ADDR (0x400010D4u) #define FREQ_MEAS_CTRL2_RESET (0x0000201Eu) - /* FREQ_MEAS_TIMER field */ - #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER (0x0000FF00u) - #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_MASK (0x0000FF00u) - #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BIT (8) - #define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BITS (8) - /* TARGET_PERIOD field */ - #define FREQ_MEAS_CTRL2_TARGET_PERIOD (0x000000FFu) - #define FREQ_MEAS_CTRL2_TARGET_PERIOD_MASK (0x000000FFu) - #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT (0) - #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS (8) +/* FREQ_MEAS_TIMER field */ +#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER (0x0000FF00u) +#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_MASK (0x0000FF00u) +#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BIT (8) +#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BITS (8) +/* TARGET_PERIOD field */ +#define FREQ_MEAS_CTRL2_TARGET_PERIOD (0x000000FFu) +#define FREQ_MEAS_CTRL2_TARGET_PERIOD_MASK (0x000000FFu) +#define FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT (0) +#define FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS (8) #define FREQ_MEAS_SHIFT *((volatile uint32_t *)0x400010D8u) #define FREQ_MEAS_SHIFT_REG *((volatile uint32_t *)0x400010D8u) #define FREQ_MEAS_SHIFT_ADDR (0x400010D8u) #define FREQ_MEAS_SHIFT_RESET (0x00000035u) - /* FREQ_MEAS_SHIFT field */ - #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT (0x000000FFu) - #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_MASK (0x000000FFu) - #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT (0) - #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS (8) +/* FREQ_MEAS_SHIFT field */ +#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT (0x000000FFu) +#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_MASK (0x000000FFu) +#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT (0) +#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS (8) #define FREQ_MEAS_STATUS1 *((volatile uint32_t *)0x400010DCu) #define FREQ_MEAS_STATUS1_REG *((volatile uint32_t *)0x400010DCu) #define FREQ_MEAS_STATUS1_ADDR (0x400010DCu) #define FREQ_MEAS_STATUS1_RESET (0x00000000u) - /* INVALID_EDGE field */ - #define FREQ_MEAS_STATUS1_INVALID_EDGE (0x00008000u) - #define FREQ_MEAS_STATUS1_INVALID_EDGE_MASK (0x00008000u) - #define FREQ_MEAS_STATUS1_INVALID_EDGE_BIT (15) - #define FREQ_MEAS_STATUS1_INVALID_EDGE_BITS (1) - /* SIGN_FOUND field */ - #define FREQ_MEAS_STATUS1_SIGN_FOUND (0x00004000u) - #define FREQ_MEAS_STATUS1_SIGN_FOUND_MASK (0x00004000u) - #define FREQ_MEAS_STATUS1_SIGN_FOUND_BIT (14) - #define FREQ_MEAS_STATUS1_SIGN_FOUND_BITS (1) - /* FREQ_SIGN field */ - #define FREQ_MEAS_STATUS1_FREQ_SIGN (0x00002000u) - #define FREQ_MEAS_STATUS1_FREQ_SIGN_MASK (0x00002000u) - #define FREQ_MEAS_STATUS1_FREQ_SIGN_BIT (13) - #define FREQ_MEAS_STATUS1_FREQ_SIGN_BITS (1) - /* PERIOD_FOUND field */ - #define FREQ_MEAS_STATUS1_PERIOD_FOUND (0x00001000u) - #define FREQ_MEAS_STATUS1_PERIOD_FOUND_MASK (0x00001000u) - #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BIT (12) - #define FREQ_MEAS_STATUS1_PERIOD_FOUND_BITS (1) - /* NEAREST_DIFF field */ - #define FREQ_MEAS_STATUS1_NEAREST_DIFF (0x000003FFu) - #define FREQ_MEAS_STATUS1_NEAREST_DIFF_MASK (0x000003FFu) - #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT (0) - #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS (10) +/* INVALID_EDGE field */ +#define FREQ_MEAS_STATUS1_INVALID_EDGE (0x00008000u) +#define FREQ_MEAS_STATUS1_INVALID_EDGE_MASK (0x00008000u) +#define FREQ_MEAS_STATUS1_INVALID_EDGE_BIT (15) +#define FREQ_MEAS_STATUS1_INVALID_EDGE_BITS (1) +/* SIGN_FOUND field */ +#define FREQ_MEAS_STATUS1_SIGN_FOUND (0x00004000u) +#define FREQ_MEAS_STATUS1_SIGN_FOUND_MASK (0x00004000u) +#define FREQ_MEAS_STATUS1_SIGN_FOUND_BIT (14) +#define FREQ_MEAS_STATUS1_SIGN_FOUND_BITS (1) +/* FREQ_SIGN field */ +#define FREQ_MEAS_STATUS1_FREQ_SIGN (0x00002000u) +#define FREQ_MEAS_STATUS1_FREQ_SIGN_MASK (0x00002000u) +#define FREQ_MEAS_STATUS1_FREQ_SIGN_BIT (13) +#define FREQ_MEAS_STATUS1_FREQ_SIGN_BITS (1) +/* PERIOD_FOUND field */ +#define FREQ_MEAS_STATUS1_PERIOD_FOUND (0x00001000u) +#define FREQ_MEAS_STATUS1_PERIOD_FOUND_MASK (0x00001000u) +#define FREQ_MEAS_STATUS1_PERIOD_FOUND_BIT (12) +#define FREQ_MEAS_STATUS1_PERIOD_FOUND_BITS (1) +/* NEAREST_DIFF field */ +#define FREQ_MEAS_STATUS1_NEAREST_DIFF (0x000003FFu) +#define FREQ_MEAS_STATUS1_NEAREST_DIFF_MASK (0x000003FFu) +#define FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT (0) +#define FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS (10) #define FREQ_MEAS_STATUS2 *((volatile uint32_t *)0x400010E0u) #define FREQ_MEAS_STATUS2_REG *((volatile uint32_t *)0x400010E0u) #define FREQ_MEAS_STATUS2_ADDR (0x400010E0u) #define FREQ_MEAS_STATUS2_RESET (0x00000000u) - /* BEAT_TIMER field */ - #define FREQ_MEAS_STATUS2_BEAT_TIMER (0x0000FFC0u) - #define FREQ_MEAS_STATUS2_BEAT_TIMER_MASK (0x0000FFC0u) - #define FREQ_MEAS_STATUS2_BEAT_TIMER_BIT (6) - #define FREQ_MEAS_STATUS2_BEAT_TIMER_BITS (10) - /* BEATS field */ - #define FREQ_MEAS_STATUS2_BEATS (0x0000003Fu) - #define FREQ_MEAS_STATUS2_BEATS_MASK (0x0000003Fu) - #define FREQ_MEAS_STATUS2_BEATS_BIT (0) - #define FREQ_MEAS_STATUS2_BEATS_BITS (6) +/* BEAT_TIMER field */ +#define FREQ_MEAS_STATUS2_BEAT_TIMER (0x0000FFC0u) +#define FREQ_MEAS_STATUS2_BEAT_TIMER_MASK (0x0000FFC0u) +#define FREQ_MEAS_STATUS2_BEAT_TIMER_BIT (6) +#define FREQ_MEAS_STATUS2_BEAT_TIMER_BITS (10) +/* BEATS field */ +#define FREQ_MEAS_STATUS2_BEATS (0x0000003Fu) +#define FREQ_MEAS_STATUS2_BEATS_MASK (0x0000003Fu) +#define FREQ_MEAS_STATUS2_BEATS_BIT (0) +#define FREQ_MEAS_STATUS2_BEATS_BITS (6) #define FREQ_MEAS_STATUS3 *((volatile uint32_t *)0x400010E4u) #define FREQ_MEAS_STATUS3_REG *((volatile uint32_t *)0x400010E4u) #define FREQ_MEAS_STATUS3_ADDR (0x400010E4u) #define FREQ_MEAS_STATUS3_RESET (0x00000020u) - /* TUNE_VCO field */ - #define FREQ_MEAS_STATUS3_TUNE_VCO (0x0000003Fu) - #define FREQ_MEAS_STATUS3_TUNE_VCO_MASK (0x0000003Fu) - #define FREQ_MEAS_STATUS3_TUNE_VCO_BIT (0) - #define FREQ_MEAS_STATUS3_TUNE_VCO_BITS (6) +/* TUNE_VCO field */ +#define FREQ_MEAS_STATUS3_TUNE_VCO (0x0000003Fu) +#define FREQ_MEAS_STATUS3_TUNE_VCO_MASK (0x0000003Fu) +#define FREQ_MEAS_STATUS3_TUNE_VCO_BIT (0) +#define FREQ_MEAS_STATUS3_TUNE_VCO_BITS (6) #define SCR_CTRL *((volatile uint32_t *)0x400010E8u) #define SCR_CTRL_REG *((volatile uint32_t *)0x400010E8u) #define SCR_CTRL_ADDR (0x400010E8u) #define SCR_CTRL_RESET (0x00000004u) - /* SCR_RESET field */ - #define SCR_CTRL_SCR_RESET (0x00000004u) - #define SCR_CTRL_SCR_RESET_MASK (0x00000004u) - #define SCR_CTRL_SCR_RESET_BIT (2) - #define SCR_CTRL_SCR_RESET_BITS (1) - /* SCR_WRITE field */ - #define SCR_CTRL_SCR_WRITE (0x00000002u) - #define SCR_CTRL_SCR_WRITE_MASK (0x00000002u) - #define SCR_CTRL_SCR_WRITE_BIT (1) - #define SCR_CTRL_SCR_WRITE_BITS (1) - /* SCR_READ field */ - #define SCR_CTRL_SCR_READ (0x00000001u) - #define SCR_CTRL_SCR_READ_MASK (0x00000001u) - #define SCR_CTRL_SCR_READ_BIT (0) - #define SCR_CTRL_SCR_READ_BITS (1) +/* SCR_RESET field */ +#define SCR_CTRL_SCR_RESET (0x00000004u) +#define SCR_CTRL_SCR_RESET_MASK (0x00000004u) +#define SCR_CTRL_SCR_RESET_BIT (2) +#define SCR_CTRL_SCR_RESET_BITS (1) +/* SCR_WRITE field */ +#define SCR_CTRL_SCR_WRITE (0x00000002u) +#define SCR_CTRL_SCR_WRITE_MASK (0x00000002u) +#define SCR_CTRL_SCR_WRITE_BIT (1) +#define SCR_CTRL_SCR_WRITE_BITS (1) +/* SCR_READ field */ +#define SCR_CTRL_SCR_READ (0x00000001u) +#define SCR_CTRL_SCR_READ_MASK (0x00000001u) +#define SCR_CTRL_SCR_READ_BIT (0) +#define SCR_CTRL_SCR_READ_BITS (1) #define SCR_BUSY *((volatile uint32_t *)0x400010ECu) #define SCR_BUSY_REG *((volatile uint32_t *)0x400010ECu) #define SCR_BUSY_ADDR (0x400010ECu) #define SCR_BUSY_RESET (0x00000000u) - /* SCR_BUSY field */ - #define SCR_BUSY_SCR_BUSY (0x00000001u) - #define SCR_BUSY_SCR_BUSY_MASK (0x00000001u) - #define SCR_BUSY_SCR_BUSY_BIT (0) - #define SCR_BUSY_SCR_BUSY_BITS (1) +/* SCR_BUSY field */ +#define SCR_BUSY_SCR_BUSY (0x00000001u) +#define SCR_BUSY_SCR_BUSY_MASK (0x00000001u) +#define SCR_BUSY_SCR_BUSY_BIT (0) +#define SCR_BUSY_SCR_BUSY_BITS (1) #define SCR_ADDR *((volatile uint32_t *)0x400010F0u) #define SCR_ADDR_REG *((volatile uint32_t *)0x400010F0u) #define SCR_ADDR_ADDR (0x400010F0u) #define SCR_ADDR_RESET (0x00000000u) - /* SCR_ADDR field */ - #define SCR_ADDR_SCR_ADDR (0x000000FFu) - #define SCR_ADDR_SCR_ADDR_MASK (0x000000FFu) - #define SCR_ADDR_SCR_ADDR_BIT (0) - #define SCR_ADDR_SCR_ADDR_BITS (8) +/* SCR_ADDR field */ +#define SCR_ADDR_SCR_ADDR (0x000000FFu) +#define SCR_ADDR_SCR_ADDR_MASK (0x000000FFu) +#define SCR_ADDR_SCR_ADDR_BIT (0) +#define SCR_ADDR_SCR_ADDR_BITS (8) #define SCR_WRITE *((volatile uint32_t *)0x400010F4u) #define SCR_WRITE_REG *((volatile uint32_t *)0x400010F4u) #define SCR_WRITE_ADDR (0x400010F4u) #define SCR_WRITE_RESET (0x00000000u) - /* SCR_WRITE field */ - #define SCR_WRITE_SCR_WRITE (0x0000FFFFu) - #define SCR_WRITE_SCR_WRITE_MASK (0x0000FFFFu) - #define SCR_WRITE_SCR_WRITE_BIT (0) - #define SCR_WRITE_SCR_WRITE_BITS (16) +/* SCR_WRITE field */ +#define SCR_WRITE_SCR_WRITE (0x0000FFFFu) +#define SCR_WRITE_SCR_WRITE_MASK (0x0000FFFFu) +#define SCR_WRITE_SCR_WRITE_BIT (0) +#define SCR_WRITE_SCR_WRITE_BITS (16) #define SCR_READ *((volatile uint32_t *)0x400010F8u) #define SCR_READ_REG *((volatile uint32_t *)0x400010F8u) #define SCR_READ_ADDR (0x400010F8u) #define SCR_READ_RESET (0x00000000u) - /* SCR_READ field */ - #define SCR_READ_SCR_READ (0x0000FFFFu) - #define SCR_READ_SCR_READ_MASK (0x0000FFFFu) - #define SCR_READ_SCR_READ_BIT (0) - #define SCR_READ_SCR_READ_BITS (16) +/* SCR_READ field */ +#define SCR_READ_SCR_READ (0x0000FFFFu) +#define SCR_READ_SCR_READ_MASK (0x0000FFFFu) +#define SCR_READ_SCR_READ_BIT (0) +#define SCR_READ_SCR_READ_BITS (16) #define SYNTH_LOCK *((volatile uint32_t *)0x400010FCu) #define SYNTH_LOCK_REG *((volatile uint32_t *)0x400010FCu) #define SYNTH_LOCK_ADDR (0x400010FCu) #define SYNTH_LOCK_RESET (0x00000000u) - /* IN_LOCK field */ - #define SYNTH_LOCK_IN_LOCK (0x00000001u) - #define SYNTH_LOCK_IN_LOCK_MASK (0x00000001u) - #define SYNTH_LOCK_IN_LOCK_BIT (0) - #define SYNTH_LOCK_IN_LOCK_BITS (1) +/* IN_LOCK field */ +#define SYNTH_LOCK_IN_LOCK (0x00000001u) +#define SYNTH_LOCK_IN_LOCK_MASK (0x00000001u) +#define SYNTH_LOCK_IN_LOCK_BIT (0) +#define SYNTH_LOCK_IN_LOCK_BITS (1) #define AN_CAL_STATUS *((volatile uint32_t *)0x40001100u) #define AN_CAL_STATUS_REG *((volatile uint32_t *)0x40001100u) #define AN_CAL_STATUS_ADDR (0x40001100u) #define AN_CAL_STATUS_RESET (0x00000000u) - /* VCO_CTRL field */ - #define AN_CAL_STATUS_VCO_CTRL (0x0000000Cu) - #define AN_CAL_STATUS_VCO_CTRL_MASK (0x0000000Cu) - #define AN_CAL_STATUS_VCO_CTRL_BIT (2) - #define AN_CAL_STATUS_VCO_CTRL_BITS (2) +/* VCO_CTRL field */ +#define AN_CAL_STATUS_VCO_CTRL (0x0000000Cu) +#define AN_CAL_STATUS_VCO_CTRL_MASK (0x0000000Cu) +#define AN_CAL_STATUS_VCO_CTRL_BIT (2) +#define AN_CAL_STATUS_VCO_CTRL_BITS (2) #define BIAS_CAL_STATUS *((volatile uint32_t *)0x40001104u) #define BIAS_CAL_STATUS_REG *((volatile uint32_t *)0x40001104u) #define BIAS_CAL_STATUS_ADDR (0x40001104u) #define BIAS_CAL_STATUS_RESET (0x00000000u) - /* VCOMP field */ - #define BIAS_CAL_STATUS_VCOMP (0x00000002u) - #define BIAS_CAL_STATUS_VCOMP_MASK (0x00000002u) - #define BIAS_CAL_STATUS_VCOMP_BIT (1) - #define BIAS_CAL_STATUS_VCOMP_BITS (1) - /* ICOMP field */ - #define BIAS_CAL_STATUS_ICOMP (0x00000001u) - #define BIAS_CAL_STATUS_ICOMP_MASK (0x00000001u) - #define BIAS_CAL_STATUS_ICOMP_BIT (0) - #define BIAS_CAL_STATUS_ICOMP_BITS (1) +/* VCOMP field */ +#define BIAS_CAL_STATUS_VCOMP (0x00000002u) +#define BIAS_CAL_STATUS_VCOMP_MASK (0x00000002u) +#define BIAS_CAL_STATUS_VCOMP_BIT (1) +#define BIAS_CAL_STATUS_VCOMP_BITS (1) +/* ICOMP field */ +#define BIAS_CAL_STATUS_ICOMP (0x00000001u) +#define BIAS_CAL_STATUS_ICOMP_MASK (0x00000001u) +#define BIAS_CAL_STATUS_ICOMP_BIT (0) +#define BIAS_CAL_STATUS_ICOMP_BITS (1) #define ATEST_SEL *((volatile uint32_t *)0x40001108u) #define ATEST_SEL_REG *((volatile uint32_t *)0x40001108u) #define ATEST_SEL_ADDR (0x40001108u) #define ATEST_SEL_RESET (0x00000000u) - /* ATEST_CTRL field */ - #define ATEST_SEL_ATEST_CTRL (0x0000FF00u) - #define ATEST_SEL_ATEST_CTRL_MASK (0x0000FF00u) - #define ATEST_SEL_ATEST_CTRL_BIT (8) - #define ATEST_SEL_ATEST_CTRL_BITS (8) - /* ATEST_SEL field */ - #define ATEST_SEL_ATEST_SEL (0x0000001Fu) - #define ATEST_SEL_ATEST_SEL_MASK (0x0000001Fu) - #define ATEST_SEL_ATEST_SEL_BIT (0) - #define ATEST_SEL_ATEST_SEL_BITS (5) +/* ATEST_CTRL field */ +#define ATEST_SEL_ATEST_CTRL (0x0000FF00u) +#define ATEST_SEL_ATEST_CTRL_MASK (0x0000FF00u) +#define ATEST_SEL_ATEST_CTRL_BIT (8) +#define ATEST_SEL_ATEST_CTRL_BITS (8) +/* ATEST_SEL field */ +#define ATEST_SEL_ATEST_SEL (0x0000001Fu) +#define ATEST_SEL_ATEST_SEL_MASK (0x0000001Fu) +#define ATEST_SEL_ATEST_SEL_BIT (0) +#define ATEST_SEL_ATEST_SEL_BITS (5) #define AN_EN_TEST *((volatile uint32_t *)0x4000110Cu) #define AN_EN_TEST_REG *((volatile uint32_t *)0x4000110Cu) #define AN_EN_TEST_ADDR (0x4000110Cu) #define AN_EN_TEST_RESET (0x00000000u) - /* AN_TEST_MODE field */ - #define AN_EN_TEST_AN_TEST_MODE (0x00008000u) - #define AN_EN_TEST_AN_TEST_MODE_MASK (0x00008000u) - #define AN_EN_TEST_AN_TEST_MODE_BIT (15) - #define AN_EN_TEST_AN_TEST_MODE_BITS (1) - /* PFD_EN field */ - #define AN_EN_TEST_PFD_EN (0x00004000u) - #define AN_EN_TEST_PFD_EN_MASK (0x00004000u) - #define AN_EN_TEST_PFD_EN_BIT (14) - #define AN_EN_TEST_PFD_EN_BITS (1) - /* ADC_EN field */ - #define AN_EN_TEST_ADC_EN (0x00002000u) - #define AN_EN_TEST_ADC_EN_MASK (0x00002000u) - #define AN_EN_TEST_ADC_EN_BIT (13) - #define AN_EN_TEST_ADC_EN_BITS (1) - /* UNUSED field */ - #define AN_EN_TEST_UNUSED (0x00001000u) - #define AN_EN_TEST_UNUSED_MASK (0x00001000u) - #define AN_EN_TEST_UNUSED_BIT (12) - #define AN_EN_TEST_UNUSED_BITS (1) - /* PRE_FILT_EN field */ - #define AN_EN_TEST_PRE_FILT_EN (0x00000800u) - #define AN_EN_TEST_PRE_FILT_EN_MASK (0x00000800u) - #define AN_EN_TEST_PRE_FILT_EN_BIT (11) - #define AN_EN_TEST_PRE_FILT_EN_BITS (1) - /* IF_AMP_EN field */ - #define AN_EN_TEST_IF_AMP_EN (0x00000400u) - #define AN_EN_TEST_IF_AMP_EN_MASK (0x00000400u) - #define AN_EN_TEST_IF_AMP_EN_BIT (10) - #define AN_EN_TEST_IF_AMP_EN_BITS (1) - /* LNA_EN field */ - #define AN_EN_TEST_LNA_EN (0x00000200u) - #define AN_EN_TEST_LNA_EN_MASK (0x00000200u) - #define AN_EN_TEST_LNA_EN_BIT (9) - #define AN_EN_TEST_LNA_EN_BITS (1) - /* MIXER_EN field */ - #define AN_EN_TEST_MIXER_EN (0x00000100u) - #define AN_EN_TEST_MIXER_EN_MASK (0x00000100u) - #define AN_EN_TEST_MIXER_EN_BIT (8) - #define AN_EN_TEST_MIXER_EN_BITS (1) - /* CH_FILT_EN field */ - #define AN_EN_TEST_CH_FILT_EN (0x00000080u) - #define AN_EN_TEST_CH_FILT_EN_MASK (0x00000080u) - #define AN_EN_TEST_CH_FILT_EN_BIT (7) - #define AN_EN_TEST_CH_FILT_EN_BITS (1) - /* MOD_DAC_EN field */ - #define AN_EN_TEST_MOD_DAC_EN (0x00000040u) - #define AN_EN_TEST_MOD_DAC_EN_MASK (0x00000040u) - #define AN_EN_TEST_MOD_DAC_EN_BIT (6) - #define AN_EN_TEST_MOD_DAC_EN_BITS (1) - /* PA_EN field */ - #define AN_EN_TEST_PA_EN (0x00000010u) - #define AN_EN_TEST_PA_EN_MASK (0x00000010u) - #define AN_EN_TEST_PA_EN_BIT (4) - #define AN_EN_TEST_PA_EN_BITS (1) - /* PRESCALER_EN field */ - #define AN_EN_TEST_PRESCALER_EN (0x00000008u) - #define AN_EN_TEST_PRESCALER_EN_MASK (0x00000008u) - #define AN_EN_TEST_PRESCALER_EN_BIT (3) - #define AN_EN_TEST_PRESCALER_EN_BITS (1) - /* VCO_EN field */ - #define AN_EN_TEST_VCO_EN (0x00000004u) - #define AN_EN_TEST_VCO_EN_MASK (0x00000004u) - #define AN_EN_TEST_VCO_EN_BIT (2) - #define AN_EN_TEST_VCO_EN_BITS (1) - /* BIAS_EN field */ - #define AN_EN_TEST_BIAS_EN (0x00000001u) - #define AN_EN_TEST_BIAS_EN_MASK (0x00000001u) - #define AN_EN_TEST_BIAS_EN_BIT (0) - #define AN_EN_TEST_BIAS_EN_BITS (1) +/* AN_TEST_MODE field */ +#define AN_EN_TEST_AN_TEST_MODE (0x00008000u) +#define AN_EN_TEST_AN_TEST_MODE_MASK (0x00008000u) +#define AN_EN_TEST_AN_TEST_MODE_BIT (15) +#define AN_EN_TEST_AN_TEST_MODE_BITS (1) +/* PFD_EN field */ +#define AN_EN_TEST_PFD_EN (0x00004000u) +#define AN_EN_TEST_PFD_EN_MASK (0x00004000u) +#define AN_EN_TEST_PFD_EN_BIT (14) +#define AN_EN_TEST_PFD_EN_BITS (1) +/* ADC_EN field */ +#define AN_EN_TEST_ADC_EN (0x00002000u) +#define AN_EN_TEST_ADC_EN_MASK (0x00002000u) +#define AN_EN_TEST_ADC_EN_BIT (13) +#define AN_EN_TEST_ADC_EN_BITS (1) +/* UNUSED field */ +#define AN_EN_TEST_UNUSED (0x00001000u) +#define AN_EN_TEST_UNUSED_MASK (0x00001000u) +#define AN_EN_TEST_UNUSED_BIT (12) +#define AN_EN_TEST_UNUSED_BITS (1) +/* PRE_FILT_EN field */ +#define AN_EN_TEST_PRE_FILT_EN (0x00000800u) +#define AN_EN_TEST_PRE_FILT_EN_MASK (0x00000800u) +#define AN_EN_TEST_PRE_FILT_EN_BIT (11) +#define AN_EN_TEST_PRE_FILT_EN_BITS (1) +/* IF_AMP_EN field */ +#define AN_EN_TEST_IF_AMP_EN (0x00000400u) +#define AN_EN_TEST_IF_AMP_EN_MASK (0x00000400u) +#define AN_EN_TEST_IF_AMP_EN_BIT (10) +#define AN_EN_TEST_IF_AMP_EN_BITS (1) +/* LNA_EN field */ +#define AN_EN_TEST_LNA_EN (0x00000200u) +#define AN_EN_TEST_LNA_EN_MASK (0x00000200u) +#define AN_EN_TEST_LNA_EN_BIT (9) +#define AN_EN_TEST_LNA_EN_BITS (1) +/* MIXER_EN field */ +#define AN_EN_TEST_MIXER_EN (0x00000100u) +#define AN_EN_TEST_MIXER_EN_MASK (0x00000100u) +#define AN_EN_TEST_MIXER_EN_BIT (8) +#define AN_EN_TEST_MIXER_EN_BITS (1) +/* CH_FILT_EN field */ +#define AN_EN_TEST_CH_FILT_EN (0x00000080u) +#define AN_EN_TEST_CH_FILT_EN_MASK (0x00000080u) +#define AN_EN_TEST_CH_FILT_EN_BIT (7) +#define AN_EN_TEST_CH_FILT_EN_BITS (1) +/* MOD_DAC_EN field */ +#define AN_EN_TEST_MOD_DAC_EN (0x00000040u) +#define AN_EN_TEST_MOD_DAC_EN_MASK (0x00000040u) +#define AN_EN_TEST_MOD_DAC_EN_BIT (6) +#define AN_EN_TEST_MOD_DAC_EN_BITS (1) +/* PA_EN field */ +#define AN_EN_TEST_PA_EN (0x00000010u) +#define AN_EN_TEST_PA_EN_MASK (0x00000010u) +#define AN_EN_TEST_PA_EN_BIT (4) +#define AN_EN_TEST_PA_EN_BITS (1) +/* PRESCALER_EN field */ +#define AN_EN_TEST_PRESCALER_EN (0x00000008u) +#define AN_EN_TEST_PRESCALER_EN_MASK (0x00000008u) +#define AN_EN_TEST_PRESCALER_EN_BIT (3) +#define AN_EN_TEST_PRESCALER_EN_BITS (1) +/* VCO_EN field */ +#define AN_EN_TEST_VCO_EN (0x00000004u) +#define AN_EN_TEST_VCO_EN_MASK (0x00000004u) +#define AN_EN_TEST_VCO_EN_BIT (2) +#define AN_EN_TEST_VCO_EN_BITS (1) +/* BIAS_EN field */ +#define AN_EN_TEST_BIAS_EN (0x00000001u) +#define AN_EN_TEST_BIAS_EN_MASK (0x00000001u) +#define AN_EN_TEST_BIAS_EN_BIT (0) +#define AN_EN_TEST_BIAS_EN_BITS (1) #define TUNE_FILTER_CTRL *((volatile uint32_t *)0x40001110u) #define TUNE_FILTER_CTRL_REG *((volatile uint32_t *)0x40001110u) #define TUNE_FILTER_CTRL_ADDR (0x40001110u) #define TUNE_FILTER_CTRL_RESET (0x00000000u) - /* TUNE_FILTER_EN field */ - #define TUNE_FILTER_CTRL_TUNE_FILTER_EN (0x00000002u) - #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_MASK (0x00000002u) - #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BIT (1) - #define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BITS (1) - /* TUNE_FILTER_RESET field */ - #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET (0x00000001u) - #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_MASK (0x00000001u) - #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT (0) - #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS (1) +/* TUNE_FILTER_EN field */ +#define TUNE_FILTER_CTRL_TUNE_FILTER_EN (0x00000002u) +#define TUNE_FILTER_CTRL_TUNE_FILTER_EN_MASK (0x00000002u) +#define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BIT (1) +#define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BITS (1) +/* TUNE_FILTER_RESET field */ +#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET (0x00000001u) +#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_MASK (0x00000001u) +#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT (0) +#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS (1) #define NOISE_EN *((volatile uint32_t *)0x40001114u) #define NOISE_EN_REG *((volatile uint32_t *)0x40001114u) #define NOISE_EN_ADDR (0x40001114u) #define NOISE_EN_RESET (0x00000000u) - /* NOISE_EN field */ - #define NOISE_EN_NOISE_EN (0x00000001u) - #define NOISE_EN_NOISE_EN_MASK (0x00000001u) - #define NOISE_EN_NOISE_EN_BIT (0) - #define NOISE_EN_NOISE_EN_BITS (1) +/* NOISE_EN field */ +#define NOISE_EN_NOISE_EN (0x00000001u) +#define NOISE_EN_NOISE_EN_MASK (0x00000001u) +#define NOISE_EN_NOISE_EN_BIT (0) +#define NOISE_EN_NOISE_EN_BITS (1) /* MAC block */ #define DATA_MAC_BASE (0x40002000u) @@ -1489,821 +1489,821 @@ #define MAC_RX_ST_ADDR_A_REG *((volatile uint32_t *)0x40002000u) #define MAC_RX_ST_ADDR_A_ADDR (0x40002000u) #define MAC_RX_ST_ADDR_A_RESET (0x20000000u) - /* MAC_RAM_OFFS field */ - #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) - #define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) - /* MAC_RX_ST_ADDR_A field */ - #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A (0x00001FFEu) - #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_MASK (0x00001FFEu) - #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT (1) - #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) +#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) +/* MAC_RX_ST_ADDR_A field */ +#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A (0x00001FFEu) +#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_MASK (0x00001FFEu) +#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT (1) +#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS (12) #define MAC_RX_END_ADDR_A *((volatile uint32_t *)0x40002004u) #define MAC_RX_END_ADDR_A_REG *((volatile uint32_t *)0x40002004u) #define MAC_RX_END_ADDR_A_ADDR (0x40002004u) #define MAC_RX_END_ADDR_A_RESET (0x20000088u) - /* MAC_RAM_OFFS field */ - #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) - #define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) - /* MAC_RX_END_ADDR_A field */ - #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A (0x00001FFEu) - #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_MASK (0x00001FFEu) - #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT (1) - #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) +#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) +/* MAC_RX_END_ADDR_A field */ +#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A (0x00001FFEu) +#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_MASK (0x00001FFEu) +#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT (1) +#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS (12) #define MAC_RX_ST_ADDR_B *((volatile uint32_t *)0x40002008u) #define MAC_RX_ST_ADDR_B_REG *((volatile uint32_t *)0x40002008u) #define MAC_RX_ST_ADDR_B_ADDR (0x40002008u) #define MAC_RX_ST_ADDR_B_RESET (0x20000000u) - /* MAC_RAM_OFFS field */ - #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) - #define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) - /* MAC_RX_ST_ADDR_B field */ - #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B (0x00001FFEu) - #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_MASK (0x00001FFEu) - #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT (1) - #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) +#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) +/* MAC_RX_ST_ADDR_B field */ +#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B (0x00001FFEu) +#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_MASK (0x00001FFEu) +#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT (1) +#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS (12) #define MAC_RX_END_ADDR_B *((volatile uint32_t *)0x4000200Cu) #define MAC_RX_END_ADDR_B_REG *((volatile uint32_t *)0x4000200Cu) #define MAC_RX_END_ADDR_B_ADDR (0x4000200Cu) #define MAC_RX_END_ADDR_B_RESET (0x20000088u) - /* MAC_RAM_OFFS field */ - #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) - #define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) - /* MAC_RX_END_ADDR_B field */ - #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B (0x00001FFEu) - #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_MASK (0x00001FFEu) - #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT (1) - #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) +#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) +/* MAC_RX_END_ADDR_B field */ +#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B (0x00001FFEu) +#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_MASK (0x00001FFEu) +#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT (1) +#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS (12) #define MAC_TX_ST_ADDR_A *((volatile uint32_t *)0x40002010u) #define MAC_TX_ST_ADDR_A_REG *((volatile uint32_t *)0x40002010u) #define MAC_TX_ST_ADDR_A_ADDR (0x40002010u) #define MAC_TX_ST_ADDR_A_RESET (0x20000000u) - /* MAC_RAM_OFFS field */ - #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) - #define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) - /* MAC_TX_ST_ADDR_A field */ - #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A (0x00001FFEu) - #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_MASK (0x00001FFEu) - #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT (1) - #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BIT (13) +#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BITS (19) +/* MAC_TX_ST_ADDR_A field */ +#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A (0x00001FFEu) +#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_MASK (0x00001FFEu) +#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT (1) +#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS (12) #define MAC_TX_END_ADDR_A *((volatile uint32_t *)0x40002014u) #define MAC_TX_END_ADDR_A_REG *((volatile uint32_t *)0x40002014u) #define MAC_TX_END_ADDR_A_ADDR (0x40002014u) #define MAC_TX_END_ADDR_A_RESET (0x20000000u) - /* MAC_RAM_OFFS field */ - #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) - #define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) - /* MAC_TX_END_ADDR_A field */ - #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A (0x00001FFEu) - #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_MASK (0x00001FFEu) - #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT (1) - #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BIT (13) +#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BITS (19) +/* MAC_TX_END_ADDR_A field */ +#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A (0x00001FFEu) +#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_MASK (0x00001FFEu) +#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT (1) +#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS (12) #define MAC_TX_ST_ADDR_B *((volatile uint32_t *)0x40002018u) #define MAC_TX_ST_ADDR_B_REG *((volatile uint32_t *)0x40002018u) #define MAC_TX_ST_ADDR_B_ADDR (0x40002018u) #define MAC_TX_ST_ADDR_B_RESET (0x20000000u) - /* MAC_RAM_OFFS field */ - #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) - #define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) - /* MAC_TX_ST_ADDR_B field */ - #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B (0x00001FFEu) - #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_MASK (0x00001FFEu) - #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT (1) - #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BIT (13) +#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BITS (19) +/* MAC_TX_ST_ADDR_B field */ +#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B (0x00001FFEu) +#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_MASK (0x00001FFEu) +#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT (1) +#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS (12) #define MAC_TX_END_ADDR_B *((volatile uint32_t *)0x4000201Cu) #define MAC_TX_END_ADDR_B_REG *((volatile uint32_t *)0x4000201Cu) #define MAC_TX_END_ADDR_B_ADDR (0x4000201Cu) #define MAC_TX_END_ADDR_B_RESET (0x20000000u) - /* MAC_RAM_OFFS field */ - #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) - #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) - #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) - #define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) - /* MAC_TX_END_ADDR_B field */ - #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B (0x00001FFEu) - #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_MASK (0x00001FFEu) - #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT (1) - #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS (12) +/* MAC_RAM_OFFS field */ +#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS (0xFFFFE000u) +#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_MASK (0xFFFFE000u) +#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BIT (13) +#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BITS (19) +/* MAC_TX_END_ADDR_B field */ +#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B (0x00001FFEu) +#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_MASK (0x00001FFEu) +#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT (1) +#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS (12) #define RX_A_COUNT *((volatile uint32_t *)0x40002020u) #define RX_A_COUNT_REG *((volatile uint32_t *)0x40002020u) #define RX_A_COUNT_ADDR (0x40002020u) #define RX_A_COUNT_RESET (0x00000000u) - /* RX_A_COUNT field */ - #define RX_A_COUNT_RX_A_COUNT (0x000007FFu) - #define RX_A_COUNT_RX_A_COUNT_MASK (0x000007FFu) - #define RX_A_COUNT_RX_A_COUNT_BIT (0) - #define RX_A_COUNT_RX_A_COUNT_BITS (11) +/* RX_A_COUNT field */ +#define RX_A_COUNT_RX_A_COUNT (0x000007FFu) +#define RX_A_COUNT_RX_A_COUNT_MASK (0x000007FFu) +#define RX_A_COUNT_RX_A_COUNT_BIT (0) +#define RX_A_COUNT_RX_A_COUNT_BITS (11) #define RX_B_COUNT *((volatile uint32_t *)0x40002024u) #define RX_B_COUNT_REG *((volatile uint32_t *)0x40002024u) #define RX_B_COUNT_ADDR (0x40002024u) #define RX_B_COUNT_RESET (0x00000000u) - /* RX_B_COUNT field */ - #define RX_B_COUNT_RX_B_COUNT (0x000007FFu) - #define RX_B_COUNT_RX_B_COUNT_MASK (0x000007FFu) - #define RX_B_COUNT_RX_B_COUNT_BIT (0) - #define RX_B_COUNT_RX_B_COUNT_BITS (11) +/* RX_B_COUNT field */ +#define RX_B_COUNT_RX_B_COUNT (0x000007FFu) +#define RX_B_COUNT_RX_B_COUNT_MASK (0x000007FFu) +#define RX_B_COUNT_RX_B_COUNT_BIT (0) +#define RX_B_COUNT_RX_B_COUNT_BITS (11) #define TX_COUNT *((volatile uint32_t *)0x40002028u) #define TX_COUNT_REG *((volatile uint32_t *)0x40002028u) #define TX_COUNT_ADDR (0x40002028u) #define TX_COUNT_RESET (0x00000000u) - /* TX_COUNT field */ - #define TX_COUNT_TX_COUNT (0x000007FFu) - #define TX_COUNT_TX_COUNT_MASK (0x000007FFu) - #define TX_COUNT_TX_COUNT_BIT (0) - #define TX_COUNT_TX_COUNT_BITS (11) +/* TX_COUNT field */ +#define TX_COUNT_TX_COUNT (0x000007FFu) +#define TX_COUNT_TX_COUNT_MASK (0x000007FFu) +#define TX_COUNT_TX_COUNT_BIT (0) +#define TX_COUNT_TX_COUNT_BITS (11) #define MAC_DMA_STATUS *((volatile uint32_t *)0x4000202Cu) #define MAC_DMA_STATUS_REG *((volatile uint32_t *)0x4000202Cu) #define MAC_DMA_STATUS_ADDR (0x4000202Cu) #define MAC_DMA_STATUS_RESET (0x00000000u) - /* TX_ACTIVE_B field */ - #define MAC_DMA_STATUS_TX_ACTIVE_B (0x00000008u) - #define MAC_DMA_STATUS_TX_ACTIVE_B_MASK (0x00000008u) - #define MAC_DMA_STATUS_TX_ACTIVE_B_BIT (3) - #define MAC_DMA_STATUS_TX_ACTIVE_B_BITS (1) - /* TX_ACTIVE_A field */ - #define MAC_DMA_STATUS_TX_ACTIVE_A (0x00000004u) - #define MAC_DMA_STATUS_TX_ACTIVE_A_MASK (0x00000004u) - #define MAC_DMA_STATUS_TX_ACTIVE_A_BIT (2) - #define MAC_DMA_STATUS_TX_ACTIVE_A_BITS (1) - /* RX_ACTIVE_B field */ - #define MAC_DMA_STATUS_RX_ACTIVE_B (0x00000002u) - #define MAC_DMA_STATUS_RX_ACTIVE_B_MASK (0x00000002u) - #define MAC_DMA_STATUS_RX_ACTIVE_B_BIT (1) - #define MAC_DMA_STATUS_RX_ACTIVE_B_BITS (1) - /* RX_ACTIVE_A field */ - #define MAC_DMA_STATUS_RX_ACTIVE_A (0x00000001u) - #define MAC_DMA_STATUS_RX_ACTIVE_A_MASK (0x00000001u) - #define MAC_DMA_STATUS_RX_ACTIVE_A_BIT (0) - #define MAC_DMA_STATUS_RX_ACTIVE_A_BITS (1) +/* TX_ACTIVE_B field */ +#define MAC_DMA_STATUS_TX_ACTIVE_B (0x00000008u) +#define MAC_DMA_STATUS_TX_ACTIVE_B_MASK (0x00000008u) +#define MAC_DMA_STATUS_TX_ACTIVE_B_BIT (3) +#define MAC_DMA_STATUS_TX_ACTIVE_B_BITS (1) +/* TX_ACTIVE_A field */ +#define MAC_DMA_STATUS_TX_ACTIVE_A (0x00000004u) +#define MAC_DMA_STATUS_TX_ACTIVE_A_MASK (0x00000004u) +#define MAC_DMA_STATUS_TX_ACTIVE_A_BIT (2) +#define MAC_DMA_STATUS_TX_ACTIVE_A_BITS (1) +/* RX_ACTIVE_B field */ +#define MAC_DMA_STATUS_RX_ACTIVE_B (0x00000002u) +#define MAC_DMA_STATUS_RX_ACTIVE_B_MASK (0x00000002u) +#define MAC_DMA_STATUS_RX_ACTIVE_B_BIT (1) +#define MAC_DMA_STATUS_RX_ACTIVE_B_BITS (1) +/* RX_ACTIVE_A field */ +#define MAC_DMA_STATUS_RX_ACTIVE_A (0x00000001u) +#define MAC_DMA_STATUS_RX_ACTIVE_A_MASK (0x00000001u) +#define MAC_DMA_STATUS_RX_ACTIVE_A_BIT (0) +#define MAC_DMA_STATUS_RX_ACTIVE_A_BITS (1) #define MAC_DMA_CONFIG *((volatile uint32_t *)0x40002030u) #define MAC_DMA_CONFIG_REG *((volatile uint32_t *)0x40002030u) #define MAC_DMA_CONFIG_ADDR (0x40002030u) #define MAC_DMA_CONFIG_RESET (0x00000000u) - /* TX_DMA_RESET field */ - #define MAC_DMA_CONFIG_TX_DMA_RESET (0x00000020u) - #define MAC_DMA_CONFIG_TX_DMA_RESET_MASK (0x00000020u) - #define MAC_DMA_CONFIG_TX_DMA_RESET_BIT (5) - #define MAC_DMA_CONFIG_TX_DMA_RESET_BITS (1) - /* RX_DMA_RESET field */ - #define MAC_DMA_CONFIG_RX_DMA_RESET (0x00000010u) - #define MAC_DMA_CONFIG_RX_DMA_RESET_MASK (0x00000010u) - #define MAC_DMA_CONFIG_RX_DMA_RESET_BIT (4) - #define MAC_DMA_CONFIG_RX_DMA_RESET_BITS (1) - /* TX_LOAD_B field */ - #define MAC_DMA_CONFIG_TX_LOAD_B (0x00000008u) - #define MAC_DMA_CONFIG_TX_LOAD_B_MASK (0x00000008u) - #define MAC_DMA_CONFIG_TX_LOAD_B_BIT (3) - #define MAC_DMA_CONFIG_TX_LOAD_B_BITS (1) - /* TX_LOAD_A field */ - #define MAC_DMA_CONFIG_TX_LOAD_A (0x00000004u) - #define MAC_DMA_CONFIG_TX_LOAD_A_MASK (0x00000004u) - #define MAC_DMA_CONFIG_TX_LOAD_A_BIT (2) - #define MAC_DMA_CONFIG_TX_LOAD_A_BITS (1) - /* RX_LOAD_B field */ - #define MAC_DMA_CONFIG_RX_LOAD_B (0x00000002u) - #define MAC_DMA_CONFIG_RX_LOAD_B_MASK (0x00000002u) - #define MAC_DMA_CONFIG_RX_LOAD_B_BIT (1) - #define MAC_DMA_CONFIG_RX_LOAD_B_BITS (1) - /* RX_LOAD_A field */ - #define MAC_DMA_CONFIG_RX_LOAD_A (0x00000001u) - #define MAC_DMA_CONFIG_RX_LOAD_A_MASK (0x00000001u) - #define MAC_DMA_CONFIG_RX_LOAD_A_BIT (0) - #define MAC_DMA_CONFIG_RX_LOAD_A_BITS (1) +/* TX_DMA_RESET field */ +#define MAC_DMA_CONFIG_TX_DMA_RESET (0x00000020u) +#define MAC_DMA_CONFIG_TX_DMA_RESET_MASK (0x00000020u) +#define MAC_DMA_CONFIG_TX_DMA_RESET_BIT (5) +#define MAC_DMA_CONFIG_TX_DMA_RESET_BITS (1) +/* RX_DMA_RESET field */ +#define MAC_DMA_CONFIG_RX_DMA_RESET (0x00000010u) +#define MAC_DMA_CONFIG_RX_DMA_RESET_MASK (0x00000010u) +#define MAC_DMA_CONFIG_RX_DMA_RESET_BIT (4) +#define MAC_DMA_CONFIG_RX_DMA_RESET_BITS (1) +/* TX_LOAD_B field */ +#define MAC_DMA_CONFIG_TX_LOAD_B (0x00000008u) +#define MAC_DMA_CONFIG_TX_LOAD_B_MASK (0x00000008u) +#define MAC_DMA_CONFIG_TX_LOAD_B_BIT (3) +#define MAC_DMA_CONFIG_TX_LOAD_B_BITS (1) +/* TX_LOAD_A field */ +#define MAC_DMA_CONFIG_TX_LOAD_A (0x00000004u) +#define MAC_DMA_CONFIG_TX_LOAD_A_MASK (0x00000004u) +#define MAC_DMA_CONFIG_TX_LOAD_A_BIT (2) +#define MAC_DMA_CONFIG_TX_LOAD_A_BITS (1) +/* RX_LOAD_B field */ +#define MAC_DMA_CONFIG_RX_LOAD_B (0x00000002u) +#define MAC_DMA_CONFIG_RX_LOAD_B_MASK (0x00000002u) +#define MAC_DMA_CONFIG_RX_LOAD_B_BIT (1) +#define MAC_DMA_CONFIG_RX_LOAD_B_BITS (1) +/* RX_LOAD_A field */ +#define MAC_DMA_CONFIG_RX_LOAD_A (0x00000001u) +#define MAC_DMA_CONFIG_RX_LOAD_A_MASK (0x00000001u) +#define MAC_DMA_CONFIG_RX_LOAD_A_BIT (0) +#define MAC_DMA_CONFIG_RX_LOAD_A_BITS (1) #define MAC_TIMER *((volatile uint32_t *)0x40002038u) #define MAC_TIMER_REG *((volatile uint32_t *)0x40002038u) #define MAC_TIMER_ADDR (0x40002038u) #define MAC_TIMER_RESET (0x00000000u) - /* MAC_TIMER field */ - #define MAC_TIMER_MAC_TIMER (0x000FFFFFu) - #define MAC_TIMER_MAC_TIMER_MASK (0x000FFFFFu) - #define MAC_TIMER_MAC_TIMER_BIT (0) - #define MAC_TIMER_MAC_TIMER_BITS (20) +/* MAC_TIMER field */ +#define MAC_TIMER_MAC_TIMER (0x000FFFFFu) +#define MAC_TIMER_MAC_TIMER_MASK (0x000FFFFFu) +#define MAC_TIMER_MAC_TIMER_BIT (0) +#define MAC_TIMER_MAC_TIMER_BITS (20) #define MAC_TIMER_COMPARE_A_H *((volatile uint32_t *)0x40002040u) #define MAC_TIMER_COMPARE_A_H_REG *((volatile uint32_t *)0x40002040u) #define MAC_TIMER_COMPARE_A_H_ADDR (0x40002040u) #define MAC_TIMER_COMPARE_A_H_RESET (0x00000000u) - /* MAC_COMPARE_A_H field */ - #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H (0x0000000Fu) - #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_MASK (0x0000000Fu) - #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT (0) - #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS (4) +/* MAC_COMPARE_A_H field */ +#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H (0x0000000Fu) +#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_MASK (0x0000000Fu) +#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT (0) +#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS (4) #define MAC_TIMER_COMPARE_A_L *((volatile uint32_t *)0x40002044u) #define MAC_TIMER_COMPARE_A_L_REG *((volatile uint32_t *)0x40002044u) #define MAC_TIMER_COMPARE_A_L_ADDR (0x40002044u) #define MAC_TIMER_COMPARE_A_L_RESET (0x00000000u) - /* MAC_COMPARE_A_L field */ - #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L (0x0000FFFFu) - #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_MASK (0x0000FFFFu) - #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT (0) - #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS (16) +/* MAC_COMPARE_A_L field */ +#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L (0x0000FFFFu) +#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_MASK (0x0000FFFFu) +#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT (0) +#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS (16) #define MAC_TIMER_COMPARE_B_H *((volatile uint32_t *)0x40002048u) #define MAC_TIMER_COMPARE_B_H_REG *((volatile uint32_t *)0x40002048u) #define MAC_TIMER_COMPARE_B_H_ADDR (0x40002048u) #define MAC_TIMER_COMPARE_B_H_RESET (0x00000000u) - /* MAC_COMPARE_B_H field */ - #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H (0x0000000Fu) - #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_MASK (0x0000000Fu) - #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT (0) - #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS (4) +/* MAC_COMPARE_B_H field */ +#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H (0x0000000Fu) +#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_MASK (0x0000000Fu) +#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT (0) +#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS (4) #define MAC_TIMER_COMPARE_B_L *((volatile uint32_t *)0x4000204Cu) #define MAC_TIMER_COMPARE_B_L_REG *((volatile uint32_t *)0x4000204Cu) #define MAC_TIMER_COMPARE_B_L_ADDR (0x4000204Cu) #define MAC_TIMER_COMPARE_B_L_RESET (0x00000000u) - /* MAC_COMPARE_B_L field */ - #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L (0x0000FFFFu) - #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_MASK (0x0000FFFFu) - #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT (0) - #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS (16) +/* MAC_COMPARE_B_L field */ +#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L (0x0000FFFFu) +#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_MASK (0x0000FFFFu) +#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT (0) +#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS (16) #define MAC_TIMER_CAPTURE_H *((volatile uint32_t *)0x40002050u) #define MAC_TIMER_CAPTURE_H_REG *((volatile uint32_t *)0x40002050u) #define MAC_TIMER_CAPTURE_H_ADDR (0x40002050u) #define MAC_TIMER_CAPTURE_H_RESET (0x00000000u) - /* MAC_SFD_CAPTURE_HIGH field */ - #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH (0x0000000Fu) - #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_MASK (0x0000000Fu) - #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT (0) - #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS (4) +/* MAC_SFD_CAPTURE_HIGH field */ +#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH (0x0000000Fu) +#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_MASK (0x0000000Fu) +#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT (0) +#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS (4) #define MAC_TIMER_CAPTURE_L *((volatile uint32_t *)0x40002054u) #define MAC_TIMER_CAPTURE_L_REG *((volatile uint32_t *)0x40002054u) #define MAC_TIMER_CAPTURE_L_ADDR (0x40002054u) #define MAC_TIMER_CAPTURE_L_RESET (0x00000000u) - /* MAC_SFD_CAPTURE_LOW field */ - #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW (0x0000FFFFu) - #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_MASK (0x0000FFFFu) - #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT (0) - #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS (16) +/* MAC_SFD_CAPTURE_LOW field */ +#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW (0x0000FFFFu) +#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_MASK (0x0000FFFFu) +#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT (0) +#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS (16) #define MAC_BO_TIMER *((volatile uint32_t *)0x40002058u) #define MAC_BO_TIMER_REG *((volatile uint32_t *)0x40002058u) #define MAC_BO_TIMER_ADDR (0x40002058u) #define MAC_BO_TIMER_RESET (0x00000000u) - /* MAC_BO_TIMER field */ - #define MAC_BO_TIMER_MAC_BO_TIMER (0x00000FFFu) - #define MAC_BO_TIMER_MAC_BO_TIMER_MASK (0x00000FFFu) - #define MAC_BO_TIMER_MAC_BO_TIMER_BIT (0) - #define MAC_BO_TIMER_MAC_BO_TIMER_BITS (12) +/* MAC_BO_TIMER field */ +#define MAC_BO_TIMER_MAC_BO_TIMER (0x00000FFFu) +#define MAC_BO_TIMER_MAC_BO_TIMER_MASK (0x00000FFFu) +#define MAC_BO_TIMER_MAC_BO_TIMER_BIT (0) +#define MAC_BO_TIMER_MAC_BO_TIMER_BITS (12) #define MAC_BOP_TIMER *((volatile uint32_t *)0x4000205Cu) #define MAC_BOP_TIMER_REG *((volatile uint32_t *)0x4000205Cu) #define MAC_BOP_TIMER_ADDR (0x4000205Cu) #define MAC_BOP_TIMER_RESET (0x00000000u) - /* MAC_BOP_TIMER field */ - #define MAC_BOP_TIMER_MAC_BOP_TIMER (0x0000007Fu) - #define MAC_BOP_TIMER_MAC_BOP_TIMER_MASK (0x0000007Fu) - #define MAC_BOP_TIMER_MAC_BOP_TIMER_BIT (0) - #define MAC_BOP_TIMER_MAC_BOP_TIMER_BITS (7) +/* MAC_BOP_TIMER field */ +#define MAC_BOP_TIMER_MAC_BOP_TIMER (0x0000007Fu) +#define MAC_BOP_TIMER_MAC_BOP_TIMER_MASK (0x0000007Fu) +#define MAC_BOP_TIMER_MAC_BOP_TIMER_BIT (0) +#define MAC_BOP_TIMER_MAC_BOP_TIMER_BITS (7) #define MAC_TX_STROBE *((volatile uint32_t *)0x40002060u) #define MAC_TX_STROBE_REG *((volatile uint32_t *)0x40002060u) #define MAC_TX_STROBE_ADDR (0x40002060u) #define MAC_TX_STROBE_RESET (0x00000000u) - /* AUTO_CRC_TX field */ - #define MAC_TX_STROBE_AUTO_CRC_TX (0x00000008u) - #define MAC_TX_STROBE_AUTO_CRC_TX_MASK (0x00000008u) - #define MAC_TX_STROBE_AUTO_CRC_TX_BIT (3) - #define MAC_TX_STROBE_AUTO_CRC_TX_BITS (1) - /* CCA_ON field */ - #define MAC_TX_STROBE_CCA_ON (0x00000004u) - #define MAC_TX_STROBE_CCA_ON_MASK (0x00000004u) - #define MAC_TX_STROBE_CCA_ON_BIT (2) - #define MAC_TX_STROBE_CCA_ON_BITS (1) - /* MAC_TX_RST field */ - #define MAC_TX_STROBE_MAC_TX_RST (0x00000002u) - #define MAC_TX_STROBE_MAC_TX_RST_MASK (0x00000002u) - #define MAC_TX_STROBE_MAC_TX_RST_BIT (1) - #define MAC_TX_STROBE_MAC_TX_RST_BITS (1) - /* START_TX field */ - #define MAC_TX_STROBE_START_TX (0x00000001u) - #define MAC_TX_STROBE_START_TX_MASK (0x00000001u) - #define MAC_TX_STROBE_START_TX_BIT (0) - #define MAC_TX_STROBE_START_TX_BITS (1) +/* AUTO_CRC_TX field */ +#define MAC_TX_STROBE_AUTO_CRC_TX (0x00000008u) +#define MAC_TX_STROBE_AUTO_CRC_TX_MASK (0x00000008u) +#define MAC_TX_STROBE_AUTO_CRC_TX_BIT (3) +#define MAC_TX_STROBE_AUTO_CRC_TX_BITS (1) +/* CCA_ON field */ +#define MAC_TX_STROBE_CCA_ON (0x00000004u) +#define MAC_TX_STROBE_CCA_ON_MASK (0x00000004u) +#define MAC_TX_STROBE_CCA_ON_BIT (2) +#define MAC_TX_STROBE_CCA_ON_BITS (1) +/* MAC_TX_RST field */ +#define MAC_TX_STROBE_MAC_TX_RST (0x00000002u) +#define MAC_TX_STROBE_MAC_TX_RST_MASK (0x00000002u) +#define MAC_TX_STROBE_MAC_TX_RST_BIT (1) +#define MAC_TX_STROBE_MAC_TX_RST_BITS (1) +/* START_TX field */ +#define MAC_TX_STROBE_START_TX (0x00000001u) +#define MAC_TX_STROBE_START_TX_MASK (0x00000001u) +#define MAC_TX_STROBE_START_TX_BIT (0) +#define MAC_TX_STROBE_START_TX_BITS (1) #define MAC_ACK_STROBE *((volatile uint32_t *)0x40002064u) #define MAC_ACK_STROBE_REG *((volatile uint32_t *)0x40002064u) #define MAC_ACK_STROBE_ADDR (0x40002064u) #define MAC_ACK_STROBE_RESET (0x00000000u) - /* MANUAL_ACK field */ - #define MAC_ACK_STROBE_MANUAL_ACK (0x00000002u) - #define MAC_ACK_STROBE_MANUAL_ACK_MASK (0x00000002u) - #define MAC_ACK_STROBE_MANUAL_ACK_BIT (1) - #define MAC_ACK_STROBE_MANUAL_ACK_BITS (1) - /* FRAME_PENDING field */ - #define MAC_ACK_STROBE_FRAME_PENDING (0x00000001u) - #define MAC_ACK_STROBE_FRAME_PENDING_MASK (0x00000001u) - #define MAC_ACK_STROBE_FRAME_PENDING_BIT (0) - #define MAC_ACK_STROBE_FRAME_PENDING_BITS (1) +/* MANUAL_ACK field */ +#define MAC_ACK_STROBE_MANUAL_ACK (0x00000002u) +#define MAC_ACK_STROBE_MANUAL_ACK_MASK (0x00000002u) +#define MAC_ACK_STROBE_MANUAL_ACK_BIT (1) +#define MAC_ACK_STROBE_MANUAL_ACK_BITS (1) +/* FRAME_PENDING field */ +#define MAC_ACK_STROBE_FRAME_PENDING (0x00000001u) +#define MAC_ACK_STROBE_FRAME_PENDING_MASK (0x00000001u) +#define MAC_ACK_STROBE_FRAME_PENDING_BIT (0) +#define MAC_ACK_STROBE_FRAME_PENDING_BITS (1) #define MAC_STATUS *((volatile uint32_t *)0x40002068u) #define MAC_STATUS_REG *((volatile uint32_t *)0x40002068u) #define MAC_STATUS_ADDR (0x40002068u) #define MAC_STATUS_RESET (0x00000000u) - /* RX_B_PEND_TX_ACK field */ - #define MAC_STATUS_RX_B_PEND_TX_ACK (0x00000800u) - #define MAC_STATUS_RX_B_PEND_TX_ACK_MASK (0x00000800u) - #define MAC_STATUS_RX_B_PEND_TX_ACK_BIT (11) - #define MAC_STATUS_RX_B_PEND_TX_ACK_BITS (1) - /* RX_A_PEND_TX_ACK field */ - #define MAC_STATUS_RX_A_PEND_TX_ACK (0x00000400u) - #define MAC_STATUS_RX_A_PEND_TX_ACK_MASK (0x00000400u) - #define MAC_STATUS_RX_A_PEND_TX_ACK_BIT (10) - #define MAC_STATUS_RX_A_PEND_TX_ACK_BITS (1) - /* RX_B_LAST_UNLOAD field */ - #define MAC_STATUS_RX_B_LAST_UNLOAD (0x00000200u) - #define MAC_STATUS_RX_B_LAST_UNLOAD_MASK (0x00000200u) - #define MAC_STATUS_RX_B_LAST_UNLOAD_BIT (9) - #define MAC_STATUS_RX_B_LAST_UNLOAD_BITS (1) - /* RX_A_LAST_UNLOAD field */ - #define MAC_STATUS_RX_A_LAST_UNLOAD (0x00000100u) - #define MAC_STATUS_RX_A_LAST_UNLOAD_MASK (0x00000100u) - #define MAC_STATUS_RX_A_LAST_UNLOAD_BIT (8) - #define MAC_STATUS_RX_A_LAST_UNLOAD_BITS (1) - /* WRONG_FORMAT field */ - #define MAC_STATUS_WRONG_FORMAT (0x00000080u) - #define MAC_STATUS_WRONG_FORMAT_MASK (0x00000080u) - #define MAC_STATUS_WRONG_FORMAT_BIT (7) - #define MAC_STATUS_WRONG_FORMAT_BITS (1) - /* WRONG_ADDRESS field */ - #define MAC_STATUS_WRONG_ADDRESS (0x00000040u) - #define MAC_STATUS_WRONG_ADDRESS_MASK (0x00000040u) - #define MAC_STATUS_WRONG_ADDRESS_BIT (6) - #define MAC_STATUS_WRONG_ADDRESS_BITS (1) - /* RX_ACK_REC field */ - #define MAC_STATUS_RX_ACK_REC (0x00000020u) - #define MAC_STATUS_RX_ACK_REC_MASK (0x00000020u) - #define MAC_STATUS_RX_ACK_REC_BIT (5) - #define MAC_STATUS_RX_ACK_REC_BITS (1) - /* SENDING_ACK field */ - #define MAC_STATUS_SENDING_ACK (0x00000010u) - #define MAC_STATUS_SENDING_ACK_MASK (0x00000010u) - #define MAC_STATUS_SENDING_ACK_BIT (4) - #define MAC_STATUS_SENDING_ACK_BITS (1) - /* RUN_BO field */ - #define MAC_STATUS_RUN_BO (0x00000008u) - #define MAC_STATUS_RUN_BO_MASK (0x00000008u) - #define MAC_STATUS_RUN_BO_BIT (3) - #define MAC_STATUS_RUN_BO_BITS (1) - /* TX_FRAME field */ - #define MAC_STATUS_TX_FRAME (0x00000004u) - #define MAC_STATUS_TX_FRAME_MASK (0x00000004u) - #define MAC_STATUS_TX_FRAME_BIT (2) - #define MAC_STATUS_TX_FRAME_BITS (1) - /* RX_FRAME field */ - #define MAC_STATUS_RX_FRAME (0x00000002u) - #define MAC_STATUS_RX_FRAME_MASK (0x00000002u) - #define MAC_STATUS_RX_FRAME_BIT (1) - #define MAC_STATUS_RX_FRAME_BITS (1) - /* RX_CRC_PASS field */ - #define MAC_STATUS_RX_CRC_PASS (0x00000001u) - #define MAC_STATUS_RX_CRC_PASS_MASK (0x00000001u) - #define MAC_STATUS_RX_CRC_PASS_BIT (0) - #define MAC_STATUS_RX_CRC_PASS_BITS (1) +/* RX_B_PEND_TX_ACK field */ +#define MAC_STATUS_RX_B_PEND_TX_ACK (0x00000800u) +#define MAC_STATUS_RX_B_PEND_TX_ACK_MASK (0x00000800u) +#define MAC_STATUS_RX_B_PEND_TX_ACK_BIT (11) +#define MAC_STATUS_RX_B_PEND_TX_ACK_BITS (1) +/* RX_A_PEND_TX_ACK field */ +#define MAC_STATUS_RX_A_PEND_TX_ACK (0x00000400u) +#define MAC_STATUS_RX_A_PEND_TX_ACK_MASK (0x00000400u) +#define MAC_STATUS_RX_A_PEND_TX_ACK_BIT (10) +#define MAC_STATUS_RX_A_PEND_TX_ACK_BITS (1) +/* RX_B_LAST_UNLOAD field */ +#define MAC_STATUS_RX_B_LAST_UNLOAD (0x00000200u) +#define MAC_STATUS_RX_B_LAST_UNLOAD_MASK (0x00000200u) +#define MAC_STATUS_RX_B_LAST_UNLOAD_BIT (9) +#define MAC_STATUS_RX_B_LAST_UNLOAD_BITS (1) +/* RX_A_LAST_UNLOAD field */ +#define MAC_STATUS_RX_A_LAST_UNLOAD (0x00000100u) +#define MAC_STATUS_RX_A_LAST_UNLOAD_MASK (0x00000100u) +#define MAC_STATUS_RX_A_LAST_UNLOAD_BIT (8) +#define MAC_STATUS_RX_A_LAST_UNLOAD_BITS (1) +/* WRONG_FORMAT field */ +#define MAC_STATUS_WRONG_FORMAT (0x00000080u) +#define MAC_STATUS_WRONG_FORMAT_MASK (0x00000080u) +#define MAC_STATUS_WRONG_FORMAT_BIT (7) +#define MAC_STATUS_WRONG_FORMAT_BITS (1) +/* WRONG_ADDRESS field */ +#define MAC_STATUS_WRONG_ADDRESS (0x00000040u) +#define MAC_STATUS_WRONG_ADDRESS_MASK (0x00000040u) +#define MAC_STATUS_WRONG_ADDRESS_BIT (6) +#define MAC_STATUS_WRONG_ADDRESS_BITS (1) +/* RX_ACK_REC field */ +#define MAC_STATUS_RX_ACK_REC (0x00000020u) +#define MAC_STATUS_RX_ACK_REC_MASK (0x00000020u) +#define MAC_STATUS_RX_ACK_REC_BIT (5) +#define MAC_STATUS_RX_ACK_REC_BITS (1) +/* SENDING_ACK field */ +#define MAC_STATUS_SENDING_ACK (0x00000010u) +#define MAC_STATUS_SENDING_ACK_MASK (0x00000010u) +#define MAC_STATUS_SENDING_ACK_BIT (4) +#define MAC_STATUS_SENDING_ACK_BITS (1) +/* RUN_BO field */ +#define MAC_STATUS_RUN_BO (0x00000008u) +#define MAC_STATUS_RUN_BO_MASK (0x00000008u) +#define MAC_STATUS_RUN_BO_BIT (3) +#define MAC_STATUS_RUN_BO_BITS (1) +/* TX_FRAME field */ +#define MAC_STATUS_TX_FRAME (0x00000004u) +#define MAC_STATUS_TX_FRAME_MASK (0x00000004u) +#define MAC_STATUS_TX_FRAME_BIT (2) +#define MAC_STATUS_TX_FRAME_BITS (1) +/* RX_FRAME field */ +#define MAC_STATUS_RX_FRAME (0x00000002u) +#define MAC_STATUS_RX_FRAME_MASK (0x00000002u) +#define MAC_STATUS_RX_FRAME_BIT (1) +#define MAC_STATUS_RX_FRAME_BITS (1) +/* RX_CRC_PASS field */ +#define MAC_STATUS_RX_CRC_PASS (0x00000001u) +#define MAC_STATUS_RX_CRC_PASS_MASK (0x00000001u) +#define MAC_STATUS_RX_CRC_PASS_BIT (0) +#define MAC_STATUS_RX_CRC_PASS_BITS (1) #define TX_CRC *((volatile uint32_t *)0x4000206Cu) #define TX_CRC_REG *((volatile uint32_t *)0x4000206Cu) #define TX_CRC_ADDR (0x4000206Cu) #define TX_CRC_RESET (0x00000000u) - /* TX_CRC field */ - #define TX_CRC_TX_CRC (0x0000FFFFu) - #define TX_CRC_TX_CRC_MASK (0x0000FFFFu) - #define TX_CRC_TX_CRC_BIT (0) - #define TX_CRC_TX_CRC_BITS (16) +/* TX_CRC field */ +#define TX_CRC_TX_CRC (0x0000FFFFu) +#define TX_CRC_TX_CRC_MASK (0x0000FFFFu) +#define TX_CRC_TX_CRC_BIT (0) +#define TX_CRC_TX_CRC_BITS (16) #define RX_CRC *((volatile uint32_t *)0x40002070u) #define RX_CRC_REG *((volatile uint32_t *)0x40002070u) #define RX_CRC_ADDR (0x40002070u) #define RX_CRC_RESET (0x00000000u) - /* RX_CRC field */ - #define RX_CRC_RX_CRC (0x0000FFFFu) - #define RX_CRC_RX_CRC_MASK (0x0000FFFFu) - #define RX_CRC_RX_CRC_BIT (0) - #define RX_CRC_RX_CRC_BITS (16) +/* RX_CRC field */ +#define RX_CRC_RX_CRC (0x0000FFFFu) +#define RX_CRC_RX_CRC_MASK (0x0000FFFFu) +#define RX_CRC_RX_CRC_BIT (0) +#define RX_CRC_RX_CRC_BITS (16) #define MAC_ACK_TO *((volatile uint32_t *)0x40002074u) #define MAC_ACK_TO_REG *((volatile uint32_t *)0x40002074u) #define MAC_ACK_TO_ADDR (0x40002074u) #define MAC_ACK_TO_RESET (0x00000300u) - /* ACK_TO field */ - #define MAC_ACK_TO_ACK_TO (0x00003FFFu) - #define MAC_ACK_TO_ACK_TO_MASK (0x00003FFFu) - #define MAC_ACK_TO_ACK_TO_BIT (0) - #define MAC_ACK_TO_ACK_TO_BITS (14) +/* ACK_TO field */ +#define MAC_ACK_TO_ACK_TO (0x00003FFFu) +#define MAC_ACK_TO_ACK_TO_MASK (0x00003FFFu) +#define MAC_ACK_TO_ACK_TO_BIT (0) +#define MAC_ACK_TO_ACK_TO_BITS (14) #define MAC_BOP_COMPARE *((volatile uint32_t *)0x40002078u) #define MAC_BOP_COMPARE_REG *((volatile uint32_t *)0x40002078u) #define MAC_BOP_COMPARE_ADDR (0x40002078u) #define MAC_BOP_COMPARE_RESET (0x00000014u) - /* MAC_BOP_COMPARE field */ - #define MAC_BOP_COMPARE_MAC_BOP_COMPARE (0x0000007Fu) - #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_MASK (0x0000007Fu) - #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT (0) - #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS (7) +/* MAC_BOP_COMPARE field */ +#define MAC_BOP_COMPARE_MAC_BOP_COMPARE (0x0000007Fu) +#define MAC_BOP_COMPARE_MAC_BOP_COMPARE_MASK (0x0000007Fu) +#define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT (0) +#define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS (7) #define MAC_TX_ACK_FRAME *((volatile uint32_t *)0x4000207Cu) #define MAC_TX_ACK_FRAME_REG *((volatile uint32_t *)0x4000207Cu) #define MAC_TX_ACK_FRAME_ADDR (0x4000207Cu) #define MAC_TX_ACK_FRAME_RESET (0x00000002u) - /* ACK_SRC_AM field */ - #define MAC_TX_ACK_FRAME_ACK_SRC_AM (0x0000C000u) - #define MAC_TX_ACK_FRAME_ACK_SRC_AM_MASK (0x0000C000u) - #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BIT (14) - #define MAC_TX_ACK_FRAME_ACK_SRC_AM_BITS (2) - /* RES1213 field */ - #define MAC_TX_ACK_FRAME_RES1213 (0x00003000u) - #define MAC_TX_ACK_FRAME_RES1213_MASK (0x00003000u) - #define MAC_TX_ACK_FRAME_RES1213_BIT (12) - #define MAC_TX_ACK_FRAME_RES1213_BITS (2) - /* ACK_DST_AM field */ - #define MAC_TX_ACK_FRAME_ACK_DST_AM (0x00000C00u) - #define MAC_TX_ACK_FRAME_ACK_DST_AM_MASK (0x00000C00u) - #define MAC_TX_ACK_FRAME_ACK_DST_AM_BIT (10) - #define MAC_TX_ACK_FRAME_ACK_DST_AM_BITS (2) - /* RES789 field */ - #define MAC_TX_ACK_FRAME_RES789 (0x00000380u) - #define MAC_TX_ACK_FRAME_RES789_MASK (0x00000380u) - #define MAC_TX_ACK_FRAME_RES789_BIT (7) - #define MAC_TX_ACK_FRAME_RES789_BITS (3) - /* ACK_IP field */ - #define MAC_TX_ACK_FRAME_ACK_IP (0x00000040u) - #define MAC_TX_ACK_FRAME_ACK_IP_MASK (0x00000040u) - #define MAC_TX_ACK_FRAME_ACK_IP_BIT (6) - #define MAC_TX_ACK_FRAME_ACK_IP_BITS (1) - /* ACK_ACK_REQ field */ - #define MAC_TX_ACK_FRAME_ACK_ACK_REQ (0x00000020u) - #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_MASK (0x00000020u) - #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BIT (5) - #define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BITS (1) - /* ACK_FRAME_P field */ - #define MAC_TX_ACK_FRAME_ACK_FRAME_P (0x00000010u) - #define MAC_TX_ACK_FRAME_ACK_FRAME_P_MASK (0x00000010u) - #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BIT (4) - #define MAC_TX_ACK_FRAME_ACK_FRAME_P_BITS (1) - /* ACK_SEC_EN field */ - #define MAC_TX_ACK_FRAME_ACK_SEC_EN (0x00000008u) - #define MAC_TX_ACK_FRAME_ACK_SEC_EN_MASK (0x00000008u) - #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BIT (3) - #define MAC_TX_ACK_FRAME_ACK_SEC_EN_BITS (1) - /* ACK_FRAME_T field */ - #define MAC_TX_ACK_FRAME_ACK_FRAME_T (0x00000007u) - #define MAC_TX_ACK_FRAME_ACK_FRAME_T_MASK (0x00000007u) - #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT (0) - #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS (3) +/* ACK_SRC_AM field */ +#define MAC_TX_ACK_FRAME_ACK_SRC_AM (0x0000C000u) +#define MAC_TX_ACK_FRAME_ACK_SRC_AM_MASK (0x0000C000u) +#define MAC_TX_ACK_FRAME_ACK_SRC_AM_BIT (14) +#define MAC_TX_ACK_FRAME_ACK_SRC_AM_BITS (2) +/* RES1213 field */ +#define MAC_TX_ACK_FRAME_RES1213 (0x00003000u) +#define MAC_TX_ACK_FRAME_RES1213_MASK (0x00003000u) +#define MAC_TX_ACK_FRAME_RES1213_BIT (12) +#define MAC_TX_ACK_FRAME_RES1213_BITS (2) +/* ACK_DST_AM field */ +#define MAC_TX_ACK_FRAME_ACK_DST_AM (0x00000C00u) +#define MAC_TX_ACK_FRAME_ACK_DST_AM_MASK (0x00000C00u) +#define MAC_TX_ACK_FRAME_ACK_DST_AM_BIT (10) +#define MAC_TX_ACK_FRAME_ACK_DST_AM_BITS (2) +/* RES789 field */ +#define MAC_TX_ACK_FRAME_RES789 (0x00000380u) +#define MAC_TX_ACK_FRAME_RES789_MASK (0x00000380u) +#define MAC_TX_ACK_FRAME_RES789_BIT (7) +#define MAC_TX_ACK_FRAME_RES789_BITS (3) +/* ACK_IP field */ +#define MAC_TX_ACK_FRAME_ACK_IP (0x00000040u) +#define MAC_TX_ACK_FRAME_ACK_IP_MASK (0x00000040u) +#define MAC_TX_ACK_FRAME_ACK_IP_BIT (6) +#define MAC_TX_ACK_FRAME_ACK_IP_BITS (1) +/* ACK_ACK_REQ field */ +#define MAC_TX_ACK_FRAME_ACK_ACK_REQ (0x00000020u) +#define MAC_TX_ACK_FRAME_ACK_ACK_REQ_MASK (0x00000020u) +#define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BIT (5) +#define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BITS (1) +/* ACK_FRAME_P field */ +#define MAC_TX_ACK_FRAME_ACK_FRAME_P (0x00000010u) +#define MAC_TX_ACK_FRAME_ACK_FRAME_P_MASK (0x00000010u) +#define MAC_TX_ACK_FRAME_ACK_FRAME_P_BIT (4) +#define MAC_TX_ACK_FRAME_ACK_FRAME_P_BITS (1) +/* ACK_SEC_EN field */ +#define MAC_TX_ACK_FRAME_ACK_SEC_EN (0x00000008u) +#define MAC_TX_ACK_FRAME_ACK_SEC_EN_MASK (0x00000008u) +#define MAC_TX_ACK_FRAME_ACK_SEC_EN_BIT (3) +#define MAC_TX_ACK_FRAME_ACK_SEC_EN_BITS (1) +/* ACK_FRAME_T field */ +#define MAC_TX_ACK_FRAME_ACK_FRAME_T (0x00000007u) +#define MAC_TX_ACK_FRAME_ACK_FRAME_T_MASK (0x00000007u) +#define MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT (0) +#define MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS (3) #define MAC_CONFIG *((volatile uint32_t *)0x40002080u) #define MAC_CONFIG_REG *((volatile uint32_t *)0x40002080u) #define MAC_CONFIG_ADDR (0x40002080u) #define MAC_CONFIG_RESET (0x00000000u) - /* RSSI_INST_EN field */ - #define MAC_CONFIG_RSSI_INST_EN (0x00000004u) - #define MAC_CONFIG_RSSI_INST_EN_MASK (0x00000004u) - #define MAC_CONFIG_RSSI_INST_EN_BIT (2) - #define MAC_CONFIG_RSSI_INST_EN_BITS (1) - /* SPI_SPY_EN field */ - #define MAC_CONFIG_SPI_SPY_EN (0x00000002u) - #define MAC_CONFIG_SPI_SPY_EN_MASK (0x00000002u) - #define MAC_CONFIG_SPI_SPY_EN_BIT (1) - #define MAC_CONFIG_SPI_SPY_EN_BITS (1) - /* MAC_MODE field */ - #define MAC_CONFIG_MAC_MODE (0x00000001u) - #define MAC_CONFIG_MAC_MODE_MASK (0x00000001u) - #define MAC_CONFIG_MAC_MODE_BIT (0) - #define MAC_CONFIG_MAC_MODE_BITS (1) +/* RSSI_INST_EN field */ +#define MAC_CONFIG_RSSI_INST_EN (0x00000004u) +#define MAC_CONFIG_RSSI_INST_EN_MASK (0x00000004u) +#define MAC_CONFIG_RSSI_INST_EN_BIT (2) +#define MAC_CONFIG_RSSI_INST_EN_BITS (1) +/* SPI_SPY_EN field */ +#define MAC_CONFIG_SPI_SPY_EN (0x00000002u) +#define MAC_CONFIG_SPI_SPY_EN_MASK (0x00000002u) +#define MAC_CONFIG_SPI_SPY_EN_BIT (1) +#define MAC_CONFIG_SPI_SPY_EN_BITS (1) +/* MAC_MODE field */ +#define MAC_CONFIG_MAC_MODE (0x00000001u) +#define MAC_CONFIG_MAC_MODE_MASK (0x00000001u) +#define MAC_CONFIG_MAC_MODE_BIT (0) +#define MAC_CONFIG_MAC_MODE_BITS (1) #define MAC_RX_CONFIG *((volatile uint32_t *)0x40002084u) #define MAC_RX_CONFIG_REG *((volatile uint32_t *)0x40002084u) #define MAC_RX_CONFIG_ADDR (0x40002084u) #define MAC_RX_CONFIG_RESET (0x00000000u) - /* AUTO_ACK field */ - #define MAC_RX_CONFIG_AUTO_ACK (0x00000080u) - #define MAC_RX_CONFIG_AUTO_ACK_MASK (0x00000080u) - #define MAC_RX_CONFIG_AUTO_ACK_BIT (7) - #define MAC_RX_CONFIG_AUTO_ACK_BITS (1) - /* APPEND_INFO field */ - #define MAC_RX_CONFIG_APPEND_INFO (0x00000040u) - #define MAC_RX_CONFIG_APPEND_INFO_MASK (0x00000040u) - #define MAC_RX_CONFIG_APPEND_INFO_BIT (6) - #define MAC_RX_CONFIG_APPEND_INFO_BITS (1) - /* COORDINATOR field */ - #define MAC_RX_CONFIG_COORDINATOR (0x00000020u) - #define MAC_RX_CONFIG_COORDINATOR_MASK (0x00000020u) - #define MAC_RX_CONFIG_COORDINATOR_BIT (5) - #define MAC_RX_CONFIG_COORDINATOR_BITS (1) - /* FILT_ADDR_ON field */ - #define MAC_RX_CONFIG_FILT_ADDR_ON (0x00000010u) - #define MAC_RX_CONFIG_FILT_ADDR_ON_MASK (0x00000010u) - #define MAC_RX_CONFIG_FILT_ADDR_ON_BIT (4) - #define MAC_RX_CONFIG_FILT_ADDR_ON_BITS (1) - /* RES_FILT_PASS_ADDR field */ - #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR (0x00000008u) - #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_MASK (0x00000008u) - #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BIT (3) - #define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BITS (1) - /* RES_FILT_PASS field */ - #define MAC_RX_CONFIG_RES_FILT_PASS (0x00000004u) - #define MAC_RX_CONFIG_RES_FILT_PASS_MASK (0x00000004u) - #define MAC_RX_CONFIG_RES_FILT_PASS_BIT (2) - #define MAC_RX_CONFIG_RES_FILT_PASS_BITS (1) - /* FILT_FORMAT_ON field */ - #define MAC_RX_CONFIG_FILT_FORMAT_ON (0x00000002u) - #define MAC_RX_CONFIG_FILT_FORMAT_ON_MASK (0x00000002u) - #define MAC_RX_CONFIG_FILT_FORMAT_ON_BIT (1) - #define MAC_RX_CONFIG_FILT_FORMAT_ON_BITS (1) - /* MAC_RX_RST field */ - #define MAC_RX_CONFIG_MAC_RX_RST (0x00000001u) - #define MAC_RX_CONFIG_MAC_RX_RST_MASK (0x00000001u) - #define MAC_RX_CONFIG_MAC_RX_RST_BIT (0) - #define MAC_RX_CONFIG_MAC_RX_RST_BITS (1) +/* AUTO_ACK field */ +#define MAC_RX_CONFIG_AUTO_ACK (0x00000080u) +#define MAC_RX_CONFIG_AUTO_ACK_MASK (0x00000080u) +#define MAC_RX_CONFIG_AUTO_ACK_BIT (7) +#define MAC_RX_CONFIG_AUTO_ACK_BITS (1) +/* APPEND_INFO field */ +#define MAC_RX_CONFIG_APPEND_INFO (0x00000040u) +#define MAC_RX_CONFIG_APPEND_INFO_MASK (0x00000040u) +#define MAC_RX_CONFIG_APPEND_INFO_BIT (6) +#define MAC_RX_CONFIG_APPEND_INFO_BITS (1) +/* COORDINATOR field */ +#define MAC_RX_CONFIG_COORDINATOR (0x00000020u) +#define MAC_RX_CONFIG_COORDINATOR_MASK (0x00000020u) +#define MAC_RX_CONFIG_COORDINATOR_BIT (5) +#define MAC_RX_CONFIG_COORDINATOR_BITS (1) +/* FILT_ADDR_ON field */ +#define MAC_RX_CONFIG_FILT_ADDR_ON (0x00000010u) +#define MAC_RX_CONFIG_FILT_ADDR_ON_MASK (0x00000010u) +#define MAC_RX_CONFIG_FILT_ADDR_ON_BIT (4) +#define MAC_RX_CONFIG_FILT_ADDR_ON_BITS (1) +/* RES_FILT_PASS_ADDR field */ +#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR (0x00000008u) +#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_MASK (0x00000008u) +#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BIT (3) +#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BITS (1) +/* RES_FILT_PASS field */ +#define MAC_RX_CONFIG_RES_FILT_PASS (0x00000004u) +#define MAC_RX_CONFIG_RES_FILT_PASS_MASK (0x00000004u) +#define MAC_RX_CONFIG_RES_FILT_PASS_BIT (2) +#define MAC_RX_CONFIG_RES_FILT_PASS_BITS (1) +/* FILT_FORMAT_ON field */ +#define MAC_RX_CONFIG_FILT_FORMAT_ON (0x00000002u) +#define MAC_RX_CONFIG_FILT_FORMAT_ON_MASK (0x00000002u) +#define MAC_RX_CONFIG_FILT_FORMAT_ON_BIT (1) +#define MAC_RX_CONFIG_FILT_FORMAT_ON_BITS (1) +/* MAC_RX_RST field */ +#define MAC_RX_CONFIG_MAC_RX_RST (0x00000001u) +#define MAC_RX_CONFIG_MAC_RX_RST_MASK (0x00000001u) +#define MAC_RX_CONFIG_MAC_RX_RST_BIT (0) +#define MAC_RX_CONFIG_MAC_RX_RST_BITS (1) #define MAC_TX_CONFIG *((volatile uint32_t *)0x40002088u) #define MAC_TX_CONFIG_REG *((volatile uint32_t *)0x40002088u) #define MAC_TX_CONFIG_ADDR (0x40002088u) #define MAC_TX_CONFIG_RESET (0x00000008u) - /* SLOTTED field */ - #define MAC_TX_CONFIG_SLOTTED (0x00000010u) - #define MAC_TX_CONFIG_SLOTTED_MASK (0x00000010u) - #define MAC_TX_CONFIG_SLOTTED_BIT (4) - #define MAC_TX_CONFIG_SLOTTED_BITS (1) - /* CCA_DELAY field */ - #define MAC_TX_CONFIG_CCA_DELAY (0x00000008u) - #define MAC_TX_CONFIG_CCA_DELAY_MASK (0x00000008u) - #define MAC_TX_CONFIG_CCA_DELAY_BIT (3) - #define MAC_TX_CONFIG_CCA_DELAY_BITS (1) - /* SLOTTED_ACK field */ - #define MAC_TX_CONFIG_SLOTTED_ACK (0x00000004u) - #define MAC_TX_CONFIG_SLOTTED_ACK_MASK (0x00000004u) - #define MAC_TX_CONFIG_SLOTTED_ACK_BIT (2) - #define MAC_TX_CONFIG_SLOTTED_ACK_BITS (1) - /* INFINITE_CRC field */ - #define MAC_TX_CONFIG_INFINITE_CRC (0x00000002u) - #define MAC_TX_CONFIG_INFINITE_CRC_MASK (0x00000002u) - #define MAC_TX_CONFIG_INFINITE_CRC_BIT (1) - #define MAC_TX_CONFIG_INFINITE_CRC_BITS (1) - /* WAIT_ACK field */ - #define MAC_TX_CONFIG_WAIT_ACK (0x00000001u) - #define MAC_TX_CONFIG_WAIT_ACK_MASK (0x00000001u) - #define MAC_TX_CONFIG_WAIT_ACK_BIT (0) - #define MAC_TX_CONFIG_WAIT_ACK_BITS (1) +/* SLOTTED field */ +#define MAC_TX_CONFIG_SLOTTED (0x00000010u) +#define MAC_TX_CONFIG_SLOTTED_MASK (0x00000010u) +#define MAC_TX_CONFIG_SLOTTED_BIT (4) +#define MAC_TX_CONFIG_SLOTTED_BITS (1) +/* CCA_DELAY field */ +#define MAC_TX_CONFIG_CCA_DELAY (0x00000008u) +#define MAC_TX_CONFIG_CCA_DELAY_MASK (0x00000008u) +#define MAC_TX_CONFIG_CCA_DELAY_BIT (3) +#define MAC_TX_CONFIG_CCA_DELAY_BITS (1) +/* SLOTTED_ACK field */ +#define MAC_TX_CONFIG_SLOTTED_ACK (0x00000004u) +#define MAC_TX_CONFIG_SLOTTED_ACK_MASK (0x00000004u) +#define MAC_TX_CONFIG_SLOTTED_ACK_BIT (2) +#define MAC_TX_CONFIG_SLOTTED_ACK_BITS (1) +/* INFINITE_CRC field */ +#define MAC_TX_CONFIG_INFINITE_CRC (0x00000002u) +#define MAC_TX_CONFIG_INFINITE_CRC_MASK (0x00000002u) +#define MAC_TX_CONFIG_INFINITE_CRC_BIT (1) +#define MAC_TX_CONFIG_INFINITE_CRC_BITS (1) +/* WAIT_ACK field */ +#define MAC_TX_CONFIG_WAIT_ACK (0x00000001u) +#define MAC_TX_CONFIG_WAIT_ACK_MASK (0x00000001u) +#define MAC_TX_CONFIG_WAIT_ACK_BIT (0) +#define MAC_TX_CONFIG_WAIT_ACK_BITS (1) #define MAC_TIMER_CTRL *((volatile uint32_t *)0x4000208Cu) #define MAC_TIMER_CTRL_REG *((volatile uint32_t *)0x4000208Cu) #define MAC_TIMER_CTRL_ADDR (0x4000208Cu) #define MAC_TIMER_CTRL_RESET (0x00000000u) - /* COMP_A_SYNC field */ - #define MAC_TIMER_CTRL_COMP_A_SYNC (0x00000040u) - #define MAC_TIMER_CTRL_COMP_A_SYNC_MASK (0x00000040u) - #define MAC_TIMER_CTRL_COMP_A_SYNC_BIT (6) - #define MAC_TIMER_CTRL_COMP_A_SYNC_BITS (1) - /* BOP_TIMER_RST field */ - #define MAC_TIMER_CTRL_BOP_TIMER_RST (0x00000020u) - #define MAC_TIMER_CTRL_BOP_TIMER_RST_MASK (0x00000020u) - #define MAC_TIMER_CTRL_BOP_TIMER_RST_BIT (5) - #define MAC_TIMER_CTRL_BOP_TIMER_RST_BITS (1) - /* BOP_TIMER_EN field */ - #define MAC_TIMER_CTRL_BOP_TIMER_EN (0x00000010u) - #define MAC_TIMER_CTRL_BOP_TIMER_EN_MASK (0x00000010u) - #define MAC_TIMER_CTRL_BOP_TIMER_EN_BIT (4) - #define MAC_TIMER_CTRL_BOP_TIMER_EN_BITS (1) - /* BO_TIMER_RST field */ - #define MAC_TIMER_CTRL_BO_TIMER_RST (0x00000008u) - #define MAC_TIMER_CTRL_BO_TIMER_RST_MASK (0x00000008u) - #define MAC_TIMER_CTRL_BO_TIMER_RST_BIT (3) - #define MAC_TIMER_CTRL_BO_TIMER_RST_BITS (1) - /* BO_TIMER_EN field */ - #define MAC_TIMER_CTRL_BO_TIMER_EN (0x00000004u) - #define MAC_TIMER_CTRL_BO_TIMER_EN_MASK (0x00000004u) - #define MAC_TIMER_CTRL_BO_TIMER_EN_BIT (2) - #define MAC_TIMER_CTRL_BO_TIMER_EN_BITS (1) - /* MAC_TIMER_RST field */ - #define MAC_TIMER_CTRL_MAC_TIMER_RST (0x00000002u) - #define MAC_TIMER_CTRL_MAC_TIMER_RST_MASK (0x00000002u) - #define MAC_TIMER_CTRL_MAC_TIMER_RST_BIT (1) - #define MAC_TIMER_CTRL_MAC_TIMER_RST_BITS (1) - /* MAC_TIMER_EN field */ - #define MAC_TIMER_CTRL_MAC_TIMER_EN (0x00000001u) - #define MAC_TIMER_CTRL_MAC_TIMER_EN_MASK (0x00000001u) - #define MAC_TIMER_CTRL_MAC_TIMER_EN_BIT (0) - #define MAC_TIMER_CTRL_MAC_TIMER_EN_BITS (1) +/* COMP_A_SYNC field */ +#define MAC_TIMER_CTRL_COMP_A_SYNC (0x00000040u) +#define MAC_TIMER_CTRL_COMP_A_SYNC_MASK (0x00000040u) +#define MAC_TIMER_CTRL_COMP_A_SYNC_BIT (6) +#define MAC_TIMER_CTRL_COMP_A_SYNC_BITS (1) +/* BOP_TIMER_RST field */ +#define MAC_TIMER_CTRL_BOP_TIMER_RST (0x00000020u) +#define MAC_TIMER_CTRL_BOP_TIMER_RST_MASK (0x00000020u) +#define MAC_TIMER_CTRL_BOP_TIMER_RST_BIT (5) +#define MAC_TIMER_CTRL_BOP_TIMER_RST_BITS (1) +/* BOP_TIMER_EN field */ +#define MAC_TIMER_CTRL_BOP_TIMER_EN (0x00000010u) +#define MAC_TIMER_CTRL_BOP_TIMER_EN_MASK (0x00000010u) +#define MAC_TIMER_CTRL_BOP_TIMER_EN_BIT (4) +#define MAC_TIMER_CTRL_BOP_TIMER_EN_BITS (1) +/* BO_TIMER_RST field */ +#define MAC_TIMER_CTRL_BO_TIMER_RST (0x00000008u) +#define MAC_TIMER_CTRL_BO_TIMER_RST_MASK (0x00000008u) +#define MAC_TIMER_CTRL_BO_TIMER_RST_BIT (3) +#define MAC_TIMER_CTRL_BO_TIMER_RST_BITS (1) +/* BO_TIMER_EN field */ +#define MAC_TIMER_CTRL_BO_TIMER_EN (0x00000004u) +#define MAC_TIMER_CTRL_BO_TIMER_EN_MASK (0x00000004u) +#define MAC_TIMER_CTRL_BO_TIMER_EN_BIT (2) +#define MAC_TIMER_CTRL_BO_TIMER_EN_BITS (1) +/* MAC_TIMER_RST field */ +#define MAC_TIMER_CTRL_MAC_TIMER_RST (0x00000002u) +#define MAC_TIMER_CTRL_MAC_TIMER_RST_MASK (0x00000002u) +#define MAC_TIMER_CTRL_MAC_TIMER_RST_BIT (1) +#define MAC_TIMER_CTRL_MAC_TIMER_RST_BITS (1) +/* MAC_TIMER_EN field */ +#define MAC_TIMER_CTRL_MAC_TIMER_EN (0x00000001u) +#define MAC_TIMER_CTRL_MAC_TIMER_EN_MASK (0x00000001u) +#define MAC_TIMER_CTRL_MAC_TIMER_EN_BIT (0) +#define MAC_TIMER_CTRL_MAC_TIMER_EN_BITS (1) #define PAN_ID *((volatile uint32_t *)0x40002090u) #define PAN_ID_REG *((volatile uint32_t *)0x40002090u) #define PAN_ID_ADDR (0x40002090u) #define PAN_ID_RESET (0x00000000u) - /* PAN_ID field */ - #define PAN_ID_PAN_ID (0x0000FFFFu) - #define PAN_ID_PAN_ID_MASK (0x0000FFFFu) - #define PAN_ID_PAN_ID_BIT (0) - #define PAN_ID_PAN_ID_BITS (16) +/* PAN_ID field */ +#define PAN_ID_PAN_ID (0x0000FFFFu) +#define PAN_ID_PAN_ID_MASK (0x0000FFFFu) +#define PAN_ID_PAN_ID_BIT (0) +#define PAN_ID_PAN_ID_BITS (16) #define SHORT_ADDR *((volatile uint32_t *)0x40002094u) #define SHORT_ADDR_REG *((volatile uint32_t *)0x40002094u) #define SHORT_ADDR_ADDR (0x40002094u) #define SHORT_ADDR_RESET (0x00000000u) - /* SHORT_ADDR field */ - #define SHORT_ADDR_SHORT_ADDR (0x0000FFFFu) - #define SHORT_ADDR_SHORT_ADDR_MASK (0x0000FFFFu) - #define SHORT_ADDR_SHORT_ADDR_BIT (0) - #define SHORT_ADDR_SHORT_ADDR_BITS (16) +/* SHORT_ADDR field */ +#define SHORT_ADDR_SHORT_ADDR (0x0000FFFFu) +#define SHORT_ADDR_SHORT_ADDR_MASK (0x0000FFFFu) +#define SHORT_ADDR_SHORT_ADDR_BIT (0) +#define SHORT_ADDR_SHORT_ADDR_BITS (16) #define EXT_ADDR_0 *((volatile uint32_t *)0x40002098u) #define EXT_ADDR_0_REG *((volatile uint32_t *)0x40002098u) #define EXT_ADDR_0_ADDR (0x40002098u) #define EXT_ADDR_0_RESET (0x00000000u) - /* EXT_ADDR_0 field */ - #define EXT_ADDR_0_EXT_ADDR_0 (0x0000FFFFu) - #define EXT_ADDR_0_EXT_ADDR_0_MASK (0x0000FFFFu) - #define EXT_ADDR_0_EXT_ADDR_0_BIT (0) - #define EXT_ADDR_0_EXT_ADDR_0_BITS (16) +/* EXT_ADDR_0 field */ +#define EXT_ADDR_0_EXT_ADDR_0 (0x0000FFFFu) +#define EXT_ADDR_0_EXT_ADDR_0_MASK (0x0000FFFFu) +#define EXT_ADDR_0_EXT_ADDR_0_BIT (0) +#define EXT_ADDR_0_EXT_ADDR_0_BITS (16) #define EXT_ADDR_1 *((volatile uint32_t *)0x4000209Cu) #define EXT_ADDR_1_REG *((volatile uint32_t *)0x4000209Cu) #define EXT_ADDR_1_ADDR (0x4000209Cu) #define EXT_ADDR_1_RESET (0x00000000u) - /* EXT_ADDR_1 field */ - #define EXT_ADDR_1_EXT_ADDR_1 (0x0000FFFFu) - #define EXT_ADDR_1_EXT_ADDR_1_MASK (0x0000FFFFu) - #define EXT_ADDR_1_EXT_ADDR_1_BIT (0) - #define EXT_ADDR_1_EXT_ADDR_1_BITS (16) +/* EXT_ADDR_1 field */ +#define EXT_ADDR_1_EXT_ADDR_1 (0x0000FFFFu) +#define EXT_ADDR_1_EXT_ADDR_1_MASK (0x0000FFFFu) +#define EXT_ADDR_1_EXT_ADDR_1_BIT (0) +#define EXT_ADDR_1_EXT_ADDR_1_BITS (16) #define EXT_ADDR_2 *((volatile uint32_t *)0x400020A0u) #define EXT_ADDR_2_REG *((volatile uint32_t *)0x400020A0u) #define EXT_ADDR_2_ADDR (0x400020A0u) #define EXT_ADDR_2_RESET (0x00000000u) - /* EXT_ADDR_2 field */ - #define EXT_ADDR_2_EXT_ADDR_2 (0x0000FFFFu) - #define EXT_ADDR_2_EXT_ADDR_2_MASK (0x0000FFFFu) - #define EXT_ADDR_2_EXT_ADDR_2_BIT (0) - #define EXT_ADDR_2_EXT_ADDR_2_BITS (16) +/* EXT_ADDR_2 field */ +#define EXT_ADDR_2_EXT_ADDR_2 (0x0000FFFFu) +#define EXT_ADDR_2_EXT_ADDR_2_MASK (0x0000FFFFu) +#define EXT_ADDR_2_EXT_ADDR_2_BIT (0) +#define EXT_ADDR_2_EXT_ADDR_2_BITS (16) #define EXT_ADDR_3 *((volatile uint32_t *)0x400020A4u) #define EXT_ADDR_3_REG *((volatile uint32_t *)0x400020A4u) #define EXT_ADDR_3_ADDR (0x400020A4u) #define EXT_ADDR_3_RESET (0x00000000u) - /* EXT_ADDR_3 field */ - #define EXT_ADDR_3_EXT_ADDR_3 (0x0000FFFFu) - #define EXT_ADDR_3_EXT_ADDR_3_MASK (0x0000FFFFu) - #define EXT_ADDR_3_EXT_ADDR_3_BIT (0) - #define EXT_ADDR_3_EXT_ADDR_3_BITS (16) +/* EXT_ADDR_3 field */ +#define EXT_ADDR_3_EXT_ADDR_3 (0x0000FFFFu) +#define EXT_ADDR_3_EXT_ADDR_3_MASK (0x0000FFFFu) +#define EXT_ADDR_3_EXT_ADDR_3_BIT (0) +#define EXT_ADDR_3_EXT_ADDR_3_BITS (16) #define MAC_STATE *((volatile uint32_t *)0x400020A8u) #define MAC_STATE_REG *((volatile uint32_t *)0x400020A8u) #define MAC_STATE_ADDR (0x400020A8u) #define MAC_STATE_RESET (0x00000000u) - /* SPY_STATE field */ - #define MAC_STATE_SPY_STATE (0x00000700u) - #define MAC_STATE_SPY_STATE_MASK (0x00000700u) - #define MAC_STATE_SPY_STATE_BIT (8) - #define MAC_STATE_SPY_STATE_BITS (3) - /* ACK_STATE field */ - #define MAC_STATE_ACK_STATE (0x000000C0u) - #define MAC_STATE_ACK_STATE_MASK (0x000000C0u) - #define MAC_STATE_ACK_STATE_BIT (6) - #define MAC_STATE_ACK_STATE_BITS (2) - /* BO_STATE field */ - #define MAC_STATE_BO_STATE (0x0000003Cu) - #define MAC_STATE_BO_STATE_MASK (0x0000003Cu) - #define MAC_STATE_BO_STATE_BIT (2) - #define MAC_STATE_BO_STATE_BITS (4) - /* TOP_STATE field */ - #define MAC_STATE_TOP_STATE (0x00000003u) - #define MAC_STATE_TOP_STATE_MASK (0x00000003u) - #define MAC_STATE_TOP_STATE_BIT (0) - #define MAC_STATE_TOP_STATE_BITS (2) +/* SPY_STATE field */ +#define MAC_STATE_SPY_STATE (0x00000700u) +#define MAC_STATE_SPY_STATE_MASK (0x00000700u) +#define MAC_STATE_SPY_STATE_BIT (8) +#define MAC_STATE_SPY_STATE_BITS (3) +/* ACK_STATE field */ +#define MAC_STATE_ACK_STATE (0x000000C0u) +#define MAC_STATE_ACK_STATE_MASK (0x000000C0u) +#define MAC_STATE_ACK_STATE_BIT (6) +#define MAC_STATE_ACK_STATE_BITS (2) +/* BO_STATE field */ +#define MAC_STATE_BO_STATE (0x0000003Cu) +#define MAC_STATE_BO_STATE_MASK (0x0000003Cu) +#define MAC_STATE_BO_STATE_BIT (2) +#define MAC_STATE_BO_STATE_BITS (4) +/* TOP_STATE field */ +#define MAC_STATE_TOP_STATE (0x00000003u) +#define MAC_STATE_TOP_STATE_MASK (0x00000003u) +#define MAC_STATE_TOP_STATE_BIT (0) +#define MAC_STATE_TOP_STATE_BITS (2) #define RX_STATE *((volatile uint32_t *)0x400020ACu) #define RX_STATE_REG *((volatile uint32_t *)0x400020ACu) #define RX_STATE_ADDR (0x400020ACu) #define RX_STATE_RESET (0x00000000u) - /* RX_BUFFER_STATE field */ - #define RX_STATE_RX_BUFFER_STATE (0x000001E0u) - #define RX_STATE_RX_BUFFER_STATE_MASK (0x000001E0u) - #define RX_STATE_RX_BUFFER_STATE_BIT (5) - #define RX_STATE_RX_BUFFER_STATE_BITS (4) - /* RX_TOP_STATE field */ - #define RX_STATE_RX_TOP_STATE (0x0000001Fu) - #define RX_STATE_RX_TOP_STATE_MASK (0x0000001Fu) - #define RX_STATE_RX_TOP_STATE_BIT (0) - #define RX_STATE_RX_TOP_STATE_BITS (5) +/* RX_BUFFER_STATE field */ +#define RX_STATE_RX_BUFFER_STATE (0x000001E0u) +#define RX_STATE_RX_BUFFER_STATE_MASK (0x000001E0u) +#define RX_STATE_RX_BUFFER_STATE_BIT (5) +#define RX_STATE_RX_BUFFER_STATE_BITS (4) +/* RX_TOP_STATE field */ +#define RX_STATE_RX_TOP_STATE (0x0000001Fu) +#define RX_STATE_RX_TOP_STATE_MASK (0x0000001Fu) +#define RX_STATE_RX_TOP_STATE_BIT (0) +#define RX_STATE_RX_TOP_STATE_BITS (5) #define TX_STATE *((volatile uint32_t *)0x400020B0u) #define TX_STATE_REG *((volatile uint32_t *)0x400020B0u) #define TX_STATE_ADDR (0x400020B0u) #define TX_STATE_RESET (0x00000000u) - /* TX_BUFFER_STATE field */ - #define TX_STATE_TX_BUFFER_STATE (0x000000F0u) - #define TX_STATE_TX_BUFFER_STATE_MASK (0x000000F0u) - #define TX_STATE_TX_BUFFER_STATE_BIT (4) - #define TX_STATE_TX_BUFFER_STATE_BITS (4) - /* TX_TOP_STATE field */ - #define TX_STATE_TX_TOP_STATE (0x0000000Fu) - #define TX_STATE_TX_TOP_STATE_MASK (0x0000000Fu) - #define TX_STATE_TX_TOP_STATE_BIT (0) - #define TX_STATE_TX_TOP_STATE_BITS (4) +/* TX_BUFFER_STATE field */ +#define TX_STATE_TX_BUFFER_STATE (0x000000F0u) +#define TX_STATE_TX_BUFFER_STATE_MASK (0x000000F0u) +#define TX_STATE_TX_BUFFER_STATE_BIT (4) +#define TX_STATE_TX_BUFFER_STATE_BITS (4) +/* TX_TOP_STATE field */ +#define TX_STATE_TX_TOP_STATE (0x0000000Fu) +#define TX_STATE_TX_TOP_STATE_MASK (0x0000000Fu) +#define TX_STATE_TX_TOP_STATE_BIT (0) +#define TX_STATE_TX_TOP_STATE_BITS (4) #define DMA_STATE *((volatile uint32_t *)0x400020B4u) #define DMA_STATE_REG *((volatile uint32_t *)0x400020B4u) #define DMA_STATE_ADDR (0x400020B4u) #define DMA_STATE_RESET (0x00000000u) - /* DMA_RX_STATE field */ - #define DMA_STATE_DMA_RX_STATE (0x00000038u) - #define DMA_STATE_DMA_RX_STATE_MASK (0x00000038u) - #define DMA_STATE_DMA_RX_STATE_BIT (3) - #define DMA_STATE_DMA_RX_STATE_BITS (3) - /* DMA_TX_STATE field */ - #define DMA_STATE_DMA_TX_STATE (0x00000007u) - #define DMA_STATE_DMA_TX_STATE_MASK (0x00000007u) - #define DMA_STATE_DMA_TX_STATE_BIT (0) - #define DMA_STATE_DMA_TX_STATE_BITS (3) +/* DMA_RX_STATE field */ +#define DMA_STATE_DMA_RX_STATE (0x00000038u) +#define DMA_STATE_DMA_RX_STATE_MASK (0x00000038u) +#define DMA_STATE_DMA_RX_STATE_BIT (3) +#define DMA_STATE_DMA_RX_STATE_BITS (3) +/* DMA_TX_STATE field */ +#define DMA_STATE_DMA_TX_STATE (0x00000007u) +#define DMA_STATE_DMA_TX_STATE_MASK (0x00000007u) +#define DMA_STATE_DMA_TX_STATE_BIT (0) +#define DMA_STATE_DMA_TX_STATE_BITS (3) #define MAC_DEBUG *((volatile uint32_t *)0x400020B8u) #define MAC_DEBUG_REG *((volatile uint32_t *)0x400020B8u) #define MAC_DEBUG_ADDR (0x400020B8u) #define MAC_DEBUG_RESET (0x00000000u) - /* SW_DEBUG_OUT field */ - #define MAC_DEBUG_SW_DEBUG_OUT (0x00000060u) - #define MAC_DEBUG_SW_DEBUG_OUT_MASK (0x00000060u) - #define MAC_DEBUG_SW_DEBUG_OUT_BIT (5) - #define MAC_DEBUG_SW_DEBUG_OUT_BITS (2) - /* MAC_DEBUG_MUX field */ - #define MAC_DEBUG_MAC_DEBUG_MUX (0x0000001Fu) - #define MAC_DEBUG_MAC_DEBUG_MUX_MASK (0x0000001Fu) - #define MAC_DEBUG_MAC_DEBUG_MUX_BIT (0) - #define MAC_DEBUG_MAC_DEBUG_MUX_BITS (5) +/* SW_DEBUG_OUT field */ +#define MAC_DEBUG_SW_DEBUG_OUT (0x00000060u) +#define MAC_DEBUG_SW_DEBUG_OUT_MASK (0x00000060u) +#define MAC_DEBUG_SW_DEBUG_OUT_BIT (5) +#define MAC_DEBUG_SW_DEBUG_OUT_BITS (2) +/* MAC_DEBUG_MUX field */ +#define MAC_DEBUG_MAC_DEBUG_MUX (0x0000001Fu) +#define MAC_DEBUG_MAC_DEBUG_MUX_MASK (0x0000001Fu) +#define MAC_DEBUG_MAC_DEBUG_MUX_BIT (0) +#define MAC_DEBUG_MAC_DEBUG_MUX_BITS (5) #define MAC_DEBUG_VIEW *((volatile uint32_t *)0x400020BCu) #define MAC_DEBUG_VIEW_REG *((volatile uint32_t *)0x400020BCu) #define MAC_DEBUG_VIEW_ADDR (0x400020BCu) #define MAC_DEBUG_VIEW_RESET (0x00000010u) - /* MAC_DEBUG_VIEW field */ - #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW (0x0000FFFFu) - #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_MASK (0x0000FFFFu) - #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT (0) - #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS (16) +/* MAC_DEBUG_VIEW field */ +#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW (0x0000FFFFu) +#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_MASK (0x0000FFFFu) +#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT (0) +#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS (16) #define MAC_RSSI_DELAY *((volatile uint32_t *)0x400020C0u) #define MAC_RSSI_DELAY_REG *((volatile uint32_t *)0x400020C0u) #define MAC_RSSI_DELAY_ADDR (0x400020C0u) #define MAC_RSSI_DELAY_RESET (0x00000000u) - /* RSSI_INST_DELAY_OK field */ - #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK (0x00000FC0u) - #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_MASK (0x00000FC0u) - #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BIT (6) - #define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BITS (6) - /* RSSI_INST_DELAY field */ - #define MAC_RSSI_DELAY_RSSI_INST_DELAY (0x0000003Fu) - #define MAC_RSSI_DELAY_RSSI_INST_DELAY_MASK (0x0000003Fu) - #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT (0) - #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS (6) +/* RSSI_INST_DELAY_OK field */ +#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK (0x00000FC0u) +#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_MASK (0x00000FC0u) +#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BIT (6) +#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BITS (6) +/* RSSI_INST_DELAY field */ +#define MAC_RSSI_DELAY_RSSI_INST_DELAY (0x0000003Fu) +#define MAC_RSSI_DELAY_RSSI_INST_DELAY_MASK (0x0000003Fu) +#define MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT (0) +#define MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS (6) #define PANID_COUNT *((volatile uint32_t *)0x400020C4u) #define PANID_COUNT_REG *((volatile uint32_t *)0x400020C4u) #define PANID_COUNT_ADDR (0x400020C4u) #define PANID_COUNT_RESET (0x00000000u) - /* PANID_COUNT field */ - #define PANID_COUNT_PANID_COUNT (0x0000FFFFu) - #define PANID_COUNT_PANID_COUNT_MASK (0x0000FFFFu) - #define PANID_COUNT_PANID_COUNT_BIT (0) - #define PANID_COUNT_PANID_COUNT_BITS (16) +/* PANID_COUNT field */ +#define PANID_COUNT_PANID_COUNT (0x0000FFFFu) +#define PANID_COUNT_PANID_COUNT_MASK (0x0000FFFFu) +#define PANID_COUNT_PANID_COUNT_BIT (0) +#define PANID_COUNT_PANID_COUNT_BITS (16) #define NONPAN_COUNT *((volatile uint32_t *)0x400020C8u) #define NONPAN_COUNT_REG *((volatile uint32_t *)0x400020C8u) #define NONPAN_COUNT_ADDR (0x400020C8u) #define NONPAN_COUNT_RESET (0x00000000u) - /* NONPAN_COUNT field */ - #define NONPAN_COUNT_NONPAN_COUNT (0x0000FFFFu) - #define NONPAN_COUNT_NONPAN_COUNT_MASK (0x0000FFFFu) - #define NONPAN_COUNT_NONPAN_COUNT_BIT (0) - #define NONPAN_COUNT_NONPAN_COUNT_BITS (16) +/* NONPAN_COUNT field */ +#define NONPAN_COUNT_NONPAN_COUNT (0x0000FFFFu) +#define NONPAN_COUNT_NONPAN_COUNT_MASK (0x0000FFFFu) +#define NONPAN_COUNT_NONPAN_COUNT_BIT (0) +#define NONPAN_COUNT_NONPAN_COUNT_BITS (16) /* SECURITY block */ #define DATA_SECURITY_BASE (0x40003000u) @@ -2314,156 +2314,156 @@ #define SECURITY_CONFIG_REG *((volatile uint32_t *)0x40003000u) #define SECURITY_CONFIG_ADDR (0x40003000u) #define SECURITY_CONFIG_RESET (0x00000000u) - /* SEC_RST field */ - #define SECURITY_CONFIG_SEC_RST (0x00000080u) - #define SECURITY_CONFIG_SEC_RST_MASK (0x00000080u) - #define SECURITY_CONFIG_SEC_RST_BIT (7) - #define SECURITY_CONFIG_SEC_RST_BITS (1) - /* CTR_IN field */ - #define SECURITY_CONFIG_CTR_IN (0x00000040u) - #define SECURITY_CONFIG_CTR_IN_MASK (0x00000040u) - #define SECURITY_CONFIG_CTR_IN_BIT (6) - #define SECURITY_CONFIG_CTR_IN_BITS (1) - /* MIC_XOR_CT field */ - #define SECURITY_CONFIG_MIC_XOR_CT (0x00000020u) - #define SECURITY_CONFIG_MIC_XOR_CT_MASK (0x00000020u) - #define SECURITY_CONFIG_MIC_XOR_CT_BIT (5) - #define SECURITY_CONFIG_MIC_XOR_CT_BITS (1) - /* CBC_XOR_PT field */ - #define SECURITY_CONFIG_CBC_XOR_PT (0x00000010u) - #define SECURITY_CONFIG_CBC_XOR_PT_MASK (0x00000010u) - #define SECURITY_CONFIG_CBC_XOR_PT_BIT (4) - #define SECURITY_CONFIG_CBC_XOR_PT_BITS (1) - /* CT_TO_CBC_ST field */ - #define SECURITY_CONFIG_CT_TO_CBC_ST (0x00000008u) - #define SECURITY_CONFIG_CT_TO_CBC_ST_MASK (0x00000008u) - #define SECURITY_CONFIG_CT_TO_CBC_ST_BIT (3) - #define SECURITY_CONFIG_CT_TO_CBC_ST_BITS (1) - /* WAIT_CT_READ field */ - #define SECURITY_CONFIG_WAIT_CT_READ (0x00000004u) - #define SECURITY_CONFIG_WAIT_CT_READ_MASK (0x00000004u) - #define SECURITY_CONFIG_WAIT_CT_READ_BIT (2) - #define SECURITY_CONFIG_WAIT_CT_READ_BITS (1) - /* WAIT_PT_WRITE field */ - #define SECURITY_CONFIG_WAIT_PT_WRITE (0x00000002u) - #define SECURITY_CONFIG_WAIT_PT_WRITE_MASK (0x00000002u) - #define SECURITY_CONFIG_WAIT_PT_WRITE_BIT (1) - #define SECURITY_CONFIG_WAIT_PT_WRITE_BITS (1) - /* START_AES field */ - #define SECURITY_CONFIG_START_AES (0x00000001u) - #define SECURITY_CONFIG_START_AES_MASK (0x00000001u) - #define SECURITY_CONFIG_START_AES_BIT (0) - #define SECURITY_CONFIG_START_AES_BITS (1) +/* SEC_RST field */ +#define SECURITY_CONFIG_SEC_RST (0x00000080u) +#define SECURITY_CONFIG_SEC_RST_MASK (0x00000080u) +#define SECURITY_CONFIG_SEC_RST_BIT (7) +#define SECURITY_CONFIG_SEC_RST_BITS (1) +/* CTR_IN field */ +#define SECURITY_CONFIG_CTR_IN (0x00000040u) +#define SECURITY_CONFIG_CTR_IN_MASK (0x00000040u) +#define SECURITY_CONFIG_CTR_IN_BIT (6) +#define SECURITY_CONFIG_CTR_IN_BITS (1) +/* MIC_XOR_CT field */ +#define SECURITY_CONFIG_MIC_XOR_CT (0x00000020u) +#define SECURITY_CONFIG_MIC_XOR_CT_MASK (0x00000020u) +#define SECURITY_CONFIG_MIC_XOR_CT_BIT (5) +#define SECURITY_CONFIG_MIC_XOR_CT_BITS (1) +/* CBC_XOR_PT field */ +#define SECURITY_CONFIG_CBC_XOR_PT (0x00000010u) +#define SECURITY_CONFIG_CBC_XOR_PT_MASK (0x00000010u) +#define SECURITY_CONFIG_CBC_XOR_PT_BIT (4) +#define SECURITY_CONFIG_CBC_XOR_PT_BITS (1) +/* CT_TO_CBC_ST field */ +#define SECURITY_CONFIG_CT_TO_CBC_ST (0x00000008u) +#define SECURITY_CONFIG_CT_TO_CBC_ST_MASK (0x00000008u) +#define SECURITY_CONFIG_CT_TO_CBC_ST_BIT (3) +#define SECURITY_CONFIG_CT_TO_CBC_ST_BITS (1) +/* WAIT_CT_READ field */ +#define SECURITY_CONFIG_WAIT_CT_READ (0x00000004u) +#define SECURITY_CONFIG_WAIT_CT_READ_MASK (0x00000004u) +#define SECURITY_CONFIG_WAIT_CT_READ_BIT (2) +#define SECURITY_CONFIG_WAIT_CT_READ_BITS (1) +/* WAIT_PT_WRITE field */ +#define SECURITY_CONFIG_WAIT_PT_WRITE (0x00000002u) +#define SECURITY_CONFIG_WAIT_PT_WRITE_MASK (0x00000002u) +#define SECURITY_CONFIG_WAIT_PT_WRITE_BIT (1) +#define SECURITY_CONFIG_WAIT_PT_WRITE_BITS (1) +/* START_AES field */ +#define SECURITY_CONFIG_START_AES (0x00000001u) +#define SECURITY_CONFIG_START_AES_MASK (0x00000001u) +#define SECURITY_CONFIG_START_AES_BIT (0) +#define SECURITY_CONFIG_START_AES_BITS (1) #define SECURITY_STATUS *((volatile uint32_t *)0x40003004u) #define SECURITY_STATUS_REG *((volatile uint32_t *)0x40003004u) #define SECURITY_STATUS_ADDR (0x40003004u) #define SECURITY_STATUS_RESET (0x00000000u) - /* SEC_BUSY field */ - #define SECURITY_STATUS_SEC_BUSY (0x00000001u) - #define SECURITY_STATUS_SEC_BUSY_MASK (0x00000001u) - #define SECURITY_STATUS_SEC_BUSY_BIT (0) - #define SECURITY_STATUS_SEC_BUSY_BITS (1) +/* SEC_BUSY field */ +#define SECURITY_STATUS_SEC_BUSY (0x00000001u) +#define SECURITY_STATUS_SEC_BUSY_MASK (0x00000001u) +#define SECURITY_STATUS_SEC_BUSY_BIT (0) +#define SECURITY_STATUS_SEC_BUSY_BITS (1) #define CBC_STATE_0 *((volatile uint32_t *)0x40003008u) #define CBC_STATE_0_REG *((volatile uint32_t *)0x40003008u) #define CBC_STATE_0_ADDR (0x40003008u) #define CBC_STATE_0_RESET (0x00000000u) - /* CBC_STATE field */ - #define CBC_STATE_0_CBC_STATE (0xFFFFFFFFu) - #define CBC_STATE_0_CBC_STATE_MASK (0xFFFFFFFFu) - #define CBC_STATE_0_CBC_STATE_BIT (0) - #define CBC_STATE_0_CBC_STATE_BITS (32) +/* CBC_STATE field */ +#define CBC_STATE_0_CBC_STATE (0xFFFFFFFFu) +#define CBC_STATE_0_CBC_STATE_MASK (0xFFFFFFFFu) +#define CBC_STATE_0_CBC_STATE_BIT (0) +#define CBC_STATE_0_CBC_STATE_BITS (32) #define CBC_STATE_1 *((volatile uint32_t *)0x4000300Cu) #define CBC_STATE_1_REG *((volatile uint32_t *)0x4000300Cu) #define CBC_STATE_1_ADDR (0x4000300Cu) #define CBC_STATE_1_RESET (0x00000000u) - /* CBC_STATE_1 field */ - #define CBC_STATE_1_CBC_STATE_1 (0xFFFFFFFFu) - #define CBC_STATE_1_CBC_STATE_1_MASK (0xFFFFFFFFu) - #define CBC_STATE_1_CBC_STATE_1_BIT (0) - #define CBC_STATE_1_CBC_STATE_1_BITS (32) +/* CBC_STATE_1 field */ +#define CBC_STATE_1_CBC_STATE_1 (0xFFFFFFFFu) +#define CBC_STATE_1_CBC_STATE_1_MASK (0xFFFFFFFFu) +#define CBC_STATE_1_CBC_STATE_1_BIT (0) +#define CBC_STATE_1_CBC_STATE_1_BITS (32) #define CBC_STATE_2 *((volatile uint32_t *)0x40003010u) #define CBC_STATE_2_REG *((volatile uint32_t *)0x40003010u) #define CBC_STATE_2_ADDR (0x40003010u) #define CBC_STATE_2_RESET (0x00000000u) - /* CBC_STATE_2 field */ - #define CBC_STATE_2_CBC_STATE_2 (0xFFFFFFFFu) - #define CBC_STATE_2_CBC_STATE_2_MASK (0xFFFFFFFFu) - #define CBC_STATE_2_CBC_STATE_2_BIT (0) - #define CBC_STATE_2_CBC_STATE_2_BITS (32) +/* CBC_STATE_2 field */ +#define CBC_STATE_2_CBC_STATE_2 (0xFFFFFFFFu) +#define CBC_STATE_2_CBC_STATE_2_MASK (0xFFFFFFFFu) +#define CBC_STATE_2_CBC_STATE_2_BIT (0) +#define CBC_STATE_2_CBC_STATE_2_BITS (32) #define CBC_STATE_3 *((volatile uint32_t *)0x40003014u) #define CBC_STATE_3_REG *((volatile uint32_t *)0x40003014u) #define CBC_STATE_3_ADDR (0x40003014u) #define CBC_STATE_3_RESET (0x00000000u) - /* CBC_STATE_3 field */ - #define CBC_STATE_3_CBC_STATE_3 (0xFFFFFFFFu) - #define CBC_STATE_3_CBC_STATE_3_MASK (0xFFFFFFFFu) - #define CBC_STATE_3_CBC_STATE_3_BIT (0) - #define CBC_STATE_3_CBC_STATE_3_BITS (32) +/* CBC_STATE_3 field */ +#define CBC_STATE_3_CBC_STATE_3 (0xFFFFFFFFu) +#define CBC_STATE_3_CBC_STATE_3_MASK (0xFFFFFFFFu) +#define CBC_STATE_3_CBC_STATE_3_BIT (0) +#define CBC_STATE_3_CBC_STATE_3_BITS (32) #define PT *((volatile uint32_t *)0x40003028u) #define PT_REG *((volatile uint32_t *)0x40003028u) #define PT_ADDR (0x40003028u) #define PT_RESET (0x00000000u) - /* PT field */ - #define PT_PT (0xFFFFFFFFu) - #define PT_PT_MASK (0xFFFFFFFFu) - #define PT_PT_BIT (0) - #define PT_PT_BITS (32) +/* PT field */ +#define PT_PT (0xFFFFFFFFu) +#define PT_PT_MASK (0xFFFFFFFFu) +#define PT_PT_BIT (0) +#define PT_PT_BITS (32) #define CT *((volatile uint32_t *)0x40003030u) #define CT_REG *((volatile uint32_t *)0x40003030u) #define CT_ADDR (0x40003030u) #define CT_RESET (0x00000000u) - /* CT field */ - #define CT_CT (0xFFFFFFFFu) - #define CT_CT_MASK (0xFFFFFFFFu) - #define CT_CT_BIT (0) - #define CT_CT_BITS (32) +/* CT field */ +#define CT_CT (0xFFFFFFFFu) +#define CT_CT_MASK (0xFFFFFFFFu) +#define CT_CT_BIT (0) +#define CT_CT_BITS (32) #define KEY_0 *((volatile uint32_t *)0x40003038u) #define KEY_0_REG *((volatile uint32_t *)0x40003038u) #define KEY_0_ADDR (0x40003038u) #define KEY_0_RESET (0x00000000u) - /* KEY_O field */ - #define KEY_0_KEY_O (0xFFFFFFFFu) - #define KEY_0_KEY_O_MASK (0xFFFFFFFFu) - #define KEY_0_KEY_O_BIT (0) - #define KEY_0_KEY_O_BITS (32) +/* KEY_O field */ +#define KEY_0_KEY_O (0xFFFFFFFFu) +#define KEY_0_KEY_O_MASK (0xFFFFFFFFu) +#define KEY_0_KEY_O_BIT (0) +#define KEY_0_KEY_O_BITS (32) #define KEY_1 *((volatile uint32_t *)0x4000303Cu) #define KEY_1_REG *((volatile uint32_t *)0x4000303Cu) #define KEY_1_ADDR (0x4000303Cu) #define KEY_1_RESET (0x00000000u) - /* KEY_1 field */ - #define KEY_1_KEY_1 (0xFFFFFFFFu) - #define KEY_1_KEY_1_MASK (0xFFFFFFFFu) - #define KEY_1_KEY_1_BIT (0) - #define KEY_1_KEY_1_BITS (32) +/* KEY_1 field */ +#define KEY_1_KEY_1 (0xFFFFFFFFu) +#define KEY_1_KEY_1_MASK (0xFFFFFFFFu) +#define KEY_1_KEY_1_BIT (0) +#define KEY_1_KEY_1_BITS (32) #define KEY_2 *((volatile uint32_t *)0x40003040u) #define KEY_2_REG *((volatile uint32_t *)0x40003040u) #define KEY_2_ADDR (0x40003040u) #define KEY_2_RESET (0x00000000u) - /* KEY_2 field */ - #define KEY_2_KEY_2 (0xFFFFFFFFu) - #define KEY_2_KEY_2_MASK (0xFFFFFFFFu) - #define KEY_2_KEY_2_BIT (0) - #define KEY_2_KEY_2_BITS (32) +/* KEY_2 field */ +#define KEY_2_KEY_2 (0xFFFFFFFFu) +#define KEY_2_KEY_2_MASK (0xFFFFFFFFu) +#define KEY_2_KEY_2_BIT (0) +#define KEY_2_KEY_2_BITS (32) #define KEY_3 *((volatile uint32_t *)0x40003044u) #define KEY_3_REG *((volatile uint32_t *)0x40003044u) #define KEY_3_ADDR (0x40003044u) #define KEY_3_RESET (0x00000000u) - /* KEY_3 field */ - #define KEY_3_KEY_3 (0xFFFFFFFFu) - #define KEY_3_KEY_3_MASK (0xFFFFFFFFu) - #define KEY_3_KEY_3_BIT (0) - #define KEY_3_KEY_3_BITS (32) +/* KEY_3 field */ +#define KEY_3_KEY_3 (0xFFFFFFFFu) +#define KEY_3_KEY_3_MASK (0xFFFFFFFFu) +#define KEY_3_KEY_3_BIT (0) +#define KEY_3_KEY_3_BITS (32) /* CM_LV block */ #define BLOCK_CM_LV_BASE (0x40004000u) @@ -2474,196 +2474,196 @@ #define SILICON_ID_REG *((volatile uint32_t *)0x40004000u) #define SILICON_ID_ADDR (0x40004000u) #define SILICON_ID_RESET (0x069A862Bu) - /* HW_VERSION field */ - #define SILICON_ID_HW_VERSION (0xF0000000u) - #define SILICON_ID_HW_VERSION_MASK (0xF0000000u) - #define SILICON_ID_HW_VERSION_BIT (28) - #define SILICON_ID_HW_VERSION_BITS (4) - /* ST_DIVISION field */ - #define SILICON_ID_ST_DIVISION (0x0F000000u) - #define SILICON_ID_ST_DIVISION_MASK (0x0F000000u) - #define SILICON_ID_ST_DIVISION_BIT (24) - #define SILICON_ID_ST_DIVISION_BITS (4) - /* CHIP_TYPE field */ - #define SILICON_ID_CHIP_TYPE (0x00FF8000u) - #define SILICON_ID_CHIP_TYPE_MASK (0x00FF8000u) - #define SILICON_ID_CHIP_TYPE_BIT (15) - #define SILICON_ID_CHIP_TYPE_BITS (9) - /* SUB_TYPE field */ - #define SILICON_ID_SUB_TYPE (0x00007000u) - #define SILICON_ID_SUB_TYPE_MASK (0x00007000u) - #define SILICON_ID_SUB_TYPE_BIT (12) - #define SILICON_ID_SUB_TYPE_BITS (3) - /* JEDEC_MAN_ID field */ - #define SILICON_ID_JEDEC_MAN_ID (0x00000FFEu) - #define SILICON_ID_JEDEC_MAN_ID_MASK (0x00000FFEu) - #define SILICON_ID_JEDEC_MAN_ID_BIT (1) - #define SILICON_ID_JEDEC_MAN_ID_BITS (11) - /* ONE field */ - #define SILICON_ID_ONE (0x00000001u) - #define SILICON_ID_ONE_MASK (0x00000001u) - #define SILICON_ID_ONE_BIT (0) - #define SILICON_ID_ONE_BITS (1) +/* HW_VERSION field */ +#define SILICON_ID_HW_VERSION (0xF0000000u) +#define SILICON_ID_HW_VERSION_MASK (0xF0000000u) +#define SILICON_ID_HW_VERSION_BIT (28) +#define SILICON_ID_HW_VERSION_BITS (4) +/* ST_DIVISION field */ +#define SILICON_ID_ST_DIVISION (0x0F000000u) +#define SILICON_ID_ST_DIVISION_MASK (0x0F000000u) +#define SILICON_ID_ST_DIVISION_BIT (24) +#define SILICON_ID_ST_DIVISION_BITS (4) +/* CHIP_TYPE field */ +#define SILICON_ID_CHIP_TYPE (0x00FF8000u) +#define SILICON_ID_CHIP_TYPE_MASK (0x00FF8000u) +#define SILICON_ID_CHIP_TYPE_BIT (15) +#define SILICON_ID_CHIP_TYPE_BITS (9) +/* SUB_TYPE field */ +#define SILICON_ID_SUB_TYPE (0x00007000u) +#define SILICON_ID_SUB_TYPE_MASK (0x00007000u) +#define SILICON_ID_SUB_TYPE_BIT (12) +#define SILICON_ID_SUB_TYPE_BITS (3) +/* JEDEC_MAN_ID field */ +#define SILICON_ID_JEDEC_MAN_ID (0x00000FFEu) +#define SILICON_ID_JEDEC_MAN_ID_MASK (0x00000FFEu) +#define SILICON_ID_JEDEC_MAN_ID_BIT (1) +#define SILICON_ID_JEDEC_MAN_ID_BITS (11) +/* ONE field */ +#define SILICON_ID_ONE (0x00000001u) +#define SILICON_ID_ONE_MASK (0x00000001u) +#define SILICON_ID_ONE_BIT (0) +#define SILICON_ID_ONE_BITS (1) #define OSC24M_BIASTRIM *((volatile uint32_t *)0x40004004u) #define OSC24M_BIASTRIM_REG *((volatile uint32_t *)0x40004004u) #define OSC24M_BIASTRIM_ADDR (0x40004004u) #define OSC24M_BIASTRIM_RESET (0x0000000Fu) - /* OSC24M_BIAS_TRIM field */ - #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM (0x0000000Fu) - #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK (0x0000000Fu) - #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT (0) - #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS (4) +/* OSC24M_BIAS_TRIM field */ +#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM (0x0000000Fu) +#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK (0x0000000Fu) +#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT (0) +#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS (4) #define OSCHF_TUNE *((volatile uint32_t *)0x40004008u) #define OSCHF_TUNE_REG *((volatile uint32_t *)0x40004008u) #define OSCHF_TUNE_ADDR (0x40004008u) #define OSCHF_TUNE_RESET (0x00000017u) - /* OSCHF_TUNE_FIELD field */ - #define OSCHF_TUNE_FIELD (0x0000001Fu) - #define OSCHF_TUNE_FIELD_MASK (0x0000001Fu) - #define OSCHF_TUNE_FIELD_BIT (0) - #define OSCHF_TUNE_FIELD_BITS (5) +/* OSCHF_TUNE_FIELD field */ +#define OSCHF_TUNE_FIELD (0x0000001Fu) +#define OSCHF_TUNE_FIELD_MASK (0x0000001Fu) +#define OSCHF_TUNE_FIELD_BIT (0) +#define OSCHF_TUNE_FIELD_BITS (5) #define OSC24M_COMP *((volatile uint32_t *)0x4000400Cu) #define OSC24M_COMP_REG *((volatile uint32_t *)0x4000400Cu) #define OSC24M_COMP_ADDR (0x4000400Cu) #define OSC24M_COMP_RESET (0x00000000u) - /* OSC24M_HI field */ - #define OSC24M_HI (0x00000002u) - #define OSC24M_HI_MASK (0x00000002u) - #define OSC24M_HI_BIT (1) - #define OSC24M_HI_BITS (1) - /* OSC24M_LO field */ - #define OSC24M_LO (0x00000001u) - #define OSC24M_LO_MASK (0x00000001u) - #define OSC24M_LO_BIT (0) - #define OSC24M_LO_BITS (1) +/* OSC24M_HI field */ +#define OSC24M_HI (0x00000002u) +#define OSC24M_HI_MASK (0x00000002u) +#define OSC24M_HI_BIT (1) +#define OSC24M_HI_BITS (1) +/* OSC24M_LO field */ +#define OSC24M_LO (0x00000001u) +#define OSC24M_LO_MASK (0x00000001u) +#define OSC24M_LO_BIT (0) +#define OSC24M_LO_BITS (1) #define CLK_PERIODMODE *((volatile uint32_t *)0x40004010u) #define CLK_PERIODMODE_REG *((volatile uint32_t *)0x40004010u) #define CLK_PERIODMODE_ADDR (0x40004010u) #define CLK_PERIODMODE_RESET (0x00000000u) - /* CLK_PERIODMODE_FIELD field */ - #define CLK_PERIODMODE_FIELD (0x00000003u) - #define CLK_PERIODMODE_FIELD_MASK (0x00000003u) - #define CLK_PERIODMODE_FIELD_BIT (0) - #define CLK_PERIODMODE_FIELD_BITS (2) +/* CLK_PERIODMODE_FIELD field */ +#define CLK_PERIODMODE_FIELD (0x00000003u) +#define CLK_PERIODMODE_FIELD_MASK (0x00000003u) +#define CLK_PERIODMODE_FIELD_BIT (0) +#define CLK_PERIODMODE_FIELD_BITS (2) #define CLK_PERIOD *((volatile uint32_t *)0x40004014u) #define CLK_PERIOD_REG *((volatile uint32_t *)0x40004014u) #define CLK_PERIOD_ADDR (0x40004014u) #define CLK_PERIOD_RESET (0x00000000u) - /* CLK_PERIOD_FIELD field */ - #define CLK_PERIOD_FIELD (0x0000FFFFu) - #define CLK_PERIOD_FIELD_MASK (0x0000FFFFu) - #define CLK_PERIOD_FIELD_BIT (0) - #define CLK_PERIOD_FIELD_BITS (16) +/* CLK_PERIOD_FIELD field */ +#define CLK_PERIOD_FIELD (0x0000FFFFu) +#define CLK_PERIOD_FIELD_MASK (0x0000FFFFu) +#define CLK_PERIOD_FIELD_BIT (0) +#define CLK_PERIOD_FIELD_BITS (16) #define DITHER_DIS *((volatile uint32_t *)0x40004018u) #define DITHER_DIS_REG *((volatile uint32_t *)0x40004018u) #define DITHER_DIS_ADDR (0x40004018u) #define DITHER_DIS_RESET (0x00000000u) - /* DITHER_DIS field */ - #define DITHER_DIS_DITHER_DIS (0x00000001u) - #define DITHER_DIS_DITHER_DIS_MASK (0x00000001u) - #define DITHER_DIS_DITHER_DIS_BIT (0) - #define DITHER_DIS_DITHER_DIS_BITS (1) +/* DITHER_DIS field */ +#define DITHER_DIS_DITHER_DIS (0x00000001u) +#define DITHER_DIS_DITHER_DIS_MASK (0x00000001u) +#define DITHER_DIS_DITHER_DIS_BIT (0) +#define DITHER_DIS_DITHER_DIS_BITS (1) #define OSC24M_CTRL *((volatile uint32_t *)0x4000401Cu) #define OSC24M_CTRL_REG *((volatile uint32_t *)0x4000401Cu) #define OSC24M_CTRL_ADDR (0x4000401Cu) #define OSC24M_CTRL_RESET (0x00000000u) - /* OSC24M_EN field */ - #define OSC24M_CTRL_OSC24M_EN (0x00000002u) - #define OSC24M_CTRL_OSC24M_EN_MASK (0x00000002u) - #define OSC24M_CTRL_OSC24M_EN_BIT (1) - #define OSC24M_CTRL_OSC24M_EN_BITS (1) - /* OSC24M_SEL field */ - #define OSC24M_CTRL_OSC24M_SEL (0x00000001u) - #define OSC24M_CTRL_OSC24M_SEL_MASK (0x00000001u) - #define OSC24M_CTRL_OSC24M_SEL_BIT (0) - #define OSC24M_CTRL_OSC24M_SEL_BITS (1) +/* OSC24M_EN field */ +#define OSC24M_CTRL_OSC24M_EN (0x00000002u) +#define OSC24M_CTRL_OSC24M_EN_MASK (0x00000002u) +#define OSC24M_CTRL_OSC24M_EN_BIT (1) +#define OSC24M_CTRL_OSC24M_EN_BITS (1) +/* OSC24M_SEL field */ +#define OSC24M_CTRL_OSC24M_SEL (0x00000001u) +#define OSC24M_CTRL_OSC24M_SEL_MASK (0x00000001u) +#define OSC24M_CTRL_OSC24M_SEL_BIT (0) +#define OSC24M_CTRL_OSC24M_SEL_BITS (1) #define CPU_CLKSEL *((volatile uint32_t *)0x40004020u) #define CPU_CLKSEL_REG *((volatile uint32_t *)0x40004020u) #define CPU_CLKSEL_ADDR (0x40004020u) #define CPU_CLKSEL_RESET (0x00000000u) - /* CPU_CLKSEL_FIELD field */ - #define CPU_CLKSEL_FIELD (0x00000001u) - #define CPU_CLKSEL_FIELD_MASK (0x00000001u) - #define CPU_CLKSEL_FIELD_BIT (0) - #define CPU_CLKSEL_FIELD_BITS (1) +/* CPU_CLKSEL_FIELD field */ +#define CPU_CLKSEL_FIELD (0x00000001u) +#define CPU_CLKSEL_FIELD_MASK (0x00000001u) +#define CPU_CLKSEL_FIELD_BIT (0) +#define CPU_CLKSEL_FIELD_BITS (1) #define BUS_FAULT *((volatile uint32_t *)0x40004024u) #define BUS_FAULT_REG *((volatile uint32_t *)0x40004024u) #define BUS_FAULT_ADDR (0x40004024u) #define BUS_FAULT_RESET (0x00000000u) - /* WRONGSIZE field */ - #define BUS_FAULT_WRONGSIZE (0x00000008u) - #define BUS_FAULT_WRONGSIZE_MASK (0x00000008u) - #define BUS_FAULT_WRONGSIZE_BIT (3) - #define BUS_FAULT_WRONGSIZE_BITS (1) - /* PROTECTED field */ - #define BUS_FAULT_PROTECTED (0x00000004u) - #define BUS_FAULT_PROTECTED_MASK (0x00000004u) - #define BUS_FAULT_PROTECTED_BIT (2) - #define BUS_FAULT_PROTECTED_BITS (1) - /* RESERVED field */ - #define BUS_FAULT_RESERVED (0x00000002u) - #define BUS_FAULT_RESERVED_MASK (0x00000002u) - #define BUS_FAULT_RESERVED_BIT (1) - #define BUS_FAULT_RESERVED_BITS (1) - /* MISSED field */ - #define BUS_FAULT_MISSED (0x00000001u) - #define BUS_FAULT_MISSED_MASK (0x00000001u) - #define BUS_FAULT_MISSED_BIT (0) - #define BUS_FAULT_MISSED_BITS (1) +/* WRONGSIZE field */ +#define BUS_FAULT_WRONGSIZE (0x00000008u) +#define BUS_FAULT_WRONGSIZE_MASK (0x00000008u) +#define BUS_FAULT_WRONGSIZE_BIT (3) +#define BUS_FAULT_WRONGSIZE_BITS (1) +/* PROTECTED field */ +#define BUS_FAULT_PROTECTED (0x00000004u) +#define BUS_FAULT_PROTECTED_MASK (0x00000004u) +#define BUS_FAULT_PROTECTED_BIT (2) +#define BUS_FAULT_PROTECTED_BITS (1) +/* RESERVED field */ +#define BUS_FAULT_RESERVED (0x00000002u) +#define BUS_FAULT_RESERVED_MASK (0x00000002u) +#define BUS_FAULT_RESERVED_BIT (1) +#define BUS_FAULT_RESERVED_BITS (1) +/* MISSED field */ +#define BUS_FAULT_MISSED (0x00000001u) +#define BUS_FAULT_MISSED_MASK (0x00000001u) +#define BUS_FAULT_MISSED_BIT (0) +#define BUS_FAULT_MISSED_BITS (1) #define PCTRACE_SEL *((volatile uint32_t *)0x40004028u) #define PCTRACE_SEL_REG *((volatile uint32_t *)0x40004028u) #define PCTRACE_SEL_ADDR (0x40004028u) #define PCTRACE_SEL_RESET (0x00000000u) - /* PCTRACE_SEL_FIELD field */ - #define PCTRACE_SEL_FIELD (0x00000001u) - #define PCTRACE_SEL_FIELD_MASK (0x00000001u) - #define PCTRACE_SEL_FIELD_BIT (0) - #define PCTRACE_SEL_FIELD_BITS (1) +/* PCTRACE_SEL_FIELD field */ +#define PCTRACE_SEL_FIELD (0x00000001u) +#define PCTRACE_SEL_FIELD_MASK (0x00000001u) +#define PCTRACE_SEL_FIELD_BIT (0) +#define PCTRACE_SEL_FIELD_BITS (1) #define FPEC_CLKREQ *((volatile uint32_t *)0x4000402Cu) #define FPEC_CLKREQ_REG *((volatile uint32_t *)0x4000402Cu) #define FPEC_CLKREQ_ADDR (0x4000402Cu) #define FPEC_CLKREQ_RESET (0x00000000u) - /* FPEC_CLKREQ_FIELD field */ - #define FPEC_CLKREQ_FIELD (0x00000001u) - #define FPEC_CLKREQ_FIELD_MASK (0x00000001u) - #define FPEC_CLKREQ_FIELD_BIT (0) - #define FPEC_CLKREQ_FIELD_BITS (1) +/* FPEC_CLKREQ_FIELD field */ +#define FPEC_CLKREQ_FIELD (0x00000001u) +#define FPEC_CLKREQ_FIELD_MASK (0x00000001u) +#define FPEC_CLKREQ_FIELD_BIT (0) +#define FPEC_CLKREQ_FIELD_BITS (1) #define FPEC_CLKSTAT *((volatile uint32_t *)0x40004030u) #define FPEC_CLKSTAT_REG *((volatile uint32_t *)0x40004030u) #define FPEC_CLKSTAT_ADDR (0x40004030u) #define FPEC_CLKSTAT_RESET (0x00000000u) - /* FPEC_CLKBSY field */ - #define FPEC_CLKBSY (0x00000002u) - #define FPEC_CLKBSY_MASK (0x00000002u) - #define FPEC_CLKBSY_BIT (1) - #define FPEC_CLKBSY_BITS (1) - /* FPEC_CLKACK field */ - #define FPEC_CLKACK (0x00000001u) - #define FPEC_CLKACK_MASK (0x00000001u) - #define FPEC_CLKACK_BIT (0) - #define FPEC_CLKACK_BITS (1) +/* FPEC_CLKBSY field */ +#define FPEC_CLKBSY (0x00000002u) +#define FPEC_CLKBSY_MASK (0x00000002u) +#define FPEC_CLKBSY_BIT (1) +#define FPEC_CLKBSY_BITS (1) +/* FPEC_CLKACK field */ +#define FPEC_CLKACK (0x00000001u) +#define FPEC_CLKACK_MASK (0x00000001u) +#define FPEC_CLKACK_BIT (0) +#define FPEC_CLKACK_BITS (1) #define LV_SPARE *((volatile uint32_t *)0x40004034u) #define LV_SPARE_REG *((volatile uint32_t *)0x40004034u) #define LV_SPARE_ADDR (0x40004034u) #define LV_SPARE_RESET (0x00000000u) - /* LV_SPARE field */ - #define LV_SPARE_LV_SPARE (0x000000FFu) - #define LV_SPARE_LV_SPARE_MASK (0x000000FFu) - #define LV_SPARE_LV_SPARE_BIT (0) - #define LV_SPARE_LV_SPARE_BITS (8) +/* LV_SPARE field */ +#define LV_SPARE_LV_SPARE (0x000000FFu) +#define LV_SPARE_LV_SPARE_MASK (0x000000FFu) +#define LV_SPARE_LV_SPARE_BIT (0) +#define LV_SPARE_LV_SPARE_BITS (8) /* RAM_CTRL block */ #define DATA_RAM_CTRL_BASE (0x40005000u) @@ -2674,126 +2674,126 @@ #define MEM_PROT_0_REG *((volatile uint32_t *)0x40005000u) #define MEM_PROT_0_ADDR (0x40005000u) #define MEM_PROT_0_RESET (0x00000000u) - /* MEM_PROT_0 field */ - #define MEM_PROT_0_MEM_PROT_0 (0xFFFFFFFFu) - #define MEM_PROT_0_MEM_PROT_0_MASK (0xFFFFFFFFu) - #define MEM_PROT_0_MEM_PROT_0_BIT (0) - #define MEM_PROT_0_MEM_PROT_0_BITS (32) +/* MEM_PROT_0 field */ +#define MEM_PROT_0_MEM_PROT_0 (0xFFFFFFFFu) +#define MEM_PROT_0_MEM_PROT_0_MASK (0xFFFFFFFFu) +#define MEM_PROT_0_MEM_PROT_0_BIT (0) +#define MEM_PROT_0_MEM_PROT_0_BITS (32) #define MEM_PROT_1 *((volatile uint32_t *)0x40005004u) #define MEM_PROT_1_REG *((volatile uint32_t *)0x40005004u) #define MEM_PROT_1_ADDR (0x40005004u) #define MEM_PROT_1_RESET (0x00000000u) - /* MEM_PROT_1 field */ - #define MEM_PROT_1_MEM_PROT_1 (0xFFFFFFFFu) - #define MEM_PROT_1_MEM_PROT_1_MASK (0xFFFFFFFFu) - #define MEM_PROT_1_MEM_PROT_1_BIT (0) - #define MEM_PROT_1_MEM_PROT_1_BITS (32) +/* MEM_PROT_1 field */ +#define MEM_PROT_1_MEM_PROT_1 (0xFFFFFFFFu) +#define MEM_PROT_1_MEM_PROT_1_MASK (0xFFFFFFFFu) +#define MEM_PROT_1_MEM_PROT_1_BIT (0) +#define MEM_PROT_1_MEM_PROT_1_BITS (32) #define MEM_PROT_2 *((volatile uint32_t *)0x40005008u) #define MEM_PROT_2_REG *((volatile uint32_t *)0x40005008u) #define MEM_PROT_2_ADDR (0x40005008u) #define MEM_PROT_2_RESET (0x00000000u) - /* MEM_PROT_2 field */ - #define MEM_PROT_2_MEM_PROT_2 (0xFFFFFFFFu) - #define MEM_PROT_2_MEM_PROT_2_MASK (0xFFFFFFFFu) - #define MEM_PROT_2_MEM_PROT_2_BIT (0) - #define MEM_PROT_2_MEM_PROT_2_BITS (32) +/* MEM_PROT_2 field */ +#define MEM_PROT_2_MEM_PROT_2 (0xFFFFFFFFu) +#define MEM_PROT_2_MEM_PROT_2_MASK (0xFFFFFFFFu) +#define MEM_PROT_2_MEM_PROT_2_BIT (0) +#define MEM_PROT_2_MEM_PROT_2_BITS (32) #define MEM_PROT_3 *((volatile uint32_t *)0x4000500Cu) #define MEM_PROT_3_REG *((volatile uint32_t *)0x4000500Cu) #define MEM_PROT_3_ADDR (0x4000500Cu) #define MEM_PROT_3_RESET (0x00000000u) - /* MEM_PROT_3 field */ - #define MEM_PROT_3_MEM_PROT_3 (0xFFFFFFFFu) - #define MEM_PROT_3_MEM_PROT_3_MASK (0xFFFFFFFFu) - #define MEM_PROT_3_MEM_PROT_3_BIT (0) - #define MEM_PROT_3_MEM_PROT_3_BITS (32) +/* MEM_PROT_3 field */ +#define MEM_PROT_3_MEM_PROT_3 (0xFFFFFFFFu) +#define MEM_PROT_3_MEM_PROT_3_MASK (0xFFFFFFFFu) +#define MEM_PROT_3_MEM_PROT_3_BIT (0) +#define MEM_PROT_3_MEM_PROT_3_BITS (32) #define MEM_PROT_4 *((volatile uint32_t *)0x40005010u) #define MEM_PROT_4_REG *((volatile uint32_t *)0x40005010u) #define MEM_PROT_4_ADDR (0x40005010u) #define MEM_PROT_4_RESET (0x00000000u) - /* MEM_PROT_4 field */ - #define MEM_PROT_4_MEM_PROT_4 (0xFFFFFFFFu) - #define MEM_PROT_4_MEM_PROT_4_MASK (0xFFFFFFFFu) - #define MEM_PROT_4_MEM_PROT_4_BIT (0) - #define MEM_PROT_4_MEM_PROT_4_BITS (32) +/* MEM_PROT_4 field */ +#define MEM_PROT_4_MEM_PROT_4 (0xFFFFFFFFu) +#define MEM_PROT_4_MEM_PROT_4_MASK (0xFFFFFFFFu) +#define MEM_PROT_4_MEM_PROT_4_BIT (0) +#define MEM_PROT_4_MEM_PROT_4_BITS (32) #define MEM_PROT_5 *((volatile uint32_t *)0x40005014u) #define MEM_PROT_5_REG *((volatile uint32_t *)0x40005014u) #define MEM_PROT_5_ADDR (0x40005014u) #define MEM_PROT_5_RESET (0x00000000u) - /* MEM_PROT_5 field */ - #define MEM_PROT_5_MEM_PROT_5 (0xFFFFFFFFu) - #define MEM_PROT_5_MEM_PROT_5_MASK (0xFFFFFFFFu) - #define MEM_PROT_5_MEM_PROT_5_BIT (0) - #define MEM_PROT_5_MEM_PROT_5_BITS (32) +/* MEM_PROT_5 field */ +#define MEM_PROT_5_MEM_PROT_5 (0xFFFFFFFFu) +#define MEM_PROT_5_MEM_PROT_5_MASK (0xFFFFFFFFu) +#define MEM_PROT_5_MEM_PROT_5_BIT (0) +#define MEM_PROT_5_MEM_PROT_5_BITS (32) #define MEM_PROT_6 *((volatile uint32_t *)0x40005018u) #define MEM_PROT_6_REG *((volatile uint32_t *)0x40005018u) #define MEM_PROT_6_ADDR (0x40005018u) #define MEM_PROT_6_RESET (0x00000000u) - /* MEM_PROT_6 field */ - #define MEM_PROT_6_MEM_PROT_6 (0xFFFFFFFFu) - #define MEM_PROT_6_MEM_PROT_6_MASK (0xFFFFFFFFu) - #define MEM_PROT_6_MEM_PROT_6_BIT (0) - #define MEM_PROT_6_MEM_PROT_6_BITS (32) +/* MEM_PROT_6 field */ +#define MEM_PROT_6_MEM_PROT_6 (0xFFFFFFFFu) +#define MEM_PROT_6_MEM_PROT_6_MASK (0xFFFFFFFFu) +#define MEM_PROT_6_MEM_PROT_6_BIT (0) +#define MEM_PROT_6_MEM_PROT_6_BITS (32) #define MEM_PROT_7 *((volatile uint32_t *)0x4000501Cu) #define MEM_PROT_7_REG *((volatile uint32_t *)0x4000501Cu) #define MEM_PROT_7_ADDR (0x4000501Cu) #define MEM_PROT_7_RESET (0x00000000u) - /* MEM_PROT_7 field */ - #define MEM_PROT_7_MEM_PROT_7 (0xFFFFFFFFu) - #define MEM_PROT_7_MEM_PROT_7_MASK (0xFFFFFFFFu) - #define MEM_PROT_7_MEM_PROT_7_BIT (0) - #define MEM_PROT_7_MEM_PROT_7_BITS (32) +/* MEM_PROT_7 field */ +#define MEM_PROT_7_MEM_PROT_7 (0xFFFFFFFFu) +#define MEM_PROT_7_MEM_PROT_7_MASK (0xFFFFFFFFu) +#define MEM_PROT_7_MEM_PROT_7_BIT (0) +#define MEM_PROT_7_MEM_PROT_7_BITS (32) #define DMA_PROT_ADDR *((volatile uint32_t *)0x40005020u) #define DMA_PROT_ADDR_REG *((volatile uint32_t *)0x40005020u) #define DMA_PROT_ADDR_ADDR (0x40005020u) #define DMA_PROT_ADDR_RESET (0x20000000u) - /* DMA_PROT_OFFS field */ - #define DMA_PROT_ADDR_DMA_PROT_OFFS (0xFFFFE000u) - #define DMA_PROT_ADDR_DMA_PROT_OFFS_MASK (0xFFFFE000u) - #define DMA_PROT_ADDR_DMA_PROT_OFFS_BIT (13) - #define DMA_PROT_ADDR_DMA_PROT_OFFS_BITS (19) - /* DMA_PROT_ADDR field */ - #define DMA_PROT_ADDR_DMA_PROT_ADDR (0x00001FFFu) - #define DMA_PROT_ADDR_DMA_PROT_ADDR_MASK (0x00001FFFu) - #define DMA_PROT_ADDR_DMA_PROT_ADDR_BIT (0) - #define DMA_PROT_ADDR_DMA_PROT_ADDR_BITS (13) +/* DMA_PROT_OFFS field */ +#define DMA_PROT_ADDR_DMA_PROT_OFFS (0xFFFFE000u) +#define DMA_PROT_ADDR_DMA_PROT_OFFS_MASK (0xFFFFE000u) +#define DMA_PROT_ADDR_DMA_PROT_OFFS_BIT (13) +#define DMA_PROT_ADDR_DMA_PROT_OFFS_BITS (19) +/* DMA_PROT_ADDR field */ +#define DMA_PROT_ADDR_DMA_PROT_ADDR (0x00001FFFu) +#define DMA_PROT_ADDR_DMA_PROT_ADDR_MASK (0x00001FFFu) +#define DMA_PROT_ADDR_DMA_PROT_ADDR_BIT (0) +#define DMA_PROT_ADDR_DMA_PROT_ADDR_BITS (13) #define DMA_PROT_CH *((volatile uint32_t *)0x40005024u) #define DMA_PROT_CH_REG *((volatile uint32_t *)0x40005024u) #define DMA_PROT_CH_ADDR (0x40005024u) #define DMA_PROT_CH_RESET (0x00000000u) - /* DMA_PROT_CH field */ - #define DMA_PROT_CH_DMA_PROT_CH (0x00000007u) - #define DMA_PROT_CH_DMA_PROT_CH_MASK (0x00000007u) - #define DMA_PROT_CH_DMA_PROT_CH_BIT (0) - #define DMA_PROT_CH_DMA_PROT_CH_BITS (3) +/* DMA_PROT_CH field */ +#define DMA_PROT_CH_DMA_PROT_CH (0x00000007u) +#define DMA_PROT_CH_DMA_PROT_CH_MASK (0x00000007u) +#define DMA_PROT_CH_DMA_PROT_CH_BIT (0) +#define DMA_PROT_CH_DMA_PROT_CH_BITS (3) #define MEM_PROT_EN *((volatile uint32_t *)0x40005028u) #define MEM_PROT_EN_REG *((volatile uint32_t *)0x40005028u) #define MEM_PROT_EN_ADDR (0x40005028u) #define MEM_PROT_EN_RESET (0x00000000u) - /* FORCE_PROT field */ - #define MEM_PROT_EN_FORCE_PROT (0x00000004u) - #define MEM_PROT_EN_FORCE_PROT_MASK (0x00000004u) - #define MEM_PROT_EN_FORCE_PROT_BIT (2) - #define MEM_PROT_EN_FORCE_PROT_BITS (1) - /* DMA_PROT_EN_MAC field */ - #define MEM_PROT_EN_DMA_PROT_EN_MAC (0x00000002u) - #define MEM_PROT_EN_DMA_PROT_EN_MAC_MASK (0x00000002u) - #define MEM_PROT_EN_DMA_PROT_EN_MAC_BIT (1) - #define MEM_PROT_EN_DMA_PROT_EN_MAC_BITS (1) - /* DMA_PROT_EN_OTHER field */ - #define MEM_PROT_EN_DMA_PROT_EN_OTHER (0x00000001u) - #define MEM_PROT_EN_DMA_PROT_EN_OTHER_MASK (0x00000001u) - #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BIT (0) - #define MEM_PROT_EN_DMA_PROT_EN_OTHER_BITS (1) +/* FORCE_PROT field */ +#define MEM_PROT_EN_FORCE_PROT (0x00000004u) +#define MEM_PROT_EN_FORCE_PROT_MASK (0x00000004u) +#define MEM_PROT_EN_FORCE_PROT_BIT (2) +#define MEM_PROT_EN_FORCE_PROT_BITS (1) +/* DMA_PROT_EN_MAC field */ +#define MEM_PROT_EN_DMA_PROT_EN_MAC (0x00000002u) +#define MEM_PROT_EN_DMA_PROT_EN_MAC_MASK (0x00000002u) +#define MEM_PROT_EN_DMA_PROT_EN_MAC_BIT (1) +#define MEM_PROT_EN_DMA_PROT_EN_MAC_BITS (1) +/* DMA_PROT_EN_OTHER field */ +#define MEM_PROT_EN_DMA_PROT_EN_OTHER (0x00000001u) +#define MEM_PROT_EN_DMA_PROT_EN_OTHER_MASK (0x00000001u) +#define MEM_PROT_EN_DMA_PROT_EN_OTHER_BIT (0) +#define MEM_PROT_EN_DMA_PROT_EN_OTHER_BITS (1) /* SLOW_TIMERS block */ #define DATA_SLOW_TIMERS_BASE (0x40006000u) @@ -2804,26 +2804,26 @@ #define WDOG_CFG_REG *((volatile uint32_t *)0x40006000u) #define WDOG_CFG_ADDR (0x40006000u) #define WDOG_CFG_RESET (0x00000002u) - /* WDOG_DISABLE field */ - #define WDOG_DISABLE (0x00000002u) - #define WDOG_DISABLE_MASK (0x00000002u) - #define WDOG_DISABLE_BIT (1) - #define WDOG_DISABLE_BITS (1) - /* WDOG_ENABLE field */ - #define WDOG_ENABLE (0x00000001u) - #define WDOG_ENABLE_MASK (0x00000001u) - #define WDOG_ENABLE_BIT (0) - #define WDOG_ENABLE_BITS (1) +/* WDOG_DISABLE field */ +#define WDOG_DISABLE (0x00000002u) +#define WDOG_DISABLE_MASK (0x00000002u) +#define WDOG_DISABLE_BIT (1) +#define WDOG_DISABLE_BITS (1) +/* WDOG_ENABLE field */ +#define WDOG_ENABLE (0x00000001u) +#define WDOG_ENABLE_MASK (0x00000001u) +#define WDOG_ENABLE_BIT (0) +#define WDOG_ENABLE_BITS (1) #define WDOG_KEY *((volatile uint32_t *)0x40006004u) #define WDOG_KEY_REG *((volatile uint32_t *)0x40006004u) #define WDOG_KEY_ADDR (0x40006004u) #define WDOG_KEY_RESET (0x00000000u) - /* WDOG_KEY_FIELD field */ - #define WDOG_KEY_FIELD (0x0000FFFFu) - #define WDOG_KEY_FIELD_MASK (0x0000FFFFu) - #define WDOG_KEY_FIELD_BIT (0) - #define WDOG_KEY_FIELD_BITS (16) +/* WDOG_KEY_FIELD field */ +#define WDOG_KEY_FIELD (0x0000FFFFu) +#define WDOG_KEY_FIELD_MASK (0x0000FFFFu) +#define WDOG_KEY_FIELD_BIT (0) +#define WDOG_KEY_FIELD_BITS (16) #define WDOG_RESET *((volatile uint32_t *)0x40006008u) #define WDOG_RESET_REG *((volatile uint32_t *)0x40006008u) @@ -2834,91 +2834,91 @@ #define SLEEPTMR_CFG_REG *((volatile uint32_t *)0x4000600Cu) #define SLEEPTMR_CFG_ADDR (0x4000600Cu) #define SLEEPTMR_CFG_RESET (0x00000400u) - /* SLEEPTMR_REVERSE field */ - #define SLEEPTMR_REVERSE (0x00001000u) - #define SLEEPTMR_REVERSE_MASK (0x00001000u) - #define SLEEPTMR_REVERSE_BIT (12) - #define SLEEPTMR_REVERSE_BITS (1) - /* SLEEPTMR_ENABLE field */ - #define SLEEPTMR_ENABLE (0x00000800u) - #define SLEEPTMR_ENABLE_MASK (0x00000800u) - #define SLEEPTMR_ENABLE_BIT (11) - #define SLEEPTMR_ENABLE_BITS (1) - /* SLEEPTMR_DBGPAUSE field */ - #define SLEEPTMR_DBGPAUSE (0x00000400u) - #define SLEEPTMR_DBGPAUSE_MASK (0x00000400u) - #define SLEEPTMR_DBGPAUSE_BIT (10) - #define SLEEPTMR_DBGPAUSE_BITS (1) - /* SLEEPTMR_CLKDIV field */ - #define SLEEPTMR_CLKDIV (0x000000F0u) - #define SLEEPTMR_CLKDIV_MASK (0x000000F0u) - #define SLEEPTMR_CLKDIV_BIT (4) - #define SLEEPTMR_CLKDIV_BITS (4) - /* SLEEPTMR_CLKSEL field */ - #define SLEEPTMR_CLKSEL (0x00000001u) - #define SLEEPTMR_CLKSEL_MASK (0x00000001u) - #define SLEEPTMR_CLKSEL_BIT (0) - #define SLEEPTMR_CLKSEL_BITS (1) +/* SLEEPTMR_REVERSE field */ +#define SLEEPTMR_REVERSE (0x00001000u) +#define SLEEPTMR_REVERSE_MASK (0x00001000u) +#define SLEEPTMR_REVERSE_BIT (12) +#define SLEEPTMR_REVERSE_BITS (1) +/* SLEEPTMR_ENABLE field */ +#define SLEEPTMR_ENABLE (0x00000800u) +#define SLEEPTMR_ENABLE_MASK (0x00000800u) +#define SLEEPTMR_ENABLE_BIT (11) +#define SLEEPTMR_ENABLE_BITS (1) +/* SLEEPTMR_DBGPAUSE field */ +#define SLEEPTMR_DBGPAUSE (0x00000400u) +#define SLEEPTMR_DBGPAUSE_MASK (0x00000400u) +#define SLEEPTMR_DBGPAUSE_BIT (10) +#define SLEEPTMR_DBGPAUSE_BITS (1) +/* SLEEPTMR_CLKDIV field */ +#define SLEEPTMR_CLKDIV (0x000000F0u) +#define SLEEPTMR_CLKDIV_MASK (0x000000F0u) +#define SLEEPTMR_CLKDIV_BIT (4) +#define SLEEPTMR_CLKDIV_BITS (4) +/* SLEEPTMR_CLKSEL field */ +#define SLEEPTMR_CLKSEL (0x00000001u) +#define SLEEPTMR_CLKSEL_MASK (0x00000001u) +#define SLEEPTMR_CLKSEL_BIT (0) +#define SLEEPTMR_CLKSEL_BITS (1) #define SLEEPTMR_CNTH *((volatile uint32_t *)0x40006010u) #define SLEEPTMR_CNTH_REG *((volatile uint32_t *)0x40006010u) #define SLEEPTMR_CNTH_ADDR (0x40006010u) #define SLEEPTMR_CNTH_RESET (0x00000000u) - /* SLEEPTMR_CNTH_FIELD field */ - #define SLEEPTMR_CNTH_FIELD (0x0000FFFFu) - #define SLEEPTMR_CNTH_FIELD_MASK (0x0000FFFFu) - #define SLEEPTMR_CNTH_FIELD_BIT (0) - #define SLEEPTMR_CNTH_FIELD_BITS (16) +/* SLEEPTMR_CNTH_FIELD field */ +#define SLEEPTMR_CNTH_FIELD (0x0000FFFFu) +#define SLEEPTMR_CNTH_FIELD_MASK (0x0000FFFFu) +#define SLEEPTMR_CNTH_FIELD_BIT (0) +#define SLEEPTMR_CNTH_FIELD_BITS (16) #define SLEEPTMR_CNTL *((volatile uint32_t *)0x40006014u) #define SLEEPTMR_CNTL_REG *((volatile uint32_t *)0x40006014u) #define SLEEPTMR_CNTL_ADDR (0x40006014u) #define SLEEPTMR_CNTL_RESET (0x00000000u) - /* SLEEPTMR_CNTL_FIELD field */ - #define SLEEPTMR_CNTL_FIELD (0x0000FFFFu) - #define SLEEPTMR_CNTL_FIELD_MASK (0x0000FFFFu) - #define SLEEPTMR_CNTL_FIELD_BIT (0) - #define SLEEPTMR_CNTL_FIELD_BITS (16) +/* SLEEPTMR_CNTL_FIELD field */ +#define SLEEPTMR_CNTL_FIELD (0x0000FFFFu) +#define SLEEPTMR_CNTL_FIELD_MASK (0x0000FFFFu) +#define SLEEPTMR_CNTL_FIELD_BIT (0) +#define SLEEPTMR_CNTL_FIELD_BITS (16) #define SLEEPTMR_CMPAH *((volatile uint32_t *)0x40006018u) #define SLEEPTMR_CMPAH_REG *((volatile uint32_t *)0x40006018u) #define SLEEPTMR_CMPAH_ADDR (0x40006018u) #define SLEEPTMR_CMPAH_RESET (0x0000FFFFu) - /* SLEEPTMR_CMPAH_FIELD field */ - #define SLEEPTMR_CMPAH_FIELD (0x0000FFFFu) - #define SLEEPTMR_CMPAH_FIELD_MASK (0x0000FFFFu) - #define SLEEPTMR_CMPAH_FIELD_BIT (0) - #define SLEEPTMR_CMPAH_FIELD_BITS (16) +/* SLEEPTMR_CMPAH_FIELD field */ +#define SLEEPTMR_CMPAH_FIELD (0x0000FFFFu) +#define SLEEPTMR_CMPAH_FIELD_MASK (0x0000FFFFu) +#define SLEEPTMR_CMPAH_FIELD_BIT (0) +#define SLEEPTMR_CMPAH_FIELD_BITS (16) #define SLEEPTMR_CMPAL *((volatile uint32_t *)0x4000601Cu) #define SLEEPTMR_CMPAL_REG *((volatile uint32_t *)0x4000601Cu) #define SLEEPTMR_CMPAL_ADDR (0x4000601Cu) #define SLEEPTMR_CMPAL_RESET (0x0000FFFFu) - /* SLEEPTMR_CMPAL_FIELD field */ - #define SLEEPTMR_CMPAL_FIELD (0x0000FFFFu) - #define SLEEPTMR_CMPAL_FIELD_MASK (0x0000FFFFu) - #define SLEEPTMR_CMPAL_FIELD_BIT (0) - #define SLEEPTMR_CMPAL_FIELD_BITS (16) +/* SLEEPTMR_CMPAL_FIELD field */ +#define SLEEPTMR_CMPAL_FIELD (0x0000FFFFu) +#define SLEEPTMR_CMPAL_FIELD_MASK (0x0000FFFFu) +#define SLEEPTMR_CMPAL_FIELD_BIT (0) +#define SLEEPTMR_CMPAL_FIELD_BITS (16) #define SLEEPTMR_CMPBH *((volatile uint32_t *)0x40006020u) #define SLEEPTMR_CMPBH_REG *((volatile uint32_t *)0x40006020u) #define SLEEPTMR_CMPBH_ADDR (0x40006020u) #define SLEEPTMR_CMPBH_RESET (0x0000FFFFu) - /* SLEEPTMR_CMPBH_FIELD field */ - #define SLEEPTMR_CMPBH_FIELD (0x0000FFFFu) - #define SLEEPTMR_CMPBH_FIELD_MASK (0x0000FFFFu) - #define SLEEPTMR_CMPBH_FIELD_BIT (0) - #define SLEEPTMR_CMPBH_FIELD_BITS (16) +/* SLEEPTMR_CMPBH_FIELD field */ +#define SLEEPTMR_CMPBH_FIELD (0x0000FFFFu) +#define SLEEPTMR_CMPBH_FIELD_MASK (0x0000FFFFu) +#define SLEEPTMR_CMPBH_FIELD_BIT (0) +#define SLEEPTMR_CMPBH_FIELD_BITS (16) #define SLEEPTMR_CMPBL *((volatile uint32_t *)0x40006024u) #define SLEEPTMR_CMPBL_REG *((volatile uint32_t *)0x40006024u) #define SLEEPTMR_CMPBL_ADDR (0x40006024u) #define SLEEPTMR_CMPBL_RESET (0x0000FFFFu) - /* SLEEPTMR_CMPBL_FIELD field */ - #define SLEEPTMR_CMPBL_FIELD (0x0000FFFFu) - #define SLEEPTMR_CMPBL_FIELD_MASK (0x0000FFFFu) - #define SLEEPTMR_CMPBL_FIELD_BIT (0) - #define SLEEPTMR_CMPBL_FIELD_BITS (16) +/* SLEEPTMR_CMPBL_FIELD field */ +#define SLEEPTMR_CMPBL_FIELD (0x0000FFFFu) +#define SLEEPTMR_CMPBL_FIELD_MASK (0x0000FFFFu) +#define SLEEPTMR_CMPBL_FIELD_BIT (0) +#define SLEEPTMR_CMPBL_FIELD_BITS (16) /* CAL_ADC block */ #define DATA_CAL_ADC_BASE (0x40007000u) @@ -2929,41 +2929,41 @@ #define CAL_ADC_DATA_REG *((volatile uint32_t *)0x40007000u) #define CAL_ADC_DATA_ADDR (0x40007000u) #define CAL_ADC_DATA_RESET (0x00000000u) - /* CAL_ADC_DATA field */ - #define CAL_ADC_DATA_CAL_ADC_DATA (0x0000FFFFu) - #define CAL_ADC_DATA_CAL_ADC_DATA_MASK (0x0000FFFFu) - #define CAL_ADC_DATA_CAL_ADC_DATA_BIT (0) - #define CAL_ADC_DATA_CAL_ADC_DATA_BITS (16) +/* CAL_ADC_DATA field */ +#define CAL_ADC_DATA_CAL_ADC_DATA (0x0000FFFFu) +#define CAL_ADC_DATA_CAL_ADC_DATA_MASK (0x0000FFFFu) +#define CAL_ADC_DATA_CAL_ADC_DATA_BIT (0) +#define CAL_ADC_DATA_CAL_ADC_DATA_BITS (16) #define CAL_ADC_CONFIG *((volatile uint32_t *)0x40007004u) #define CAL_ADC_CONFIG_REG *((volatile uint32_t *)0x40007004u) #define CAL_ADC_CONFIG_ADDR (0x40007004u) #define CAL_ADC_CONFIG_RESET (0x00000000u) - /* CAL_ADC_RATE field */ - #define CAL_ADC_CONFIG_CAL_ADC_RATE (0x00007000u) - #define CAL_ADC_CONFIG_CAL_ADC_RATE_MASK (0x00007000u) - #define CAL_ADC_CONFIG_CAL_ADC_RATE_BIT (12) - #define CAL_ADC_CONFIG_CAL_ADC_RATE_BITS (3) - /* CAL_ADC_MUX field */ - #define CAL_ADC_CONFIG_CAL_ADC_MUX (0x00000F80u) - #define CAL_ADC_CONFIG_CAL_ADC_MUX_MASK (0x00000F80u) - #define CAL_ADC_CONFIG_CAL_ADC_MUX_BIT (7) - #define CAL_ADC_CONFIG_CAL_ADC_MUX_BITS (5) - /* CAL_ADC_CLKSEL field */ - #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL (0x00000004u) - #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_MASK (0x00000004u) - #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT (2) - #define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BITS (1) - /* CAL_ADC_DITHER_DIS field */ - #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS (0x00000002u) - #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_MASK (0x00000002u) - #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BIT (1) - #define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BITS (1) - /* CAL_ADC_EN field */ - #define CAL_ADC_CONFIG_CAL_ADC_EN (0x00000001u) - #define CAL_ADC_CONFIG_CAL_ADC_EN_MASK (0x00000001u) - #define CAL_ADC_CONFIG_CAL_ADC_EN_BIT (0) - #define CAL_ADC_CONFIG_CAL_ADC_EN_BITS (1) +/* CAL_ADC_RATE field */ +#define CAL_ADC_CONFIG_CAL_ADC_RATE (0x00007000u) +#define CAL_ADC_CONFIG_CAL_ADC_RATE_MASK (0x00007000u) +#define CAL_ADC_CONFIG_CAL_ADC_RATE_BIT (12) +#define CAL_ADC_CONFIG_CAL_ADC_RATE_BITS (3) +/* CAL_ADC_MUX field */ +#define CAL_ADC_CONFIG_CAL_ADC_MUX (0x00000F80u) +#define CAL_ADC_CONFIG_CAL_ADC_MUX_MASK (0x00000F80u) +#define CAL_ADC_CONFIG_CAL_ADC_MUX_BIT (7) +#define CAL_ADC_CONFIG_CAL_ADC_MUX_BITS (5) +/* CAL_ADC_CLKSEL field */ +#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL (0x00000004u) +#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_MASK (0x00000004u) +#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT (2) +#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BITS (1) +/* CAL_ADC_DITHER_DIS field */ +#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS (0x00000002u) +#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_MASK (0x00000002u) +#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BIT (1) +#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BITS (1) +/* CAL_ADC_EN field */ +#define CAL_ADC_CONFIG_CAL_ADC_EN (0x00000001u) +#define CAL_ADC_CONFIG_CAL_ADC_EN_MASK (0x00000001u) +#define CAL_ADC_CONFIG_CAL_ADC_EN_BIT (0) +#define CAL_ADC_CONFIG_CAL_ADC_EN_BITS (1) /* FLASH_CONTROL block */ #define DATA_FLASH_CONTROL_BASE (0x40008000u) @@ -2974,271 +2974,271 @@ #define FLASH_ACCESS_REG *((volatile uint32_t *)0x40008000u) #define FLASH_ACCESS_ADDR (0x40008000u) #define FLASH_ACCESS_RESET (0x00000031u) - /* PREFETCH_STATUS field */ - #define FLASH_ACCESS_PREFETCH_STATUS (0x00000020u) - #define FLASH_ACCESS_PREFETCH_STATUS_MASK (0x00000020u) - #define FLASH_ACCESS_PREFETCH_STATUS_BIT (5) - #define FLASH_ACCESS_PREFETCH_STATUS_BITS (1) - /* PREFETCH_EN field */ - #define FLASH_ACCESS_PREFETCH_EN (0x00000010u) - #define FLASH_ACCESS_PREFETCH_EN_MASK (0x00000010u) - #define FLASH_ACCESS_PREFETCH_EN_BIT (4) - #define FLASH_ACCESS_PREFETCH_EN_BITS (1) - /* HALFCYCLE_ACCESS field */ - #define FLASH_ACCESS_HALFCYCLE_ACCESS (0x00000008u) - #define FLASH_ACCESS_HALFCYCLE_ACCESS_MASK (0x00000008u) - #define FLASH_ACCESS_HALFCYCLE_ACCESS_BIT (3) - #define FLASH_ACCESS_HALFCYCLE_ACCESS_BITS (1) - /* CODE_LATENCY field */ - #define FLASH_ACCESS_CODE_LATENCY (0x00000007u) - #define FLASH_ACCESS_CODE_LATENCY_MASK (0x00000007u) - #define FLASH_ACCESS_CODE_LATENCY_BIT (0) - #define FLASH_ACCESS_CODE_LATENCY_BITS (3) +/* PREFETCH_STATUS field */ +#define FLASH_ACCESS_PREFETCH_STATUS (0x00000020u) +#define FLASH_ACCESS_PREFETCH_STATUS_MASK (0x00000020u) +#define FLASH_ACCESS_PREFETCH_STATUS_BIT (5) +#define FLASH_ACCESS_PREFETCH_STATUS_BITS (1) +/* PREFETCH_EN field */ +#define FLASH_ACCESS_PREFETCH_EN (0x00000010u) +#define FLASH_ACCESS_PREFETCH_EN_MASK (0x00000010u) +#define FLASH_ACCESS_PREFETCH_EN_BIT (4) +#define FLASH_ACCESS_PREFETCH_EN_BITS (1) +/* HALFCYCLE_ACCESS field */ +#define FLASH_ACCESS_HALFCYCLE_ACCESS (0x00000008u) +#define FLASH_ACCESS_HALFCYCLE_ACCESS_MASK (0x00000008u) +#define FLASH_ACCESS_HALFCYCLE_ACCESS_BIT (3) +#define FLASH_ACCESS_HALFCYCLE_ACCESS_BITS (1) +/* CODE_LATENCY field */ +#define FLASH_ACCESS_CODE_LATENCY (0x00000007u) +#define FLASH_ACCESS_CODE_LATENCY_MASK (0x00000007u) +#define FLASH_ACCESS_CODE_LATENCY_BIT (0) +#define FLASH_ACCESS_CODE_LATENCY_BITS (3) #define FPEC_KEY *((volatile uint32_t *)0x40008004u) #define FPEC_KEY_REG *((volatile uint32_t *)0x40008004u) #define FPEC_KEY_ADDR (0x40008004u) #define FPEC_KEY_RESET (0x00000000u) - /* FKEYR field */ - #define FPEC_KEY_FKEYR (0xFFFFFFFFu) - #define FPEC_KEY_FKEYR_MASK (0xFFFFFFFFu) - #define FPEC_KEY_FKEYR_BIT (0) - #define FPEC_KEY_FKEYR_BITS (32) +/* FKEYR field */ +#define FPEC_KEY_FKEYR (0xFFFFFFFFu) +#define FPEC_KEY_FKEYR_MASK (0xFFFFFFFFu) +#define FPEC_KEY_FKEYR_BIT (0) +#define FPEC_KEY_FKEYR_BITS (32) #define OPT_KEY *((volatile uint32_t *)0x40008008u) #define OPT_KEY_REG *((volatile uint32_t *)0x40008008u) #define OPT_KEY_ADDR (0x40008008u) #define OPT_KEY_RESET (0x00000000u) - /* OPTKEYR field */ - #define OPT_KEY_OPTKEYR (0xFFFFFFFFu) - #define OPT_KEY_OPTKEYR_MASK (0xFFFFFFFFu) - #define OPT_KEY_OPTKEYR_BIT (0) - #define OPT_KEY_OPTKEYR_BITS (32) +/* OPTKEYR field */ +#define OPT_KEY_OPTKEYR (0xFFFFFFFFu) +#define OPT_KEY_OPTKEYR_MASK (0xFFFFFFFFu) +#define OPT_KEY_OPTKEYR_BIT (0) +#define OPT_KEY_OPTKEYR_BITS (32) #define FLASH_STATUS *((volatile uint32_t *)0x4000800Cu) #define FLASH_STATUS_REG *((volatile uint32_t *)0x4000800Cu) #define FLASH_STATUS_ADDR (0x4000800Cu) #define FLASH_STATUS_RESET (0x00000000u) - /* EOP field */ - #define FLASH_STATUS_EOP (0x00000020u) - #define FLASH_STATUS_EOP_MASK (0x00000020u) - #define FLASH_STATUS_EOP_BIT (5) - #define FLASH_STATUS_EOP_BITS (1) - /* WRP_ERR field */ - #define FLASH_STATUS_WRP_ERR (0x00000010u) - #define FLASH_STATUS_WRP_ERR_MASK (0x00000010u) - #define FLASH_STATUS_WRP_ERR_BIT (4) - #define FLASH_STATUS_WRP_ERR_BITS (1) - /* PAGE_PROG_ERR field */ - #define FLASH_STATUS_PAGE_PROG_ERR (0x00000008u) - #define FLASH_STATUS_PAGE_PROG_ERR_MASK (0x00000008u) - #define FLASH_STATUS_PAGE_PROG_ERR_BIT (3) - #define FLASH_STATUS_PAGE_PROG_ERR_BITS (1) - /* PROG_ERR field */ - #define FLASH_STATUS_PROG_ERR (0x00000004u) - #define FLASH_STATUS_PROG_ERR_MASK (0x00000004u) - #define FLASH_STATUS_PROG_ERR_BIT (2) - #define FLASH_STATUS_PROG_ERR_BITS (1) - /* EARLY_BSY field */ - #define FLASH_STATUS_EARLY_BSY (0x00000002u) - #define FLASH_STATUS_EARLY_BSY_MASK (0x00000002u) - #define FLASH_STATUS_EARLY_BSY_BIT (1) - #define FLASH_STATUS_EARLY_BSY_BITS (1) - /* FLA_BSY field */ - #define FLASH_STATUS_FLA_BSY (0x00000001u) - #define FLASH_STATUS_FLA_BSY_MASK (0x00000001u) - #define FLASH_STATUS_FLA_BSY_BIT (0) - #define FLASH_STATUS_FLA_BSY_BITS (1) +/* EOP field */ +#define FLASH_STATUS_EOP (0x00000020u) +#define FLASH_STATUS_EOP_MASK (0x00000020u) +#define FLASH_STATUS_EOP_BIT (5) +#define FLASH_STATUS_EOP_BITS (1) +/* WRP_ERR field */ +#define FLASH_STATUS_WRP_ERR (0x00000010u) +#define FLASH_STATUS_WRP_ERR_MASK (0x00000010u) +#define FLASH_STATUS_WRP_ERR_BIT (4) +#define FLASH_STATUS_WRP_ERR_BITS (1) +/* PAGE_PROG_ERR field */ +#define FLASH_STATUS_PAGE_PROG_ERR (0x00000008u) +#define FLASH_STATUS_PAGE_PROG_ERR_MASK (0x00000008u) +#define FLASH_STATUS_PAGE_PROG_ERR_BIT (3) +#define FLASH_STATUS_PAGE_PROG_ERR_BITS (1) +/* PROG_ERR field */ +#define FLASH_STATUS_PROG_ERR (0x00000004u) +#define FLASH_STATUS_PROG_ERR_MASK (0x00000004u) +#define FLASH_STATUS_PROG_ERR_BIT (2) +#define FLASH_STATUS_PROG_ERR_BITS (1) +/* EARLY_BSY field */ +#define FLASH_STATUS_EARLY_BSY (0x00000002u) +#define FLASH_STATUS_EARLY_BSY_MASK (0x00000002u) +#define FLASH_STATUS_EARLY_BSY_BIT (1) +#define FLASH_STATUS_EARLY_BSY_BITS (1) +/* FLA_BSY field */ +#define FLASH_STATUS_FLA_BSY (0x00000001u) +#define FLASH_STATUS_FLA_BSY_MASK (0x00000001u) +#define FLASH_STATUS_FLA_BSY_BIT (0) +#define FLASH_STATUS_FLA_BSY_BITS (1) #define FLASH_CTRL *((volatile uint32_t *)0x40008010u) #define FLASH_CTRL_REG *((volatile uint32_t *)0x40008010u) #define FLASH_CTRL_ADDR (0x40008010u) #define FLASH_CTRL_RESET (0x00000080u) - /* EOPIE field */ - #define FLASH_CTRL_EOPIE (0x00001000u) - #define FLASH_CTRL_EOPIE_MASK (0x00001000u) - #define FLASH_CTRL_EOPIE_BIT (12) - #define FLASH_CTRL_EOPIE_BITS (1) - /* EARLYBSYIE field */ - #define FLASH_CTRL_EARLYBSYIE (0x00000800u) - #define FLASH_CTRL_EARLYBSYIE_MASK (0x00000800u) - #define FLASH_CTRL_EARLYBSYIE_BIT (11) - #define FLASH_CTRL_EARLYBSYIE_BITS (1) - /* ERRIE field */ - #define FLASH_CTRL_ERRIE (0x00000400u) - #define FLASH_CTRL_ERRIE_MASK (0x00000400u) - #define FLASH_CTRL_ERRIE_BIT (10) - #define FLASH_CTRL_ERRIE_BITS (1) - /* OPTWREN field */ - #define FLASH_CTRL_OPTWREN (0x00000200u) - #define FLASH_CTRL_OPTWREN_MASK (0x00000200u) - #define FLASH_CTRL_OPTWREN_BIT (9) - #define FLASH_CTRL_OPTWREN_BITS (1) - /* FSTPROG field */ - #define FLASH_CTRL_FSTPROG (0x00000100u) - #define FLASH_CTRL_FSTPROG_MASK (0x00000100u) - #define FLASH_CTRL_FSTPROG_BIT (8) - #define FLASH_CTRL_FSTPROG_BITS (1) - /* LOCK field */ - #define FLASH_CTRL_LOCK (0x00000080u) - #define FLASH_CTRL_LOCK_MASK (0x00000080u) - #define FLASH_CTRL_LOCK_BIT (7) - #define FLASH_CTRL_LOCK_BITS (1) - /* FLA_START field */ - #define FLASH_CTRL_FLA_START (0x00000040u) - #define FLASH_CTRL_FLA_START_MASK (0x00000040u) - #define FLASH_CTRL_FLA_START_BIT (6) - #define FLASH_CTRL_FLA_START_BITS (1) - /* OPTERASE field */ - #define FLASH_CTRL_OPTERASE (0x00000020u) - #define FLASH_CTRL_OPTERASE_MASK (0x00000020u) - #define FLASH_CTRL_OPTERASE_BIT (5) - #define FLASH_CTRL_OPTERASE_BITS (1) - /* OPTPROG field */ - #define FLASH_CTRL_OPTPROG (0x00000010u) - #define FLASH_CTRL_OPTPROG_MASK (0x00000010u) - #define FLASH_CTRL_OPTPROG_BIT (4) - #define FLASH_CTRL_OPTPROG_BITS (1) - /* GLOBALERASE field */ - #define FLASH_CTRL_GLOBALERASE (0x00000008u) - #define FLASH_CTRL_GLOBALERASE_MASK (0x00000008u) - #define FLASH_CTRL_GLOBALERASE_BIT (3) - #define FLASH_CTRL_GLOBALERASE_BITS (1) - /* MASSERASE field */ - #define FLASH_CTRL_MASSERASE (0x00000004u) - #define FLASH_CTRL_MASSERASE_MASK (0x00000004u) - #define FLASH_CTRL_MASSERASE_BIT (2) - #define FLASH_CTRL_MASSERASE_BITS (1) - /* PAGEERASE field */ - #define FLASH_CTRL_PAGEERASE (0x00000002u) - #define FLASH_CTRL_PAGEERASE_MASK (0x00000002u) - #define FLASH_CTRL_PAGEERASE_BIT (1) - #define FLASH_CTRL_PAGEERASE_BITS (1) - /* PROG field */ - #define FLASH_CTRL_PROG (0x00000001u) - #define FLASH_CTRL_PROG_MASK (0x00000001u) - #define FLASH_CTRL_PROG_BIT (0) - #define FLASH_CTRL_PROG_BITS (1) +/* EOPIE field */ +#define FLASH_CTRL_EOPIE (0x00001000u) +#define FLASH_CTRL_EOPIE_MASK (0x00001000u) +#define FLASH_CTRL_EOPIE_BIT (12) +#define FLASH_CTRL_EOPIE_BITS (1) +/* EARLYBSYIE field */ +#define FLASH_CTRL_EARLYBSYIE (0x00000800u) +#define FLASH_CTRL_EARLYBSYIE_MASK (0x00000800u) +#define FLASH_CTRL_EARLYBSYIE_BIT (11) +#define FLASH_CTRL_EARLYBSYIE_BITS (1) +/* ERRIE field */ +#define FLASH_CTRL_ERRIE (0x00000400u) +#define FLASH_CTRL_ERRIE_MASK (0x00000400u) +#define FLASH_CTRL_ERRIE_BIT (10) +#define FLASH_CTRL_ERRIE_BITS (1) +/* OPTWREN field */ +#define FLASH_CTRL_OPTWREN (0x00000200u) +#define FLASH_CTRL_OPTWREN_MASK (0x00000200u) +#define FLASH_CTRL_OPTWREN_BIT (9) +#define FLASH_CTRL_OPTWREN_BITS (1) +/* FSTPROG field */ +#define FLASH_CTRL_FSTPROG (0x00000100u) +#define FLASH_CTRL_FSTPROG_MASK (0x00000100u) +#define FLASH_CTRL_FSTPROG_BIT (8) +#define FLASH_CTRL_FSTPROG_BITS (1) +/* LOCK field */ +#define FLASH_CTRL_LOCK (0x00000080u) +#define FLASH_CTRL_LOCK_MASK (0x00000080u) +#define FLASH_CTRL_LOCK_BIT (7) +#define FLASH_CTRL_LOCK_BITS (1) +/* FLA_START field */ +#define FLASH_CTRL_FLA_START (0x00000040u) +#define FLASH_CTRL_FLA_START_MASK (0x00000040u) +#define FLASH_CTRL_FLA_START_BIT (6) +#define FLASH_CTRL_FLA_START_BITS (1) +/* OPTERASE field */ +#define FLASH_CTRL_OPTERASE (0x00000020u) +#define FLASH_CTRL_OPTERASE_MASK (0x00000020u) +#define FLASH_CTRL_OPTERASE_BIT (5) +#define FLASH_CTRL_OPTERASE_BITS (1) +/* OPTPROG field */ +#define FLASH_CTRL_OPTPROG (0x00000010u) +#define FLASH_CTRL_OPTPROG_MASK (0x00000010u) +#define FLASH_CTRL_OPTPROG_BIT (4) +#define FLASH_CTRL_OPTPROG_BITS (1) +/* GLOBALERASE field */ +#define FLASH_CTRL_GLOBALERASE (0x00000008u) +#define FLASH_CTRL_GLOBALERASE_MASK (0x00000008u) +#define FLASH_CTRL_GLOBALERASE_BIT (3) +#define FLASH_CTRL_GLOBALERASE_BITS (1) +/* MASSERASE field */ +#define FLASH_CTRL_MASSERASE (0x00000004u) +#define FLASH_CTRL_MASSERASE_MASK (0x00000004u) +#define FLASH_CTRL_MASSERASE_BIT (2) +#define FLASH_CTRL_MASSERASE_BITS (1) +/* PAGEERASE field */ +#define FLASH_CTRL_PAGEERASE (0x00000002u) +#define FLASH_CTRL_PAGEERASE_MASK (0x00000002u) +#define FLASH_CTRL_PAGEERASE_BIT (1) +#define FLASH_CTRL_PAGEERASE_BITS (1) +/* PROG field */ +#define FLASH_CTRL_PROG (0x00000001u) +#define FLASH_CTRL_PROG_MASK (0x00000001u) +#define FLASH_CTRL_PROG_BIT (0) +#define FLASH_CTRL_PROG_BITS (1) #define FLASH_ADDR *((volatile uint32_t *)0x40008014u) #define FLASH_ADDR_REG *((volatile uint32_t *)0x40008014u) #define FLASH_ADDR_ADDR (0x40008014u) #define FLASH_ADDR_RESET (0x00000000u) - /* FAR field */ - #define FLASH_ADDR_FAR (0xFFFFFFFFu) - #define FLASH_ADDR_FAR_MASK (0xFFFFFFFFu) - #define FLASH_ADDR_FAR_BIT (0) - #define FLASH_ADDR_FAR_BITS (32) +/* FAR field */ +#define FLASH_ADDR_FAR (0xFFFFFFFFu) +#define FLASH_ADDR_FAR_MASK (0xFFFFFFFFu) +#define FLASH_ADDR_FAR_BIT (0) +#define FLASH_ADDR_FAR_BITS (32) #define OPT_BYTE *((volatile uint32_t *)0x4000801Cu) #define OPT_BYTE_REG *((volatile uint32_t *)0x4000801Cu) #define OPT_BYTE_ADDR (0x4000801Cu) #define OPT_BYTE_RESET (0xFBFFFFFEu) - /* RSVD field */ - #define OPT_BYTE_RSVD (0xF8000000u) - #define OPT_BYTE_RSVD_MASK (0xF8000000u) - #define OPT_BYTE_RSVD_BIT (27) - #define OPT_BYTE_RSVD_BITS (5) - /* OBR field */ - #define OPT_BYTE_OBR (0x07FFFFFCu) - #define OPT_BYTE_OBR_MASK (0x07FFFFFCu) - #define OPT_BYTE_OBR_BIT (2) - #define OPT_BYTE_OBR_BITS (25) - /* RDPROT field */ - #define OPT_BYTE_RDPROT (0x00000002u) - #define OPT_BYTE_RDPROT_MASK (0x00000002u) - #define OPT_BYTE_RDPROT_BIT (1) - #define OPT_BYTE_RDPROT_BITS (1) - /* OPT_ERR field */ - #define OPT_BYTE_OPT_ERR (0x00000001u) - #define OPT_BYTE_OPT_ERR_MASK (0x00000001u) - #define OPT_BYTE_OPT_ERR_BIT (0) - #define OPT_BYTE_OPT_ERR_BITS (1) +/* RSVD field */ +#define OPT_BYTE_RSVD (0xF8000000u) +#define OPT_BYTE_RSVD_MASK (0xF8000000u) +#define OPT_BYTE_RSVD_BIT (27) +#define OPT_BYTE_RSVD_BITS (5) +/* OBR field */ +#define OPT_BYTE_OBR (0x07FFFFFCu) +#define OPT_BYTE_OBR_MASK (0x07FFFFFCu) +#define OPT_BYTE_OBR_BIT (2) +#define OPT_BYTE_OBR_BITS (25) +/* RDPROT field */ +#define OPT_BYTE_RDPROT (0x00000002u) +#define OPT_BYTE_RDPROT_MASK (0x00000002u) +#define OPT_BYTE_RDPROT_BIT (1) +#define OPT_BYTE_RDPROT_BITS (1) +/* OPT_ERR field */ +#define OPT_BYTE_OPT_ERR (0x00000001u) +#define OPT_BYTE_OPT_ERR_MASK (0x00000001u) +#define OPT_BYTE_OPT_ERR_BIT (0) +#define OPT_BYTE_OPT_ERR_BITS (1) #define WRPROT *((volatile uint32_t *)0x40008020u) #define WRPROT_REG *((volatile uint32_t *)0x40008020u) #define WRPROT_ADDR (0x40008020u) #define WRPROT_RESET (0xFFFFFFFFu) - /* WRP field */ - #define WRPROT_WRP (0xFFFFFFFFu) - #define WRPROT_WRP_MASK (0xFFFFFFFFu) - #define WRPROT_WRP_BIT (0) - #define WRPROT_WRP_BITS (32) +/* WRP field */ +#define WRPROT_WRP (0xFFFFFFFFu) +#define WRPROT_WRP_MASK (0xFFFFFFFFu) +#define WRPROT_WRP_BIT (0) +#define WRPROT_WRP_BITS (32) #define FLASH_TEST_CTRL *((volatile uint32_t *)0x40008080u) #define FLASH_TEST_CTRL_REG *((volatile uint32_t *)0x40008080u) #define FLASH_TEST_CTRL_ADDR (0x40008080u) #define FLASH_TEST_CTRL_RESET (0x00000000u) - /* TMR field */ - #define FLASH_TEST_CTRL_TMR (0x00001000u) - #define FLASH_TEST_CTRL_TMR_MASK (0x00001000u) - #define FLASH_TEST_CTRL_TMR_BIT (12) - #define FLASH_TEST_CTRL_TMR_BITS (1) - /* ERASE field */ - #define FLASH_TEST_CTRL_ERASE (0x00000800u) - #define FLASH_TEST_CTRL_ERASE_MASK (0x00000800u) - #define FLASH_TEST_CTRL_ERASE_BIT (11) - #define FLASH_TEST_CTRL_ERASE_BITS (1) - /* MAS1 field */ - #define FLASH_TEST_CTRL_MAS1 (0x00000400u) - #define FLASH_TEST_CTRL_MAS1_MASK (0x00000400u) - #define FLASH_TEST_CTRL_MAS1_BIT (10) - #define FLASH_TEST_CTRL_MAS1_BITS (1) - /* TEST_PROG field */ - #define FLASH_TEST_CTRL_TEST_PROG (0x00000200u) - #define FLASH_TEST_CTRL_TEST_PROG_MASK (0x00000200u) - #define FLASH_TEST_CTRL_TEST_PROG_BIT (9) - #define FLASH_TEST_CTRL_TEST_PROG_BITS (1) - /* NVSTR field */ - #define FLASH_TEST_CTRL_NVSTR (0x00000100u) - #define FLASH_TEST_CTRL_NVSTR_MASK (0x00000100u) - #define FLASH_TEST_CTRL_NVSTR_BIT (8) - #define FLASH_TEST_CTRL_NVSTR_BITS (1) - /* SE field */ - #define FLASH_TEST_CTRL_SE (0x00000080u) - #define FLASH_TEST_CTRL_SE_MASK (0x00000080u) - #define FLASH_TEST_CTRL_SE_BIT (7) - #define FLASH_TEST_CTRL_SE_BITS (1) - /* IFREN field */ - #define FLASH_TEST_CTRL_IFREN (0x00000040u) - #define FLASH_TEST_CTRL_IFREN_MASK (0x00000040u) - #define FLASH_TEST_CTRL_IFREN_BIT (6) - #define FLASH_TEST_CTRL_IFREN_BITS (1) - /* YE field */ - #define FLASH_TEST_CTRL_YE (0x00000020u) - #define FLASH_TEST_CTRL_YE_MASK (0x00000020u) - #define FLASH_TEST_CTRL_YE_BIT (5) - #define FLASH_TEST_CTRL_YE_BITS (1) - /* XE field */ - #define FLASH_TEST_CTRL_XE (0x00000010u) - #define FLASH_TEST_CTRL_XE_MASK (0x00000010u) - #define FLASH_TEST_CTRL_XE_BIT (4) - #define FLASH_TEST_CTRL_XE_BITS (1) - /* SW_CTRL field */ - #define FLASH_TEST_CTRL_SW_CTRL (0x00000008u) - #define FLASH_TEST_CTRL_SW_CTRL_MASK (0x00000008u) - #define FLASH_TEST_CTRL_SW_CTRL_BIT (3) - #define FLASH_TEST_CTRL_SW_CTRL_BITS (1) - /* SW field */ - #define FLASH_TEST_CTRL_SW (0x00000006u) - #define FLASH_TEST_CTRL_SW_MASK (0x00000006u) - #define FLASH_TEST_CTRL_SW_BIT (1) - #define FLASH_TEST_CTRL_SW_BITS (2) - /* SW_EN field */ - #define FLASH_TEST_CTRL_SW_EN (0x00000001u) - #define FLASH_TEST_CTRL_SW_EN_MASK (0x00000001u) - #define FLASH_TEST_CTRL_SW_EN_BIT (0) - #define FLASH_TEST_CTRL_SW_EN_BITS (1) +/* TMR field */ +#define FLASH_TEST_CTRL_TMR (0x00001000u) +#define FLASH_TEST_CTRL_TMR_MASK (0x00001000u) +#define FLASH_TEST_CTRL_TMR_BIT (12) +#define FLASH_TEST_CTRL_TMR_BITS (1) +/* ERASE field */ +#define FLASH_TEST_CTRL_ERASE (0x00000800u) +#define FLASH_TEST_CTRL_ERASE_MASK (0x00000800u) +#define FLASH_TEST_CTRL_ERASE_BIT (11) +#define FLASH_TEST_CTRL_ERASE_BITS (1) +/* MAS1 field */ +#define FLASH_TEST_CTRL_MAS1 (0x00000400u) +#define FLASH_TEST_CTRL_MAS1_MASK (0x00000400u) +#define FLASH_TEST_CTRL_MAS1_BIT (10) +#define FLASH_TEST_CTRL_MAS1_BITS (1) +/* TEST_PROG field */ +#define FLASH_TEST_CTRL_TEST_PROG (0x00000200u) +#define FLASH_TEST_CTRL_TEST_PROG_MASK (0x00000200u) +#define FLASH_TEST_CTRL_TEST_PROG_BIT (9) +#define FLASH_TEST_CTRL_TEST_PROG_BITS (1) +/* NVSTR field */ +#define FLASH_TEST_CTRL_NVSTR (0x00000100u) +#define FLASH_TEST_CTRL_NVSTR_MASK (0x00000100u) +#define FLASH_TEST_CTRL_NVSTR_BIT (8) +#define FLASH_TEST_CTRL_NVSTR_BITS (1) +/* SE field */ +#define FLASH_TEST_CTRL_SE (0x00000080u) +#define FLASH_TEST_CTRL_SE_MASK (0x00000080u) +#define FLASH_TEST_CTRL_SE_BIT (7) +#define FLASH_TEST_CTRL_SE_BITS (1) +/* IFREN field */ +#define FLASH_TEST_CTRL_IFREN (0x00000040u) +#define FLASH_TEST_CTRL_IFREN_MASK (0x00000040u) +#define FLASH_TEST_CTRL_IFREN_BIT (6) +#define FLASH_TEST_CTRL_IFREN_BITS (1) +/* YE field */ +#define FLASH_TEST_CTRL_YE (0x00000020u) +#define FLASH_TEST_CTRL_YE_MASK (0x00000020u) +#define FLASH_TEST_CTRL_YE_BIT (5) +#define FLASH_TEST_CTRL_YE_BITS (1) +/* XE field */ +#define FLASH_TEST_CTRL_XE (0x00000010u) +#define FLASH_TEST_CTRL_XE_MASK (0x00000010u) +#define FLASH_TEST_CTRL_XE_BIT (4) +#define FLASH_TEST_CTRL_XE_BITS (1) +/* SW_CTRL field */ +#define FLASH_TEST_CTRL_SW_CTRL (0x00000008u) +#define FLASH_TEST_CTRL_SW_CTRL_MASK (0x00000008u) +#define FLASH_TEST_CTRL_SW_CTRL_BIT (3) +#define FLASH_TEST_CTRL_SW_CTRL_BITS (1) +/* SW field */ +#define FLASH_TEST_CTRL_SW (0x00000006u) +#define FLASH_TEST_CTRL_SW_MASK (0x00000006u) +#define FLASH_TEST_CTRL_SW_BIT (1) +#define FLASH_TEST_CTRL_SW_BITS (2) +/* SW_EN field */ +#define FLASH_TEST_CTRL_SW_EN (0x00000001u) +#define FLASH_TEST_CTRL_SW_EN_MASK (0x00000001u) +#define FLASH_TEST_CTRL_SW_EN_BIT (0) +#define FLASH_TEST_CTRL_SW_EN_BITS (1) #define FLASH_DATA0 *((volatile uint32_t *)0x40008084u) #define FLASH_DATA0_REG *((volatile uint32_t *)0x40008084u) #define FLASH_DATA0_ADDR (0x40008084u) #define FLASH_DATA0_RESET (0xFFFFFFFFu) - /* FDR0 field */ - #define FLASH_DATA0_FDR0 (0xFFFFFFFFu) - #define FLASH_DATA0_FDR0_MASK (0xFFFFFFFFu) - #define FLASH_DATA0_FDR0_BIT (0) - #define FLASH_DATA0_FDR0_BITS (32) +/* FDR0 field */ +#define FLASH_DATA0_FDR0 (0xFFFFFFFFu) +#define FLASH_DATA0_FDR0_MASK (0xFFFFFFFFu) +#define FLASH_DATA0_FDR0_BIT (0) +#define FLASH_DATA0_FDR0_BITS (32) /* EMU_REGS block */ #define DATA_EMU_REGS_BASE (0x40009000u) @@ -3249,11 +3249,11 @@ #define I_AM_AN_EMULATOR_REG *((volatile uint32_t *)0x40009000u) #define I_AM_AN_EMULATOR_ADDR (0x40009000u) #define I_AM_AN_EMULATOR_RESET (0x00000000u) - /* I_AM_AN_EMULATOR field */ - #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR (0x00000001u) - #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK (0x00000001u) - #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT (0) - #define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS (1) +/* I_AM_AN_EMULATOR field */ +#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR (0x00000001u) +#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK (0x00000001u) +#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT (0) +#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS (1) /* INTERRUPTS block */ #define BLOCK_INTERRUPTS_BASE (0x4000A000u) @@ -3264,1326 +3264,1326 @@ #define MAC_RX_INT_SRC_REG *((volatile uint32_t *)0x4000A000u) #define MAC_RX_INT_SRC_ADDR (0x4000A000u) #define MAC_RX_INT_SRC_RESET (0x00000000u) - /* TX_B_ACK_ERR_SRC field */ - #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC (0x00008000u) - #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_MASK (0x00008000u) - #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BIT (15) - #define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BITS (1) - /* TX_A_ACK_ERR_SRC field */ - #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC (0x00004000u) - #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_MASK (0x00004000u) - #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BIT (14) - #define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BITS (1) - /* RX_OVFLW_SRC field */ - #define MAC_RX_INT_SRC_RX_OVFLW_SRC (0x00002000u) - #define MAC_RX_INT_SRC_RX_OVFLW_SRC_MASK (0x00002000u) - #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BIT (13) - #define MAC_RX_INT_SRC_RX_OVFLW_SRC_BITS (1) - /* RX_ERROR_SRC field */ - #define MAC_RX_INT_SRC_RX_ERROR_SRC (0x00001000u) - #define MAC_RX_INT_SRC_RX_ERROR_SRC_MASK (0x00001000u) - #define MAC_RX_INT_SRC_RX_ERROR_SRC_BIT (12) - #define MAC_RX_INT_SRC_RX_ERROR_SRC_BITS (1) - /* BB_RX_LEN_ERR_SRC field */ - #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC (0x00000800u) - #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_MASK (0x00000800u) - #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BIT (11) - #define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BITS (1) - /* TX_COLL_RX_SRC field */ - #define MAC_RX_INT_SRC_TX_COLL_RX_SRC (0x00000400u) - #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_MASK (0x00000400u) - #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BIT (10) - #define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BITS (1) - /* RSSI_INST_MEAS_SRC field */ - #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC (0x00000200u) - #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_MASK (0x00000200u) - #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BIT (9) - #define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BITS (1) - /* TX_B_ACK_SRC field */ - #define MAC_RX_INT_SRC_TX_B_ACK_SRC (0x00000100u) - #define MAC_RX_INT_SRC_TX_B_ACK_SRC_MASK (0x00000100u) - #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BIT (8) - #define MAC_RX_INT_SRC_TX_B_ACK_SRC_BITS (1) - /* TX_A_ACK_SRC field */ - #define MAC_RX_INT_SRC_TX_A_ACK_SRC (0x00000080u) - #define MAC_RX_INT_SRC_TX_A_ACK_SRC_MASK (0x00000080u) - #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BIT (7) - #define MAC_RX_INT_SRC_TX_A_ACK_SRC_BITS (1) - /* RX_B_UNLOAD_COMP_SRC field */ - #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC (0x00000040u) - #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_MASK (0x00000040u) - #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BIT (6) - #define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BITS (1) - /* RX_A_UNLOAD_COMP_SRC field */ - #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC (0x00000020u) - #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_MASK (0x00000020u) - #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BIT (5) - #define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BITS (1) - /* RX_B_ADDR_REC_SRC field */ - #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC (0x00000010u) - #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_MASK (0x00000010u) - #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BIT (4) - #define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BITS (1) - /* RX_A_ADDR_REC_SRC field */ - #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC (0x00000008u) - #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_MASK (0x00000008u) - #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BIT (3) - #define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BITS (1) - /* RX_B_FILT_COMP_SRC field */ - #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC (0x00000004u) - #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_MASK (0x00000004u) - #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BIT (2) - #define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BITS (1) - /* RX_A_FILT_COMP_SRC field */ - #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC (0x00000002u) - #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_MASK (0x00000002u) - #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BIT (1) - #define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BITS (1) - /* RX_FRAME_SRC field */ - #define MAC_RX_INT_SRC_RX_FRAME_SRC (0x00000001u) - #define MAC_RX_INT_SRC_RX_FRAME_SRC_MASK (0x00000001u) - #define MAC_RX_INT_SRC_RX_FRAME_SRC_BIT (0) - #define MAC_RX_INT_SRC_RX_FRAME_SRC_BITS (1) +/* TX_B_ACK_ERR_SRC field */ +#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC (0x00008000u) +#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_MASK (0x00008000u) +#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BIT (15) +#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BITS (1) +/* TX_A_ACK_ERR_SRC field */ +#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC (0x00004000u) +#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_MASK (0x00004000u) +#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BIT (14) +#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BITS (1) +/* RX_OVFLW_SRC field */ +#define MAC_RX_INT_SRC_RX_OVFLW_SRC (0x00002000u) +#define MAC_RX_INT_SRC_RX_OVFLW_SRC_MASK (0x00002000u) +#define MAC_RX_INT_SRC_RX_OVFLW_SRC_BIT (13) +#define MAC_RX_INT_SRC_RX_OVFLW_SRC_BITS (1) +/* RX_ERROR_SRC field */ +#define MAC_RX_INT_SRC_RX_ERROR_SRC (0x00001000u) +#define MAC_RX_INT_SRC_RX_ERROR_SRC_MASK (0x00001000u) +#define MAC_RX_INT_SRC_RX_ERROR_SRC_BIT (12) +#define MAC_RX_INT_SRC_RX_ERROR_SRC_BITS (1) +/* BB_RX_LEN_ERR_SRC field */ +#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC (0x00000800u) +#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_MASK (0x00000800u) +#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BIT (11) +#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BITS (1) +/* TX_COLL_RX_SRC field */ +#define MAC_RX_INT_SRC_TX_COLL_RX_SRC (0x00000400u) +#define MAC_RX_INT_SRC_TX_COLL_RX_SRC_MASK (0x00000400u) +#define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BIT (10) +#define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BITS (1) +/* RSSI_INST_MEAS_SRC field */ +#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC (0x00000200u) +#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_MASK (0x00000200u) +#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BIT (9) +#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BITS (1) +/* TX_B_ACK_SRC field */ +#define MAC_RX_INT_SRC_TX_B_ACK_SRC (0x00000100u) +#define MAC_RX_INT_SRC_TX_B_ACK_SRC_MASK (0x00000100u) +#define MAC_RX_INT_SRC_TX_B_ACK_SRC_BIT (8) +#define MAC_RX_INT_SRC_TX_B_ACK_SRC_BITS (1) +/* TX_A_ACK_SRC field */ +#define MAC_RX_INT_SRC_TX_A_ACK_SRC (0x00000080u) +#define MAC_RX_INT_SRC_TX_A_ACK_SRC_MASK (0x00000080u) +#define MAC_RX_INT_SRC_TX_A_ACK_SRC_BIT (7) +#define MAC_RX_INT_SRC_TX_A_ACK_SRC_BITS (1) +/* RX_B_UNLOAD_COMP_SRC field */ +#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC (0x00000040u) +#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_MASK (0x00000040u) +#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BIT (6) +#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BITS (1) +/* RX_A_UNLOAD_COMP_SRC field */ +#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC (0x00000020u) +#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_MASK (0x00000020u) +#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BIT (5) +#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BITS (1) +/* RX_B_ADDR_REC_SRC field */ +#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC (0x00000010u) +#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_MASK (0x00000010u) +#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BIT (4) +#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BITS (1) +/* RX_A_ADDR_REC_SRC field */ +#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC (0x00000008u) +#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_MASK (0x00000008u) +#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BIT (3) +#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BITS (1) +/* RX_B_FILT_COMP_SRC field */ +#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC (0x00000004u) +#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_MASK (0x00000004u) +#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BIT (2) +#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BITS (1) +/* RX_A_FILT_COMP_SRC field */ +#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC (0x00000002u) +#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_MASK (0x00000002u) +#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BIT (1) +#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BITS (1) +/* RX_FRAME_SRC field */ +#define MAC_RX_INT_SRC_RX_FRAME_SRC (0x00000001u) +#define MAC_RX_INT_SRC_RX_FRAME_SRC_MASK (0x00000001u) +#define MAC_RX_INT_SRC_RX_FRAME_SRC_BIT (0) +#define MAC_RX_INT_SRC_RX_FRAME_SRC_BITS (1) #define MAC_TX_INT_SRC *((volatile uint32_t *)0x4000A004u) #define MAC_TX_INT_SRC_REG *((volatile uint32_t *)0x4000A004u) #define MAC_TX_INT_SRC_ADDR (0x4000A004u) #define MAC_TX_INT_SRC_RESET (0x00000000u) - /* RX_B_ACK_SRC field */ - #define MAC_TX_INT_SRC_RX_B_ACK_SRC (0x00000800u) - #define MAC_TX_INT_SRC_RX_B_ACK_SRC_MASK (0x00000800u) - #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BIT (11) - #define MAC_TX_INT_SRC_RX_B_ACK_SRC_BITS (1) - /* RX_A_ACK_SRC field */ - #define MAC_TX_INT_SRC_RX_A_ACK_SRC (0x00000400u) - #define MAC_TX_INT_SRC_RX_A_ACK_SRC_MASK (0x00000400u) - #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BIT (10) - #define MAC_TX_INT_SRC_RX_A_ACK_SRC_BITS (1) - /* TX_B_UNLOAD_SRC field */ - #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC (0x00000200u) - #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_MASK (0x00000200u) - #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BIT (9) - #define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BITS (1) - /* TX_A_UNLOAD_SRC field */ - #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC (0x00000100u) - #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_MASK (0x00000100u) - #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BIT (8) - #define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BITS (1) - /* ACK_EXPIRED_SRC field */ - #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC (0x00000080u) - #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_MASK (0x00000080u) - #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BIT (7) - #define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BITS (1) - /* TX_LOCK_FAIL_SRC field */ - #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC (0x00000040u) - #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_MASK (0x00000040u) - #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BIT (6) - #define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BITS (1) - /* TX_UNDERFLOW_SRC field */ - #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC (0x00000020u) - #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_MASK (0x00000020u) - #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BIT (5) - #define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BITS (1) - /* CCA_FAIL_SRC field */ - #define MAC_TX_INT_SRC_CCA_FAIL_SRC (0x00000010u) - #define MAC_TX_INT_SRC_CCA_FAIL_SRC_MASK (0x00000010u) - #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BIT (4) - #define MAC_TX_INT_SRC_CCA_FAIL_SRC_BITS (1) - /* SFD_SENT_SRC field */ - #define MAC_TX_INT_SRC_SFD_SENT_SRC (0x00000008u) - #define MAC_TX_INT_SRC_SFD_SENT_SRC_MASK (0x00000008u) - #define MAC_TX_INT_SRC_SFD_SENT_SRC_BIT (3) - #define MAC_TX_INT_SRC_SFD_SENT_SRC_BITS (1) - /* BO_COMPLETE_SRC field */ - #define MAC_TX_INT_SRC_BO_COMPLETE_SRC (0x00000004u) - #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_MASK (0x00000004u) - #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BIT (2) - #define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BITS (1) - /* RX_ACK_SRC field */ - #define MAC_TX_INT_SRC_RX_ACK_SRC (0x00000002u) - #define MAC_TX_INT_SRC_RX_ACK_SRC_MASK (0x00000002u) - #define MAC_TX_INT_SRC_RX_ACK_SRC_BIT (1) - #define MAC_TX_INT_SRC_RX_ACK_SRC_BITS (1) - /* TX_COMPLETE_SRC field */ - #define MAC_TX_INT_SRC_TX_COMPLETE_SRC (0x00000001u) - #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_MASK (0x00000001u) - #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT (0) - #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS (1) +/* RX_B_ACK_SRC field */ +#define MAC_TX_INT_SRC_RX_B_ACK_SRC (0x00000800u) +#define MAC_TX_INT_SRC_RX_B_ACK_SRC_MASK (0x00000800u) +#define MAC_TX_INT_SRC_RX_B_ACK_SRC_BIT (11) +#define MAC_TX_INT_SRC_RX_B_ACK_SRC_BITS (1) +/* RX_A_ACK_SRC field */ +#define MAC_TX_INT_SRC_RX_A_ACK_SRC (0x00000400u) +#define MAC_TX_INT_SRC_RX_A_ACK_SRC_MASK (0x00000400u) +#define MAC_TX_INT_SRC_RX_A_ACK_SRC_BIT (10) +#define MAC_TX_INT_SRC_RX_A_ACK_SRC_BITS (1) +/* TX_B_UNLOAD_SRC field */ +#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC (0x00000200u) +#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_MASK (0x00000200u) +#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BIT (9) +#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BITS (1) +/* TX_A_UNLOAD_SRC field */ +#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC (0x00000100u) +#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_MASK (0x00000100u) +#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BIT (8) +#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BITS (1) +/* ACK_EXPIRED_SRC field */ +#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC (0x00000080u) +#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_MASK (0x00000080u) +#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BIT (7) +#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BITS (1) +/* TX_LOCK_FAIL_SRC field */ +#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC (0x00000040u) +#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_MASK (0x00000040u) +#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BIT (6) +#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BITS (1) +/* TX_UNDERFLOW_SRC field */ +#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC (0x00000020u) +#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_MASK (0x00000020u) +#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BIT (5) +#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BITS (1) +/* CCA_FAIL_SRC field */ +#define MAC_TX_INT_SRC_CCA_FAIL_SRC (0x00000010u) +#define MAC_TX_INT_SRC_CCA_FAIL_SRC_MASK (0x00000010u) +#define MAC_TX_INT_SRC_CCA_FAIL_SRC_BIT (4) +#define MAC_TX_INT_SRC_CCA_FAIL_SRC_BITS (1) +/* SFD_SENT_SRC field */ +#define MAC_TX_INT_SRC_SFD_SENT_SRC (0x00000008u) +#define MAC_TX_INT_SRC_SFD_SENT_SRC_MASK (0x00000008u) +#define MAC_TX_INT_SRC_SFD_SENT_SRC_BIT (3) +#define MAC_TX_INT_SRC_SFD_SENT_SRC_BITS (1) +/* BO_COMPLETE_SRC field */ +#define MAC_TX_INT_SRC_BO_COMPLETE_SRC (0x00000004u) +#define MAC_TX_INT_SRC_BO_COMPLETE_SRC_MASK (0x00000004u) +#define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BIT (2) +#define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BITS (1) +/* RX_ACK_SRC field */ +#define MAC_TX_INT_SRC_RX_ACK_SRC (0x00000002u) +#define MAC_TX_INT_SRC_RX_ACK_SRC_MASK (0x00000002u) +#define MAC_TX_INT_SRC_RX_ACK_SRC_BIT (1) +#define MAC_TX_INT_SRC_RX_ACK_SRC_BITS (1) +/* TX_COMPLETE_SRC field */ +#define MAC_TX_INT_SRC_TX_COMPLETE_SRC (0x00000001u) +#define MAC_TX_INT_SRC_TX_COMPLETE_SRC_MASK (0x00000001u) +#define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT (0) +#define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS (1) #define MAC_TIMER_INT_SRC *((volatile uint32_t *)0x4000A008u) #define MAC_TIMER_INT_SRC_REG *((volatile uint32_t *)0x4000A008u) #define MAC_TIMER_INT_SRC_ADDR (0x4000A008u) #define MAC_TIMER_INT_SRC_RESET (0x00000000u) - /* TIMER_COMP_B_SRC field */ - #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC (0x00000004u) - #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_MASK (0x00000004u) - #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BIT (2) - #define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BITS (1) - /* TIMER_COMP_A_SRC field */ - #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC (0x00000002u) - #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_MASK (0x00000002u) - #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BIT (1) - #define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BITS (1) - /* TIMER_WRAP_SRC field */ - #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC (0x00000001u) - #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_MASK (0x00000001u) - #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT (0) - #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS (1) +/* TIMER_COMP_B_SRC field */ +#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC (0x00000004u) +#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_MASK (0x00000004u) +#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BIT (2) +#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BITS (1) +/* TIMER_COMP_A_SRC field */ +#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC (0x00000002u) +#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_MASK (0x00000002u) +#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BIT (1) +#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BITS (1) +/* TIMER_WRAP_SRC field */ +#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC (0x00000001u) +#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_MASK (0x00000001u) +#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT (0) +#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS (1) #define BB_INT_SRC *((volatile uint32_t *)0x4000A00Cu) #define BB_INT_SRC_REG *((volatile uint32_t *)0x4000A00Cu) #define BB_INT_SRC_ADDR (0x4000A00Cu) #define BB_INT_SRC_RESET (0x00000000u) - /* RSSI_INT_SRC field */ - #define BB_INT_SRC_RSSI_INT_SRC (0x00000002u) - #define BB_INT_SRC_RSSI_INT_SRC_MASK (0x00000002u) - #define BB_INT_SRC_RSSI_INT_SRC_BIT (1) - #define BB_INT_SRC_RSSI_INT_SRC_BITS (1) - /* BASEBAND_INT_SRC field */ - #define BB_INT_SRC_BASEBAND_INT_SRC (0x00000001u) - #define BB_INT_SRC_BASEBAND_INT_SRC_MASK (0x00000001u) - #define BB_INT_SRC_BASEBAND_INT_SRC_BIT (0) - #define BB_INT_SRC_BASEBAND_INT_SRC_BITS (1) +/* RSSI_INT_SRC field */ +#define BB_INT_SRC_RSSI_INT_SRC (0x00000002u) +#define BB_INT_SRC_RSSI_INT_SRC_MASK (0x00000002u) +#define BB_INT_SRC_RSSI_INT_SRC_BIT (1) +#define BB_INT_SRC_RSSI_INT_SRC_BITS (1) +/* BASEBAND_INT_SRC field */ +#define BB_INT_SRC_BASEBAND_INT_SRC (0x00000001u) +#define BB_INT_SRC_BASEBAND_INT_SRC_MASK (0x00000001u) +#define BB_INT_SRC_BASEBAND_INT_SRC_BIT (0) +#define BB_INT_SRC_BASEBAND_INT_SRC_BITS (1) #define SEC_INT_SRC *((volatile uint32_t *)0x4000A010u) #define SEC_INT_SRC_REG *((volatile uint32_t *)0x4000A010u) #define SEC_INT_SRC_ADDR (0x4000A010u) #define SEC_INT_SRC_RESET (0x00000000u) - /* CT_WORD_VALID_SRC field */ - #define SEC_INT_SRC_CT_WORD_VALID_SRC (0x00000004u) - #define SEC_INT_SRC_CT_WORD_VALID_SRC_MASK (0x00000004u) - #define SEC_INT_SRC_CT_WORD_VALID_SRC_BIT (2) - #define SEC_INT_SRC_CT_WORD_VALID_SRC_BITS (1) - /* PT_WORD_REQ_SRC field */ - #define SEC_INT_SRC_PT_WORD_REQ_SRC (0x00000002u) - #define SEC_INT_SRC_PT_WORD_REQ_SRC_MASK (0x00000002u) - #define SEC_INT_SRC_PT_WORD_REQ_SRC_BIT (1) - #define SEC_INT_SRC_PT_WORD_REQ_SRC_BITS (1) - /* ENC_COMPLETE_SRC field */ - #define SEC_INT_SRC_ENC_COMPLETE_SRC (0x00000001u) - #define SEC_INT_SRC_ENC_COMPLETE_SRC_MASK (0x00000001u) - #define SEC_INT_SRC_ENC_COMPLETE_SRC_BIT (0) - #define SEC_INT_SRC_ENC_COMPLETE_SRC_BITS (1) +/* CT_WORD_VALID_SRC field */ +#define SEC_INT_SRC_CT_WORD_VALID_SRC (0x00000004u) +#define SEC_INT_SRC_CT_WORD_VALID_SRC_MASK (0x00000004u) +#define SEC_INT_SRC_CT_WORD_VALID_SRC_BIT (2) +#define SEC_INT_SRC_CT_WORD_VALID_SRC_BITS (1) +/* PT_WORD_REQ_SRC field */ +#define SEC_INT_SRC_PT_WORD_REQ_SRC (0x00000002u) +#define SEC_INT_SRC_PT_WORD_REQ_SRC_MASK (0x00000002u) +#define SEC_INT_SRC_PT_WORD_REQ_SRC_BIT (1) +#define SEC_INT_SRC_PT_WORD_REQ_SRC_BITS (1) +/* ENC_COMPLETE_SRC field */ +#define SEC_INT_SRC_ENC_COMPLETE_SRC (0x00000001u) +#define SEC_INT_SRC_ENC_COMPLETE_SRC_MASK (0x00000001u) +#define SEC_INT_SRC_ENC_COMPLETE_SRC_BIT (0) +#define SEC_INT_SRC_ENC_COMPLETE_SRC_BITS (1) #define INT_SLEEPTMRFLAG *((volatile uint32_t *)0x4000A014u) #define INT_SLEEPTMRFLAG_REG *((volatile uint32_t *)0x4000A014u) #define INT_SLEEPTMRFLAG_ADDR (0x4000A014u) #define INT_SLEEPTMRFLAG_RESET (0x00000000u) - /* INT_SLEEPTMRCMPB field */ - #define INT_SLEEPTMRCMPB (0x00000004u) - #define INT_SLEEPTMRCMPB_MASK (0x00000004u) - #define INT_SLEEPTMRCMPB_BIT (2) - #define INT_SLEEPTMRCMPB_BITS (1) - /* INT_SLEEPTMRCMPA field */ - #define INT_SLEEPTMRCMPA (0x00000002u) - #define INT_SLEEPTMRCMPA_MASK (0x00000002u) - #define INT_SLEEPTMRCMPA_BIT (1) - #define INT_SLEEPTMRCMPA_BITS (1) - /* INT_SLEEPTMRWRAP field */ - #define INT_SLEEPTMRWRAP (0x00000001u) - #define INT_SLEEPTMRWRAP_MASK (0x00000001u) - #define INT_SLEEPTMRWRAP_BIT (0) - #define INT_SLEEPTMRWRAP_BITS (1) +/* INT_SLEEPTMRCMPB field */ +#define INT_SLEEPTMRCMPB (0x00000004u) +#define INT_SLEEPTMRCMPB_MASK (0x00000004u) +#define INT_SLEEPTMRCMPB_BIT (2) +#define INT_SLEEPTMRCMPB_BITS (1) +/* INT_SLEEPTMRCMPA field */ +#define INT_SLEEPTMRCMPA (0x00000002u) +#define INT_SLEEPTMRCMPA_MASK (0x00000002u) +#define INT_SLEEPTMRCMPA_BIT (1) +#define INT_SLEEPTMRCMPA_BITS (1) +/* INT_SLEEPTMRWRAP field */ +#define INT_SLEEPTMRWRAP (0x00000001u) +#define INT_SLEEPTMRWRAP_MASK (0x00000001u) +#define INT_SLEEPTMRWRAP_BIT (0) +#define INT_SLEEPTMRWRAP_BITS (1) #define INT_MGMTFLAG *((volatile uint32_t *)0x4000A018u) #define INT_MGMTFLAG_REG *((volatile uint32_t *)0x4000A018u) #define INT_MGMTFLAG_ADDR (0x4000A018u) #define INT_MGMTFLAG_RESET (0x00000000u) - /* INT_MGMTDMAPROT field */ - #define INT_MGMTDMAPROT (0x00000010u) - #define INT_MGMTDMAPROT_MASK (0x00000010u) - #define INT_MGMTDMAPROT_BIT (4) - #define INT_MGMTDMAPROT_BITS (1) - /* INT_MGMTCALADC field */ - #define INT_MGMTCALADC (0x00000008u) - #define INT_MGMTCALADC_MASK (0x00000008u) - #define INT_MGMTCALADC_BIT (3) - #define INT_MGMTCALADC_BITS (1) - /* INT_MGMTFPEC field */ - #define INT_MGMTFPEC (0x00000004u) - #define INT_MGMTFPEC_MASK (0x00000004u) - #define INT_MGMTFPEC_BIT (2) - #define INT_MGMTFPEC_BITS (1) - /* INT_MGMTOSC24MHI field */ - #define INT_MGMTOSC24MHI (0x00000002u) - #define INT_MGMTOSC24MHI_MASK (0x00000002u) - #define INT_MGMTOSC24MHI_BIT (1) - #define INT_MGMTOSC24MHI_BITS (1) - /* INT_MGMTOSC24MLO field */ - #define INT_MGMTOSC24MLO (0x00000001u) - #define INT_MGMTOSC24MLO_MASK (0x00000001u) - #define INT_MGMTOSC24MLO_BIT (0) - #define INT_MGMTOSC24MLO_BITS (1) +/* INT_MGMTDMAPROT field */ +#define INT_MGMTDMAPROT (0x00000010u) +#define INT_MGMTDMAPROT_MASK (0x00000010u) +#define INT_MGMTDMAPROT_BIT (4) +#define INT_MGMTDMAPROT_BITS (1) +/* INT_MGMTCALADC field */ +#define INT_MGMTCALADC (0x00000008u) +#define INT_MGMTCALADC_MASK (0x00000008u) +#define INT_MGMTCALADC_BIT (3) +#define INT_MGMTCALADC_BITS (1) +/* INT_MGMTFPEC field */ +#define INT_MGMTFPEC (0x00000004u) +#define INT_MGMTFPEC_MASK (0x00000004u) +#define INT_MGMTFPEC_BIT (2) +#define INT_MGMTFPEC_BITS (1) +/* INT_MGMTOSC24MHI field */ +#define INT_MGMTOSC24MHI (0x00000002u) +#define INT_MGMTOSC24MHI_MASK (0x00000002u) +#define INT_MGMTOSC24MHI_BIT (1) +#define INT_MGMTOSC24MHI_BITS (1) +/* INT_MGMTOSC24MLO field */ +#define INT_MGMTOSC24MLO (0x00000001u) +#define INT_MGMTOSC24MLO_MASK (0x00000001u) +#define INT_MGMTOSC24MLO_BIT (0) +#define INT_MGMTOSC24MLO_BITS (1) #define INT_NMIFLAG *((volatile uint32_t *)0x4000A01Cu) #define INT_NMIFLAG_REG *((volatile uint32_t *)0x4000A01Cu) #define INT_NMIFLAG_ADDR (0x4000A01Cu) #define INT_NMIFLAG_RESET (0x00000000u) - /* INT_NMICLK24M field */ - #define INT_NMICLK24M (0x00000002u) - #define INT_NMICLK24M_MASK (0x00000002u) - #define INT_NMICLK24M_BIT (1) - #define INT_NMICLK24M_BITS (1) - /* INT_NMIWDOG field */ - #define INT_NMIWDOG (0x00000001u) - #define INT_NMIWDOG_MASK (0x00000001u) - #define INT_NMIWDOG_BIT (0) - #define INT_NMIWDOG_BITS (1) +/* INT_NMICLK24M field */ +#define INT_NMICLK24M (0x00000002u) +#define INT_NMICLK24M_MASK (0x00000002u) +#define INT_NMICLK24M_BIT (1) +#define INT_NMICLK24M_BITS (1) +/* INT_NMIWDOG field */ +#define INT_NMIWDOG (0x00000001u) +#define INT_NMIWDOG_MASK (0x00000001u) +#define INT_NMIWDOG_BIT (0) +#define INT_NMIWDOG_BITS (1) #define INT_SLEEPTMRFORCE *((volatile uint32_t *)0x4000A020u) #define INT_SLEEPTMRFORCE_REG *((volatile uint32_t *)0x4000A020u) #define INT_SLEEPTMRFORCE_ADDR (0x4000A020u) #define INT_SLEEPTMRFORCE_RESET (0x00000000u) - /* INT_SLEEPTMRCMPB field */ - #define INT_SLEEPTMRCMPB (0x00000004u) - #define INT_SLEEPTMRCMPB_MASK (0x00000004u) - #define INT_SLEEPTMRCMPB_BIT (2) - #define INT_SLEEPTMRCMPB_BITS (1) - /* INT_SLEEPTMRCMPA field */ - #define INT_SLEEPTMRCMPA (0x00000002u) - #define INT_SLEEPTMRCMPA_MASK (0x00000002u) - #define INT_SLEEPTMRCMPA_BIT (1) - #define INT_SLEEPTMRCMPA_BITS (1) - /* INT_SLEEPTMRWRAP field */ - #define INT_SLEEPTMRWRAP (0x00000001u) - #define INT_SLEEPTMRWRAP_MASK (0x00000001u) - #define INT_SLEEPTMRWRAP_BIT (0) - #define INT_SLEEPTMRWRAP_BITS (1) +/* INT_SLEEPTMRCMPB field */ +#define INT_SLEEPTMRCMPB (0x00000004u) +#define INT_SLEEPTMRCMPB_MASK (0x00000004u) +#define INT_SLEEPTMRCMPB_BIT (2) +#define INT_SLEEPTMRCMPB_BITS (1) +/* INT_SLEEPTMRCMPA field */ +#define INT_SLEEPTMRCMPA (0x00000002u) +#define INT_SLEEPTMRCMPA_MASK (0x00000002u) +#define INT_SLEEPTMRCMPA_BIT (1) +#define INT_SLEEPTMRCMPA_BITS (1) +/* INT_SLEEPTMRWRAP field */ +#define INT_SLEEPTMRWRAP (0x00000001u) +#define INT_SLEEPTMRWRAP_MASK (0x00000001u) +#define INT_SLEEPTMRWRAP_BIT (0) +#define INT_SLEEPTMRWRAP_BITS (1) #define TEST_FORCE_ALL_INT *((volatile uint32_t *)0x4000A024u) #define TEST_FORCE_ALL_INT_REG *((volatile uint32_t *)0x4000A024u) #define TEST_FORCE_ALL_INT_ADDR (0x4000A024u) #define TEST_FORCE_ALL_INT_RESET (0x00000000u) - /* FORCE_ALL_INT field */ - #define TEST_FORCE_ALL_INT_FORCE_ALL_INT (0x00000001u) - #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_MASK (0x00000001u) - #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT (0) - #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS (1) +/* FORCE_ALL_INT field */ +#define TEST_FORCE_ALL_INT_FORCE_ALL_INT (0x00000001u) +#define TEST_FORCE_ALL_INT_FORCE_ALL_INT_MASK (0x00000001u) +#define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT (0) +#define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS (1) #define MAC_RX_INT_MASK *((volatile uint32_t *)0x4000A040u) #define MAC_RX_INT_MASK_REG *((volatile uint32_t *)0x4000A040u) #define MAC_RX_INT_MASK_ADDR (0x4000A040u) #define MAC_RX_INT_MASK_RESET (0x00000000u) - /* TX_B_ACK_ERR_MSK field */ - #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK (0x00008000u) - #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_MASK (0x00008000u) - #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BIT (15) - #define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BITS (1) - /* TX_A_ACK_ERR_MSK field */ - #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK (0x00004000u) - #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_MASK (0x00004000u) - #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BIT (14) - #define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BITS (1) - /* RX_OVFLW_MSK field */ - #define MAC_RX_INT_MASK_RX_OVFLW_MSK (0x00002000u) - #define MAC_RX_INT_MASK_RX_OVFLW_MSK_MASK (0x00002000u) - #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BIT (13) - #define MAC_RX_INT_MASK_RX_OVFLW_MSK_BITS (1) - /* RX_ERROR_MSK field */ - #define MAC_RX_INT_MASK_RX_ERROR_MSK (0x00001000u) - #define MAC_RX_INT_MASK_RX_ERROR_MSK_MASK (0x00001000u) - #define MAC_RX_INT_MASK_RX_ERROR_MSK_BIT (12) - #define MAC_RX_INT_MASK_RX_ERROR_MSK_BITS (1) - /* BB_RX_LEN_ERR_MSK field */ - #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK (0x00000800u) - #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_MASK (0x00000800u) - #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BIT (11) - #define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BITS (1) - /* TX_COLL_RX_MSK field */ - #define MAC_RX_INT_MASK_TX_COLL_RX_MSK (0x00000400u) - #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_MASK (0x00000400u) - #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BIT (10) - #define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BITS (1) - /* RSSI_INST_MEAS_MSK field */ - #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK (0x00000200u) - #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_MASK (0x00000200u) - #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BIT (9) - #define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BITS (1) - /* TX_B_ACK_MSK field */ - #define MAC_RX_INT_MASK_TX_B_ACK_MSK (0x00000100u) - #define MAC_RX_INT_MASK_TX_B_ACK_MSK_MASK (0x00000100u) - #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BIT (8) - #define MAC_RX_INT_MASK_TX_B_ACK_MSK_BITS (1) - /* TX_A_ACK_MSK field */ - #define MAC_RX_INT_MASK_TX_A_ACK_MSK (0x00000080u) - #define MAC_RX_INT_MASK_TX_A_ACK_MSK_MASK (0x00000080u) - #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BIT (7) - #define MAC_RX_INT_MASK_TX_A_ACK_MSK_BITS (1) - /* RX_B_UNLOAD_COMP_MSK field */ - #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK (0x00000040u) - #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_MASK (0x00000040u) - #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BIT (6) - #define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BITS (1) - /* RX_A_UNLOAD_COMP_MSK field */ - #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK (0x00000020u) - #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_MASK (0x00000020u) - #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BIT (5) - #define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BITS (1) - /* RX_B_ADDR_REC_MSK field */ - #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK (0x00000010u) - #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_MASK (0x00000010u) - #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BIT (4) - #define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BITS (1) - /* RX_A_ADDR_REC_MSK field */ - #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK (0x00000008u) - #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_MASK (0x00000008u) - #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BIT (3) - #define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BITS (1) - /* RX_B_FILT_COMP_MSK field */ - #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK (0x00000004u) - #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_MASK (0x00000004u) - #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BIT (2) - #define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BITS (1) - /* RX_A_FILT_COMP_MSK field */ - #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK (0x00000002u) - #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_MASK (0x00000002u) - #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BIT (1) - #define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BITS (1) - /* RX_FRAME_MSK field */ - #define MAC_RX_INT_MASK_RX_FRAME_MSK (0x00000001u) - #define MAC_RX_INT_MASK_RX_FRAME_MSK_MASK (0x00000001u) - #define MAC_RX_INT_MASK_RX_FRAME_MSK_BIT (0) - #define MAC_RX_INT_MASK_RX_FRAME_MSK_BITS (1) +/* TX_B_ACK_ERR_MSK field */ +#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK (0x00008000u) +#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_MASK (0x00008000u) +#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BIT (15) +#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BITS (1) +/* TX_A_ACK_ERR_MSK field */ +#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK (0x00004000u) +#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_MASK (0x00004000u) +#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BIT (14) +#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BITS (1) +/* RX_OVFLW_MSK field */ +#define MAC_RX_INT_MASK_RX_OVFLW_MSK (0x00002000u) +#define MAC_RX_INT_MASK_RX_OVFLW_MSK_MASK (0x00002000u) +#define MAC_RX_INT_MASK_RX_OVFLW_MSK_BIT (13) +#define MAC_RX_INT_MASK_RX_OVFLW_MSK_BITS (1) +/* RX_ERROR_MSK field */ +#define MAC_RX_INT_MASK_RX_ERROR_MSK (0x00001000u) +#define MAC_RX_INT_MASK_RX_ERROR_MSK_MASK (0x00001000u) +#define MAC_RX_INT_MASK_RX_ERROR_MSK_BIT (12) +#define MAC_RX_INT_MASK_RX_ERROR_MSK_BITS (1) +/* BB_RX_LEN_ERR_MSK field */ +#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK (0x00000800u) +#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_MASK (0x00000800u) +#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BIT (11) +#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BITS (1) +/* TX_COLL_RX_MSK field */ +#define MAC_RX_INT_MASK_TX_COLL_RX_MSK (0x00000400u) +#define MAC_RX_INT_MASK_TX_COLL_RX_MSK_MASK (0x00000400u) +#define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BIT (10) +#define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BITS (1) +/* RSSI_INST_MEAS_MSK field */ +#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK (0x00000200u) +#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_MASK (0x00000200u) +#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BIT (9) +#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BITS (1) +/* TX_B_ACK_MSK field */ +#define MAC_RX_INT_MASK_TX_B_ACK_MSK (0x00000100u) +#define MAC_RX_INT_MASK_TX_B_ACK_MSK_MASK (0x00000100u) +#define MAC_RX_INT_MASK_TX_B_ACK_MSK_BIT (8) +#define MAC_RX_INT_MASK_TX_B_ACK_MSK_BITS (1) +/* TX_A_ACK_MSK field */ +#define MAC_RX_INT_MASK_TX_A_ACK_MSK (0x00000080u) +#define MAC_RX_INT_MASK_TX_A_ACK_MSK_MASK (0x00000080u) +#define MAC_RX_INT_MASK_TX_A_ACK_MSK_BIT (7) +#define MAC_RX_INT_MASK_TX_A_ACK_MSK_BITS (1) +/* RX_B_UNLOAD_COMP_MSK field */ +#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK (0x00000040u) +#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_MASK (0x00000040u) +#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BIT (6) +#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BITS (1) +/* RX_A_UNLOAD_COMP_MSK field */ +#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK (0x00000020u) +#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_MASK (0x00000020u) +#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BIT (5) +#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BITS (1) +/* RX_B_ADDR_REC_MSK field */ +#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK (0x00000010u) +#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_MASK (0x00000010u) +#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BIT (4) +#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BITS (1) +/* RX_A_ADDR_REC_MSK field */ +#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK (0x00000008u) +#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_MASK (0x00000008u) +#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BIT (3) +#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BITS (1) +/* RX_B_FILT_COMP_MSK field */ +#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK (0x00000004u) +#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_MASK (0x00000004u) +#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BIT (2) +#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BITS (1) +/* RX_A_FILT_COMP_MSK field */ +#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK (0x00000002u) +#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_MASK (0x00000002u) +#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BIT (1) +#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BITS (1) +/* RX_FRAME_MSK field */ +#define MAC_RX_INT_MASK_RX_FRAME_MSK (0x00000001u) +#define MAC_RX_INT_MASK_RX_FRAME_MSK_MASK (0x00000001u) +#define MAC_RX_INT_MASK_RX_FRAME_MSK_BIT (0) +#define MAC_RX_INT_MASK_RX_FRAME_MSK_BITS (1) #define MAC_TX_INT_MASK *((volatile uint32_t *)0x4000A044u) #define MAC_TX_INT_MASK_REG *((volatile uint32_t *)0x4000A044u) #define MAC_TX_INT_MASK_ADDR (0x4000A044u) #define MAC_TX_INT_MASK_RESET (0x00000000u) - /* RX_B_ACK_MSK field */ - #define MAC_TX_INT_MASK_RX_B_ACK_MSK (0x00000800u) - #define MAC_TX_INT_MASK_RX_B_ACK_MSK_MASK (0x00000800u) - #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BIT (11) - #define MAC_TX_INT_MASK_RX_B_ACK_MSK_BITS (1) - /* RX_A_ACK_MSK field */ - #define MAC_TX_INT_MASK_RX_A_ACK_MSK (0x00000400u) - #define MAC_TX_INT_MASK_RX_A_ACK_MSK_MASK (0x00000400u) - #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BIT (10) - #define MAC_TX_INT_MASK_RX_A_ACK_MSK_BITS (1) - /* TX_B_UNLOAD_MSK field */ - #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK (0x00000200u) - #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_MASK (0x00000200u) - #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BIT (9) - #define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BITS (1) - /* TX_A_UNLOAD_MSK field */ - #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK (0x00000100u) - #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_MASK (0x00000100u) - #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BIT (8) - #define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BITS (1) - /* ACK_EXPIRED_MSK field */ - #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK (0x00000080u) - #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_MASK (0x00000080u) - #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BIT (7) - #define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BITS (1) - /* TX_LOCK_FAIL_MSK field */ - #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK (0x00000040u) - #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_MASK (0x00000040u) - #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BIT (6) - #define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BITS (1) - /* TX_UNDERFLOW_MSK field */ - #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK (0x00000020u) - #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_MASK (0x00000020u) - #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BIT (5) - #define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BITS (1) - /* CCA_FAIL_MSK field */ - #define MAC_TX_INT_MASK_CCA_FAIL_MSK (0x00000010u) - #define MAC_TX_INT_MASK_CCA_FAIL_MSK_MASK (0x00000010u) - #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BIT (4) - #define MAC_TX_INT_MASK_CCA_FAIL_MSK_BITS (1) - /* SFD_SENT_MSK field */ - #define MAC_TX_INT_MASK_SFD_SENT_MSK (0x00000008u) - #define MAC_TX_INT_MASK_SFD_SENT_MSK_MASK (0x00000008u) - #define MAC_TX_INT_MASK_SFD_SENT_MSK_BIT (3) - #define MAC_TX_INT_MASK_SFD_SENT_MSK_BITS (1) - /* BO_COMPLETE_MSK field */ - #define MAC_TX_INT_MASK_BO_COMPLETE_MSK (0x00000004u) - #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_MASK (0x00000004u) - #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BIT (2) - #define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BITS (1) - /* RX_ACK_MSK field */ - #define MAC_TX_INT_MASK_RX_ACK_MSK (0x00000002u) - #define MAC_TX_INT_MASK_RX_ACK_MSK_MASK (0x00000002u) - #define MAC_TX_INT_MASK_RX_ACK_MSK_BIT (1) - #define MAC_TX_INT_MASK_RX_ACK_MSK_BITS (1) - /* TX_COMPLETE_MSK field */ - #define MAC_TX_INT_MASK_TX_COMPLETE_MSK (0x00000001u) - #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_MASK (0x00000001u) - #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT (0) - #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS (1) +/* RX_B_ACK_MSK field */ +#define MAC_TX_INT_MASK_RX_B_ACK_MSK (0x00000800u) +#define MAC_TX_INT_MASK_RX_B_ACK_MSK_MASK (0x00000800u) +#define MAC_TX_INT_MASK_RX_B_ACK_MSK_BIT (11) +#define MAC_TX_INT_MASK_RX_B_ACK_MSK_BITS (1) +/* RX_A_ACK_MSK field */ +#define MAC_TX_INT_MASK_RX_A_ACK_MSK (0x00000400u) +#define MAC_TX_INT_MASK_RX_A_ACK_MSK_MASK (0x00000400u) +#define MAC_TX_INT_MASK_RX_A_ACK_MSK_BIT (10) +#define MAC_TX_INT_MASK_RX_A_ACK_MSK_BITS (1) +/* TX_B_UNLOAD_MSK field */ +#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK (0x00000200u) +#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_MASK (0x00000200u) +#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BIT (9) +#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BITS (1) +/* TX_A_UNLOAD_MSK field */ +#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK (0x00000100u) +#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_MASK (0x00000100u) +#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BIT (8) +#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BITS (1) +/* ACK_EXPIRED_MSK field */ +#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK (0x00000080u) +#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_MASK (0x00000080u) +#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BIT (7) +#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BITS (1) +/* TX_LOCK_FAIL_MSK field */ +#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK (0x00000040u) +#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_MASK (0x00000040u) +#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BIT (6) +#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BITS (1) +/* TX_UNDERFLOW_MSK field */ +#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK (0x00000020u) +#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_MASK (0x00000020u) +#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BIT (5) +#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BITS (1) +/* CCA_FAIL_MSK field */ +#define MAC_TX_INT_MASK_CCA_FAIL_MSK (0x00000010u) +#define MAC_TX_INT_MASK_CCA_FAIL_MSK_MASK (0x00000010u) +#define MAC_TX_INT_MASK_CCA_FAIL_MSK_BIT (4) +#define MAC_TX_INT_MASK_CCA_FAIL_MSK_BITS (1) +/* SFD_SENT_MSK field */ +#define MAC_TX_INT_MASK_SFD_SENT_MSK (0x00000008u) +#define MAC_TX_INT_MASK_SFD_SENT_MSK_MASK (0x00000008u) +#define MAC_TX_INT_MASK_SFD_SENT_MSK_BIT (3) +#define MAC_TX_INT_MASK_SFD_SENT_MSK_BITS (1) +/* BO_COMPLETE_MSK field */ +#define MAC_TX_INT_MASK_BO_COMPLETE_MSK (0x00000004u) +#define MAC_TX_INT_MASK_BO_COMPLETE_MSK_MASK (0x00000004u) +#define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BIT (2) +#define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BITS (1) +/* RX_ACK_MSK field */ +#define MAC_TX_INT_MASK_RX_ACK_MSK (0x00000002u) +#define MAC_TX_INT_MASK_RX_ACK_MSK_MASK (0x00000002u) +#define MAC_TX_INT_MASK_RX_ACK_MSK_BIT (1) +#define MAC_TX_INT_MASK_RX_ACK_MSK_BITS (1) +/* TX_COMPLETE_MSK field */ +#define MAC_TX_INT_MASK_TX_COMPLETE_MSK (0x00000001u) +#define MAC_TX_INT_MASK_TX_COMPLETE_MSK_MASK (0x00000001u) +#define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT (0) +#define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS (1) #define MAC_TIMER_INT_MASK *((volatile uint32_t *)0x4000A048u) #define MAC_TIMER_INT_MASK_REG *((volatile uint32_t *)0x4000A048u) #define MAC_TIMER_INT_MASK_ADDR (0x4000A048u) #define MAC_TIMER_INT_MASK_RESET (0x00000000u) - /* TIMER_COMP_B_MSK field */ - #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK (0x00000004u) - #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_MASK (0x00000004u) - #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BIT (2) - #define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BITS (1) - /* TIMER_COMP_A_MSK field */ - #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK (0x00000002u) - #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_MASK (0x00000002u) - #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BIT (1) - #define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BITS (1) - /* TIMER_WRAP_MSK field */ - #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK (0x00000001u) - #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_MASK (0x00000001u) - #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT (0) - #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS (1) +/* TIMER_COMP_B_MSK field */ +#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK (0x00000004u) +#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_MASK (0x00000004u) +#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BIT (2) +#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BITS (1) +/* TIMER_COMP_A_MSK field */ +#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK (0x00000002u) +#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_MASK (0x00000002u) +#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BIT (1) +#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BITS (1) +/* TIMER_WRAP_MSK field */ +#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK (0x00000001u) +#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_MASK (0x00000001u) +#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT (0) +#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS (1) #define BB_INT_MASK *((volatile uint32_t *)0x4000A04Cu) #define BB_INT_MASK_REG *((volatile uint32_t *)0x4000A04Cu) #define BB_INT_MASK_ADDR (0x4000A04Cu) #define BB_INT_MASK_RESET (0x00000000u) - /* RSSI_INT_MSK field */ - #define BB_INT_MASK_RSSI_INT_MSK (0x00000002u) - #define BB_INT_MASK_RSSI_INT_MSK_MASK (0x00000002u) - #define BB_INT_MASK_RSSI_INT_MSK_BIT (1) - #define BB_INT_MASK_RSSI_INT_MSK_BITS (1) - /* BASEBAND_INT_MSK field */ - #define BB_INT_MASK_BASEBAND_INT_MSK (0x00000001u) - #define BB_INT_MASK_BASEBAND_INT_MSK_MASK (0x00000001u) - #define BB_INT_MASK_BASEBAND_INT_MSK_BIT (0) - #define BB_INT_MASK_BASEBAND_INT_MSK_BITS (1) +/* RSSI_INT_MSK field */ +#define BB_INT_MASK_RSSI_INT_MSK (0x00000002u) +#define BB_INT_MASK_RSSI_INT_MSK_MASK (0x00000002u) +#define BB_INT_MASK_RSSI_INT_MSK_BIT (1) +#define BB_INT_MASK_RSSI_INT_MSK_BITS (1) +/* BASEBAND_INT_MSK field */ +#define BB_INT_MASK_BASEBAND_INT_MSK (0x00000001u) +#define BB_INT_MASK_BASEBAND_INT_MSK_MASK (0x00000001u) +#define BB_INT_MASK_BASEBAND_INT_MSK_BIT (0) +#define BB_INT_MASK_BASEBAND_INT_MSK_BITS (1) #define SEC_INT_MASK *((volatile uint32_t *)0x4000A050u) #define SEC_INT_MASK_REG *((volatile uint32_t *)0x4000A050u) #define SEC_INT_MASK_ADDR (0x4000A050u) #define SEC_INT_MASK_RESET (0x00000000u) - /* CT_WORD_VALID_MSK field */ - #define SEC_INT_MASK_CT_WORD_VALID_MSK (0x00000004u) - #define SEC_INT_MASK_CT_WORD_VALID_MSK_MASK (0x00000004u) - #define SEC_INT_MASK_CT_WORD_VALID_MSK_BIT (2) - #define SEC_INT_MASK_CT_WORD_VALID_MSK_BITS (1) - /* PT_WORD_REQ_MSK field */ - #define SEC_INT_MASK_PT_WORD_REQ_MSK (0x00000002u) - #define SEC_INT_MASK_PT_WORD_REQ_MSK_MASK (0x00000002u) - #define SEC_INT_MASK_PT_WORD_REQ_MSK_BIT (1) - #define SEC_INT_MASK_PT_WORD_REQ_MSK_BITS (1) - /* ENC_COMPLETE_MSK field */ - #define SEC_INT_MASK_ENC_COMPLETE_MSK (0x00000001u) - #define SEC_INT_MASK_ENC_COMPLETE_MSK_MASK (0x00000001u) - #define SEC_INT_MASK_ENC_COMPLETE_MSK_BIT (0) - #define SEC_INT_MASK_ENC_COMPLETE_MSK_BITS (1) +/* CT_WORD_VALID_MSK field */ +#define SEC_INT_MASK_CT_WORD_VALID_MSK (0x00000004u) +#define SEC_INT_MASK_CT_WORD_VALID_MSK_MASK (0x00000004u) +#define SEC_INT_MASK_CT_WORD_VALID_MSK_BIT (2) +#define SEC_INT_MASK_CT_WORD_VALID_MSK_BITS (1) +/* PT_WORD_REQ_MSK field */ +#define SEC_INT_MASK_PT_WORD_REQ_MSK (0x00000002u) +#define SEC_INT_MASK_PT_WORD_REQ_MSK_MASK (0x00000002u) +#define SEC_INT_MASK_PT_WORD_REQ_MSK_BIT (1) +#define SEC_INT_MASK_PT_WORD_REQ_MSK_BITS (1) +/* ENC_COMPLETE_MSK field */ +#define SEC_INT_MASK_ENC_COMPLETE_MSK (0x00000001u) +#define SEC_INT_MASK_ENC_COMPLETE_MSK_MASK (0x00000001u) +#define SEC_INT_MASK_ENC_COMPLETE_MSK_BIT (0) +#define SEC_INT_MASK_ENC_COMPLETE_MSK_BITS (1) #define INT_SLEEPTMRCFG *((volatile uint32_t *)0x4000A054u) #define INT_SLEEPTMRCFG_REG *((volatile uint32_t *)0x4000A054u) #define INT_SLEEPTMRCFG_ADDR (0x4000A054u) #define INT_SLEEPTMRCFG_RESET (0x00000000u) - /* INT_SLEEPTMRCMPB field */ - #define INT_SLEEPTMRCMPB (0x00000004u) - #define INT_SLEEPTMRCMPB_MASK (0x00000004u) - #define INT_SLEEPTMRCMPB_BIT (2) - #define INT_SLEEPTMRCMPB_BITS (1) - /* INT_SLEEPTMRCMPA field */ - #define INT_SLEEPTMRCMPA (0x00000002u) - #define INT_SLEEPTMRCMPA_MASK (0x00000002u) - #define INT_SLEEPTMRCMPA_BIT (1) - #define INT_SLEEPTMRCMPA_BITS (1) - /* INT_SLEEPTMRWRAP field */ - #define INT_SLEEPTMRWRAP (0x00000001u) - #define INT_SLEEPTMRWRAP_MASK (0x00000001u) - #define INT_SLEEPTMRWRAP_BIT (0) - #define INT_SLEEPTMRWRAP_BITS (1) +/* INT_SLEEPTMRCMPB field */ +#define INT_SLEEPTMRCMPB (0x00000004u) +#define INT_SLEEPTMRCMPB_MASK (0x00000004u) +#define INT_SLEEPTMRCMPB_BIT (2) +#define INT_SLEEPTMRCMPB_BITS (1) +/* INT_SLEEPTMRCMPA field */ +#define INT_SLEEPTMRCMPA (0x00000002u) +#define INT_SLEEPTMRCMPA_MASK (0x00000002u) +#define INT_SLEEPTMRCMPA_BIT (1) +#define INT_SLEEPTMRCMPA_BITS (1) +/* INT_SLEEPTMRWRAP field */ +#define INT_SLEEPTMRWRAP (0x00000001u) +#define INT_SLEEPTMRWRAP_MASK (0x00000001u) +#define INT_SLEEPTMRWRAP_BIT (0) +#define INT_SLEEPTMRWRAP_BITS (1) #define INT_MGMTCFG *((volatile uint32_t *)0x4000A058u) #define INT_MGMTCFG_REG *((volatile uint32_t *)0x4000A058u) #define INT_MGMTCFG_ADDR (0x4000A058u) #define INT_MGMTCFG_RESET (0x00000000u) - /* INT_MGMTDMAPROT field */ - #define INT_MGMTDMAPROT (0x00000010u) - #define INT_MGMTDMAPROT_MASK (0x00000010u) - #define INT_MGMTDMAPROT_BIT (4) - #define INT_MGMTDMAPROT_BITS (1) - /* INT_MGMTCALADC field */ - #define INT_MGMTCALADC (0x00000008u) - #define INT_MGMTCALADC_MASK (0x00000008u) - #define INT_MGMTCALADC_BIT (3) - #define INT_MGMTCALADC_BITS (1) - /* INT_MGMTFPEC field */ - #define INT_MGMTFPEC (0x00000004u) - #define INT_MGMTFPEC_MASK (0x00000004u) - #define INT_MGMTFPEC_BIT (2) - #define INT_MGMTFPEC_BITS (1) - /* INT_MGMTOSC24MHI field */ - #define INT_MGMTOSC24MHI (0x00000002u) - #define INT_MGMTOSC24MHI_MASK (0x00000002u) - #define INT_MGMTOSC24MHI_BIT (1) - #define INT_MGMTOSC24MHI_BITS (1) - /* INT_MGMTOSC24MLO field */ - #define INT_MGMTOSC24MLO (0x00000001u) - #define INT_MGMTOSC24MLO_MASK (0x00000001u) - #define INT_MGMTOSC24MLO_BIT (0) - #define INT_MGMTOSC24MLO_BITS (1) +/* INT_MGMTDMAPROT field */ +#define INT_MGMTDMAPROT (0x00000010u) +#define INT_MGMTDMAPROT_MASK (0x00000010u) +#define INT_MGMTDMAPROT_BIT (4) +#define INT_MGMTDMAPROT_BITS (1) +/* INT_MGMTCALADC field */ +#define INT_MGMTCALADC (0x00000008u) +#define INT_MGMTCALADC_MASK (0x00000008u) +#define INT_MGMTCALADC_BIT (3) +#define INT_MGMTCALADC_BITS (1) +/* INT_MGMTFPEC field */ +#define INT_MGMTFPEC (0x00000004u) +#define INT_MGMTFPEC_MASK (0x00000004u) +#define INT_MGMTFPEC_BIT (2) +#define INT_MGMTFPEC_BITS (1) +/* INT_MGMTOSC24MHI field */ +#define INT_MGMTOSC24MHI (0x00000002u) +#define INT_MGMTOSC24MHI_MASK (0x00000002u) +#define INT_MGMTOSC24MHI_BIT (1) +#define INT_MGMTOSC24MHI_BITS (1) +/* INT_MGMTOSC24MLO field */ +#define INT_MGMTOSC24MLO (0x00000001u) +#define INT_MGMTOSC24MLO_MASK (0x00000001u) +#define INT_MGMTOSC24MLO_BIT (0) +#define INT_MGMTOSC24MLO_BITS (1) #define INT_TIM1FLAG *((volatile uint32_t *)0x4000A800u) #define INT_TIM1FLAG_REG *((volatile uint32_t *)0x4000A800u) #define INT_TIM1FLAG_ADDR (0x4000A800u) #define INT_TIM1FLAG_RESET (0x00000000u) - /* INT_TIMRSVD field */ - #define INT_TIMRSVD (0x00001E00u) - #define INT_TIMRSVD_MASK (0x00001E00u) - #define INT_TIMRSVD_BIT (9) - #define INT_TIMRSVD_BITS (4) - /* INT_TIMTIF field */ - #define INT_TIMTIF (0x00000040u) - #define INT_TIMTIF_MASK (0x00000040u) - #define INT_TIMTIF_BIT (6) - #define INT_TIMTIF_BITS (1) - /* INT_TIMCC4IF field */ - #define INT_TIMCC4IF (0x00000010u) - #define INT_TIMCC4IF_MASK (0x00000010u) - #define INT_TIMCC4IF_BIT (4) - #define INT_TIMCC4IF_BITS (1) - /* INT_TIMCC3IF field */ - #define INT_TIMCC3IF (0x00000008u) - #define INT_TIMCC3IF_MASK (0x00000008u) - #define INT_TIMCC3IF_BIT (3) - #define INT_TIMCC3IF_BITS (1) - /* INT_TIMCC2IF field */ - #define INT_TIMCC2IF (0x00000004u) - #define INT_TIMCC2IF_MASK (0x00000004u) - #define INT_TIMCC2IF_BIT (2) - #define INT_TIMCC2IF_BITS (1) - /* INT_TIMCC1IF field */ - #define INT_TIMCC1IF (0x00000002u) - #define INT_TIMCC1IF_MASK (0x00000002u) - #define INT_TIMCC1IF_BIT (1) - #define INT_TIMCC1IF_BITS (1) - /* INT_TIMUIF field */ - #define INT_TIMUIF (0x00000001u) - #define INT_TIMUIF_MASK (0x00000001u) - #define INT_TIMUIF_BIT (0) - #define INT_TIMUIF_BITS (1) +/* INT_TIMRSVD field */ +#define INT_TIMRSVD (0x00001E00u) +#define INT_TIMRSVD_MASK (0x00001E00u) +#define INT_TIMRSVD_BIT (9) +#define INT_TIMRSVD_BITS (4) +/* INT_TIMTIF field */ +#define INT_TIMTIF (0x00000040u) +#define INT_TIMTIF_MASK (0x00000040u) +#define INT_TIMTIF_BIT (6) +#define INT_TIMTIF_BITS (1) +/* INT_TIMCC4IF field */ +#define INT_TIMCC4IF (0x00000010u) +#define INT_TIMCC4IF_MASK (0x00000010u) +#define INT_TIMCC4IF_BIT (4) +#define INT_TIMCC4IF_BITS (1) +/* INT_TIMCC3IF field */ +#define INT_TIMCC3IF (0x00000008u) +#define INT_TIMCC3IF_MASK (0x00000008u) +#define INT_TIMCC3IF_BIT (3) +#define INT_TIMCC3IF_BITS (1) +/* INT_TIMCC2IF field */ +#define INT_TIMCC2IF (0x00000004u) +#define INT_TIMCC2IF_MASK (0x00000004u) +#define INT_TIMCC2IF_BIT (2) +#define INT_TIMCC2IF_BITS (1) +/* INT_TIMCC1IF field */ +#define INT_TIMCC1IF (0x00000002u) +#define INT_TIMCC1IF_MASK (0x00000002u) +#define INT_TIMCC1IF_BIT (1) +#define INT_TIMCC1IF_BITS (1) +/* INT_TIMUIF field */ +#define INT_TIMUIF (0x00000001u) +#define INT_TIMUIF_MASK (0x00000001u) +#define INT_TIMUIF_BIT (0) +#define INT_TIMUIF_BITS (1) #define INT_TIM2FLAG *((volatile uint32_t *)0x4000A804u) #define INT_TIM2FLAG_REG *((volatile uint32_t *)0x4000A804u) #define INT_TIM2FLAG_ADDR (0x4000A804u) #define INT_TIM2FLAG_RESET (0x00000000u) - /* INT_TIMRSVD field */ - #define INT_TIMRSVD (0x00001E00u) - #define INT_TIMRSVD_MASK (0x00001E00u) - #define INT_TIMRSVD_BIT (9) - #define INT_TIMRSVD_BITS (4) - /* INT_TIMTIF field */ - #define INT_TIMTIF (0x00000040u) - #define INT_TIMTIF_MASK (0x00000040u) - #define INT_TIMTIF_BIT (6) - #define INT_TIMTIF_BITS (1) - /* INT_TIMCC4IF field */ - #define INT_TIMCC4IF (0x00000010u) - #define INT_TIMCC4IF_MASK (0x00000010u) - #define INT_TIMCC4IF_BIT (4) - #define INT_TIMCC4IF_BITS (1) - /* INT_TIMCC3IF field */ - #define INT_TIMCC3IF (0x00000008u) - #define INT_TIMCC3IF_MASK (0x00000008u) - #define INT_TIMCC3IF_BIT (3) - #define INT_TIMCC3IF_BITS (1) - /* INT_TIMCC2IF field */ - #define INT_TIMCC2IF (0x00000004u) - #define INT_TIMCC2IF_MASK (0x00000004u) - #define INT_TIMCC2IF_BIT (2) - #define INT_TIMCC2IF_BITS (1) - /* INT_TIMCC1IF field */ - #define INT_TIMCC1IF (0x00000002u) - #define INT_TIMCC1IF_MASK (0x00000002u) - #define INT_TIMCC1IF_BIT (1) - #define INT_TIMCC1IF_BITS (1) - /* INT_TIMUIF field */ - #define INT_TIMUIF (0x00000001u) - #define INT_TIMUIF_MASK (0x00000001u) - #define INT_TIMUIF_BIT (0) - #define INT_TIMUIF_BITS (1) +/* INT_TIMRSVD field */ +#define INT_TIMRSVD (0x00001E00u) +#define INT_TIMRSVD_MASK (0x00001E00u) +#define INT_TIMRSVD_BIT (9) +#define INT_TIMRSVD_BITS (4) +/* INT_TIMTIF field */ +#define INT_TIMTIF (0x00000040u) +#define INT_TIMTIF_MASK (0x00000040u) +#define INT_TIMTIF_BIT (6) +#define INT_TIMTIF_BITS (1) +/* INT_TIMCC4IF field */ +#define INT_TIMCC4IF (0x00000010u) +#define INT_TIMCC4IF_MASK (0x00000010u) +#define INT_TIMCC4IF_BIT (4) +#define INT_TIMCC4IF_BITS (1) +/* INT_TIMCC3IF field */ +#define INT_TIMCC3IF (0x00000008u) +#define INT_TIMCC3IF_MASK (0x00000008u) +#define INT_TIMCC3IF_BIT (3) +#define INT_TIMCC3IF_BITS (1) +/* INT_TIMCC2IF field */ +#define INT_TIMCC2IF (0x00000004u) +#define INT_TIMCC2IF_MASK (0x00000004u) +#define INT_TIMCC2IF_BIT (2) +#define INT_TIMCC2IF_BITS (1) +/* INT_TIMCC1IF field */ +#define INT_TIMCC1IF (0x00000002u) +#define INT_TIMCC1IF_MASK (0x00000002u) +#define INT_TIMCC1IF_BIT (1) +#define INT_TIMCC1IF_BITS (1) +/* INT_TIMUIF field */ +#define INT_TIMUIF (0x00000001u) +#define INT_TIMUIF_MASK (0x00000001u) +#define INT_TIMUIF_BIT (0) +#define INT_TIMUIF_BITS (1) #define INT_SC1FLAG *((volatile uint32_t *)0x4000A808u) #define INT_SC1FLAG_REG *((volatile uint32_t *)0x4000A808u) #define INT_SC1FLAG_ADDR (0x4000A808u) #define INT_SC1FLAG_RESET (0x00000000u) - /* INT_SC1PARERR field */ - #define INT_SC1PARERR (0x00004000u) - #define INT_SC1PARERR_MASK (0x00004000u) - #define INT_SC1PARERR_BIT (14) - #define INT_SC1PARERR_BITS (1) - /* INT_SC1FRMERR field */ - #define INT_SC1FRMERR (0x00002000u) - #define INT_SC1FRMERR_MASK (0x00002000u) - #define INT_SC1FRMERR_BIT (13) - #define INT_SC1FRMERR_BITS (1) - /* INT_SCTXULDB field */ - #define INT_SCTXULDB (0x00001000u) - #define INT_SCTXULDB_MASK (0x00001000u) - #define INT_SCTXULDB_BIT (12) - #define INT_SCTXULDB_BITS (1) - /* INT_SCTXULDA field */ - #define INT_SCTXULDA (0x00000800u) - #define INT_SCTXULDA_MASK (0x00000800u) - #define INT_SCTXULDA_BIT (11) - #define INT_SCTXULDA_BITS (1) - /* INT_SCRXULDB field */ - #define INT_SCRXULDB (0x00000400u) - #define INT_SCRXULDB_MASK (0x00000400u) - #define INT_SCRXULDB_BIT (10) - #define INT_SCRXULDB_BITS (1) - /* INT_SCRXULDA field */ - #define INT_SCRXULDA (0x00000200u) - #define INT_SCRXULDA_MASK (0x00000200u) - #define INT_SCRXULDA_BIT (9) - #define INT_SCRXULDA_BITS (1) - /* INT_SCNAK field */ - #define INT_SCNAK (0x00000100u) - #define INT_SCNAK_MASK (0x00000100u) - #define INT_SCNAK_BIT (8) - #define INT_SCNAK_BITS (1) - /* INT_SCCMDFIN field */ - #define INT_SCCMDFIN (0x00000080u) - #define INT_SCCMDFIN_MASK (0x00000080u) - #define INT_SCCMDFIN_BIT (7) - #define INT_SCCMDFIN_BITS (1) - /* INT_SCTXFIN field */ - #define INT_SCTXFIN (0x00000040u) - #define INT_SCTXFIN_MASK (0x00000040u) - #define INT_SCTXFIN_BIT (6) - #define INT_SCTXFIN_BITS (1) - /* INT_SCRXFIN field */ - #define INT_SCRXFIN (0x00000020u) - #define INT_SCRXFIN_MASK (0x00000020u) - #define INT_SCRXFIN_BIT (5) - #define INT_SCRXFIN_BITS (1) - /* INT_SCTXUND field */ - #define INT_SCTXUND (0x00000010u) - #define INT_SCTXUND_MASK (0x00000010u) - #define INT_SCTXUND_BIT (4) - #define INT_SCTXUND_BITS (1) - /* INT_SCRXOVF field */ - #define INT_SCRXOVF (0x00000008u) - #define INT_SCRXOVF_MASK (0x00000008u) - #define INT_SCRXOVF_BIT (3) - #define INT_SCRXOVF_BITS (1) - /* INT_SCTXIDLE field */ - #define INT_SCTXIDLE (0x00000004u) - #define INT_SCTXIDLE_MASK (0x00000004u) - #define INT_SCTXIDLE_BIT (2) - #define INT_SCTXIDLE_BITS (1) - /* INT_SCTXFREE field */ - #define INT_SCTXFREE (0x00000002u) - #define INT_SCTXFREE_MASK (0x00000002u) - #define INT_SCTXFREE_BIT (1) - #define INT_SCTXFREE_BITS (1) - /* INT_SCRXVAL field */ - #define INT_SCRXVAL (0x00000001u) - #define INT_SCRXVAL_MASK (0x00000001u) - #define INT_SCRXVAL_BIT (0) - #define INT_SCRXVAL_BITS (1) +/* INT_SC1PARERR field */ +#define INT_SC1PARERR (0x00004000u) +#define INT_SC1PARERR_MASK (0x00004000u) +#define INT_SC1PARERR_BIT (14) +#define INT_SC1PARERR_BITS (1) +/* INT_SC1FRMERR field */ +#define INT_SC1FRMERR (0x00002000u) +#define INT_SC1FRMERR_MASK (0x00002000u) +#define INT_SC1FRMERR_BIT (13) +#define INT_SC1FRMERR_BITS (1) +/* INT_SCTXULDB field */ +#define INT_SCTXULDB (0x00001000u) +#define INT_SCTXULDB_MASK (0x00001000u) +#define INT_SCTXULDB_BIT (12) +#define INT_SCTXULDB_BITS (1) +/* INT_SCTXULDA field */ +#define INT_SCTXULDA (0x00000800u) +#define INT_SCTXULDA_MASK (0x00000800u) +#define INT_SCTXULDA_BIT (11) +#define INT_SCTXULDA_BITS (1) +/* INT_SCRXULDB field */ +#define INT_SCRXULDB (0x00000400u) +#define INT_SCRXULDB_MASK (0x00000400u) +#define INT_SCRXULDB_BIT (10) +#define INT_SCRXULDB_BITS (1) +/* INT_SCRXULDA field */ +#define INT_SCRXULDA (0x00000200u) +#define INT_SCRXULDA_MASK (0x00000200u) +#define INT_SCRXULDA_BIT (9) +#define INT_SCRXULDA_BITS (1) +/* INT_SCNAK field */ +#define INT_SCNAK (0x00000100u) +#define INT_SCNAK_MASK (0x00000100u) +#define INT_SCNAK_BIT (8) +#define INT_SCNAK_BITS (1) +/* INT_SCCMDFIN field */ +#define INT_SCCMDFIN (0x00000080u) +#define INT_SCCMDFIN_MASK (0x00000080u) +#define INT_SCCMDFIN_BIT (7) +#define INT_SCCMDFIN_BITS (1) +/* INT_SCTXFIN field */ +#define INT_SCTXFIN (0x00000040u) +#define INT_SCTXFIN_MASK (0x00000040u) +#define INT_SCTXFIN_BIT (6) +#define INT_SCTXFIN_BITS (1) +/* INT_SCRXFIN field */ +#define INT_SCRXFIN (0x00000020u) +#define INT_SCRXFIN_MASK (0x00000020u) +#define INT_SCRXFIN_BIT (5) +#define INT_SCRXFIN_BITS (1) +/* INT_SCTXUND field */ +#define INT_SCTXUND (0x00000010u) +#define INT_SCTXUND_MASK (0x00000010u) +#define INT_SCTXUND_BIT (4) +#define INT_SCTXUND_BITS (1) +/* INT_SCRXOVF field */ +#define INT_SCRXOVF (0x00000008u) +#define INT_SCRXOVF_MASK (0x00000008u) +#define INT_SCRXOVF_BIT (3) +#define INT_SCRXOVF_BITS (1) +/* INT_SCTXIDLE field */ +#define INT_SCTXIDLE (0x00000004u) +#define INT_SCTXIDLE_MASK (0x00000004u) +#define INT_SCTXIDLE_BIT (2) +#define INT_SCTXIDLE_BITS (1) +/* INT_SCTXFREE field */ +#define INT_SCTXFREE (0x00000002u) +#define INT_SCTXFREE_MASK (0x00000002u) +#define INT_SCTXFREE_BIT (1) +#define INT_SCTXFREE_BITS (1) +/* INT_SCRXVAL field */ +#define INT_SCRXVAL (0x00000001u) +#define INT_SCRXVAL_MASK (0x00000001u) +#define INT_SCRXVAL_BIT (0) +#define INT_SCRXVAL_BITS (1) #define INT_SC2FLAG *((volatile uint32_t *)0x4000A80Cu) #define INT_SC2FLAG_REG *((volatile uint32_t *)0x4000A80Cu) #define INT_SC2FLAG_ADDR (0x4000A80Cu) #define INT_SC2FLAG_RESET (0x00000000u) - /* INT_SCTXULDB field */ - #define INT_SCTXULDB (0x00001000u) - #define INT_SCTXULDB_MASK (0x00001000u) - #define INT_SCTXULDB_BIT (12) - #define INT_SCTXULDB_BITS (1) - /* INT_SCTXULDA field */ - #define INT_SCTXULDA (0x00000800u) - #define INT_SCTXULDA_MASK (0x00000800u) - #define INT_SCTXULDA_BIT (11) - #define INT_SCTXULDA_BITS (1) - /* INT_SCRXULDB field */ - #define INT_SCRXULDB (0x00000400u) - #define INT_SCRXULDB_MASK (0x00000400u) - #define INT_SCRXULDB_BIT (10) - #define INT_SCRXULDB_BITS (1) - /* INT_SCRXULDA field */ - #define INT_SCRXULDA (0x00000200u) - #define INT_SCRXULDA_MASK (0x00000200u) - #define INT_SCRXULDA_BIT (9) - #define INT_SCRXULDA_BITS (1) - /* INT_SCNAK field */ - #define INT_SCNAK (0x00000100u) - #define INT_SCNAK_MASK (0x00000100u) - #define INT_SCNAK_BIT (8) - #define INT_SCNAK_BITS (1) - /* INT_SCCMDFIN field */ - #define INT_SCCMDFIN (0x00000080u) - #define INT_SCCMDFIN_MASK (0x00000080u) - #define INT_SCCMDFIN_BIT (7) - #define INT_SCCMDFIN_BITS (1) - /* INT_SCTXFIN field */ - #define INT_SCTXFIN (0x00000040u) - #define INT_SCTXFIN_MASK (0x00000040u) - #define INT_SCTXFIN_BIT (6) - #define INT_SCTXFIN_BITS (1) - /* INT_SCRXFIN field */ - #define INT_SCRXFIN (0x00000020u) - #define INT_SCRXFIN_MASK (0x00000020u) - #define INT_SCRXFIN_BIT (5) - #define INT_SCRXFIN_BITS (1) - /* INT_SCTXUND field */ - #define INT_SCTXUND (0x00000010u) - #define INT_SCTXUND_MASK (0x00000010u) - #define INT_SCTXUND_BIT (4) - #define INT_SCTXUND_BITS (1) - /* INT_SCRXOVF field */ - #define INT_SCRXOVF (0x00000008u) - #define INT_SCRXOVF_MASK (0x00000008u) - #define INT_SCRXOVF_BIT (3) - #define INT_SCRXOVF_BITS (1) - /* INT_SCTXIDLE field */ - #define INT_SCTXIDLE (0x00000004u) - #define INT_SCTXIDLE_MASK (0x00000004u) - #define INT_SCTXIDLE_BIT (2) - #define INT_SCTXIDLE_BITS (1) - /* INT_SCTXFREE field */ - #define INT_SCTXFREE (0x00000002u) - #define INT_SCTXFREE_MASK (0x00000002u) - #define INT_SCTXFREE_BIT (1) - #define INT_SCTXFREE_BITS (1) - /* INT_SCRXVAL field */ - #define INT_SCRXVAL (0x00000001u) - #define INT_SCRXVAL_MASK (0x00000001u) - #define INT_SCRXVAL_BIT (0) - #define INT_SCRXVAL_BITS (1) +/* INT_SCTXULDB field */ +#define INT_SCTXULDB (0x00001000u) +#define INT_SCTXULDB_MASK (0x00001000u) +#define INT_SCTXULDB_BIT (12) +#define INT_SCTXULDB_BITS (1) +/* INT_SCTXULDA field */ +#define INT_SCTXULDA (0x00000800u) +#define INT_SCTXULDA_MASK (0x00000800u) +#define INT_SCTXULDA_BIT (11) +#define INT_SCTXULDA_BITS (1) +/* INT_SCRXULDB field */ +#define INT_SCRXULDB (0x00000400u) +#define INT_SCRXULDB_MASK (0x00000400u) +#define INT_SCRXULDB_BIT (10) +#define INT_SCRXULDB_BITS (1) +/* INT_SCRXULDA field */ +#define INT_SCRXULDA (0x00000200u) +#define INT_SCRXULDA_MASK (0x00000200u) +#define INT_SCRXULDA_BIT (9) +#define INT_SCRXULDA_BITS (1) +/* INT_SCNAK field */ +#define INT_SCNAK (0x00000100u) +#define INT_SCNAK_MASK (0x00000100u) +#define INT_SCNAK_BIT (8) +#define INT_SCNAK_BITS (1) +/* INT_SCCMDFIN field */ +#define INT_SCCMDFIN (0x00000080u) +#define INT_SCCMDFIN_MASK (0x00000080u) +#define INT_SCCMDFIN_BIT (7) +#define INT_SCCMDFIN_BITS (1) +/* INT_SCTXFIN field */ +#define INT_SCTXFIN (0x00000040u) +#define INT_SCTXFIN_MASK (0x00000040u) +#define INT_SCTXFIN_BIT (6) +#define INT_SCTXFIN_BITS (1) +/* INT_SCRXFIN field */ +#define INT_SCRXFIN (0x00000020u) +#define INT_SCRXFIN_MASK (0x00000020u) +#define INT_SCRXFIN_BIT (5) +#define INT_SCRXFIN_BITS (1) +/* INT_SCTXUND field */ +#define INT_SCTXUND (0x00000010u) +#define INT_SCTXUND_MASK (0x00000010u) +#define INT_SCTXUND_BIT (4) +#define INT_SCTXUND_BITS (1) +/* INT_SCRXOVF field */ +#define INT_SCRXOVF (0x00000008u) +#define INT_SCRXOVF_MASK (0x00000008u) +#define INT_SCRXOVF_BIT (3) +#define INT_SCRXOVF_BITS (1) +/* INT_SCTXIDLE field */ +#define INT_SCTXIDLE (0x00000004u) +#define INT_SCTXIDLE_MASK (0x00000004u) +#define INT_SCTXIDLE_BIT (2) +#define INT_SCTXIDLE_BITS (1) +/* INT_SCTXFREE field */ +#define INT_SCTXFREE (0x00000002u) +#define INT_SCTXFREE_MASK (0x00000002u) +#define INT_SCTXFREE_BIT (1) +#define INT_SCTXFREE_BITS (1) +/* INT_SCRXVAL field */ +#define INT_SCRXVAL (0x00000001u) +#define INT_SCRXVAL_MASK (0x00000001u) +#define INT_SCRXVAL_BIT (0) +#define INT_SCRXVAL_BITS (1) #define INT_ADCFLAG *((volatile uint32_t *)0x4000A810u) #define INT_ADCFLAG_REG *((volatile uint32_t *)0x4000A810u) #define INT_ADCFLAG_ADDR (0x4000A810u) #define INT_ADCFLAG_RESET (0x00000000u) - /* INT_ADCOVF field */ - #define INT_ADCOVF (0x00000010u) - #define INT_ADCOVF_MASK (0x00000010u) - #define INT_ADCOVF_BIT (4) - #define INT_ADCOVF_BITS (1) - /* INT_ADCSAT field */ - #define INT_ADCSAT (0x00000008u) - #define INT_ADCSAT_MASK (0x00000008u) - #define INT_ADCSAT_BIT (3) - #define INT_ADCSAT_BITS (1) - /* INT_ADCULDFULL field */ - #define INT_ADCULDFULL (0x00000004u) - #define INT_ADCULDFULL_MASK (0x00000004u) - #define INT_ADCULDFULL_BIT (2) - #define INT_ADCULDFULL_BITS (1) - /* INT_ADCULDHALF field */ - #define INT_ADCULDHALF (0x00000002u) - #define INT_ADCULDHALF_MASK (0x00000002u) - #define INT_ADCULDHALF_BIT (1) - #define INT_ADCULDHALF_BITS (1) - /* INT_ADCFLAGRSVD field */ - #define INT_ADCFLAGRSVD (0x00000001u) - #define INT_ADCFLAGRSVD_MASK (0x00000001u) - #define INT_ADCFLAGRSVD_BIT (0) - #define INT_ADCFLAGRSVD_BITS (1) +/* INT_ADCOVF field */ +#define INT_ADCOVF (0x00000010u) +#define INT_ADCOVF_MASK (0x00000010u) +#define INT_ADCOVF_BIT (4) +#define INT_ADCOVF_BITS (1) +/* INT_ADCSAT field */ +#define INT_ADCSAT (0x00000008u) +#define INT_ADCSAT_MASK (0x00000008u) +#define INT_ADCSAT_BIT (3) +#define INT_ADCSAT_BITS (1) +/* INT_ADCULDFULL field */ +#define INT_ADCULDFULL (0x00000004u) +#define INT_ADCULDFULL_MASK (0x00000004u) +#define INT_ADCULDFULL_BIT (2) +#define INT_ADCULDFULL_BITS (1) +/* INT_ADCULDHALF field */ +#define INT_ADCULDHALF (0x00000002u) +#define INT_ADCULDHALF_MASK (0x00000002u) +#define INT_ADCULDHALF_BIT (1) +#define INT_ADCULDHALF_BITS (1) +/* INT_ADCFLAGRSVD field */ +#define INT_ADCFLAGRSVD (0x00000001u) +#define INT_ADCFLAGRSVD_MASK (0x00000001u) +#define INT_ADCFLAGRSVD_BIT (0) +#define INT_ADCFLAGRSVD_BITS (1) #define INT_GPIOFLAG *((volatile uint32_t *)0x4000A814u) #define INT_GPIOFLAG_REG *((volatile uint32_t *)0x4000A814u) #define INT_GPIOFLAG_ADDR (0x4000A814u) #define INT_GPIOFLAG_RESET (0x00000000u) - /* INT_IRQDFLAG field */ - #define INT_IRQDFLAG (0x00000008u) - #define INT_IRQDFLAG_MASK (0x00000008u) - #define INT_IRQDFLAG_BIT (3) - #define INT_IRQDFLAG_BITS (1) - /* INT_IRQCFLAG field */ - #define INT_IRQCFLAG (0x00000004u) - #define INT_IRQCFLAG_MASK (0x00000004u) - #define INT_IRQCFLAG_BIT (2) - #define INT_IRQCFLAG_BITS (1) - /* INT_IRQBFLAG field */ - #define INT_IRQBFLAG (0x00000002u) - #define INT_IRQBFLAG_MASK (0x00000002u) - #define INT_IRQBFLAG_BIT (1) - #define INT_IRQBFLAG_BITS (1) - /* INT_IRQAFLAG field */ - #define INT_IRQAFLAG (0x00000001u) - #define INT_IRQAFLAG_MASK (0x00000001u) - #define INT_IRQAFLAG_BIT (0) - #define INT_IRQAFLAG_BITS (1) +/* INT_IRQDFLAG field */ +#define INT_IRQDFLAG (0x00000008u) +#define INT_IRQDFLAG_MASK (0x00000008u) +#define INT_IRQDFLAG_BIT (3) +#define INT_IRQDFLAG_BITS (1) +/* INT_IRQCFLAG field */ +#define INT_IRQCFLAG (0x00000004u) +#define INT_IRQCFLAG_MASK (0x00000004u) +#define INT_IRQCFLAG_BIT (2) +#define INT_IRQCFLAG_BITS (1) +/* INT_IRQBFLAG field */ +#define INT_IRQBFLAG (0x00000002u) +#define INT_IRQBFLAG_MASK (0x00000002u) +#define INT_IRQBFLAG_BIT (1) +#define INT_IRQBFLAG_BITS (1) +/* INT_IRQAFLAG field */ +#define INT_IRQAFLAG (0x00000001u) +#define INT_IRQAFLAG_MASK (0x00000001u) +#define INT_IRQAFLAG_BIT (0) +#define INT_IRQAFLAG_BITS (1) #define INT_TIM1MISS *((volatile uint32_t *)0x4000A818u) #define INT_TIM1MISS_REG *((volatile uint32_t *)0x4000A818u) #define INT_TIM1MISS_ADDR (0x4000A818u) #define INT_TIM1MISS_RESET (0x00000000u) - /* INT_TIMMISSCC4IF field */ - #define INT_TIMMISSCC4IF (0x00001000u) - #define INT_TIMMISSCC4IF_MASK (0x00001000u) - #define INT_TIMMISSCC4IF_BIT (12) - #define INT_TIMMISSCC4IF_BITS (1) - /* INT_TIMMISSCC3IF field */ - #define INT_TIMMISSCC3IF (0x00000800u) - #define INT_TIMMISSCC3IF_MASK (0x00000800u) - #define INT_TIMMISSCC3IF_BIT (11) - #define INT_TIMMISSCC3IF_BITS (1) - /* INT_TIMMISSCC2IF field */ - #define INT_TIMMISSCC2IF (0x00000400u) - #define INT_TIMMISSCC2IF_MASK (0x00000400u) - #define INT_TIMMISSCC2IF_BIT (10) - #define INT_TIMMISSCC2IF_BITS (1) - /* INT_TIMMISSCC1IF field */ - #define INT_TIMMISSCC1IF (0x00000200u) - #define INT_TIMMISSCC1IF_MASK (0x00000200u) - #define INT_TIMMISSCC1IF_BIT (9) - #define INT_TIMMISSCC1IF_BITS (1) - /* INT_TIMMISSRSVD field */ - #define INT_TIMMISSRSVD (0x0000007Fu) - #define INT_TIMMISSRSVD_MASK (0x0000007Fu) - #define INT_TIMMISSRSVD_BIT (0) - #define INT_TIMMISSRSVD_BITS (7) +/* INT_TIMMISSCC4IF field */ +#define INT_TIMMISSCC4IF (0x00001000u) +#define INT_TIMMISSCC4IF_MASK (0x00001000u) +#define INT_TIMMISSCC4IF_BIT (12) +#define INT_TIMMISSCC4IF_BITS (1) +/* INT_TIMMISSCC3IF field */ +#define INT_TIMMISSCC3IF (0x00000800u) +#define INT_TIMMISSCC3IF_MASK (0x00000800u) +#define INT_TIMMISSCC3IF_BIT (11) +#define INT_TIMMISSCC3IF_BITS (1) +/* INT_TIMMISSCC2IF field */ +#define INT_TIMMISSCC2IF (0x00000400u) +#define INT_TIMMISSCC2IF_MASK (0x00000400u) +#define INT_TIMMISSCC2IF_BIT (10) +#define INT_TIMMISSCC2IF_BITS (1) +/* INT_TIMMISSCC1IF field */ +#define INT_TIMMISSCC1IF (0x00000200u) +#define INT_TIMMISSCC1IF_MASK (0x00000200u) +#define INT_TIMMISSCC1IF_BIT (9) +#define INT_TIMMISSCC1IF_BITS (1) +/* INT_TIMMISSRSVD field */ +#define INT_TIMMISSRSVD (0x0000007Fu) +#define INT_TIMMISSRSVD_MASK (0x0000007Fu) +#define INT_TIMMISSRSVD_BIT (0) +#define INT_TIMMISSRSVD_BITS (7) #define INT_TIM2MISS *((volatile uint32_t *)0x4000A81Cu) #define INT_TIM2MISS_REG *((volatile uint32_t *)0x4000A81Cu) #define INT_TIM2MISS_ADDR (0x4000A81Cu) #define INT_TIM2MISS_RESET (0x00000000u) - /* INT_TIMMISSCC4IF field */ - #define INT_TIMMISSCC4IF (0x00001000u) - #define INT_TIMMISSCC4IF_MASK (0x00001000u) - #define INT_TIMMISSCC4IF_BIT (12) - #define INT_TIMMISSCC4IF_BITS (1) - /* INT_TIMMISSCC3IF field */ - #define INT_TIMMISSCC3IF (0x00000800u) - #define INT_TIMMISSCC3IF_MASK (0x00000800u) - #define INT_TIMMISSCC3IF_BIT (11) - #define INT_TIMMISSCC3IF_BITS (1) - /* INT_TIMMISSCC2IF field */ - #define INT_TIMMISSCC2IF (0x00000400u) - #define INT_TIMMISSCC2IF_MASK (0x00000400u) - #define INT_TIMMISSCC2IF_BIT (10) - #define INT_TIMMISSCC2IF_BITS (1) - /* INT_TIMMISSCC1IF field */ - #define INT_TIMMISSCC1IF (0x00000200u) - #define INT_TIMMISSCC1IF_MASK (0x00000200u) - #define INT_TIMMISSCC1IF_BIT (9) - #define INT_TIMMISSCC1IF_BITS (1) - /* INT_TIMMISSRSVD field */ - #define INT_TIMMISSRSVD (0x0000007Fu) - #define INT_TIMMISSRSVD_MASK (0x0000007Fu) - #define INT_TIMMISSRSVD_BIT (0) - #define INT_TIMMISSRSVD_BITS (7) +/* INT_TIMMISSCC4IF field */ +#define INT_TIMMISSCC4IF (0x00001000u) +#define INT_TIMMISSCC4IF_MASK (0x00001000u) +#define INT_TIMMISSCC4IF_BIT (12) +#define INT_TIMMISSCC4IF_BITS (1) +/* INT_TIMMISSCC3IF field */ +#define INT_TIMMISSCC3IF (0x00000800u) +#define INT_TIMMISSCC3IF_MASK (0x00000800u) +#define INT_TIMMISSCC3IF_BIT (11) +#define INT_TIMMISSCC3IF_BITS (1) +/* INT_TIMMISSCC2IF field */ +#define INT_TIMMISSCC2IF (0x00000400u) +#define INT_TIMMISSCC2IF_MASK (0x00000400u) +#define INT_TIMMISSCC2IF_BIT (10) +#define INT_TIMMISSCC2IF_BITS (1) +/* INT_TIMMISSCC1IF field */ +#define INT_TIMMISSCC1IF (0x00000200u) +#define INT_TIMMISSCC1IF_MASK (0x00000200u) +#define INT_TIMMISSCC1IF_BIT (9) +#define INT_TIMMISSCC1IF_BITS (1) +/* INT_TIMMISSRSVD field */ +#define INT_TIMMISSRSVD (0x0000007Fu) +#define INT_TIMMISSRSVD_MASK (0x0000007Fu) +#define INT_TIMMISSRSVD_BIT (0) +#define INT_TIMMISSRSVD_BITS (7) #define INT_MISS *((volatile uint32_t *)0x4000A820u) #define INT_MISS_REG *((volatile uint32_t *)0x4000A820u) #define INT_MISS_ADDR (0x4000A820u) #define INT_MISS_RESET (0x00000000u) - /* INT_MISSIRQD field */ - #define INT_MISSIRQD (0x00008000u) - #define INT_MISSIRQD_MASK (0x00008000u) - #define INT_MISSIRQD_BIT (15) - #define INT_MISSIRQD_BITS (1) - /* INT_MISSIRQC field */ - #define INT_MISSIRQC (0x00004000u) - #define INT_MISSIRQC_MASK (0x00004000u) - #define INT_MISSIRQC_BIT (14) - #define INT_MISSIRQC_BITS (1) - /* INT_MISSIRQB field */ - #define INT_MISSIRQB (0x00002000u) - #define INT_MISSIRQB_MASK (0x00002000u) - #define INT_MISSIRQB_BIT (13) - #define INT_MISSIRQB_BITS (1) - /* INT_MISSIRQA field */ - #define INT_MISSIRQA (0x00001000u) - #define INT_MISSIRQA_MASK (0x00001000u) - #define INT_MISSIRQA_BIT (12) - #define INT_MISSIRQA_BITS (1) - /* INT_MISSADC field */ - #define INT_MISSADC (0x00000800u) - #define INT_MISSADC_MASK (0x00000800u) - #define INT_MISSADC_BIT (11) - #define INT_MISSADC_BITS (1) - /* INT_MISSMACRX field */ - #define INT_MISSMACRX (0x00000400u) - #define INT_MISSMACRX_MASK (0x00000400u) - #define INT_MISSMACRX_BIT (10) - #define INT_MISSMACRX_BITS (1) - /* INT_MISSMACTX field */ - #define INT_MISSMACTX (0x00000200u) - #define INT_MISSMACTX_MASK (0x00000200u) - #define INT_MISSMACTX_BIT (9) - #define INT_MISSMACTX_BITS (1) - /* INT_MISSMACTMR field */ - #define INT_MISSMACTMR (0x00000100u) - #define INT_MISSMACTMR_MASK (0x00000100u) - #define INT_MISSMACTMR_BIT (8) - #define INT_MISSMACTMR_BITS (1) - /* INT_MISSSEC field */ - #define INT_MISSSEC (0x00000080u) - #define INT_MISSSEC_MASK (0x00000080u) - #define INT_MISSSEC_BIT (7) - #define INT_MISSSEC_BITS (1) - /* INT_MISSSC2 field */ - #define INT_MISSSC2 (0x00000040u) - #define INT_MISSSC2_MASK (0x00000040u) - #define INT_MISSSC2_BIT (6) - #define INT_MISSSC2_BITS (1) - /* INT_MISSSC1 field */ - #define INT_MISSSC1 (0x00000020u) - #define INT_MISSSC1_MASK (0x00000020u) - #define INT_MISSSC1_BIT (5) - #define INT_MISSSC1_BITS (1) - /* INT_MISSSLEEP field */ - #define INT_MISSSLEEP (0x00000010u) - #define INT_MISSSLEEP_MASK (0x00000010u) - #define INT_MISSSLEEP_BIT (4) - #define INT_MISSSLEEP_BITS (1) - /* INT_MISSBB field */ - #define INT_MISSBB (0x00000008u) - #define INT_MISSBB_MASK (0x00000008u) - #define INT_MISSBB_BIT (3) - #define INT_MISSBB_BITS (1) - /* INT_MISSMGMT field */ - #define INT_MISSMGMT (0x00000004u) - #define INT_MISSMGMT_MASK (0x00000004u) - #define INT_MISSMGMT_BIT (2) - #define INT_MISSMGMT_BITS (1) +/* INT_MISSIRQD field */ +#define INT_MISSIRQD (0x00008000u) +#define INT_MISSIRQD_MASK (0x00008000u) +#define INT_MISSIRQD_BIT (15) +#define INT_MISSIRQD_BITS (1) +/* INT_MISSIRQC field */ +#define INT_MISSIRQC (0x00004000u) +#define INT_MISSIRQC_MASK (0x00004000u) +#define INT_MISSIRQC_BIT (14) +#define INT_MISSIRQC_BITS (1) +/* INT_MISSIRQB field */ +#define INT_MISSIRQB (0x00002000u) +#define INT_MISSIRQB_MASK (0x00002000u) +#define INT_MISSIRQB_BIT (13) +#define INT_MISSIRQB_BITS (1) +/* INT_MISSIRQA field */ +#define INT_MISSIRQA (0x00001000u) +#define INT_MISSIRQA_MASK (0x00001000u) +#define INT_MISSIRQA_BIT (12) +#define INT_MISSIRQA_BITS (1) +/* INT_MISSADC field */ +#define INT_MISSADC (0x00000800u) +#define INT_MISSADC_MASK (0x00000800u) +#define INT_MISSADC_BIT (11) +#define INT_MISSADC_BITS (1) +/* INT_MISSMACRX field */ +#define INT_MISSMACRX (0x00000400u) +#define INT_MISSMACRX_MASK (0x00000400u) +#define INT_MISSMACRX_BIT (10) +#define INT_MISSMACRX_BITS (1) +/* INT_MISSMACTX field */ +#define INT_MISSMACTX (0x00000200u) +#define INT_MISSMACTX_MASK (0x00000200u) +#define INT_MISSMACTX_BIT (9) +#define INT_MISSMACTX_BITS (1) +/* INT_MISSMACTMR field */ +#define INT_MISSMACTMR (0x00000100u) +#define INT_MISSMACTMR_MASK (0x00000100u) +#define INT_MISSMACTMR_BIT (8) +#define INT_MISSMACTMR_BITS (1) +/* INT_MISSSEC field */ +#define INT_MISSSEC (0x00000080u) +#define INT_MISSSEC_MASK (0x00000080u) +#define INT_MISSSEC_BIT (7) +#define INT_MISSSEC_BITS (1) +/* INT_MISSSC2 field */ +#define INT_MISSSC2 (0x00000040u) +#define INT_MISSSC2_MASK (0x00000040u) +#define INT_MISSSC2_BIT (6) +#define INT_MISSSC2_BITS (1) +/* INT_MISSSC1 field */ +#define INT_MISSSC1 (0x00000020u) +#define INT_MISSSC1_MASK (0x00000020u) +#define INT_MISSSC1_BIT (5) +#define INT_MISSSC1_BITS (1) +/* INT_MISSSLEEP field */ +#define INT_MISSSLEEP (0x00000010u) +#define INT_MISSSLEEP_MASK (0x00000010u) +#define INT_MISSSLEEP_BIT (4) +#define INT_MISSSLEEP_BITS (1) +/* INT_MISSBB field */ +#define INT_MISSBB (0x00000008u) +#define INT_MISSBB_MASK (0x00000008u) +#define INT_MISSBB_BIT (3) +#define INT_MISSBB_BITS (1) +/* INT_MISSMGMT field */ +#define INT_MISSMGMT (0x00000004u) +#define INT_MISSMGMT_MASK (0x00000004u) +#define INT_MISSMGMT_BIT (2) +#define INT_MISSMGMT_BITS (1) #define INT_TIM1CFG *((volatile uint32_t *)0x4000A840u) #define INT_TIM1CFG_REG *((volatile uint32_t *)0x4000A840u) #define INT_TIM1CFG_ADDR (0x4000A840u) #define INT_TIM1CFG_RESET (0x00000000u) - /* INT_TIMTIF field */ - #define INT_TIMTIF (0x00000040u) - #define INT_TIMTIF_MASK (0x00000040u) - #define INT_TIMTIF_BIT (6) - #define INT_TIMTIF_BITS (1) - /* INT_TIMCC4IF field */ - #define INT_TIMCC4IF (0x00000010u) - #define INT_TIMCC4IF_MASK (0x00000010u) - #define INT_TIMCC4IF_BIT (4) - #define INT_TIMCC4IF_BITS (1) - /* INT_TIMCC3IF field */ - #define INT_TIMCC3IF (0x00000008u) - #define INT_TIMCC3IF_MASK (0x00000008u) - #define INT_TIMCC3IF_BIT (3) - #define INT_TIMCC3IF_BITS (1) - /* INT_TIMCC2IF field */ - #define INT_TIMCC2IF (0x00000004u) - #define INT_TIMCC2IF_MASK (0x00000004u) - #define INT_TIMCC2IF_BIT (2) - #define INT_TIMCC2IF_BITS (1) - /* INT_TIMCC1IF field */ - #define INT_TIMCC1IF (0x00000002u) - #define INT_TIMCC1IF_MASK (0x00000002u) - #define INT_TIMCC1IF_BIT (1) - #define INT_TIMCC1IF_BITS (1) - /* INT_TIMUIF field */ - #define INT_TIMUIF (0x00000001u) - #define INT_TIMUIF_MASK (0x00000001u) - #define INT_TIMUIF_BIT (0) - #define INT_TIMUIF_BITS (1) +/* INT_TIMTIF field */ +#define INT_TIMTIF (0x00000040u) +#define INT_TIMTIF_MASK (0x00000040u) +#define INT_TIMTIF_BIT (6) +#define INT_TIMTIF_BITS (1) +/* INT_TIMCC4IF field */ +#define INT_TIMCC4IF (0x00000010u) +#define INT_TIMCC4IF_MASK (0x00000010u) +#define INT_TIMCC4IF_BIT (4) +#define INT_TIMCC4IF_BITS (1) +/* INT_TIMCC3IF field */ +#define INT_TIMCC3IF (0x00000008u) +#define INT_TIMCC3IF_MASK (0x00000008u) +#define INT_TIMCC3IF_BIT (3) +#define INT_TIMCC3IF_BITS (1) +/* INT_TIMCC2IF field */ +#define INT_TIMCC2IF (0x00000004u) +#define INT_TIMCC2IF_MASK (0x00000004u) +#define INT_TIMCC2IF_BIT (2) +#define INT_TIMCC2IF_BITS (1) +/* INT_TIMCC1IF field */ +#define INT_TIMCC1IF (0x00000002u) +#define INT_TIMCC1IF_MASK (0x00000002u) +#define INT_TIMCC1IF_BIT (1) +#define INT_TIMCC1IF_BITS (1) +/* INT_TIMUIF field */ +#define INT_TIMUIF (0x00000001u) +#define INT_TIMUIF_MASK (0x00000001u) +#define INT_TIMUIF_BIT (0) +#define INT_TIMUIF_BITS (1) #define INT_TIM2CFG *((volatile uint32_t *)0x4000A844u) #define INT_TIM2CFG_REG *((volatile uint32_t *)0x4000A844u) #define INT_TIM2CFG_ADDR (0x4000A844u) #define INT_TIM2CFG_RESET (0x00000000u) - /* INT_TIMTIF field */ - #define INT_TIMTIF (0x00000040u) - #define INT_TIMTIF_MASK (0x00000040u) - #define INT_TIMTIF_BIT (6) - #define INT_TIMTIF_BITS (1) - /* INT_TIMCC4IF field */ - #define INT_TIMCC4IF (0x00000010u) - #define INT_TIMCC4IF_MASK (0x00000010u) - #define INT_TIMCC4IF_BIT (4) - #define INT_TIMCC4IF_BITS (1) - /* INT_TIMCC3IF field */ - #define INT_TIMCC3IF (0x00000008u) - #define INT_TIMCC3IF_MASK (0x00000008u) - #define INT_TIMCC3IF_BIT (3) - #define INT_TIMCC3IF_BITS (1) - /* INT_TIMCC2IF field */ - #define INT_TIMCC2IF (0x00000004u) - #define INT_TIMCC2IF_MASK (0x00000004u) - #define INT_TIMCC2IF_BIT (2) - #define INT_TIMCC2IF_BITS (1) - /* INT_TIMCC1IF field */ - #define INT_TIMCC1IF (0x00000002u) - #define INT_TIMCC1IF_MASK (0x00000002u) - #define INT_TIMCC1IF_BIT (1) - #define INT_TIMCC1IF_BITS (1) - /* INT_TIMUIF field */ - #define INT_TIMUIF (0x00000001u) - #define INT_TIMUIF_MASK (0x00000001u) - #define INT_TIMUIF_BIT (0) - #define INT_TIMUIF_BITS (1) +/* INT_TIMTIF field */ +#define INT_TIMTIF (0x00000040u) +#define INT_TIMTIF_MASK (0x00000040u) +#define INT_TIMTIF_BIT (6) +#define INT_TIMTIF_BITS (1) +/* INT_TIMCC4IF field */ +#define INT_TIMCC4IF (0x00000010u) +#define INT_TIMCC4IF_MASK (0x00000010u) +#define INT_TIMCC4IF_BIT (4) +#define INT_TIMCC4IF_BITS (1) +/* INT_TIMCC3IF field */ +#define INT_TIMCC3IF (0x00000008u) +#define INT_TIMCC3IF_MASK (0x00000008u) +#define INT_TIMCC3IF_BIT (3) +#define INT_TIMCC3IF_BITS (1) +/* INT_TIMCC2IF field */ +#define INT_TIMCC2IF (0x00000004u) +#define INT_TIMCC2IF_MASK (0x00000004u) +#define INT_TIMCC2IF_BIT (2) +#define INT_TIMCC2IF_BITS (1) +/* INT_TIMCC1IF field */ +#define INT_TIMCC1IF (0x00000002u) +#define INT_TIMCC1IF_MASK (0x00000002u) +#define INT_TIMCC1IF_BIT (1) +#define INT_TIMCC1IF_BITS (1) +/* INT_TIMUIF field */ +#define INT_TIMUIF (0x00000001u) +#define INT_TIMUIF_MASK (0x00000001u) +#define INT_TIMUIF_BIT (0) +#define INT_TIMUIF_BITS (1) #define INT_SC1CFG *((volatile uint32_t *)0x4000A848u) #define INT_SC1CFG_REG *((volatile uint32_t *)0x4000A848u) #define INT_SC1CFG_ADDR (0x4000A848u) #define INT_SC1CFG_RESET (0x00000000u) - /* INT_SC1PARERR field */ - #define INT_SC1PARERR (0x00004000u) - #define INT_SC1PARERR_MASK (0x00004000u) - #define INT_SC1PARERR_BIT (14) - #define INT_SC1PARERR_BITS (1) - /* INT_SC1FRMERR field */ - #define INT_SC1FRMERR (0x00002000u) - #define INT_SC1FRMERR_MASK (0x00002000u) - #define INT_SC1FRMERR_BIT (13) - #define INT_SC1FRMERR_BITS (1) - /* INT_SCTXULDB field */ - #define INT_SCTXULDB (0x00001000u) - #define INT_SCTXULDB_MASK (0x00001000u) - #define INT_SCTXULDB_BIT (12) - #define INT_SCTXULDB_BITS (1) - /* INT_SCTXULDA field */ - #define INT_SCTXULDA (0x00000800u) - #define INT_SCTXULDA_MASK (0x00000800u) - #define INT_SCTXULDA_BIT (11) - #define INT_SCTXULDA_BITS (1) - /* INT_SCRXULDB field */ - #define INT_SCRXULDB (0x00000400u) - #define INT_SCRXULDB_MASK (0x00000400u) - #define INT_SCRXULDB_BIT (10) - #define INT_SCRXULDB_BITS (1) - /* INT_SCRXULDA field */ - #define INT_SCRXULDA (0x00000200u) - #define INT_SCRXULDA_MASK (0x00000200u) - #define INT_SCRXULDA_BIT (9) - #define INT_SCRXULDA_BITS (1) - /* INT_SCNAK field */ - #define INT_SCNAK (0x00000100u) - #define INT_SCNAK_MASK (0x00000100u) - #define INT_SCNAK_BIT (8) - #define INT_SCNAK_BITS (1) - /* INT_SCCMDFIN field */ - #define INT_SCCMDFIN (0x00000080u) - #define INT_SCCMDFIN_MASK (0x00000080u) - #define INT_SCCMDFIN_BIT (7) - #define INT_SCCMDFIN_BITS (1) - /* INT_SCTXFIN field */ - #define INT_SCTXFIN (0x00000040u) - #define INT_SCTXFIN_MASK (0x00000040u) - #define INT_SCTXFIN_BIT (6) - #define INT_SCTXFIN_BITS (1) - /* INT_SCRXFIN field */ - #define INT_SCRXFIN (0x00000020u) - #define INT_SCRXFIN_MASK (0x00000020u) - #define INT_SCRXFIN_BIT (5) - #define INT_SCRXFIN_BITS (1) - /* INT_SCTXUND field */ - #define INT_SCTXUND (0x00000010u) - #define INT_SCTXUND_MASK (0x00000010u) - #define INT_SCTXUND_BIT (4) - #define INT_SCTXUND_BITS (1) - /* INT_SCRXOVF field */ - #define INT_SCRXOVF (0x00000008u) - #define INT_SCRXOVF_MASK (0x00000008u) - #define INT_SCRXOVF_BIT (3) - #define INT_SCRXOVF_BITS (1) - /* INT_SCTXIDLE field */ - #define INT_SCTXIDLE (0x00000004u) - #define INT_SCTXIDLE_MASK (0x00000004u) - #define INT_SCTXIDLE_BIT (2) - #define INT_SCTXIDLE_BITS (1) - /* INT_SCTXFREE field */ - #define INT_SCTXFREE (0x00000002u) - #define INT_SCTXFREE_MASK (0x00000002u) - #define INT_SCTXFREE_BIT (1) - #define INT_SCTXFREE_BITS (1) - /* INT_SCRXVAL field */ - #define INT_SCRXVAL (0x00000001u) - #define INT_SCRXVAL_MASK (0x00000001u) - #define INT_SCRXVAL_BIT (0) - #define INT_SCRXVAL_BITS (1) +/* INT_SC1PARERR field */ +#define INT_SC1PARERR (0x00004000u) +#define INT_SC1PARERR_MASK (0x00004000u) +#define INT_SC1PARERR_BIT (14) +#define INT_SC1PARERR_BITS (1) +/* INT_SC1FRMERR field */ +#define INT_SC1FRMERR (0x00002000u) +#define INT_SC1FRMERR_MASK (0x00002000u) +#define INT_SC1FRMERR_BIT (13) +#define INT_SC1FRMERR_BITS (1) +/* INT_SCTXULDB field */ +#define INT_SCTXULDB (0x00001000u) +#define INT_SCTXULDB_MASK (0x00001000u) +#define INT_SCTXULDB_BIT (12) +#define INT_SCTXULDB_BITS (1) +/* INT_SCTXULDA field */ +#define INT_SCTXULDA (0x00000800u) +#define INT_SCTXULDA_MASK (0x00000800u) +#define INT_SCTXULDA_BIT (11) +#define INT_SCTXULDA_BITS (1) +/* INT_SCRXULDB field */ +#define INT_SCRXULDB (0x00000400u) +#define INT_SCRXULDB_MASK (0x00000400u) +#define INT_SCRXULDB_BIT (10) +#define INT_SCRXULDB_BITS (1) +/* INT_SCRXULDA field */ +#define INT_SCRXULDA (0x00000200u) +#define INT_SCRXULDA_MASK (0x00000200u) +#define INT_SCRXULDA_BIT (9) +#define INT_SCRXULDA_BITS (1) +/* INT_SCNAK field */ +#define INT_SCNAK (0x00000100u) +#define INT_SCNAK_MASK (0x00000100u) +#define INT_SCNAK_BIT (8) +#define INT_SCNAK_BITS (1) +/* INT_SCCMDFIN field */ +#define INT_SCCMDFIN (0x00000080u) +#define INT_SCCMDFIN_MASK (0x00000080u) +#define INT_SCCMDFIN_BIT (7) +#define INT_SCCMDFIN_BITS (1) +/* INT_SCTXFIN field */ +#define INT_SCTXFIN (0x00000040u) +#define INT_SCTXFIN_MASK (0x00000040u) +#define INT_SCTXFIN_BIT (6) +#define INT_SCTXFIN_BITS (1) +/* INT_SCRXFIN field */ +#define INT_SCRXFIN (0x00000020u) +#define INT_SCRXFIN_MASK (0x00000020u) +#define INT_SCRXFIN_BIT (5) +#define INT_SCRXFIN_BITS (1) +/* INT_SCTXUND field */ +#define INT_SCTXUND (0x00000010u) +#define INT_SCTXUND_MASK (0x00000010u) +#define INT_SCTXUND_BIT (4) +#define INT_SCTXUND_BITS (1) +/* INT_SCRXOVF field */ +#define INT_SCRXOVF (0x00000008u) +#define INT_SCRXOVF_MASK (0x00000008u) +#define INT_SCRXOVF_BIT (3) +#define INT_SCRXOVF_BITS (1) +/* INT_SCTXIDLE field */ +#define INT_SCTXIDLE (0x00000004u) +#define INT_SCTXIDLE_MASK (0x00000004u) +#define INT_SCTXIDLE_BIT (2) +#define INT_SCTXIDLE_BITS (1) +/* INT_SCTXFREE field */ +#define INT_SCTXFREE (0x00000002u) +#define INT_SCTXFREE_MASK (0x00000002u) +#define INT_SCTXFREE_BIT (1) +#define INT_SCTXFREE_BITS (1) +/* INT_SCRXVAL field */ +#define INT_SCRXVAL (0x00000001u) +#define INT_SCRXVAL_MASK (0x00000001u) +#define INT_SCRXVAL_BIT (0) +#define INT_SCRXVAL_BITS (1) #define INT_SC2CFG *((volatile uint32_t *)0x4000A84Cu) #define INT_SC2CFG_REG *((volatile uint32_t *)0x4000A84Cu) #define INT_SC2CFG_ADDR (0x4000A84Cu) #define INT_SC2CFG_RESET (0x00000000u) - /* INT_SCTXULDB field */ - #define INT_SCTXULDB (0x00001000u) - #define INT_SCTXULDB_MASK (0x00001000u) - #define INT_SCTXULDB_BIT (12) - #define INT_SCTXULDB_BITS (1) - /* INT_SCTXULDA field */ - #define INT_SCTXULDA (0x00000800u) - #define INT_SCTXULDA_MASK (0x00000800u) - #define INT_SCTXULDA_BIT (11) - #define INT_SCTXULDA_BITS (1) - /* INT_SCRXULDB field */ - #define INT_SCRXULDB (0x00000400u) - #define INT_SCRXULDB_MASK (0x00000400u) - #define INT_SCRXULDB_BIT (10) - #define INT_SCRXULDB_BITS (1) - /* INT_SCRXULDA field */ - #define INT_SCRXULDA (0x00000200u) - #define INT_SCRXULDA_MASK (0x00000200u) - #define INT_SCRXULDA_BIT (9) - #define INT_SCRXULDA_BITS (1) - /* INT_SCNAK field */ - #define INT_SCNAK (0x00000100u) - #define INT_SCNAK_MASK (0x00000100u) - #define INT_SCNAK_BIT (8) - #define INT_SCNAK_BITS (1) - /* INT_SCCMDFIN field */ - #define INT_SCCMDFIN (0x00000080u) - #define INT_SCCMDFIN_MASK (0x00000080u) - #define INT_SCCMDFIN_BIT (7) - #define INT_SCCMDFIN_BITS (1) - /* INT_SCTXFIN field */ - #define INT_SCTXFIN (0x00000040u) - #define INT_SCTXFIN_MASK (0x00000040u) - #define INT_SCTXFIN_BIT (6) - #define INT_SCTXFIN_BITS (1) - /* INT_SCRXFIN field */ - #define INT_SCRXFIN (0x00000020u) - #define INT_SCRXFIN_MASK (0x00000020u) - #define INT_SCRXFIN_BIT (5) - #define INT_SCRXFIN_BITS (1) - /* INT_SCTXUND field */ - #define INT_SCTXUND (0x00000010u) - #define INT_SCTXUND_MASK (0x00000010u) - #define INT_SCTXUND_BIT (4) - #define INT_SCTXUND_BITS (1) - /* INT_SCRXOVF field */ - #define INT_SCRXOVF (0x00000008u) - #define INT_SCRXOVF_MASK (0x00000008u) - #define INT_SCRXOVF_BIT (3) - #define INT_SCRXOVF_BITS (1) - /* INT_SCTXIDLE field */ - #define INT_SCTXIDLE (0x00000004u) - #define INT_SCTXIDLE_MASK (0x00000004u) - #define INT_SCTXIDLE_BIT (2) - #define INT_SCTXIDLE_BITS (1) - /* INT_SCTXFREE field */ - #define INT_SCTXFREE (0x00000002u) - #define INT_SCTXFREE_MASK (0x00000002u) - #define INT_SCTXFREE_BIT (1) - #define INT_SCTXFREE_BITS (1) - /* INT_SCRXVAL field */ - #define INT_SCRXVAL (0x00000001u) - #define INT_SCRXVAL_MASK (0x00000001u) - #define INT_SCRXVAL_BIT (0) - #define INT_SCRXVAL_BITS (1) +/* INT_SCTXULDB field */ +#define INT_SCTXULDB (0x00001000u) +#define INT_SCTXULDB_MASK (0x00001000u) +#define INT_SCTXULDB_BIT (12) +#define INT_SCTXULDB_BITS (1) +/* INT_SCTXULDA field */ +#define INT_SCTXULDA (0x00000800u) +#define INT_SCTXULDA_MASK (0x00000800u) +#define INT_SCTXULDA_BIT (11) +#define INT_SCTXULDA_BITS (1) +/* INT_SCRXULDB field */ +#define INT_SCRXULDB (0x00000400u) +#define INT_SCRXULDB_MASK (0x00000400u) +#define INT_SCRXULDB_BIT (10) +#define INT_SCRXULDB_BITS (1) +/* INT_SCRXULDA field */ +#define INT_SCRXULDA (0x00000200u) +#define INT_SCRXULDA_MASK (0x00000200u) +#define INT_SCRXULDA_BIT (9) +#define INT_SCRXULDA_BITS (1) +/* INT_SCNAK field */ +#define INT_SCNAK (0x00000100u) +#define INT_SCNAK_MASK (0x00000100u) +#define INT_SCNAK_BIT (8) +#define INT_SCNAK_BITS (1) +/* INT_SCCMDFIN field */ +#define INT_SCCMDFIN (0x00000080u) +#define INT_SCCMDFIN_MASK (0x00000080u) +#define INT_SCCMDFIN_BIT (7) +#define INT_SCCMDFIN_BITS (1) +/* INT_SCTXFIN field */ +#define INT_SCTXFIN (0x00000040u) +#define INT_SCTXFIN_MASK (0x00000040u) +#define INT_SCTXFIN_BIT (6) +#define INT_SCTXFIN_BITS (1) +/* INT_SCRXFIN field */ +#define INT_SCRXFIN (0x00000020u) +#define INT_SCRXFIN_MASK (0x00000020u) +#define INT_SCRXFIN_BIT (5) +#define INT_SCRXFIN_BITS (1) +/* INT_SCTXUND field */ +#define INT_SCTXUND (0x00000010u) +#define INT_SCTXUND_MASK (0x00000010u) +#define INT_SCTXUND_BIT (4) +#define INT_SCTXUND_BITS (1) +/* INT_SCRXOVF field */ +#define INT_SCRXOVF (0x00000008u) +#define INT_SCRXOVF_MASK (0x00000008u) +#define INT_SCRXOVF_BIT (3) +#define INT_SCRXOVF_BITS (1) +/* INT_SCTXIDLE field */ +#define INT_SCTXIDLE (0x00000004u) +#define INT_SCTXIDLE_MASK (0x00000004u) +#define INT_SCTXIDLE_BIT (2) +#define INT_SCTXIDLE_BITS (1) +/* INT_SCTXFREE field */ +#define INT_SCTXFREE (0x00000002u) +#define INT_SCTXFREE_MASK (0x00000002u) +#define INT_SCTXFREE_BIT (1) +#define INT_SCTXFREE_BITS (1) +/* INT_SCRXVAL field */ +#define INT_SCRXVAL (0x00000001u) +#define INT_SCRXVAL_MASK (0x00000001u) +#define INT_SCRXVAL_BIT (0) +#define INT_SCRXVAL_BITS (1) #define INT_ADCCFG *((volatile uint32_t *)0x4000A850u) #define INT_ADCCFG_REG *((volatile uint32_t *)0x4000A850u) #define INT_ADCCFG_ADDR (0x4000A850u) #define INT_ADCCFG_RESET (0x00000000u) - /* INT_ADCOVF field */ - #define INT_ADCOVF (0x00000010u) - #define INT_ADCOVF_MASK (0x00000010u) - #define INT_ADCOVF_BIT (4) - #define INT_ADCOVF_BITS (1) - /* INT_ADCSAT field */ - #define INT_ADCSAT (0x00000008u) - #define INT_ADCSAT_MASK (0x00000008u) - #define INT_ADCSAT_BIT (3) - #define INT_ADCSAT_BITS (1) - /* INT_ADCULDFULL field */ - #define INT_ADCULDFULL (0x00000004u) - #define INT_ADCULDFULL_MASK (0x00000004u) - #define INT_ADCULDFULL_BIT (2) - #define INT_ADCULDFULL_BITS (1) - /* INT_ADCULDHALF field */ - #define INT_ADCULDHALF (0x00000002u) - #define INT_ADCULDHALF_MASK (0x00000002u) - #define INT_ADCULDHALF_BIT (1) - #define INT_ADCULDHALF_BITS (1) - /* INT_ADCCFGRSVD field */ - #define INT_ADCCFGRSVD (0x00000001u) - #define INT_ADCCFGRSVD_MASK (0x00000001u) - #define INT_ADCCFGRSVD_BIT (0) - #define INT_ADCCFGRSVD_BITS (1) +/* INT_ADCOVF field */ +#define INT_ADCOVF (0x00000010u) +#define INT_ADCOVF_MASK (0x00000010u) +#define INT_ADCOVF_BIT (4) +#define INT_ADCOVF_BITS (1) +/* INT_ADCSAT field */ +#define INT_ADCSAT (0x00000008u) +#define INT_ADCSAT_MASK (0x00000008u) +#define INT_ADCSAT_BIT (3) +#define INT_ADCSAT_BITS (1) +/* INT_ADCULDFULL field */ +#define INT_ADCULDFULL (0x00000004u) +#define INT_ADCULDFULL_MASK (0x00000004u) +#define INT_ADCULDFULL_BIT (2) +#define INT_ADCULDFULL_BITS (1) +/* INT_ADCULDHALF field */ +#define INT_ADCULDHALF (0x00000002u) +#define INT_ADCULDHALF_MASK (0x00000002u) +#define INT_ADCULDHALF_BIT (1) +#define INT_ADCULDHALF_BITS (1) +/* INT_ADCCFGRSVD field */ +#define INT_ADCCFGRSVD (0x00000001u) +#define INT_ADCCFGRSVD_MASK (0x00000001u) +#define INT_ADCCFGRSVD_BIT (0) +#define INT_ADCCFGRSVD_BITS (1) #define SC1_INTMODE *((volatile uint32_t *)0x4000A854u) #define SC1_INTMODE_REG *((volatile uint32_t *)0x4000A854u) #define SC1_INTMODE_ADDR (0x4000A854u) #define SC1_INTMODE_RESET (0x00000000u) - /* SC_TXIDLELEVEL field */ - #define SC_TXIDLELEVEL (0x00000004u) - #define SC_TXIDLELEVEL_MASK (0x00000004u) - #define SC_TXIDLELEVEL_BIT (2) - #define SC_TXIDLELEVEL_BITS (1) - /* SC_TXFREELEVEL field */ - #define SC_TXFREELEVEL (0x00000002u) - #define SC_TXFREELEVEL_MASK (0x00000002u) - #define SC_TXFREELEVEL_BIT (1) - #define SC_TXFREELEVEL_BITS (1) - /* SC_RXVALLEVEL field */ - #define SC_RXVALLEVEL (0x00000001u) - #define SC_RXVALLEVEL_MASK (0x00000001u) - #define SC_RXVALLEVEL_BIT (0) - #define SC_RXVALLEVEL_BITS (1) +/* SC_TXIDLELEVEL field */ +#define SC_TXIDLELEVEL (0x00000004u) +#define SC_TXIDLELEVEL_MASK (0x00000004u) +#define SC_TXIDLELEVEL_BIT (2) +#define SC_TXIDLELEVEL_BITS (1) +/* SC_TXFREELEVEL field */ +#define SC_TXFREELEVEL (0x00000002u) +#define SC_TXFREELEVEL_MASK (0x00000002u) +#define SC_TXFREELEVEL_BIT (1) +#define SC_TXFREELEVEL_BITS (1) +/* SC_RXVALLEVEL field */ +#define SC_RXVALLEVEL (0x00000001u) +#define SC_RXVALLEVEL_MASK (0x00000001u) +#define SC_RXVALLEVEL_BIT (0) +#define SC_RXVALLEVEL_BITS (1) #define SC2_INTMODE *((volatile uint32_t *)0x4000A858u) #define SC2_INTMODE_REG *((volatile uint32_t *)0x4000A858u) #define SC2_INTMODE_ADDR (0x4000A858u) #define SC2_INTMODE_RESET (0x00000000u) - /* SC_TXIDLELEVEL field */ - #define SC_TXIDLELEVEL (0x00000004u) - #define SC_TXIDLELEVEL_MASK (0x00000004u) - #define SC_TXIDLELEVEL_BIT (2) - #define SC_TXIDLELEVEL_BITS (1) - /* SC_TXFREELEVEL field */ - #define SC_TXFREELEVEL (0x00000002u) - #define SC_TXFREELEVEL_MASK (0x00000002u) - #define SC_TXFREELEVEL_BIT (1) - #define SC_TXFREELEVEL_BITS (1) - /* SC_RXVALLEVEL field */ - #define SC_RXVALLEVEL (0x00000001u) - #define SC_RXVALLEVEL_MASK (0x00000001u) - #define SC_RXVALLEVEL_BIT (0) - #define SC_RXVALLEVEL_BITS (1) +/* SC_TXIDLELEVEL field */ +#define SC_TXIDLELEVEL (0x00000004u) +#define SC_TXIDLELEVEL_MASK (0x00000004u) +#define SC_TXIDLELEVEL_BIT (2) +#define SC_TXIDLELEVEL_BITS (1) +/* SC_TXFREELEVEL field */ +#define SC_TXFREELEVEL (0x00000002u) +#define SC_TXFREELEVEL_MASK (0x00000002u) +#define SC_TXFREELEVEL_BIT (1) +#define SC_TXFREELEVEL_BITS (1) +/* SC_RXVALLEVEL field */ +#define SC_RXVALLEVEL (0x00000001u) +#define SC_RXVALLEVEL_MASK (0x00000001u) +#define SC_RXVALLEVEL_BIT (0) +#define SC_RXVALLEVEL_BITS (1) #define GPIO_INTCFGA *((volatile uint32_t *)0x4000A860u) #define GPIO_INTCFGA_REG *((volatile uint32_t *)0x4000A860u) #define GPIO_INTCFGA_ADDR (0x4000A860u) #define GPIO_INTCFGA_RESET (0x00000000u) - /* GPIO_INTFILT field */ - #define GPIO_INTFILT (0x00000100u) - #define GPIO_INTFILT_MASK (0x00000100u) - #define GPIO_INTFILT_BIT (8) - #define GPIO_INTFILT_BITS (1) - /* GPIO_INTMOD field */ - #define GPIO_INTMOD (0x000000E0u) - #define GPIO_INTMOD_MASK (0x000000E0u) - #define GPIO_INTMOD_BIT (5) - #define GPIO_INTMOD_BITS (3) +/* GPIO_INTFILT field */ +#define GPIO_INTFILT (0x00000100u) +#define GPIO_INTFILT_MASK (0x00000100u) +#define GPIO_INTFILT_BIT (8) +#define GPIO_INTFILT_BITS (1) +/* GPIO_INTMOD field */ +#define GPIO_INTMOD (0x000000E0u) +#define GPIO_INTMOD_MASK (0x000000E0u) +#define GPIO_INTMOD_BIT (5) +#define GPIO_INTMOD_BITS (3) #define GPIO_INTCFGB *((volatile uint32_t *)0x4000A864u) #define GPIO_INTCFGB_REG *((volatile uint32_t *)0x4000A864u) #define GPIO_INTCFGB_ADDR (0x4000A864u) #define GPIO_INTCFGB_RESET (0x00000000u) - /* GPIO_INTFILT field */ - #define GPIO_INTFILT (0x00000100u) - #define GPIO_INTFILT_MASK (0x00000100u) - #define GPIO_INTFILT_BIT (8) - #define GPIO_INTFILT_BITS (1) - /* GPIO_INTMOD field */ - #define GPIO_INTMOD (0x000000E0u) - #define GPIO_INTMOD_MASK (0x000000E0u) - #define GPIO_INTMOD_BIT (5) - #define GPIO_INTMOD_BITS (3) +/* GPIO_INTFILT field */ +#define GPIO_INTFILT (0x00000100u) +#define GPIO_INTFILT_MASK (0x00000100u) +#define GPIO_INTFILT_BIT (8) +#define GPIO_INTFILT_BITS (1) +/* GPIO_INTMOD field */ +#define GPIO_INTMOD (0x000000E0u) +#define GPIO_INTMOD_MASK (0x000000E0u) +#define GPIO_INTMOD_BIT (5) +#define GPIO_INTMOD_BITS (3) #define GPIO_INTCFGC *((volatile uint32_t *)0x4000A868u) #define GPIO_INTCFGC_REG *((volatile uint32_t *)0x4000A868u) #define GPIO_INTCFGC_ADDR (0x4000A868u) #define GPIO_INTCFGC_RESET (0x00000000u) - /* GPIO_INTFILT field */ - #define GPIO_INTFILT (0x00000100u) - #define GPIO_INTFILT_MASK (0x00000100u) - #define GPIO_INTFILT_BIT (8) - #define GPIO_INTFILT_BITS (1) - /* GPIO_INTMOD field */ - #define GPIO_INTMOD (0x000000E0u) - #define GPIO_INTMOD_MASK (0x000000E0u) - #define GPIO_INTMOD_BIT (5) - #define GPIO_INTMOD_BITS (3) +/* GPIO_INTFILT field */ +#define GPIO_INTFILT (0x00000100u) +#define GPIO_INTFILT_MASK (0x00000100u) +#define GPIO_INTFILT_BIT (8) +#define GPIO_INTFILT_BITS (1) +/* GPIO_INTMOD field */ +#define GPIO_INTMOD (0x000000E0u) +#define GPIO_INTMOD_MASK (0x000000E0u) +#define GPIO_INTMOD_BIT (5) +#define GPIO_INTMOD_BITS (3) #define GPIO_INTCFGD *((volatile uint32_t *)0x4000A86Cu) #define GPIO_INTCFGD_REG *((volatile uint32_t *)0x4000A86Cu) #define GPIO_INTCFGD_ADDR (0x4000A86Cu) #define GPIO_INTCFGD_RESET (0x00000000u) - /* GPIO_INTFILT field */ - #define GPIO_INTFILT (0x00000100u) - #define GPIO_INTFILT_MASK (0x00000100u) - #define GPIO_INTFILT_BIT (8) - #define GPIO_INTFILT_BITS (1) - /* GPIO_INTMOD field */ - #define GPIO_INTMOD (0x000000E0u) - #define GPIO_INTMOD_MASK (0x000000E0u) - #define GPIO_INTMOD_BIT (5) - #define GPIO_INTMOD_BITS (3) +/* GPIO_INTFILT field */ +#define GPIO_INTFILT (0x00000100u) +#define GPIO_INTFILT_MASK (0x00000100u) +#define GPIO_INTFILT_BIT (8) +#define GPIO_INTFILT_BITS (1) +/* GPIO_INTMOD field */ +#define GPIO_INTMOD (0x000000E0u) +#define GPIO_INTMOD_MASK (0x000000E0u) +#define GPIO_INTMOD_BIT (5) +#define GPIO_INTMOD_BITS (3) /* GPIO block */ #define BLOCK_GPIO_BASE (0x4000B000u) @@ -4594,937 +4594,937 @@ #define GPIO_PACFGL_REG *((volatile uint32_t *)0x4000B000u) #define GPIO_PACFGL_ADDR (0x4000B000u) #define GPIO_PACFGL_RESET (0x00004444u) - /* PA3_CFG field */ - #define PA3_CFG (0x0000F000u) - #define PA3_CFG_MASK (0x0000F000u) - #define PA3_CFG_BIT (12) - #define PA3_CFG_BITS (4) - /* PA2_CFG field */ - #define PA2_CFG (0x00000F00u) - #define PA2_CFG_MASK (0x00000F00u) - #define PA2_CFG_BIT (8) - #define PA2_CFG_BITS (4) - /* PA1_CFG field */ - #define PA1_CFG (0x000000F0u) - #define PA1_CFG_MASK (0x000000F0u) - #define PA1_CFG_BIT (4) - #define PA1_CFG_BITS (4) - /* PA0_CFG field */ - #define PA0_CFG (0x0000000Fu) - #define PA0_CFG_MASK (0x0000000Fu) - #define PA0_CFG_BIT (0) - #define PA0_CFG_BITS (4) - /* GPIO_PxCFGx Bit Field Values */ - #define GPIOCFG_OUT (0x1u) - #define GPIOCFG_OUT_OD (0x5u) - #define GPIOCFG_OUT_ALT (0x9u) - #define GPIOCFG_OUT_ALT_OD (0xDu) - #define GPIOCFG_ANALOG (0x0u) - #define GPIOCFG_IN (0x4u) - #define GPIOCFG_IN_PUD (0x8u) +/* PA3_CFG field */ +#define PA3_CFG (0x0000F000u) +#define PA3_CFG_MASK (0x0000F000u) +#define PA3_CFG_BIT (12) +#define PA3_CFG_BITS (4) +/* PA2_CFG field */ +#define PA2_CFG (0x00000F00u) +#define PA2_CFG_MASK (0x00000F00u) +#define PA2_CFG_BIT (8) +#define PA2_CFG_BITS (4) +/* PA1_CFG field */ +#define PA1_CFG (0x000000F0u) +#define PA1_CFG_MASK (0x000000F0u) +#define PA1_CFG_BIT (4) +#define PA1_CFG_BITS (4) +/* PA0_CFG field */ +#define PA0_CFG (0x0000000Fu) +#define PA0_CFG_MASK (0x0000000Fu) +#define PA0_CFG_BIT (0) +#define PA0_CFG_BITS (4) +/* GPIO_PxCFGx Bit Field Values */ +#define GPIOCFG_OUT (0x1u) +#define GPIOCFG_OUT_OD (0x5u) +#define GPIOCFG_OUT_ALT (0x9u) +#define GPIOCFG_OUT_ALT_OD (0xDu) +#define GPIOCFG_ANALOG (0x0u) +#define GPIOCFG_IN (0x4u) +#define GPIOCFG_IN_PUD (0x8u) #define GPIO_PACFGH *((volatile uint32_t *)0x4000B004u) #define GPIO_PACFGH_REG *((volatile uint32_t *)0x4000B004u) #define GPIO_PACFGH_ADDR (0x4000B004u) #define GPIO_PACFGH_RESET (0x00004444u) - /* PA7_CFG field */ - #define PA7_CFG (0x0000F000u) - #define PA7_CFG_MASK (0x0000F000u) - #define PA7_CFG_BIT (12) - #define PA7_CFG_BITS (4) - /* PA6_CFG field */ - #define PA6_CFG (0x00000F00u) - #define PA6_CFG_MASK (0x00000F00u) - #define PA6_CFG_BIT (8) - #define PA6_CFG_BITS (4) - /* PA5_CFG field */ - #define PA5_CFG (0x000000F0u) - #define PA5_CFG_MASK (0x000000F0u) - #define PA5_CFG_BIT (4) - #define PA5_CFG_BITS (4) - /* PA4_CFG field */ - #define PA4_CFG (0x0000000Fu) - #define PA4_CFG_MASK (0x0000000Fu) - #define PA4_CFG_BIT (0) - #define PA4_CFG_BITS (4) +/* PA7_CFG field */ +#define PA7_CFG (0x0000F000u) +#define PA7_CFG_MASK (0x0000F000u) +#define PA7_CFG_BIT (12) +#define PA7_CFG_BITS (4) +/* PA6_CFG field */ +#define PA6_CFG (0x00000F00u) +#define PA6_CFG_MASK (0x00000F00u) +#define PA6_CFG_BIT (8) +#define PA6_CFG_BITS (4) +/* PA5_CFG field */ +#define PA5_CFG (0x000000F0u) +#define PA5_CFG_MASK (0x000000F0u) +#define PA5_CFG_BIT (4) +#define PA5_CFG_BITS (4) +/* PA4_CFG field */ +#define PA4_CFG (0x0000000Fu) +#define PA4_CFG_MASK (0x0000000Fu) +#define PA4_CFG_BIT (0) +#define PA4_CFG_BITS (4) #define GPIO_PAIN *((volatile uint32_t *)0x4000B008u) #define GPIO_PAIN_REG *((volatile uint32_t *)0x4000B008u) #define GPIO_PAIN_ADDR (0x4000B008u) #define GPIO_PAIN_RESET (0x00000000u) - /* PA7 field */ - #define PA7 (0x00000080u) - #define PA7_MASK (0x00000080u) - #define PA7_BIT (7) - #define PA7_BITS (1) - /* PA6 field */ - #define PA6 (0x00000040u) - #define PA6_MASK (0x00000040u) - #define PA6_BIT (6) - #define PA6_BITS (1) - /* PA5 field */ - #define PA5 (0x00000020u) - #define PA5_MASK (0x00000020u) - #define PA5_BIT (5) - #define PA5_BITS (1) - /* PA4 field */ - #define PA4 (0x00000010u) - #define PA4_MASK (0x00000010u) - #define PA4_BIT (4) - #define PA4_BITS (1) - /* PA3 field */ - #define PA3 (0x00000008u) - #define PA3_MASK (0x00000008u) - #define PA3_BIT (3) - #define PA3_BITS (1) - /* PA2 field */ - #define PA2 (0x00000004u) - #define PA2_MASK (0x00000004u) - #define PA2_BIT (2) - #define PA2_BITS (1) - /* PA1 field */ - #define PA1 (0x00000002u) - #define PA1_MASK (0x00000002u) - #define PA1_BIT (1) - #define PA1_BITS (1) - /* PA0 field */ - #define PA0 (0x00000001u) - #define PA0_MASK (0x00000001u) - #define PA0_BIT (0) - #define PA0_BITS (1) +/* PA7 field */ +#define PA7 (0x00000080u) +#define PA7_MASK (0x00000080u) +#define PA7_BIT (7) +#define PA7_BITS (1) +/* PA6 field */ +#define PA6 (0x00000040u) +#define PA6_MASK (0x00000040u) +#define PA6_BIT (6) +#define PA6_BITS (1) +/* PA5 field */ +#define PA5 (0x00000020u) +#define PA5_MASK (0x00000020u) +#define PA5_BIT (5) +#define PA5_BITS (1) +/* PA4 field */ +#define PA4 (0x00000010u) +#define PA4_MASK (0x00000010u) +#define PA4_BIT (4) +#define PA4_BITS (1) +/* PA3 field */ +#define PA3 (0x00000008u) +#define PA3_MASK (0x00000008u) +#define PA3_BIT (3) +#define PA3_BITS (1) +/* PA2 field */ +#define PA2 (0x00000004u) +#define PA2_MASK (0x00000004u) +#define PA2_BIT (2) +#define PA2_BITS (1) +/* PA1 field */ +#define PA1 (0x00000002u) +#define PA1_MASK (0x00000002u) +#define PA1_BIT (1) +#define PA1_BITS (1) +/* PA0 field */ +#define PA0 (0x00000001u) +#define PA0_MASK (0x00000001u) +#define PA0_BIT (0) +#define PA0_BITS (1) #define GPIO_PAOUT *((volatile uint32_t *)0x4000B00Cu) #define GPIO_PAOUT_REG *((volatile uint32_t *)0x4000B00Cu) #define GPIO_PAOUT_ADDR (0x4000B00Cu) #define GPIO_PAOUT_RESET (0x00000000u) - /* PA7 field */ - #define PA7 (0x00000080u) - #define PA7_MASK (0x00000080u) - #define PA7_BIT (7) - #define PA7_BITS (1) - /* PA6 field */ - #define PA6 (0x00000040u) - #define PA6_MASK (0x00000040u) - #define PA6_BIT (6) - #define PA6_BITS (1) - /* PA5 field */ - #define PA5 (0x00000020u) - #define PA5_MASK (0x00000020u) - #define PA5_BIT (5) - #define PA5_BITS (1) - /* PA4 field */ - #define PA4 (0x00000010u) - #define PA4_MASK (0x00000010u) - #define PA4_BIT (4) - #define PA4_BITS (1) - /* PA3 field */ - #define PA3 (0x00000008u) - #define PA3_MASK (0x00000008u) - #define PA3_BIT (3) - #define PA3_BITS (1) - /* PA2 field */ - #define PA2 (0x00000004u) - #define PA2_MASK (0x00000004u) - #define PA2_BIT (2) - #define PA2_BITS (1) - /* PA1 field */ - #define PA1 (0x00000002u) - #define PA1_MASK (0x00000002u) - #define PA1_BIT (1) - #define PA1_BITS (1) - /* PA0 field */ - #define PA0 (0x00000001u) - #define PA0_MASK (0x00000001u) - #define PA0_BIT (0) - #define PA0_BITS (1) - /* GPIO_PxOUT Bit Field Values */ - #define GPIOOUT_PULLUP (0x1u) - #define GPIOOUT_PULLDOWN (0x0u) +/* PA7 field */ +#define PA7 (0x00000080u) +#define PA7_MASK (0x00000080u) +#define PA7_BIT (7) +#define PA7_BITS (1) +/* PA6 field */ +#define PA6 (0x00000040u) +#define PA6_MASK (0x00000040u) +#define PA6_BIT (6) +#define PA6_BITS (1) +/* PA5 field */ +#define PA5 (0x00000020u) +#define PA5_MASK (0x00000020u) +#define PA5_BIT (5) +#define PA5_BITS (1) +/* PA4 field */ +#define PA4 (0x00000010u) +#define PA4_MASK (0x00000010u) +#define PA4_BIT (4) +#define PA4_BITS (1) +/* PA3 field */ +#define PA3 (0x00000008u) +#define PA3_MASK (0x00000008u) +#define PA3_BIT (3) +#define PA3_BITS (1) +/* PA2 field */ +#define PA2 (0x00000004u) +#define PA2_MASK (0x00000004u) +#define PA2_BIT (2) +#define PA2_BITS (1) +/* PA1 field */ +#define PA1 (0x00000002u) +#define PA1_MASK (0x00000002u) +#define PA1_BIT (1) +#define PA1_BITS (1) +/* PA0 field */ +#define PA0 (0x00000001u) +#define PA0_MASK (0x00000001u) +#define PA0_BIT (0) +#define PA0_BITS (1) +/* GPIO_PxOUT Bit Field Values */ +#define GPIOOUT_PULLUP (0x1u) +#define GPIOOUT_PULLDOWN (0x0u) #define GPIO_PASET *((volatile uint32_t *)0x4000B010u) #define GPIO_PASET_REG *((volatile uint32_t *)0x4000B010u) #define GPIO_PASET_ADDR (0x4000B010u) #define GPIO_PASET_RESET (0x00000000u) - /* GPIO_PXSETRSVD field */ - #define GPIO_PXSETRSVD (0x0000FF00u) - #define GPIO_PXSETRSVD_MASK (0x0000FF00u) - #define GPIO_PXSETRSVD_BIT (8) - #define GPIO_PXSETRSVD_BITS (8) - /* PA7 field */ - #define PA7 (0x00000080u) - #define PA7_MASK (0x00000080u) - #define PA7_BIT (7) - #define PA7_BITS (1) - /* PA6 field */ - #define PA6 (0x00000040u) - #define PA6_MASK (0x00000040u) - #define PA6_BIT (6) - #define PA6_BITS (1) - /* PA5 field */ - #define PA5 (0x00000020u) - #define PA5_MASK (0x00000020u) - #define PA5_BIT (5) - #define PA5_BITS (1) - /* PA4 field */ - #define PA4 (0x00000010u) - #define PA4_MASK (0x00000010u) - #define PA4_BIT (4) - #define PA4_BITS (1) - /* PA3 field */ - #define PA3 (0x00000008u) - #define PA3_MASK (0x00000008u) - #define PA3_BIT (3) - #define PA3_BITS (1) - /* PA2 field */ - #define PA2 (0x00000004u) - #define PA2_MASK (0x00000004u) - #define PA2_BIT (2) - #define PA2_BITS (1) - /* PA1 field */ - #define PA1 (0x00000002u) - #define PA1_MASK (0x00000002u) - #define PA1_BIT (1) - #define PA1_BITS (1) - /* PA0 field */ - #define PA0 (0x00000001u) - #define PA0_MASK (0x00000001u) - #define PA0_BIT (0) - #define PA0_BITS (1) +/* GPIO_PXSETRSVD field */ +#define GPIO_PXSETRSVD (0x0000FF00u) +#define GPIO_PXSETRSVD_MASK (0x0000FF00u) +#define GPIO_PXSETRSVD_BIT (8) +#define GPIO_PXSETRSVD_BITS (8) +/* PA7 field */ +#define PA7 (0x00000080u) +#define PA7_MASK (0x00000080u) +#define PA7_BIT (7) +#define PA7_BITS (1) +/* PA6 field */ +#define PA6 (0x00000040u) +#define PA6_MASK (0x00000040u) +#define PA6_BIT (6) +#define PA6_BITS (1) +/* PA5 field */ +#define PA5 (0x00000020u) +#define PA5_MASK (0x00000020u) +#define PA5_BIT (5) +#define PA5_BITS (1) +/* PA4 field */ +#define PA4 (0x00000010u) +#define PA4_MASK (0x00000010u) +#define PA4_BIT (4) +#define PA4_BITS (1) +/* PA3 field */ +#define PA3 (0x00000008u) +#define PA3_MASK (0x00000008u) +#define PA3_BIT (3) +#define PA3_BITS (1) +/* PA2 field */ +#define PA2 (0x00000004u) +#define PA2_MASK (0x00000004u) +#define PA2_BIT (2) +#define PA2_BITS (1) +/* PA1 field */ +#define PA1 (0x00000002u) +#define PA1_MASK (0x00000002u) +#define PA1_BIT (1) +#define PA1_BITS (1) +/* PA0 field */ +#define PA0 (0x00000001u) +#define PA0_MASK (0x00000001u) +#define PA0_BIT (0) +#define PA0_BITS (1) #define GPIO_PACLR *((volatile uint32_t *)0x4000B014u) #define GPIO_PACLR_REG *((volatile uint32_t *)0x4000B014u) #define GPIO_PACLR_ADDR (0x4000B014u) #define GPIO_PACLR_RESET (0x00000000u) - /* PA7 field */ - #define PA7 (0x00000080u) - #define PA7_MASK (0x00000080u) - #define PA7_BIT (7) - #define PA7_BITS (1) - /* PA6 field */ - #define PA6 (0x00000040u) - #define PA6_MASK (0x00000040u) - #define PA6_BIT (6) - #define PA6_BITS (1) - /* PA5 field */ - #define PA5 (0x00000020u) - #define PA5_MASK (0x00000020u) - #define PA5_BIT (5) - #define PA5_BITS (1) - /* PA4 field */ - #define PA4 (0x00000010u) - #define PA4_MASK (0x00000010u) - #define PA4_BIT (4) - #define PA4_BITS (1) - /* PA3 field */ - #define PA3 (0x00000008u) - #define PA3_MASK (0x00000008u) - #define PA3_BIT (3) - #define PA3_BITS (1) - /* PA2 field */ - #define PA2 (0x00000004u) - #define PA2_MASK (0x00000004u) - #define PA2_BIT (2) - #define PA2_BITS (1) - /* PA1 field */ - #define PA1 (0x00000002u) - #define PA1_MASK (0x00000002u) - #define PA1_BIT (1) - #define PA1_BITS (1) - /* PA0 field */ - #define PA0 (0x00000001u) - #define PA0_MASK (0x00000001u) - #define PA0_BIT (0) - #define PA0_BITS (1) +/* PA7 field */ +#define PA7 (0x00000080u) +#define PA7_MASK (0x00000080u) +#define PA7_BIT (7) +#define PA7_BITS (1) +/* PA6 field */ +#define PA6 (0x00000040u) +#define PA6_MASK (0x00000040u) +#define PA6_BIT (6) +#define PA6_BITS (1) +/* PA5 field */ +#define PA5 (0x00000020u) +#define PA5_MASK (0x00000020u) +#define PA5_BIT (5) +#define PA5_BITS (1) +/* PA4 field */ +#define PA4 (0x00000010u) +#define PA4_MASK (0x00000010u) +#define PA4_BIT (4) +#define PA4_BITS (1) +/* PA3 field */ +#define PA3 (0x00000008u) +#define PA3_MASK (0x00000008u) +#define PA3_BIT (3) +#define PA3_BITS (1) +/* PA2 field */ +#define PA2 (0x00000004u) +#define PA2_MASK (0x00000004u) +#define PA2_BIT (2) +#define PA2_BITS (1) +/* PA1 field */ +#define PA1 (0x00000002u) +#define PA1_MASK (0x00000002u) +#define PA1_BIT (1) +#define PA1_BITS (1) +/* PA0 field */ +#define PA0 (0x00000001u) +#define PA0_MASK (0x00000001u) +#define PA0_BIT (0) +#define PA0_BITS (1) #define GPIO_PBCFGL *((volatile uint32_t *)0x4000B400u) #define GPIO_PBCFGL_REG *((volatile uint32_t *)0x4000B400u) #define GPIO_PBCFGL_ADDR (0x4000B400u) #define GPIO_PBCFGL_RESET (0x00004444u) - /* PB3_CFG field */ - #define PB3_CFG (0x0000F000u) - #define PB3_CFG_MASK (0x0000F000u) - #define PB3_CFG_BIT (12) - #define PB3_CFG_BITS (4) - /* PB2_CFG field */ - #define PB2_CFG (0x00000F00u) - #define PB2_CFG_MASK (0x00000F00u) - #define PB2_CFG_BIT (8) - #define PB2_CFG_BITS (4) - /* PB1_CFG field */ - #define PB1_CFG (0x000000F0u) - #define PB1_CFG_MASK (0x000000F0u) - #define PB1_CFG_BIT (4) - #define PB1_CFG_BITS (4) - /* PB0_CFG field */ - #define PB0_CFG (0x0000000Fu) - #define PB0_CFG_MASK (0x0000000Fu) - #define PB0_CFG_BIT (0) - #define PB0_CFG_BITS (4) +/* PB3_CFG field */ +#define PB3_CFG (0x0000F000u) +#define PB3_CFG_MASK (0x0000F000u) +#define PB3_CFG_BIT (12) +#define PB3_CFG_BITS (4) +/* PB2_CFG field */ +#define PB2_CFG (0x00000F00u) +#define PB2_CFG_MASK (0x00000F00u) +#define PB2_CFG_BIT (8) +#define PB2_CFG_BITS (4) +/* PB1_CFG field */ +#define PB1_CFG (0x000000F0u) +#define PB1_CFG_MASK (0x000000F0u) +#define PB1_CFG_BIT (4) +#define PB1_CFG_BITS (4) +/* PB0_CFG field */ +#define PB0_CFG (0x0000000Fu) +#define PB0_CFG_MASK (0x0000000Fu) +#define PB0_CFG_BIT (0) +#define PB0_CFG_BITS (4) #define GPIO_PBCFGH *((volatile uint32_t *)0x4000B404u) #define GPIO_PBCFGH_REG *((volatile uint32_t *)0x4000B404u) #define GPIO_PBCFGH_ADDR (0x4000B404u) #define GPIO_PBCFGH_RESET (0x00004444u) - /* PB7_CFG field */ - #define PB7_CFG (0x0000F000u) - #define PB7_CFG_MASK (0x0000F000u) - #define PB7_CFG_BIT (12) - #define PB7_CFG_BITS (4) - /* PB6_CFG field */ - #define PB6_CFG (0x00000F00u) - #define PB6_CFG_MASK (0x00000F00u) - #define PB6_CFG_BIT (8) - #define PB6_CFG_BITS (4) - /* PB5_CFG field */ - #define PB5_CFG (0x000000F0u) - #define PB5_CFG_MASK (0x000000F0u) - #define PB5_CFG_BIT (4) - #define PB5_CFG_BITS (4) - /* PB4_CFG field */ - #define PB4_CFG (0x0000000Fu) - #define PB4_CFG_MASK (0x0000000Fu) - #define PB4_CFG_BIT (0) - #define PB4_CFG_BITS (4) +/* PB7_CFG field */ +#define PB7_CFG (0x0000F000u) +#define PB7_CFG_MASK (0x0000F000u) +#define PB7_CFG_BIT (12) +#define PB7_CFG_BITS (4) +/* PB6_CFG field */ +#define PB6_CFG (0x00000F00u) +#define PB6_CFG_MASK (0x00000F00u) +#define PB6_CFG_BIT (8) +#define PB6_CFG_BITS (4) +/* PB5_CFG field */ +#define PB5_CFG (0x000000F0u) +#define PB5_CFG_MASK (0x000000F0u) +#define PB5_CFG_BIT (4) +#define PB5_CFG_BITS (4) +/* PB4_CFG field */ +#define PB4_CFG (0x0000000Fu) +#define PB4_CFG_MASK (0x0000000Fu) +#define PB4_CFG_BIT (0) +#define PB4_CFG_BITS (4) #define GPIO_PBIN *((volatile uint32_t *)0x4000B408u) #define GPIO_PBIN_REG *((volatile uint32_t *)0x4000B408u) #define GPIO_PBIN_ADDR (0x4000B408u) #define GPIO_PBIN_RESET (0x00000000u) - /* PB7 field */ - #define PB7 (0x00000080u) - #define PB7_MASK (0x00000080u) - #define PB7_BIT (7) - #define PB7_BITS (1) - /* PB6 field */ - #define PB6 (0x00000040u) - #define PB6_MASK (0x00000040u) - #define PB6_BIT (6) - #define PB6_BITS (1) - /* PB5 field */ - #define PB5 (0x00000020u) - #define PB5_MASK (0x00000020u) - #define PB5_BIT (5) - #define PB5_BITS (1) - /* PB4 field */ - #define PB4 (0x00000010u) - #define PB4_MASK (0x00000010u) - #define PB4_BIT (4) - #define PB4_BITS (1) - /* PB3 field */ - #define PB3 (0x00000008u) - #define PB3_MASK (0x00000008u) - #define PB3_BIT (3) - #define PB3_BITS (1) - /* PB2 field */ - #define PB2 (0x00000004u) - #define PB2_MASK (0x00000004u) - #define PB2_BIT (2) - #define PB2_BITS (1) - /* PB1 field */ - #define PB1 (0x00000002u) - #define PB1_MASK (0x00000002u) - #define PB1_BIT (1) - #define PB1_BITS (1) - /* PB0 field */ - #define PB0 (0x00000001u) - #define PB0_MASK (0x00000001u) - #define PB0_BIT (0) - #define PB0_BITS (1) +/* PB7 field */ +#define PB7 (0x00000080u) +#define PB7_MASK (0x00000080u) +#define PB7_BIT (7) +#define PB7_BITS (1) +/* PB6 field */ +#define PB6 (0x00000040u) +#define PB6_MASK (0x00000040u) +#define PB6_BIT (6) +#define PB6_BITS (1) +/* PB5 field */ +#define PB5 (0x00000020u) +#define PB5_MASK (0x00000020u) +#define PB5_BIT (5) +#define PB5_BITS (1) +/* PB4 field */ +#define PB4 (0x00000010u) +#define PB4_MASK (0x00000010u) +#define PB4_BIT (4) +#define PB4_BITS (1) +/* PB3 field */ +#define PB3 (0x00000008u) +#define PB3_MASK (0x00000008u) +#define PB3_BIT (3) +#define PB3_BITS (1) +/* PB2 field */ +#define PB2 (0x00000004u) +#define PB2_MASK (0x00000004u) +#define PB2_BIT (2) +#define PB2_BITS (1) +/* PB1 field */ +#define PB1 (0x00000002u) +#define PB1_MASK (0x00000002u) +#define PB1_BIT (1) +#define PB1_BITS (1) +/* PB0 field */ +#define PB0 (0x00000001u) +#define PB0_MASK (0x00000001u) +#define PB0_BIT (0) +#define PB0_BITS (1) #define GPIO_PBOUT *((volatile uint32_t *)0x4000B40Cu) #define GPIO_PBOUT_REG *((volatile uint32_t *)0x4000B40Cu) #define GPIO_PBOUT_ADDR (0x4000B40Cu) #define GPIO_PBOUT_RESET (0x00000000u) - /* PB7 field */ - #define PB7 (0x00000080u) - #define PB7_MASK (0x00000080u) - #define PB7_BIT (7) - #define PB7_BITS (1) - /* PB6 field */ - #define PB6 (0x00000040u) - #define PB6_MASK (0x00000040u) - #define PB6_BIT (6) - #define PB6_BITS (1) - /* PB5 field */ - #define PB5 (0x00000020u) - #define PB5_MASK (0x00000020u) - #define PB5_BIT (5) - #define PB5_BITS (1) - /* PB4 field */ - #define PB4 (0x00000010u) - #define PB4_MASK (0x00000010u) - #define PB4_BIT (4) - #define PB4_BITS (1) - /* PB3 field */ - #define PB3 (0x00000008u) - #define PB3_MASK (0x00000008u) - #define PB3_BIT (3) - #define PB3_BITS (1) - /* PB2 field */ - #define PB2 (0x00000004u) - #define PB2_MASK (0x00000004u) - #define PB2_BIT (2) - #define PB2_BITS (1) - /* PB1 field */ - #define PB1 (0x00000002u) - #define PB1_MASK (0x00000002u) - #define PB1_BIT (1) - #define PB1_BITS (1) - /* PB0 field */ - #define PB0 (0x00000001u) - #define PB0_MASK (0x00000001u) - #define PB0_BIT (0) - #define PB0_BITS (1) +/* PB7 field */ +#define PB7 (0x00000080u) +#define PB7_MASK (0x00000080u) +#define PB7_BIT (7) +#define PB7_BITS (1) +/* PB6 field */ +#define PB6 (0x00000040u) +#define PB6_MASK (0x00000040u) +#define PB6_BIT (6) +#define PB6_BITS (1) +/* PB5 field */ +#define PB5 (0x00000020u) +#define PB5_MASK (0x00000020u) +#define PB5_BIT (5) +#define PB5_BITS (1) +/* PB4 field */ +#define PB4 (0x00000010u) +#define PB4_MASK (0x00000010u) +#define PB4_BIT (4) +#define PB4_BITS (1) +/* PB3 field */ +#define PB3 (0x00000008u) +#define PB3_MASK (0x00000008u) +#define PB3_BIT (3) +#define PB3_BITS (1) +/* PB2 field */ +#define PB2 (0x00000004u) +#define PB2_MASK (0x00000004u) +#define PB2_BIT (2) +#define PB2_BITS (1) +/* PB1 field */ +#define PB1 (0x00000002u) +#define PB1_MASK (0x00000002u) +#define PB1_BIT (1) +#define PB1_BITS (1) +/* PB0 field */ +#define PB0 (0x00000001u) +#define PB0_MASK (0x00000001u) +#define PB0_BIT (0) +#define PB0_BITS (1) #define GPIO_PBSET *((volatile uint32_t *)0x4000B410u) #define GPIO_PBSET_REG *((volatile uint32_t *)0x4000B410u) #define GPIO_PBSET_ADDR (0x4000B410u) #define GPIO_PBSET_RESET (0x00000000u) - /* GPIO_PXSETRSVD field */ - #define GPIO_PXSETRSVD (0x0000FF00u) - #define GPIO_PXSETRSVD_MASK (0x0000FF00u) - #define GPIO_PXSETRSVD_BIT (8) - #define GPIO_PXSETRSVD_BITS (8) - /* PB7 field */ - #define PB7 (0x00000080u) - #define PB7_MASK (0x00000080u) - #define PB7_BIT (7) - #define PB7_BITS (1) - /* PB6 field */ - #define PB6 (0x00000040u) - #define PB6_MASK (0x00000040u) - #define PB6_BIT (6) - #define PB6_BITS (1) - /* PB5 field */ - #define PB5 (0x00000020u) - #define PB5_MASK (0x00000020u) - #define PB5_BIT (5) - #define PB5_BITS (1) - /* PB4 field */ - #define PB4 (0x00000010u) - #define PB4_MASK (0x00000010u) - #define PB4_BIT (4) - #define PB4_BITS (1) - /* PB3 field */ - #define PB3 (0x00000008u) - #define PB3_MASK (0x00000008u) - #define PB3_BIT (3) - #define PB3_BITS (1) - /* PB2 field */ - #define PB2 (0x00000004u) - #define PB2_MASK (0x00000004u) - #define PB2_BIT (2) - #define PB2_BITS (1) - /* PB1 field */ - #define PB1 (0x00000002u) - #define PB1_MASK (0x00000002u) - #define PB1_BIT (1) - #define PB1_BITS (1) - /* PB0 field */ - #define PB0 (0x00000001u) - #define PB0_MASK (0x00000001u) - #define PB0_BIT (0) - #define PB0_BITS (1) +/* GPIO_PXSETRSVD field */ +#define GPIO_PXSETRSVD (0x0000FF00u) +#define GPIO_PXSETRSVD_MASK (0x0000FF00u) +#define GPIO_PXSETRSVD_BIT (8) +#define GPIO_PXSETRSVD_BITS (8) +/* PB7 field */ +#define PB7 (0x00000080u) +#define PB7_MASK (0x00000080u) +#define PB7_BIT (7) +#define PB7_BITS (1) +/* PB6 field */ +#define PB6 (0x00000040u) +#define PB6_MASK (0x00000040u) +#define PB6_BIT (6) +#define PB6_BITS (1) +/* PB5 field */ +#define PB5 (0x00000020u) +#define PB5_MASK (0x00000020u) +#define PB5_BIT (5) +#define PB5_BITS (1) +/* PB4 field */ +#define PB4 (0x00000010u) +#define PB4_MASK (0x00000010u) +#define PB4_BIT (4) +#define PB4_BITS (1) +/* PB3 field */ +#define PB3 (0x00000008u) +#define PB3_MASK (0x00000008u) +#define PB3_BIT (3) +#define PB3_BITS (1) +/* PB2 field */ +#define PB2 (0x00000004u) +#define PB2_MASK (0x00000004u) +#define PB2_BIT (2) +#define PB2_BITS (1) +/* PB1 field */ +#define PB1 (0x00000002u) +#define PB1_MASK (0x00000002u) +#define PB1_BIT (1) +#define PB1_BITS (1) +/* PB0 field */ +#define PB0 (0x00000001u) +#define PB0_MASK (0x00000001u) +#define PB0_BIT (0) +#define PB0_BITS (1) #define GPIO_PBCLR *((volatile uint32_t *)0x4000B414u) #define GPIO_PBCLR_REG *((volatile uint32_t *)0x4000B414u) #define GPIO_PBCLR_ADDR (0x4000B414u) #define GPIO_PBCLR_RESET (0x00000000u) - /* PB7 field */ - #define PB7 (0x00000080u) - #define PB7_MASK (0x00000080u) - #define PB7_BIT (7) - #define PB7_BITS (1) - /* PB6 field */ - #define PB6 (0x00000040u) - #define PB6_MASK (0x00000040u) - #define PB6_BIT (6) - #define PB6_BITS (1) - /* PB5 field */ - #define PB5 (0x00000020u) - #define PB5_MASK (0x00000020u) - #define PB5_BIT (5) - #define PB5_BITS (1) - /* PB4 field */ - #define PB4 (0x00000010u) - #define PB4_MASK (0x00000010u) - #define PB4_BIT (4) - #define PB4_BITS (1) - /* PB3 field */ - #define PB3 (0x00000008u) - #define PB3_MASK (0x00000008u) - #define PB3_BIT (3) - #define PB3_BITS (1) - /* PB2 field */ - #define PB2 (0x00000004u) - #define PB2_MASK (0x00000004u) - #define PB2_BIT (2) - #define PB2_BITS (1) - /* PB1 field */ - #define PB1 (0x00000002u) - #define PB1_MASK (0x00000002u) - #define PB1_BIT (1) - #define PB1_BITS (1) - /* PB0 field */ - #define PB0 (0x00000001u) - #define PB0_MASK (0x00000001u) - #define PB0_BIT (0) - #define PB0_BITS (1) +/* PB7 field */ +#define PB7 (0x00000080u) +#define PB7_MASK (0x00000080u) +#define PB7_BIT (7) +#define PB7_BITS (1) +/* PB6 field */ +#define PB6 (0x00000040u) +#define PB6_MASK (0x00000040u) +#define PB6_BIT (6) +#define PB6_BITS (1) +/* PB5 field */ +#define PB5 (0x00000020u) +#define PB5_MASK (0x00000020u) +#define PB5_BIT (5) +#define PB5_BITS (1) +/* PB4 field */ +#define PB4 (0x00000010u) +#define PB4_MASK (0x00000010u) +#define PB4_BIT (4) +#define PB4_BITS (1) +/* PB3 field */ +#define PB3 (0x00000008u) +#define PB3_MASK (0x00000008u) +#define PB3_BIT (3) +#define PB3_BITS (1) +/* PB2 field */ +#define PB2 (0x00000004u) +#define PB2_MASK (0x00000004u) +#define PB2_BIT (2) +#define PB2_BITS (1) +/* PB1 field */ +#define PB1 (0x00000002u) +#define PB1_MASK (0x00000002u) +#define PB1_BIT (1) +#define PB1_BITS (1) +/* PB0 field */ +#define PB0 (0x00000001u) +#define PB0_MASK (0x00000001u) +#define PB0_BIT (0) +#define PB0_BITS (1) #define GPIO_PCCFGL *((volatile uint32_t *)0x4000B800u) #define GPIO_PCCFGL_REG *((volatile uint32_t *)0x4000B800u) #define GPIO_PCCFGL_ADDR (0x4000B800u) #define GPIO_PCCFGL_RESET (0x00004444u) - /* PC3_CFG field */ - #define PC3_CFG (0x0000F000u) - #define PC3_CFG_MASK (0x0000F000u) - #define PC3_CFG_BIT (12) - #define PC3_CFG_BITS (4) - /* PC2_CFG field */ - #define PC2_CFG (0x00000F00u) - #define PC2_CFG_MASK (0x00000F00u) - #define PC2_CFG_BIT (8) - #define PC2_CFG_BITS (4) - /* PC1_CFG field */ - #define PC1_CFG (0x000000F0u) - #define PC1_CFG_MASK (0x000000F0u) - #define PC1_CFG_BIT (4) - #define PC1_CFG_BITS (4) - /* PC0_CFG field */ - #define PC0_CFG (0x0000000Fu) - #define PC0_CFG_MASK (0x0000000Fu) - #define PC0_CFG_BIT (0) - #define PC0_CFG_BITS (4) +/* PC3_CFG field */ +#define PC3_CFG (0x0000F000u) +#define PC3_CFG_MASK (0x0000F000u) +#define PC3_CFG_BIT (12) +#define PC3_CFG_BITS (4) +/* PC2_CFG field */ +#define PC2_CFG (0x00000F00u) +#define PC2_CFG_MASK (0x00000F00u) +#define PC2_CFG_BIT (8) +#define PC2_CFG_BITS (4) +/* PC1_CFG field */ +#define PC1_CFG (0x000000F0u) +#define PC1_CFG_MASK (0x000000F0u) +#define PC1_CFG_BIT (4) +#define PC1_CFG_BITS (4) +/* PC0_CFG field */ +#define PC0_CFG (0x0000000Fu) +#define PC0_CFG_MASK (0x0000000Fu) +#define PC0_CFG_BIT (0) +#define PC0_CFG_BITS (4) #define GPIO_PCCFGH *((volatile uint32_t *)0x4000B804u) #define GPIO_PCCFGH_REG *((volatile uint32_t *)0x4000B804u) #define GPIO_PCCFGH_ADDR (0x4000B804u) #define GPIO_PCCFGH_RESET (0x00004444u) - /* PC7_CFG field */ - #define PC7_CFG (0x0000F000u) - #define PC7_CFG_MASK (0x0000F000u) - #define PC7_CFG_BIT (12) - #define PC7_CFG_BITS (4) - /* PC6_CFG field */ - #define PC6_CFG (0x00000F00u) - #define PC6_CFG_MASK (0x00000F00u) - #define PC6_CFG_BIT (8) - #define PC6_CFG_BITS (4) - /* PC5_CFG field */ - #define PC5_CFG (0x000000F0u) - #define PC5_CFG_MASK (0x000000F0u) - #define PC5_CFG_BIT (4) - #define PC5_CFG_BITS (4) - /* PC4_CFG field */ - #define PC4_CFG (0x0000000Fu) - #define PC4_CFG_MASK (0x0000000Fu) - #define PC4_CFG_BIT (0) - #define PC4_CFG_BITS (4) +/* PC7_CFG field */ +#define PC7_CFG (0x0000F000u) +#define PC7_CFG_MASK (0x0000F000u) +#define PC7_CFG_BIT (12) +#define PC7_CFG_BITS (4) +/* PC6_CFG field */ +#define PC6_CFG (0x00000F00u) +#define PC6_CFG_MASK (0x00000F00u) +#define PC6_CFG_BIT (8) +#define PC6_CFG_BITS (4) +/* PC5_CFG field */ +#define PC5_CFG (0x000000F0u) +#define PC5_CFG_MASK (0x000000F0u) +#define PC5_CFG_BIT (4) +#define PC5_CFG_BITS (4) +/* PC4_CFG field */ +#define PC4_CFG (0x0000000Fu) +#define PC4_CFG_MASK (0x0000000Fu) +#define PC4_CFG_BIT (0) +#define PC4_CFG_BITS (4) #define GPIO_PCIN *((volatile uint32_t *)0x4000B808u) #define GPIO_PCIN_REG *((volatile uint32_t *)0x4000B808u) #define GPIO_PCIN_ADDR (0x4000B808u) #define GPIO_PCIN_RESET (0x00000000u) - /* PC7 field */ - #define PC7 (0x00000080u) - #define PC7_MASK (0x00000080u) - #define PC7_BIT (7) - #define PC7_BITS (1) - /* PC6 field */ - #define PC6 (0x00000040u) - #define PC6_MASK (0x00000040u) - #define PC6_BIT (6) - #define PC6_BITS (1) - /* PC5 field */ - #define PC5 (0x00000020u) - #define PC5_MASK (0x00000020u) - #define PC5_BIT (5) - #define PC5_BITS (1) - /* PC4 field */ - #define PC4 (0x00000010u) - #define PC4_MASK (0x00000010u) - #define PC4_BIT (4) - #define PC4_BITS (1) - /* PC3 field */ - #define PC3 (0x00000008u) - #define PC3_MASK (0x00000008u) - #define PC3_BIT (3) - #define PC3_BITS (1) - /* PC2 field */ - #define PC2 (0x00000004u) - #define PC2_MASK (0x00000004u) - #define PC2_BIT (2) - #define PC2_BITS (1) - /* PC1 field */ - #define PC1 (0x00000002u) - #define PC1_MASK (0x00000002u) - #define PC1_BIT (1) - #define PC1_BITS (1) - /* PC0 field */ - #define PC0 (0x00000001u) - #define PC0_MASK (0x00000001u) - #define PC0_BIT (0) - #define PC0_BITS (1) +/* PC7 field */ +#define PC7 (0x00000080u) +#define PC7_MASK (0x00000080u) +#define PC7_BIT (7) +#define PC7_BITS (1) +/* PC6 field */ +#define PC6 (0x00000040u) +#define PC6_MASK (0x00000040u) +#define PC6_BIT (6) +#define PC6_BITS (1) +/* PC5 field */ +#define PC5 (0x00000020u) +#define PC5_MASK (0x00000020u) +#define PC5_BIT (5) +#define PC5_BITS (1) +/* PC4 field */ +#define PC4 (0x00000010u) +#define PC4_MASK (0x00000010u) +#define PC4_BIT (4) +#define PC4_BITS (1) +/* PC3 field */ +#define PC3 (0x00000008u) +#define PC3_MASK (0x00000008u) +#define PC3_BIT (3) +#define PC3_BITS (1) +/* PC2 field */ +#define PC2 (0x00000004u) +#define PC2_MASK (0x00000004u) +#define PC2_BIT (2) +#define PC2_BITS (1) +/* PC1 field */ +#define PC1 (0x00000002u) +#define PC1_MASK (0x00000002u) +#define PC1_BIT (1) +#define PC1_BITS (1) +/* PC0 field */ +#define PC0 (0x00000001u) +#define PC0_MASK (0x00000001u) +#define PC0_BIT (0) +#define PC0_BITS (1) #define GPIO_PCOUT *((volatile uint32_t *)0x4000B80Cu) #define GPIO_PCOUT_REG *((volatile uint32_t *)0x4000B80Cu) #define GPIO_PCOUT_ADDR (0x4000B80Cu) #define GPIO_PCOUT_RESET (0x00000000u) - /* PC7 field */ - #define PC7 (0x00000080u) - #define PC7_MASK (0x00000080u) - #define PC7_BIT (7) - #define PC7_BITS (1) - /* PC6 field */ - #define PC6 (0x00000040u) - #define PC6_MASK (0x00000040u) - #define PC6_BIT (6) - #define PC6_BITS (1) - /* PC5 field */ - #define PC5 (0x00000020u) - #define PC5_MASK (0x00000020u) - #define PC5_BIT (5) - #define PC5_BITS (1) - /* PC4 field */ - #define PC4 (0x00000010u) - #define PC4_MASK (0x00000010u) - #define PC4_BIT (4) - #define PC4_BITS (1) - /* PC3 field */ - #define PC3 (0x00000008u) - #define PC3_MASK (0x00000008u) - #define PC3_BIT (3) - #define PC3_BITS (1) - /* PC2 field */ - #define PC2 (0x00000004u) - #define PC2_MASK (0x00000004u) - #define PC2_BIT (2) - #define PC2_BITS (1) - /* PC1 field */ - #define PC1 (0x00000002u) - #define PC1_MASK (0x00000002u) - #define PC1_BIT (1) - #define PC1_BITS (1) - /* PC0 field */ - #define PC0 (0x00000001u) - #define PC0_MASK (0x00000001u) - #define PC0_BIT (0) - #define PC0_BITS (1) +/* PC7 field */ +#define PC7 (0x00000080u) +#define PC7_MASK (0x00000080u) +#define PC7_BIT (7) +#define PC7_BITS (1) +/* PC6 field */ +#define PC6 (0x00000040u) +#define PC6_MASK (0x00000040u) +#define PC6_BIT (6) +#define PC6_BITS (1) +/* PC5 field */ +#define PC5 (0x00000020u) +#define PC5_MASK (0x00000020u) +#define PC5_BIT (5) +#define PC5_BITS (1) +/* PC4 field */ +#define PC4 (0x00000010u) +#define PC4_MASK (0x00000010u) +#define PC4_BIT (4) +#define PC4_BITS (1) +/* PC3 field */ +#define PC3 (0x00000008u) +#define PC3_MASK (0x00000008u) +#define PC3_BIT (3) +#define PC3_BITS (1) +/* PC2 field */ +#define PC2 (0x00000004u) +#define PC2_MASK (0x00000004u) +#define PC2_BIT (2) +#define PC2_BITS (1) +/* PC1 field */ +#define PC1 (0x00000002u) +#define PC1_MASK (0x00000002u) +#define PC1_BIT (1) +#define PC1_BITS (1) +/* PC0 field */ +#define PC0 (0x00000001u) +#define PC0_MASK (0x00000001u) +#define PC0_BIT (0) +#define PC0_BITS (1) #define GPIO_PCSET *((volatile uint32_t *)0x4000B810u) #define GPIO_PCSET_REG *((volatile uint32_t *)0x4000B810u) #define GPIO_PCSET_ADDR (0x4000B810u) #define GPIO_PCSET_RESET (0x00000000u) - /* GPIO_PXSETRSVD field */ - #define GPIO_PXSETRSVD (0x0000FF00u) - #define GPIO_PXSETRSVD_MASK (0x0000FF00u) - #define GPIO_PXSETRSVD_BIT (8) - #define GPIO_PXSETRSVD_BITS (8) - /* PC7 field */ - #define PC7 (0x00000080u) - #define PC7_MASK (0x00000080u) - #define PC7_BIT (7) - #define PC7_BITS (1) - /* PC6 field */ - #define PC6 (0x00000040u) - #define PC6_MASK (0x00000040u) - #define PC6_BIT (6) - #define PC6_BITS (1) - /* PC5 field */ - #define PC5 (0x00000020u) - #define PC5_MASK (0x00000020u) - #define PC5_BIT (5) - #define PC5_BITS (1) - /* PC4 field */ - #define PC4 (0x00000010u) - #define PC4_MASK (0x00000010u) - #define PC4_BIT (4) - #define PC4_BITS (1) - /* PC3 field */ - #define PC3 (0x00000008u) - #define PC3_MASK (0x00000008u) - #define PC3_BIT (3) - #define PC3_BITS (1) - /* PC2 field */ - #define PC2 (0x00000004u) - #define PC2_MASK (0x00000004u) - #define PC2_BIT (2) - #define PC2_BITS (1) - /* PC1 field */ - #define PC1 (0x00000002u) - #define PC1_MASK (0x00000002u) - #define PC1_BIT (1) - #define PC1_BITS (1) - /* PC0 field */ - #define PC0 (0x00000001u) - #define PC0_MASK (0x00000001u) - #define PC0_BIT (0) - #define PC0_BITS (1) +/* GPIO_PXSETRSVD field */ +#define GPIO_PXSETRSVD (0x0000FF00u) +#define GPIO_PXSETRSVD_MASK (0x0000FF00u) +#define GPIO_PXSETRSVD_BIT (8) +#define GPIO_PXSETRSVD_BITS (8) +/* PC7 field */ +#define PC7 (0x00000080u) +#define PC7_MASK (0x00000080u) +#define PC7_BIT (7) +#define PC7_BITS (1) +/* PC6 field */ +#define PC6 (0x00000040u) +#define PC6_MASK (0x00000040u) +#define PC6_BIT (6) +#define PC6_BITS (1) +/* PC5 field */ +#define PC5 (0x00000020u) +#define PC5_MASK (0x00000020u) +#define PC5_BIT (5) +#define PC5_BITS (1) +/* PC4 field */ +#define PC4 (0x00000010u) +#define PC4_MASK (0x00000010u) +#define PC4_BIT (4) +#define PC4_BITS (1) +/* PC3 field */ +#define PC3 (0x00000008u) +#define PC3_MASK (0x00000008u) +#define PC3_BIT (3) +#define PC3_BITS (1) +/* PC2 field */ +#define PC2 (0x00000004u) +#define PC2_MASK (0x00000004u) +#define PC2_BIT (2) +#define PC2_BITS (1) +/* PC1 field */ +#define PC1 (0x00000002u) +#define PC1_MASK (0x00000002u) +#define PC1_BIT (1) +#define PC1_BITS (1) +/* PC0 field */ +#define PC0 (0x00000001u) +#define PC0_MASK (0x00000001u) +#define PC0_BIT (0) +#define PC0_BITS (1) #define GPIO_PCCLR *((volatile uint32_t *)0x4000B814u) #define GPIO_PCCLR_REG *((volatile uint32_t *)0x4000B814u) #define GPIO_PCCLR_ADDR (0x4000B814u) #define GPIO_PCCLR_RESET (0x00000000u) - /* PC7 field */ - #define PC7 (0x00000080u) - #define PC7_MASK (0x00000080u) - #define PC7_BIT (7) - #define PC7_BITS (1) - /* PC6 field */ - #define PC6 (0x00000040u) - #define PC6_MASK (0x00000040u) - #define PC6_BIT (6) - #define PC6_BITS (1) - /* PC5 field */ - #define PC5 (0x00000020u) - #define PC5_MASK (0x00000020u) - #define PC5_BIT (5) - #define PC5_BITS (1) - /* PC4 field */ - #define PC4 (0x00000010u) - #define PC4_MASK (0x00000010u) - #define PC4_BIT (4) - #define PC4_BITS (1) - /* PC3 field */ - #define PC3 (0x00000008u) - #define PC3_MASK (0x00000008u) - #define PC3_BIT (3) - #define PC3_BITS (1) - /* PC2 field */ - #define PC2 (0x00000004u) - #define PC2_MASK (0x00000004u) - #define PC2_BIT (2) - #define PC2_BITS (1) - /* PC1 field */ - #define PC1 (0x00000002u) - #define PC1_MASK (0x00000002u) - #define PC1_BIT (1) - #define PC1_BITS (1) - /* PC0 field */ - #define PC0 (0x00000001u) - #define PC0_MASK (0x00000001u) - #define PC0_BIT (0) - #define PC0_BITS (1) +/* PC7 field */ +#define PC7 (0x00000080u) +#define PC7_MASK (0x00000080u) +#define PC7_BIT (7) +#define PC7_BITS (1) +/* PC6 field */ +#define PC6 (0x00000040u) +#define PC6_MASK (0x00000040u) +#define PC6_BIT (6) +#define PC6_BITS (1) +/* PC5 field */ +#define PC5 (0x00000020u) +#define PC5_MASK (0x00000020u) +#define PC5_BIT (5) +#define PC5_BITS (1) +/* PC4 field */ +#define PC4 (0x00000010u) +#define PC4_MASK (0x00000010u) +#define PC4_BIT (4) +#define PC4_BITS (1) +/* PC3 field */ +#define PC3 (0x00000008u) +#define PC3_MASK (0x00000008u) +#define PC3_BIT (3) +#define PC3_BITS (1) +/* PC2 field */ +#define PC2 (0x00000004u) +#define PC2_MASK (0x00000004u) +#define PC2_BIT (2) +#define PC2_BITS (1) +/* PC1 field */ +#define PC1 (0x00000002u) +#define PC1_MASK (0x00000002u) +#define PC1_BIT (1) +#define PC1_BITS (1) +/* PC0 field */ +#define PC0 (0x00000001u) +#define PC0_MASK (0x00000001u) +#define PC0_BIT (0) +#define PC0_BITS (1) #define GPIO_DBGCFG *((volatile uint32_t *)0x4000BC00u) #define GPIO_DBGCFG_REG *((volatile uint32_t *)0x4000BC00u) #define GPIO_DBGCFG_ADDR (0x4000BC00u) #define GPIO_DBGCFG_RESET (0x00000010u) - /* GPIO_DEBUGDIS field */ - #define GPIO_DEBUGDIS (0x00000020u) - #define GPIO_DEBUGDIS_MASK (0x00000020u) - #define GPIO_DEBUGDIS_BIT (5) - #define GPIO_DEBUGDIS_BITS (1) - /* GPIO_EXTREGEN field */ - #define GPIO_EXTREGEN (0x00000010u) - #define GPIO_EXTREGEN_MASK (0x00000010u) - #define GPIO_EXTREGEN_BIT (4) - #define GPIO_EXTREGEN_BITS (1) - /* GPIO_DBGCFGRSVD field */ - #define GPIO_DBGCFGRSVD (0x00000008u) - #define GPIO_DBGCFGRSVD_MASK (0x00000008u) - #define GPIO_DBGCFGRSVD_BIT (3) - #define GPIO_DBGCFGRSVD_BITS (1) +/* GPIO_DEBUGDIS field */ +#define GPIO_DEBUGDIS (0x00000020u) +#define GPIO_DEBUGDIS_MASK (0x00000020u) +#define GPIO_DEBUGDIS_BIT (5) +#define GPIO_DEBUGDIS_BITS (1) +/* GPIO_EXTREGEN field */ +#define GPIO_EXTREGEN (0x00000010u) +#define GPIO_EXTREGEN_MASK (0x00000010u) +#define GPIO_EXTREGEN_BIT (4) +#define GPIO_EXTREGEN_BITS (1) +/* GPIO_DBGCFGRSVD field */ +#define GPIO_DBGCFGRSVD (0x00000008u) +#define GPIO_DBGCFGRSVD_MASK (0x00000008u) +#define GPIO_DBGCFGRSVD_BIT (3) +#define GPIO_DBGCFGRSVD_BITS (1) #define GPIO_DBGSTAT *((volatile uint32_t *)0x4000BC04u) #define GPIO_DBGSTAT_REG *((volatile uint32_t *)0x4000BC04u) #define GPIO_DBGSTAT_ADDR (0x4000BC04u) #define GPIO_DBGSTAT_RESET (0x00000000u) - /* GPIO_BOOTMODE field */ - #define GPIO_BOOTMODE (0x00000008u) - #define GPIO_BOOTMODE_MASK (0x00000008u) - #define GPIO_BOOTMODE_BIT (3) - #define GPIO_BOOTMODE_BITS (1) - /* GPIO_FORCEDBG field */ - #define GPIO_FORCEDBG (0x00000002u) - #define GPIO_FORCEDBG_MASK (0x00000002u) - #define GPIO_FORCEDBG_BIT (1) - #define GPIO_FORCEDBG_BITS (1) - /* GPIO_SWEN field */ - #define GPIO_SWEN (0x00000001u) - #define GPIO_SWEN_MASK (0x00000001u) - #define GPIO_SWEN_BIT (0) - #define GPIO_SWEN_BITS (1) +/* GPIO_BOOTMODE field */ +#define GPIO_BOOTMODE (0x00000008u) +#define GPIO_BOOTMODE_MASK (0x00000008u) +#define GPIO_BOOTMODE_BIT (3) +#define GPIO_BOOTMODE_BITS (1) +/* GPIO_FORCEDBG field */ +#define GPIO_FORCEDBG (0x00000002u) +#define GPIO_FORCEDBG_MASK (0x00000002u) +#define GPIO_FORCEDBG_BIT (1) +#define GPIO_FORCEDBG_BITS (1) +/* GPIO_SWEN field */ +#define GPIO_SWEN (0x00000001u) +#define GPIO_SWEN_MASK (0x00000001u) +#define GPIO_SWEN_BIT (0) +#define GPIO_SWEN_BITS (1) #define GPIO_PAWAKE *((volatile uint32_t *)0x4000BC08u) #define GPIO_PAWAKE_REG *((volatile uint32_t *)0x4000BC08u) #define GPIO_PAWAKE_ADDR (0x4000BC08u) #define GPIO_PAWAKE_RESET (0x00000000u) - /* PA7 field */ - #define PA7 (0x00000080u) - #define PA7_MASK (0x00000080u) - #define PA7_BIT (7) - #define PA7_BITS (1) - /* PA6 field */ - #define PA6 (0x00000040u) - #define PA6_MASK (0x00000040u) - #define PA6_BIT (6) - #define PA6_BITS (1) - /* PA5 field */ - #define PA5 (0x00000020u) - #define PA5_MASK (0x00000020u) - #define PA5_BIT (5) - #define PA5_BITS (1) - /* PA4 field */ - #define PA4 (0x00000010u) - #define PA4_MASK (0x00000010u) - #define PA4_BIT (4) - #define PA4_BITS (1) - /* PA3 field */ - #define PA3 (0x00000008u) - #define PA3_MASK (0x00000008u) - #define PA3_BIT (3) - #define PA3_BITS (1) - /* PA2 field */ - #define PA2 (0x00000004u) - #define PA2_MASK (0x00000004u) - #define PA2_BIT (2) - #define PA2_BITS (1) - /* PA1 field */ - #define PA1 (0x00000002u) - #define PA1_MASK (0x00000002u) - #define PA1_BIT (1) - #define PA1_BITS (1) - /* PA0 field */ - #define PA0 (0x00000001u) - #define PA0_MASK (0x00000001u) - #define PA0_BIT (0) - #define PA0_BITS (1) +/* PA7 field */ +#define PA7 (0x00000080u) +#define PA7_MASK (0x00000080u) +#define PA7_BIT (7) +#define PA7_BITS (1) +/* PA6 field */ +#define PA6 (0x00000040u) +#define PA6_MASK (0x00000040u) +#define PA6_BIT (6) +#define PA6_BITS (1) +/* PA5 field */ +#define PA5 (0x00000020u) +#define PA5_MASK (0x00000020u) +#define PA5_BIT (5) +#define PA5_BITS (1) +/* PA4 field */ +#define PA4 (0x00000010u) +#define PA4_MASK (0x00000010u) +#define PA4_BIT (4) +#define PA4_BITS (1) +/* PA3 field */ +#define PA3 (0x00000008u) +#define PA3_MASK (0x00000008u) +#define PA3_BIT (3) +#define PA3_BITS (1) +/* PA2 field */ +#define PA2 (0x00000004u) +#define PA2_MASK (0x00000004u) +#define PA2_BIT (2) +#define PA2_BITS (1) +/* PA1 field */ +#define PA1 (0x00000002u) +#define PA1_MASK (0x00000002u) +#define PA1_BIT (1) +#define PA1_BITS (1) +/* PA0 field */ +#define PA0 (0x00000001u) +#define PA0_MASK (0x00000001u) +#define PA0_BIT (0) +#define PA0_BITS (1) #define GPIO_PBWAKE *((volatile uint32_t *)0x4000BC0Cu) #define GPIO_PBWAKE_REG *((volatile uint32_t *)0x4000BC0Cu) #define GPIO_PBWAKE_ADDR (0x4000BC0Cu) #define GPIO_PBWAKE_RESET (0x00000000u) - /* PB7 field */ - #define PB7 (0x00000080u) - #define PB7_MASK (0x00000080u) - #define PB7_BIT (7) - #define PB7_BITS (1) - /* PB6 field */ - #define PB6 (0x00000040u) - #define PB6_MASK (0x00000040u) - #define PB6_BIT (6) - #define PB6_BITS (1) - /* PB5 field */ - #define PB5 (0x00000020u) - #define PB5_MASK (0x00000020u) - #define PB5_BIT (5) - #define PB5_BITS (1) - /* PB4 field */ - #define PB4 (0x00000010u) - #define PB4_MASK (0x00000010u) - #define PB4_BIT (4) - #define PB4_BITS (1) - /* PB3 field */ - #define PB3 (0x00000008u) - #define PB3_MASK (0x00000008u) - #define PB3_BIT (3) - #define PB3_BITS (1) - /* PB2 field */ - #define PB2 (0x00000004u) - #define PB2_MASK (0x00000004u) - #define PB2_BIT (2) - #define PB2_BITS (1) - /* PB1 field */ - #define PB1 (0x00000002u) - #define PB1_MASK (0x00000002u) - #define PB1_BIT (1) - #define PB1_BITS (1) - /* PB0 field */ - #define PB0 (0x00000001u) - #define PB0_MASK (0x00000001u) - #define PB0_BIT (0) - #define PB0_BITS (1) +/* PB7 field */ +#define PB7 (0x00000080u) +#define PB7_MASK (0x00000080u) +#define PB7_BIT (7) +#define PB7_BITS (1) +/* PB6 field */ +#define PB6 (0x00000040u) +#define PB6_MASK (0x00000040u) +#define PB6_BIT (6) +#define PB6_BITS (1) +/* PB5 field */ +#define PB5 (0x00000020u) +#define PB5_MASK (0x00000020u) +#define PB5_BIT (5) +#define PB5_BITS (1) +/* PB4 field */ +#define PB4 (0x00000010u) +#define PB4_MASK (0x00000010u) +#define PB4_BIT (4) +#define PB4_BITS (1) +/* PB3 field */ +#define PB3 (0x00000008u) +#define PB3_MASK (0x00000008u) +#define PB3_BIT (3) +#define PB3_BITS (1) +/* PB2 field */ +#define PB2 (0x00000004u) +#define PB2_MASK (0x00000004u) +#define PB2_BIT (2) +#define PB2_BITS (1) +/* PB1 field */ +#define PB1 (0x00000002u) +#define PB1_MASK (0x00000002u) +#define PB1_BIT (1) +#define PB1_BITS (1) +/* PB0 field */ +#define PB0 (0x00000001u) +#define PB0_MASK (0x00000001u) +#define PB0_BIT (0) +#define PB0_BITS (1) #define GPIO_PCWAKE *((volatile uint32_t *)0x4000BC10u) #define GPIO_PCWAKE_REG *((volatile uint32_t *)0x4000BC10u) #define GPIO_PCWAKE_ADDR (0x4000BC10u) #define GPIO_PCWAKE_RESET (0x00000000u) - /* PC7 field */ - #define PC7 (0x00000080u) - #define PC7_MASK (0x00000080u) - #define PC7_BIT (7) - #define PC7_BITS (1) - /* PC6 field */ - #define PC6 (0x00000040u) - #define PC6_MASK (0x00000040u) - #define PC6_BIT (6) - #define PC6_BITS (1) - /* PC5 field */ - #define PC5 (0x00000020u) - #define PC5_MASK (0x00000020u) - #define PC5_BIT (5) - #define PC5_BITS (1) - /* PC4 field */ - #define PC4 (0x00000010u) - #define PC4_MASK (0x00000010u) - #define PC4_BIT (4) - #define PC4_BITS (1) - /* PC3 field */ - #define PC3 (0x00000008u) - #define PC3_MASK (0x00000008u) - #define PC3_BIT (3) - #define PC3_BITS (1) - /* PC2 field */ - #define PC2 (0x00000004u) - #define PC2_MASK (0x00000004u) - #define PC2_BIT (2) - #define PC2_BITS (1) - /* PC1 field */ - #define PC1 (0x00000002u) - #define PC1_MASK (0x00000002u) - #define PC1_BIT (1) - #define PC1_BITS (1) - /* PC0 field */ - #define PC0 (0x00000001u) - #define PC0_MASK (0x00000001u) - #define PC0_BIT (0) - #define PC0_BITS (1) +/* PC7 field */ +#define PC7 (0x00000080u) +#define PC7_MASK (0x00000080u) +#define PC7_BIT (7) +#define PC7_BITS (1) +/* PC6 field */ +#define PC6 (0x00000040u) +#define PC6_MASK (0x00000040u) +#define PC6_BIT (6) +#define PC6_BITS (1) +/* PC5 field */ +#define PC5 (0x00000020u) +#define PC5_MASK (0x00000020u) +#define PC5_BIT (5) +#define PC5_BITS (1) +/* PC4 field */ +#define PC4 (0x00000010u) +#define PC4_MASK (0x00000010u) +#define PC4_BIT (4) +#define PC4_BITS (1) +/* PC3 field */ +#define PC3 (0x00000008u) +#define PC3_MASK (0x00000008u) +#define PC3_BIT (3) +#define PC3_BITS (1) +/* PC2 field */ +#define PC2 (0x00000004u) +#define PC2_MASK (0x00000004u) +#define PC2_BIT (2) +#define PC2_BITS (1) +/* PC1 field */ +#define PC1 (0x00000002u) +#define PC1_MASK (0x00000002u) +#define PC1_BIT (1) +#define PC1_BITS (1) +/* PC0 field */ +#define PC0 (0x00000001u) +#define PC0_MASK (0x00000001u) +#define PC0_BIT (0) +#define PC0_BITS (1) #define GPIO_IRQCSEL *((volatile uint32_t *)0x4000BC14u) #define GPIO_IRQCSEL_REG *((volatile uint32_t *)0x4000BC14u) #define GPIO_IRQCSEL_ADDR (0x4000BC14u) #define GPIO_IRQCSEL_RESET (0x0000000Fu) - /* SEL_GPIO field */ - #define SEL_GPIO (0x0000001Fu) - #define SEL_GPIO_MASK (0x0000001Fu) - #define SEL_GPIO_BIT (0) - #define SEL_GPIO_BITS (5) +/* SEL_GPIO field */ +#define SEL_GPIO (0x0000001Fu) +#define SEL_GPIO_MASK (0x0000001Fu) +#define SEL_GPIO_BIT (0) +#define SEL_GPIO_BITS (5) #define GPIO_IRQDSEL *((volatile uint32_t *)0x4000BC18u) #define GPIO_IRQDSEL_REG *((volatile uint32_t *)0x4000BC18u) #define GPIO_IRQDSEL_ADDR (0x4000BC18u) #define GPIO_IRQDSEL_RESET (0x00000010u) - /* SEL_GPIO field */ - #define SEL_GPIO (0x0000001Fu) - #define SEL_GPIO_MASK (0x0000001Fu) - #define SEL_GPIO_BIT (0) - #define SEL_GPIO_BITS (5) +/* SEL_GPIO field */ +#define SEL_GPIO (0x0000001Fu) +#define SEL_GPIO_MASK (0x0000001Fu) +#define SEL_GPIO_BIT (0) +#define SEL_GPIO_BITS (5) #define GPIO_WAKEFILT *((volatile uint32_t *)0x4000BC1Cu) #define GPIO_WAKEFILT_REG *((volatile uint32_t *)0x4000BC1Cu) #define GPIO_WAKEFILT_ADDR (0x4000BC1Cu) #define GPIO_WAKEFILT_RESET (0x00000000u) - /* IRQD_WAKE_FILTER field */ - #define IRQD_WAKE_FILTER (0x00000008u) - #define IRQD_WAKE_FILTER_MASK (0x00000008u) - #define IRQD_WAKE_FILTER_BIT (3) - #define IRQD_WAKE_FILTER_BITS (1) - /* SC2_WAKE_FILTER field */ - #define SC2_WAKE_FILTER (0x00000004u) - #define SC2_WAKE_FILTER_MASK (0x00000004u) - #define SC2_WAKE_FILTER_BIT (2) - #define SC2_WAKE_FILTER_BITS (1) - /* SC1_WAKE_FILTER field */ - #define SC1_WAKE_FILTER (0x00000002u) - #define SC1_WAKE_FILTER_MASK (0x00000002u) - #define SC1_WAKE_FILTER_BIT (1) - #define SC1_WAKE_FILTER_BITS (1) - /* GPIO_WAKE_FILTER field */ - #define GPIO_WAKE_FILTER (0x00000001u) - #define GPIO_WAKE_FILTER_MASK (0x00000001u) - #define GPIO_WAKE_FILTER_BIT (0) - #define GPIO_WAKE_FILTER_BITS (1) +/* IRQD_WAKE_FILTER field */ +#define IRQD_WAKE_FILTER (0x00000008u) +#define IRQD_WAKE_FILTER_MASK (0x00000008u) +#define IRQD_WAKE_FILTER_BIT (3) +#define IRQD_WAKE_FILTER_BITS (1) +/* SC2_WAKE_FILTER field */ +#define SC2_WAKE_FILTER (0x00000004u) +#define SC2_WAKE_FILTER_MASK (0x00000004u) +#define SC2_WAKE_FILTER_BIT (2) +#define SC2_WAKE_FILTER_BITS (1) +/* SC1_WAKE_FILTER field */ +#define SC1_WAKE_FILTER (0x00000002u) +#define SC1_WAKE_FILTER_MASK (0x00000002u) +#define SC1_WAKE_FILTER_BIT (1) +#define SC1_WAKE_FILTER_BITS (1) +/* GPIO_WAKE_FILTER field */ +#define GPIO_WAKE_FILTER (0x00000001u) +#define GPIO_WAKE_FILTER_MASK (0x00000001u) +#define GPIO_WAKE_FILTER_BIT (0) +#define GPIO_WAKE_FILTER_BITS (1) /* SERIAL block */ #define BLOCK_SERIAL_BASE (0x4000C000u) @@ -5535,960 +5535,960 @@ #define SC2_RXBEGA_REG *((volatile uint32_t *)0x4000C000u) #define SC2_RXBEGA_ADDR (0x4000C000u) #define SC2_RXBEGA_RESET (0x20000000u) - /* FIXED field */ - #define SC2_RXBEGA_FIXED (0xFFFFE000u) - #define SC2_RXBEGA_FIXED_MASK (0xFFFFE000u) - #define SC2_RXBEGA_FIXED_BIT (13) - #define SC2_RXBEGA_FIXED_BITS (19) - /* SC_RXBEGA field */ - #define SC_RXBEGA (0x00001FFFu) - #define SC_RXBEGA_MASK (0x00001FFFu) - #define SC_RXBEGA_BIT (0) - #define SC_RXBEGA_BITS (13) +/* FIXED field */ +#define SC2_RXBEGA_FIXED (0xFFFFE000u) +#define SC2_RXBEGA_FIXED_MASK (0xFFFFE000u) +#define SC2_RXBEGA_FIXED_BIT (13) +#define SC2_RXBEGA_FIXED_BITS (19) +/* SC_RXBEGA field */ +#define SC_RXBEGA (0x00001FFFu) +#define SC_RXBEGA_MASK (0x00001FFFu) +#define SC_RXBEGA_BIT (0) +#define SC_RXBEGA_BITS (13) #define SC2_RXENDA *((volatile uint32_t *)0x4000C004u) #define SC2_RXENDA_REG *((volatile uint32_t *)0x4000C004u) #define SC2_RXENDA_ADDR (0x4000C004u) #define SC2_RXENDA_RESET (0x20000000u) - /* FIXED field */ - #define SC2_RXENDA_FIXED (0xFFFFE000u) - #define SC2_RXENDA_FIXED_MASK (0xFFFFE000u) - #define SC2_RXENDA_FIXED_BIT (13) - #define SC2_RXENDA_FIXED_BITS (19) - /* SC_RXENDA field */ - #define SC_RXENDA (0x00001FFFu) - #define SC_RXENDA_MASK (0x00001FFFu) - #define SC_RXENDA_BIT (0) - #define SC_RXENDA_BITS (13) +/* FIXED field */ +#define SC2_RXENDA_FIXED (0xFFFFE000u) +#define SC2_RXENDA_FIXED_MASK (0xFFFFE000u) +#define SC2_RXENDA_FIXED_BIT (13) +#define SC2_RXENDA_FIXED_BITS (19) +/* SC_RXENDA field */ +#define SC_RXENDA (0x00001FFFu) +#define SC_RXENDA_MASK (0x00001FFFu) +#define SC_RXENDA_BIT (0) +#define SC_RXENDA_BITS (13) #define SC2_RXBEGB *((volatile uint32_t *)0x4000C008u) #define SC2_RXBEGB_REG *((volatile uint32_t *)0x4000C008u) #define SC2_RXBEGB_ADDR (0x4000C008u) #define SC2_RXBEGB_RESET (0x20000000u) - /* FIXED field */ - #define SC2_RXBEGB_FIXED (0xFFFFE000u) - #define SC2_RXBEGB_FIXED_MASK (0xFFFFE000u) - #define SC2_RXBEGB_FIXED_BIT (13) - #define SC2_RXBEGB_FIXED_BITS (19) - /* SC_RXBEGB field */ - #define SC_RXBEGB (0x00001FFFu) - #define SC_RXBEGB_MASK (0x00001FFFu) - #define SC_RXBEGB_BIT (0) - #define SC_RXBEGB_BITS (13) +/* FIXED field */ +#define SC2_RXBEGB_FIXED (0xFFFFE000u) +#define SC2_RXBEGB_FIXED_MASK (0xFFFFE000u) +#define SC2_RXBEGB_FIXED_BIT (13) +#define SC2_RXBEGB_FIXED_BITS (19) +/* SC_RXBEGB field */ +#define SC_RXBEGB (0x00001FFFu) +#define SC_RXBEGB_MASK (0x00001FFFu) +#define SC_RXBEGB_BIT (0) +#define SC_RXBEGB_BITS (13) #define SC2_RXENDB *((volatile uint32_t *)0x4000C00Cu) #define SC2_RXENDB_REG *((volatile uint32_t *)0x4000C00Cu) #define SC2_RXENDB_ADDR (0x4000C00Cu) #define SC2_RXENDB_RESET (0x20000000u) - /* FIXED field */ - #define SC2_RXENDB_FIXED (0xFFFFE000u) - #define SC2_RXENDB_FIXED_MASK (0xFFFFE000u) - #define SC2_RXENDB_FIXED_BIT (13) - #define SC2_RXENDB_FIXED_BITS (19) - /* SC_RXENDB field */ - #define SC_RXENDB (0x00001FFFu) - #define SC_RXENDB_MASK (0x00001FFFu) - #define SC_RXENDB_BIT (0) - #define SC_RXENDB_BITS (13) +/* FIXED field */ +#define SC2_RXENDB_FIXED (0xFFFFE000u) +#define SC2_RXENDB_FIXED_MASK (0xFFFFE000u) +#define SC2_RXENDB_FIXED_BIT (13) +#define SC2_RXENDB_FIXED_BITS (19) +/* SC_RXENDB field */ +#define SC_RXENDB (0x00001FFFu) +#define SC_RXENDB_MASK (0x00001FFFu) +#define SC_RXENDB_BIT (0) +#define SC_RXENDB_BITS (13) #define SC2_TXBEGA *((volatile uint32_t *)0x4000C010u) #define SC2_TXBEGA_REG *((volatile uint32_t *)0x4000C010u) #define SC2_TXBEGA_ADDR (0x4000C010u) #define SC2_TXBEGA_RESET (0x20000000u) - /* FIXED field */ - #define SC2_TXBEGA_FIXED (0xFFFFE000u) - #define SC2_TXBEGA_FIXED_MASK (0xFFFFE000u) - #define SC2_TXBEGA_FIXED_BIT (13) - #define SC2_TXBEGA_FIXED_BITS (19) - /* SC_TXBEGA field */ - #define SC_TXBEGA (0x00001FFFu) - #define SC_TXBEGA_MASK (0x00001FFFu) - #define SC_TXBEGA_BIT (0) - #define SC_TXBEGA_BITS (13) +/* FIXED field */ +#define SC2_TXBEGA_FIXED (0xFFFFE000u) +#define SC2_TXBEGA_FIXED_MASK (0xFFFFE000u) +#define SC2_TXBEGA_FIXED_BIT (13) +#define SC2_TXBEGA_FIXED_BITS (19) +/* SC_TXBEGA field */ +#define SC_TXBEGA (0x00001FFFu) +#define SC_TXBEGA_MASK (0x00001FFFu) +#define SC_TXBEGA_BIT (0) +#define SC_TXBEGA_BITS (13) #define SC2_TXENDA *((volatile uint32_t *)0x4000C014u) #define SC2_TXENDA_REG *((volatile uint32_t *)0x4000C014u) #define SC2_TXENDA_ADDR (0x4000C014u) #define SC2_TXENDA_RESET (0x20000000u) - /* FIXED field */ - #define SC2_TXENDA_FIXED (0xFFFFE000u) - #define SC2_TXENDA_FIXED_MASK (0xFFFFE000u) - #define SC2_TXENDA_FIXED_BIT (13) - #define SC2_TXENDA_FIXED_BITS (19) - /* SC_TXENDA field */ - #define SC_TXENDA (0x00001FFFu) - #define SC_TXENDA_MASK (0x00001FFFu) - #define SC_TXENDA_BIT (0) - #define SC_TXENDA_BITS (13) +/* FIXED field */ +#define SC2_TXENDA_FIXED (0xFFFFE000u) +#define SC2_TXENDA_FIXED_MASK (0xFFFFE000u) +#define SC2_TXENDA_FIXED_BIT (13) +#define SC2_TXENDA_FIXED_BITS (19) +/* SC_TXENDA field */ +#define SC_TXENDA (0x00001FFFu) +#define SC_TXENDA_MASK (0x00001FFFu) +#define SC_TXENDA_BIT (0) +#define SC_TXENDA_BITS (13) #define SC2_TXBEGB *((volatile uint32_t *)0x4000C018u) #define SC2_TXBEGB_REG *((volatile uint32_t *)0x4000C018u) #define SC2_TXBEGB_ADDR (0x4000C018u) #define SC2_TXBEGB_RESET (0x20000000u) - /* FIXED field */ - #define SC2_TXBEGB_FIXED (0xFFFFE000u) - #define SC2_TXBEGB_FIXED_MASK (0xFFFFE000u) - #define SC2_TXBEGB_FIXED_BIT (13) - #define SC2_TXBEGB_FIXED_BITS (19) - /* SC_TXBEGB field */ - #define SC_TXBEGB (0x00001FFFu) - #define SC_TXBEGB_MASK (0x00001FFFu) - #define SC_TXBEGB_BIT (0) - #define SC_TXBEGB_BITS (13) +/* FIXED field */ +#define SC2_TXBEGB_FIXED (0xFFFFE000u) +#define SC2_TXBEGB_FIXED_MASK (0xFFFFE000u) +#define SC2_TXBEGB_FIXED_BIT (13) +#define SC2_TXBEGB_FIXED_BITS (19) +/* SC_TXBEGB field */ +#define SC_TXBEGB (0x00001FFFu) +#define SC_TXBEGB_MASK (0x00001FFFu) +#define SC_TXBEGB_BIT (0) +#define SC_TXBEGB_BITS (13) #define SC2_TXENDB *((volatile uint32_t *)0x4000C01Cu) #define SC2_TXENDB_REG *((volatile uint32_t *)0x4000C01Cu) #define SC2_TXENDB_ADDR (0x4000C01Cu) #define SC2_TXENDB_RESET (0x20000000u) - /* FIXED field */ - #define SC2_TXENDB_FIXED (0xFFFFE000u) - #define SC2_TXENDB_FIXED_MASK (0xFFFFE000u) - #define SC2_TXENDB_FIXED_BIT (13) - #define SC2_TXENDB_FIXED_BITS (19) - /* SC_TXENDB field */ - #define SC_TXENDB (0x00001FFFu) - #define SC_TXENDB_MASK (0x00001FFFu) - #define SC_TXENDB_BIT (0) - #define SC_TXENDB_BITS (13) +/* FIXED field */ +#define SC2_TXENDB_FIXED (0xFFFFE000u) +#define SC2_TXENDB_FIXED_MASK (0xFFFFE000u) +#define SC2_TXENDB_FIXED_BIT (13) +#define SC2_TXENDB_FIXED_BITS (19) +/* SC_TXENDB field */ +#define SC_TXENDB (0x00001FFFu) +#define SC_TXENDB_MASK (0x00001FFFu) +#define SC_TXENDB_BIT (0) +#define SC_TXENDB_BITS (13) #define SC2_RXCNTA *((volatile uint32_t *)0x4000C020u) #define SC2_RXCNTA_REG *((volatile uint32_t *)0x4000C020u) #define SC2_RXCNTA_ADDR (0x4000C020u) #define SC2_RXCNTA_RESET (0x00000000u) - /* SC_RXCNTA field */ - #define SC_RXCNTA (0x00001FFFu) - #define SC_RXCNTA_MASK (0x00001FFFu) - #define SC_RXCNTA_BIT (0) - #define SC_RXCNTA_BITS (13) +/* SC_RXCNTA field */ +#define SC_RXCNTA (0x00001FFFu) +#define SC_RXCNTA_MASK (0x00001FFFu) +#define SC_RXCNTA_BIT (0) +#define SC_RXCNTA_BITS (13) #define SC2_RXCNTB *((volatile uint32_t *)0x4000C024u) #define SC2_RXCNTB_REG *((volatile uint32_t *)0x4000C024u) #define SC2_RXCNTB_ADDR (0x4000C024u) #define SC2_RXCNTB_RESET (0x00000000u) - /* SC_RXCNTB field */ - #define SC_RXCNTB (0x00001FFFu) - #define SC_RXCNTB_MASK (0x00001FFFu) - #define SC_RXCNTB_BIT (0) - #define SC_RXCNTB_BITS (13) +/* SC_RXCNTB field */ +#define SC_RXCNTB (0x00001FFFu) +#define SC_RXCNTB_MASK (0x00001FFFu) +#define SC_RXCNTB_BIT (0) +#define SC_RXCNTB_BITS (13) #define SC2_TXCNT *((volatile uint32_t *)0x4000C028u) #define SC2_TXCNT_REG *((volatile uint32_t *)0x4000C028u) #define SC2_TXCNT_ADDR (0x4000C028u) #define SC2_TXCNT_RESET (0x00000000u) - /* SC_TXCNT field */ - #define SC_TXCNT (0x00001FFFu) - #define SC_TXCNT_MASK (0x00001FFFu) - #define SC_TXCNT_BIT (0) - #define SC_TXCNT_BITS (13) +/* SC_TXCNT field */ +#define SC_TXCNT (0x00001FFFu) +#define SC_TXCNT_MASK (0x00001FFFu) +#define SC_TXCNT_BIT (0) +#define SC_TXCNT_BITS (13) #define SC2_DMASTAT *((volatile uint32_t *)0x4000C02Cu) #define SC2_DMASTAT_REG *((volatile uint32_t *)0x4000C02Cu) #define SC2_DMASTAT_ADDR (0x4000C02Cu) #define SC2_DMASTAT_RESET (0x00000000u) - /* SC_RXSSEL field */ - #define SC_RXSSEL (0x00001C00u) - #define SC_RXSSEL_MASK (0x00001C00u) - #define SC_RXSSEL_BIT (10) - #define SC_RXSSEL_BITS (3) - /* SC_RXOVFB field */ - #define SC_RXOVFB (0x00000020u) - #define SC_RXOVFB_MASK (0x00000020u) - #define SC_RXOVFB_BIT (5) - #define SC_RXOVFB_BITS (1) - /* SC_RXOVFA field */ - #define SC_RXOVFA (0x00000010u) - #define SC_RXOVFA_MASK (0x00000010u) - #define SC_RXOVFA_BIT (4) - #define SC_RXOVFA_BITS (1) - /* SC_TXACTB field */ - #define SC_TXACTB (0x00000008u) - #define SC_TXACTB_MASK (0x00000008u) - #define SC_TXACTB_BIT (3) - #define SC_TXACTB_BITS (1) - /* SC_TXACTA field */ - #define SC_TXACTA (0x00000004u) - #define SC_TXACTA_MASK (0x00000004u) - #define SC_TXACTA_BIT (2) - #define SC_TXACTA_BITS (1) - /* SC_RXACTB field */ - #define SC_RXACTB (0x00000002u) - #define SC_RXACTB_MASK (0x00000002u) - #define SC_RXACTB_BIT (1) - #define SC_RXACTB_BITS (1) - /* SC_RXACTA field */ - #define SC_RXACTA (0x00000001u) - #define SC_RXACTA_MASK (0x00000001u) - #define SC_RXACTA_BIT (0) - #define SC_RXACTA_BITS (1) +/* SC_RXSSEL field */ +#define SC_RXSSEL (0x00001C00u) +#define SC_RXSSEL_MASK (0x00001C00u) +#define SC_RXSSEL_BIT (10) +#define SC_RXSSEL_BITS (3) +/* SC_RXOVFB field */ +#define SC_RXOVFB (0x00000020u) +#define SC_RXOVFB_MASK (0x00000020u) +#define SC_RXOVFB_BIT (5) +#define SC_RXOVFB_BITS (1) +/* SC_RXOVFA field */ +#define SC_RXOVFA (0x00000010u) +#define SC_RXOVFA_MASK (0x00000010u) +#define SC_RXOVFA_BIT (4) +#define SC_RXOVFA_BITS (1) +/* SC_TXACTB field */ +#define SC_TXACTB (0x00000008u) +#define SC_TXACTB_MASK (0x00000008u) +#define SC_TXACTB_BIT (3) +#define SC_TXACTB_BITS (1) +/* SC_TXACTA field */ +#define SC_TXACTA (0x00000004u) +#define SC_TXACTA_MASK (0x00000004u) +#define SC_TXACTA_BIT (2) +#define SC_TXACTA_BITS (1) +/* SC_RXACTB field */ +#define SC_RXACTB (0x00000002u) +#define SC_RXACTB_MASK (0x00000002u) +#define SC_RXACTB_BIT (1) +#define SC_RXACTB_BITS (1) +/* SC_RXACTA field */ +#define SC_RXACTA (0x00000001u) +#define SC_RXACTA_MASK (0x00000001u) +#define SC_RXACTA_BIT (0) +#define SC_RXACTA_BITS (1) #define SC2_DMACTRL *((volatile uint32_t *)0x4000C030u) #define SC2_DMACTRL_REG *((volatile uint32_t *)0x4000C030u) #define SC2_DMACTRL_ADDR (0x4000C030u) #define SC2_DMACTRL_RESET (0x00000000u) - /* SC_TXDMARST field */ - #define SC_TXDMARST (0x00000020u) - #define SC_TXDMARST_MASK (0x00000020u) - #define SC_TXDMARST_BIT (5) - #define SC_TXDMARST_BITS (1) - /* SC_RXDMARST field */ - #define SC_RXDMARST (0x00000010u) - #define SC_RXDMARST_MASK (0x00000010u) - #define SC_RXDMARST_BIT (4) - #define SC_RXDMARST_BITS (1) - /* SC_TXLODB field */ - #define SC_TXLODB (0x00000008u) - #define SC_TXLODB_MASK (0x00000008u) - #define SC_TXLODB_BIT (3) - #define SC_TXLODB_BITS (1) - /* SC_TXLODA field */ - #define SC_TXLODA (0x00000004u) - #define SC_TXLODA_MASK (0x00000004u) - #define SC_TXLODA_BIT (2) - #define SC_TXLODA_BITS (1) - /* SC_RXLODB field */ - #define SC_RXLODB (0x00000002u) - #define SC_RXLODB_MASK (0x00000002u) - #define SC_RXLODB_BIT (1) - #define SC_RXLODB_BITS (1) - /* SC_RXLODA field */ - #define SC_RXLODA (0x00000001u) - #define SC_RXLODA_MASK (0x00000001u) - #define SC_RXLODA_BIT (0) - #define SC_RXLODA_BITS (1) +/* SC_TXDMARST field */ +#define SC_TXDMARST (0x00000020u) +#define SC_TXDMARST_MASK (0x00000020u) +#define SC_TXDMARST_BIT (5) +#define SC_TXDMARST_BITS (1) +/* SC_RXDMARST field */ +#define SC_RXDMARST (0x00000010u) +#define SC_RXDMARST_MASK (0x00000010u) +#define SC_RXDMARST_BIT (4) +#define SC_RXDMARST_BITS (1) +/* SC_TXLODB field */ +#define SC_TXLODB (0x00000008u) +#define SC_TXLODB_MASK (0x00000008u) +#define SC_TXLODB_BIT (3) +#define SC_TXLODB_BITS (1) +/* SC_TXLODA field */ +#define SC_TXLODA (0x00000004u) +#define SC_TXLODA_MASK (0x00000004u) +#define SC_TXLODA_BIT (2) +#define SC_TXLODA_BITS (1) +/* SC_RXLODB field */ +#define SC_RXLODB (0x00000002u) +#define SC_RXLODB_MASK (0x00000002u) +#define SC_RXLODB_BIT (1) +#define SC_RXLODB_BITS (1) +/* SC_RXLODA field */ +#define SC_RXLODA (0x00000001u) +#define SC_RXLODA_MASK (0x00000001u) +#define SC_RXLODA_BIT (0) +#define SC_RXLODA_BITS (1) #define SC2_RXERRA *((volatile uint32_t *)0x4000C034u) #define SC2_RXERRA_REG *((volatile uint32_t *)0x4000C034u) #define SC2_RXERRA_ADDR (0x4000C034u) #define SC2_RXERRA_RESET (0x00000000u) - /* SC_RXERRA field */ - #define SC_RXERRA (0x00001FFFu) - #define SC_RXERRA_MASK (0x00001FFFu) - #define SC_RXERRA_BIT (0) - #define SC_RXERRA_BITS (13) +/* SC_RXERRA field */ +#define SC_RXERRA (0x00001FFFu) +#define SC_RXERRA_MASK (0x00001FFFu) +#define SC_RXERRA_BIT (0) +#define SC_RXERRA_BITS (13) #define SC2_RXERRB *((volatile uint32_t *)0x4000C038u) #define SC2_RXERRB_REG *((volatile uint32_t *)0x4000C038u) #define SC2_RXERRB_ADDR (0x4000C038u) #define SC2_RXERRB_RESET (0x00000000u) - /* SC_RXERRB field */ - #define SC_RXERRB (0x00001FFFu) - #define SC_RXERRB_MASK (0x00001FFFu) - #define SC_RXERRB_BIT (0) - #define SC_RXERRB_BITS (13) +/* SC_RXERRB field */ +#define SC_RXERRB (0x00001FFFu) +#define SC_RXERRB_MASK (0x00001FFFu) +#define SC_RXERRB_BIT (0) +#define SC_RXERRB_BITS (13) #define SC2_DATA *((volatile uint32_t *)0x4000C03Cu) #define SC2_DATA_REG *((volatile uint32_t *)0x4000C03Cu) #define SC2_DATA_ADDR (0x4000C03Cu) #define SC2_DATA_RESET (0x00000000u) - /* SC_DATA field */ - #define SC_DATA (0x000000FFu) - #define SC_DATA_MASK (0x000000FFu) - #define SC_DATA_BIT (0) - #define SC_DATA_BITS (8) +/* SC_DATA field */ +#define SC_DATA (0x000000FFu) +#define SC_DATA_MASK (0x000000FFu) +#define SC_DATA_BIT (0) +#define SC_DATA_BITS (8) #define SC2_SPISTAT *((volatile uint32_t *)0x4000C040u) #define SC2_SPISTAT_REG *((volatile uint32_t *)0x4000C040u) #define SC2_SPISTAT_ADDR (0x4000C040u) #define SC2_SPISTAT_RESET (0x00000000u) - /* SC_SPITXIDLE field */ - #define SC_SPITXIDLE (0x00000008u) - #define SC_SPITXIDLE_MASK (0x00000008u) - #define SC_SPITXIDLE_BIT (3) - #define SC_SPITXIDLE_BITS (1) - /* SC_SPITXFREE field */ - #define SC_SPITXFREE (0x00000004u) - #define SC_SPITXFREE_MASK (0x00000004u) - #define SC_SPITXFREE_BIT (2) - #define SC_SPITXFREE_BITS (1) - /* SC_SPIRXVAL field */ - #define SC_SPIRXVAL (0x00000002u) - #define SC_SPIRXVAL_MASK (0x00000002u) - #define SC_SPIRXVAL_BIT (1) - #define SC_SPIRXVAL_BITS (1) - /* SC_SPIRXOVF field */ - #define SC_SPIRXOVF (0x00000001u) - #define SC_SPIRXOVF_MASK (0x00000001u) - #define SC_SPIRXOVF_BIT (0) - #define SC_SPIRXOVF_BITS (1) +/* SC_SPITXIDLE field */ +#define SC_SPITXIDLE (0x00000008u) +#define SC_SPITXIDLE_MASK (0x00000008u) +#define SC_SPITXIDLE_BIT (3) +#define SC_SPITXIDLE_BITS (1) +/* SC_SPITXFREE field */ +#define SC_SPITXFREE (0x00000004u) +#define SC_SPITXFREE_MASK (0x00000004u) +#define SC_SPITXFREE_BIT (2) +#define SC_SPITXFREE_BITS (1) +/* SC_SPIRXVAL field */ +#define SC_SPIRXVAL (0x00000002u) +#define SC_SPIRXVAL_MASK (0x00000002u) +#define SC_SPIRXVAL_BIT (1) +#define SC_SPIRXVAL_BITS (1) +/* SC_SPIRXOVF field */ +#define SC_SPIRXOVF (0x00000001u) +#define SC_SPIRXOVF_MASK (0x00000001u) +#define SC_SPIRXOVF_BIT (0) +#define SC_SPIRXOVF_BITS (1) #define SC2_TWISTAT *((volatile uint32_t *)0x4000C044u) #define SC2_TWISTAT_REG *((volatile uint32_t *)0x4000C044u) #define SC2_TWISTAT_ADDR (0x4000C044u) #define SC2_TWISTAT_RESET (0x00000000u) - /* SC_TWICMDFIN field */ - #define SC_TWICMDFIN (0x00000008u) - #define SC_TWICMDFIN_MASK (0x00000008u) - #define SC_TWICMDFIN_BIT (3) - #define SC_TWICMDFIN_BITS (1) - /* SC_TWIRXFIN field */ - #define SC_TWIRXFIN (0x00000004u) - #define SC_TWIRXFIN_MASK (0x00000004u) - #define SC_TWIRXFIN_BIT (2) - #define SC_TWIRXFIN_BITS (1) - /* SC_TWITXFIN field */ - #define SC_TWITXFIN (0x00000002u) - #define SC_TWITXFIN_MASK (0x00000002u) - #define SC_TWITXFIN_BIT (1) - #define SC_TWITXFIN_BITS (1) - /* SC_TWIRXNAK field */ - #define SC_TWIRXNAK (0x00000001u) - #define SC_TWIRXNAK_MASK (0x00000001u) - #define SC_TWIRXNAK_BIT (0) - #define SC_TWIRXNAK_BITS (1) +/* SC_TWICMDFIN field */ +#define SC_TWICMDFIN (0x00000008u) +#define SC_TWICMDFIN_MASK (0x00000008u) +#define SC_TWICMDFIN_BIT (3) +#define SC_TWICMDFIN_BITS (1) +/* SC_TWIRXFIN field */ +#define SC_TWIRXFIN (0x00000004u) +#define SC_TWIRXFIN_MASK (0x00000004u) +#define SC_TWIRXFIN_BIT (2) +#define SC_TWIRXFIN_BITS (1) +/* SC_TWITXFIN field */ +#define SC_TWITXFIN (0x00000002u) +#define SC_TWITXFIN_MASK (0x00000002u) +#define SC_TWITXFIN_BIT (1) +#define SC_TWITXFIN_BITS (1) +/* SC_TWIRXNAK field */ +#define SC_TWIRXNAK (0x00000001u) +#define SC_TWIRXNAK_MASK (0x00000001u) +#define SC_TWIRXNAK_BIT (0) +#define SC_TWIRXNAK_BITS (1) #define SC2_TWICTRL1 *((volatile uint32_t *)0x4000C04Cu) #define SC2_TWICTRL1_REG *((volatile uint32_t *)0x4000C04Cu) #define SC2_TWICTRL1_ADDR (0x4000C04Cu) #define SC2_TWICTRL1_RESET (0x00000000u) - /* SC_TWISTOP field */ - #define SC_TWISTOP (0x00000008u) - #define SC_TWISTOP_MASK (0x00000008u) - #define SC_TWISTOP_BIT (3) - #define SC_TWISTOP_BITS (1) - /* SC_TWISTART field */ - #define SC_TWISTART (0x00000004u) - #define SC_TWISTART_MASK (0x00000004u) - #define SC_TWISTART_BIT (2) - #define SC_TWISTART_BITS (1) - /* SC_TWISEND field */ - #define SC_TWISEND (0x00000002u) - #define SC_TWISEND_MASK (0x00000002u) - #define SC_TWISEND_BIT (1) - #define SC_TWISEND_BITS (1) - /* SC_TWIRECV field */ - #define SC_TWIRECV (0x00000001u) - #define SC_TWIRECV_MASK (0x00000001u) - #define SC_TWIRECV_BIT (0) - #define SC_TWIRECV_BITS (1) +/* SC_TWISTOP field */ +#define SC_TWISTOP (0x00000008u) +#define SC_TWISTOP_MASK (0x00000008u) +#define SC_TWISTOP_BIT (3) +#define SC_TWISTOP_BITS (1) +/* SC_TWISTART field */ +#define SC_TWISTART (0x00000004u) +#define SC_TWISTART_MASK (0x00000004u) +#define SC_TWISTART_BIT (2) +#define SC_TWISTART_BITS (1) +/* SC_TWISEND field */ +#define SC_TWISEND (0x00000002u) +#define SC_TWISEND_MASK (0x00000002u) +#define SC_TWISEND_BIT (1) +#define SC_TWISEND_BITS (1) +/* SC_TWIRECV field */ +#define SC_TWIRECV (0x00000001u) +#define SC_TWIRECV_MASK (0x00000001u) +#define SC_TWIRECV_BIT (0) +#define SC_TWIRECV_BITS (1) #define SC2_TWICTRL2 *((volatile uint32_t *)0x4000C050u) #define SC2_TWICTRL2_REG *((volatile uint32_t *)0x4000C050u) #define SC2_TWICTRL2_ADDR (0x4000C050u) #define SC2_TWICTRL2_RESET (0x00000000u) - /* SC_TWIACK field */ - #define SC_TWIACK (0x00000001u) - #define SC_TWIACK_MASK (0x00000001u) - #define SC_TWIACK_BIT (0) - #define SC_TWIACK_BITS (1) +/* SC_TWIACK field */ +#define SC_TWIACK (0x00000001u) +#define SC_TWIACK_MASK (0x00000001u) +#define SC_TWIACK_BIT (0) +#define SC_TWIACK_BITS (1) #define SC2_MODE *((volatile uint32_t *)0x4000C054u) #define SC2_MODE_REG *((volatile uint32_t *)0x4000C054u) #define SC2_MODE_ADDR (0x4000C054u) #define SC2_MODE_RESET (0x00000000u) - /* SC_MODE field */ - #define SC_MODE (0x00000003u) - #define SC_MODE_MASK (0x00000003u) - #define SC_MODE_BIT (0) - #define SC_MODE_BITS (2) - /* SC_MODE Bit Field Values */ - #define SC2_MODE_DISABLED (0) - #define SC2_MODE_SPI (2) - #define SC2_MODE_I2C (3) +/* SC_MODE field */ +#define SC_MODE (0x00000003u) +#define SC_MODE_MASK (0x00000003u) +#define SC_MODE_BIT (0) +#define SC_MODE_BITS (2) +/* SC_MODE Bit Field Values */ +#define SC2_MODE_DISABLED (0) +#define SC2_MODE_SPI (2) +#define SC2_MODE_I2C (3) #define SC2_SPICFG *((volatile uint32_t *)0x4000C058u) #define SC2_SPICFG_REG *((volatile uint32_t *)0x4000C058u) #define SC2_SPICFG_ADDR (0x4000C058u) #define SC2_SPICFG_RESET (0x00000000u) - /* SC_SPIRXDRV field */ - #define SC_SPIRXDRV (0x00000020u) - #define SC_SPIRXDRV_MASK (0x00000020u) - #define SC_SPIRXDRV_BIT (5) - #define SC_SPIRXDRV_BITS (1) - /* SC_SPIMST field */ - #define SC_SPIMST (0x00000010u) - #define SC_SPIMST_MASK (0x00000010u) - #define SC_SPIMST_BIT (4) - #define SC_SPIMST_BITS (1) - /* SC_SPIRPT field */ - #define SC_SPIRPT (0x00000008u) - #define SC_SPIRPT_MASK (0x00000008u) - #define SC_SPIRPT_BIT (3) - #define SC_SPIRPT_BITS (1) - /* SC_SPIORD field */ - #define SC_SPIORD (0x00000004u) - #define SC_SPIORD_MASK (0x00000004u) - #define SC_SPIORD_BIT (2) - #define SC_SPIORD_BITS (1) - /* SC_SPIPHA field */ - #define SC_SPIPHA (0x00000002u) - #define SC_SPIPHA_MASK (0x00000002u) - #define SC_SPIPHA_BIT (1) - #define SC_SPIPHA_BITS (1) - /* SC_SPIPOL field */ - #define SC_SPIPOL (0x00000001u) - #define SC_SPIPOL_MASK (0x00000001u) - #define SC_SPIPOL_BIT (0) - #define SC_SPIPOL_BITS (1) +/* SC_SPIRXDRV field */ +#define SC_SPIRXDRV (0x00000020u) +#define SC_SPIRXDRV_MASK (0x00000020u) +#define SC_SPIRXDRV_BIT (5) +#define SC_SPIRXDRV_BITS (1) +/* SC_SPIMST field */ +#define SC_SPIMST (0x00000010u) +#define SC_SPIMST_MASK (0x00000010u) +#define SC_SPIMST_BIT (4) +#define SC_SPIMST_BITS (1) +/* SC_SPIRPT field */ +#define SC_SPIRPT (0x00000008u) +#define SC_SPIRPT_MASK (0x00000008u) +#define SC_SPIRPT_BIT (3) +#define SC_SPIRPT_BITS (1) +/* SC_SPIORD field */ +#define SC_SPIORD (0x00000004u) +#define SC_SPIORD_MASK (0x00000004u) +#define SC_SPIORD_BIT (2) +#define SC_SPIORD_BITS (1) +/* SC_SPIPHA field */ +#define SC_SPIPHA (0x00000002u) +#define SC_SPIPHA_MASK (0x00000002u) +#define SC_SPIPHA_BIT (1) +#define SC_SPIPHA_BITS (1) +/* SC_SPIPOL field */ +#define SC_SPIPOL (0x00000001u) +#define SC_SPIPOL_MASK (0x00000001u) +#define SC_SPIPOL_BIT (0) +#define SC_SPIPOL_BITS (1) #define SC2_RATELIN *((volatile uint32_t *)0x4000C060u) #define SC2_RATELIN_REG *((volatile uint32_t *)0x4000C060u) #define SC2_RATELIN_ADDR (0x4000C060u) #define SC2_RATELIN_RESET (0x00000000u) - /* SC_RATELIN field */ - #define SC_RATELIN (0x0000000Fu) - #define SC_RATELIN_MASK (0x0000000Fu) - #define SC_RATELIN_BIT (0) - #define SC_RATELIN_BITS (4) +/* SC_RATELIN field */ +#define SC_RATELIN (0x0000000Fu) +#define SC_RATELIN_MASK (0x0000000Fu) +#define SC_RATELIN_BIT (0) +#define SC_RATELIN_BITS (4) #define SC2_RATEEXP *((volatile uint32_t *)0x4000C064u) #define SC2_RATEEXP_REG *((volatile uint32_t *)0x4000C064u) #define SC2_RATEEXP_ADDR (0x4000C064u) #define SC2_RATEEXP_RESET (0x00000000u) - /* SC_RATEEXP field */ - #define SC_RATEEXP (0x0000000Fu) - #define SC_RATEEXP_MASK (0x0000000Fu) - #define SC_RATEEXP_BIT (0) - #define SC_RATEEXP_BITS (4) +/* SC_RATEEXP field */ +#define SC_RATEEXP (0x0000000Fu) +#define SC_RATEEXP_MASK (0x0000000Fu) +#define SC_RATEEXP_BIT (0) +#define SC_RATEEXP_BITS (4) #define SC2_RXCNTSAVED *((volatile uint32_t *)0x4000C070u) #define SC2_RXCNTSAVED_REG *((volatile uint32_t *)0x4000C070u) #define SC2_RXCNTSAVED_ADDR (0x4000C070u) #define SC2_RXCNTSAVED_RESET (0x00000000u) - /* SC_RXCNTSAVED field */ - #define SC_RXCNTSAVED (0x00001FFFu) - #define SC_RXCNTSAVED_MASK (0x00001FFFu) - #define SC_RXCNTSAVED_BIT (0) - #define SC_RXCNTSAVED_BITS (13) +/* SC_RXCNTSAVED field */ +#define SC_RXCNTSAVED (0x00001FFFu) +#define SC_RXCNTSAVED_MASK (0x00001FFFu) +#define SC_RXCNTSAVED_BIT (0) +#define SC_RXCNTSAVED_BITS (13) #define SC1_RXBEGA *((volatile uint32_t *)0x4000C800u) #define SC1_RXBEGA_REG *((volatile uint32_t *)0x4000C800u) #define SC1_RXBEGA_ADDR (0x4000C800u) #define SC1_RXBEGA_RESET (0x20000000u) - /* FIXED field */ - #define SC1_RXBEGA_FIXED (0xFFFFE000u) - #define SC1_RXBEGA_FIXED_MASK (0xFFFFE000u) - #define SC1_RXBEGA_FIXED_BIT (13) - #define SC1_RXBEGA_FIXED_BITS (19) - /* SC_RXBEGA field */ - #define SC_RXBEGA (0x00001FFFu) - #define SC_RXBEGA_MASK (0x00001FFFu) - #define SC_RXBEGA_BIT (0) - #define SC_RXBEGA_BITS (13) +/* FIXED field */ +#define SC1_RXBEGA_FIXED (0xFFFFE000u) +#define SC1_RXBEGA_FIXED_MASK (0xFFFFE000u) +#define SC1_RXBEGA_FIXED_BIT (13) +#define SC1_RXBEGA_FIXED_BITS (19) +/* SC_RXBEGA field */ +#define SC_RXBEGA (0x00001FFFu) +#define SC_RXBEGA_MASK (0x00001FFFu) +#define SC_RXBEGA_BIT (0) +#define SC_RXBEGA_BITS (13) #define SC1_RXENDA *((volatile uint32_t *)0x4000C804u) #define SC1_RXENDA_REG *((volatile uint32_t *)0x4000C804u) #define SC1_RXENDA_ADDR (0x4000C804u) #define SC1_RXENDA_RESET (0x20000000u) - /* FIXED field */ - #define SC1_RXENDA_FIXED (0xFFFFE000u) - #define SC1_RXENDA_FIXED_MASK (0xFFFFE000u) - #define SC1_RXENDA_FIXED_BIT (13) - #define SC1_RXENDA_FIXED_BITS (19) - /* SC_RXENDA field */ - #define SC_RXENDA (0x00001FFFu) - #define SC_RXENDA_MASK (0x00001FFFu) - #define SC_RXENDA_BIT (0) - #define SC_RXENDA_BITS (13) +/* FIXED field */ +#define SC1_RXENDA_FIXED (0xFFFFE000u) +#define SC1_RXENDA_FIXED_MASK (0xFFFFE000u) +#define SC1_RXENDA_FIXED_BIT (13) +#define SC1_RXENDA_FIXED_BITS (19) +/* SC_RXENDA field */ +#define SC_RXENDA (0x00001FFFu) +#define SC_RXENDA_MASK (0x00001FFFu) +#define SC_RXENDA_BIT (0) +#define SC_RXENDA_BITS (13) #define SC1_RXBEGB *((volatile uint32_t *)0x4000C808u) #define SC1_RXBEGB_REG *((volatile uint32_t *)0x4000C808u) #define SC1_RXBEGB_ADDR (0x4000C808u) #define SC1_RXBEGB_RESET (0x20000000u) - /* FIXED field */ - #define SC1_RXBEGB_FIXED (0xFFFFE000u) - #define SC1_RXBEGB_FIXED_MASK (0xFFFFE000u) - #define SC1_RXBEGB_FIXED_BIT (13) - #define SC1_RXBEGB_FIXED_BITS (19) - /* SC_RXBEGB field */ - #define SC_RXBEGB (0x00001FFFu) - #define SC_RXBEGB_MASK (0x00001FFFu) - #define SC_RXBEGB_BIT (0) - #define SC_RXBEGB_BITS (13) +/* FIXED field */ +#define SC1_RXBEGB_FIXED (0xFFFFE000u) +#define SC1_RXBEGB_FIXED_MASK (0xFFFFE000u) +#define SC1_RXBEGB_FIXED_BIT (13) +#define SC1_RXBEGB_FIXED_BITS (19) +/* SC_RXBEGB field */ +#define SC_RXBEGB (0x00001FFFu) +#define SC_RXBEGB_MASK (0x00001FFFu) +#define SC_RXBEGB_BIT (0) +#define SC_RXBEGB_BITS (13) #define SC1_RXENDB *((volatile uint32_t *)0x4000C80Cu) #define SC1_RXENDB_REG *((volatile uint32_t *)0x4000C80Cu) #define SC1_RXENDB_ADDR (0x4000C80Cu) #define SC1_RXENDB_RESET (0x20000000u) - /* FIXED field */ - #define SC1_RXENDB_FIXED (0xFFFFE000u) - #define SC1_RXENDB_FIXED_MASK (0xFFFFE000u) - #define SC1_RXENDB_FIXED_BIT (13) - #define SC1_RXENDB_FIXED_BITS (19) - /* SC_RXENDB field */ - #define SC_RXENDB (0x00001FFFu) - #define SC_RXENDB_MASK (0x00001FFFu) - #define SC_RXENDB_BIT (0) - #define SC_RXENDB_BITS (13) +/* FIXED field */ +#define SC1_RXENDB_FIXED (0xFFFFE000u) +#define SC1_RXENDB_FIXED_MASK (0xFFFFE000u) +#define SC1_RXENDB_FIXED_BIT (13) +#define SC1_RXENDB_FIXED_BITS (19) +/* SC_RXENDB field */ +#define SC_RXENDB (0x00001FFFu) +#define SC_RXENDB_MASK (0x00001FFFu) +#define SC_RXENDB_BIT (0) +#define SC_RXENDB_BITS (13) #define SC1_TXBEGA *((volatile uint32_t *)0x4000C810u) #define SC1_TXBEGA_REG *((volatile uint32_t *)0x4000C810u) #define SC1_TXBEGA_ADDR (0x4000C810u) #define SC1_TXBEGA_RESET (0x20000000u) - /* FIXED field */ - #define SC1_TXBEGA_FIXED (0xFFFFE000u) - #define SC1_TXBEGA_FIXED_MASK (0xFFFFE000u) - #define SC1_TXBEGA_FIXED_BIT (13) - #define SC1_TXBEGA_FIXED_BITS (19) - /* SC_TXBEGA field */ - #define SC_TXBEGA (0x00001FFFu) - #define SC_TXBEGA_MASK (0x00001FFFu) - #define SC_TXBEGA_BIT (0) - #define SC_TXBEGA_BITS (13) +/* FIXED field */ +#define SC1_TXBEGA_FIXED (0xFFFFE000u) +#define SC1_TXBEGA_FIXED_MASK (0xFFFFE000u) +#define SC1_TXBEGA_FIXED_BIT (13) +#define SC1_TXBEGA_FIXED_BITS (19) +/* SC_TXBEGA field */ +#define SC_TXBEGA (0x00001FFFu) +#define SC_TXBEGA_MASK (0x00001FFFu) +#define SC_TXBEGA_BIT (0) +#define SC_TXBEGA_BITS (13) #define SC1_TXENDA *((volatile uint32_t *)0x4000C814u) #define SC1_TXENDA_REG *((volatile uint32_t *)0x4000C814u) #define SC1_TXENDA_ADDR (0x4000C814u) #define SC1_TXENDA_RESET (0x20000000u) - /* FIXED field */ - #define SC1_TXENDA_FIXED (0xFFFFE000u) - #define SC1_TXENDA_FIXED_MASK (0xFFFFE000u) - #define SC1_TXENDA_FIXED_BIT (13) - #define SC1_TXENDA_FIXED_BITS (19) - /* SC_TXENDA field */ - #define SC_TXENDA (0x00001FFFu) - #define SC_TXENDA_MASK (0x00001FFFu) - #define SC_TXENDA_BIT (0) - #define SC_TXENDA_BITS (13) +/* FIXED field */ +#define SC1_TXENDA_FIXED (0xFFFFE000u) +#define SC1_TXENDA_FIXED_MASK (0xFFFFE000u) +#define SC1_TXENDA_FIXED_BIT (13) +#define SC1_TXENDA_FIXED_BITS (19) +/* SC_TXENDA field */ +#define SC_TXENDA (0x00001FFFu) +#define SC_TXENDA_MASK (0x00001FFFu) +#define SC_TXENDA_BIT (0) +#define SC_TXENDA_BITS (13) #define SC1_TXBEGB *((volatile uint32_t *)0x4000C818u) #define SC1_TXBEGB_REG *((volatile uint32_t *)0x4000C818u) #define SC1_TXBEGB_ADDR (0x4000C818u) #define SC1_TXBEGB_RESET (0x20000000u) - /* FIXED field */ - #define SC1_TXBEGB_FIXED (0xFFFFE000u) - #define SC1_TXBEGB_FIXED_MASK (0xFFFFE000u) - #define SC1_TXBEGB_FIXED_BIT (13) - #define SC1_TXBEGB_FIXED_BITS (19) - /* SC_TXBEGB field */ - #define SC_TXBEGB (0x00001FFFu) - #define SC_TXBEGB_MASK (0x00001FFFu) - #define SC_TXBEGB_BIT (0) - #define SC_TXBEGB_BITS (13) +/* FIXED field */ +#define SC1_TXBEGB_FIXED (0xFFFFE000u) +#define SC1_TXBEGB_FIXED_MASK (0xFFFFE000u) +#define SC1_TXBEGB_FIXED_BIT (13) +#define SC1_TXBEGB_FIXED_BITS (19) +/* SC_TXBEGB field */ +#define SC_TXBEGB (0x00001FFFu) +#define SC_TXBEGB_MASK (0x00001FFFu) +#define SC_TXBEGB_BIT (0) +#define SC_TXBEGB_BITS (13) #define SC1_TXENDB *((volatile uint32_t *)0x4000C81Cu) #define SC1_TXENDB_REG *((volatile uint32_t *)0x4000C81Cu) #define SC1_TXENDB_ADDR (0x4000C81Cu) #define SC1_TXENDB_RESET (0x20000000u) - /* FIXED field */ - #define SC1_TXENDB_FIXED (0xFFFFE000u) - #define SC1_TXENDB_FIXED_MASK (0xFFFFE000u) - #define SC1_TXENDB_FIXED_BIT (13) - #define SC1_TXENDB_FIXED_BITS (19) - /* SC_TXENDB field */ - #define SC_TXENDB (0x00001FFFu) - #define SC_TXENDB_MASK (0x00001FFFu) - #define SC_TXENDB_BIT (0) - #define SC_TXENDB_BITS (13) +/* FIXED field */ +#define SC1_TXENDB_FIXED (0xFFFFE000u) +#define SC1_TXENDB_FIXED_MASK (0xFFFFE000u) +#define SC1_TXENDB_FIXED_BIT (13) +#define SC1_TXENDB_FIXED_BITS (19) +/* SC_TXENDB field */ +#define SC_TXENDB (0x00001FFFu) +#define SC_TXENDB_MASK (0x00001FFFu) +#define SC_TXENDB_BIT (0) +#define SC_TXENDB_BITS (13) #define SC1_RXCNTA *((volatile uint32_t *)0x4000C820u) #define SC1_RXCNTA_REG *((volatile uint32_t *)0x4000C820u) #define SC1_RXCNTA_ADDR (0x4000C820u) #define SC1_RXCNTA_RESET (0x00000000u) - /* SC_RXCNTA field */ - #define SC_RXCNTA (0x00001FFFu) - #define SC_RXCNTA_MASK (0x00001FFFu) - #define SC_RXCNTA_BIT (0) - #define SC_RXCNTA_BITS (13) +/* SC_RXCNTA field */ +#define SC_RXCNTA (0x00001FFFu) +#define SC_RXCNTA_MASK (0x00001FFFu) +#define SC_RXCNTA_BIT (0) +#define SC_RXCNTA_BITS (13) #define SC1_RXCNTB *((volatile uint32_t *)0x4000C824u) #define SC1_RXCNTB_REG *((volatile uint32_t *)0x4000C824u) #define SC1_RXCNTB_ADDR (0x4000C824u) #define SC1_RXCNTB_RESET (0x00000000u) - /* SC_RXCNTB field */ - #define SC_RXCNTB (0x00001FFFu) - #define SC_RXCNTB_MASK (0x00001FFFu) - #define SC_RXCNTB_BIT (0) - #define SC_RXCNTB_BITS (13) +/* SC_RXCNTB field */ +#define SC_RXCNTB (0x00001FFFu) +#define SC_RXCNTB_MASK (0x00001FFFu) +#define SC_RXCNTB_BIT (0) +#define SC_RXCNTB_BITS (13) #define SC1_TXCNT *((volatile uint32_t *)0x4000C828u) #define SC1_TXCNT_REG *((volatile uint32_t *)0x4000C828u) #define SC1_TXCNT_ADDR (0x4000C828u) #define SC1_TXCNT_RESET (0x00000000u) - /* SC_TXCNT field */ - #define SC_TXCNT (0x00001FFFu) - #define SC_TXCNT_MASK (0x00001FFFu) - #define SC_TXCNT_BIT (0) - #define SC_TXCNT_BITS (13) +/* SC_TXCNT field */ +#define SC_TXCNT (0x00001FFFu) +#define SC_TXCNT_MASK (0x00001FFFu) +#define SC_TXCNT_BIT (0) +#define SC_TXCNT_BITS (13) #define SC1_DMASTAT *((volatile uint32_t *)0x4000C82Cu) #define SC1_DMASTAT_REG *((volatile uint32_t *)0x4000C82Cu) #define SC1_DMASTAT_ADDR (0x4000C82Cu) #define SC1_DMASTAT_RESET (0x00000000u) - /* SC_RXSSEL field */ - #define SC_RXSSEL (0x00001C00u) - #define SC_RXSSEL_MASK (0x00001C00u) - #define SC_RXSSEL_BIT (10) - #define SC_RXSSEL_BITS (3) - /* SC_RXFRMB field */ - #define SC_RXFRMB (0x00000200u) - #define SC_RXFRMB_MASK (0x00000200u) - #define SC_RXFRMB_BIT (9) - #define SC_RXFRMB_BITS (1) - /* SC_RXFRMA field */ - #define SC_RXFRMA (0x00000100u) - #define SC_RXFRMA_MASK (0x00000100u) - #define SC_RXFRMA_BIT (8) - #define SC_RXFRMA_BITS (1) - /* SC_RXPARB field */ - #define SC_RXPARB (0x00000080u) - #define SC_RXPARB_MASK (0x00000080u) - #define SC_RXPARB_BIT (7) - #define SC_RXPARB_BITS (1) - /* SC_RXPARA field */ - #define SC_RXPARA (0x00000040u) - #define SC_RXPARA_MASK (0x00000040u) - #define SC_RXPARA_BIT (6) - #define SC_RXPARA_BITS (1) - /* SC_RXOVFB field */ - #define SC_RXOVFB (0x00000020u) - #define SC_RXOVFB_MASK (0x00000020u) - #define SC_RXOVFB_BIT (5) - #define SC_RXOVFB_BITS (1) - /* SC_RXOVFA field */ - #define SC_RXOVFA (0x00000010u) - #define SC_RXOVFA_MASK (0x00000010u) - #define SC_RXOVFA_BIT (4) - #define SC_RXOVFA_BITS (1) - /* SC_TXACTB field */ - #define SC_TXACTB (0x00000008u) - #define SC_TXACTB_MASK (0x00000008u) - #define SC_TXACTB_BIT (3) - #define SC_TXACTB_BITS (1) - /* SC_TXACTA field */ - #define SC_TXACTA (0x00000004u) - #define SC_TXACTA_MASK (0x00000004u) - #define SC_TXACTA_BIT (2) - #define SC_TXACTA_BITS (1) - /* SC_RXACTB field */ - #define SC_RXACTB (0x00000002u) - #define SC_RXACTB_MASK (0x00000002u) - #define SC_RXACTB_BIT (1) - #define SC_RXACTB_BITS (1) - /* SC_RXACTA field */ - #define SC_RXACTA (0x00000001u) - #define SC_RXACTA_MASK (0x00000001u) - #define SC_RXACTA_BIT (0) - #define SC_RXACTA_BITS (1) +/* SC_RXSSEL field */ +#define SC_RXSSEL (0x00001C00u) +#define SC_RXSSEL_MASK (0x00001C00u) +#define SC_RXSSEL_BIT (10) +#define SC_RXSSEL_BITS (3) +/* SC_RXFRMB field */ +#define SC_RXFRMB (0x00000200u) +#define SC_RXFRMB_MASK (0x00000200u) +#define SC_RXFRMB_BIT (9) +#define SC_RXFRMB_BITS (1) +/* SC_RXFRMA field */ +#define SC_RXFRMA (0x00000100u) +#define SC_RXFRMA_MASK (0x00000100u) +#define SC_RXFRMA_BIT (8) +#define SC_RXFRMA_BITS (1) +/* SC_RXPARB field */ +#define SC_RXPARB (0x00000080u) +#define SC_RXPARB_MASK (0x00000080u) +#define SC_RXPARB_BIT (7) +#define SC_RXPARB_BITS (1) +/* SC_RXPARA field */ +#define SC_RXPARA (0x00000040u) +#define SC_RXPARA_MASK (0x00000040u) +#define SC_RXPARA_BIT (6) +#define SC_RXPARA_BITS (1) +/* SC_RXOVFB field */ +#define SC_RXOVFB (0x00000020u) +#define SC_RXOVFB_MASK (0x00000020u) +#define SC_RXOVFB_BIT (5) +#define SC_RXOVFB_BITS (1) +/* SC_RXOVFA field */ +#define SC_RXOVFA (0x00000010u) +#define SC_RXOVFA_MASK (0x00000010u) +#define SC_RXOVFA_BIT (4) +#define SC_RXOVFA_BITS (1) +/* SC_TXACTB field */ +#define SC_TXACTB (0x00000008u) +#define SC_TXACTB_MASK (0x00000008u) +#define SC_TXACTB_BIT (3) +#define SC_TXACTB_BITS (1) +/* SC_TXACTA field */ +#define SC_TXACTA (0x00000004u) +#define SC_TXACTA_MASK (0x00000004u) +#define SC_TXACTA_BIT (2) +#define SC_TXACTA_BITS (1) +/* SC_RXACTB field */ +#define SC_RXACTB (0x00000002u) +#define SC_RXACTB_MASK (0x00000002u) +#define SC_RXACTB_BIT (1) +#define SC_RXACTB_BITS (1) +/* SC_RXACTA field */ +#define SC_RXACTA (0x00000001u) +#define SC_RXACTA_MASK (0x00000001u) +#define SC_RXACTA_BIT (0) +#define SC_RXACTA_BITS (1) #define SC1_DMACTRL *((volatile uint32_t *)0x4000C830u) #define SC1_DMACTRL_REG *((volatile uint32_t *)0x4000C830u) #define SC1_DMACTRL_ADDR (0x4000C830u) #define SC1_DMACTRL_RESET (0x00000000u) - /* SC_TXDMARST field */ - #define SC_TXDMARST (0x00000020u) - #define SC_TXDMARST_MASK (0x00000020u) - #define SC_TXDMARST_BIT (5) - #define SC_TXDMARST_BITS (1) - /* SC_RXDMARST field */ - #define SC_RXDMARST (0x00000010u) - #define SC_RXDMARST_MASK (0x00000010u) - #define SC_RXDMARST_BIT (4) - #define SC_RXDMARST_BITS (1) - /* SC_TXLODB field */ - #define SC_TXLODB (0x00000008u) - #define SC_TXLODB_MASK (0x00000008u) - #define SC_TXLODB_BIT (3) - #define SC_TXLODB_BITS (1) - /* SC_TXLODA field */ - #define SC_TXLODA (0x00000004u) - #define SC_TXLODA_MASK (0x00000004u) - #define SC_TXLODA_BIT (2) - #define SC_TXLODA_BITS (1) - /* SC_RXLODB field */ - #define SC_RXLODB (0x00000002u) - #define SC_RXLODB_MASK (0x00000002u) - #define SC_RXLODB_BIT (1) - #define SC_RXLODB_BITS (1) - /* SC_RXLODA field */ - #define SC_RXLODA (0x00000001u) - #define SC_RXLODA_MASK (0x00000001u) - #define SC_RXLODA_BIT (0) - #define SC_RXLODA_BITS (1) +/* SC_TXDMARST field */ +#define SC_TXDMARST (0x00000020u) +#define SC_TXDMARST_MASK (0x00000020u) +#define SC_TXDMARST_BIT (5) +#define SC_TXDMARST_BITS (1) +/* SC_RXDMARST field */ +#define SC_RXDMARST (0x00000010u) +#define SC_RXDMARST_MASK (0x00000010u) +#define SC_RXDMARST_BIT (4) +#define SC_RXDMARST_BITS (1) +/* SC_TXLODB field */ +#define SC_TXLODB (0x00000008u) +#define SC_TXLODB_MASK (0x00000008u) +#define SC_TXLODB_BIT (3) +#define SC_TXLODB_BITS (1) +/* SC_TXLODA field */ +#define SC_TXLODA (0x00000004u) +#define SC_TXLODA_MASK (0x00000004u) +#define SC_TXLODA_BIT (2) +#define SC_TXLODA_BITS (1) +/* SC_RXLODB field */ +#define SC_RXLODB (0x00000002u) +#define SC_RXLODB_MASK (0x00000002u) +#define SC_RXLODB_BIT (1) +#define SC_RXLODB_BITS (1) +/* SC_RXLODA field */ +#define SC_RXLODA (0x00000001u) +#define SC_RXLODA_MASK (0x00000001u) +#define SC_RXLODA_BIT (0) +#define SC_RXLODA_BITS (1) #define SC1_RXERRA *((volatile uint32_t *)0x4000C834u) #define SC1_RXERRA_REG *((volatile uint32_t *)0x4000C834u) #define SC1_RXERRA_ADDR (0x4000C834u) #define SC1_RXERRA_RESET (0x00000000u) - /* SC_RXERRA field */ - #define SC_RXERRA (0x00001FFFu) - #define SC_RXERRA_MASK (0x00001FFFu) - #define SC_RXERRA_BIT (0) - #define SC_RXERRA_BITS (13) +/* SC_RXERRA field */ +#define SC_RXERRA (0x00001FFFu) +#define SC_RXERRA_MASK (0x00001FFFu) +#define SC_RXERRA_BIT (0) +#define SC_RXERRA_BITS (13) #define SC1_RXERRB *((volatile uint32_t *)0x4000C838u) #define SC1_RXERRB_REG *((volatile uint32_t *)0x4000C838u) #define SC1_RXERRB_ADDR (0x4000C838u) #define SC1_RXERRB_RESET (0x00000000u) - /* SC_RXERRB field */ - #define SC_RXERRB (0x00001FFFu) - #define SC_RXERRB_MASK (0x00001FFFu) - #define SC_RXERRB_BIT (0) - #define SC_RXERRB_BITS (13) +/* SC_RXERRB field */ +#define SC_RXERRB (0x00001FFFu) +#define SC_RXERRB_MASK (0x00001FFFu) +#define SC_RXERRB_BIT (0) +#define SC_RXERRB_BITS (13) #define SC1_DATA *((volatile uint32_t *)0x4000C83Cu) #define SC1_DATA_REG *((volatile uint32_t *)0x4000C83Cu) #define SC1_DATA_ADDR (0x4000C83Cu) #define SC1_DATA_RESET (0x00000000u) - /* SC_DATA field */ - #define SC_DATA (0x000000FFu) - #define SC_DATA_MASK (0x000000FFu) - #define SC_DATA_BIT (0) - #define SC_DATA_BITS (8) +/* SC_DATA field */ +#define SC_DATA (0x000000FFu) +#define SC_DATA_MASK (0x000000FFu) +#define SC_DATA_BIT (0) +#define SC_DATA_BITS (8) #define SC1_SPISTAT *((volatile uint32_t *)0x4000C840u) #define SC1_SPISTAT_REG *((volatile uint32_t *)0x4000C840u) #define SC1_SPISTAT_ADDR (0x4000C840u) #define SC1_SPISTAT_RESET (0x00000000u) - /* SC_SPITXIDLE field */ - #define SC_SPITXIDLE (0x00000008u) - #define SC_SPITXIDLE_MASK (0x00000008u) - #define SC_SPITXIDLE_BIT (3) - #define SC_SPITXIDLE_BITS (1) - /* SC_SPITXFREE field */ - #define SC_SPITXFREE (0x00000004u) - #define SC_SPITXFREE_MASK (0x00000004u) - #define SC_SPITXFREE_BIT (2) - #define SC_SPITXFREE_BITS (1) - /* SC_SPIRXVAL field */ - #define SC_SPIRXVAL (0x00000002u) - #define SC_SPIRXVAL_MASK (0x00000002u) - #define SC_SPIRXVAL_BIT (1) - #define SC_SPIRXVAL_BITS (1) - /* SC_SPIRXOVF field */ - #define SC_SPIRXOVF (0x00000001u) - #define SC_SPIRXOVF_MASK (0x00000001u) - #define SC_SPIRXOVF_BIT (0) - #define SC_SPIRXOVF_BITS (1) +/* SC_SPITXIDLE field */ +#define SC_SPITXIDLE (0x00000008u) +#define SC_SPITXIDLE_MASK (0x00000008u) +#define SC_SPITXIDLE_BIT (3) +#define SC_SPITXIDLE_BITS (1) +/* SC_SPITXFREE field */ +#define SC_SPITXFREE (0x00000004u) +#define SC_SPITXFREE_MASK (0x00000004u) +#define SC_SPITXFREE_BIT (2) +#define SC_SPITXFREE_BITS (1) +/* SC_SPIRXVAL field */ +#define SC_SPIRXVAL (0x00000002u) +#define SC_SPIRXVAL_MASK (0x00000002u) +#define SC_SPIRXVAL_BIT (1) +#define SC_SPIRXVAL_BITS (1) +/* SC_SPIRXOVF field */ +#define SC_SPIRXOVF (0x00000001u) +#define SC_SPIRXOVF_MASK (0x00000001u) +#define SC_SPIRXOVF_BIT (0) +#define SC_SPIRXOVF_BITS (1) #define SC1_TWISTAT *((volatile uint32_t *)0x4000C844u) #define SC1_TWISTAT_REG *((volatile uint32_t *)0x4000C844u) #define SC1_TWISTAT_ADDR (0x4000C844u) #define SC1_TWISTAT_RESET (0x00000000u) - /* SC_TWICMDFIN field */ - #define SC_TWICMDFIN (0x00000008u) - #define SC_TWICMDFIN_MASK (0x00000008u) - #define SC_TWICMDFIN_BIT (3) - #define SC_TWICMDFIN_BITS (1) - /* SC_TWIRXFIN field */ - #define SC_TWIRXFIN (0x00000004u) - #define SC_TWIRXFIN_MASK (0x00000004u) - #define SC_TWIRXFIN_BIT (2) - #define SC_TWIRXFIN_BITS (1) - /* SC_TWITXFIN field */ - #define SC_TWITXFIN (0x00000002u) - #define SC_TWITXFIN_MASK (0x00000002u) - #define SC_TWITXFIN_BIT (1) - #define SC_TWITXFIN_BITS (1) - /* SC_TWIRXNAK field */ - #define SC_TWIRXNAK (0x00000001u) - #define SC_TWIRXNAK_MASK (0x00000001u) - #define SC_TWIRXNAK_BIT (0) - #define SC_TWIRXNAK_BITS (1) +/* SC_TWICMDFIN field */ +#define SC_TWICMDFIN (0x00000008u) +#define SC_TWICMDFIN_MASK (0x00000008u) +#define SC_TWICMDFIN_BIT (3) +#define SC_TWICMDFIN_BITS (1) +/* SC_TWIRXFIN field */ +#define SC_TWIRXFIN (0x00000004u) +#define SC_TWIRXFIN_MASK (0x00000004u) +#define SC_TWIRXFIN_BIT (2) +#define SC_TWIRXFIN_BITS (1) +/* SC_TWITXFIN field */ +#define SC_TWITXFIN (0x00000002u) +#define SC_TWITXFIN_MASK (0x00000002u) +#define SC_TWITXFIN_BIT (1) +#define SC_TWITXFIN_BITS (1) +/* SC_TWIRXNAK field */ +#define SC_TWIRXNAK (0x00000001u) +#define SC_TWIRXNAK_MASK (0x00000001u) +#define SC_TWIRXNAK_BIT (0) +#define SC_TWIRXNAK_BITS (1) #define SC1_UARTSTAT *((volatile uint32_t *)0x4000C848u) #define SC1_UARTSTAT_REG *((volatile uint32_t *)0x4000C848u) #define SC1_UARTSTAT_ADDR (0x4000C848u) #define SC1_UARTSTAT_RESET (0x00000040u) - /* SC_UARTTXIDLE field */ - #define SC_UARTTXIDLE (0x00000040u) - #define SC_UARTTXIDLE_MASK (0x00000040u) - #define SC_UARTTXIDLE_BIT (6) - #define SC_UARTTXIDLE_BITS (1) - /* SC_UARTPARERR field */ - #define SC_UARTPARERR (0x00000020u) - #define SC_UARTPARERR_MASK (0x00000020u) - #define SC_UARTPARERR_BIT (5) - #define SC_UARTPARERR_BITS (1) - /* SC_UARTFRMERR field */ - #define SC_UARTFRMERR (0x00000010u) - #define SC_UARTFRMERR_MASK (0x00000010u) - #define SC_UARTFRMERR_BIT (4) - #define SC_UARTFRMERR_BITS (1) - /* SC_UARTRXOVF field */ - #define SC_UARTRXOVF (0x00000008u) - #define SC_UARTRXOVF_MASK (0x00000008u) - #define SC_UARTRXOVF_BIT (3) - #define SC_UARTRXOVF_BITS (1) - /* SC_UARTTXFREE field */ - #define SC_UARTTXFREE (0x00000004u) - #define SC_UARTTXFREE_MASK (0x00000004u) - #define SC_UARTTXFREE_BIT (2) - #define SC_UARTTXFREE_BITS (1) - /* SC_UARTRXVAL field */ - #define SC_UARTRXVAL (0x00000002u) - #define SC_UARTRXVAL_MASK (0x00000002u) - #define SC_UARTRXVAL_BIT (1) - #define SC_UARTRXVAL_BITS (1) - /* SC_UARTCTS field */ - #define SC_UARTCTS (0x00000001u) - #define SC_UARTCTS_MASK (0x00000001u) - #define SC_UARTCTS_BIT (0) - #define SC_UARTCTS_BITS (1) +/* SC_UARTTXIDLE field */ +#define SC_UARTTXIDLE (0x00000040u) +#define SC_UARTTXIDLE_MASK (0x00000040u) +#define SC_UARTTXIDLE_BIT (6) +#define SC_UARTTXIDLE_BITS (1) +/* SC_UARTPARERR field */ +#define SC_UARTPARERR (0x00000020u) +#define SC_UARTPARERR_MASK (0x00000020u) +#define SC_UARTPARERR_BIT (5) +#define SC_UARTPARERR_BITS (1) +/* SC_UARTFRMERR field */ +#define SC_UARTFRMERR (0x00000010u) +#define SC_UARTFRMERR_MASK (0x00000010u) +#define SC_UARTFRMERR_BIT (4) +#define SC_UARTFRMERR_BITS (1) +/* SC_UARTRXOVF field */ +#define SC_UARTRXOVF (0x00000008u) +#define SC_UARTRXOVF_MASK (0x00000008u) +#define SC_UARTRXOVF_BIT (3) +#define SC_UARTRXOVF_BITS (1) +/* SC_UARTTXFREE field */ +#define SC_UARTTXFREE (0x00000004u) +#define SC_UARTTXFREE_MASK (0x00000004u) +#define SC_UARTTXFREE_BIT (2) +#define SC_UARTTXFREE_BITS (1) +/* SC_UARTRXVAL field */ +#define SC_UARTRXVAL (0x00000002u) +#define SC_UARTRXVAL_MASK (0x00000002u) +#define SC_UARTRXVAL_BIT (1) +#define SC_UARTRXVAL_BITS (1) +/* SC_UARTCTS field */ +#define SC_UARTCTS (0x00000001u) +#define SC_UARTCTS_MASK (0x00000001u) +#define SC_UARTCTS_BIT (0) +#define SC_UARTCTS_BITS (1) #define SC1_TWICTRL1 *((volatile uint32_t *)0x4000C84Cu) #define SC1_TWICTRL1_REG *((volatile uint32_t *)0x4000C84Cu) #define SC1_TWICTRL1_ADDR (0x4000C84Cu) #define SC1_TWICTRL1_RESET (0x00000000u) - /* SC_TWISTOP field */ - #define SC_TWISTOP (0x00000008u) - #define SC_TWISTOP_MASK (0x00000008u) - #define SC_TWISTOP_BIT (3) - #define SC_TWISTOP_BITS (1) - /* SC_TWISTART field */ - #define SC_TWISTART (0x00000004u) - #define SC_TWISTART_MASK (0x00000004u) - #define SC_TWISTART_BIT (2) - #define SC_TWISTART_BITS (1) - /* SC_TWISEND field */ - #define SC_TWISEND (0x00000002u) - #define SC_TWISEND_MASK (0x00000002u) - #define SC_TWISEND_BIT (1) - #define SC_TWISEND_BITS (1) - /* SC_TWIRECV field */ - #define SC_TWIRECV (0x00000001u) - #define SC_TWIRECV_MASK (0x00000001u) - #define SC_TWIRECV_BIT (0) - #define SC_TWIRECV_BITS (1) +/* SC_TWISTOP field */ +#define SC_TWISTOP (0x00000008u) +#define SC_TWISTOP_MASK (0x00000008u) +#define SC_TWISTOP_BIT (3) +#define SC_TWISTOP_BITS (1) +/* SC_TWISTART field */ +#define SC_TWISTART (0x00000004u) +#define SC_TWISTART_MASK (0x00000004u) +#define SC_TWISTART_BIT (2) +#define SC_TWISTART_BITS (1) +/* SC_TWISEND field */ +#define SC_TWISEND (0x00000002u) +#define SC_TWISEND_MASK (0x00000002u) +#define SC_TWISEND_BIT (1) +#define SC_TWISEND_BITS (1) +/* SC_TWIRECV field */ +#define SC_TWIRECV (0x00000001u) +#define SC_TWIRECV_MASK (0x00000001u) +#define SC_TWIRECV_BIT (0) +#define SC_TWIRECV_BITS (1) #define SC1_TWICTRL2 *((volatile uint32_t *)0x4000C850u) #define SC1_TWICTRL2_REG *((volatile uint32_t *)0x4000C850u) #define SC1_TWICTRL2_ADDR (0x4000C850u) #define SC1_TWICTRL2_RESET (0x00000000u) - /* SC_TWIACK field */ - #define SC_TWIACK (0x00000001u) - #define SC_TWIACK_MASK (0x00000001u) - #define SC_TWIACK_BIT (0) - #define SC_TWIACK_BITS (1) +/* SC_TWIACK field */ +#define SC_TWIACK (0x00000001u) +#define SC_TWIACK_MASK (0x00000001u) +#define SC_TWIACK_BIT (0) +#define SC_TWIACK_BITS (1) #define SC1_MODE *((volatile uint32_t *)0x4000C854u) #define SC1_MODE_REG *((volatile uint32_t *)0x4000C854u) #define SC1_MODE_ADDR (0x4000C854u) #define SC1_MODE_RESET (0x00000000u) - /* SC_MODE field */ - #define SC_MODE (0x00000003u) - #define SC_MODE_MASK (0x00000003u) - #define SC_MODE_BIT (0) - #define SC_MODE_BITS (2) - /* SC_MODE Bit Field Values */ - #define SC1_MODE_DISABLED (0) - #define SC1_MODE_UART (1) - #define SC1_MODE_SPI (2) - #define SC1_MODE_I2C (3) +/* SC_MODE field */ +#define SC_MODE (0x00000003u) +#define SC_MODE_MASK (0x00000003u) +#define SC_MODE_BIT (0) +#define SC_MODE_BITS (2) +/* SC_MODE Bit Field Values */ +#define SC1_MODE_DISABLED (0) +#define SC1_MODE_UART (1) +#define SC1_MODE_SPI (2) +#define SC1_MODE_I2C (3) #define SC1_SPICFG *((volatile uint32_t *)0x4000C858u) #define SC1_SPICFG_REG *((volatile uint32_t *)0x4000C858u) #define SC1_SPICFG_ADDR (0x4000C858u) #define SC1_SPICFG_RESET (0x00000000u) - /* SC_SPIRXDRV field */ - #define SC_SPIRXDRV (0x00000020u) - #define SC_SPIRXDRV_MASK (0x00000020u) - #define SC_SPIRXDRV_BIT (5) - #define SC_SPIRXDRV_BITS (1) - /* SC_SPIMST field */ - #define SC_SPIMST (0x00000010u) - #define SC_SPIMST_MASK (0x00000010u) - #define SC_SPIMST_BIT (4) - #define SC_SPIMST_BITS (1) - /* SC_SPIRPT field */ - #define SC_SPIRPT (0x00000008u) - #define SC_SPIRPT_MASK (0x00000008u) - #define SC_SPIRPT_BIT (3) - #define SC_SPIRPT_BITS (1) - /* SC_SPIORD field */ - #define SC_SPIORD (0x00000004u) - #define SC_SPIORD_MASK (0x00000004u) - #define SC_SPIORD_BIT (2) - #define SC_SPIORD_BITS (1) - /* SC_SPIPHA field */ - #define SC_SPIPHA (0x00000002u) - #define SC_SPIPHA_MASK (0x00000002u) - #define SC_SPIPHA_BIT (1) - #define SC_SPIPHA_BITS (1) - /* SC_SPIPOL field */ - #define SC_SPIPOL (0x00000001u) - #define SC_SPIPOL_MASK (0x00000001u) - #define SC_SPIPOL_BIT (0) - #define SC_SPIPOL_BITS (1) +/* SC_SPIRXDRV field */ +#define SC_SPIRXDRV (0x00000020u) +#define SC_SPIRXDRV_MASK (0x00000020u) +#define SC_SPIRXDRV_BIT (5) +#define SC_SPIRXDRV_BITS (1) +/* SC_SPIMST field */ +#define SC_SPIMST (0x00000010u) +#define SC_SPIMST_MASK (0x00000010u) +#define SC_SPIMST_BIT (4) +#define SC_SPIMST_BITS (1) +/* SC_SPIRPT field */ +#define SC_SPIRPT (0x00000008u) +#define SC_SPIRPT_MASK (0x00000008u) +#define SC_SPIRPT_BIT (3) +#define SC_SPIRPT_BITS (1) +/* SC_SPIORD field */ +#define SC_SPIORD (0x00000004u) +#define SC_SPIORD_MASK (0x00000004u) +#define SC_SPIORD_BIT (2) +#define SC_SPIORD_BITS (1) +/* SC_SPIPHA field */ +#define SC_SPIPHA (0x00000002u) +#define SC_SPIPHA_MASK (0x00000002u) +#define SC_SPIPHA_BIT (1) +#define SC_SPIPHA_BITS (1) +/* SC_SPIPOL field */ +#define SC_SPIPOL (0x00000001u) +#define SC_SPIPOL_MASK (0x00000001u) +#define SC_SPIPOL_BIT (0) +#define SC_SPIPOL_BITS (1) #define SC1_UARTCFG *((volatile uint32_t *)0x4000C85Cu) #define SC1_UARTCFG_REG *((volatile uint32_t *)0x4000C85Cu) #define SC1_UARTCFG_ADDR (0x4000C85Cu) #define SC1_UARTCFG_RESET (0x00000000u) - /* SC_UARTAUTO field */ - #define SC_UARTAUTO (0x00000040u) - #define SC_UARTAUTO_MASK (0x00000040u) - #define SC_UARTAUTO_BIT (6) - #define SC_UARTAUTO_BITS (1) - /* SC_UARTFLOW field */ - #define SC_UARTFLOW (0x00000020u) - #define SC_UARTFLOW_MASK (0x00000020u) - #define SC_UARTFLOW_BIT (5) - #define SC_UARTFLOW_BITS (1) - /* SC_UARTODD field */ - #define SC_UARTODD (0x00000010u) - #define SC_UARTODD_MASK (0x00000010u) - #define SC_UARTODD_BIT (4) - #define SC_UARTODD_BITS (1) - /* SC_UARTPAR field */ - #define SC_UARTPAR (0x00000008u) - #define SC_UARTPAR_MASK (0x00000008u) - #define SC_UARTPAR_BIT (3) - #define SC_UARTPAR_BITS (1) - /* SC_UART2STP field */ - #define SC_UART2STP (0x00000004u) - #define SC_UART2STP_MASK (0x00000004u) - #define SC_UART2STP_BIT (2) - #define SC_UART2STP_BITS (1) - /* SC_UART8BIT field */ - #define SC_UART8BIT (0x00000002u) - #define SC_UART8BIT_MASK (0x00000002u) - #define SC_UART8BIT_BIT (1) - #define SC_UART8BIT_BITS (1) - /* SC_UARTRTS field */ - #define SC_UARTRTS (0x00000001u) - #define SC_UARTRTS_MASK (0x00000001u) - #define SC_UARTRTS_BIT (0) - #define SC_UARTRTS_BITS (1) +/* SC_UARTAUTO field */ +#define SC_UARTAUTO (0x00000040u) +#define SC_UARTAUTO_MASK (0x00000040u) +#define SC_UARTAUTO_BIT (6) +#define SC_UARTAUTO_BITS (1) +/* SC_UARTFLOW field */ +#define SC_UARTFLOW (0x00000020u) +#define SC_UARTFLOW_MASK (0x00000020u) +#define SC_UARTFLOW_BIT (5) +#define SC_UARTFLOW_BITS (1) +/* SC_UARTODD field */ +#define SC_UARTODD (0x00000010u) +#define SC_UARTODD_MASK (0x00000010u) +#define SC_UARTODD_BIT (4) +#define SC_UARTODD_BITS (1) +/* SC_UARTPAR field */ +#define SC_UARTPAR (0x00000008u) +#define SC_UARTPAR_MASK (0x00000008u) +#define SC_UARTPAR_BIT (3) +#define SC_UARTPAR_BITS (1) +/* SC_UART2STP field */ +#define SC_UART2STP (0x00000004u) +#define SC_UART2STP_MASK (0x00000004u) +#define SC_UART2STP_BIT (2) +#define SC_UART2STP_BITS (1) +/* SC_UART8BIT field */ +#define SC_UART8BIT (0x00000002u) +#define SC_UART8BIT_MASK (0x00000002u) +#define SC_UART8BIT_BIT (1) +#define SC_UART8BIT_BITS (1) +/* SC_UARTRTS field */ +#define SC_UARTRTS (0x00000001u) +#define SC_UARTRTS_MASK (0x00000001u) +#define SC_UARTRTS_BIT (0) +#define SC_UARTRTS_BITS (1) #define SC1_RATELIN *((volatile uint32_t *)0x4000C860u) #define SC1_RATELIN_REG *((volatile uint32_t *)0x4000C860u) #define SC1_RATELIN_ADDR (0x4000C860u) #define SC1_RATELIN_RESET (0x00000000u) - /* SC_RATELIN field */ - #define SC_RATELIN (0x0000000Fu) - #define SC_RATELIN_MASK (0x0000000Fu) - #define SC_RATELIN_BIT (0) - #define SC_RATELIN_BITS (4) +/* SC_RATELIN field */ +#define SC_RATELIN (0x0000000Fu) +#define SC_RATELIN_MASK (0x0000000Fu) +#define SC_RATELIN_BIT (0) +#define SC_RATELIN_BITS (4) #define SC1_RATEEXP *((volatile uint32_t *)0x4000C864u) #define SC1_RATEEXP_REG *((volatile uint32_t *)0x4000C864u) #define SC1_RATEEXP_ADDR (0x4000C864u) #define SC1_RATEEXP_RESET (0x00000000u) - /* SC_RATEEXP field */ - #define SC_RATEEXP (0x0000000Fu) - #define SC_RATEEXP_MASK (0x0000000Fu) - #define SC_RATEEXP_BIT (0) - #define SC_RATEEXP_BITS (4) +/* SC_RATEEXP field */ +#define SC_RATEEXP (0x0000000Fu) +#define SC_RATEEXP_MASK (0x0000000Fu) +#define SC_RATEEXP_BIT (0) +#define SC_RATEEXP_BITS (4) #define SC1_UARTPER *((volatile uint32_t *)0x4000C868u) #define SC1_UARTPER_REG *((volatile uint32_t *)0x4000C868u) #define SC1_UARTPER_ADDR (0x4000C868u) #define SC1_UARTPER_RESET (0x00000000u) - /* SC_UARTPER field */ - #define SC_UARTPER (0x0000FFFFu) - #define SC_UARTPER_MASK (0x0000FFFFu) - #define SC_UARTPER_BIT (0) - #define SC_UARTPER_BITS (16) +/* SC_UARTPER field */ +#define SC_UARTPER (0x0000FFFFu) +#define SC_UARTPER_MASK (0x0000FFFFu) +#define SC_UARTPER_BIT (0) +#define SC_UARTPER_BITS (16) #define SC1_UARTFRAC *((volatile uint32_t *)0x4000C86Cu) #define SC1_UARTFRAC_REG *((volatile uint32_t *)0x4000C86Cu) #define SC1_UARTFRAC_ADDR (0x4000C86Cu) #define SC1_UARTFRAC_RESET (0x00000000u) - /* SC_UARTFRAC field */ - #define SC_UARTFRAC (0x00000001u) - #define SC_UARTFRAC_MASK (0x00000001u) - #define SC_UARTFRAC_BIT (0) - #define SC_UARTFRAC_BITS (1) +/* SC_UARTFRAC field */ +#define SC_UARTFRAC (0x00000001u) +#define SC_UARTFRAC_MASK (0x00000001u) +#define SC_UARTFRAC_BIT (0) +#define SC_UARTFRAC_BITS (1) #define SC1_RXCNTSAVED *((volatile uint32_t *)0x4000C870u) #define SC1_RXCNTSAVED_REG *((volatile uint32_t *)0x4000C870u) #define SC1_RXCNTSAVED_ADDR (0x4000C870u) #define SC1_RXCNTSAVED_RESET (0x00000000u) - /* SC_RXCNTSAVED field */ - #define SC_RXCNTSAVED (0x00001FFFu) - #define SC_RXCNTSAVED_MASK (0x00001FFFu) - #define SC_RXCNTSAVED_BIT (0) - #define SC_RXCNTSAVED_BITS (13) +/* SC_RXCNTSAVED field */ +#define SC_RXCNTSAVED (0x00001FFFu) +#define SC_RXCNTSAVED_MASK (0x00001FFFu) +#define SC_RXCNTSAVED_BIT (0) +#define SC_RXCNTSAVED_BITS (13) /* ADC block */ #define BLOCK_ADC_BASE (0x4000D000u) @@ -6499,161 +6499,161 @@ #define ADC_DATA_REG *((volatile uint32_t *)0x4000D000u) #define ADC_DATA_ADDR (0x4000D000u) #define ADC_DATA_RESET (0x00000000u) - /* ADC_DATA_FIELD field */ - #define ADC_DATA_FIELD (0x0000FFFFu) - #define ADC_DATA_FIELD_MASK (0x0000FFFFu) - #define ADC_DATA_FIELD_BIT (0) - #define ADC_DATA_FIELD_BITS (16) +/* ADC_DATA_FIELD field */ +#define ADC_DATA_FIELD (0x0000FFFFu) +#define ADC_DATA_FIELD_MASK (0x0000FFFFu) +#define ADC_DATA_FIELD_BIT (0) +#define ADC_DATA_FIELD_BITS (16) #define ADC_CFG *((volatile uint32_t *)0x4000D004u) #define ADC_CFG_REG *((volatile uint32_t *)0x4000D004u) #define ADC_CFG_ADDR (0x4000D004u) #define ADC_CFG_RESET (0x00001800u) - /* ADC_PERIOD field */ - #define ADC_PERIOD (0x0000E000u) - #define ADC_PERIOD_MASK (0x0000E000u) - #define ADC_PERIOD_BIT (13) - #define ADC_PERIOD_BITS (3) - /* ADC_HVSELP field */ - #define ADC_HVSELP (0x00001000u) - #define ADC_HVSELP_MASK (0x00001000u) - #define ADC_HVSELP_BIT (12) - #define ADC_HVSELP_BITS (1) - /* ADC_HVSELN field */ - #define ADC_HVSELN (0x00000800u) - #define ADC_HVSELN_MASK (0x00000800u) - #define ADC_HVSELN_BIT (11) - #define ADC_HVSELN_BITS (1) - /* ADC_MUXP field */ - #define ADC_MUXP (0x00000780u) - #define ADC_MUXP_MASK (0x00000780u) - #define ADC_MUXP_BIT (7) - #define ADC_MUXP_BITS (4) - /* ADC_MUXN field */ - #define ADC_MUXN (0x00000078u) - #define ADC_MUXN_MASK (0x00000078u) - #define ADC_MUXN_BIT (3) - #define ADC_MUXN_BITS (4) - /* ADC_1MHZCLK field */ - #define ADC_1MHZCLK (0x00000004u) - #define ADC_1MHZCLK_MASK (0x00000004u) - #define ADC_1MHZCLK_BIT (2) - #define ADC_1MHZCLK_BITS (1) - /* ADC_CFGRSVD field */ - #define ADC_CFGRSVD (0x00000002u) - #define ADC_CFGRSVD_MASK (0x00000002u) - #define ADC_CFGRSVD_BIT (1) - #define ADC_CFGRSVD_BITS (1) - /* ADC_ENABLE field */ - #define ADC_ENABLE (0x00000001u) - #define ADC_ENABLE_MASK (0x00000001u) - #define ADC_ENABLE_BIT (0) - #define ADC_ENABLE_BITS (1) +/* ADC_PERIOD field */ +#define ADC_PERIOD (0x0000E000u) +#define ADC_PERIOD_MASK (0x0000E000u) +#define ADC_PERIOD_BIT (13) +#define ADC_PERIOD_BITS (3) +/* ADC_HVSELP field */ +#define ADC_HVSELP (0x00001000u) +#define ADC_HVSELP_MASK (0x00001000u) +#define ADC_HVSELP_BIT (12) +#define ADC_HVSELP_BITS (1) +/* ADC_HVSELN field */ +#define ADC_HVSELN (0x00000800u) +#define ADC_HVSELN_MASK (0x00000800u) +#define ADC_HVSELN_BIT (11) +#define ADC_HVSELN_BITS (1) +/* ADC_MUXP field */ +#define ADC_MUXP (0x00000780u) +#define ADC_MUXP_MASK (0x00000780u) +#define ADC_MUXP_BIT (7) +#define ADC_MUXP_BITS (4) +/* ADC_MUXN field */ +#define ADC_MUXN (0x00000078u) +#define ADC_MUXN_MASK (0x00000078u) +#define ADC_MUXN_BIT (3) +#define ADC_MUXN_BITS (4) +/* ADC_1MHZCLK field */ +#define ADC_1MHZCLK (0x00000004u) +#define ADC_1MHZCLK_MASK (0x00000004u) +#define ADC_1MHZCLK_BIT (2) +#define ADC_1MHZCLK_BITS (1) +/* ADC_CFGRSVD field */ +#define ADC_CFGRSVD (0x00000002u) +#define ADC_CFGRSVD_MASK (0x00000002u) +#define ADC_CFGRSVD_BIT (1) +#define ADC_CFGRSVD_BITS (1) +/* ADC_ENABLE field */ +#define ADC_ENABLE (0x00000001u) +#define ADC_ENABLE_MASK (0x00000001u) +#define ADC_ENABLE_BIT (0) +#define ADC_ENABLE_BITS (1) #define ADC_OFFSET *((volatile uint32_t *)0x4000D008u) #define ADC_OFFSET_REG *((volatile uint32_t *)0x4000D008u) #define ADC_OFFSET_ADDR (0x4000D008u) #define ADC_OFFSET_RESET (0x00000000u) - /* ADC_OFFSET_FIELD field */ - #define ADC_OFFSET_FIELD (0x0000FFFFu) - #define ADC_OFFSET_FIELD_MASK (0x0000FFFFu) - #define ADC_OFFSET_FIELD_BIT (0) - #define ADC_OFFSET_FIELD_BITS (16) +/* ADC_OFFSET_FIELD field */ +#define ADC_OFFSET_FIELD (0x0000FFFFu) +#define ADC_OFFSET_FIELD_MASK (0x0000FFFFu) +#define ADC_OFFSET_FIELD_BIT (0) +#define ADC_OFFSET_FIELD_BITS (16) #define ADC_GAIN *((volatile uint32_t *)0x4000D00Cu) #define ADC_GAIN_REG *((volatile uint32_t *)0x4000D00Cu) #define ADC_GAIN_ADDR (0x4000D00Cu) #define ADC_GAIN_RESET (0x00008000u) - /* ADC_GAIN_FIELD field */ - #define ADC_GAIN_FIELD (0x0000FFFFu) - #define ADC_GAIN_FIELD_MASK (0x0000FFFFu) - #define ADC_GAIN_FIELD_BIT (0) - #define ADC_GAIN_FIELD_BITS (16) +/* ADC_GAIN_FIELD field */ +#define ADC_GAIN_FIELD (0x0000FFFFu) +#define ADC_GAIN_FIELD_MASK (0x0000FFFFu) +#define ADC_GAIN_FIELD_BIT (0) +#define ADC_GAIN_FIELD_BITS (16) #define ADC_DMACFG *((volatile uint32_t *)0x4000D010u) #define ADC_DMACFG_REG *((volatile uint32_t *)0x4000D010u) #define ADC_DMACFG_ADDR (0x4000D010u) #define ADC_DMACFG_RESET (0x00000000u) - /* ADC_DMARST field */ - #define ADC_DMARST (0x00000010u) - #define ADC_DMARST_MASK (0x00000010u) - #define ADC_DMARST_BIT (4) - #define ADC_DMARST_BITS (1) - /* ADC_DMAAUTOWRAP field */ - #define ADC_DMAAUTOWRAP (0x00000002u) - #define ADC_DMAAUTOWRAP_MASK (0x00000002u) - #define ADC_DMAAUTOWRAP_BIT (1) - #define ADC_DMAAUTOWRAP_BITS (1) - /* ADC_DMALOAD field */ - #define ADC_DMALOAD (0x00000001u) - #define ADC_DMALOAD_MASK (0x00000001u) - #define ADC_DMALOAD_BIT (0) - #define ADC_DMALOAD_BITS (1) +/* ADC_DMARST field */ +#define ADC_DMARST (0x00000010u) +#define ADC_DMARST_MASK (0x00000010u) +#define ADC_DMARST_BIT (4) +#define ADC_DMARST_BITS (1) +/* ADC_DMAAUTOWRAP field */ +#define ADC_DMAAUTOWRAP (0x00000002u) +#define ADC_DMAAUTOWRAP_MASK (0x00000002u) +#define ADC_DMAAUTOWRAP_BIT (1) +#define ADC_DMAAUTOWRAP_BITS (1) +/* ADC_DMALOAD field */ +#define ADC_DMALOAD (0x00000001u) +#define ADC_DMALOAD_MASK (0x00000001u) +#define ADC_DMALOAD_BIT (0) +#define ADC_DMALOAD_BITS (1) #define ADC_DMASTAT *((volatile uint32_t *)0x4000D014u) #define ADC_DMASTAT_REG *((volatile uint32_t *)0x4000D014u) #define ADC_DMASTAT_ADDR (0x4000D014u) #define ADC_DMASTAT_RESET (0x00000000u) - /* ADC_DMAOVF field */ - #define ADC_DMAOVF (0x00000002u) - #define ADC_DMAOVF_MASK (0x00000002u) - #define ADC_DMAOVF_BIT (1) - #define ADC_DMAOVF_BITS (1) - /* ADC_DMAACT field */ - #define ADC_DMAACT (0x00000001u) - #define ADC_DMAACT_MASK (0x00000001u) - #define ADC_DMAACT_BIT (0) - #define ADC_DMAACT_BITS (1) +/* ADC_DMAOVF field */ +#define ADC_DMAOVF (0x00000002u) +#define ADC_DMAOVF_MASK (0x00000002u) +#define ADC_DMAOVF_BIT (1) +#define ADC_DMAOVF_BITS (1) +/* ADC_DMAACT field */ +#define ADC_DMAACT (0x00000001u) +#define ADC_DMAACT_MASK (0x00000001u) +#define ADC_DMAACT_BIT (0) +#define ADC_DMAACT_BITS (1) #define ADC_DMABEG *((volatile uint32_t *)0x4000D018u) #define ADC_DMABEG_REG *((volatile uint32_t *)0x4000D018u) #define ADC_DMABEG_ADDR (0x4000D018u) #define ADC_DMABEG_RESET (0x20000000u) - /* ADC_DMABEG_FIXED field */ - #define ADC_DMABEG_FIXED (0xFFFFE000u) - #define ADC_DMABEG_FIXED_MASK (0xFFFFE000u) - #define ADC_DMABEG_FIXED_BIT (13) - #define ADC_DMABEG_FIXED_BITS (19) - /* ADC_DMABEG_FIELD field */ - #define ADC_DMABEG_FIELD (0x00001FFFu) - #define ADC_DMABEG_FIELD_MASK (0x00001FFFu) - #define ADC_DMABEG_FIELD_BIT (0) - #define ADC_DMABEG_FIELD_BITS (13) +/* ADC_DMABEG_FIXED field */ +#define ADC_DMABEG_FIXED (0xFFFFE000u) +#define ADC_DMABEG_FIXED_MASK (0xFFFFE000u) +#define ADC_DMABEG_FIXED_BIT (13) +#define ADC_DMABEG_FIXED_BITS (19) +/* ADC_DMABEG_FIELD field */ +#define ADC_DMABEG_FIELD (0x00001FFFu) +#define ADC_DMABEG_FIELD_MASK (0x00001FFFu) +#define ADC_DMABEG_FIELD_BIT (0) +#define ADC_DMABEG_FIELD_BITS (13) #define ADC_DMASIZE *((volatile uint32_t *)0x4000D01Cu) #define ADC_DMASIZE_REG *((volatile uint32_t *)0x4000D01Cu) #define ADC_DMASIZE_ADDR (0x4000D01Cu) #define ADC_DMASIZE_RESET (0x00000000u) - /* ADC_DMASIZE_FIELD field */ - #define ADC_DMASIZE_FIELD (0x00000FFFu) - #define ADC_DMASIZE_FIELD_MASK (0x00000FFFu) - #define ADC_DMASIZE_FIELD_BIT (0) - #define ADC_DMASIZE_FIELD_BITS (12) +/* ADC_DMASIZE_FIELD field */ +#define ADC_DMASIZE_FIELD (0x00000FFFu) +#define ADC_DMASIZE_FIELD_MASK (0x00000FFFu) +#define ADC_DMASIZE_FIELD_BIT (0) +#define ADC_DMASIZE_FIELD_BITS (12) #define ADC_DMACUR *((volatile uint32_t *)0x4000D020u) #define ADC_DMACUR_REG *((volatile uint32_t *)0x4000D020u) #define ADC_DMACUR_ADDR (0x4000D020u) #define ADC_DMACUR_RESET (0x20000000u) - /* ADC_DMACUR_FIXED field */ - #define ADC_DMACUR_FIXED (0xFFFFE000u) - #define ADC_DMACUR_FIXED_MASK (0xFFFFE000u) - #define ADC_DMACUR_FIXED_BIT (13) - #define ADC_DMACUR_FIXED_BITS (19) - /* ADC_DMACUR_FIELD field */ - #define ADC_DMACUR_FIELD (0x00001FFFu) - #define ADC_DMACUR_FIELD_MASK (0x00001FFFu) - #define ADC_DMACUR_FIELD_BIT (0) - #define ADC_DMACUR_FIELD_BITS (13) +/* ADC_DMACUR_FIXED field */ +#define ADC_DMACUR_FIXED (0xFFFFE000u) +#define ADC_DMACUR_FIXED_MASK (0xFFFFE000u) +#define ADC_DMACUR_FIXED_BIT (13) +#define ADC_DMACUR_FIXED_BITS (19) +/* ADC_DMACUR_FIELD field */ +#define ADC_DMACUR_FIELD (0x00001FFFu) +#define ADC_DMACUR_FIELD_MASK (0x00001FFFu) +#define ADC_DMACUR_FIELD_BIT (0) +#define ADC_DMACUR_FIELD_BITS (13) #define ADC_DMACNT *((volatile uint32_t *)0x4000D024u) #define ADC_DMACNT_REG *((volatile uint32_t *)0x4000D024u) #define ADC_DMACNT_ADDR (0x4000D024u) #define ADC_DMACNT_RESET (0x00000000u) - /* ADC_DMACNT_FIELD field */ - #define ADC_DMACNT_FIELD (0x00000FFFu) - #define ADC_DMACNT_FIELD_MASK (0x00000FFFu) - #define ADC_DMACNT_FIELD_BIT (0) - #define ADC_DMACNT_FIELD_BITS (12) +/* ADC_DMACNT_FIELD field */ +#define ADC_DMACNT_FIELD (0x00000FFFu) +#define ADC_DMACNT_FIELD_MASK (0x00000FFFu) +#define ADC_DMACNT_FIELD_BIT (0) +#define ADC_DMACNT_FIELD_BITS (12) /* TIM1 block */ #define BLOCK_TIM1_BASE (0x4000E000u) @@ -6664,506 +6664,506 @@ #define TIM1_CR1_REG *((volatile uint32_t *)0x4000E000u) #define TIM1_CR1_ADDR (0x4000E000u) #define TIM1_CR1_RESET (0x00000000u) - /* TIM_ARBE field */ - #define TIM_ARBE (0x00000080u) - #define TIM_ARBE_MASK (0x00000080u) - #define TIM_ARBE_BIT (7) - #define TIM_ARBE_BITS (1) - /* TIM_CMS field */ - #define TIM_CMS (0x00000060u) - #define TIM_CMS_MASK (0x00000060u) - #define TIM_CMS_BIT (5) - #define TIM_CMS_BITS (2) - /* TIM_DIR field */ - #define TIM_DIR (0x00000010u) - #define TIM_DIR_MASK (0x00000010u) - #define TIM_DIR_BIT (4) - #define TIM_DIR_BITS (1) - /* TIM_OPM field */ - #define TIM_OPM (0x00000008u) - #define TIM_OPM_MASK (0x00000008u) - #define TIM_OPM_BIT (3) - #define TIM_OPM_BITS (1) - /* TIM_URS field */ - #define TIM_URS (0x00000004u) - #define TIM_URS_MASK (0x00000004u) - #define TIM_URS_BIT (2) - #define TIM_URS_BITS (1) - /* TIM_UDIS field */ - #define TIM_UDIS (0x00000002u) - #define TIM_UDIS_MASK (0x00000002u) - #define TIM_UDIS_BIT (1) - #define TIM_UDIS_BITS (1) - /* TIM_CEN field */ - #define TIM_CEN (0x00000001u) - #define TIM_CEN_MASK (0x00000001u) - #define TIM_CEN_BIT (0) - #define TIM_CEN_BITS (1) +/* TIM_ARBE field */ +#define TIM_ARBE (0x00000080u) +#define TIM_ARBE_MASK (0x00000080u) +#define TIM_ARBE_BIT (7) +#define TIM_ARBE_BITS (1) +/* TIM_CMS field */ +#define TIM_CMS (0x00000060u) +#define TIM_CMS_MASK (0x00000060u) +#define TIM_CMS_BIT (5) +#define TIM_CMS_BITS (2) +/* TIM_DIR field */ +#define TIM_DIR (0x00000010u) +#define TIM_DIR_MASK (0x00000010u) +#define TIM_DIR_BIT (4) +#define TIM_DIR_BITS (1) +/* TIM_OPM field */ +#define TIM_OPM (0x00000008u) +#define TIM_OPM_MASK (0x00000008u) +#define TIM_OPM_BIT (3) +#define TIM_OPM_BITS (1) +/* TIM_URS field */ +#define TIM_URS (0x00000004u) +#define TIM_URS_MASK (0x00000004u) +#define TIM_URS_BIT (2) +#define TIM_URS_BITS (1) +/* TIM_UDIS field */ +#define TIM_UDIS (0x00000002u) +#define TIM_UDIS_MASK (0x00000002u) +#define TIM_UDIS_BIT (1) +#define TIM_UDIS_BITS (1) +/* TIM_CEN field */ +#define TIM_CEN (0x00000001u) +#define TIM_CEN_MASK (0x00000001u) +#define TIM_CEN_BIT (0) +#define TIM_CEN_BITS (1) #define TIM1_CR2 *((volatile uint32_t *)0x4000E004u) #define TIM1_CR2_REG *((volatile uint32_t *)0x4000E004u) #define TIM1_CR2_ADDR (0x4000E004u) #define TIM1_CR2_RESET (0x00000000u) - /* TIM_TI1S field */ - #define TIM_TI1S (0x00000080u) - #define TIM_TI1S_MASK (0x00000080u) - #define TIM_TI1S_BIT (7) - #define TIM_TI1S_BITS (1) - /* TIM_MMS field */ - #define TIM_MMS (0x00000070u) - #define TIM_MMS_MASK (0x00000070u) - #define TIM_MMS_BIT (4) - #define TIM_MMS_BITS (3) +/* TIM_TI1S field */ +#define TIM_TI1S (0x00000080u) +#define TIM_TI1S_MASK (0x00000080u) +#define TIM_TI1S_BIT (7) +#define TIM_TI1S_BITS (1) +/* TIM_MMS field */ +#define TIM_MMS (0x00000070u) +#define TIM_MMS_MASK (0x00000070u) +#define TIM_MMS_BIT (4) +#define TIM_MMS_BITS (3) #define TIM1_SMCR *((volatile uint32_t *)0x4000E008u) #define TIM1_SMCR_REG *((volatile uint32_t *)0x4000E008u) #define TIM1_SMCR_ADDR (0x4000E008u) #define TIM1_SMCR_RESET (0x00000000u) - /* TIM_ETP field */ - #define TIM_ETP (0x00008000u) - #define TIM_ETP_MASK (0x00008000u) - #define TIM_ETP_BIT (15) - #define TIM_ETP_BITS (1) - /* TIM_ECE field */ - #define TIM_ECE (0x00004000u) - #define TIM_ECE_MASK (0x00004000u) - #define TIM_ECE_BIT (14) - #define TIM_ECE_BITS (1) - /* TIM_ETPS field */ - #define TIM_ETPS (0x00003000u) - #define TIM_ETPS_MASK (0x00003000u) - #define TIM_ETPS_BIT (12) - #define TIM_ETPS_BITS (2) - /* TIM_ETF field */ - #define TIM_ETF (0x00000F00u) - #define TIM_ETF_MASK (0x00000F00u) - #define TIM_ETF_BIT (8) - #define TIM_ETF_BITS (4) - /* TIM_MSM field */ - #define TIM_MSM (0x00000080u) - #define TIM_MSM_MASK (0x00000080u) - #define TIM_MSM_BIT (7) - #define TIM_MSM_BITS (1) - /* TIM_TS field */ - #define TIM_TS (0x00000070u) - #define TIM_TS_MASK (0x00000070u) - #define TIM_TS_BIT (4) - #define TIM_TS_BITS (3) - /* TIM_SMS field */ - #define TIM_SMS (0x00000007u) - #define TIM_SMS_MASK (0x00000007u) - #define TIM_SMS_BIT (0) - #define TIM_SMS_BITS (3) +/* TIM_ETP field */ +#define TIM_ETP (0x00008000u) +#define TIM_ETP_MASK (0x00008000u) +#define TIM_ETP_BIT (15) +#define TIM_ETP_BITS (1) +/* TIM_ECE field */ +#define TIM_ECE (0x00004000u) +#define TIM_ECE_MASK (0x00004000u) +#define TIM_ECE_BIT (14) +#define TIM_ECE_BITS (1) +/* TIM_ETPS field */ +#define TIM_ETPS (0x00003000u) +#define TIM_ETPS_MASK (0x00003000u) +#define TIM_ETPS_BIT (12) +#define TIM_ETPS_BITS (2) +/* TIM_ETF field */ +#define TIM_ETF (0x00000F00u) +#define TIM_ETF_MASK (0x00000F00u) +#define TIM_ETF_BIT (8) +#define TIM_ETF_BITS (4) +/* TIM_MSM field */ +#define TIM_MSM (0x00000080u) +#define TIM_MSM_MASK (0x00000080u) +#define TIM_MSM_BIT (7) +#define TIM_MSM_BITS (1) +/* TIM_TS field */ +#define TIM_TS (0x00000070u) +#define TIM_TS_MASK (0x00000070u) +#define TIM_TS_BIT (4) +#define TIM_TS_BITS (3) +/* TIM_SMS field */ +#define TIM_SMS (0x00000007u) +#define TIM_SMS_MASK (0x00000007u) +#define TIM_SMS_BIT (0) +#define TIM_SMS_BITS (3) #define TMR1_DIER *((volatile uint32_t *)0x4000E00Cu) #define TMR1_DIER_REG *((volatile uint32_t *)0x4000E00Cu) #define TMR1_DIER_ADDR (0x4000E00Cu) #define TMR1_DIER_RESET (0x00000000u) - /* TIE field */ - #define TMR1_DIER_TIE (0x00000040u) - #define TMR1_DIER_TIE_MASK (0x00000040u) - #define TMR1_DIER_TIE_BIT (6) - #define TMR1_DIER_TIE_BITS (1) - /* CC4IE field */ - #define TMR1_DIER_CC4IE (0x00000010u) - #define TMR1_DIER_CC4IE_MASK (0x00000010u) - #define TMR1_DIER_CC4IE_BIT (4) - #define TMR1_DIER_CC4IE_BITS (1) - /* CC3IE field */ - #define TMR1_DIER_CC3IE (0x00000008u) - #define TMR1_DIER_CC3IE_MASK (0x00000008u) - #define TMR1_DIER_CC3IE_BIT (3) - #define TMR1_DIER_CC3IE_BITS (1) - /* CC2IE field */ - #define TMR1_DIER_CC2IE (0x00000004u) - #define TMR1_DIER_CC2IE_MASK (0x00000004u) - #define TMR1_DIER_CC2IE_BIT (2) - #define TMR1_DIER_CC2IE_BITS (1) - /* CC1IE field */ - #define TMR1_DIER_CC1IE (0x00000002u) - #define TMR1_DIER_CC1IE_MASK (0x00000002u) - #define TMR1_DIER_CC1IE_BIT (1) - #define TMR1_DIER_CC1IE_BITS (1) - /* UIE field */ - #define TMR1_DIER_UIE (0x00000001u) - #define TMR1_DIER_UIE_MASK (0x00000001u) - #define TMR1_DIER_UIE_BIT (0) - #define TMR1_DIER_UIE_BITS (1) +/* TIE field */ +#define TMR1_DIER_TIE (0x00000040u) +#define TMR1_DIER_TIE_MASK (0x00000040u) +#define TMR1_DIER_TIE_BIT (6) +#define TMR1_DIER_TIE_BITS (1) +/* CC4IE field */ +#define TMR1_DIER_CC4IE (0x00000010u) +#define TMR1_DIER_CC4IE_MASK (0x00000010u) +#define TMR1_DIER_CC4IE_BIT (4) +#define TMR1_DIER_CC4IE_BITS (1) +/* CC3IE field */ +#define TMR1_DIER_CC3IE (0x00000008u) +#define TMR1_DIER_CC3IE_MASK (0x00000008u) +#define TMR1_DIER_CC3IE_BIT (3) +#define TMR1_DIER_CC3IE_BITS (1) +/* CC2IE field */ +#define TMR1_DIER_CC2IE (0x00000004u) +#define TMR1_DIER_CC2IE_MASK (0x00000004u) +#define TMR1_DIER_CC2IE_BIT (2) +#define TMR1_DIER_CC2IE_BITS (1) +/* CC1IE field */ +#define TMR1_DIER_CC1IE (0x00000002u) +#define TMR1_DIER_CC1IE_MASK (0x00000002u) +#define TMR1_DIER_CC1IE_BIT (1) +#define TMR1_DIER_CC1IE_BITS (1) +/* UIE field */ +#define TMR1_DIER_UIE (0x00000001u) +#define TMR1_DIER_UIE_MASK (0x00000001u) +#define TMR1_DIER_UIE_BIT (0) +#define TMR1_DIER_UIE_BITS (1) #define TMR1_SR *((volatile uint32_t *)0x4000E010u) #define TMR1_SR_REG *((volatile uint32_t *)0x4000E010u) #define TMR1_SR_ADDR (0x4000E010u) #define TMR1_SR_RESET (0x00000000u) - /* CC4OF field */ - #define TMR1_SR_CC4OF (0x00001000u) - #define TMR1_SR_CC4OF_MASK (0x00001000u) - #define TMR1_SR_CC4OF_BIT (12) - #define TMR1_SR_CC4OF_BITS (1) - /* CC3OF field */ - #define TMR1_SR_CC3OF (0x00000800u) - #define TMR1_SR_CC3OF_MASK (0x00000800u) - #define TMR1_SR_CC3OF_BIT (11) - #define TMR1_SR_CC3OF_BITS (1) - /* CC2OF field */ - #define TMR1_SR_CC2OF (0x00000400u) - #define TMR1_SR_CC2OF_MASK (0x00000400u) - #define TMR1_SR_CC2OF_BIT (10) - #define TMR1_SR_CC2OF_BITS (1) - /* CC1OF field */ - #define TMR1_SR_CC1OF (0x00000200u) - #define TMR1_SR_CC1OF_MASK (0x00000200u) - #define TMR1_SR_CC1OF_BIT (9) - #define TMR1_SR_CC1OF_BITS (1) - /* TIF field */ - #define TMR1_SR_TIF (0x00000040u) - #define TMR1_SR_TIF_MASK (0x00000040u) - #define TMR1_SR_TIF_BIT (6) - #define TMR1_SR_TIF_BITS (1) - /* CC4IF field */ - #define TMR1_SR_CC4IF (0x00000010u) - #define TMR1_SR_CC4IF_MASK (0x00000010u) - #define TMR1_SR_CC4IF_BIT (4) - #define TMR1_SR_CC4IF_BITS (1) - /* CC3IF field */ - #define TMR1_SR_CC3IF (0x00000008u) - #define TMR1_SR_CC3IF_MASK (0x00000008u) - #define TMR1_SR_CC3IF_BIT (3) - #define TMR1_SR_CC3IF_BITS (1) - /* CC2IF field */ - #define TMR1_SR_CC2IF (0x00000004u) - #define TMR1_SR_CC2IF_MASK (0x00000004u) - #define TMR1_SR_CC2IF_BIT (2) - #define TMR1_SR_CC2IF_BITS (1) - /* CC1IF field */ - #define TMR1_SR_CC1IF (0x00000002u) - #define TMR1_SR_CC1IF_MASK (0x00000002u) - #define TMR1_SR_CC1IF_BIT (1) - #define TMR1_SR_CC1IF_BITS (1) - /* UIF field */ - #define TMR1_SR_UIF (0x00000001u) - #define TMR1_SR_UIF_MASK (0x00000001u) - #define TMR1_SR_UIF_BIT (0) - #define TMR1_SR_UIF_BITS (1) +/* CC4OF field */ +#define TMR1_SR_CC4OF (0x00001000u) +#define TMR1_SR_CC4OF_MASK (0x00001000u) +#define TMR1_SR_CC4OF_BIT (12) +#define TMR1_SR_CC4OF_BITS (1) +/* CC3OF field */ +#define TMR1_SR_CC3OF (0x00000800u) +#define TMR1_SR_CC3OF_MASK (0x00000800u) +#define TMR1_SR_CC3OF_BIT (11) +#define TMR1_SR_CC3OF_BITS (1) +/* CC2OF field */ +#define TMR1_SR_CC2OF (0x00000400u) +#define TMR1_SR_CC2OF_MASK (0x00000400u) +#define TMR1_SR_CC2OF_BIT (10) +#define TMR1_SR_CC2OF_BITS (1) +/* CC1OF field */ +#define TMR1_SR_CC1OF (0x00000200u) +#define TMR1_SR_CC1OF_MASK (0x00000200u) +#define TMR1_SR_CC1OF_BIT (9) +#define TMR1_SR_CC1OF_BITS (1) +/* TIF field */ +#define TMR1_SR_TIF (0x00000040u) +#define TMR1_SR_TIF_MASK (0x00000040u) +#define TMR1_SR_TIF_BIT (6) +#define TMR1_SR_TIF_BITS (1) +/* CC4IF field */ +#define TMR1_SR_CC4IF (0x00000010u) +#define TMR1_SR_CC4IF_MASK (0x00000010u) +#define TMR1_SR_CC4IF_BIT (4) +#define TMR1_SR_CC4IF_BITS (1) +/* CC3IF field */ +#define TMR1_SR_CC3IF (0x00000008u) +#define TMR1_SR_CC3IF_MASK (0x00000008u) +#define TMR1_SR_CC3IF_BIT (3) +#define TMR1_SR_CC3IF_BITS (1) +/* CC2IF field */ +#define TMR1_SR_CC2IF (0x00000004u) +#define TMR1_SR_CC2IF_MASK (0x00000004u) +#define TMR1_SR_CC2IF_BIT (2) +#define TMR1_SR_CC2IF_BITS (1) +/* CC1IF field */ +#define TMR1_SR_CC1IF (0x00000002u) +#define TMR1_SR_CC1IF_MASK (0x00000002u) +#define TMR1_SR_CC1IF_BIT (1) +#define TMR1_SR_CC1IF_BITS (1) +/* UIF field */ +#define TMR1_SR_UIF (0x00000001u) +#define TMR1_SR_UIF_MASK (0x00000001u) +#define TMR1_SR_UIF_BIT (0) +#define TMR1_SR_UIF_BITS (1) #define TIM1_EGR *((volatile uint32_t *)0x4000E014u) #define TIM1_EGR_REG *((volatile uint32_t *)0x4000E014u) #define TIM1_EGR_ADDR (0x4000E014u) #define TIM1_EGR_RESET (0x00000000u) - /* TIM_TG field */ - #define TIM_TG (0x00000040u) - #define TIM_TG_MASK (0x00000040u) - #define TIM_TG_BIT (6) - #define TIM_TG_BITS (1) - /* TIM_CC4G field */ - #define TIM_CC4G (0x00000010u) - #define TIM_CC4G_MASK (0x00000010u) - #define TIM_CC4G_BIT (4) - #define TIM_CC4G_BITS (1) - /* TIM_CC3G field */ - #define TIM_CC3G (0x00000008u) - #define TIM_CC3G_MASK (0x00000008u) - #define TIM_CC3G_BIT (3) - #define TIM_CC3G_BITS (1) - /* TIM_CC2G field */ - #define TIM_CC2G (0x00000004u) - #define TIM_CC2G_MASK (0x00000004u) - #define TIM_CC2G_BIT (2) - #define TIM_CC2G_BITS (1) - /* TIM_CC1G field */ - #define TIM_CC1G (0x00000002u) - #define TIM_CC1G_MASK (0x00000002u) - #define TIM_CC1G_BIT (1) - #define TIM_CC1G_BITS (1) - /* TIM_UG field */ - #define TIM_UG (0x00000001u) - #define TIM_UG_MASK (0x00000001u) - #define TIM_UG_BIT (0) - #define TIM_UG_BITS (1) +/* TIM_TG field */ +#define TIM_TG (0x00000040u) +#define TIM_TG_MASK (0x00000040u) +#define TIM_TG_BIT (6) +#define TIM_TG_BITS (1) +/* TIM_CC4G field */ +#define TIM_CC4G (0x00000010u) +#define TIM_CC4G_MASK (0x00000010u) +#define TIM_CC4G_BIT (4) +#define TIM_CC4G_BITS (1) +/* TIM_CC3G field */ +#define TIM_CC3G (0x00000008u) +#define TIM_CC3G_MASK (0x00000008u) +#define TIM_CC3G_BIT (3) +#define TIM_CC3G_BITS (1) +/* TIM_CC2G field */ +#define TIM_CC2G (0x00000004u) +#define TIM_CC2G_MASK (0x00000004u) +#define TIM_CC2G_BIT (2) +#define TIM_CC2G_BITS (1) +/* TIM_CC1G field */ +#define TIM_CC1G (0x00000002u) +#define TIM_CC1G_MASK (0x00000002u) +#define TIM_CC1G_BIT (1) +#define TIM_CC1G_BITS (1) +/* TIM_UG field */ +#define TIM_UG (0x00000001u) +#define TIM_UG_MASK (0x00000001u) +#define TIM_UG_BIT (0) +#define TIM_UG_BITS (1) #define TIM1_CCMR1 *((volatile uint32_t *)0x4000E018u) #define TIM1_CCMR1_REG *((volatile uint32_t *)0x4000E018u) #define TIM1_CCMR1_ADDR (0x4000E018u) #define TIM1_CCMR1_RESET (0x00000000u) - /* TIM_IC2F field */ - #define TIM_IC2F (0x0000F000u) - #define TIM_IC2F_MASK (0x0000F000u) - #define TIM_IC2F_BIT (12) - #define TIM_IC2F_BITS (4) - /* TIM_IC2PSC field */ - #define TIM_IC2PSC (0x00000C00u) - #define TIM_IC2PSC_MASK (0x00000C00u) - #define TIM_IC2PSC_BIT (10) - #define TIM_IC2PSC_BITS (2) - /* TIM_IC1F field */ - #define TIM_IC1F (0x000000F0u) - #define TIM_IC1F_MASK (0x000000F0u) - #define TIM_IC1F_BIT (4) - #define TIM_IC1F_BITS (4) - /* TIM_IC1PSC field */ - #define TIM_IC1PSC (0x0000000Cu) - #define TIM_IC1PSC_MASK (0x0000000Cu) - #define TIM_IC1PSC_BIT (2) - #define TIM_IC1PSC_BITS (2) - /* TIM_OC2CE field */ - #define TIM_OC2CE (0x00008000u) - #define TIM_OC2CE_MASK (0x00008000u) - #define TIM_OC2CE_BIT (15) - #define TIM_OC2CE_BITS (1) - /* TIM_OC2M field */ - #define TIM_OC2M (0x00007000u) - #define TIM_OC2M_MASK (0x00007000u) - #define TIM_OC2M_BIT (12) - #define TIM_OC2M_BITS (3) - /* TIM_OC2BE field */ - #define TIM_OC2BE (0x00000800u) - #define TIM_OC2BE_MASK (0x00000800u) - #define TIM_OC2BE_BIT (11) - #define TIM_OC2BE_BITS (1) - /* TIM_OC2FE field */ - #define TIM_OC2FE (0x00000400u) - #define TIM_OC2FE_MASK (0x00000400u) - #define TIM_OC2FE_BIT (10) - #define TIM_OC2FE_BITS (1) - /* TIM_CC2S field */ - #define TIM_CC2S (0x00000300u) - #define TIM_CC2S_MASK (0x00000300u) - #define TIM_CC2S_BIT (8) - #define TIM_CC2S_BITS (2) - /* TIM_OC1CE field */ - #define TIM_OC1CE (0x00000080u) - #define TIM_OC1CE_MASK (0x00000080u) - #define TIM_OC1CE_BIT (7) - #define TIM_OC1CE_BITS (1) - /* TIM_OC1M field */ - #define TIM_OC1M (0x00000070u) - #define TIM_OC1M_MASK (0x00000070u) - #define TIM_OC1M_BIT (4) - #define TIM_OC1M_BITS (3) - /* TIM_OC1PE field */ - #define TIM_OC1PE (0x00000008u) - #define TIM_OC1PE_MASK (0x00000008u) - #define TIM_OC1PE_BIT (3) - #define TIM_OC1PE_BITS (1) - /* TIM_OC1FE field */ - #define TIM_OC1FE (0x00000004u) - #define TIM_OC1FE_MASK (0x00000004u) - #define TIM_OC1FE_BIT (2) - #define TIM_OC1FE_BITS (1) - /* TIM_CC1S field */ - #define TIM_CC1S (0x00000003u) - #define TIM_CC1S_MASK (0x00000003u) - #define TIM_CC1S_BIT (0) - #define TIM_CC1S_BITS (2) +/* TIM_IC2F field */ +#define TIM_IC2F (0x0000F000u) +#define TIM_IC2F_MASK (0x0000F000u) +#define TIM_IC2F_BIT (12) +#define TIM_IC2F_BITS (4) +/* TIM_IC2PSC field */ +#define TIM_IC2PSC (0x00000C00u) +#define TIM_IC2PSC_MASK (0x00000C00u) +#define TIM_IC2PSC_BIT (10) +#define TIM_IC2PSC_BITS (2) +/* TIM_IC1F field */ +#define TIM_IC1F (0x000000F0u) +#define TIM_IC1F_MASK (0x000000F0u) +#define TIM_IC1F_BIT (4) +#define TIM_IC1F_BITS (4) +/* TIM_IC1PSC field */ +#define TIM_IC1PSC (0x0000000Cu) +#define TIM_IC1PSC_MASK (0x0000000Cu) +#define TIM_IC1PSC_BIT (2) +#define TIM_IC1PSC_BITS (2) +/* TIM_OC2CE field */ +#define TIM_OC2CE (0x00008000u) +#define TIM_OC2CE_MASK (0x00008000u) +#define TIM_OC2CE_BIT (15) +#define TIM_OC2CE_BITS (1) +/* TIM_OC2M field */ +#define TIM_OC2M (0x00007000u) +#define TIM_OC2M_MASK (0x00007000u) +#define TIM_OC2M_BIT (12) +#define TIM_OC2M_BITS (3) +/* TIM_OC2BE field */ +#define TIM_OC2BE (0x00000800u) +#define TIM_OC2BE_MASK (0x00000800u) +#define TIM_OC2BE_BIT (11) +#define TIM_OC2BE_BITS (1) +/* TIM_OC2FE field */ +#define TIM_OC2FE (0x00000400u) +#define TIM_OC2FE_MASK (0x00000400u) +#define TIM_OC2FE_BIT (10) +#define TIM_OC2FE_BITS (1) +/* TIM_CC2S field */ +#define TIM_CC2S (0x00000300u) +#define TIM_CC2S_MASK (0x00000300u) +#define TIM_CC2S_BIT (8) +#define TIM_CC2S_BITS (2) +/* TIM_OC1CE field */ +#define TIM_OC1CE (0x00000080u) +#define TIM_OC1CE_MASK (0x00000080u) +#define TIM_OC1CE_BIT (7) +#define TIM_OC1CE_BITS (1) +/* TIM_OC1M field */ +#define TIM_OC1M (0x00000070u) +#define TIM_OC1M_MASK (0x00000070u) +#define TIM_OC1M_BIT (4) +#define TIM_OC1M_BITS (3) +/* TIM_OC1PE field */ +#define TIM_OC1PE (0x00000008u) +#define TIM_OC1PE_MASK (0x00000008u) +#define TIM_OC1PE_BIT (3) +#define TIM_OC1PE_BITS (1) +/* TIM_OC1FE field */ +#define TIM_OC1FE (0x00000004u) +#define TIM_OC1FE_MASK (0x00000004u) +#define TIM_OC1FE_BIT (2) +#define TIM_OC1FE_BITS (1) +/* TIM_CC1S field */ +#define TIM_CC1S (0x00000003u) +#define TIM_CC1S_MASK (0x00000003u) +#define TIM_CC1S_BIT (0) +#define TIM_CC1S_BITS (2) #define TIM1_CCMR2 *((volatile uint32_t *)0x4000E01Cu) #define TIM1_CCMR2_REG *((volatile uint32_t *)0x4000E01Cu) #define TIM1_CCMR2_ADDR (0x4000E01Cu) #define TIM1_CCMR2_RESET (0x00000000u) - /* TIM_IC4F field */ - #define TIM_IC4F (0x0000F000u) - #define TIM_IC4F_MASK (0x0000F000u) - #define TIM_IC4F_BIT (12) - #define TIM_IC4F_BITS (4) - /* TIM_IC4PSC field */ - #define TIM_IC4PSC (0x00000C00u) - #define TIM_IC4PSC_MASK (0x00000C00u) - #define TIM_IC4PSC_BIT (10) - #define TIM_IC4PSC_BITS (2) - /* TIM_IC3F field */ - #define TIM_IC3F (0x000000F0u) - #define TIM_IC3F_MASK (0x000000F0u) - #define TIM_IC3F_BIT (4) - #define TIM_IC3F_BITS (4) - /* TIM_IC3PSC field */ - #define TIM_IC3PSC (0x0000000Cu) - #define TIM_IC3PSC_MASK (0x0000000Cu) - #define TIM_IC3PSC_BIT (2) - #define TIM_IC3PSC_BITS (2) - /* TIM_OC4CE field */ - #define TIM_OC4CE (0x00008000u) - #define TIM_OC4CE_MASK (0x00008000u) - #define TIM_OC4CE_BIT (15) - #define TIM_OC4CE_BITS (1) - /* TIM_OC4M field */ - #define TIM_OC4M (0x00007000u) - #define TIM_OC4M_MASK (0x00007000u) - #define TIM_OC4M_BIT (12) - #define TIM_OC4M_BITS (3) - /* TIM_OC4BE field */ - #define TIM_OC4BE (0x00000800u) - #define TIM_OC4BE_MASK (0x00000800u) - #define TIM_OC4BE_BIT (11) - #define TIM_OC4BE_BITS (1) - /* TIM_OC4FE field */ - #define TIM_OC4FE (0x00000400u) - #define TIM_OC4FE_MASK (0x00000400u) - #define TIM_OC4FE_BIT (10) - #define TIM_OC4FE_BITS (1) - /* TIM_CC4S field */ - #define TIM_CC4S (0x00000300u) - #define TIM_CC4S_MASK (0x00000300u) - #define TIM_CC4S_BIT (8) - #define TIM_CC4S_BITS (2) - /* TIM_OC3CE field */ - #define TIM_OC3CE (0x00000080u) - #define TIM_OC3CE_MASK (0x00000080u) - #define TIM_OC3CE_BIT (7) - #define TIM_OC3CE_BITS (1) - /* TIM_OC3M field */ - #define TIM_OC3M (0x00000070u) - #define TIM_OC3M_MASK (0x00000070u) - #define TIM_OC3M_BIT (4) - #define TIM_OC3M_BITS (3) - /* TIM_OC3BE field */ - #define TIM_OC3BE (0x00000008u) - #define TIM_OC3BE_MASK (0x00000008u) - #define TIM_OC3BE_BIT (3) - #define TIM_OC3BE_BITS (1) - /* TIM_OC3FE field */ - #define TIM_OC3FE (0x00000004u) - #define TIM_OC3FE_MASK (0x00000004u) - #define TIM_OC3FE_BIT (2) - #define TIM_OC3FE_BITS (1) - /* TIM_CC3S field */ - #define TIM_CC3S (0x00000003u) - #define TIM_CC3S_MASK (0x00000003u) - #define TIM_CC3S_BIT (0) - #define TIM_CC3S_BITS (2) +/* TIM_IC4F field */ +#define TIM_IC4F (0x0000F000u) +#define TIM_IC4F_MASK (0x0000F000u) +#define TIM_IC4F_BIT (12) +#define TIM_IC4F_BITS (4) +/* TIM_IC4PSC field */ +#define TIM_IC4PSC (0x00000C00u) +#define TIM_IC4PSC_MASK (0x00000C00u) +#define TIM_IC4PSC_BIT (10) +#define TIM_IC4PSC_BITS (2) +/* TIM_IC3F field */ +#define TIM_IC3F (0x000000F0u) +#define TIM_IC3F_MASK (0x000000F0u) +#define TIM_IC3F_BIT (4) +#define TIM_IC3F_BITS (4) +/* TIM_IC3PSC field */ +#define TIM_IC3PSC (0x0000000Cu) +#define TIM_IC3PSC_MASK (0x0000000Cu) +#define TIM_IC3PSC_BIT (2) +#define TIM_IC3PSC_BITS (2) +/* TIM_OC4CE field */ +#define TIM_OC4CE (0x00008000u) +#define TIM_OC4CE_MASK (0x00008000u) +#define TIM_OC4CE_BIT (15) +#define TIM_OC4CE_BITS (1) +/* TIM_OC4M field */ +#define TIM_OC4M (0x00007000u) +#define TIM_OC4M_MASK (0x00007000u) +#define TIM_OC4M_BIT (12) +#define TIM_OC4M_BITS (3) +/* TIM_OC4BE field */ +#define TIM_OC4BE (0x00000800u) +#define TIM_OC4BE_MASK (0x00000800u) +#define TIM_OC4BE_BIT (11) +#define TIM_OC4BE_BITS (1) +/* TIM_OC4FE field */ +#define TIM_OC4FE (0x00000400u) +#define TIM_OC4FE_MASK (0x00000400u) +#define TIM_OC4FE_BIT (10) +#define TIM_OC4FE_BITS (1) +/* TIM_CC4S field */ +#define TIM_CC4S (0x00000300u) +#define TIM_CC4S_MASK (0x00000300u) +#define TIM_CC4S_BIT (8) +#define TIM_CC4S_BITS (2) +/* TIM_OC3CE field */ +#define TIM_OC3CE (0x00000080u) +#define TIM_OC3CE_MASK (0x00000080u) +#define TIM_OC3CE_BIT (7) +#define TIM_OC3CE_BITS (1) +/* TIM_OC3M field */ +#define TIM_OC3M (0x00000070u) +#define TIM_OC3M_MASK (0x00000070u) +#define TIM_OC3M_BIT (4) +#define TIM_OC3M_BITS (3) +/* TIM_OC3BE field */ +#define TIM_OC3BE (0x00000008u) +#define TIM_OC3BE_MASK (0x00000008u) +#define TIM_OC3BE_BIT (3) +#define TIM_OC3BE_BITS (1) +/* TIM_OC3FE field */ +#define TIM_OC3FE (0x00000004u) +#define TIM_OC3FE_MASK (0x00000004u) +#define TIM_OC3FE_BIT (2) +#define TIM_OC3FE_BITS (1) +/* TIM_CC3S field */ +#define TIM_CC3S (0x00000003u) +#define TIM_CC3S_MASK (0x00000003u) +#define TIM_CC3S_BIT (0) +#define TIM_CC3S_BITS (2) #define TIM1_CCER *((volatile uint32_t *)0x4000E020u) #define TIM1_CCER_REG *((volatile uint32_t *)0x4000E020u) #define TIM1_CCER_ADDR (0x4000E020u) #define TIM1_CCER_RESET (0x00000000u) - /* TIM_CC4P field */ - #define TIM_CC4P (0x00002000u) - #define TIM_CC4P_MASK (0x00002000u) - #define TIM_CC4P_BIT (13) - #define TIM_CC4P_BITS (1) - /* TIM_CC4E field */ - #define TIM_CC4E (0x00001000u) - #define TIM_CC4E_MASK (0x00001000u) - #define TIM_CC4E_BIT (12) - #define TIM_CC4E_BITS (1) - /* TIM_CC3P field */ - #define TIM_CC3P (0x00000200u) - #define TIM_CC3P_MASK (0x00000200u) - #define TIM_CC3P_BIT (9) - #define TIM_CC3P_BITS (1) - /* TIM_CC3E field */ - #define TIM_CC3E (0x00000100u) - #define TIM_CC3E_MASK (0x00000100u) - #define TIM_CC3E_BIT (8) - #define TIM_CC3E_BITS (1) - /* TIM_CC2P field */ - #define TIM_CC2P (0x00000020u) - #define TIM_CC2P_MASK (0x00000020u) - #define TIM_CC2P_BIT (5) - #define TIM_CC2P_BITS (1) - /* TIM_CC2E field */ - #define TIM_CC2E (0x00000010u) - #define TIM_CC2E_MASK (0x00000010u) - #define TIM_CC2E_BIT (4) - #define TIM_CC2E_BITS (1) - /* TIM_CC1P field */ - #define TIM_CC1P (0x00000002u) - #define TIM_CC1P_MASK (0x00000002u) - #define TIM_CC1P_BIT (1) - #define TIM_CC1P_BITS (1) - /* TIM_CC1E field */ - #define TIM_CC1E (0x00000001u) - #define TIM_CC1E_MASK (0x00000001u) - #define TIM_CC1E_BIT (0) - #define TIM_CC1E_BITS (1) +/* TIM_CC4P field */ +#define TIM_CC4P (0x00002000u) +#define TIM_CC4P_MASK (0x00002000u) +#define TIM_CC4P_BIT (13) +#define TIM_CC4P_BITS (1) +/* TIM_CC4E field */ +#define TIM_CC4E (0x00001000u) +#define TIM_CC4E_MASK (0x00001000u) +#define TIM_CC4E_BIT (12) +#define TIM_CC4E_BITS (1) +/* TIM_CC3P field */ +#define TIM_CC3P (0x00000200u) +#define TIM_CC3P_MASK (0x00000200u) +#define TIM_CC3P_BIT (9) +#define TIM_CC3P_BITS (1) +/* TIM_CC3E field */ +#define TIM_CC3E (0x00000100u) +#define TIM_CC3E_MASK (0x00000100u) +#define TIM_CC3E_BIT (8) +#define TIM_CC3E_BITS (1) +/* TIM_CC2P field */ +#define TIM_CC2P (0x00000020u) +#define TIM_CC2P_MASK (0x00000020u) +#define TIM_CC2P_BIT (5) +#define TIM_CC2P_BITS (1) +/* TIM_CC2E field */ +#define TIM_CC2E (0x00000010u) +#define TIM_CC2E_MASK (0x00000010u) +#define TIM_CC2E_BIT (4) +#define TIM_CC2E_BITS (1) +/* TIM_CC1P field */ +#define TIM_CC1P (0x00000002u) +#define TIM_CC1P_MASK (0x00000002u) +#define TIM_CC1P_BIT (1) +#define TIM_CC1P_BITS (1) +/* TIM_CC1E field */ +#define TIM_CC1E (0x00000001u) +#define TIM_CC1E_MASK (0x00000001u) +#define TIM_CC1E_BIT (0) +#define TIM_CC1E_BITS (1) #define TIM1_CNT *((volatile uint32_t *)0x4000E024u) #define TIM1_CNT_REG *((volatile uint32_t *)0x4000E024u) #define TIM1_CNT_ADDR (0x4000E024u) #define TIM1_CNT_RESET (0x00000000u) - /* TIM_CNT field */ - #define TIM_CNT (0x0000FFFFu) - #define TIM_CNT_MASK (0x0000FFFFu) - #define TIM_CNT_BIT (0) - #define TIM_CNT_BITS (16) +/* TIM_CNT field */ +#define TIM_CNT (0x0000FFFFu) +#define TIM_CNT_MASK (0x0000FFFFu) +#define TIM_CNT_BIT (0) +#define TIM_CNT_BITS (16) #define TIM1_PSC *((volatile uint32_t *)0x4000E028u) #define TIM1_PSC_REG *((volatile uint32_t *)0x4000E028u) #define TIM1_PSC_ADDR (0x4000E028u) #define TIM1_PSC_RESET (0x00000000u) - /* TIM_PSC field */ - #define TIM_PSC (0x0000000Fu) - #define TIM_PSC_MASK (0x0000000Fu) - #define TIM_PSC_BIT (0) - #define TIM_PSC_BITS (4) +/* TIM_PSC field */ +#define TIM_PSC (0x0000000Fu) +#define TIM_PSC_MASK (0x0000000Fu) +#define TIM_PSC_BIT (0) +#define TIM_PSC_BITS (4) #define TIM1_ARR *((volatile uint32_t *)0x4000E02Cu) #define TIM1_ARR_REG *((volatile uint32_t *)0x4000E02Cu) #define TIM1_ARR_ADDR (0x4000E02Cu) #define TIM1_ARR_RESET (0x0000FFFFu) - /* TIM_ARR field */ - #define TIM_ARR (0x0000FFFFu) - #define TIM_ARR_MASK (0x0000FFFFu) - #define TIM_ARR_BIT (0) - #define TIM_ARR_BITS (16) +/* TIM_ARR field */ +#define TIM_ARR (0x0000FFFFu) +#define TIM_ARR_MASK (0x0000FFFFu) +#define TIM_ARR_BIT (0) +#define TIM_ARR_BITS (16) #define TIM1_CCR1 *((volatile uint32_t *)0x4000E034u) #define TIM1_CCR1_REG *((volatile uint32_t *)0x4000E034u) #define TIM1_CCR1_ADDR (0x4000E034u) #define TIM1_CCR1_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM1_CCR2 *((volatile uint32_t *)0x4000E038u) #define TIM1_CCR2_REG *((volatile uint32_t *)0x4000E038u) #define TIM1_CCR2_ADDR (0x4000E038u) #define TIM1_CCR2_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM1_CCR3 *((volatile uint32_t *)0x4000E03Cu) #define TIM1_CCR3_REG *((volatile uint32_t *)0x4000E03Cu) #define TIM1_CCR3_ADDR (0x4000E03Cu) #define TIM1_CCR3_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM1_CCR4 *((volatile uint32_t *)0x4000E040u) #define TIM1_CCR4_REG *((volatile uint32_t *)0x4000E040u) #define TIM1_CCR4_ADDR (0x4000E040u) #define TIM1_CCR4_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM1_OR *((volatile uint32_t *)0x4000E050u) #define TIM1_OR_REG *((volatile uint32_t *)0x4000E050u) #define TIM1_OR_ADDR (0x4000E050u) #define TIM1_OR_RESET (0x00000000u) - /* TIM_ORRSVD field */ - #define TIM_ORRSVD (0x00000008u) - #define TIM_ORRSVD_MASK (0x00000008u) - #define TIM_ORRSVD_BIT (3) - #define TIM_ORRSVD_BITS (1) - /* TIM_CLKMSKEN field */ - #define TIM_CLKMSKEN (0x00000004u) - #define TIM_CLKMSKEN_MASK (0x00000004u) - #define TIM_CLKMSKEN_BIT (2) - #define TIM_CLKMSKEN_BITS (1) - /* TIM1_EXTRIGSEL field */ - #define TIM1_EXTRIGSEL (0x00000003u) - #define TIM1_EXTRIGSEL_MASK (0x00000003u) - #define TIM1_EXTRIGSEL_BIT (0) - #define TIM1_EXTRIGSEL_BITS (2) +/* TIM_ORRSVD field */ +#define TIM_ORRSVD (0x00000008u) +#define TIM_ORRSVD_MASK (0x00000008u) +#define TIM_ORRSVD_BIT (3) +#define TIM_ORRSVD_BITS (1) +/* TIM_CLKMSKEN field */ +#define TIM_CLKMSKEN (0x00000004u) +#define TIM_CLKMSKEN_MASK (0x00000004u) +#define TIM_CLKMSKEN_BIT (2) +#define TIM_CLKMSKEN_BITS (1) +/* TIM1_EXTRIGSEL field */ +#define TIM1_EXTRIGSEL (0x00000003u) +#define TIM1_EXTRIGSEL_MASK (0x00000003u) +#define TIM1_EXTRIGSEL_BIT (0) +#define TIM1_EXTRIGSEL_BITS (2) /* TIM2 block */ #define BLOCK_TIM2_BASE (0x4000F000u) @@ -7174,526 +7174,526 @@ #define TIM2_CR1_REG *((volatile uint32_t *)0x4000F000u) #define TIM2_CR1_ADDR (0x4000F000u) #define TIM2_CR1_RESET (0x00000000u) - /* TIM_ARBE field */ - #define TIM_ARBE (0x00000080u) - #define TIM_ARBE_MASK (0x00000080u) - #define TIM_ARBE_BIT (7) - #define TIM_ARBE_BITS (1) - /* TIM_CMS field */ - #define TIM_CMS (0x00000060u) - #define TIM_CMS_MASK (0x00000060u) - #define TIM_CMS_BIT (5) - #define TIM_CMS_BITS (2) - /* TIM_DIR field */ - #define TIM_DIR (0x00000010u) - #define TIM_DIR_MASK (0x00000010u) - #define TIM_DIR_BIT (4) - #define TIM_DIR_BITS (1) - /* TIM_OPM field */ - #define TIM_OPM (0x00000008u) - #define TIM_OPM_MASK (0x00000008u) - #define TIM_OPM_BIT (3) - #define TIM_OPM_BITS (1) - /* TIM_URS field */ - #define TIM_URS (0x00000004u) - #define TIM_URS_MASK (0x00000004u) - #define TIM_URS_BIT (2) - #define TIM_URS_BITS (1) - /* TIM_UDIS field */ - #define TIM_UDIS (0x00000002u) - #define TIM_UDIS_MASK (0x00000002u) - #define TIM_UDIS_BIT (1) - #define TIM_UDIS_BITS (1) - /* TIM_CEN field */ - #define TIM_CEN (0x00000001u) - #define TIM_CEN_MASK (0x00000001u) - #define TIM_CEN_BIT (0) - #define TIM_CEN_BITS (1) +/* TIM_ARBE field */ +#define TIM_ARBE (0x00000080u) +#define TIM_ARBE_MASK (0x00000080u) +#define TIM_ARBE_BIT (7) +#define TIM_ARBE_BITS (1) +/* TIM_CMS field */ +#define TIM_CMS (0x00000060u) +#define TIM_CMS_MASK (0x00000060u) +#define TIM_CMS_BIT (5) +#define TIM_CMS_BITS (2) +/* TIM_DIR field */ +#define TIM_DIR (0x00000010u) +#define TIM_DIR_MASK (0x00000010u) +#define TIM_DIR_BIT (4) +#define TIM_DIR_BITS (1) +/* TIM_OPM field */ +#define TIM_OPM (0x00000008u) +#define TIM_OPM_MASK (0x00000008u) +#define TIM_OPM_BIT (3) +#define TIM_OPM_BITS (1) +/* TIM_URS field */ +#define TIM_URS (0x00000004u) +#define TIM_URS_MASK (0x00000004u) +#define TIM_URS_BIT (2) +#define TIM_URS_BITS (1) +/* TIM_UDIS field */ +#define TIM_UDIS (0x00000002u) +#define TIM_UDIS_MASK (0x00000002u) +#define TIM_UDIS_BIT (1) +#define TIM_UDIS_BITS (1) +/* TIM_CEN field */ +#define TIM_CEN (0x00000001u) +#define TIM_CEN_MASK (0x00000001u) +#define TIM_CEN_BIT (0) +#define TIM_CEN_BITS (1) #define TIM2_CR2 *((volatile uint32_t *)0x4000F004u) #define TIM2_CR2_REG *((volatile uint32_t *)0x4000F004u) #define TIM2_CR2_ADDR (0x4000F004u) #define TIM2_CR2_RESET (0x00000000u) - /* TIM_TI1S field */ - #define TIM_TI1S (0x00000080u) - #define TIM_TI1S_MASK (0x00000080u) - #define TIM_TI1S_BIT (7) - #define TIM_TI1S_BITS (1) - /* TIM_MMS field */ - #define TIM_MMS (0x00000070u) - #define TIM_MMS_MASK (0x00000070u) - #define TIM_MMS_BIT (4) - #define TIM_MMS_BITS (3) +/* TIM_TI1S field */ +#define TIM_TI1S (0x00000080u) +#define TIM_TI1S_MASK (0x00000080u) +#define TIM_TI1S_BIT (7) +#define TIM_TI1S_BITS (1) +/* TIM_MMS field */ +#define TIM_MMS (0x00000070u) +#define TIM_MMS_MASK (0x00000070u) +#define TIM_MMS_BIT (4) +#define TIM_MMS_BITS (3) #define TIM2_SMCR *((volatile uint32_t *)0x4000F008u) #define TIM2_SMCR_REG *((volatile uint32_t *)0x4000F008u) #define TIM2_SMCR_ADDR (0x4000F008u) #define TIM2_SMCR_RESET (0x00000000u) - /* TIM_ETP field */ - #define TIM_ETP (0x00008000u) - #define TIM_ETP_MASK (0x00008000u) - #define TIM_ETP_BIT (15) - #define TIM_ETP_BITS (1) - /* TIM_ECE field */ - #define TIM_ECE (0x00004000u) - #define TIM_ECE_MASK (0x00004000u) - #define TIM_ECE_BIT (14) - #define TIM_ECE_BITS (1) - /* TIM_ETPS field */ - #define TIM_ETPS (0x00003000u) - #define TIM_ETPS_MASK (0x00003000u) - #define TIM_ETPS_BIT (12) - #define TIM_ETPS_BITS (2) - /* TIM_ETF field */ - #define TIM_ETF (0x00000F00u) - #define TIM_ETF_MASK (0x00000F00u) - #define TIM_ETF_BIT (8) - #define TIM_ETF_BITS (4) - /* TIM_MSM field */ - #define TIM_MSM (0x00000080u) - #define TIM_MSM_MASK (0x00000080u) - #define TIM_MSM_BIT (7) - #define TIM_MSM_BITS (1) - /* TIM_TS field */ - #define TIM_TS (0x00000070u) - #define TIM_TS_MASK (0x00000070u) - #define TIM_TS_BIT (4) - #define TIM_TS_BITS (3) - /* TIM_SMS field */ - #define TIM_SMS (0x00000007u) - #define TIM_SMS_MASK (0x00000007u) - #define TIM_SMS_BIT (0) - #define TIM_SMS_BITS (3) +/* TIM_ETP field */ +#define TIM_ETP (0x00008000u) +#define TIM_ETP_MASK (0x00008000u) +#define TIM_ETP_BIT (15) +#define TIM_ETP_BITS (1) +/* TIM_ECE field */ +#define TIM_ECE (0x00004000u) +#define TIM_ECE_MASK (0x00004000u) +#define TIM_ECE_BIT (14) +#define TIM_ECE_BITS (1) +/* TIM_ETPS field */ +#define TIM_ETPS (0x00003000u) +#define TIM_ETPS_MASK (0x00003000u) +#define TIM_ETPS_BIT (12) +#define TIM_ETPS_BITS (2) +/* TIM_ETF field */ +#define TIM_ETF (0x00000F00u) +#define TIM_ETF_MASK (0x00000F00u) +#define TIM_ETF_BIT (8) +#define TIM_ETF_BITS (4) +/* TIM_MSM field */ +#define TIM_MSM (0x00000080u) +#define TIM_MSM_MASK (0x00000080u) +#define TIM_MSM_BIT (7) +#define TIM_MSM_BITS (1) +/* TIM_TS field */ +#define TIM_TS (0x00000070u) +#define TIM_TS_MASK (0x00000070u) +#define TIM_TS_BIT (4) +#define TIM_TS_BITS (3) +/* TIM_SMS field */ +#define TIM_SMS (0x00000007u) +#define TIM_SMS_MASK (0x00000007u) +#define TIM_SMS_BIT (0) +#define TIM_SMS_BITS (3) #define TMR2_DIER *((volatile uint32_t *)0x4000F00Cu) #define TMR2_DIER_REG *((volatile uint32_t *)0x4000F00Cu) #define TMR2_DIER_ADDR (0x4000F00Cu) #define TMR2_DIER_RESET (0x00000000u) - /* TIE field */ - #define TMR2_DIER_TIE (0x00000040u) - #define TMR2_DIER_TIE_MASK (0x00000040u) - #define TMR2_DIER_TIE_BIT (6) - #define TMR2_DIER_TIE_BITS (1) - /* CC4IE field */ - #define TMR2_DIER_CC4IE (0x00000010u) - #define TMR2_DIER_CC4IE_MASK (0x00000010u) - #define TMR2_DIER_CC4IE_BIT (4) - #define TMR2_DIER_CC4IE_BITS (1) - /* CC3IE field */ - #define TMR2_DIER_CC3IE (0x00000008u) - #define TMR2_DIER_CC3IE_MASK (0x00000008u) - #define TMR2_DIER_CC3IE_BIT (3) - #define TMR2_DIER_CC3IE_BITS (1) - /* CC2IE field */ - #define TMR2_DIER_CC2IE (0x00000004u) - #define TMR2_DIER_CC2IE_MASK (0x00000004u) - #define TMR2_DIER_CC2IE_BIT (2) - #define TMR2_DIER_CC2IE_BITS (1) - /* CC1IE field */ - #define TMR2_DIER_CC1IE (0x00000002u) - #define TMR2_DIER_CC1IE_MASK (0x00000002u) - #define TMR2_DIER_CC1IE_BIT (1) - #define TMR2_DIER_CC1IE_BITS (1) - /* UIE field */ - #define TMR2_DIER_UIE (0x00000001u) - #define TMR2_DIER_UIE_MASK (0x00000001u) - #define TMR2_DIER_UIE_BIT (0) - #define TMR2_DIER_UIE_BITS (1) +/* TIE field */ +#define TMR2_DIER_TIE (0x00000040u) +#define TMR2_DIER_TIE_MASK (0x00000040u) +#define TMR2_DIER_TIE_BIT (6) +#define TMR2_DIER_TIE_BITS (1) +/* CC4IE field */ +#define TMR2_DIER_CC4IE (0x00000010u) +#define TMR2_DIER_CC4IE_MASK (0x00000010u) +#define TMR2_DIER_CC4IE_BIT (4) +#define TMR2_DIER_CC4IE_BITS (1) +/* CC3IE field */ +#define TMR2_DIER_CC3IE (0x00000008u) +#define TMR2_DIER_CC3IE_MASK (0x00000008u) +#define TMR2_DIER_CC3IE_BIT (3) +#define TMR2_DIER_CC3IE_BITS (1) +/* CC2IE field */ +#define TMR2_DIER_CC2IE (0x00000004u) +#define TMR2_DIER_CC2IE_MASK (0x00000004u) +#define TMR2_DIER_CC2IE_BIT (2) +#define TMR2_DIER_CC2IE_BITS (1) +/* CC1IE field */ +#define TMR2_DIER_CC1IE (0x00000002u) +#define TMR2_DIER_CC1IE_MASK (0x00000002u) +#define TMR2_DIER_CC1IE_BIT (1) +#define TMR2_DIER_CC1IE_BITS (1) +/* UIE field */ +#define TMR2_DIER_UIE (0x00000001u) +#define TMR2_DIER_UIE_MASK (0x00000001u) +#define TMR2_DIER_UIE_BIT (0) +#define TMR2_DIER_UIE_BITS (1) #define TMR2_SR *((volatile uint32_t *)0x4000F010u) #define TMR2_SR_REG *((volatile uint32_t *)0x4000F010u) #define TMR2_SR_ADDR (0x4000F010u) #define TMR2_SR_RESET (0x00000000u) - /* CC4OF field */ - #define TMR2_SR_CC4OF (0x00001000u) - #define TMR2_SR_CC4OF_MASK (0x00001000u) - #define TMR2_SR_CC4OF_BIT (12) - #define TMR2_SR_CC4OF_BITS (1) - /* CC3OF field */ - #define TMR2_SR_CC3OF (0x00000800u) - #define TMR2_SR_CC3OF_MASK (0x00000800u) - #define TMR2_SR_CC3OF_BIT (11) - #define TMR2_SR_CC3OF_BITS (1) - /* CC2OF field */ - #define TMR2_SR_CC2OF (0x00000400u) - #define TMR2_SR_CC2OF_MASK (0x00000400u) - #define TMR2_SR_CC2OF_BIT (10) - #define TMR2_SR_CC2OF_BITS (1) - /* CC1OF field */ - #define TMR2_SR_CC1OF (0x00000200u) - #define TMR2_SR_CC1OF_MASK (0x00000200u) - #define TMR2_SR_CC1OF_BIT (9) - #define TMR2_SR_CC1OF_BITS (1) - /* TIF field */ - #define TMR2_SR_TIF (0x00000040u) - #define TMR2_SR_TIF_MASK (0x00000040u) - #define TMR2_SR_TIF_BIT (6) - #define TMR2_SR_TIF_BITS (1) - /* CC4IF field */ - #define TMR2_SR_CC4IF (0x00000010u) - #define TMR2_SR_CC4IF_MASK (0x00000010u) - #define TMR2_SR_CC4IF_BIT (4) - #define TMR2_SR_CC4IF_BITS (1) - /* CC3IF field */ - #define TMR2_SR_CC3IF (0x00000008u) - #define TMR2_SR_CC3IF_MASK (0x00000008u) - #define TMR2_SR_CC3IF_BIT (3) - #define TMR2_SR_CC3IF_BITS (1) - /* CC2IF field */ - #define TMR2_SR_CC2IF (0x00000004u) - #define TMR2_SR_CC2IF_MASK (0x00000004u) - #define TMR2_SR_CC2IF_BIT (2) - #define TMR2_SR_CC2IF_BITS (1) - /* CC1IF field */ - #define TMR2_SR_CC1IF (0x00000002u) - #define TMR2_SR_CC1IF_MASK (0x00000002u) - #define TMR2_SR_CC1IF_BIT (1) - #define TMR2_SR_CC1IF_BITS (1) - /* UIF field */ - #define TMR2_SR_UIF (0x00000001u) - #define TMR2_SR_UIF_MASK (0x00000001u) - #define TMR2_SR_UIF_BIT (0) - #define TMR2_SR_UIF_BITS (1) +/* CC4OF field */ +#define TMR2_SR_CC4OF (0x00001000u) +#define TMR2_SR_CC4OF_MASK (0x00001000u) +#define TMR2_SR_CC4OF_BIT (12) +#define TMR2_SR_CC4OF_BITS (1) +/* CC3OF field */ +#define TMR2_SR_CC3OF (0x00000800u) +#define TMR2_SR_CC3OF_MASK (0x00000800u) +#define TMR2_SR_CC3OF_BIT (11) +#define TMR2_SR_CC3OF_BITS (1) +/* CC2OF field */ +#define TMR2_SR_CC2OF (0x00000400u) +#define TMR2_SR_CC2OF_MASK (0x00000400u) +#define TMR2_SR_CC2OF_BIT (10) +#define TMR2_SR_CC2OF_BITS (1) +/* CC1OF field */ +#define TMR2_SR_CC1OF (0x00000200u) +#define TMR2_SR_CC1OF_MASK (0x00000200u) +#define TMR2_SR_CC1OF_BIT (9) +#define TMR2_SR_CC1OF_BITS (1) +/* TIF field */ +#define TMR2_SR_TIF (0x00000040u) +#define TMR2_SR_TIF_MASK (0x00000040u) +#define TMR2_SR_TIF_BIT (6) +#define TMR2_SR_TIF_BITS (1) +/* CC4IF field */ +#define TMR2_SR_CC4IF (0x00000010u) +#define TMR2_SR_CC4IF_MASK (0x00000010u) +#define TMR2_SR_CC4IF_BIT (4) +#define TMR2_SR_CC4IF_BITS (1) +/* CC3IF field */ +#define TMR2_SR_CC3IF (0x00000008u) +#define TMR2_SR_CC3IF_MASK (0x00000008u) +#define TMR2_SR_CC3IF_BIT (3) +#define TMR2_SR_CC3IF_BITS (1) +/* CC2IF field */ +#define TMR2_SR_CC2IF (0x00000004u) +#define TMR2_SR_CC2IF_MASK (0x00000004u) +#define TMR2_SR_CC2IF_BIT (2) +#define TMR2_SR_CC2IF_BITS (1) +/* CC1IF field */ +#define TMR2_SR_CC1IF (0x00000002u) +#define TMR2_SR_CC1IF_MASK (0x00000002u) +#define TMR2_SR_CC1IF_BIT (1) +#define TMR2_SR_CC1IF_BITS (1) +/* UIF field */ +#define TMR2_SR_UIF (0x00000001u) +#define TMR2_SR_UIF_MASK (0x00000001u) +#define TMR2_SR_UIF_BIT (0) +#define TMR2_SR_UIF_BITS (1) #define TIM2_EGR *((volatile uint32_t *)0x4000F014u) #define TIM2_EGR_REG *((volatile uint32_t *)0x4000F014u) #define TIM2_EGR_ADDR (0x4000F014u) #define TIM2_EGR_RESET (0x00000000u) - /* TIM_TG field */ - #define TIM_TG (0x00000040u) - #define TIM_TG_MASK (0x00000040u) - #define TIM_TG_BIT (6) - #define TIM_TG_BITS (1) - /* TIM_CC4G field */ - #define TIM_CC4G (0x00000010u) - #define TIM_CC4G_MASK (0x00000010u) - #define TIM_CC4G_BIT (4) - #define TIM_CC4G_BITS (1) - /* TIM_CC3G field */ - #define TIM_CC3G (0x00000008u) - #define TIM_CC3G_MASK (0x00000008u) - #define TIM_CC3G_BIT (3) - #define TIM_CC3G_BITS (1) - /* TIM_CC2G field */ - #define TIM_CC2G (0x00000004u) - #define TIM_CC2G_MASK (0x00000004u) - #define TIM_CC2G_BIT (2) - #define TIM_CC2G_BITS (1) - /* TIM_CC1G field */ - #define TIM_CC1G (0x00000002u) - #define TIM_CC1G_MASK (0x00000002u) - #define TIM_CC1G_BIT (1) - #define TIM_CC1G_BITS (1) - /* TIM_UG field */ - #define TIM_UG (0x00000001u) - #define TIM_UG_MASK (0x00000001u) - #define TIM_UG_BIT (0) - #define TIM_UG_BITS (1) +/* TIM_TG field */ +#define TIM_TG (0x00000040u) +#define TIM_TG_MASK (0x00000040u) +#define TIM_TG_BIT (6) +#define TIM_TG_BITS (1) +/* TIM_CC4G field */ +#define TIM_CC4G (0x00000010u) +#define TIM_CC4G_MASK (0x00000010u) +#define TIM_CC4G_BIT (4) +#define TIM_CC4G_BITS (1) +/* TIM_CC3G field */ +#define TIM_CC3G (0x00000008u) +#define TIM_CC3G_MASK (0x00000008u) +#define TIM_CC3G_BIT (3) +#define TIM_CC3G_BITS (1) +/* TIM_CC2G field */ +#define TIM_CC2G (0x00000004u) +#define TIM_CC2G_MASK (0x00000004u) +#define TIM_CC2G_BIT (2) +#define TIM_CC2G_BITS (1) +/* TIM_CC1G field */ +#define TIM_CC1G (0x00000002u) +#define TIM_CC1G_MASK (0x00000002u) +#define TIM_CC1G_BIT (1) +#define TIM_CC1G_BITS (1) +/* TIM_UG field */ +#define TIM_UG (0x00000001u) +#define TIM_UG_MASK (0x00000001u) +#define TIM_UG_BIT (0) +#define TIM_UG_BITS (1) #define TIM2_CCMR1 *((volatile uint32_t *)0x4000F018u) #define TIM2_CCMR1_REG *((volatile uint32_t *)0x4000F018u) #define TIM2_CCMR1_ADDR (0x4000F018u) #define TIM2_CCMR1_RESET (0x00000000u) - /* TIM_IC2F field */ - #define TIM_IC2F (0x0000F000u) - #define TIM_IC2F_MASK (0x0000F000u) - #define TIM_IC2F_BIT (12) - #define TIM_IC2F_BITS (4) - /* TIM_IC2PSC field */ - #define TIM_IC2PSC (0x00000C00u) - #define TIM_IC2PSC_MASK (0x00000C00u) - #define TIM_IC2PSC_BIT (10) - #define TIM_IC2PSC_BITS (2) - /* TIM_IC1F field */ - #define TIM_IC1F (0x000000F0u) - #define TIM_IC1F_MASK (0x000000F0u) - #define TIM_IC1F_BIT (4) - #define TIM_IC1F_BITS (4) - /* TIM_IC1PSC field */ - #define TIM_IC1PSC (0x0000000Cu) - #define TIM_IC1PSC_MASK (0x0000000Cu) - #define TIM_IC1PSC_BIT (2) - #define TIM_IC1PSC_BITS (2) - /* TIM_OC2CE field */ - #define TIM_OC2CE (0x00008000u) - #define TIM_OC2CE_MASK (0x00008000u) - #define TIM_OC2CE_BIT (15) - #define TIM_OC2CE_BITS (1) - /* TIM_OC2M field */ - #define TIM_OC2M (0x00007000u) - #define TIM_OC2M_MASK (0x00007000u) - #define TIM_OC2M_BIT (12) - #define TIM_OC2M_BITS (3) - /* TIM_OC2BE field */ - #define TIM_OC2BE (0x00000800u) - #define TIM_OC2BE_MASK (0x00000800u) - #define TIM_OC2BE_BIT (11) - #define TIM_OC2BE_BITS (1) - /* TIM_OC2FE field */ - #define TIM_OC2FE (0x00000400u) - #define TIM_OC2FE_MASK (0x00000400u) - #define TIM_OC2FE_BIT (10) - #define TIM_OC2FE_BITS (1) - /* TIM_CC2S field */ - #define TIM_CC2S (0x00000300u) - #define TIM_CC2S_MASK (0x00000300u) - #define TIM_CC2S_BIT (8) - #define TIM_CC2S_BITS (2) - /* TIM_OC1CE field */ - #define TIM_OC1CE (0x00000080u) - #define TIM_OC1CE_MASK (0x00000080u) - #define TIM_OC1CE_BIT (7) - #define TIM_OC1CE_BITS (1) - /* TIM_OC1M field */ - #define TIM_OC1M (0x00000070u) - #define TIM_OC1M_MASK (0x00000070u) - #define TIM_OC1M_BIT (4) - #define TIM_OC1M_BITS (3) - /* TIM_OC1PE field */ - #define TIM_OC1PE (0x00000008u) - #define TIM_OC1PE_MASK (0x00000008u) - #define TIM_OC1PE_BIT (3) - #define TIM_OC1PE_BITS (1) - /* TIM_OC1FE field */ - #define TIM_OC1FE (0x00000004u) - #define TIM_OC1FE_MASK (0x00000004u) - #define TIM_OC1FE_BIT (2) - #define TIM_OC1FE_BITS (1) - /* TIM_CC1S field */ - #define TIM_CC1S (0x00000003u) - #define TIM_CC1S_MASK (0x00000003u) - #define TIM_CC1S_BIT (0) - #define TIM_CC1S_BITS (2) +/* TIM_IC2F field */ +#define TIM_IC2F (0x0000F000u) +#define TIM_IC2F_MASK (0x0000F000u) +#define TIM_IC2F_BIT (12) +#define TIM_IC2F_BITS (4) +/* TIM_IC2PSC field */ +#define TIM_IC2PSC (0x00000C00u) +#define TIM_IC2PSC_MASK (0x00000C00u) +#define TIM_IC2PSC_BIT (10) +#define TIM_IC2PSC_BITS (2) +/* TIM_IC1F field */ +#define TIM_IC1F (0x000000F0u) +#define TIM_IC1F_MASK (0x000000F0u) +#define TIM_IC1F_BIT (4) +#define TIM_IC1F_BITS (4) +/* TIM_IC1PSC field */ +#define TIM_IC1PSC (0x0000000Cu) +#define TIM_IC1PSC_MASK (0x0000000Cu) +#define TIM_IC1PSC_BIT (2) +#define TIM_IC1PSC_BITS (2) +/* TIM_OC2CE field */ +#define TIM_OC2CE (0x00008000u) +#define TIM_OC2CE_MASK (0x00008000u) +#define TIM_OC2CE_BIT (15) +#define TIM_OC2CE_BITS (1) +/* TIM_OC2M field */ +#define TIM_OC2M (0x00007000u) +#define TIM_OC2M_MASK (0x00007000u) +#define TIM_OC2M_BIT (12) +#define TIM_OC2M_BITS (3) +/* TIM_OC2BE field */ +#define TIM_OC2BE (0x00000800u) +#define TIM_OC2BE_MASK (0x00000800u) +#define TIM_OC2BE_BIT (11) +#define TIM_OC2BE_BITS (1) +/* TIM_OC2FE field */ +#define TIM_OC2FE (0x00000400u) +#define TIM_OC2FE_MASK (0x00000400u) +#define TIM_OC2FE_BIT (10) +#define TIM_OC2FE_BITS (1) +/* TIM_CC2S field */ +#define TIM_CC2S (0x00000300u) +#define TIM_CC2S_MASK (0x00000300u) +#define TIM_CC2S_BIT (8) +#define TIM_CC2S_BITS (2) +/* TIM_OC1CE field */ +#define TIM_OC1CE (0x00000080u) +#define TIM_OC1CE_MASK (0x00000080u) +#define TIM_OC1CE_BIT (7) +#define TIM_OC1CE_BITS (1) +/* TIM_OC1M field */ +#define TIM_OC1M (0x00000070u) +#define TIM_OC1M_MASK (0x00000070u) +#define TIM_OC1M_BIT (4) +#define TIM_OC1M_BITS (3) +/* TIM_OC1PE field */ +#define TIM_OC1PE (0x00000008u) +#define TIM_OC1PE_MASK (0x00000008u) +#define TIM_OC1PE_BIT (3) +#define TIM_OC1PE_BITS (1) +/* TIM_OC1FE field */ +#define TIM_OC1FE (0x00000004u) +#define TIM_OC1FE_MASK (0x00000004u) +#define TIM_OC1FE_BIT (2) +#define TIM_OC1FE_BITS (1) +/* TIM_CC1S field */ +#define TIM_CC1S (0x00000003u) +#define TIM_CC1S_MASK (0x00000003u) +#define TIM_CC1S_BIT (0) +#define TIM_CC1S_BITS (2) #define TIM2_CCMR2 *((volatile uint32_t *)0x4000F01Cu) #define TIM2_CCMR2_REG *((volatile uint32_t *)0x4000F01Cu) #define TIM2_CCMR2_ADDR (0x4000F01Cu) #define TIM2_CCMR2_RESET (0x00000000u) - /* TIM_IC4F field */ - #define TIM_IC4F (0x0000F000u) - #define TIM_IC4F_MASK (0x0000F000u) - #define TIM_IC4F_BIT (12) - #define TIM_IC4F_BITS (4) - /* TIM_IC4PSC field */ - #define TIM_IC4PSC (0x00000C00u) - #define TIM_IC4PSC_MASK (0x00000C00u) - #define TIM_IC4PSC_BIT (10) - #define TIM_IC4PSC_BITS (2) - /* TIM_IC3F field */ - #define TIM_IC3F (0x000000F0u) - #define TIM_IC3F_MASK (0x000000F0u) - #define TIM_IC3F_BIT (4) - #define TIM_IC3F_BITS (4) - /* TIM_IC3PSC field */ - #define TIM_IC3PSC (0x0000000Cu) - #define TIM_IC3PSC_MASK (0x0000000Cu) - #define TIM_IC3PSC_BIT (2) - #define TIM_IC3PSC_BITS (2) - /* TIM_OC4CE field */ - #define TIM_OC4CE (0x00008000u) - #define TIM_OC4CE_MASK (0x00008000u) - #define TIM_OC4CE_BIT (15) - #define TIM_OC4CE_BITS (1) - /* TIM_OC4M field */ - #define TIM_OC4M (0x00007000u) - #define TIM_OC4M_MASK (0x00007000u) - #define TIM_OC4M_BIT (12) - #define TIM_OC4M_BITS (3) - /* TIM_OC4BE field */ - #define TIM_OC4BE (0x00000800u) - #define TIM_OC4BE_MASK (0x00000800u) - #define TIM_OC4BE_BIT (11) - #define TIM_OC4BE_BITS (1) - /* TIM_OC4FE field */ - #define TIM_OC4FE (0x00000400u) - #define TIM_OC4FE_MASK (0x00000400u) - #define TIM_OC4FE_BIT (10) - #define TIM_OC4FE_BITS (1) - /* TIM_CC4S field */ - #define TIM_CC4S (0x00000300u) - #define TIM_CC4S_MASK (0x00000300u) - #define TIM_CC4S_BIT (8) - #define TIM_CC4S_BITS (2) - /* TIM_OC3CE field */ - #define TIM_OC3CE (0x00000080u) - #define TIM_OC3CE_MASK (0x00000080u) - #define TIM_OC3CE_BIT (7) - #define TIM_OC3CE_BITS (1) - /* TIM_OC3M field */ - #define TIM_OC3M (0x00000070u) - #define TIM_OC3M_MASK (0x00000070u) - #define TIM_OC3M_BIT (4) - #define TIM_OC3M_BITS (3) - /* TIM_OC3BE field */ - #define TIM_OC3BE (0x00000008u) - #define TIM_OC3BE_MASK (0x00000008u) - #define TIM_OC3BE_BIT (3) - #define TIM_OC3BE_BITS (1) - /* TIM_OC3FE field */ - #define TIM_OC3FE (0x00000004u) - #define TIM_OC3FE_MASK (0x00000004u) - #define TIM_OC3FE_BIT (2) - #define TIM_OC3FE_BITS (1) - /* TIM_CC3S field */ - #define TIM_CC3S (0x00000003u) - #define TIM_CC3S_MASK (0x00000003u) - #define TIM_CC3S_BIT (0) - #define TIM_CC3S_BITS (2) +/* TIM_IC4F field */ +#define TIM_IC4F (0x0000F000u) +#define TIM_IC4F_MASK (0x0000F000u) +#define TIM_IC4F_BIT (12) +#define TIM_IC4F_BITS (4) +/* TIM_IC4PSC field */ +#define TIM_IC4PSC (0x00000C00u) +#define TIM_IC4PSC_MASK (0x00000C00u) +#define TIM_IC4PSC_BIT (10) +#define TIM_IC4PSC_BITS (2) +/* TIM_IC3F field */ +#define TIM_IC3F (0x000000F0u) +#define TIM_IC3F_MASK (0x000000F0u) +#define TIM_IC3F_BIT (4) +#define TIM_IC3F_BITS (4) +/* TIM_IC3PSC field */ +#define TIM_IC3PSC (0x0000000Cu) +#define TIM_IC3PSC_MASK (0x0000000Cu) +#define TIM_IC3PSC_BIT (2) +#define TIM_IC3PSC_BITS (2) +/* TIM_OC4CE field */ +#define TIM_OC4CE (0x00008000u) +#define TIM_OC4CE_MASK (0x00008000u) +#define TIM_OC4CE_BIT (15) +#define TIM_OC4CE_BITS (1) +/* TIM_OC4M field */ +#define TIM_OC4M (0x00007000u) +#define TIM_OC4M_MASK (0x00007000u) +#define TIM_OC4M_BIT (12) +#define TIM_OC4M_BITS (3) +/* TIM_OC4BE field */ +#define TIM_OC4BE (0x00000800u) +#define TIM_OC4BE_MASK (0x00000800u) +#define TIM_OC4BE_BIT (11) +#define TIM_OC4BE_BITS (1) +/* TIM_OC4FE field */ +#define TIM_OC4FE (0x00000400u) +#define TIM_OC4FE_MASK (0x00000400u) +#define TIM_OC4FE_BIT (10) +#define TIM_OC4FE_BITS (1) +/* TIM_CC4S field */ +#define TIM_CC4S (0x00000300u) +#define TIM_CC4S_MASK (0x00000300u) +#define TIM_CC4S_BIT (8) +#define TIM_CC4S_BITS (2) +/* TIM_OC3CE field */ +#define TIM_OC3CE (0x00000080u) +#define TIM_OC3CE_MASK (0x00000080u) +#define TIM_OC3CE_BIT (7) +#define TIM_OC3CE_BITS (1) +/* TIM_OC3M field */ +#define TIM_OC3M (0x00000070u) +#define TIM_OC3M_MASK (0x00000070u) +#define TIM_OC3M_BIT (4) +#define TIM_OC3M_BITS (3) +/* TIM_OC3BE field */ +#define TIM_OC3BE (0x00000008u) +#define TIM_OC3BE_MASK (0x00000008u) +#define TIM_OC3BE_BIT (3) +#define TIM_OC3BE_BITS (1) +/* TIM_OC3FE field */ +#define TIM_OC3FE (0x00000004u) +#define TIM_OC3FE_MASK (0x00000004u) +#define TIM_OC3FE_BIT (2) +#define TIM_OC3FE_BITS (1) +/* TIM_CC3S field */ +#define TIM_CC3S (0x00000003u) +#define TIM_CC3S_MASK (0x00000003u) +#define TIM_CC3S_BIT (0) +#define TIM_CC3S_BITS (2) #define TIM2_CCER *((volatile uint32_t *)0x4000F020u) #define TIM2_CCER_REG *((volatile uint32_t *)0x4000F020u) #define TIM2_CCER_ADDR (0x4000F020u) #define TIM2_CCER_RESET (0x00000000u) - /* TIM_CC4P field */ - #define TIM_CC4P (0x00002000u) - #define TIM_CC4P_MASK (0x00002000u) - #define TIM_CC4P_BIT (13) - #define TIM_CC4P_BITS (1) - /* TIM_CC4E field */ - #define TIM_CC4E (0x00001000u) - #define TIM_CC4E_MASK (0x00001000u) - #define TIM_CC4E_BIT (12) - #define TIM_CC4E_BITS (1) - /* TIM_CC3P field */ - #define TIM_CC3P (0x00000200u) - #define TIM_CC3P_MASK (0x00000200u) - #define TIM_CC3P_BIT (9) - #define TIM_CC3P_BITS (1) - /* TIM_CC3E field */ - #define TIM_CC3E (0x00000100u) - #define TIM_CC3E_MASK (0x00000100u) - #define TIM_CC3E_BIT (8) - #define TIM_CC3E_BITS (1) - /* TIM_CC2P field */ - #define TIM_CC2P (0x00000020u) - #define TIM_CC2P_MASK (0x00000020u) - #define TIM_CC2P_BIT (5) - #define TIM_CC2P_BITS (1) - /* TIM_CC2E field */ - #define TIM_CC2E (0x00000010u) - #define TIM_CC2E_MASK (0x00000010u) - #define TIM_CC2E_BIT (4) - #define TIM_CC2E_BITS (1) - /* TIM_CC1P field */ - #define TIM_CC1P (0x00000002u) - #define TIM_CC1P_MASK (0x00000002u) - #define TIM_CC1P_BIT (1) - #define TIM_CC1P_BITS (1) - /* TIM_CC1E field */ - #define TIM_CC1E (0x00000001u) - #define TIM_CC1E_MASK (0x00000001u) - #define TIM_CC1E_BIT (0) - #define TIM_CC1E_BITS (1) +/* TIM_CC4P field */ +#define TIM_CC4P (0x00002000u) +#define TIM_CC4P_MASK (0x00002000u) +#define TIM_CC4P_BIT (13) +#define TIM_CC4P_BITS (1) +/* TIM_CC4E field */ +#define TIM_CC4E (0x00001000u) +#define TIM_CC4E_MASK (0x00001000u) +#define TIM_CC4E_BIT (12) +#define TIM_CC4E_BITS (1) +/* TIM_CC3P field */ +#define TIM_CC3P (0x00000200u) +#define TIM_CC3P_MASK (0x00000200u) +#define TIM_CC3P_BIT (9) +#define TIM_CC3P_BITS (1) +/* TIM_CC3E field */ +#define TIM_CC3E (0x00000100u) +#define TIM_CC3E_MASK (0x00000100u) +#define TIM_CC3E_BIT (8) +#define TIM_CC3E_BITS (1) +/* TIM_CC2P field */ +#define TIM_CC2P (0x00000020u) +#define TIM_CC2P_MASK (0x00000020u) +#define TIM_CC2P_BIT (5) +#define TIM_CC2P_BITS (1) +/* TIM_CC2E field */ +#define TIM_CC2E (0x00000010u) +#define TIM_CC2E_MASK (0x00000010u) +#define TIM_CC2E_BIT (4) +#define TIM_CC2E_BITS (1) +/* TIM_CC1P field */ +#define TIM_CC1P (0x00000002u) +#define TIM_CC1P_MASK (0x00000002u) +#define TIM_CC1P_BIT (1) +#define TIM_CC1P_BITS (1) +/* TIM_CC1E field */ +#define TIM_CC1E (0x00000001u) +#define TIM_CC1E_MASK (0x00000001u) +#define TIM_CC1E_BIT (0) +#define TIM_CC1E_BITS (1) #define TIM2_CNT *((volatile uint32_t *)0x4000F024u) #define TIM2_CNT_REG *((volatile uint32_t *)0x4000F024u) #define TIM2_CNT_ADDR (0x4000F024u) #define TIM2_CNT_RESET (0x00000000u) - /* TIM_CNT field */ - #define TIM_CNT (0x0000FFFFu) - #define TIM_CNT_MASK (0x0000FFFFu) - #define TIM_CNT_BIT (0) - #define TIM_CNT_BITS (16) +/* TIM_CNT field */ +#define TIM_CNT (0x0000FFFFu) +#define TIM_CNT_MASK (0x0000FFFFu) +#define TIM_CNT_BIT (0) +#define TIM_CNT_BITS (16) #define TIM2_PSC *((volatile uint32_t *)0x4000F028u) #define TIM2_PSC_REG *((volatile uint32_t *)0x4000F028u) #define TIM2_PSC_ADDR (0x4000F028u) #define TIM2_PSC_RESET (0x00000000u) - /* TIM_PSC field */ - #define TIM_PSC (0x0000000Fu) - #define TIM_PSC_MASK (0x0000000Fu) - #define TIM_PSC_BIT (0) - #define TIM_PSC_BITS (4) +/* TIM_PSC field */ +#define TIM_PSC (0x0000000Fu) +#define TIM_PSC_MASK (0x0000000Fu) +#define TIM_PSC_BIT (0) +#define TIM_PSC_BITS (4) #define TIM2_ARR *((volatile uint32_t *)0x4000F02Cu) #define TIM2_ARR_REG *((volatile uint32_t *)0x4000F02Cu) #define TIM2_ARR_ADDR (0x4000F02Cu) #define TIM2_ARR_RESET (0x0000FFFFu) - /* TIM_ARR field */ - #define TIM_ARR (0x0000FFFFu) - #define TIM_ARR_MASK (0x0000FFFFu) - #define TIM_ARR_BIT (0) - #define TIM_ARR_BITS (16) +/* TIM_ARR field */ +#define TIM_ARR (0x0000FFFFu) +#define TIM_ARR_MASK (0x0000FFFFu) +#define TIM_ARR_BIT (0) +#define TIM_ARR_BITS (16) #define TIM2_CCR1 *((volatile uint32_t *)0x4000F034u) #define TIM2_CCR1_REG *((volatile uint32_t *)0x4000F034u) #define TIM2_CCR1_ADDR (0x4000F034u) #define TIM2_CCR1_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM2_CCR2 *((volatile uint32_t *)0x4000F038u) #define TIM2_CCR2_REG *((volatile uint32_t *)0x4000F038u) #define TIM2_CCR2_ADDR (0x4000F038u) #define TIM2_CCR2_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM2_CCR3 *((volatile uint32_t *)0x4000F03Cu) #define TIM2_CCR3_REG *((volatile uint32_t *)0x4000F03Cu) #define TIM2_CCR3_ADDR (0x4000F03Cu) #define TIM2_CCR3_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM2_CCR4 *((volatile uint32_t *)0x4000F040u) #define TIM2_CCR4_REG *((volatile uint32_t *)0x4000F040u) #define TIM2_CCR4_ADDR (0x4000F040u) #define TIM2_CCR4_RESET (0x00000000u) - /* TIM_CCR field */ - #define TIM_CCR (0x0000FFFFu) - #define TIM_CCR_MASK (0x0000FFFFu) - #define TIM_CCR_BIT (0) - #define TIM_CCR_BITS (16) +/* TIM_CCR field */ +#define TIM_CCR (0x0000FFFFu) +#define TIM_CCR_MASK (0x0000FFFFu) +#define TIM_CCR_BIT (0) +#define TIM_CCR_BITS (16) #define TIM2_OR *((volatile uint32_t *)0x4000F050u) #define TIM2_OR_REG *((volatile uint32_t *)0x4000F050u) #define TIM2_OR_ADDR (0x4000F050u) #define TIM2_OR_RESET (0x00000000u) - /* TIM_REMAPC4 field */ - #define TIM_REMAPC4 (0x00000080u) - #define TIM_REMAPC4_MASK (0x00000080u) - #define TIM_REMAPC4_BIT (7) - #define TIM_REMAPC4_BITS (1) - /* TIM_REMAPC3 field */ - #define TIM_REMAPC3 (0x00000040u) - #define TIM_REMAPC3_MASK (0x00000040u) - #define TIM_REMAPC3_BIT (6) - #define TIM_REMAPC3_BITS (1) - /* TIM_REMAPC2 field */ - #define TIM_REMAPC2 (0x00000020u) - #define TIM_REMAPC2_MASK (0x00000020u) - #define TIM_REMAPC2_BIT (5) - #define TIM_REMAPC2_BITS (1) - /* TIM_REMAPC1 field */ - #define TIM_REMAPC1 (0x00000010u) - #define TIM_REMAPC1_MASK (0x00000010u) - #define TIM_REMAPC1_BIT (4) - #define TIM_REMAPC1_BITS (1) - /* TIM_ORRSVD field */ - #define TIM_ORRSVD (0x00000008u) - #define TIM_ORRSVD_MASK (0x00000008u) - #define TIM_ORRSVD_BIT (3) - #define TIM_ORRSVD_BITS (1) - /* TIM_CLKMSKEN field */ - #define TIM_CLKMSKEN (0x00000004u) - #define TIM_CLKMSKEN_MASK (0x00000004u) - #define TIM_CLKMSKEN_BIT (2) - #define TIM_CLKMSKEN_BITS (1) - /* TIM1_EXTRIGSEL field */ - #define TIM1_EXTRIGSEL (0x00000003u) - #define TIM1_EXTRIGSEL_MASK (0x00000003u) - #define TIM1_EXTRIGSEL_BIT (0) - #define TIM1_EXTRIGSEL_BITS (2) +/* TIM_REMAPC4 field */ +#define TIM_REMAPC4 (0x00000080u) +#define TIM_REMAPC4_MASK (0x00000080u) +#define TIM_REMAPC4_BIT (7) +#define TIM_REMAPC4_BITS (1) +/* TIM_REMAPC3 field */ +#define TIM_REMAPC3 (0x00000040u) +#define TIM_REMAPC3_MASK (0x00000040u) +#define TIM_REMAPC3_BIT (6) +#define TIM_REMAPC3_BITS (1) +/* TIM_REMAPC2 field */ +#define TIM_REMAPC2 (0x00000020u) +#define TIM_REMAPC2_MASK (0x00000020u) +#define TIM_REMAPC2_BIT (5) +#define TIM_REMAPC2_BITS (1) +/* TIM_REMAPC1 field */ +#define TIM_REMAPC1 (0x00000010u) +#define TIM_REMAPC1_MASK (0x00000010u) +#define TIM_REMAPC1_BIT (4) +#define TIM_REMAPC1_BITS (1) +/* TIM_ORRSVD field */ +#define TIM_ORRSVD (0x00000008u) +#define TIM_ORRSVD_MASK (0x00000008u) +#define TIM_ORRSVD_BIT (3) +#define TIM_ORRSVD_BITS (1) +/* TIM_CLKMSKEN field */ +#define TIM_CLKMSKEN (0x00000004u) +#define TIM_CLKMSKEN_MASK (0x00000004u) +#define TIM_CLKMSKEN_BIT (2) +#define TIM_CLKMSKEN_BITS (1) +/* TIM1_EXTRIGSEL field */ +#define TIM1_EXTRIGSEL (0x00000003u) +#define TIM1_EXTRIGSEL_MASK (0x00000003u) +#define TIM1_EXTRIGSEL_BIT (0) +#define TIM1_EXTRIGSEL_BITS (2) /* EXT_RAM block */ #define DATA_EXT_RAM_BASE (0x60000000u) @@ -7714,726 +7714,726 @@ #define ITM_SP0_REG *((volatile uint32_t *)0xE0000000u) #define ITM_SP0_ADDR (0xE0000000u) #define ITM_SP0_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP0_FIFOREADY (0x00000001u) - #define ITM_SP0_FIFOREADY_MASK (0x00000001u) - #define ITM_SP0_FIFOREADY_BIT (0) - #define ITM_SP0_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP0_STIMULUS (0xFFFFFFFFu) - #define ITM_SP0_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP0_STIMULUS_BIT (0) - #define ITM_SP0_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP0_FIFOREADY (0x00000001u) +#define ITM_SP0_FIFOREADY_MASK (0x00000001u) +#define ITM_SP0_FIFOREADY_BIT (0) +#define ITM_SP0_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP0_STIMULUS (0xFFFFFFFFu) +#define ITM_SP0_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP0_STIMULUS_BIT (0) +#define ITM_SP0_STIMULUS_BITS (32) #define ITM_SP1 *((volatile uint32_t *)0xE0000004u) #define ITM_SP1_REG *((volatile uint32_t *)0xE0000004u) #define ITM_SP1_ADDR (0xE0000004u) #define ITM_SP1_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP1_FIFOREADY (0x00000001u) - #define ITM_SP1_FIFOREADY_MASK (0x00000001u) - #define ITM_SP1_FIFOREADY_BIT (0) - #define ITM_SP1_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP1_STIMULUS (0xFFFFFFFFu) - #define ITM_SP1_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP1_STIMULUS_BIT (0) - #define ITM_SP1_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP1_FIFOREADY (0x00000001u) +#define ITM_SP1_FIFOREADY_MASK (0x00000001u) +#define ITM_SP1_FIFOREADY_BIT (0) +#define ITM_SP1_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP1_STIMULUS (0xFFFFFFFFu) +#define ITM_SP1_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP1_STIMULUS_BIT (0) +#define ITM_SP1_STIMULUS_BITS (32) #define ITM_SP2 *((volatile uint32_t *)0xE0000008u) #define ITM_SP2_REG *((volatile uint32_t *)0xE0000008u) #define ITM_SP2_ADDR (0xE0000008u) #define ITM_SP2_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP2_FIFOREADY (0x00000001u) - #define ITM_SP2_FIFOREADY_MASK (0x00000001u) - #define ITM_SP2_FIFOREADY_BIT (0) - #define ITM_SP2_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP2_STIMULUS (0xFFFFFFFFu) - #define ITM_SP2_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP2_STIMULUS_BIT (0) - #define ITM_SP2_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP2_FIFOREADY (0x00000001u) +#define ITM_SP2_FIFOREADY_MASK (0x00000001u) +#define ITM_SP2_FIFOREADY_BIT (0) +#define ITM_SP2_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP2_STIMULUS (0xFFFFFFFFu) +#define ITM_SP2_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP2_STIMULUS_BIT (0) +#define ITM_SP2_STIMULUS_BITS (32) #define ITM_SP3 *((volatile uint32_t *)0xE000000Cu) #define ITM_SP3_REG *((volatile uint32_t *)0xE000000Cu) #define ITM_SP3_ADDR (0xE000000Cu) #define ITM_SP3_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP3_FIFOREADY (0x00000001u) - #define ITM_SP3_FIFOREADY_MASK (0x00000001u) - #define ITM_SP3_FIFOREADY_BIT (0) - #define ITM_SP3_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP3_STIMULUS (0xFFFFFFFFu) - #define ITM_SP3_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP3_STIMULUS_BIT (0) - #define ITM_SP3_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP3_FIFOREADY (0x00000001u) +#define ITM_SP3_FIFOREADY_MASK (0x00000001u) +#define ITM_SP3_FIFOREADY_BIT (0) +#define ITM_SP3_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP3_STIMULUS (0xFFFFFFFFu) +#define ITM_SP3_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP3_STIMULUS_BIT (0) +#define ITM_SP3_STIMULUS_BITS (32) #define ITM_SP4 *((volatile uint32_t *)0xE0000010u) #define ITM_SP4_REG *((volatile uint32_t *)0xE0000010u) #define ITM_SP4_ADDR (0xE0000010u) #define ITM_SP4_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP4_FIFOREADY (0x00000001u) - #define ITM_SP4_FIFOREADY_MASK (0x00000001u) - #define ITM_SP4_FIFOREADY_BIT (0) - #define ITM_SP4_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP4_STIMULUS (0xFFFFFFFFu) - #define ITM_SP4_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP4_STIMULUS_BIT (0) - #define ITM_SP4_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP4_FIFOREADY (0x00000001u) +#define ITM_SP4_FIFOREADY_MASK (0x00000001u) +#define ITM_SP4_FIFOREADY_BIT (0) +#define ITM_SP4_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP4_STIMULUS (0xFFFFFFFFu) +#define ITM_SP4_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP4_STIMULUS_BIT (0) +#define ITM_SP4_STIMULUS_BITS (32) #define ITM_SP5 *((volatile uint32_t *)0xE0000014u) #define ITM_SP5_REG *((volatile uint32_t *)0xE0000014u) #define ITM_SP5_ADDR (0xE0000014u) #define ITM_SP5_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP5_FIFOREADY (0x00000001u) - #define ITM_SP5_FIFOREADY_MASK (0x00000001u) - #define ITM_SP5_FIFOREADY_BIT (0) - #define ITM_SP5_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP5_STIMULUS (0xFFFFFFFFu) - #define ITM_SP5_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP5_STIMULUS_BIT (0) - #define ITM_SP5_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP5_FIFOREADY (0x00000001u) +#define ITM_SP5_FIFOREADY_MASK (0x00000001u) +#define ITM_SP5_FIFOREADY_BIT (0) +#define ITM_SP5_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP5_STIMULUS (0xFFFFFFFFu) +#define ITM_SP5_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP5_STIMULUS_BIT (0) +#define ITM_SP5_STIMULUS_BITS (32) #define ITM_SP6 *((volatile uint32_t *)0xE0000018u) #define ITM_SP6_REG *((volatile uint32_t *)0xE0000018u) #define ITM_SP6_ADDR (0xE0000018u) #define ITM_SP6_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP6_FIFOREADY (0x00000001u) - #define ITM_SP6_FIFOREADY_MASK (0x00000001u) - #define ITM_SP6_FIFOREADY_BIT (0) - #define ITM_SP6_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP6_STIMULUS (0xFFFFFFFFu) - #define ITM_SP6_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP6_STIMULUS_BIT (0) - #define ITM_SP6_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP6_FIFOREADY (0x00000001u) +#define ITM_SP6_FIFOREADY_MASK (0x00000001u) +#define ITM_SP6_FIFOREADY_BIT (0) +#define ITM_SP6_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP6_STIMULUS (0xFFFFFFFFu) +#define ITM_SP6_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP6_STIMULUS_BIT (0) +#define ITM_SP6_STIMULUS_BITS (32) #define ITM_SP7 *((volatile uint32_t *)0xE000001Cu) #define ITM_SP7_REG *((volatile uint32_t *)0xE000001Cu) #define ITM_SP7_ADDR (0xE000001Cu) #define ITM_SP7_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP7_FIFOREADY (0x00000001u) - #define ITM_SP7_FIFOREADY_MASK (0x00000001u) - #define ITM_SP7_FIFOREADY_BIT (0) - #define ITM_SP7_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP7_STIMULUS (0xFFFFFFFFu) - #define ITM_SP7_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP7_STIMULUS_BIT (0) - #define ITM_SP7_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP7_FIFOREADY (0x00000001u) +#define ITM_SP7_FIFOREADY_MASK (0x00000001u) +#define ITM_SP7_FIFOREADY_BIT (0) +#define ITM_SP7_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP7_STIMULUS (0xFFFFFFFFu) +#define ITM_SP7_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP7_STIMULUS_BIT (0) +#define ITM_SP7_STIMULUS_BITS (32) #define ITM_SP8 *((volatile uint32_t *)0xE0000020u) #define ITM_SP8_REG *((volatile uint32_t *)0xE0000020u) #define ITM_SP8_ADDR (0xE0000020u) #define ITM_SP8_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP8_FIFOREADY (0x00000001u) - #define ITM_SP8_FIFOREADY_MASK (0x00000001u) - #define ITM_SP8_FIFOREADY_BIT (0) - #define ITM_SP8_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP8_STIMULUS (0xFFFFFFFFu) - #define ITM_SP8_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP8_STIMULUS_BIT (0) - #define ITM_SP8_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP8_FIFOREADY (0x00000001u) +#define ITM_SP8_FIFOREADY_MASK (0x00000001u) +#define ITM_SP8_FIFOREADY_BIT (0) +#define ITM_SP8_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP8_STIMULUS (0xFFFFFFFFu) +#define ITM_SP8_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP8_STIMULUS_BIT (0) +#define ITM_SP8_STIMULUS_BITS (32) #define ITM_SP9 *((volatile uint32_t *)0xE0000024u) #define ITM_SP9_REG *((volatile uint32_t *)0xE0000024u) #define ITM_SP9_ADDR (0xE0000024u) #define ITM_SP9_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP9_FIFOREADY (0x00000001u) - #define ITM_SP9_FIFOREADY_MASK (0x00000001u) - #define ITM_SP9_FIFOREADY_BIT (0) - #define ITM_SP9_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP9_STIMULUS (0xFFFFFFFFu) - #define ITM_SP9_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP9_STIMULUS_BIT (0) - #define ITM_SP9_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP9_FIFOREADY (0x00000001u) +#define ITM_SP9_FIFOREADY_MASK (0x00000001u) +#define ITM_SP9_FIFOREADY_BIT (0) +#define ITM_SP9_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP9_STIMULUS (0xFFFFFFFFu) +#define ITM_SP9_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP9_STIMULUS_BIT (0) +#define ITM_SP9_STIMULUS_BITS (32) #define ITM_SP10 *((volatile uint32_t *)0xE0000028u) #define ITM_SP10_REG *((volatile uint32_t *)0xE0000028u) #define ITM_SP10_ADDR (0xE0000028u) #define ITM_SP10_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP10_FIFOREADY (0x00000001u) - #define ITM_SP10_FIFOREADY_MASK (0x00000001u) - #define ITM_SP10_FIFOREADY_BIT (0) - #define ITM_SP10_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP10_STIMULUS (0xFFFFFFFFu) - #define ITM_SP10_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP10_STIMULUS_BIT (0) - #define ITM_SP10_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP10_FIFOREADY (0x00000001u) +#define ITM_SP10_FIFOREADY_MASK (0x00000001u) +#define ITM_SP10_FIFOREADY_BIT (0) +#define ITM_SP10_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP10_STIMULUS (0xFFFFFFFFu) +#define ITM_SP10_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP10_STIMULUS_BIT (0) +#define ITM_SP10_STIMULUS_BITS (32) #define ITM_SP11 *((volatile uint32_t *)0xE000002Cu) #define ITM_SP11_REG *((volatile uint32_t *)0xE000002Cu) #define ITM_SP11_ADDR (0xE000002Cu) #define ITM_SP11_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP11_FIFOREADY (0x00000001u) - #define ITM_SP11_FIFOREADY_MASK (0x00000001u) - #define ITM_SP11_FIFOREADY_BIT (0) - #define ITM_SP11_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP11_STIMULUS (0xFFFFFFFFu) - #define ITM_SP11_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP11_STIMULUS_BIT (0) - #define ITM_SP11_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP11_FIFOREADY (0x00000001u) +#define ITM_SP11_FIFOREADY_MASK (0x00000001u) +#define ITM_SP11_FIFOREADY_BIT (0) +#define ITM_SP11_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP11_STIMULUS (0xFFFFFFFFu) +#define ITM_SP11_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP11_STIMULUS_BIT (0) +#define ITM_SP11_STIMULUS_BITS (32) #define ITM_SP12 *((volatile uint32_t *)0xE0000030u) #define ITM_SP12_REG *((volatile uint32_t *)0xE0000030u) #define ITM_SP12_ADDR (0xE0000030u) #define ITM_SP12_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP12_FIFOREADY (0x00000001u) - #define ITM_SP12_FIFOREADY_MASK (0x00000001u) - #define ITM_SP12_FIFOREADY_BIT (0) - #define ITM_SP12_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP12_STIMULUS (0xFFFFFFFFu) - #define ITM_SP12_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP12_STIMULUS_BIT (0) - #define ITM_SP12_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP12_FIFOREADY (0x00000001u) +#define ITM_SP12_FIFOREADY_MASK (0x00000001u) +#define ITM_SP12_FIFOREADY_BIT (0) +#define ITM_SP12_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP12_STIMULUS (0xFFFFFFFFu) +#define ITM_SP12_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP12_STIMULUS_BIT (0) +#define ITM_SP12_STIMULUS_BITS (32) #define ITM_SP13 *((volatile uint32_t *)0xE0000034u) #define ITM_SP13_REG *((volatile uint32_t *)0xE0000034u) #define ITM_SP13_ADDR (0xE0000034u) #define ITM_SP13_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP13_FIFOREADY (0x00000001u) - #define ITM_SP13_FIFOREADY_MASK (0x00000001u) - #define ITM_SP13_FIFOREADY_BIT (0) - #define ITM_SP13_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP13_STIMULUS (0xFFFFFFFFu) - #define ITM_SP13_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP13_STIMULUS_BIT (0) - #define ITM_SP13_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP13_FIFOREADY (0x00000001u) +#define ITM_SP13_FIFOREADY_MASK (0x00000001u) +#define ITM_SP13_FIFOREADY_BIT (0) +#define ITM_SP13_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP13_STIMULUS (0xFFFFFFFFu) +#define ITM_SP13_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP13_STIMULUS_BIT (0) +#define ITM_SP13_STIMULUS_BITS (32) #define ITM_SP14 *((volatile uint32_t *)0xE0000038u) #define ITM_SP14_REG *((volatile uint32_t *)0xE0000038u) #define ITM_SP14_ADDR (0xE0000038u) #define ITM_SP14_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP14_FIFOREADY (0x00000001u) - #define ITM_SP14_FIFOREADY_MASK (0x00000001u) - #define ITM_SP14_FIFOREADY_BIT (0) - #define ITM_SP14_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP14_STIMULUS (0xFFFFFFFFu) - #define ITM_SP14_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP14_STIMULUS_BIT (0) - #define ITM_SP14_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP14_FIFOREADY (0x00000001u) +#define ITM_SP14_FIFOREADY_MASK (0x00000001u) +#define ITM_SP14_FIFOREADY_BIT (0) +#define ITM_SP14_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP14_STIMULUS (0xFFFFFFFFu) +#define ITM_SP14_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP14_STIMULUS_BIT (0) +#define ITM_SP14_STIMULUS_BITS (32) #define ITM_SP15 *((volatile uint32_t *)0xE000003Cu) #define ITM_SP15_REG *((volatile uint32_t *)0xE000003Cu) #define ITM_SP15_ADDR (0xE000003Cu) #define ITM_SP15_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP15_FIFOREADY (0x00000001u) - #define ITM_SP15_FIFOREADY_MASK (0x00000001u) - #define ITM_SP15_FIFOREADY_BIT (0) - #define ITM_SP15_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP15_STIMULUS (0xFFFFFFFFu) - #define ITM_SP15_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP15_STIMULUS_BIT (0) - #define ITM_SP15_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP15_FIFOREADY (0x00000001u) +#define ITM_SP15_FIFOREADY_MASK (0x00000001u) +#define ITM_SP15_FIFOREADY_BIT (0) +#define ITM_SP15_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP15_STIMULUS (0xFFFFFFFFu) +#define ITM_SP15_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP15_STIMULUS_BIT (0) +#define ITM_SP15_STIMULUS_BITS (32) #define ITM_SP16 *((volatile uint32_t *)0xE0000040u) #define ITM_SP16_REG *((volatile uint32_t *)0xE0000040u) #define ITM_SP16_ADDR (0xE0000040u) #define ITM_SP16_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP16_FIFOREADY (0x00000001u) - #define ITM_SP16_FIFOREADY_MASK (0x00000001u) - #define ITM_SP16_FIFOREADY_BIT (0) - #define ITM_SP16_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP16_STIMULUS (0xFFFFFFFFu) - #define ITM_SP16_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP16_STIMULUS_BIT (0) - #define ITM_SP16_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP16_FIFOREADY (0x00000001u) +#define ITM_SP16_FIFOREADY_MASK (0x00000001u) +#define ITM_SP16_FIFOREADY_BIT (0) +#define ITM_SP16_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP16_STIMULUS (0xFFFFFFFFu) +#define ITM_SP16_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP16_STIMULUS_BIT (0) +#define ITM_SP16_STIMULUS_BITS (32) #define ITM_SP17 *((volatile uint32_t *)0xE0000044u) #define ITM_SP17_REG *((volatile uint32_t *)0xE0000044u) #define ITM_SP17_ADDR (0xE0000044u) #define ITM_SP17_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP17_FIFOREADY (0x00000001u) - #define ITM_SP17_FIFOREADY_MASK (0x00000001u) - #define ITM_SP17_FIFOREADY_BIT (0) - #define ITM_SP17_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP17_STIMULUS (0xFFFFFFFFu) - #define ITM_SP17_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP17_STIMULUS_BIT (0) - #define ITM_SP17_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP17_FIFOREADY (0x00000001u) +#define ITM_SP17_FIFOREADY_MASK (0x00000001u) +#define ITM_SP17_FIFOREADY_BIT (0) +#define ITM_SP17_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP17_STIMULUS (0xFFFFFFFFu) +#define ITM_SP17_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP17_STIMULUS_BIT (0) +#define ITM_SP17_STIMULUS_BITS (32) #define ITM_SP18 *((volatile uint32_t *)0xE0000048u) #define ITM_SP18_REG *((volatile uint32_t *)0xE0000048u) #define ITM_SP18_ADDR (0xE0000048u) #define ITM_SP18_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP18_FIFOREADY (0x00000001u) - #define ITM_SP18_FIFOREADY_MASK (0x00000001u) - #define ITM_SP18_FIFOREADY_BIT (0) - #define ITM_SP18_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP18_STIMULUS (0xFFFFFFFFu) - #define ITM_SP18_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP18_STIMULUS_BIT (0) - #define ITM_SP18_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP18_FIFOREADY (0x00000001u) +#define ITM_SP18_FIFOREADY_MASK (0x00000001u) +#define ITM_SP18_FIFOREADY_BIT (0) +#define ITM_SP18_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP18_STIMULUS (0xFFFFFFFFu) +#define ITM_SP18_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP18_STIMULUS_BIT (0) +#define ITM_SP18_STIMULUS_BITS (32) #define ITM_SP19 *((volatile uint32_t *)0xE000004Cu) #define ITM_SP19_REG *((volatile uint32_t *)0xE000004Cu) #define ITM_SP19_ADDR (0xE000004Cu) #define ITM_SP19_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP19_FIFOREADY (0x00000001u) - #define ITM_SP19_FIFOREADY_MASK (0x00000001u) - #define ITM_SP19_FIFOREADY_BIT (0) - #define ITM_SP19_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP19_STIMULUS (0xFFFFFFFFu) - #define ITM_SP19_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP19_STIMULUS_BIT (0) - #define ITM_SP19_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP19_FIFOREADY (0x00000001u) +#define ITM_SP19_FIFOREADY_MASK (0x00000001u) +#define ITM_SP19_FIFOREADY_BIT (0) +#define ITM_SP19_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP19_STIMULUS (0xFFFFFFFFu) +#define ITM_SP19_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP19_STIMULUS_BIT (0) +#define ITM_SP19_STIMULUS_BITS (32) #define ITM_SP20 *((volatile uint32_t *)0xE0000050u) #define ITM_SP20_REG *((volatile uint32_t *)0xE0000050u) #define ITM_SP20_ADDR (0xE0000050u) #define ITM_SP20_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP20_FIFOREADY (0x00000001u) - #define ITM_SP20_FIFOREADY_MASK (0x00000001u) - #define ITM_SP20_FIFOREADY_BIT (0) - #define ITM_SP20_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP20_STIMULUS (0xFFFFFFFFu) - #define ITM_SP20_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP20_STIMULUS_BIT (0) - #define ITM_SP20_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP20_FIFOREADY (0x00000001u) +#define ITM_SP20_FIFOREADY_MASK (0x00000001u) +#define ITM_SP20_FIFOREADY_BIT (0) +#define ITM_SP20_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP20_STIMULUS (0xFFFFFFFFu) +#define ITM_SP20_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP20_STIMULUS_BIT (0) +#define ITM_SP20_STIMULUS_BITS (32) #define ITM_SP21 *((volatile uint32_t *)0xE0000054u) #define ITM_SP21_REG *((volatile uint32_t *)0xE0000054u) #define ITM_SP21_ADDR (0xE0000054u) #define ITM_SP21_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP21_FIFOREADY (0x00000001u) - #define ITM_SP21_FIFOREADY_MASK (0x00000001u) - #define ITM_SP21_FIFOREADY_BIT (0) - #define ITM_SP21_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP21_STIMULUS (0xFFFFFFFFu) - #define ITM_SP21_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP21_STIMULUS_BIT (0) - #define ITM_SP21_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP21_FIFOREADY (0x00000001u) +#define ITM_SP21_FIFOREADY_MASK (0x00000001u) +#define ITM_SP21_FIFOREADY_BIT (0) +#define ITM_SP21_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP21_STIMULUS (0xFFFFFFFFu) +#define ITM_SP21_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP21_STIMULUS_BIT (0) +#define ITM_SP21_STIMULUS_BITS (32) #define ITM_SP22 *((volatile uint32_t *)0xE0000058u) #define ITM_SP22_REG *((volatile uint32_t *)0xE0000058u) #define ITM_SP22_ADDR (0xE0000058u) #define ITM_SP22_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP22_FIFOREADY (0x00000001u) - #define ITM_SP22_FIFOREADY_MASK (0x00000001u) - #define ITM_SP22_FIFOREADY_BIT (0) - #define ITM_SP22_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP22_STIMULUS (0xFFFFFFFFu) - #define ITM_SP22_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP22_STIMULUS_BIT (0) - #define ITM_SP22_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP22_FIFOREADY (0x00000001u) +#define ITM_SP22_FIFOREADY_MASK (0x00000001u) +#define ITM_SP22_FIFOREADY_BIT (0) +#define ITM_SP22_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP22_STIMULUS (0xFFFFFFFFu) +#define ITM_SP22_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP22_STIMULUS_BIT (0) +#define ITM_SP22_STIMULUS_BITS (32) #define ITM_SP23 *((volatile uint32_t *)0xE000005Cu) #define ITM_SP23_REG *((volatile uint32_t *)0xE000005Cu) #define ITM_SP23_ADDR (0xE000005Cu) #define ITM_SP23_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP23_FIFOREADY (0x00000001u) - #define ITM_SP23_FIFOREADY_MASK (0x00000001u) - #define ITM_SP23_FIFOREADY_BIT (0) - #define ITM_SP23_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP23_STIMULUS (0xFFFFFFFFu) - #define ITM_SP23_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP23_STIMULUS_BIT (0) - #define ITM_SP23_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP23_FIFOREADY (0x00000001u) +#define ITM_SP23_FIFOREADY_MASK (0x00000001u) +#define ITM_SP23_FIFOREADY_BIT (0) +#define ITM_SP23_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP23_STIMULUS (0xFFFFFFFFu) +#define ITM_SP23_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP23_STIMULUS_BIT (0) +#define ITM_SP23_STIMULUS_BITS (32) #define ITM_SP24 *((volatile uint32_t *)0xE0000060u) #define ITM_SP24_REG *((volatile uint32_t *)0xE0000060u) #define ITM_SP24_ADDR (0xE0000060u) #define ITM_SP24_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP24_FIFOREADY (0x00000001u) - #define ITM_SP24_FIFOREADY_MASK (0x00000001u) - #define ITM_SP24_FIFOREADY_BIT (0) - #define ITM_SP24_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP24_STIMULUS (0xFFFFFFFFu) - #define ITM_SP24_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP24_STIMULUS_BIT (0) - #define ITM_SP24_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP24_FIFOREADY (0x00000001u) +#define ITM_SP24_FIFOREADY_MASK (0x00000001u) +#define ITM_SP24_FIFOREADY_BIT (0) +#define ITM_SP24_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP24_STIMULUS (0xFFFFFFFFu) +#define ITM_SP24_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP24_STIMULUS_BIT (0) +#define ITM_SP24_STIMULUS_BITS (32) #define ITM_SP25 *((volatile uint32_t *)0xE0000064u) #define ITM_SP25_REG *((volatile uint32_t *)0xE0000064u) #define ITM_SP25_ADDR (0xE0000064u) #define ITM_SP25_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP25_FIFOREADY (0x00000001u) - #define ITM_SP25_FIFOREADY_MASK (0x00000001u) - #define ITM_SP25_FIFOREADY_BIT (0) - #define ITM_SP25_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP25_STIMULUS (0xFFFFFFFFu) - #define ITM_SP25_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP25_STIMULUS_BIT (0) - #define ITM_SP25_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP25_FIFOREADY (0x00000001u) +#define ITM_SP25_FIFOREADY_MASK (0x00000001u) +#define ITM_SP25_FIFOREADY_BIT (0) +#define ITM_SP25_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP25_STIMULUS (0xFFFFFFFFu) +#define ITM_SP25_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP25_STIMULUS_BIT (0) +#define ITM_SP25_STIMULUS_BITS (32) #define ITM_SP26 *((volatile uint32_t *)0xE0000068u) #define ITM_SP26_REG *((volatile uint32_t *)0xE0000068u) #define ITM_SP26_ADDR (0xE0000068u) #define ITM_SP26_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP26_FIFOREADY (0x00000001u) - #define ITM_SP26_FIFOREADY_MASK (0x00000001u) - #define ITM_SP26_FIFOREADY_BIT (0) - #define ITM_SP26_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP26_STIMULUS (0xFFFFFFFFu) - #define ITM_SP26_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP26_STIMULUS_BIT (0) - #define ITM_SP26_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP26_FIFOREADY (0x00000001u) +#define ITM_SP26_FIFOREADY_MASK (0x00000001u) +#define ITM_SP26_FIFOREADY_BIT (0) +#define ITM_SP26_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP26_STIMULUS (0xFFFFFFFFu) +#define ITM_SP26_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP26_STIMULUS_BIT (0) +#define ITM_SP26_STIMULUS_BITS (32) #define ITM_SP27 *((volatile uint32_t *)0xE000006Cu) #define ITM_SP27_REG *((volatile uint32_t *)0xE000006Cu) #define ITM_SP27_ADDR (0xE000006Cu) #define ITM_SP27_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP27_FIFOREADY (0x00000001u) - #define ITM_SP27_FIFOREADY_MASK (0x00000001u) - #define ITM_SP27_FIFOREADY_BIT (0) - #define ITM_SP27_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP27_STIMULUS (0xFFFFFFFFu) - #define ITM_SP27_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP27_STIMULUS_BIT (0) - #define ITM_SP27_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP27_FIFOREADY (0x00000001u) +#define ITM_SP27_FIFOREADY_MASK (0x00000001u) +#define ITM_SP27_FIFOREADY_BIT (0) +#define ITM_SP27_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP27_STIMULUS (0xFFFFFFFFu) +#define ITM_SP27_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP27_STIMULUS_BIT (0) +#define ITM_SP27_STIMULUS_BITS (32) #define ITM_SP28 *((volatile uint32_t *)0xE0000070u) #define ITM_SP28_REG *((volatile uint32_t *)0xE0000070u) #define ITM_SP28_ADDR (0xE0000070u) #define ITM_SP28_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP28_FIFOREADY (0x00000001u) - #define ITM_SP28_FIFOREADY_MASK (0x00000001u) - #define ITM_SP28_FIFOREADY_BIT (0) - #define ITM_SP28_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP28_STIMULUS (0xFFFFFFFFu) - #define ITM_SP28_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP28_STIMULUS_BIT (0) - #define ITM_SP28_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP28_FIFOREADY (0x00000001u) +#define ITM_SP28_FIFOREADY_MASK (0x00000001u) +#define ITM_SP28_FIFOREADY_BIT (0) +#define ITM_SP28_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP28_STIMULUS (0xFFFFFFFFu) +#define ITM_SP28_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP28_STIMULUS_BIT (0) +#define ITM_SP28_STIMULUS_BITS (32) #define ITM_SP29 *((volatile uint32_t *)0xE0000074u) #define ITM_SP29_REG *((volatile uint32_t *)0xE0000074u) #define ITM_SP29_ADDR (0xE0000074u) #define ITM_SP29_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP29_FIFOREADY (0x00000001u) - #define ITM_SP29_FIFOREADY_MASK (0x00000001u) - #define ITM_SP29_FIFOREADY_BIT (0) - #define ITM_SP29_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP29_STIMULUS (0xFFFFFFFFu) - #define ITM_SP29_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP29_STIMULUS_BIT (0) - #define ITM_SP29_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP29_FIFOREADY (0x00000001u) +#define ITM_SP29_FIFOREADY_MASK (0x00000001u) +#define ITM_SP29_FIFOREADY_BIT (0) +#define ITM_SP29_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP29_STIMULUS (0xFFFFFFFFu) +#define ITM_SP29_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP29_STIMULUS_BIT (0) +#define ITM_SP29_STIMULUS_BITS (32) #define ITM_SP30 *((volatile uint32_t *)0xE0000078u) #define ITM_SP30_REG *((volatile uint32_t *)0xE0000078u) #define ITM_SP30_ADDR (0xE0000078u) #define ITM_SP30_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP30_FIFOREADY (0x00000001u) - #define ITM_SP30_FIFOREADY_MASK (0x00000001u) - #define ITM_SP30_FIFOREADY_BIT (0) - #define ITM_SP30_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP30_STIMULUS (0xFFFFFFFFu) - #define ITM_SP30_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP30_STIMULUS_BIT (0) - #define ITM_SP30_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP30_FIFOREADY (0x00000001u) +#define ITM_SP30_FIFOREADY_MASK (0x00000001u) +#define ITM_SP30_FIFOREADY_BIT (0) +#define ITM_SP30_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP30_STIMULUS (0xFFFFFFFFu) +#define ITM_SP30_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP30_STIMULUS_BIT (0) +#define ITM_SP30_STIMULUS_BITS (32) #define ITM_SP31 *((volatile uint32_t *)0xE000007Cu) #define ITM_SP31_REG *((volatile uint32_t *)0xE000007Cu) #define ITM_SP31_ADDR (0xE000007Cu) #define ITM_SP31_RESET (0x00000000u) - /* FIFOREADY field */ - #define ITM_SP31_FIFOREADY (0x00000001u) - #define ITM_SP31_FIFOREADY_MASK (0x00000001u) - #define ITM_SP31_FIFOREADY_BIT (0) - #define ITM_SP31_FIFOREADY_BITS (1) - /* STIMULUS field */ - #define ITM_SP31_STIMULUS (0xFFFFFFFFu) - #define ITM_SP31_STIMULUS_MASK (0xFFFFFFFFu) - #define ITM_SP31_STIMULUS_BIT (0) - #define ITM_SP31_STIMULUS_BITS (32) +/* FIFOREADY field */ +#define ITM_SP31_FIFOREADY (0x00000001u) +#define ITM_SP31_FIFOREADY_MASK (0x00000001u) +#define ITM_SP31_FIFOREADY_BIT (0) +#define ITM_SP31_FIFOREADY_BITS (1) +/* STIMULUS field */ +#define ITM_SP31_STIMULUS (0xFFFFFFFFu) +#define ITM_SP31_STIMULUS_MASK (0xFFFFFFFFu) +#define ITM_SP31_STIMULUS_BIT (0) +#define ITM_SP31_STIMULUS_BITS (32) #define ITM_TER *((volatile uint32_t *)0xE0000E00u) #define ITM_TER_REG *((volatile uint32_t *)0xE0000E00u) #define ITM_TER_ADDR (0xE0000E00u) #define ITM_TER_RESET (0x00000000u) - /* STIMENA field */ - #define ITM_TER_STIMENA (0xFFFFFFFFu) - #define ITM_TER_STIMENA_MASK (0xFFFFFFFFu) - #define ITM_TER_STIMENA_BIT (0) - #define ITM_TER_STIMENA_BITS (32) +/* STIMENA field */ +#define ITM_TER_STIMENA (0xFFFFFFFFu) +#define ITM_TER_STIMENA_MASK (0xFFFFFFFFu) +#define ITM_TER_STIMENA_BIT (0) +#define ITM_TER_STIMENA_BITS (32) #define ITM_TPR *((volatile uint32_t *)0xE0000E40u) #define ITM_TPR_REG *((volatile uint32_t *)0xE0000E40u) #define ITM_TPR_ADDR (0xE0000E40u) #define ITM_TPR_RESET (0x00000000u) - /* PRIVMASK field */ - #define ITM_TPR_PRIVMASK (0x0000000Fu) - #define ITM_TPR_PRIVMASK_MASK (0x0000000Fu) - #define ITM_TPR_PRIVMASK_BIT (0) - #define ITM_TPR_PRIVMASK_BITS (4) +/* PRIVMASK field */ +#define ITM_TPR_PRIVMASK (0x0000000Fu) +#define ITM_TPR_PRIVMASK_MASK (0x0000000Fu) +#define ITM_TPR_PRIVMASK_BIT (0) +#define ITM_TPR_PRIVMASK_BITS (4) #define ITM_TCR *((volatile uint32_t *)0xE0000E80u) #define ITM_TCR_REG *((volatile uint32_t *)0xE0000E80u) #define ITM_TCR_ADDR (0xE0000E80u) #define ITM_TCR_RESET (0x00000000u) - /* BUSY field */ - #define ITM_TCR_BUSY (0x00800000u) - #define ITM_TCR_BUSY_MASK (0x00800000u) - #define ITM_TCR_BUSY_BIT (23) - #define ITM_TCR_BUSY_BITS (1) - /* ATBID field */ - #define ITM_TCR_ATBID (0x007F0000u) - #define ITM_TCR_ATBID_MASK (0x007F0000u) - #define ITM_TCR_ATBID_BIT (16) - #define ITM_TCR_ATBID_BITS (7) - /* TSPRESCALE field */ - #define ITM_TCR_TSPRESCALE (0x00000300u) - #define ITM_TCR_TSPRESCALE_MASK (0x00000300u) - #define ITM_TCR_TSPRESCALE_BIT (8) - #define ITM_TCR_TSPRESCALE_BITS (2) - /* SWOENA field */ - #define ITM_TCR_SWOENA (0x00000010u) - #define ITM_TCR_SWOENA_MASK (0x00000010u) - #define ITM_TCR_SWOENA_BIT (4) - #define ITM_TCR_SWOENA_BITS (1) - /* DWTENA field */ - #define ITM_TCR_DWTENA (0x00000008u) - #define ITM_TCR_DWTENA_MASK (0x00000008u) - #define ITM_TCR_DWTENA_BIT (3) - #define ITM_TCR_DWTENA_BITS (1) - /* SYNCENA field */ - #define ITM_TCR_SYNCENA (0x00000004u) - #define ITM_TCR_SYNCENA_MASK (0x00000004u) - #define ITM_TCR_SYNCENA_BIT (2) - #define ITM_TCR_SYNCENA_BITS (1) - /* TSENA field */ - #define ITM_TCR_TSENA (0x00000002u) - #define ITM_TCR_TSENA_MASK (0x00000002u) - #define ITM_TCR_TSENA_BIT (1) - #define ITM_TCR_TSENA_BITS (1) - /* ITMEN field */ - #define ITM_TCR_ITMEN (0x00000001u) - #define ITM_TCR_ITMEN_MASK (0x00000001u) - #define ITM_TCR_ITMEN_BIT (0) - #define ITM_TCR_ITMEN_BITS (1) +/* BUSY field */ +#define ITM_TCR_BUSY (0x00800000u) +#define ITM_TCR_BUSY_MASK (0x00800000u) +#define ITM_TCR_BUSY_BIT (23) +#define ITM_TCR_BUSY_BITS (1) +/* ATBID field */ +#define ITM_TCR_ATBID (0x007F0000u) +#define ITM_TCR_ATBID_MASK (0x007F0000u) +#define ITM_TCR_ATBID_BIT (16) +#define ITM_TCR_ATBID_BITS (7) +/* TSPRESCALE field */ +#define ITM_TCR_TSPRESCALE (0x00000300u) +#define ITM_TCR_TSPRESCALE_MASK (0x00000300u) +#define ITM_TCR_TSPRESCALE_BIT (8) +#define ITM_TCR_TSPRESCALE_BITS (2) +/* SWOENA field */ +#define ITM_TCR_SWOENA (0x00000010u) +#define ITM_TCR_SWOENA_MASK (0x00000010u) +#define ITM_TCR_SWOENA_BIT (4) +#define ITM_TCR_SWOENA_BITS (1) +/* DWTENA field */ +#define ITM_TCR_DWTENA (0x00000008u) +#define ITM_TCR_DWTENA_MASK (0x00000008u) +#define ITM_TCR_DWTENA_BIT (3) +#define ITM_TCR_DWTENA_BITS (1) +/* SYNCENA field */ +#define ITM_TCR_SYNCENA (0x00000004u) +#define ITM_TCR_SYNCENA_MASK (0x00000004u) +#define ITM_TCR_SYNCENA_BIT (2) +#define ITM_TCR_SYNCENA_BITS (1) +/* TSENA field */ +#define ITM_TCR_TSENA (0x00000002u) +#define ITM_TCR_TSENA_MASK (0x00000002u) +#define ITM_TCR_TSENA_BIT (1) +#define ITM_TCR_TSENA_BITS (1) +/* ITMEN field */ +#define ITM_TCR_ITMEN (0x00000001u) +#define ITM_TCR_ITMEN_MASK (0x00000001u) +#define ITM_TCR_ITMEN_BIT (0) +#define ITM_TCR_ITMEN_BITS (1) #define ITM_IW *((volatile uint32_t *)0xE0000EF8u) #define ITM_IW_REG *((volatile uint32_t *)0xE0000EF8u) #define ITM_IW_ADDR (0xE0000EF8u) #define ITM_IW_RESET (0x00000000u) - /* ATVALIDM field */ - #define ITM_IW_ATVALIDM (0x00000001u) - #define ITM_IW_ATVALIDM_MASK (0x00000001u) - #define ITM_IW_ATVALIDM_BIT (0) - #define ITM_IW_ATVALIDM_BITS (1) +/* ATVALIDM field */ +#define ITM_IW_ATVALIDM (0x00000001u) +#define ITM_IW_ATVALIDM_MASK (0x00000001u) +#define ITM_IW_ATVALIDM_BIT (0) +#define ITM_IW_ATVALIDM_BITS (1) #define ITM_IR *((volatile uint32_t *)0xE0000EFCu) #define ITM_IR_REG *((volatile uint32_t *)0xE0000EFCu) #define ITM_IR_ADDR (0xE0000EFCu) #define ITM_IR_RESET (0x00000000u) - /* ATREADYM field */ - #define ITM_IR_ATREADYM (0x00000001u) - #define ITM_IR_ATREADYM_MASK (0x00000001u) - #define ITM_IR_ATREADYM_BIT (0) - #define ITM_IR_ATREADYM_BITS (1) +/* ATREADYM field */ +#define ITM_IR_ATREADYM (0x00000001u) +#define ITM_IR_ATREADYM_MASK (0x00000001u) +#define ITM_IR_ATREADYM_BIT (0) +#define ITM_IR_ATREADYM_BITS (1) #define ITM_IMC *((volatile uint32_t *)0xE0000F00u) #define ITM_IMC_REG *((volatile uint32_t *)0xE0000F00u) #define ITM_IMC_ADDR (0xE0000F00u) #define ITM_IMC_RESET (0x00000000u) - /* INTEGRATION field */ - #define ITM_IMC_INTEGRATION (0x00000001u) - #define ITM_IMC_INTEGRATION_MASK (0x00000001u) - #define ITM_IMC_INTEGRATION_BIT (0) - #define ITM_IMC_INTEGRATION_BITS (1) +/* INTEGRATION field */ +#define ITM_IMC_INTEGRATION (0x00000001u) +#define ITM_IMC_INTEGRATION_MASK (0x00000001u) +#define ITM_IMC_INTEGRATION_BIT (0) +#define ITM_IMC_INTEGRATION_BITS (1) #define ITM_LA *((volatile uint32_t *)0xE0000FB0u) #define ITM_LA_REG *((volatile uint32_t *)0xE0000FB0u) #define ITM_LA_ADDR (0xE0000FB0u) #define ITM_LA_RESET (0x00000000u) - /* LOCKACC field */ - #define ITM_LA_LOCKACC (0xFFFFFFFFu) - #define ITM_LA_LOCKACC_MASK (0xFFFFFFFFu) - #define ITM_LA_LOCKACC_BIT (0) - #define ITM_LA_LOCKACC_BITS (32) +/* LOCKACC field */ +#define ITM_LA_LOCKACC (0xFFFFFFFFu) +#define ITM_LA_LOCKACC_MASK (0xFFFFFFFFu) +#define ITM_LA_LOCKACC_BIT (0) +#define ITM_LA_LOCKACC_BITS (32) #define ITM_LS *((volatile uint32_t *)0xE0000FB4u) #define ITM_LS_REG *((volatile uint32_t *)0xE0000FB4u) #define ITM_LS_ADDR (0xE0000FB4u) #define ITM_LS_RESET (0x00000000u) - /* BYTEACC field */ - #define ITM_LS_BYTEACC (0x00000004u) - #define ITM_LS_BYTEACC_MASK (0x00000004u) - #define ITM_LS_BYTEACC_BIT (2) - #define ITM_LS_BYTEACC_BITS (1) - /* ACCESS field */ - #define ITM_LS_ACCESS (0x00000002u) - #define ITM_LS_ACCESS_MASK (0x00000002u) - #define ITM_LS_ACCESS_BIT (1) - #define ITM_LS_ACCESS_BITS (1) - /* PRESENT field */ - #define ITM_LS_PRESENT (0x00000001u) - #define ITM_LS_PRESENT_MASK (0x00000001u) - #define ITM_LS_PRESENT_BIT (0) - #define ITM_LS_PRESENT_BITS (1) +/* BYTEACC field */ +#define ITM_LS_BYTEACC (0x00000004u) +#define ITM_LS_BYTEACC_MASK (0x00000004u) +#define ITM_LS_BYTEACC_BIT (2) +#define ITM_LS_BYTEACC_BITS (1) +/* ACCESS field */ +#define ITM_LS_ACCESS (0x00000002u) +#define ITM_LS_ACCESS_MASK (0x00000002u) +#define ITM_LS_ACCESS_BIT (1) +#define ITM_LS_ACCESS_BITS (1) +/* PRESENT field */ +#define ITM_LS_PRESENT (0x00000001u) +#define ITM_LS_PRESENT_MASK (0x00000001u) +#define ITM_LS_PRESENT_BIT (0) +#define ITM_LS_PRESENT_BITS (1) #define ITM_PERIPHID4 *((volatile uint32_t *)0xE0000FD0u) #define ITM_PERIPHID4_REG *((volatile uint32_t *)0xE0000FD0u) #define ITM_PERIPHID4_ADDR (0xE0000FD0u) #define ITM_PERIPHID4_RESET (0x00000004u) - /* PERIPHID field */ - #define ITM_PERIPHID4_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID4_PERIPHID_BIT (0) - #define ITM_PERIPHID4_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID4_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID4_PERIPHID_BIT (0) +#define ITM_PERIPHID4_PERIPHID_BITS (32) #define ITM_PERIPHID5 *((volatile uint32_t *)0xE0000FD4u) #define ITM_PERIPHID5_REG *((volatile uint32_t *)0xE0000FD4u) #define ITM_PERIPHID5_ADDR (0xE0000FD4u) #define ITM_PERIPHID5_RESET (0x00000000u) - /* PERIPHID field */ - #define ITM_PERIPHID5_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID5_PERIPHID_BIT (0) - #define ITM_PERIPHID5_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID5_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID5_PERIPHID_BIT (0) +#define ITM_PERIPHID5_PERIPHID_BITS (32) #define ITM_PERIPHID6 *((volatile uint32_t *)0xE0000FD8u) #define ITM_PERIPHID6_REG *((volatile uint32_t *)0xE0000FD8u) #define ITM_PERIPHID6_ADDR (0xE0000FD8u) #define ITM_PERIPHID6_RESET (0x00000000u) - /* PERIPHID field */ - #define ITM_PERIPHID6_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID6_PERIPHID_BIT (0) - #define ITM_PERIPHID6_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID6_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID6_PERIPHID_BIT (0) +#define ITM_PERIPHID6_PERIPHID_BITS (32) #define ITM_PERIPHID7 *((volatile uint32_t *)0xE0000FDCu) #define ITM_PERIPHID7_REG *((volatile uint32_t *)0xE0000FDCu) #define ITM_PERIPHID7_ADDR (0xE0000FDCu) #define ITM_PERIPHID7_RESET (0x00000000u) - /* PERIPHID field */ - #define ITM_PERIPHID7_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID7_PERIPHID_BIT (0) - #define ITM_PERIPHID7_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID7_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID7_PERIPHID_BIT (0) +#define ITM_PERIPHID7_PERIPHID_BITS (32) #define ITM_PERIPHID0 *((volatile uint32_t *)0xE0000FE0u) #define ITM_PERIPHID0_REG *((volatile uint32_t *)0xE0000FE0u) #define ITM_PERIPHID0_ADDR (0xE0000FE0u) #define ITM_PERIPHID0_RESET (0x00000001u) - /* PERIPHID field */ - #define ITM_PERIPHID0_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID0_PERIPHID_BIT (0) - #define ITM_PERIPHID0_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID0_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID0_PERIPHID_BIT (0) +#define ITM_PERIPHID0_PERIPHID_BITS (32) #define ITM_PERIPHID1 *((volatile uint32_t *)0xE0000FE4u) #define ITM_PERIPHID1_REG *((volatile uint32_t *)0xE0000FE4u) #define ITM_PERIPHID1_ADDR (0xE0000FE4u) #define ITM_PERIPHID1_RESET (0x000000B0u) - /* PERIPHID field */ - #define ITM_PERIPHID1_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID1_PERIPHID_BIT (0) - #define ITM_PERIPHID1_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID1_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID1_PERIPHID_BIT (0) +#define ITM_PERIPHID1_PERIPHID_BITS (32) #define ITM_PERIPHID2 *((volatile uint32_t *)0xE0000FE8u) #define ITM_PERIPHID2_REG *((volatile uint32_t *)0xE0000FE8u) #define ITM_PERIPHID2_ADDR (0xE0000FE8u) #define ITM_PERIPHID2_RESET (0x0000001Bu) - /* PERIPHID field */ - #define ITM_PERIPHID2_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID2_PERIPHID_BIT (0) - #define ITM_PERIPHID2_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID2_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID2_PERIPHID_BIT (0) +#define ITM_PERIPHID2_PERIPHID_BITS (32) #define ITM_PERIPHID3 *((volatile uint32_t *)0xE0000FECu) #define ITM_PERIPHID3_REG *((volatile uint32_t *)0xE0000FECu) #define ITM_PERIPHID3_ADDR (0xE0000FECu) #define ITM_PERIPHID3_RESET (0x00000000u) - /* PERIPHID field */ - #define ITM_PERIPHID3_PERIPHID (0xFFFFFFFFu) - #define ITM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_PERIPHID3_PERIPHID_BIT (0) - #define ITM_PERIPHID3_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_PERIPHID3_PERIPHID (0xFFFFFFFFu) +#define ITM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_PERIPHID3_PERIPHID_BIT (0) +#define ITM_PERIPHID3_PERIPHID_BITS (32) #define ITM_CELLID0 *((volatile uint32_t *)0xE0000FF0u) #define ITM_CELLID0_REG *((volatile uint32_t *)0xE0000FF0u) #define ITM_CELLID0_ADDR (0xE0000FF0u) #define ITM_CELLID0_RESET (0x0000000Du) - /* PERIPHID field */ - #define ITM_CELLID0_PERIPHID (0xFFFFFFFFu) - #define ITM_CELLID0_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_CELLID0_PERIPHID_BIT (0) - #define ITM_CELLID0_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_CELLID0_PERIPHID (0xFFFFFFFFu) +#define ITM_CELLID0_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_CELLID0_PERIPHID_BIT (0) +#define ITM_CELLID0_PERIPHID_BITS (32) #define ITM_CELLID1 *((volatile uint32_t *)0xE0000FF4u) #define ITM_CELLID1_REG *((volatile uint32_t *)0xE0000FF4u) #define ITM_CELLID1_ADDR (0xE0000FF4u) #define ITM_CELLID1_RESET (0x000000E0u) - /* PERIPHID field */ - #define ITM_CELLID1_PERIPHID (0xFFFFFFFFu) - #define ITM_CELLID1_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_CELLID1_PERIPHID_BIT (0) - #define ITM_CELLID1_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_CELLID1_PERIPHID (0xFFFFFFFFu) +#define ITM_CELLID1_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_CELLID1_PERIPHID_BIT (0) +#define ITM_CELLID1_PERIPHID_BITS (32) #define ITM_CELLID2 *((volatile uint32_t *)0xE0000FF8u) #define ITM_CELLID2_REG *((volatile uint32_t *)0xE0000FF8u) #define ITM_CELLID2_ADDR (0xE0000FF8u) #define ITM_CELLID2_RESET (0x00000005u) - /* PERIPHID field */ - #define ITM_CELLID2_PERIPHID (0xFFFFFFFFu) - #define ITM_CELLID2_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_CELLID2_PERIPHID_BIT (0) - #define ITM_CELLID2_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_CELLID2_PERIPHID (0xFFFFFFFFu) +#define ITM_CELLID2_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_CELLID2_PERIPHID_BIT (0) +#define ITM_CELLID2_PERIPHID_BITS (32) #define ITM_CELLID3 *((volatile uint32_t *)0xE0000FFCu) #define ITM_CELLID3_REG *((volatile uint32_t *)0xE0000FFCu) #define ITM_CELLID3_ADDR (0xE0000FFCu) #define ITM_CELLID3_RESET (0x000000B1u) - /* PERIPHID field */ - #define ITM_CELLID3_PERIPHID (0xFFFFFFFFu) - #define ITM_CELLID3_PERIPHID_MASK (0xFFFFFFFFu) - #define ITM_CELLID3_PERIPHID_BIT (0) - #define ITM_CELLID3_PERIPHID_BITS (32) +/* PERIPHID field */ +#define ITM_CELLID3_PERIPHID (0xFFFFFFFFu) +#define ITM_CELLID3_PERIPHID_MASK (0xFFFFFFFFu) +#define ITM_CELLID3_PERIPHID_BIT (0) +#define ITM_CELLID3_PERIPHID_BITS (32) /* DWT block */ #define DATA_DWT_BASE (0xE0001000u) @@ -8444,456 +8444,456 @@ #define DWT_CTRL_REG *((volatile uint32_t *)0xE0001000u) #define DWT_CTRL_ADDR (0xE0001000u) #define DWT_CTRL_RESET (0x40000000u) - /* NUMCOMP field */ - #define DWT_CTRL_NUMCOMP (0xF0000000u) - #define DWT_CTRL_NUMCOMP_MASK (0xF0000000u) - #define DWT_CTRL_NUMCOMP_BIT (28) - #define DWT_CTRL_NUMCOMP_BITS (4) - /* CYCEVTENA field */ - #define DWT_CTRL_CYCEVTENA (0x00400000u) - #define DWT_CTRL_CYCEVTENA_MASK (0x00400000u) - #define DWT_CTRL_CYCEVTENA_BIT (22) - #define DWT_CTRL_CYCEVTENA_BITS (1) - /* FOLDEVTENA field */ - #define DWT_CTRL_FOLDEVTENA (0x00200000u) - #define DWT_CTRL_FOLDEVTENA_MASK (0x00200000u) - #define DWT_CTRL_FOLDEVTENA_BIT (21) - #define DWT_CTRL_FOLDEVTENA_BITS (1) - /* LSUEVTENA field */ - #define DWT_CTRL_LSUEVTENA (0x00100000u) - #define DWT_CTRL_LSUEVTENA_MASK (0x00100000u) - #define DWT_CTRL_LSUEVTENA_BIT (20) - #define DWT_CTRL_LSUEVTENA_BITS (1) - /* SLEEPEVTENA field */ - #define DWT_CTRL_SLEEPEVTENA (0x00080000u) - #define DWT_CTRL_SLEEPEVTENA_MASK (0x00080000u) - #define DWT_CTRL_SLEEPEVTENA_BIT (19) - #define DWT_CTRL_SLEEPEVTENA_BITS (1) - /* EXCEVTENA field */ - #define DWT_CTRL_EXCEVTENA (0x00040000u) - #define DWT_CTRL_EXCEVTENA_MASK (0x00040000u) - #define DWT_CTRL_EXCEVTENA_BIT (18) - #define DWT_CTRL_EXCEVTENA_BITS (1) - /* CPIEVTENA field */ - #define DWT_CTRL_CPIEVTENA (0x00020000u) - #define DWT_CTRL_CPIEVTENA_MASK (0x00020000u) - #define DWT_CTRL_CPIEVTENA_BIT (17) - #define DWT_CTRL_CPIEVTENA_BITS (1) - /* EXCTRCENA field */ - #define DWT_CTRL_EXCTRCENA (0x00010000u) - #define DWT_CTRL_EXCTRCENA_MASK (0x00010000u) - #define DWT_CTRL_EXCTRCENA_BIT (16) - #define DWT_CTRL_EXCTRCENA_BITS (1) - /* PCSAMPLEENA field */ - #define DWT_CTRL_PCSAMPLEENA (0x00001000u) - #define DWT_CTRL_PCSAMPLEENA_MASK (0x00001000u) - #define DWT_CTRL_PCSAMPLEENA_BIT (12) - #define DWT_CTRL_PCSAMPLEENA_BITS (1) - /* SYNCTAP field */ - #define DWT_CTRL_SYNCTAP (0x00000C00u) - #define DWT_CTRL_SYNCTAP_MASK (0x00000C00u) - #define DWT_CTRL_SYNCTAP_BIT (10) - #define DWT_CTRL_SYNCTAP_BITS (2) - /* CYCTAP field */ - #define DWT_CTRL_CYCTAP (0x00000200u) - #define DWT_CTRL_CYCTAP_MASK (0x00000200u) - #define DWT_CTRL_CYCTAP_BIT (9) - #define DWT_CTRL_CYCTAP_BITS (1) - /* POSTCNT field */ - #define DWT_CTRL_POSTCNT (0x000001E0u) - #define DWT_CTRL_POSTCNT_MASK (0x000001E0u) - #define DWT_CTRL_POSTCNT_BIT (5) - #define DWT_CTRL_POSTCNT_BITS (4) - /* POSTPRESET field */ - #define DWT_CTRL_POSTPRESET (0x0000001Eu) - #define DWT_CTRL_POSTPRESET_MASK (0x0000001Eu) - #define DWT_CTRL_POSTPRESET_BIT (1) - #define DWT_CTRL_POSTPRESET_BITS (4) - /* CYCCNTENA field */ - #define DWT_CTRL_CYCCNTENA (0x00000001u) - #define DWT_CTRL_CYCCNTENA_MASK (0x00000001u) - #define DWT_CTRL_CYCCNTENA_BIT (0) - #define DWT_CTRL_CYCCNTENA_BITS (1) +/* NUMCOMP field */ +#define DWT_CTRL_NUMCOMP (0xF0000000u) +#define DWT_CTRL_NUMCOMP_MASK (0xF0000000u) +#define DWT_CTRL_NUMCOMP_BIT (28) +#define DWT_CTRL_NUMCOMP_BITS (4) +/* CYCEVTENA field */ +#define DWT_CTRL_CYCEVTENA (0x00400000u) +#define DWT_CTRL_CYCEVTENA_MASK (0x00400000u) +#define DWT_CTRL_CYCEVTENA_BIT (22) +#define DWT_CTRL_CYCEVTENA_BITS (1) +/* FOLDEVTENA field */ +#define DWT_CTRL_FOLDEVTENA (0x00200000u) +#define DWT_CTRL_FOLDEVTENA_MASK (0x00200000u) +#define DWT_CTRL_FOLDEVTENA_BIT (21) +#define DWT_CTRL_FOLDEVTENA_BITS (1) +/* LSUEVTENA field */ +#define DWT_CTRL_LSUEVTENA (0x00100000u) +#define DWT_CTRL_LSUEVTENA_MASK (0x00100000u) +#define DWT_CTRL_LSUEVTENA_BIT (20) +#define DWT_CTRL_LSUEVTENA_BITS (1) +/* SLEEPEVTENA field */ +#define DWT_CTRL_SLEEPEVTENA (0x00080000u) +#define DWT_CTRL_SLEEPEVTENA_MASK (0x00080000u) +#define DWT_CTRL_SLEEPEVTENA_BIT (19) +#define DWT_CTRL_SLEEPEVTENA_BITS (1) +/* EXCEVTENA field */ +#define DWT_CTRL_EXCEVTENA (0x00040000u) +#define DWT_CTRL_EXCEVTENA_MASK (0x00040000u) +#define DWT_CTRL_EXCEVTENA_BIT (18) +#define DWT_CTRL_EXCEVTENA_BITS (1) +/* CPIEVTENA field */ +#define DWT_CTRL_CPIEVTENA (0x00020000u) +#define DWT_CTRL_CPIEVTENA_MASK (0x00020000u) +#define DWT_CTRL_CPIEVTENA_BIT (17) +#define DWT_CTRL_CPIEVTENA_BITS (1) +/* EXCTRCENA field */ +#define DWT_CTRL_EXCTRCENA (0x00010000u) +#define DWT_CTRL_EXCTRCENA_MASK (0x00010000u) +#define DWT_CTRL_EXCTRCENA_BIT (16) +#define DWT_CTRL_EXCTRCENA_BITS (1) +/* PCSAMPLEENA field */ +#define DWT_CTRL_PCSAMPLEENA (0x00001000u) +#define DWT_CTRL_PCSAMPLEENA_MASK (0x00001000u) +#define DWT_CTRL_PCSAMPLEENA_BIT (12) +#define DWT_CTRL_PCSAMPLEENA_BITS (1) +/* SYNCTAP field */ +#define DWT_CTRL_SYNCTAP (0x00000C00u) +#define DWT_CTRL_SYNCTAP_MASK (0x00000C00u) +#define DWT_CTRL_SYNCTAP_BIT (10) +#define DWT_CTRL_SYNCTAP_BITS (2) +/* CYCTAP field */ +#define DWT_CTRL_CYCTAP (0x00000200u) +#define DWT_CTRL_CYCTAP_MASK (0x00000200u) +#define DWT_CTRL_CYCTAP_BIT (9) +#define DWT_CTRL_CYCTAP_BITS (1) +/* POSTCNT field */ +#define DWT_CTRL_POSTCNT (0x000001E0u) +#define DWT_CTRL_POSTCNT_MASK (0x000001E0u) +#define DWT_CTRL_POSTCNT_BIT (5) +#define DWT_CTRL_POSTCNT_BITS (4) +/* POSTPRESET field */ +#define DWT_CTRL_POSTPRESET (0x0000001Eu) +#define DWT_CTRL_POSTPRESET_MASK (0x0000001Eu) +#define DWT_CTRL_POSTPRESET_BIT (1) +#define DWT_CTRL_POSTPRESET_BITS (4) +/* CYCCNTENA field */ +#define DWT_CTRL_CYCCNTENA (0x00000001u) +#define DWT_CTRL_CYCCNTENA_MASK (0x00000001u) +#define DWT_CTRL_CYCCNTENA_BIT (0) +#define DWT_CTRL_CYCCNTENA_BITS (1) #define DWT_CYCCNT *((volatile uint32_t *)0xE0001004u) #define DWT_CYCCNT_REG *((volatile uint32_t *)0xE0001004u) #define DWT_CYCCNT_ADDR (0xE0001004u) #define DWT_CYCCNT_RESET (0x00000000u) - /* CYCCNT field */ - #define DWT_CYCCNT_CYCCNT (0xFFFFFFFFu) - #define DWT_CYCCNT_CYCCNT_MASK (0xFFFFFFFFu) - #define DWT_CYCCNT_CYCCNT_BIT (0) - #define DWT_CYCCNT_CYCCNT_BITS (32) +/* CYCCNT field */ +#define DWT_CYCCNT_CYCCNT (0xFFFFFFFFu) +#define DWT_CYCCNT_CYCCNT_MASK (0xFFFFFFFFu) +#define DWT_CYCCNT_CYCCNT_BIT (0) +#define DWT_CYCCNT_CYCCNT_BITS (32) #define DWT_CPICNT *((volatile uint32_t *)0xE0001008u) #define DWT_CPICNT_REG *((volatile uint32_t *)0xE0001008u) #define DWT_CPICNT_ADDR (0xE0001008u) #define DWT_CPICNT_RESET (0x00000000u) - /* CPICNT field */ - #define DWT_CPICNT_CPICNT (0x000000FFu) - #define DWT_CPICNT_CPICNT_MASK (0x000000FFu) - #define DWT_CPICNT_CPICNT_BIT (0) - #define DWT_CPICNT_CPICNT_BITS (8) +/* CPICNT field */ +#define DWT_CPICNT_CPICNT (0x000000FFu) +#define DWT_CPICNT_CPICNT_MASK (0x000000FFu) +#define DWT_CPICNT_CPICNT_BIT (0) +#define DWT_CPICNT_CPICNT_BITS (8) #define DWT_EXCCNT *((volatile uint32_t *)0xE000100Cu) #define DWT_EXCCNT_REG *((volatile uint32_t *)0xE000100Cu) #define DWT_EXCCNT_ADDR (0xE000100Cu) #define DWT_EXCCNT_RESET (0x00000000u) - /* EXCCNT field */ - #define DWT_EXCCNT_EXCCNT (0x000000FFu) - #define DWT_EXCCNT_EXCCNT_MASK (0x000000FFu) - #define DWT_EXCCNT_EXCCNT_BIT (0) - #define DWT_EXCCNT_EXCCNT_BITS (8) +/* EXCCNT field */ +#define DWT_EXCCNT_EXCCNT (0x000000FFu) +#define DWT_EXCCNT_EXCCNT_MASK (0x000000FFu) +#define DWT_EXCCNT_EXCCNT_BIT (0) +#define DWT_EXCCNT_EXCCNT_BITS (8) #define DWT_SLEEPCNT *((volatile uint32_t *)0xE0001010u) #define DWT_SLEEPCNT_REG *((volatile uint32_t *)0xE0001010u) #define DWT_SLEEPCNT_ADDR (0xE0001010u) #define DWT_SLEEPCNT_RESET (0x00000000u) - /* SLEEPCNT field */ - #define DWT_SLEEPCNT_SLEEPCNT (0x000000FFu) - #define DWT_SLEEPCNT_SLEEPCNT_MASK (0x000000FFu) - #define DWT_SLEEPCNT_SLEEPCNT_BIT (0) - #define DWT_SLEEPCNT_SLEEPCNT_BITS (8) +/* SLEEPCNT field */ +#define DWT_SLEEPCNT_SLEEPCNT (0x000000FFu) +#define DWT_SLEEPCNT_SLEEPCNT_MASK (0x000000FFu) +#define DWT_SLEEPCNT_SLEEPCNT_BIT (0) +#define DWT_SLEEPCNT_SLEEPCNT_BITS (8) #define DWT_LSUCNT *((volatile uint32_t *)0xE0001014u) #define DWT_LSUCNT_REG *((volatile uint32_t *)0xE0001014u) #define DWT_LSUCNT_ADDR (0xE0001014u) #define DWT_LSUCNT_RESET (0x00000000u) - /* CPICNT field */ - #define DWT_LSUCNT_CPICNT (0x000000FFu) - #define DWT_LSUCNT_CPICNT_MASK (0x000000FFu) - #define DWT_LSUCNT_CPICNT_BIT (0) - #define DWT_LSUCNT_CPICNT_BITS (8) +/* CPICNT field */ +#define DWT_LSUCNT_CPICNT (0x000000FFu) +#define DWT_LSUCNT_CPICNT_MASK (0x000000FFu) +#define DWT_LSUCNT_CPICNT_BIT (0) +#define DWT_LSUCNT_CPICNT_BITS (8) #define DWT_FOLDCNT *((volatile uint32_t *)0xE0001018u) #define DWT_FOLDCNT_REG *((volatile uint32_t *)0xE0001018u) #define DWT_FOLDCNT_ADDR (0xE0001018u) #define DWT_FOLDCNT_RESET (0x00000000u) - /* CPICNT field */ - #define DWT_FOLDCNT_CPICNT (0x000000FFu) - #define DWT_FOLDCNT_CPICNT_MASK (0x000000FFu) - #define DWT_FOLDCNT_CPICNT_BIT (0) - #define DWT_FOLDCNT_CPICNT_BITS (8) +/* CPICNT field */ +#define DWT_FOLDCNT_CPICNT (0x000000FFu) +#define DWT_FOLDCNT_CPICNT_MASK (0x000000FFu) +#define DWT_FOLDCNT_CPICNT_BIT (0) +#define DWT_FOLDCNT_CPICNT_BITS (8) #define DWT_PCSR *((volatile uint32_t *)0xE000101Cu) #define DWT_PCSR_REG *((volatile uint32_t *)0xE000101Cu) #define DWT_PCSR_ADDR (0xE000101Cu) #define DWT_PCSR_RESET (0x00000000u) - /* EIASAMPLE field */ - #define DWT_PCSR_EIASAMPLE (0xFFFFFFFFu) - #define DWT_PCSR_EIASAMPLE_MASK (0xFFFFFFFFu) - #define DWT_PCSR_EIASAMPLE_BIT (0) - #define DWT_PCSR_EIASAMPLE_BITS (32) +/* EIASAMPLE field */ +#define DWT_PCSR_EIASAMPLE (0xFFFFFFFFu) +#define DWT_PCSR_EIASAMPLE_MASK (0xFFFFFFFFu) +#define DWT_PCSR_EIASAMPLE_BIT (0) +#define DWT_PCSR_EIASAMPLE_BITS (32) #define DWT_COMP0 *((volatile uint32_t *)0xE0001020u) #define DWT_COMP0_REG *((volatile uint32_t *)0xE0001020u) #define DWT_COMP0_ADDR (0xE0001020u) #define DWT_COMP0_RESET (0x00000000u) - /* COMP0 field */ - #define DWT_COMP0_COMP0 (0xFFFFFFFFu) - #define DWT_COMP0_COMP0_MASK (0xFFFFFFFFu) - #define DWT_COMP0_COMP0_BIT (0) - #define DWT_COMP0_COMP0_BITS (32) +/* COMP0 field */ +#define DWT_COMP0_COMP0 (0xFFFFFFFFu) +#define DWT_COMP0_COMP0_MASK (0xFFFFFFFFu) +#define DWT_COMP0_COMP0_BIT (0) +#define DWT_COMP0_COMP0_BITS (32) #define DWT_MASK0 *((volatile uint32_t *)0xE0001024u) #define DWT_MASK0_REG *((volatile uint32_t *)0xE0001024u) #define DWT_MASK0_ADDR (0xE0001024u) #define DWT_MASK0_RESET (0x00000000u) - /* MASK0 field */ - #define DWT_MASK0_MASK0 (0x0000001Fu) - #define DWT_MASK0_MASK0_MASK (0x0000001Fu) - #define DWT_MASK0_MASK0_BIT (0) - #define DWT_MASK0_MASK0_BITS (5) +/* MASK0 field */ +#define DWT_MASK0_MASK0 (0x0000001Fu) +#define DWT_MASK0_MASK0_MASK (0x0000001Fu) +#define DWT_MASK0_MASK0_BIT (0) +#define DWT_MASK0_MASK0_BITS (5) #define DWT_FUNCTION0 *((volatile uint32_t *)0xE0001028u) #define DWT_FUNCTION0_REG *((volatile uint32_t *)0xE0001028u) #define DWT_FUNCTION0_ADDR (0xE0001028u) #define DWT_FUNCTION0_RESET (0x00000000u) - /* MATCHED field */ - #define DWT_FUNCTION0_MATCHED (0x01000000u) - #define DWT_FUNCTION0_MATCHED_MASK (0x01000000u) - #define DWT_FUNCTION0_MATCHED_BIT (24) - #define DWT_FUNCTION0_MATCHED_BITS (1) - /* CYCMATCH field */ - #define DWT_FUNCTION0_CYCMATCH (0x00000080u) - #define DWT_FUNCTION0_CYCMATCH_MASK (0x00000080u) - #define DWT_FUNCTION0_CYCMATCH_BIT (7) - #define DWT_FUNCTION0_CYCMATCH_BITS (1) - /* EMITRANGE field */ - #define DWT_FUNCTION0_EMITRANGE (0x00000020u) - #define DWT_FUNCTION0_EMITRANGE_MASK (0x00000020u) - #define DWT_FUNCTION0_EMITRANGE_BIT (5) - #define DWT_FUNCTION0_EMITRANGE_BITS (1) - /* FUNCTION field */ - #define DWT_FUNCTION0_FUNCTION (0x0000000Fu) - #define DWT_FUNCTION0_FUNCTION_MASK (0x0000000Fu) - #define DWT_FUNCTION0_FUNCTION_BIT (0) - #define DWT_FUNCTION0_FUNCTION_BITS (4) +/* MATCHED field */ +#define DWT_FUNCTION0_MATCHED (0x01000000u) +#define DWT_FUNCTION0_MATCHED_MASK (0x01000000u) +#define DWT_FUNCTION0_MATCHED_BIT (24) +#define DWT_FUNCTION0_MATCHED_BITS (1) +/* CYCMATCH field */ +#define DWT_FUNCTION0_CYCMATCH (0x00000080u) +#define DWT_FUNCTION0_CYCMATCH_MASK (0x00000080u) +#define DWT_FUNCTION0_CYCMATCH_BIT (7) +#define DWT_FUNCTION0_CYCMATCH_BITS (1) +/* EMITRANGE field */ +#define DWT_FUNCTION0_EMITRANGE (0x00000020u) +#define DWT_FUNCTION0_EMITRANGE_MASK (0x00000020u) +#define DWT_FUNCTION0_EMITRANGE_BIT (5) +#define DWT_FUNCTION0_EMITRANGE_BITS (1) +/* FUNCTION field */ +#define DWT_FUNCTION0_FUNCTION (0x0000000Fu) +#define DWT_FUNCTION0_FUNCTION_MASK (0x0000000Fu) +#define DWT_FUNCTION0_FUNCTION_BIT (0) +#define DWT_FUNCTION0_FUNCTION_BITS (4) #define DWT_COMP1 *((volatile uint32_t *)0xE0001030u) #define DWT_COMP1_REG *((volatile uint32_t *)0xE0001030u) #define DWT_COMP1_ADDR (0xE0001030u) #define DWT_COMP1_RESET (0x00000000u) - /* COMP1 field */ - #define DWT_COMP1_COMP1 (0xFFFFFFFFu) - #define DWT_COMP1_COMP1_MASK (0xFFFFFFFFu) - #define DWT_COMP1_COMP1_BIT (0) - #define DWT_COMP1_COMP1_BITS (32) +/* COMP1 field */ +#define DWT_COMP1_COMP1 (0xFFFFFFFFu) +#define DWT_COMP1_COMP1_MASK (0xFFFFFFFFu) +#define DWT_COMP1_COMP1_BIT (0) +#define DWT_COMP1_COMP1_BITS (32) #define DWT_MASK1 *((volatile uint32_t *)0xE0001034u) #define DWT_MASK1_REG *((volatile uint32_t *)0xE0001034u) #define DWT_MASK1_ADDR (0xE0001034u) #define DWT_MASK1_RESET (0x00000000u) - /* MASK1 field */ - #define DWT_MASK1_MASK1 (0x0000001Fu) - #define DWT_MASK1_MASK1_MASK (0x0000001Fu) - #define DWT_MASK1_MASK1_BIT (0) - #define DWT_MASK1_MASK1_BITS (5) +/* MASK1 field */ +#define DWT_MASK1_MASK1 (0x0000001Fu) +#define DWT_MASK1_MASK1_MASK (0x0000001Fu) +#define DWT_MASK1_MASK1_BIT (0) +#define DWT_MASK1_MASK1_BITS (5) #define DWT_FUNCTION1 *((volatile uint32_t *)0xE0001038u) #define DWT_FUNCTION1_REG *((volatile uint32_t *)0xE0001038u) #define DWT_FUNCTION1_ADDR (0xE0001038u) #define DWT_FUNCTION1_RESET (0x00000200u) - /* MATCHED field */ - #define DWT_FUNCTION1_MATCHED (0x01000000u) - #define DWT_FUNCTION1_MATCHED_MASK (0x01000000u) - #define DWT_FUNCTION1_MATCHED_BIT (24) - #define DWT_FUNCTION1_MATCHED_BITS (1) - /* DATAVADDR1 field */ - #define DWT_FUNCTION1_DATAVADDR1 (0x000F0000u) - #define DWT_FUNCTION1_DATAVADDR1_MASK (0x000F0000u) - #define DWT_FUNCTION1_DATAVADDR1_BIT (16) - #define DWT_FUNCTION1_DATAVADDR1_BITS (4) - /* DATAVADDR0 field */ - #define DWT_FUNCTION1_DATAVADDR0 (0x0000F000u) - #define DWT_FUNCTION1_DATAVADDR0_MASK (0x0000F000u) - #define DWT_FUNCTION1_DATAVADDR0_BIT (12) - #define DWT_FUNCTION1_DATAVADDR0_BITS (4) - /* DATAVSIZE field */ - #define DWT_FUNCTION1_DATAVSIZE (0x00000C00u) - #define DWT_FUNCTION1_DATAVSIZE_MASK (0x00000C00u) - #define DWT_FUNCTION1_DATAVSIZE_BIT (10) - #define DWT_FUNCTION1_DATAVSIZE_BITS (2) - /* LNK1ENA field */ - #define DWT_FUNCTION1_LNK1ENA (0x00000200u) - #define DWT_FUNCTION1_LNK1ENA_MASK (0x00000200u) - #define DWT_FUNCTION1_LNK1ENA_BIT (9) - #define DWT_FUNCTION1_LNK1ENA_BITS (1) - /* DATAVMATCH field */ - #define DWT_FUNCTION1_DATAVMATCH (0x00000100u) - #define DWT_FUNCTION1_DATAVMATCH_MASK (0x00000100u) - #define DWT_FUNCTION1_DATAVMATCH_BIT (8) - #define DWT_FUNCTION1_DATAVMATCH_BITS (1) - /* EMITRANGE field */ - #define DWT_FUNCTION1_EMITRANGE (0x00000020u) - #define DWT_FUNCTION1_EMITRANGE_MASK (0x00000020u) - #define DWT_FUNCTION1_EMITRANGE_BIT (5) - #define DWT_FUNCTION1_EMITRANGE_BITS (1) - /* FUNCTION field */ - #define DWT_FUNCTION1_FUNCTION (0x0000000Fu) - #define DWT_FUNCTION1_FUNCTION_MASK (0x0000000Fu) - #define DWT_FUNCTION1_FUNCTION_BIT (0) - #define DWT_FUNCTION1_FUNCTION_BITS (4) +/* MATCHED field */ +#define DWT_FUNCTION1_MATCHED (0x01000000u) +#define DWT_FUNCTION1_MATCHED_MASK (0x01000000u) +#define DWT_FUNCTION1_MATCHED_BIT (24) +#define DWT_FUNCTION1_MATCHED_BITS (1) +/* DATAVADDR1 field */ +#define DWT_FUNCTION1_DATAVADDR1 (0x000F0000u) +#define DWT_FUNCTION1_DATAVADDR1_MASK (0x000F0000u) +#define DWT_FUNCTION1_DATAVADDR1_BIT (16) +#define DWT_FUNCTION1_DATAVADDR1_BITS (4) +/* DATAVADDR0 field */ +#define DWT_FUNCTION1_DATAVADDR0 (0x0000F000u) +#define DWT_FUNCTION1_DATAVADDR0_MASK (0x0000F000u) +#define DWT_FUNCTION1_DATAVADDR0_BIT (12) +#define DWT_FUNCTION1_DATAVADDR0_BITS (4) +/* DATAVSIZE field */ +#define DWT_FUNCTION1_DATAVSIZE (0x00000C00u) +#define DWT_FUNCTION1_DATAVSIZE_MASK (0x00000C00u) +#define DWT_FUNCTION1_DATAVSIZE_BIT (10) +#define DWT_FUNCTION1_DATAVSIZE_BITS (2) +/* LNK1ENA field */ +#define DWT_FUNCTION1_LNK1ENA (0x00000200u) +#define DWT_FUNCTION1_LNK1ENA_MASK (0x00000200u) +#define DWT_FUNCTION1_LNK1ENA_BIT (9) +#define DWT_FUNCTION1_LNK1ENA_BITS (1) +/* DATAVMATCH field */ +#define DWT_FUNCTION1_DATAVMATCH (0x00000100u) +#define DWT_FUNCTION1_DATAVMATCH_MASK (0x00000100u) +#define DWT_FUNCTION1_DATAVMATCH_BIT (8) +#define DWT_FUNCTION1_DATAVMATCH_BITS (1) +/* EMITRANGE field */ +#define DWT_FUNCTION1_EMITRANGE (0x00000020u) +#define DWT_FUNCTION1_EMITRANGE_MASK (0x00000020u) +#define DWT_FUNCTION1_EMITRANGE_BIT (5) +#define DWT_FUNCTION1_EMITRANGE_BITS (1) +/* FUNCTION field */ +#define DWT_FUNCTION1_FUNCTION (0x0000000Fu) +#define DWT_FUNCTION1_FUNCTION_MASK (0x0000000Fu) +#define DWT_FUNCTION1_FUNCTION_BIT (0) +#define DWT_FUNCTION1_FUNCTION_BITS (4) #define DWT_COMP2 *((volatile uint32_t *)0xE0001040u) #define DWT_COMP2_REG *((volatile uint32_t *)0xE0001040u) #define DWT_COMP2_ADDR (0xE0001040u) #define DWT_COMP2_RESET (0x00000000u) - /* COMP2 field */ - #define DWT_COMP2_COMP2 (0xFFFFFFFFu) - #define DWT_COMP2_COMP2_MASK (0xFFFFFFFFu) - #define DWT_COMP2_COMP2_BIT (0) - #define DWT_COMP2_COMP2_BITS (32) +/* COMP2 field */ +#define DWT_COMP2_COMP2 (0xFFFFFFFFu) +#define DWT_COMP2_COMP2_MASK (0xFFFFFFFFu) +#define DWT_COMP2_COMP2_BIT (0) +#define DWT_COMP2_COMP2_BITS (32) #define DWT_MASK2 *((volatile uint32_t *)0xE0001044u) #define DWT_MASK2_REG *((volatile uint32_t *)0xE0001044u) #define DWT_MASK2_ADDR (0xE0001044u) #define DWT_MASK2_RESET (0x00000000u) - /* MASK2 field */ - #define DWT_MASK2_MASK2 (0x0000001Fu) - #define DWT_MASK2_MASK2_MASK (0x0000001Fu) - #define DWT_MASK2_MASK2_BIT (0) - #define DWT_MASK2_MASK2_BITS (5) +/* MASK2 field */ +#define DWT_MASK2_MASK2 (0x0000001Fu) +#define DWT_MASK2_MASK2_MASK (0x0000001Fu) +#define DWT_MASK2_MASK2_BIT (0) +#define DWT_MASK2_MASK2_BITS (5) #define DWT_FUNCTION2 *((volatile uint32_t *)0xE0001048u) #define DWT_FUNCTION2_REG *((volatile uint32_t *)0xE0001048u) #define DWT_FUNCTION2_ADDR (0xE0001048u) #define DWT_FUNCTION2_RESET (0x00000000u) - /* MATCHED field */ - #define DWT_FUNCTION2_MATCHED (0x01000000u) - #define DWT_FUNCTION2_MATCHED_MASK (0x01000000u) - #define DWT_FUNCTION2_MATCHED_BIT (24) - #define DWT_FUNCTION2_MATCHED_BITS (1) - /* EMITRANGE field */ - #define DWT_FUNCTION2_EMITRANGE (0x00000020u) - #define DWT_FUNCTION2_EMITRANGE_MASK (0x00000020u) - #define DWT_FUNCTION2_EMITRANGE_BIT (5) - #define DWT_FUNCTION2_EMITRANGE_BITS (1) - /* FUNCTION field */ - #define DWT_FUNCTION2_FUNCTION (0x0000000Fu) - #define DWT_FUNCTION2_FUNCTION_MASK (0x0000000Fu) - #define DWT_FUNCTION2_FUNCTION_BIT (0) - #define DWT_FUNCTION2_FUNCTION_BITS (4) +/* MATCHED field */ +#define DWT_FUNCTION2_MATCHED (0x01000000u) +#define DWT_FUNCTION2_MATCHED_MASK (0x01000000u) +#define DWT_FUNCTION2_MATCHED_BIT (24) +#define DWT_FUNCTION2_MATCHED_BITS (1) +/* EMITRANGE field */ +#define DWT_FUNCTION2_EMITRANGE (0x00000020u) +#define DWT_FUNCTION2_EMITRANGE_MASK (0x00000020u) +#define DWT_FUNCTION2_EMITRANGE_BIT (5) +#define DWT_FUNCTION2_EMITRANGE_BITS (1) +/* FUNCTION field */ +#define DWT_FUNCTION2_FUNCTION (0x0000000Fu) +#define DWT_FUNCTION2_FUNCTION_MASK (0x0000000Fu) +#define DWT_FUNCTION2_FUNCTION_BIT (0) +#define DWT_FUNCTION2_FUNCTION_BITS (4) #define DWT_COMP3 *((volatile uint32_t *)0xE0001050u) #define DWT_COMP3_REG *((volatile uint32_t *)0xE0001050u) #define DWT_COMP3_ADDR (0xE0001050u) #define DWT_COMP3_RESET (0x00000000u) - /* COMP3 field */ - #define DWT_COMP3_COMP3 (0xFFFFFFFFu) - #define DWT_COMP3_COMP3_MASK (0xFFFFFFFFu) - #define DWT_COMP3_COMP3_BIT (0) - #define DWT_COMP3_COMP3_BITS (32) +/* COMP3 field */ +#define DWT_COMP3_COMP3 (0xFFFFFFFFu) +#define DWT_COMP3_COMP3_MASK (0xFFFFFFFFu) +#define DWT_COMP3_COMP3_BIT (0) +#define DWT_COMP3_COMP3_BITS (32) #define DWT_MASK3 *((volatile uint32_t *)0xE0001054u) #define DWT_MASK3_REG *((volatile uint32_t *)0xE0001054u) #define DWT_MASK3_ADDR (0xE0001054u) #define DWT_MASK3_RESET (0x00000000u) - /* MASK3 field */ - #define DWT_MASK3_MASK3 (0x0000001Fu) - #define DWT_MASK3_MASK3_MASK (0x0000001Fu) - #define DWT_MASK3_MASK3_BIT (0) - #define DWT_MASK3_MASK3_BITS (5) +/* MASK3 field */ +#define DWT_MASK3_MASK3 (0x0000001Fu) +#define DWT_MASK3_MASK3_MASK (0x0000001Fu) +#define DWT_MASK3_MASK3_BIT (0) +#define DWT_MASK3_MASK3_BITS (5) #define DWT_FUNCTION3 *((volatile uint32_t *)0xE0001058u) #define DWT_FUNCTION3_REG *((volatile uint32_t *)0xE0001058u) #define DWT_FUNCTION3_ADDR (0xE0001058u) #define DWT_FUNCTION3_RESET (0x00000000u) - /* MATCHED field */ - #define DWT_FUNCTION3_MATCHED (0x01000000u) - #define DWT_FUNCTION3_MATCHED_MASK (0x01000000u) - #define DWT_FUNCTION3_MATCHED_BIT (24) - #define DWT_FUNCTION3_MATCHED_BITS (1) - /* EMITRANGE field */ - #define DWT_FUNCTION3_EMITRANGE (0x00000020u) - #define DWT_FUNCTION3_EMITRANGE_MASK (0x00000020u) - #define DWT_FUNCTION3_EMITRANGE_BIT (5) - #define DWT_FUNCTION3_EMITRANGE_BITS (1) - /* FUNCTION field */ - #define DWT_FUNCTION3_FUNCTION (0x0000000Fu) - #define DWT_FUNCTION3_FUNCTION_MASK (0x0000000Fu) - #define DWT_FUNCTION3_FUNCTION_BIT (0) - #define DWT_FUNCTION3_FUNCTION_BITS (4) +/* MATCHED field */ +#define DWT_FUNCTION3_MATCHED (0x01000000u) +#define DWT_FUNCTION3_MATCHED_MASK (0x01000000u) +#define DWT_FUNCTION3_MATCHED_BIT (24) +#define DWT_FUNCTION3_MATCHED_BITS (1) +/* EMITRANGE field */ +#define DWT_FUNCTION3_EMITRANGE (0x00000020u) +#define DWT_FUNCTION3_EMITRANGE_MASK (0x00000020u) +#define DWT_FUNCTION3_EMITRANGE_BIT (5) +#define DWT_FUNCTION3_EMITRANGE_BITS (1) +/* FUNCTION field */ +#define DWT_FUNCTION3_FUNCTION (0x0000000Fu) +#define DWT_FUNCTION3_FUNCTION_MASK (0x0000000Fu) +#define DWT_FUNCTION3_FUNCTION_BIT (0) +#define DWT_FUNCTION3_FUNCTION_BITS (4) #define DWT_PERIPHID4 *((volatile uint32_t *)0xE0001FD0u) #define DWT_PERIPHID4_REG *((volatile uint32_t *)0xE0001FD0u) #define DWT_PERIPHID4_ADDR (0xE0001FD0u) #define DWT_PERIPHID4_RESET (0x00000004u) - /* PERIPHID field */ - #define DWT_PERIPHID4_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID4_PERIPHID_BIT (0) - #define DWT_PERIPHID4_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID4_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID4_PERIPHID_BIT (0) +#define DWT_PERIPHID4_PERIPHID_BITS (32) #define DWT_PERIPHID5 *((volatile uint32_t *)0xE0001FD4u) #define DWT_PERIPHID5_REG *((volatile uint32_t *)0xE0001FD4u) #define DWT_PERIPHID5_ADDR (0xE0001FD4u) #define DWT_PERIPHID5_RESET (0x00000000u) - /* PERIPHID field */ - #define DWT_PERIPHID5_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID5_PERIPHID_BIT (0) - #define DWT_PERIPHID5_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID5_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID5_PERIPHID_BIT (0) +#define DWT_PERIPHID5_PERIPHID_BITS (32) #define DWT_PERIPHID6 *((volatile uint32_t *)0xE0001FD8u) #define DWT_PERIPHID6_REG *((volatile uint32_t *)0xE0001FD8u) #define DWT_PERIPHID6_ADDR (0xE0001FD8u) #define DWT_PERIPHID6_RESET (0x00000000u) - /* PERIPHID field */ - #define DWT_PERIPHID6_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID6_PERIPHID_BIT (0) - #define DWT_PERIPHID6_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID6_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID6_PERIPHID_BIT (0) +#define DWT_PERIPHID6_PERIPHID_BITS (32) #define DWT_PERIPHID7 *((volatile uint32_t *)0xE0001FDCu) #define DWT_PERIPHID7_REG *((volatile uint32_t *)0xE0001FDCu) #define DWT_PERIPHID7_ADDR (0xE0001FDCu) #define DWT_PERIPHID7_RESET (0x00000000u) - /* PERIPHID field */ - #define DWT_PERIPHID7_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID7_PERIPHID_BIT (0) - #define DWT_PERIPHID7_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID7_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID7_PERIPHID_BIT (0) +#define DWT_PERIPHID7_PERIPHID_BITS (32) #define DWT_PERIPHID0 *((volatile uint32_t *)0xE0001FE0u) #define DWT_PERIPHID0_REG *((volatile uint32_t *)0xE0001FE0u) #define DWT_PERIPHID0_ADDR (0xE0001FE0u) #define DWT_PERIPHID0_RESET (0x00000002u) - /* PERIPHID field */ - #define DWT_PERIPHID0_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID0_PERIPHID_BIT (0) - #define DWT_PERIPHID0_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID0_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID0_PERIPHID_BIT (0) +#define DWT_PERIPHID0_PERIPHID_BITS (32) #define DWT_PERIPHID1 *((volatile uint32_t *)0xE0001FE4u) #define DWT_PERIPHID1_REG *((volatile uint32_t *)0xE0001FE4u) #define DWT_PERIPHID1_ADDR (0xE0001FE4u) #define DWT_PERIPHID1_RESET (0x00000000u) - /* PERIPHID field */ - #define DWT_PERIPHID1_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID1_PERIPHID_BIT (0) - #define DWT_PERIPHID1_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID1_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID1_PERIPHID_BIT (0) +#define DWT_PERIPHID1_PERIPHID_BITS (32) #define DWT_PERIPHID2 *((volatile uint32_t *)0xE0001FE8u) #define DWT_PERIPHID2_REG *((volatile uint32_t *)0xE0001FE8u) #define DWT_PERIPHID2_ADDR (0xE0001FE8u) #define DWT_PERIPHID2_RESET (0x0000001Bu) - /* PERIPHID field */ - #define DWT_PERIPHID2_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID2_PERIPHID_BIT (0) - #define DWT_PERIPHID2_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID2_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID2_PERIPHID_BIT (0) +#define DWT_PERIPHID2_PERIPHID_BITS (32) #define DWT_PERIPHID3 *((volatile uint32_t *)0xE0001FECu) #define DWT_PERIPHID3_REG *((volatile uint32_t *)0xE0001FECu) #define DWT_PERIPHID3_ADDR (0xE0001FECu) #define DWT_PERIPHID3_RESET (0x00000000u) - /* PERIPHID field */ - #define DWT_PERIPHID3_PERIPHID (0xFFFFFFFFu) - #define DWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) - #define DWT_PERIPHID3_PERIPHID_BIT (0) - #define DWT_PERIPHID3_PERIPHID_BITS (32) +/* PERIPHID field */ +#define DWT_PERIPHID3_PERIPHID (0xFFFFFFFFu) +#define DWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) +#define DWT_PERIPHID3_PERIPHID_BIT (0) +#define DWT_PERIPHID3_PERIPHID_BITS (32) #define DWT_CELLID0 *((volatile uint32_t *)0xE0001FF0u) #define DWT_CELLID0_REG *((volatile uint32_t *)0xE0001FF0u) #define DWT_CELLID0_ADDR (0xE0001FF0u) #define DWT_CELLID0_RESET (0x0000000Du) - /* CELLID field */ - #define DWT_CELLID0_CELLID (0xFFFFFFFFu) - #define DWT_CELLID0_CELLID_MASK (0xFFFFFFFFu) - #define DWT_CELLID0_CELLID_BIT (0) - #define DWT_CELLID0_CELLID_BITS (32) +/* CELLID field */ +#define DWT_CELLID0_CELLID (0xFFFFFFFFu) +#define DWT_CELLID0_CELLID_MASK (0xFFFFFFFFu) +#define DWT_CELLID0_CELLID_BIT (0) +#define DWT_CELLID0_CELLID_BITS (32) #define DWT_CELLID1 *((volatile uint32_t *)0xE0001FF4u) #define DWT_CELLID1_REG *((volatile uint32_t *)0xE0001FF4u) #define DWT_CELLID1_ADDR (0xE0001FF4u) #define DWT_CELLID1_RESET (0x000000E0u) - /* CELLID field */ - #define DWT_CELLID1_CELLID (0xFFFFFFFFu) - #define DWT_CELLID1_CELLID_MASK (0xFFFFFFFFu) - #define DWT_CELLID1_CELLID_BIT (0) - #define DWT_CELLID1_CELLID_BITS (32) +/* CELLID field */ +#define DWT_CELLID1_CELLID (0xFFFFFFFFu) +#define DWT_CELLID1_CELLID_MASK (0xFFFFFFFFu) +#define DWT_CELLID1_CELLID_BIT (0) +#define DWT_CELLID1_CELLID_BITS (32) #define DWT_CELLID2 *((volatile uint32_t *)0xE0001FF8u) #define DWT_CELLID2_REG *((volatile uint32_t *)0xE0001FF8u) #define DWT_CELLID2_ADDR (0xE0001FF8u) #define DWT_CELLID2_RESET (0x00000005u) - /* CELLID field */ - #define DWT_CELLID2_CELLID (0xFFFFFFFFu) - #define DWT_CELLID2_CELLID_MASK (0xFFFFFFFFu) - #define DWT_CELLID2_CELLID_BIT (0) - #define DWT_CELLID2_CELLID_BITS (32) +/* CELLID field */ +#define DWT_CELLID2_CELLID (0xFFFFFFFFu) +#define DWT_CELLID2_CELLID_MASK (0xFFFFFFFFu) +#define DWT_CELLID2_CELLID_BIT (0) +#define DWT_CELLID2_CELLID_BITS (32) #define DWT_CELLID3 *((volatile uint32_t *)0xE0001FFCu) #define DWT_CELLID3_REG *((volatile uint32_t *)0xE0001FFCu) #define DWT_CELLID3_ADDR (0xE0001FFCu) #define DWT_CELLID3_RESET (0x000000B1u) - /* CELLID field */ - #define DWT_CELLID3_CELLID (0xFFFFFFFFu) - #define DWT_CELLID3_CELLID_MASK (0xFFFFFFFFu) - #define DWT_CELLID3_CELLID_BIT (0) - #define DWT_CELLID3_CELLID_BITS (32) +/* CELLID field */ +#define DWT_CELLID3_CELLID (0xFFFFFFFFu) +#define DWT_CELLID3_CELLID_MASK (0xFFFFFFFFu) +#define DWT_CELLID3_CELLID_BIT (0) +#define DWT_CELLID3_CELLID_BITS (32) /* FPB block */ #define DATA_FPB_BASE (0xE0002000u) @@ -8904,316 +8904,316 @@ #define FPB_CTRL_REG *((volatile uint32_t *)0xE0002000u) #define FPB_CTRL_ADDR (0xE0002000u) #define FPB_CTRL_RESET (0x00000000u) - /* NUM_LIT field */ - #define FPB_CTRL_NUM_LIT (0x00000F00u) - #define FPB_CTRL_NUM_LIT_MASK (0x00000F00u) - #define FPB_CTRL_NUM_LIT_BIT (8) - #define FPB_CTRL_NUM_LIT_BITS (4) - /* NUM_CODE field */ - #define FPB_CTRL_NUM_CODE (0x000000F0u) - #define FPB_CTRL_NUM_CODE_MASK (0x000000F0u) - #define FPB_CTRL_NUM_CODE_BIT (4) - #define FPB_CTRL_NUM_CODE_BITS (4) - /* KEY field */ - #define FPB_CTRL_KEY (0x00000002u) - #define FPB_CTRL_KEY_MASK (0x00000002u) - #define FPB_CTRL_KEY_BIT (1) - #define FPB_CTRL_KEY_BITS (1) - /* enable field */ - #define FPB_CTRL_enable (0x00000001u) - #define FPB_CTRL_enable_MASK (0x00000001u) - #define FPB_CTRL_enable_BIT (0) - #define FPB_CTRL_enable_BITS (1) +/* NUM_LIT field */ +#define FPB_CTRL_NUM_LIT (0x00000F00u) +#define FPB_CTRL_NUM_LIT_MASK (0x00000F00u) +#define FPB_CTRL_NUM_LIT_BIT (8) +#define FPB_CTRL_NUM_LIT_BITS (4) +/* NUM_CODE field */ +#define FPB_CTRL_NUM_CODE (0x000000F0u) +#define FPB_CTRL_NUM_CODE_MASK (0x000000F0u) +#define FPB_CTRL_NUM_CODE_BIT (4) +#define FPB_CTRL_NUM_CODE_BITS (4) +/* KEY field */ +#define FPB_CTRL_KEY (0x00000002u) +#define FPB_CTRL_KEY_MASK (0x00000002u) +#define FPB_CTRL_KEY_BIT (1) +#define FPB_CTRL_KEY_BITS (1) +/* enable field */ +#define FPB_CTRL_enable (0x00000001u) +#define FPB_CTRL_enable_MASK (0x00000001u) +#define FPB_CTRL_enable_BIT (0) +#define FPB_CTRL_enable_BITS (1) #define FPB_REMAP *((volatile uint32_t *)0xE0002004u) #define FPB_REMAP_REG *((volatile uint32_t *)0xE0002004u) #define FPB_REMAP_ADDR (0xE0002004u) #define FPB_REMAP_RESET (0x20000000u) - /* REMAP field */ - #define FPB_REMAP_REMAP (0x1FFFFFE0u) - #define FPB_REMAP_REMAP_MASK (0x1FFFFFE0u) - #define FPB_REMAP_REMAP_BIT (5) - #define FPB_REMAP_REMAP_BITS (24) +/* REMAP field */ +#define FPB_REMAP_REMAP (0x1FFFFFE0u) +#define FPB_REMAP_REMAP_MASK (0x1FFFFFE0u) +#define FPB_REMAP_REMAP_BIT (5) +#define FPB_REMAP_REMAP_BITS (24) #define FPB_COMP0 *((volatile uint32_t *)0xE0002008u) #define FPB_COMP0_REG *((volatile uint32_t *)0xE0002008u) #define FPB_COMP0_ADDR (0xE0002008u) #define FPB_COMP0_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP0_REPLACE (0xC0000000u) - #define FPB_COMP0_REPLACE_MASK (0xC0000000u) - #define FPB_COMP0_REPLACE_BIT (30) - #define FPB_COMP0_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP0_COMP (0x1FFFFFFCu) - #define FPB_COMP0_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP0_COMP_BIT (2) - #define FPB_COMP0_COMP_BITS (27) - /* enable field */ - #define FPB_COMP0_enable (0x00000001u) - #define FPB_COMP0_enable_MASK (0x00000001u) - #define FPB_COMP0_enable_BIT (0) - #define FPB_COMP0_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP0_REPLACE (0xC0000000u) +#define FPB_COMP0_REPLACE_MASK (0xC0000000u) +#define FPB_COMP0_REPLACE_BIT (30) +#define FPB_COMP0_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP0_COMP (0x1FFFFFFCu) +#define FPB_COMP0_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP0_COMP_BIT (2) +#define FPB_COMP0_COMP_BITS (27) +/* enable field */ +#define FPB_COMP0_enable (0x00000001u) +#define FPB_COMP0_enable_MASK (0x00000001u) +#define FPB_COMP0_enable_BIT (0) +#define FPB_COMP0_enable_BITS (1) #define FPB_COMP1 *((volatile uint32_t *)0xE000200Cu) #define FPB_COMP1_REG *((volatile uint32_t *)0xE000200Cu) #define FPB_COMP1_ADDR (0xE000200Cu) #define FPB_COMP1_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP1_REPLACE (0xC0000000u) - #define FPB_COMP1_REPLACE_MASK (0xC0000000u) - #define FPB_COMP1_REPLACE_BIT (30) - #define FPB_COMP1_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP1_COMP (0x1FFFFFFCu) - #define FPB_COMP1_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP1_COMP_BIT (2) - #define FPB_COMP1_COMP_BITS (27) - /* enable field */ - #define FPB_COMP1_enable (0x00000001u) - #define FPB_COMP1_enable_MASK (0x00000001u) - #define FPB_COMP1_enable_BIT (0) - #define FPB_COMP1_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP1_REPLACE (0xC0000000u) +#define FPB_COMP1_REPLACE_MASK (0xC0000000u) +#define FPB_COMP1_REPLACE_BIT (30) +#define FPB_COMP1_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP1_COMP (0x1FFFFFFCu) +#define FPB_COMP1_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP1_COMP_BIT (2) +#define FPB_COMP1_COMP_BITS (27) +/* enable field */ +#define FPB_COMP1_enable (0x00000001u) +#define FPB_COMP1_enable_MASK (0x00000001u) +#define FPB_COMP1_enable_BIT (0) +#define FPB_COMP1_enable_BITS (1) #define FPB_COMP2 *((volatile uint32_t *)0xE0002010u) #define FPB_COMP2_REG *((volatile uint32_t *)0xE0002010u) #define FPB_COMP2_ADDR (0xE0002010u) #define FPB_COMP2_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP2_REPLACE (0xC0000000u) - #define FPB_COMP2_REPLACE_MASK (0xC0000000u) - #define FPB_COMP2_REPLACE_BIT (30) - #define FPB_COMP2_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP2_COMP (0x1FFFFFFCu) - #define FPB_COMP2_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP2_COMP_BIT (2) - #define FPB_COMP2_COMP_BITS (27) - /* enable field */ - #define FPB_COMP2_enable (0x00000001u) - #define FPB_COMP2_enable_MASK (0x00000001u) - #define FPB_COMP2_enable_BIT (0) - #define FPB_COMP2_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP2_REPLACE (0xC0000000u) +#define FPB_COMP2_REPLACE_MASK (0xC0000000u) +#define FPB_COMP2_REPLACE_BIT (30) +#define FPB_COMP2_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP2_COMP (0x1FFFFFFCu) +#define FPB_COMP2_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP2_COMP_BIT (2) +#define FPB_COMP2_COMP_BITS (27) +/* enable field */ +#define FPB_COMP2_enable (0x00000001u) +#define FPB_COMP2_enable_MASK (0x00000001u) +#define FPB_COMP2_enable_BIT (0) +#define FPB_COMP2_enable_BITS (1) #define FPB_COMP3 *((volatile uint32_t *)0xE0002014u) #define FPB_COMP3_REG *((volatile uint32_t *)0xE0002014u) #define FPB_COMP3_ADDR (0xE0002014u) #define FPB_COMP3_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP3_REPLACE (0xC0000000u) - #define FPB_COMP3_REPLACE_MASK (0xC0000000u) - #define FPB_COMP3_REPLACE_BIT (30) - #define FPB_COMP3_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP3_COMP (0x1FFFFFFCu) - #define FPB_COMP3_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP3_COMP_BIT (2) - #define FPB_COMP3_COMP_BITS (27) - /* enable field */ - #define FPB_COMP3_enable (0x00000001u) - #define FPB_COMP3_enable_MASK (0x00000001u) - #define FPB_COMP3_enable_BIT (0) - #define FPB_COMP3_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP3_REPLACE (0xC0000000u) +#define FPB_COMP3_REPLACE_MASK (0xC0000000u) +#define FPB_COMP3_REPLACE_BIT (30) +#define FPB_COMP3_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP3_COMP (0x1FFFFFFCu) +#define FPB_COMP3_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP3_COMP_BIT (2) +#define FPB_COMP3_COMP_BITS (27) +/* enable field */ +#define FPB_COMP3_enable (0x00000001u) +#define FPB_COMP3_enable_MASK (0x00000001u) +#define FPB_COMP3_enable_BIT (0) +#define FPB_COMP3_enable_BITS (1) #define FPB_COMP4 *((volatile uint32_t *)0xE0002018u) #define FPB_COMP4_REG *((volatile uint32_t *)0xE0002018u) #define FPB_COMP4_ADDR (0xE0002018u) #define FPB_COMP4_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP4_REPLACE (0xC0000000u) - #define FPB_COMP4_REPLACE_MASK (0xC0000000u) - #define FPB_COMP4_REPLACE_BIT (30) - #define FPB_COMP4_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP4_COMP (0x1FFFFFFCu) - #define FPB_COMP4_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP4_COMP_BIT (2) - #define FPB_COMP4_COMP_BITS (27) - /* enable field */ - #define FPB_COMP4_enable (0x00000001u) - #define FPB_COMP4_enable_MASK (0x00000001u) - #define FPB_COMP4_enable_BIT (0) - #define FPB_COMP4_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP4_REPLACE (0xC0000000u) +#define FPB_COMP4_REPLACE_MASK (0xC0000000u) +#define FPB_COMP4_REPLACE_BIT (30) +#define FPB_COMP4_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP4_COMP (0x1FFFFFFCu) +#define FPB_COMP4_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP4_COMP_BIT (2) +#define FPB_COMP4_COMP_BITS (27) +/* enable field */ +#define FPB_COMP4_enable (0x00000001u) +#define FPB_COMP4_enable_MASK (0x00000001u) +#define FPB_COMP4_enable_BIT (0) +#define FPB_COMP4_enable_BITS (1) #define FPB_COMP5 *((volatile uint32_t *)0xE000201Cu) #define FPB_COMP5_REG *((volatile uint32_t *)0xE000201Cu) #define FPB_COMP5_ADDR (0xE000201Cu) #define FPB_COMP5_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP5_REPLACE (0xC0000000u) - #define FPB_COMP5_REPLACE_MASK (0xC0000000u) - #define FPB_COMP5_REPLACE_BIT (30) - #define FPB_COMP5_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP5_COMP (0x1FFFFFFCu) - #define FPB_COMP5_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP5_COMP_BIT (2) - #define FPB_COMP5_COMP_BITS (27) - /* enable field */ - #define FPB_COMP5_enable (0x00000001u) - #define FPB_COMP5_enable_MASK (0x00000001u) - #define FPB_COMP5_enable_BIT (0) - #define FPB_COMP5_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP5_REPLACE (0xC0000000u) +#define FPB_COMP5_REPLACE_MASK (0xC0000000u) +#define FPB_COMP5_REPLACE_BIT (30) +#define FPB_COMP5_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP5_COMP (0x1FFFFFFCu) +#define FPB_COMP5_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP5_COMP_BIT (2) +#define FPB_COMP5_COMP_BITS (27) +/* enable field */ +#define FPB_COMP5_enable (0x00000001u) +#define FPB_COMP5_enable_MASK (0x00000001u) +#define FPB_COMP5_enable_BIT (0) +#define FPB_COMP5_enable_BITS (1) #define FPB_COMP6 *((volatile uint32_t *)0xE0002020u) #define FPB_COMP6_REG *((volatile uint32_t *)0xE0002020u) #define FPB_COMP6_ADDR (0xE0002020u) #define FPB_COMP6_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP6_REPLACE (0xC0000000u) - #define FPB_COMP6_REPLACE_MASK (0xC0000000u) - #define FPB_COMP6_REPLACE_BIT (30) - #define FPB_COMP6_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP6_COMP (0x1FFFFFFCu) - #define FPB_COMP6_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP6_COMP_BIT (2) - #define FPB_COMP6_COMP_BITS (27) - /* enable field */ - #define FPB_COMP6_enable (0x00000001u) - #define FPB_COMP6_enable_MASK (0x00000001u) - #define FPB_COMP6_enable_BIT (0) - #define FPB_COMP6_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP6_REPLACE (0xC0000000u) +#define FPB_COMP6_REPLACE_MASK (0xC0000000u) +#define FPB_COMP6_REPLACE_BIT (30) +#define FPB_COMP6_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP6_COMP (0x1FFFFFFCu) +#define FPB_COMP6_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP6_COMP_BIT (2) +#define FPB_COMP6_COMP_BITS (27) +/* enable field */ +#define FPB_COMP6_enable (0x00000001u) +#define FPB_COMP6_enable_MASK (0x00000001u) +#define FPB_COMP6_enable_BIT (0) +#define FPB_COMP6_enable_BITS (1) #define FPB_COMP7 *((volatile uint32_t *)0xE0002024u) #define FPB_COMP7_REG *((volatile uint32_t *)0xE0002024u) #define FPB_COMP7_ADDR (0xE0002024u) #define FPB_COMP7_RESET (0x00000000u) - /* REPLACE field */ - #define FPB_COMP7_REPLACE (0xC0000000u) - #define FPB_COMP7_REPLACE_MASK (0xC0000000u) - #define FPB_COMP7_REPLACE_BIT (30) - #define FPB_COMP7_REPLACE_BITS (2) - /* COMP field */ - #define FPB_COMP7_COMP (0x1FFFFFFCu) - #define FPB_COMP7_COMP_MASK (0x1FFFFFFCu) - #define FPB_COMP7_COMP_BIT (2) - #define FPB_COMP7_COMP_BITS (27) - /* enable field */ - #define FPB_COMP7_enable (0x00000001u) - #define FPB_COMP7_enable_MASK (0x00000001u) - #define FPB_COMP7_enable_BIT (0) - #define FPB_COMP7_enable_BITS (1) +/* REPLACE field */ +#define FPB_COMP7_REPLACE (0xC0000000u) +#define FPB_COMP7_REPLACE_MASK (0xC0000000u) +#define FPB_COMP7_REPLACE_BIT (30) +#define FPB_COMP7_REPLACE_BITS (2) +/* COMP field */ +#define FPB_COMP7_COMP (0x1FFFFFFCu) +#define FPB_COMP7_COMP_MASK (0x1FFFFFFCu) +#define FPB_COMP7_COMP_BIT (2) +#define FPB_COMP7_COMP_BITS (27) +/* enable field */ +#define FPB_COMP7_enable (0x00000001u) +#define FPB_COMP7_enable_MASK (0x00000001u) +#define FPB_COMP7_enable_BIT (0) +#define FPB_COMP7_enable_BITS (1) #define FPB_PERIPHID4 *((volatile uint32_t *)0xE0002FD0u) #define FPB_PERIPHID4_REG *((volatile uint32_t *)0xE0002FD0u) #define FPB_PERIPHID4_ADDR (0xE0002FD0u) #define FPB_PERIPHID4_RESET (0x00000004u) - /* PERIPHID field */ - #define FPB_PERIPHID4_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID4_PERIPHID_BIT (0) - #define FPB_PERIPHID4_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID4_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID4_PERIPHID_BIT (0) +#define FPB_PERIPHID4_PERIPHID_BITS (32) #define FPB_PERIPHID5 *((volatile uint32_t *)0xE0002FD4u) #define FPB_PERIPHID5_REG *((volatile uint32_t *)0xE0002FD4u) #define FPB_PERIPHID5_ADDR (0xE0002FD4u) #define FPB_PERIPHID5_RESET (0x00000000u) - /* PERIPHID field */ - #define FPB_PERIPHID5_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID5_PERIPHID_BIT (0) - #define FPB_PERIPHID5_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID5_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID5_PERIPHID_BIT (0) +#define FPB_PERIPHID5_PERIPHID_BITS (32) #define FPB_PERIPHID6 *((volatile uint32_t *)0xE0002FD8u) #define FPB_PERIPHID6_REG *((volatile uint32_t *)0xE0002FD8u) #define FPB_PERIPHID6_ADDR (0xE0002FD8u) #define FPB_PERIPHID6_RESET (0x00000000u) - /* PERIPHID field */ - #define FPB_PERIPHID6_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID6_PERIPHID_BIT (0) - #define FPB_PERIPHID6_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID6_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID6_PERIPHID_BIT (0) +#define FPB_PERIPHID6_PERIPHID_BITS (32) #define FPB_PERIPHID7 *((volatile uint32_t *)0xE0002FDCu) #define FPB_PERIPHID7_REG *((volatile uint32_t *)0xE0002FDCu) #define FPB_PERIPHID7_ADDR (0xE0002FDCu) #define FPB_PERIPHID7_RESET (0x00000000u) - /* PERIPHID field */ - #define FPB_PERIPHID7_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID7_PERIPHID_BIT (0) - #define FPB_PERIPHID7_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID7_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID7_PERIPHID_BIT (0) +#define FPB_PERIPHID7_PERIPHID_BITS (32) #define FPB_PERIPHID0 *((volatile uint32_t *)0xE0002FE0u) #define FPB_PERIPHID0_REG *((volatile uint32_t *)0xE0002FE0u) #define FPB_PERIPHID0_ADDR (0xE0002FE0u) #define FPB_PERIPHID0_RESET (0x00000003u) - /* PERIPHID field */ - #define FPB_PERIPHID0_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID0_PERIPHID_BIT (0) - #define FPB_PERIPHID0_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID0_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID0_PERIPHID_BIT (0) +#define FPB_PERIPHID0_PERIPHID_BITS (32) #define FPB_PERIPHID1 *((volatile uint32_t *)0xE0002FE4u) #define FPB_PERIPHID1_REG *((volatile uint32_t *)0xE0002FE4u) #define FPB_PERIPHID1_ADDR (0xE0002FE4u) #define FPB_PERIPHID1_RESET (0x000000B0u) - /* PERIPHID field */ - #define FPB_PERIPHID1_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID1_PERIPHID_BIT (0) - #define FPB_PERIPHID1_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID1_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID1_PERIPHID_BIT (0) +#define FPB_PERIPHID1_PERIPHID_BITS (32) #define FPB_PERIPHID2 *((volatile uint32_t *)0xE0002FE8u) #define FPB_PERIPHID2_REG *((volatile uint32_t *)0xE0002FE8u) #define FPB_PERIPHID2_ADDR (0xE0002FE8u) #define FPB_PERIPHID2_RESET (0x0000000Bu) - /* PERIPHID field */ - #define FPB_PERIPHID2_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID2_PERIPHID_BIT (0) - #define FPB_PERIPHID2_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID2_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID2_PERIPHID_BIT (0) +#define FPB_PERIPHID2_PERIPHID_BITS (32) #define FPB_PERIPHID3 *((volatile uint32_t *)0xE0002FECu) #define FPB_PERIPHID3_REG *((volatile uint32_t *)0xE0002FECu) #define FPB_PERIPHID3_ADDR (0xE0002FECu) #define FPB_PERIPHID3_RESET (0x00000000u) - /* PERIPHID field */ - #define FPB_PERIPHID3_PERIPHID (0xFFFFFFFFu) - #define FPB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) - #define FPB_PERIPHID3_PERIPHID_BIT (0) - #define FPB_PERIPHID3_PERIPHID_BITS (32) +/* PERIPHID field */ +#define FPB_PERIPHID3_PERIPHID (0xFFFFFFFFu) +#define FPB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) +#define FPB_PERIPHID3_PERIPHID_BIT (0) +#define FPB_PERIPHID3_PERIPHID_BITS (32) #define FPB_CELLID0 *((volatile uint32_t *)0xE0002FF0u) #define FPB_CELLID0_REG *((volatile uint32_t *)0xE0002FF0u) #define FPB_CELLID0_ADDR (0xE0002FF0u) #define FPB_CELLID0_RESET (0x0000000Du) - /* CELLID field */ - #define FPB_CELLID0_CELLID (0xFFFFFFFFu) - #define FPB_CELLID0_CELLID_MASK (0xFFFFFFFFu) - #define FPB_CELLID0_CELLID_BIT (0) - #define FPB_CELLID0_CELLID_BITS (32) +/* CELLID field */ +#define FPB_CELLID0_CELLID (0xFFFFFFFFu) +#define FPB_CELLID0_CELLID_MASK (0xFFFFFFFFu) +#define FPB_CELLID0_CELLID_BIT (0) +#define FPB_CELLID0_CELLID_BITS (32) #define FPB_CELLID1 *((volatile uint32_t *)0xE0002FF4u) #define FPB_CELLID1_REG *((volatile uint32_t *)0xE0002FF4u) #define FPB_CELLID1_ADDR (0xE0002FF4u) #define FPB_CELLID1_RESET (0x000000E0u) - /* CELLID field */ - #define FPB_CELLID1_CELLID (0xFFFFFFFFu) - #define FPB_CELLID1_CELLID_MASK (0xFFFFFFFFu) - #define FPB_CELLID1_CELLID_BIT (0) - #define FPB_CELLID1_CELLID_BITS (32) +/* CELLID field */ +#define FPB_CELLID1_CELLID (0xFFFFFFFFu) +#define FPB_CELLID1_CELLID_MASK (0xFFFFFFFFu) +#define FPB_CELLID1_CELLID_BIT (0) +#define FPB_CELLID1_CELLID_BITS (32) #define FPB_CELLID2 *((volatile uint32_t *)0xE0002FF8u) #define FPB_CELLID2_REG *((volatile uint32_t *)0xE0002FF8u) #define FPB_CELLID2_ADDR (0xE0002FF8u) #define FPB_CELLID2_RESET (0x00000005u) - /* CELLID field */ - #define FPB_CELLID2_CELLID (0xFFFFFFFFu) - #define FPB_CELLID2_CELLID_MASK (0xFFFFFFFFu) - #define FPB_CELLID2_CELLID_BIT (0) - #define FPB_CELLID2_CELLID_BITS (32) +/* CELLID field */ +#define FPB_CELLID2_CELLID (0xFFFFFFFFu) +#define FPB_CELLID2_CELLID_MASK (0xFFFFFFFFu) +#define FPB_CELLID2_CELLID_BIT (0) +#define FPB_CELLID2_CELLID_BITS (32) #define FPB_CELLID3 *((volatile uint32_t *)0xE0002FFCu) #define FPB_CELLID3_REG *((volatile uint32_t *)0xE0002FFCu) #define FPB_CELLID3_ADDR (0xE0002FFCu) #define FPB_CELLID3_RESET (0x000000B1u) - /* CELLID field */ - #define FPB_CELLID3_CELLID (0xFFFFFFFFu) - #define FPB_CELLID3_CELLID_MASK (0xFFFFFFFFu) - #define FPB_CELLID3_CELLID_BIT (0) - #define FPB_CELLID3_CELLID_BITS (32) +/* CELLID field */ +#define FPB_CELLID3_CELLID (0xFFFFFFFFu) +#define FPB_CELLID3_CELLID_MASK (0xFFFFFFFFu) +#define FPB_CELLID3_CELLID_BIT (0) +#define FPB_CELLID3_CELLID_BITS (32) /* NVIC block */ #define BLOCK_NVIC_BASE (0xE000E000u) @@ -9229,1926 +9229,1926 @@ #define NVIC_ICTR_REG *((volatile uint32_t *)0xE000E004u) #define NVIC_ICTR_ADDR (0xE000E004u) #define NVIC_ICTR_RESET (0x00000000u) - /* INTLINESNUM field */ - #define NVIC_ICTR_INTLINESNUM (0x0000001Fu) - #define NVIC_ICTR_INTLINESNUM_MASK (0x0000001Fu) - #define NVIC_ICTR_INTLINESNUM_BIT (0) - #define NVIC_ICTR_INTLINESNUM_BITS (5) +/* INTLINESNUM field */ +#define NVIC_ICTR_INTLINESNUM (0x0000001Fu) +#define NVIC_ICTR_INTLINESNUM_MASK (0x0000001Fu) +#define NVIC_ICTR_INTLINESNUM_BIT (0) +#define NVIC_ICTR_INTLINESNUM_BITS (5) #define ST_CSR *((volatile uint32_t *)0xE000E010u) #define ST_CSR_REG *((volatile uint32_t *)0xE000E010u) #define ST_CSR_ADDR (0xE000E010u) #define ST_CSR_RESET (0x00000000u) - /* COUNTFLAG field */ - #define ST_CSR_COUNTFLAG (0x00010000u) - #define ST_CSR_COUNTFLAG_MASK (0x00010000u) - #define ST_CSR_COUNTFLAG_BIT (16) - #define ST_CSR_COUNTFLAG_BITS (1) - /* CLKSOURCE field */ - #define ST_CSR_CLKSOURCE (0x00000004u) - #define ST_CSR_CLKSOURCE_MASK (0x00000004u) - #define ST_CSR_CLKSOURCE_BIT (2) - #define ST_CSR_CLKSOURCE_BITS (1) - /* TICKINT field */ - #define ST_CSR_TICKINT (0x00000002u) - #define ST_CSR_TICKINT_MASK (0x00000002u) - #define ST_CSR_TICKINT_BIT (1) - #define ST_CSR_TICKINT_BITS (1) - /* ENABLE field */ - #define ST_CSR_ENABLE (0x00000001u) - #define ST_CSR_ENABLE_MASK (0x00000001u) - #define ST_CSR_ENABLE_BIT (0) - #define ST_CSR_ENABLE_BITS (1) +/* COUNTFLAG field */ +#define ST_CSR_COUNTFLAG (0x00010000u) +#define ST_CSR_COUNTFLAG_MASK (0x00010000u) +#define ST_CSR_COUNTFLAG_BIT (16) +#define ST_CSR_COUNTFLAG_BITS (1) +/* CLKSOURCE field */ +#define ST_CSR_CLKSOURCE (0x00000004u) +#define ST_CSR_CLKSOURCE_MASK (0x00000004u) +#define ST_CSR_CLKSOURCE_BIT (2) +#define ST_CSR_CLKSOURCE_BITS (1) +/* TICKINT field */ +#define ST_CSR_TICKINT (0x00000002u) +#define ST_CSR_TICKINT_MASK (0x00000002u) +#define ST_CSR_TICKINT_BIT (1) +#define ST_CSR_TICKINT_BITS (1) +/* ENABLE field */ +#define ST_CSR_ENABLE (0x00000001u) +#define ST_CSR_ENABLE_MASK (0x00000001u) +#define ST_CSR_ENABLE_BIT (0) +#define ST_CSR_ENABLE_BITS (1) #define ST_RVR *((volatile uint32_t *)0xE000E014u) #define ST_RVR_REG *((volatile uint32_t *)0xE000E014u) #define ST_RVR_ADDR (0xE000E014u) #define ST_RVR_RESET (0x00000000u) - /* RELOAD field */ - #define ST_RVR_RELOAD (0x00FFFFFFu) - #define ST_RVR_RELOAD_MASK (0x00FFFFFFu) - #define ST_RVR_RELOAD_BIT (0) - #define ST_RVR_RELOAD_BITS (24) +/* RELOAD field */ +#define ST_RVR_RELOAD (0x00FFFFFFu) +#define ST_RVR_RELOAD_MASK (0x00FFFFFFu) +#define ST_RVR_RELOAD_BIT (0) +#define ST_RVR_RELOAD_BITS (24) #define ST_CVR *((volatile uint32_t *)0xE000E018u) #define ST_CVR_REG *((volatile uint32_t *)0xE000E018u) #define ST_CVR_ADDR (0xE000E018u) #define ST_CVR_RESET (0x00000000u) - /* CURRENT field */ - #define ST_CVR_CURRENT (0xFFFFFFFFu) - #define ST_CVR_CURRENT_MASK (0xFFFFFFFFu) - #define ST_CVR_CURRENT_BIT (0) - #define ST_CVR_CURRENT_BITS (32) +/* CURRENT field */ +#define ST_CVR_CURRENT (0xFFFFFFFFu) +#define ST_CVR_CURRENT_MASK (0xFFFFFFFFu) +#define ST_CVR_CURRENT_BIT (0) +#define ST_CVR_CURRENT_BITS (32) #define ST_CALVR *((volatile uint32_t *)0xE000E01Cu) #define ST_CALVR_REG *((volatile uint32_t *)0xE000E01Cu) #define ST_CALVR_ADDR (0xE000E01Cu) #define ST_CALVR_RESET (0x00000000u) - /* NOREF field */ - #define ST_CALVR_NOREF (0x80000000u) - #define ST_CALVR_NOREF_MASK (0x80000000u) - #define ST_CALVR_NOREF_BIT (31) - #define ST_CALVR_NOREF_BITS (1) - /* SKEW field */ - #define ST_CALVR_SKEW (0x40000000u) - #define ST_CALVR_SKEW_MASK (0x40000000u) - #define ST_CALVR_SKEW_BIT (30) - #define ST_CALVR_SKEW_BITS (1) - /* TENMS field */ - #define ST_CALVR_TENMS (0x00FFFFFFu) - #define ST_CALVR_TENMS_MASK (0x00FFFFFFu) - #define ST_CALVR_TENMS_BIT (0) - #define ST_CALVR_TENMS_BITS (24) +/* NOREF field */ +#define ST_CALVR_NOREF (0x80000000u) +#define ST_CALVR_NOREF_MASK (0x80000000u) +#define ST_CALVR_NOREF_BIT (31) +#define ST_CALVR_NOREF_BITS (1) +/* SKEW field */ +#define ST_CALVR_SKEW (0x40000000u) +#define ST_CALVR_SKEW_MASK (0x40000000u) +#define ST_CALVR_SKEW_BIT (30) +#define ST_CALVR_SKEW_BITS (1) +/* TENMS field */ +#define ST_CALVR_TENMS (0x00FFFFFFu) +#define ST_CALVR_TENMS_MASK (0x00FFFFFFu) +#define ST_CALVR_TENMS_BIT (0) +#define ST_CALVR_TENMS_BITS (24) #define INT_CFGSET *((volatile uint32_t *)0xE000E100u) #define INT_CFGSET_REG *((volatile uint32_t *)0xE000E100u) #define INT_CFGSET_ADDR (0xE000E100u) #define INT_CFGSET_RESET (0x00000000u) - /* INT_DEBUG field */ - #define INT_DEBUG (0x00010000u) - #define INT_DEBUG_MASK (0x00010000u) - #define INT_DEBUG_BIT (16) - #define INT_DEBUG_BITS (1) - /* INT_IRQD field */ - #define INT_IRQD (0x00008000u) - #define INT_IRQD_MASK (0x00008000u) - #define INT_IRQD_BIT (15) - #define INT_IRQD_BITS (1) - /* INT_IRQC field */ - #define INT_IRQC (0x00004000u) - #define INT_IRQC_MASK (0x00004000u) - #define INT_IRQC_BIT (14) - #define INT_IRQC_BITS (1) - /* INT_IRQB field */ - #define INT_IRQB (0x00002000u) - #define INT_IRQB_MASK (0x00002000u) - #define INT_IRQB_BIT (13) - #define INT_IRQB_BITS (1) - /* INT_IRQA field */ - #define INT_IRQA (0x00001000u) - #define INT_IRQA_MASK (0x00001000u) - #define INT_IRQA_BIT (12) - #define INT_IRQA_BITS (1) - /* INT_ADC field */ - #define INT_ADC (0x00000800u) - #define INT_ADC_MASK (0x00000800u) - #define INT_ADC_BIT (11) - #define INT_ADC_BITS (1) - /* INT_MACRX field */ - #define INT_MACRX (0x00000400u) - #define INT_MACRX_MASK (0x00000400u) - #define INT_MACRX_BIT (10) - #define INT_MACRX_BITS (1) - /* INT_MACTX field */ - #define INT_MACTX (0x00000200u) - #define INT_MACTX_MASK (0x00000200u) - #define INT_MACTX_BIT (9) - #define INT_MACTX_BITS (1) - /* INT_MACTMR field */ - #define INT_MACTMR (0x00000100u) - #define INT_MACTMR_MASK (0x00000100u) - #define INT_MACTMR_BIT (8) - #define INT_MACTMR_BITS (1) - /* INT_SEC field */ - #define INT_SEC (0x00000080u) - #define INT_SEC_MASK (0x00000080u) - #define INT_SEC_BIT (7) - #define INT_SEC_BITS (1) - /* INT_SC2 field */ - #define INT_SC2 (0x00000040u) - #define INT_SC2_MASK (0x00000040u) - #define INT_SC2_BIT (6) - #define INT_SC2_BITS (1) - /* INT_SC1 field */ - #define INT_SC1 (0x00000020u) - #define INT_SC1_MASK (0x00000020u) - #define INT_SC1_BIT (5) - #define INT_SC1_BITS (1) - /* INT_SLEEPTMR field */ - #define INT_SLEEPTMR (0x00000010u) - #define INT_SLEEPTMR_MASK (0x00000010u) - #define INT_SLEEPTMR_BIT (4) - #define INT_SLEEPTMR_BITS (1) - /* INT_BB field */ - #define INT_BB (0x00000008u) - #define INT_BB_MASK (0x00000008u) - #define INT_BB_BIT (3) - #define INT_BB_BITS (1) - /* INT_MGMT field */ - #define INT_MGMT (0x00000004u) - #define INT_MGMT_MASK (0x00000004u) - #define INT_MGMT_BIT (2) - #define INT_MGMT_BITS (1) - /* INT_TIM2 field */ - #define INT_TIM2 (0x00000002u) - #define INT_TIM2_MASK (0x00000002u) - #define INT_TIM2_BIT (1) - #define INT_TIM2_BITS (1) - /* INT_TIM1 field */ - #define INT_TIM1 (0x00000001u) - #define INT_TIM1_MASK (0x00000001u) - #define INT_TIM1_BIT (0) - #define INT_TIM1_BITS (1) +/* INT_DEBUG field */ +#define INT_DEBUG (0x00010000u) +#define INT_DEBUG_MASK (0x00010000u) +#define INT_DEBUG_BIT (16) +#define INT_DEBUG_BITS (1) +/* INT_IRQD field */ +#define INT_IRQD (0x00008000u) +#define INT_IRQD_MASK (0x00008000u) +#define INT_IRQD_BIT (15) +#define INT_IRQD_BITS (1) +/* INT_IRQC field */ +#define INT_IRQC (0x00004000u) +#define INT_IRQC_MASK (0x00004000u) +#define INT_IRQC_BIT (14) +#define INT_IRQC_BITS (1) +/* INT_IRQB field */ +#define INT_IRQB (0x00002000u) +#define INT_IRQB_MASK (0x00002000u) +#define INT_IRQB_BIT (13) +#define INT_IRQB_BITS (1) +/* INT_IRQA field */ +#define INT_IRQA (0x00001000u) +#define INT_IRQA_MASK (0x00001000u) +#define INT_IRQA_BIT (12) +#define INT_IRQA_BITS (1) +/* INT_ADC field */ +#define INT_ADC (0x00000800u) +#define INT_ADC_MASK (0x00000800u) +#define INT_ADC_BIT (11) +#define INT_ADC_BITS (1) +/* INT_MACRX field */ +#define INT_MACRX (0x00000400u) +#define INT_MACRX_MASK (0x00000400u) +#define INT_MACRX_BIT (10) +#define INT_MACRX_BITS (1) +/* INT_MACTX field */ +#define INT_MACTX (0x00000200u) +#define INT_MACTX_MASK (0x00000200u) +#define INT_MACTX_BIT (9) +#define INT_MACTX_BITS (1) +/* INT_MACTMR field */ +#define INT_MACTMR (0x00000100u) +#define INT_MACTMR_MASK (0x00000100u) +#define INT_MACTMR_BIT (8) +#define INT_MACTMR_BITS (1) +/* INT_SEC field */ +#define INT_SEC (0x00000080u) +#define INT_SEC_MASK (0x00000080u) +#define INT_SEC_BIT (7) +#define INT_SEC_BITS (1) +/* INT_SC2 field */ +#define INT_SC2 (0x00000040u) +#define INT_SC2_MASK (0x00000040u) +#define INT_SC2_BIT (6) +#define INT_SC2_BITS (1) +/* INT_SC1 field */ +#define INT_SC1 (0x00000020u) +#define INT_SC1_MASK (0x00000020u) +#define INT_SC1_BIT (5) +#define INT_SC1_BITS (1) +/* INT_SLEEPTMR field */ +#define INT_SLEEPTMR (0x00000010u) +#define INT_SLEEPTMR_MASK (0x00000010u) +#define INT_SLEEPTMR_BIT (4) +#define INT_SLEEPTMR_BITS (1) +/* INT_BB field */ +#define INT_BB (0x00000008u) +#define INT_BB_MASK (0x00000008u) +#define INT_BB_BIT (3) +#define INT_BB_BITS (1) +/* INT_MGMT field */ +#define INT_MGMT (0x00000004u) +#define INT_MGMT_MASK (0x00000004u) +#define INT_MGMT_BIT (2) +#define INT_MGMT_BITS (1) +/* INT_TIM2 field */ +#define INT_TIM2 (0x00000002u) +#define INT_TIM2_MASK (0x00000002u) +#define INT_TIM2_BIT (1) +#define INT_TIM2_BITS (1) +/* INT_TIM1 field */ +#define INT_TIM1 (0x00000001u) +#define INT_TIM1_MASK (0x00000001u) +#define INT_TIM1_BIT (0) +#define INT_TIM1_BITS (1) #define INT_CFGCLR *((volatile uint32_t *)0xE000E180u) #define INT_CFGCLR_REG *((volatile uint32_t *)0xE000E180u) #define INT_CFGCLR_ADDR (0xE000E180u) #define INT_CFGCLR_RESET (0x00000000u) - /* INT_DEBUG field */ - #define INT_DEBUG (0x00010000u) - #define INT_DEBUG_MASK (0x00010000u) - #define INT_DEBUG_BIT (16) - #define INT_DEBUG_BITS (1) - /* INT_IRQD field */ - #define INT_IRQD (0x00008000u) - #define INT_IRQD_MASK (0x00008000u) - #define INT_IRQD_BIT (15) - #define INT_IRQD_BITS (1) - /* INT_IRQC field */ - #define INT_IRQC (0x00004000u) - #define INT_IRQC_MASK (0x00004000u) - #define INT_IRQC_BIT (14) - #define INT_IRQC_BITS (1) - /* INT_IRQB field */ - #define INT_IRQB (0x00002000u) - #define INT_IRQB_MASK (0x00002000u) - #define INT_IRQB_BIT (13) - #define INT_IRQB_BITS (1) - /* INT_IRQA field */ - #define INT_IRQA (0x00001000u) - #define INT_IRQA_MASK (0x00001000u) - #define INT_IRQA_BIT (12) - #define INT_IRQA_BITS (1) - /* INT_ADC field */ - #define INT_ADC (0x00000800u) - #define INT_ADC_MASK (0x00000800u) - #define INT_ADC_BIT (11) - #define INT_ADC_BITS (1) - /* INT_MACRX field */ - #define INT_MACRX (0x00000400u) - #define INT_MACRX_MASK (0x00000400u) - #define INT_MACRX_BIT (10) - #define INT_MACRX_BITS (1) - /* INT_MACTX field */ - #define INT_MACTX (0x00000200u) - #define INT_MACTX_MASK (0x00000200u) - #define INT_MACTX_BIT (9) - #define INT_MACTX_BITS (1) - /* INT_MACTMR field */ - #define INT_MACTMR (0x00000100u) - #define INT_MACTMR_MASK (0x00000100u) - #define INT_MACTMR_BIT (8) - #define INT_MACTMR_BITS (1) - /* INT_SEC field */ - #define INT_SEC (0x00000080u) - #define INT_SEC_MASK (0x00000080u) - #define INT_SEC_BIT (7) - #define INT_SEC_BITS (1) - /* INT_SC2 field */ - #define INT_SC2 (0x00000040u) - #define INT_SC2_MASK (0x00000040u) - #define INT_SC2_BIT (6) - #define INT_SC2_BITS (1) - /* INT_SC1 field */ - #define INT_SC1 (0x00000020u) - #define INT_SC1_MASK (0x00000020u) - #define INT_SC1_BIT (5) - #define INT_SC1_BITS (1) - /* INT_SLEEPTMR field */ - #define INT_SLEEPTMR (0x00000010u) - #define INT_SLEEPTMR_MASK (0x00000010u) - #define INT_SLEEPTMR_BIT (4) - #define INT_SLEEPTMR_BITS (1) - /* INT_BB field */ - #define INT_BB (0x00000008u) - #define INT_BB_MASK (0x00000008u) - #define INT_BB_BIT (3) - #define INT_BB_BITS (1) - /* INT_MGMT field */ - #define INT_MGMT (0x00000004u) - #define INT_MGMT_MASK (0x00000004u) - #define INT_MGMT_BIT (2) - #define INT_MGMT_BITS (1) - /* INT_TIM2 field */ - #define INT_TIM2 (0x00000002u) - #define INT_TIM2_MASK (0x00000002u) - #define INT_TIM2_BIT (1) - #define INT_TIM2_BITS (1) - /* INT_TIM1 field */ - #define INT_TIM1 (0x00000001u) - #define INT_TIM1_MASK (0x00000001u) - #define INT_TIM1_BIT (0) - #define INT_TIM1_BITS (1) +/* INT_DEBUG field */ +#define INT_DEBUG (0x00010000u) +#define INT_DEBUG_MASK (0x00010000u) +#define INT_DEBUG_BIT (16) +#define INT_DEBUG_BITS (1) +/* INT_IRQD field */ +#define INT_IRQD (0x00008000u) +#define INT_IRQD_MASK (0x00008000u) +#define INT_IRQD_BIT (15) +#define INT_IRQD_BITS (1) +/* INT_IRQC field */ +#define INT_IRQC (0x00004000u) +#define INT_IRQC_MASK (0x00004000u) +#define INT_IRQC_BIT (14) +#define INT_IRQC_BITS (1) +/* INT_IRQB field */ +#define INT_IRQB (0x00002000u) +#define INT_IRQB_MASK (0x00002000u) +#define INT_IRQB_BIT (13) +#define INT_IRQB_BITS (1) +/* INT_IRQA field */ +#define INT_IRQA (0x00001000u) +#define INT_IRQA_MASK (0x00001000u) +#define INT_IRQA_BIT (12) +#define INT_IRQA_BITS (1) +/* INT_ADC field */ +#define INT_ADC (0x00000800u) +#define INT_ADC_MASK (0x00000800u) +#define INT_ADC_BIT (11) +#define INT_ADC_BITS (1) +/* INT_MACRX field */ +#define INT_MACRX (0x00000400u) +#define INT_MACRX_MASK (0x00000400u) +#define INT_MACRX_BIT (10) +#define INT_MACRX_BITS (1) +/* INT_MACTX field */ +#define INT_MACTX (0x00000200u) +#define INT_MACTX_MASK (0x00000200u) +#define INT_MACTX_BIT (9) +#define INT_MACTX_BITS (1) +/* INT_MACTMR field */ +#define INT_MACTMR (0x00000100u) +#define INT_MACTMR_MASK (0x00000100u) +#define INT_MACTMR_BIT (8) +#define INT_MACTMR_BITS (1) +/* INT_SEC field */ +#define INT_SEC (0x00000080u) +#define INT_SEC_MASK (0x00000080u) +#define INT_SEC_BIT (7) +#define INT_SEC_BITS (1) +/* INT_SC2 field */ +#define INT_SC2 (0x00000040u) +#define INT_SC2_MASK (0x00000040u) +#define INT_SC2_BIT (6) +#define INT_SC2_BITS (1) +/* INT_SC1 field */ +#define INT_SC1 (0x00000020u) +#define INT_SC1_MASK (0x00000020u) +#define INT_SC1_BIT (5) +#define INT_SC1_BITS (1) +/* INT_SLEEPTMR field */ +#define INT_SLEEPTMR (0x00000010u) +#define INT_SLEEPTMR_MASK (0x00000010u) +#define INT_SLEEPTMR_BIT (4) +#define INT_SLEEPTMR_BITS (1) +/* INT_BB field */ +#define INT_BB (0x00000008u) +#define INT_BB_MASK (0x00000008u) +#define INT_BB_BIT (3) +#define INT_BB_BITS (1) +/* INT_MGMT field */ +#define INT_MGMT (0x00000004u) +#define INT_MGMT_MASK (0x00000004u) +#define INT_MGMT_BIT (2) +#define INT_MGMT_BITS (1) +/* INT_TIM2 field */ +#define INT_TIM2 (0x00000002u) +#define INT_TIM2_MASK (0x00000002u) +#define INT_TIM2_BIT (1) +#define INT_TIM2_BITS (1) +/* INT_TIM1 field */ +#define INT_TIM1 (0x00000001u) +#define INT_TIM1_MASK (0x00000001u) +#define INT_TIM1_BIT (0) +#define INT_TIM1_BITS (1) #define INT_PENDSET *((volatile uint32_t *)0xE000E200u) #define INT_PENDSET_REG *((volatile uint32_t *)0xE000E200u) #define INT_PENDSET_ADDR (0xE000E200u) #define INT_PENDSET_RESET (0x00000000u) - /* INT_DEBUG field */ - #define INT_DEBUG (0x00010000u) - #define INT_DEBUG_MASK (0x00010000u) - #define INT_DEBUG_BIT (16) - #define INT_DEBUG_BITS (1) - /* INT_IRQD field */ - #define INT_IRQD (0x00008000u) - #define INT_IRQD_MASK (0x00008000u) - #define INT_IRQD_BIT (15) - #define INT_IRQD_BITS (1) - /* INT_IRQC field */ - #define INT_IRQC (0x00004000u) - #define INT_IRQC_MASK (0x00004000u) - #define INT_IRQC_BIT (14) - #define INT_IRQC_BITS (1) - /* INT_IRQB field */ - #define INT_IRQB (0x00002000u) - #define INT_IRQB_MASK (0x00002000u) - #define INT_IRQB_BIT (13) - #define INT_IRQB_BITS (1) - /* INT_IRQA field */ - #define INT_IRQA (0x00001000u) - #define INT_IRQA_MASK (0x00001000u) - #define INT_IRQA_BIT (12) - #define INT_IRQA_BITS (1) - /* INT_ADC field */ - #define INT_ADC (0x00000800u) - #define INT_ADC_MASK (0x00000800u) - #define INT_ADC_BIT (11) - #define INT_ADC_BITS (1) - /* INT_MACRX field */ - #define INT_MACRX (0x00000400u) - #define INT_MACRX_MASK (0x00000400u) - #define INT_MACRX_BIT (10) - #define INT_MACRX_BITS (1) - /* INT_MACTX field */ - #define INT_MACTX (0x00000200u) - #define INT_MACTX_MASK (0x00000200u) - #define INT_MACTX_BIT (9) - #define INT_MACTX_BITS (1) - /* INT_MACTMR field */ - #define INT_MACTMR (0x00000100u) - #define INT_MACTMR_MASK (0x00000100u) - #define INT_MACTMR_BIT (8) - #define INT_MACTMR_BITS (1) - /* INT_SEC field */ - #define INT_SEC (0x00000080u) - #define INT_SEC_MASK (0x00000080u) - #define INT_SEC_BIT (7) - #define INT_SEC_BITS (1) - /* INT_SC2 field */ - #define INT_SC2 (0x00000040u) - #define INT_SC2_MASK (0x00000040u) - #define INT_SC2_BIT (6) - #define INT_SC2_BITS (1) - /* INT_SC1 field */ - #define INT_SC1 (0x00000020u) - #define INT_SC1_MASK (0x00000020u) - #define INT_SC1_BIT (5) - #define INT_SC1_BITS (1) - /* INT_SLEEPTMR field */ - #define INT_SLEEPTMR (0x00000010u) - #define INT_SLEEPTMR_MASK (0x00000010u) - #define INT_SLEEPTMR_BIT (4) - #define INT_SLEEPTMR_BITS (1) - /* INT_BB field */ - #define INT_BB (0x00000008u) - #define INT_BB_MASK (0x00000008u) - #define INT_BB_BIT (3) - #define INT_BB_BITS (1) - /* INT_MGMT field */ - #define INT_MGMT (0x00000004u) - #define INT_MGMT_MASK (0x00000004u) - #define INT_MGMT_BIT (2) - #define INT_MGMT_BITS (1) - /* INT_TIM2 field */ - #define INT_TIM2 (0x00000002u) - #define INT_TIM2_MASK (0x00000002u) - #define INT_TIM2_BIT (1) - #define INT_TIM2_BITS (1) - /* INT_TIM1 field */ - #define INT_TIM1 (0x00000001u) - #define INT_TIM1_MASK (0x00000001u) - #define INT_TIM1_BIT (0) - #define INT_TIM1_BITS (1) +/* INT_DEBUG field */ +#define INT_DEBUG (0x00010000u) +#define INT_DEBUG_MASK (0x00010000u) +#define INT_DEBUG_BIT (16) +#define INT_DEBUG_BITS (1) +/* INT_IRQD field */ +#define INT_IRQD (0x00008000u) +#define INT_IRQD_MASK (0x00008000u) +#define INT_IRQD_BIT (15) +#define INT_IRQD_BITS (1) +/* INT_IRQC field */ +#define INT_IRQC (0x00004000u) +#define INT_IRQC_MASK (0x00004000u) +#define INT_IRQC_BIT (14) +#define INT_IRQC_BITS (1) +/* INT_IRQB field */ +#define INT_IRQB (0x00002000u) +#define INT_IRQB_MASK (0x00002000u) +#define INT_IRQB_BIT (13) +#define INT_IRQB_BITS (1) +/* INT_IRQA field */ +#define INT_IRQA (0x00001000u) +#define INT_IRQA_MASK (0x00001000u) +#define INT_IRQA_BIT (12) +#define INT_IRQA_BITS (1) +/* INT_ADC field */ +#define INT_ADC (0x00000800u) +#define INT_ADC_MASK (0x00000800u) +#define INT_ADC_BIT (11) +#define INT_ADC_BITS (1) +/* INT_MACRX field */ +#define INT_MACRX (0x00000400u) +#define INT_MACRX_MASK (0x00000400u) +#define INT_MACRX_BIT (10) +#define INT_MACRX_BITS (1) +/* INT_MACTX field */ +#define INT_MACTX (0x00000200u) +#define INT_MACTX_MASK (0x00000200u) +#define INT_MACTX_BIT (9) +#define INT_MACTX_BITS (1) +/* INT_MACTMR field */ +#define INT_MACTMR (0x00000100u) +#define INT_MACTMR_MASK (0x00000100u) +#define INT_MACTMR_BIT (8) +#define INT_MACTMR_BITS (1) +/* INT_SEC field */ +#define INT_SEC (0x00000080u) +#define INT_SEC_MASK (0x00000080u) +#define INT_SEC_BIT (7) +#define INT_SEC_BITS (1) +/* INT_SC2 field */ +#define INT_SC2 (0x00000040u) +#define INT_SC2_MASK (0x00000040u) +#define INT_SC2_BIT (6) +#define INT_SC2_BITS (1) +/* INT_SC1 field */ +#define INT_SC1 (0x00000020u) +#define INT_SC1_MASK (0x00000020u) +#define INT_SC1_BIT (5) +#define INT_SC1_BITS (1) +/* INT_SLEEPTMR field */ +#define INT_SLEEPTMR (0x00000010u) +#define INT_SLEEPTMR_MASK (0x00000010u) +#define INT_SLEEPTMR_BIT (4) +#define INT_SLEEPTMR_BITS (1) +/* INT_BB field */ +#define INT_BB (0x00000008u) +#define INT_BB_MASK (0x00000008u) +#define INT_BB_BIT (3) +#define INT_BB_BITS (1) +/* INT_MGMT field */ +#define INT_MGMT (0x00000004u) +#define INT_MGMT_MASK (0x00000004u) +#define INT_MGMT_BIT (2) +#define INT_MGMT_BITS (1) +/* INT_TIM2 field */ +#define INT_TIM2 (0x00000002u) +#define INT_TIM2_MASK (0x00000002u) +#define INT_TIM2_BIT (1) +#define INT_TIM2_BITS (1) +/* INT_TIM1 field */ +#define INT_TIM1 (0x00000001u) +#define INT_TIM1_MASK (0x00000001u) +#define INT_TIM1_BIT (0) +#define INT_TIM1_BITS (1) #define INT_PENDCLR *((volatile uint32_t *)0xE000E280u) #define INT_PENDCLR_REG *((volatile uint32_t *)0xE000E280u) #define INT_PENDCLR_ADDR (0xE000E280u) #define INT_PENDCLR_RESET (0x00000000u) - /* INT_DEBUG field */ - #define INT_DEBUG (0x00010000u) - #define INT_DEBUG_MASK (0x00010000u) - #define INT_DEBUG_BIT (16) - #define INT_DEBUG_BITS (1) - /* INT_IRQD field */ - #define INT_IRQD (0x00008000u) - #define INT_IRQD_MASK (0x00008000u) - #define INT_IRQD_BIT (15) - #define INT_IRQD_BITS (1) - /* INT_IRQC field */ - #define INT_IRQC (0x00004000u) - #define INT_IRQC_MASK (0x00004000u) - #define INT_IRQC_BIT (14) - #define INT_IRQC_BITS (1) - /* INT_IRQB field */ - #define INT_IRQB (0x00002000u) - #define INT_IRQB_MASK (0x00002000u) - #define INT_IRQB_BIT (13) - #define INT_IRQB_BITS (1) - /* INT_IRQA field */ - #define INT_IRQA (0x00001000u) - #define INT_IRQA_MASK (0x00001000u) - #define INT_IRQA_BIT (12) - #define INT_IRQA_BITS (1) - /* INT_ADC field */ - #define INT_ADC (0x00000800u) - #define INT_ADC_MASK (0x00000800u) - #define INT_ADC_BIT (11) - #define INT_ADC_BITS (1) - /* INT_MACRX field */ - #define INT_MACRX (0x00000400u) - #define INT_MACRX_MASK (0x00000400u) - #define INT_MACRX_BIT (10) - #define INT_MACRX_BITS (1) - /* INT_MACTX field */ - #define INT_MACTX (0x00000200u) - #define INT_MACTX_MASK (0x00000200u) - #define INT_MACTX_BIT (9) - #define INT_MACTX_BITS (1) - /* INT_MACTMR field */ - #define INT_MACTMR (0x00000100u) - #define INT_MACTMR_MASK (0x00000100u) - #define INT_MACTMR_BIT (8) - #define INT_MACTMR_BITS (1) - /* INT_SEC field */ - #define INT_SEC (0x00000080u) - #define INT_SEC_MASK (0x00000080u) - #define INT_SEC_BIT (7) - #define INT_SEC_BITS (1) - /* INT_SC2 field */ - #define INT_SC2 (0x00000040u) - #define INT_SC2_MASK (0x00000040u) - #define INT_SC2_BIT (6) - #define INT_SC2_BITS (1) - /* INT_SC1 field */ - #define INT_SC1 (0x00000020u) - #define INT_SC1_MASK (0x00000020u) - #define INT_SC1_BIT (5) - #define INT_SC1_BITS (1) - /* INT_SLEEPTMR field */ - #define INT_SLEEPTMR (0x00000010u) - #define INT_SLEEPTMR_MASK (0x00000010u) - #define INT_SLEEPTMR_BIT (4) - #define INT_SLEEPTMR_BITS (1) - /* INT_BB field */ - #define INT_BB (0x00000008u) - #define INT_BB_MASK (0x00000008u) - #define INT_BB_BIT (3) - #define INT_BB_BITS (1) - /* INT_MGMT field */ - #define INT_MGMT (0x00000004u) - #define INT_MGMT_MASK (0x00000004u) - #define INT_MGMT_BIT (2) - #define INT_MGMT_BITS (1) - /* INT_TIM2 field */ - #define INT_TIM2 (0x00000002u) - #define INT_TIM2_MASK (0x00000002u) - #define INT_TIM2_BIT (1) - #define INT_TIM2_BITS (1) - /* INT_TIM1 field */ - #define INT_TIM1 (0x00000001u) - #define INT_TIM1_MASK (0x00000001u) - #define INT_TIM1_BIT (0) - #define INT_TIM1_BITS (1) +/* INT_DEBUG field */ +#define INT_DEBUG (0x00010000u) +#define INT_DEBUG_MASK (0x00010000u) +#define INT_DEBUG_BIT (16) +#define INT_DEBUG_BITS (1) +/* INT_IRQD field */ +#define INT_IRQD (0x00008000u) +#define INT_IRQD_MASK (0x00008000u) +#define INT_IRQD_BIT (15) +#define INT_IRQD_BITS (1) +/* INT_IRQC field */ +#define INT_IRQC (0x00004000u) +#define INT_IRQC_MASK (0x00004000u) +#define INT_IRQC_BIT (14) +#define INT_IRQC_BITS (1) +/* INT_IRQB field */ +#define INT_IRQB (0x00002000u) +#define INT_IRQB_MASK (0x00002000u) +#define INT_IRQB_BIT (13) +#define INT_IRQB_BITS (1) +/* INT_IRQA field */ +#define INT_IRQA (0x00001000u) +#define INT_IRQA_MASK (0x00001000u) +#define INT_IRQA_BIT (12) +#define INT_IRQA_BITS (1) +/* INT_ADC field */ +#define INT_ADC (0x00000800u) +#define INT_ADC_MASK (0x00000800u) +#define INT_ADC_BIT (11) +#define INT_ADC_BITS (1) +/* INT_MACRX field */ +#define INT_MACRX (0x00000400u) +#define INT_MACRX_MASK (0x00000400u) +#define INT_MACRX_BIT (10) +#define INT_MACRX_BITS (1) +/* INT_MACTX field */ +#define INT_MACTX (0x00000200u) +#define INT_MACTX_MASK (0x00000200u) +#define INT_MACTX_BIT (9) +#define INT_MACTX_BITS (1) +/* INT_MACTMR field */ +#define INT_MACTMR (0x00000100u) +#define INT_MACTMR_MASK (0x00000100u) +#define INT_MACTMR_BIT (8) +#define INT_MACTMR_BITS (1) +/* INT_SEC field */ +#define INT_SEC (0x00000080u) +#define INT_SEC_MASK (0x00000080u) +#define INT_SEC_BIT (7) +#define INT_SEC_BITS (1) +/* INT_SC2 field */ +#define INT_SC2 (0x00000040u) +#define INT_SC2_MASK (0x00000040u) +#define INT_SC2_BIT (6) +#define INT_SC2_BITS (1) +/* INT_SC1 field */ +#define INT_SC1 (0x00000020u) +#define INT_SC1_MASK (0x00000020u) +#define INT_SC1_BIT (5) +#define INT_SC1_BITS (1) +/* INT_SLEEPTMR field */ +#define INT_SLEEPTMR (0x00000010u) +#define INT_SLEEPTMR_MASK (0x00000010u) +#define INT_SLEEPTMR_BIT (4) +#define INT_SLEEPTMR_BITS (1) +/* INT_BB field */ +#define INT_BB (0x00000008u) +#define INT_BB_MASK (0x00000008u) +#define INT_BB_BIT (3) +#define INT_BB_BITS (1) +/* INT_MGMT field */ +#define INT_MGMT (0x00000004u) +#define INT_MGMT_MASK (0x00000004u) +#define INT_MGMT_BIT (2) +#define INT_MGMT_BITS (1) +/* INT_TIM2 field */ +#define INT_TIM2 (0x00000002u) +#define INT_TIM2_MASK (0x00000002u) +#define INT_TIM2_BIT (1) +#define INT_TIM2_BITS (1) +/* INT_TIM1 field */ +#define INT_TIM1 (0x00000001u) +#define INT_TIM1_MASK (0x00000001u) +#define INT_TIM1_BIT (0) +#define INT_TIM1_BITS (1) #define INT_ACTIVE *((volatile uint32_t *)0xE000E300u) #define INT_ACTIVE_REG *((volatile uint32_t *)0xE000E300u) #define INT_ACTIVE_ADDR (0xE000E300u) #define INT_ACTIVE_RESET (0x00000000u) - /* INT_DEBUG field */ - #define INT_DEBUG (0x00010000u) - #define INT_DEBUG_MASK (0x00010000u) - #define INT_DEBUG_BIT (16) - #define INT_DEBUG_BITS (1) - /* INT_IRQD field */ - #define INT_IRQD (0x00008000u) - #define INT_IRQD_MASK (0x00008000u) - #define INT_IRQD_BIT (15) - #define INT_IRQD_BITS (1) - /* INT_IRQC field */ - #define INT_IRQC (0x00004000u) - #define INT_IRQC_MASK (0x00004000u) - #define INT_IRQC_BIT (14) - #define INT_IRQC_BITS (1) - /* INT_IRQB field */ - #define INT_IRQB (0x00002000u) - #define INT_IRQB_MASK (0x00002000u) - #define INT_IRQB_BIT (13) - #define INT_IRQB_BITS (1) - /* INT_IRQA field */ - #define INT_IRQA (0x00001000u) - #define INT_IRQA_MASK (0x00001000u) - #define INT_IRQA_BIT (12) - #define INT_IRQA_BITS (1) - /* INT_ADC field */ - #define INT_ADC (0x00000800u) - #define INT_ADC_MASK (0x00000800u) - #define INT_ADC_BIT (11) - #define INT_ADC_BITS (1) - /* INT_MACRX field */ - #define INT_MACRX (0x00000400u) - #define INT_MACRX_MASK (0x00000400u) - #define INT_MACRX_BIT (10) - #define INT_MACRX_BITS (1) - /* INT_MACTX field */ - #define INT_MACTX (0x00000200u) - #define INT_MACTX_MASK (0x00000200u) - #define INT_MACTX_BIT (9) - #define INT_MACTX_BITS (1) - /* INT_MACTMR field */ - #define INT_MACTMR (0x00000100u) - #define INT_MACTMR_MASK (0x00000100u) - #define INT_MACTMR_BIT (8) - #define INT_MACTMR_BITS (1) - /* INT_SEC field */ - #define INT_SEC (0x00000080u) - #define INT_SEC_MASK (0x00000080u) - #define INT_SEC_BIT (7) - #define INT_SEC_BITS (1) - /* INT_SC2 field */ - #define INT_SC2 (0x00000040u) - #define INT_SC2_MASK (0x00000040u) - #define INT_SC2_BIT (6) - #define INT_SC2_BITS (1) - /* INT_SC1 field */ - #define INT_SC1 (0x00000020u) - #define INT_SC1_MASK (0x00000020u) - #define INT_SC1_BIT (5) - #define INT_SC1_BITS (1) - /* INT_SLEEPTMR field */ - #define INT_SLEEPTMR (0x00000010u) - #define INT_SLEEPTMR_MASK (0x00000010u) - #define INT_SLEEPTMR_BIT (4) - #define INT_SLEEPTMR_BITS (1) - /* INT_BB field */ - #define INT_BB (0x00000008u) - #define INT_BB_MASK (0x00000008u) - #define INT_BB_BIT (3) - #define INT_BB_BITS (1) - /* INT_MGMT field */ - #define INT_MGMT (0x00000004u) - #define INT_MGMT_MASK (0x00000004u) - #define INT_MGMT_BIT (2) - #define INT_MGMT_BITS (1) - /* INT_TIM2 field */ - #define INT_TIM2 (0x00000002u) - #define INT_TIM2_MASK (0x00000002u) - #define INT_TIM2_BIT (1) - #define INT_TIM2_BITS (1) - /* INT_TIM1 field */ - #define INT_TIM1 (0x00000001u) - #define INT_TIM1_MASK (0x00000001u) - #define INT_TIM1_BIT (0) - #define INT_TIM1_BITS (1) +/* INT_DEBUG field */ +#define INT_DEBUG (0x00010000u) +#define INT_DEBUG_MASK (0x00010000u) +#define INT_DEBUG_BIT (16) +#define INT_DEBUG_BITS (1) +/* INT_IRQD field */ +#define INT_IRQD (0x00008000u) +#define INT_IRQD_MASK (0x00008000u) +#define INT_IRQD_BIT (15) +#define INT_IRQD_BITS (1) +/* INT_IRQC field */ +#define INT_IRQC (0x00004000u) +#define INT_IRQC_MASK (0x00004000u) +#define INT_IRQC_BIT (14) +#define INT_IRQC_BITS (1) +/* INT_IRQB field */ +#define INT_IRQB (0x00002000u) +#define INT_IRQB_MASK (0x00002000u) +#define INT_IRQB_BIT (13) +#define INT_IRQB_BITS (1) +/* INT_IRQA field */ +#define INT_IRQA (0x00001000u) +#define INT_IRQA_MASK (0x00001000u) +#define INT_IRQA_BIT (12) +#define INT_IRQA_BITS (1) +/* INT_ADC field */ +#define INT_ADC (0x00000800u) +#define INT_ADC_MASK (0x00000800u) +#define INT_ADC_BIT (11) +#define INT_ADC_BITS (1) +/* INT_MACRX field */ +#define INT_MACRX (0x00000400u) +#define INT_MACRX_MASK (0x00000400u) +#define INT_MACRX_BIT (10) +#define INT_MACRX_BITS (1) +/* INT_MACTX field */ +#define INT_MACTX (0x00000200u) +#define INT_MACTX_MASK (0x00000200u) +#define INT_MACTX_BIT (9) +#define INT_MACTX_BITS (1) +/* INT_MACTMR field */ +#define INT_MACTMR (0x00000100u) +#define INT_MACTMR_MASK (0x00000100u) +#define INT_MACTMR_BIT (8) +#define INT_MACTMR_BITS (1) +/* INT_SEC field */ +#define INT_SEC (0x00000080u) +#define INT_SEC_MASK (0x00000080u) +#define INT_SEC_BIT (7) +#define INT_SEC_BITS (1) +/* INT_SC2 field */ +#define INT_SC2 (0x00000040u) +#define INT_SC2_MASK (0x00000040u) +#define INT_SC2_BIT (6) +#define INT_SC2_BITS (1) +/* INT_SC1 field */ +#define INT_SC1 (0x00000020u) +#define INT_SC1_MASK (0x00000020u) +#define INT_SC1_BIT (5) +#define INT_SC1_BITS (1) +/* INT_SLEEPTMR field */ +#define INT_SLEEPTMR (0x00000010u) +#define INT_SLEEPTMR_MASK (0x00000010u) +#define INT_SLEEPTMR_BIT (4) +#define INT_SLEEPTMR_BITS (1) +/* INT_BB field */ +#define INT_BB (0x00000008u) +#define INT_BB_MASK (0x00000008u) +#define INT_BB_BIT (3) +#define INT_BB_BITS (1) +/* INT_MGMT field */ +#define INT_MGMT (0x00000004u) +#define INT_MGMT_MASK (0x00000004u) +#define INT_MGMT_BIT (2) +#define INT_MGMT_BITS (1) +/* INT_TIM2 field */ +#define INT_TIM2 (0x00000002u) +#define INT_TIM2_MASK (0x00000002u) +#define INT_TIM2_BIT (1) +#define INT_TIM2_BITS (1) +/* INT_TIM1 field */ +#define INT_TIM1 (0x00000001u) +#define INT_TIM1_MASK (0x00000001u) +#define INT_TIM1_BIT (0) +#define INT_TIM1_BITS (1) #define NVIC_IPR_3to0 *((volatile uint32_t *)0xE000E400u) #define NVIC_IPR_3to0_REG *((volatile uint32_t *)0xE000E400u) #define NVIC_IPR_3to0_ADDR (0xE000E400u) #define NVIC_IPR_3to0_RESET (0x00000000u) - /* PRI_3 field */ - #define NVIC_IPR_3to0_PRI_3 (0xFF000000u) - #define NVIC_IPR_3to0_PRI_3_MASK (0xFF000000u) - #define NVIC_IPR_3to0_PRI_3_BIT (24) - #define NVIC_IPR_3to0_PRI_3_BITS (8) - /* PRI_2 field */ - #define NVIC_IPR_3to0_PRI_2 (0x00FF0000u) - #define NVIC_IPR_3to0_PRI_2_MASK (0x00FF0000u) - #define NVIC_IPR_3to0_PRI_2_BIT (16) - #define NVIC_IPR_3to0_PRI_2_BITS (8) - /* PRI_1 field */ - #define NVIC_IPR_3to0_PRI_1 (0x0000FF00u) - #define NVIC_IPR_3to0_PRI_1_MASK (0x0000FF00u) - #define NVIC_IPR_3to0_PRI_1_BIT (8) - #define NVIC_IPR_3to0_PRI_1_BITS (8) - /* PRI_0 field */ - #define NVIC_IPR_3to0_PRI_0 (0x000000FFu) - #define NVIC_IPR_3to0_PRI_0_MASK (0x000000FFu) - #define NVIC_IPR_3to0_PRI_0_BIT (0) - #define NVIC_IPR_3to0_PRI_0_BITS (8) +/* PRI_3 field */ +#define NVIC_IPR_3to0_PRI_3 (0xFF000000u) +#define NVIC_IPR_3to0_PRI_3_MASK (0xFF000000u) +#define NVIC_IPR_3to0_PRI_3_BIT (24) +#define NVIC_IPR_3to0_PRI_3_BITS (8) +/* PRI_2 field */ +#define NVIC_IPR_3to0_PRI_2 (0x00FF0000u) +#define NVIC_IPR_3to0_PRI_2_MASK (0x00FF0000u) +#define NVIC_IPR_3to0_PRI_2_BIT (16) +#define NVIC_IPR_3to0_PRI_2_BITS (8) +/* PRI_1 field */ +#define NVIC_IPR_3to0_PRI_1 (0x0000FF00u) +#define NVIC_IPR_3to0_PRI_1_MASK (0x0000FF00u) +#define NVIC_IPR_3to0_PRI_1_BIT (8) +#define NVIC_IPR_3to0_PRI_1_BITS (8) +/* PRI_0 field */ +#define NVIC_IPR_3to0_PRI_0 (0x000000FFu) +#define NVIC_IPR_3to0_PRI_0_MASK (0x000000FFu) +#define NVIC_IPR_3to0_PRI_0_BIT (0) +#define NVIC_IPR_3to0_PRI_0_BITS (8) #define NVIC_IPR_7to4 *((volatile uint32_t *)0xE000E404u) #define NVIC_IPR_7to4_REG *((volatile uint32_t *)0xE000E404u) #define NVIC_IPR_7to4_ADDR (0xE000E404u) #define NVIC_IPR_7to4_RESET (0x00000000u) - /* PRI_7 field */ - #define NVIC_IPR_7to4_PRI_7 (0xFF000000u) - #define NVIC_IPR_7to4_PRI_7_MASK (0xFF000000u) - #define NVIC_IPR_7to4_PRI_7_BIT (24) - #define NVIC_IPR_7to4_PRI_7_BITS (8) - /* PRI_6 field */ - #define NVIC_IPR_7to4_PRI_6 (0x00FF0000u) - #define NVIC_IPR_7to4_PRI_6_MASK (0x00FF0000u) - #define NVIC_IPR_7to4_PRI_6_BIT (16) - #define NVIC_IPR_7to4_PRI_6_BITS (8) - /* PRI_5 field */ - #define NVIC_IPR_7to4_PRI_5 (0x0000FF00u) - #define NVIC_IPR_7to4_PRI_5_MASK (0x0000FF00u) - #define NVIC_IPR_7to4_PRI_5_BIT (8) - #define NVIC_IPR_7to4_PRI_5_BITS (8) - /* PRI_4 field */ - #define NVIC_IPR_7to4_PRI_4 (0x000000FFu) - #define NVIC_IPR_7to4_PRI_4_MASK (0x000000FFu) - #define NVIC_IPR_7to4_PRI_4_BIT (0) - #define NVIC_IPR_7to4_PRI_4_BITS (8) +/* PRI_7 field */ +#define NVIC_IPR_7to4_PRI_7 (0xFF000000u) +#define NVIC_IPR_7to4_PRI_7_MASK (0xFF000000u) +#define NVIC_IPR_7to4_PRI_7_BIT (24) +#define NVIC_IPR_7to4_PRI_7_BITS (8) +/* PRI_6 field */ +#define NVIC_IPR_7to4_PRI_6 (0x00FF0000u) +#define NVIC_IPR_7to4_PRI_6_MASK (0x00FF0000u) +#define NVIC_IPR_7to4_PRI_6_BIT (16) +#define NVIC_IPR_7to4_PRI_6_BITS (8) +/* PRI_5 field */ +#define NVIC_IPR_7to4_PRI_5 (0x0000FF00u) +#define NVIC_IPR_7to4_PRI_5_MASK (0x0000FF00u) +#define NVIC_IPR_7to4_PRI_5_BIT (8) +#define NVIC_IPR_7to4_PRI_5_BITS (8) +/* PRI_4 field */ +#define NVIC_IPR_7to4_PRI_4 (0x000000FFu) +#define NVIC_IPR_7to4_PRI_4_MASK (0x000000FFu) +#define NVIC_IPR_7to4_PRI_4_BIT (0) +#define NVIC_IPR_7to4_PRI_4_BITS (8) #define NVIC_IPR_11to8 *((volatile uint32_t *)0xE000E408u) #define NVIC_IPR_11to8_REG *((volatile uint32_t *)0xE000E408u) #define NVIC_IPR_11to8_ADDR (0xE000E408u) #define NVIC_IPR_11to8_RESET (0x00000000u) - /* PRI_11 field */ - #define NVIC_IPR_11to8_PRI_11 (0xFF000000u) - #define NVIC_IPR_11to8_PRI_11_MASK (0xFF000000u) - #define NVIC_IPR_11to8_PRI_11_BIT (24) - #define NVIC_IPR_11to8_PRI_11_BITS (8) - /* PRI_10 field */ - #define NVIC_IPR_11to8_PRI_10 (0x00FF0000u) - #define NVIC_IPR_11to8_PRI_10_MASK (0x00FF0000u) - #define NVIC_IPR_11to8_PRI_10_BIT (16) - #define NVIC_IPR_11to8_PRI_10_BITS (8) - /* PRI_9 field */ - #define NVIC_IPR_11to8_PRI_9 (0x0000FF00u) - #define NVIC_IPR_11to8_PRI_9_MASK (0x0000FF00u) - #define NVIC_IPR_11to8_PRI_9_BIT (8) - #define NVIC_IPR_11to8_PRI_9_BITS (8) - /* PRI_8 field */ - #define NVIC_IPR_11to8_PRI_8 (0x000000FFu) - #define NVIC_IPR_11to8_PRI_8_MASK (0x000000FFu) - #define NVIC_IPR_11to8_PRI_8_BIT (0) - #define NVIC_IPR_11to8_PRI_8_BITS (8) +/* PRI_11 field */ +#define NVIC_IPR_11to8_PRI_11 (0xFF000000u) +#define NVIC_IPR_11to8_PRI_11_MASK (0xFF000000u) +#define NVIC_IPR_11to8_PRI_11_BIT (24) +#define NVIC_IPR_11to8_PRI_11_BITS (8) +/* PRI_10 field */ +#define NVIC_IPR_11to8_PRI_10 (0x00FF0000u) +#define NVIC_IPR_11to8_PRI_10_MASK (0x00FF0000u) +#define NVIC_IPR_11to8_PRI_10_BIT (16) +#define NVIC_IPR_11to8_PRI_10_BITS (8) +/* PRI_9 field */ +#define NVIC_IPR_11to8_PRI_9 (0x0000FF00u) +#define NVIC_IPR_11to8_PRI_9_MASK (0x0000FF00u) +#define NVIC_IPR_11to8_PRI_9_BIT (8) +#define NVIC_IPR_11to8_PRI_9_BITS (8) +/* PRI_8 field */ +#define NVIC_IPR_11to8_PRI_8 (0x000000FFu) +#define NVIC_IPR_11to8_PRI_8_MASK (0x000000FFu) +#define NVIC_IPR_11to8_PRI_8_BIT (0) +#define NVIC_IPR_11to8_PRI_8_BITS (8) #define NVIC_IPR_15to12 *((volatile uint32_t *)0xE000E40Cu) #define NVIC_IPR_15to12_REG *((volatile uint32_t *)0xE000E40Cu) #define NVIC_IPR_15to12_ADDR (0xE000E40Cu) #define NVIC_IPR_15to12_RESET (0x00000000u) - /* PRI_15 field */ - #define NVIC_IPR_15to12_PRI_15 (0xFF000000u) - #define NVIC_IPR_15to12_PRI_15_MASK (0xFF000000u) - #define NVIC_IPR_15to12_PRI_15_BIT (24) - #define NVIC_IPR_15to12_PRI_15_BITS (8) - /* PRI_14 field */ - #define NVIC_IPR_15to12_PRI_14 (0x00FF0000u) - #define NVIC_IPR_15to12_PRI_14_MASK (0x00FF0000u) - #define NVIC_IPR_15to12_PRI_14_BIT (16) - #define NVIC_IPR_15to12_PRI_14_BITS (8) - /* PRI_13 field */ - #define NVIC_IPR_15to12_PRI_13 (0x0000FF00u) - #define NVIC_IPR_15to12_PRI_13_MASK (0x0000FF00u) - #define NVIC_IPR_15to12_PRI_13_BIT (8) - #define NVIC_IPR_15to12_PRI_13_BITS (8) - /* PRI_12 field */ - #define NVIC_IPR_15to12_PRI_12 (0x000000FFu) - #define NVIC_IPR_15to12_PRI_12_MASK (0x000000FFu) - #define NVIC_IPR_15to12_PRI_12_BIT (0) - #define NVIC_IPR_15to12_PRI_12_BITS (8) +/* PRI_15 field */ +#define NVIC_IPR_15to12_PRI_15 (0xFF000000u) +#define NVIC_IPR_15to12_PRI_15_MASK (0xFF000000u) +#define NVIC_IPR_15to12_PRI_15_BIT (24) +#define NVIC_IPR_15to12_PRI_15_BITS (8) +/* PRI_14 field */ +#define NVIC_IPR_15to12_PRI_14 (0x00FF0000u) +#define NVIC_IPR_15to12_PRI_14_MASK (0x00FF0000u) +#define NVIC_IPR_15to12_PRI_14_BIT (16) +#define NVIC_IPR_15to12_PRI_14_BITS (8) +/* PRI_13 field */ +#define NVIC_IPR_15to12_PRI_13 (0x0000FF00u) +#define NVIC_IPR_15to12_PRI_13_MASK (0x0000FF00u) +#define NVIC_IPR_15to12_PRI_13_BIT (8) +#define NVIC_IPR_15to12_PRI_13_BITS (8) +/* PRI_12 field */ +#define NVIC_IPR_15to12_PRI_12 (0x000000FFu) +#define NVIC_IPR_15to12_PRI_12_MASK (0x000000FFu) +#define NVIC_IPR_15to12_PRI_12_BIT (0) +#define NVIC_IPR_15to12_PRI_12_BITS (8) #define NVIC_IPR_19to16 *((volatile uint32_t *)0xE000E410u) #define NVIC_IPR_19to16_REG *((volatile uint32_t *)0xE000E410u) #define NVIC_IPR_19to16_ADDR (0xE000E410u) #define NVIC_IPR_19to16_RESET (0x00000000u) - /* PRI_19 field */ - #define NVIC_IPR_19to16_PRI_19 (0xFF000000u) - #define NVIC_IPR_19to16_PRI_19_MASK (0xFF000000u) - #define NVIC_IPR_19to16_PRI_19_BIT (24) - #define NVIC_IPR_19to16_PRI_19_BITS (8) - /* PRI_18 field */ - #define NVIC_IPR_19to16_PRI_18 (0x00FF0000u) - #define NVIC_IPR_19to16_PRI_18_MASK (0x00FF0000u) - #define NVIC_IPR_19to16_PRI_18_BIT (16) - #define NVIC_IPR_19to16_PRI_18_BITS (8) - /* PRI_17 field */ - #define NVIC_IPR_19to16_PRI_17 (0x0000FF00u) - #define NVIC_IPR_19to16_PRI_17_MASK (0x0000FF00u) - #define NVIC_IPR_19to16_PRI_17_BIT (8) - #define NVIC_IPR_19to16_PRI_17_BITS (8) - /* PRI_16 field */ - #define NVIC_IPR_19to16_PRI_16 (0x000000FFu) - #define NVIC_IPR_19to16_PRI_16_MASK (0x000000FFu) - #define NVIC_IPR_19to16_PRI_16_BIT (0) - #define NVIC_IPR_19to16_PRI_16_BITS (8) +/* PRI_19 field */ +#define NVIC_IPR_19to16_PRI_19 (0xFF000000u) +#define NVIC_IPR_19to16_PRI_19_MASK (0xFF000000u) +#define NVIC_IPR_19to16_PRI_19_BIT (24) +#define NVIC_IPR_19to16_PRI_19_BITS (8) +/* PRI_18 field */ +#define NVIC_IPR_19to16_PRI_18 (0x00FF0000u) +#define NVIC_IPR_19to16_PRI_18_MASK (0x00FF0000u) +#define NVIC_IPR_19to16_PRI_18_BIT (16) +#define NVIC_IPR_19to16_PRI_18_BITS (8) +/* PRI_17 field */ +#define NVIC_IPR_19to16_PRI_17 (0x0000FF00u) +#define NVIC_IPR_19to16_PRI_17_MASK (0x0000FF00u) +#define NVIC_IPR_19to16_PRI_17_BIT (8) +#define NVIC_IPR_19to16_PRI_17_BITS (8) +/* PRI_16 field */ +#define NVIC_IPR_19to16_PRI_16 (0x000000FFu) +#define NVIC_IPR_19to16_PRI_16_MASK (0x000000FFu) +#define NVIC_IPR_19to16_PRI_16_BIT (0) +#define NVIC_IPR_19to16_PRI_16_BITS (8) #define SCS_CPUID *((volatile uint32_t *)0xE000ED00u) #define SCS_CPUID_REG *((volatile uint32_t *)0xE000ED00u) #define SCS_CPUID_ADDR (0xE000ED00u) #define SCS_CPUID_RESET (0x411FC231u) - /* IMPLEMENTER field */ - #define SCS_CPUID_IMPLEMENTER (0xFF000000u) - #define SCS_CPUID_IMPLEMENTER_MASK (0xFF000000u) - #define SCS_CPUID_IMPLEMENTER_BIT (24) - #define SCS_CPUID_IMPLEMENTER_BITS (8) - /* VARIANT field */ - #define SCS_CPUID_VARIANT (0x00F00000u) - #define SCS_CPUID_VARIANT_MASK (0x00F00000u) - #define SCS_CPUID_VARIANT_BIT (20) - #define SCS_CPUID_VARIANT_BITS (4) - /* CONSTANT field */ - #define SCS_CPUID_CONSTANT (0x000F0000u) - #define SCS_CPUID_CONSTANT_MASK (0x000F0000u) - #define SCS_CPUID_CONSTANT_BIT (16) - #define SCS_CPUID_CONSTANT_BITS (4) - /* PARTNO field */ - #define SCS_CPUID_PARTNO (0x0000FFF0u) - #define SCS_CPUID_PARTNO_MASK (0x0000FFF0u) - #define SCS_CPUID_PARTNO_BIT (4) - #define SCS_CPUID_PARTNO_BITS (12) - /* REVISION field */ - #define SCS_CPUID_REVISION (0x0000000Fu) - #define SCS_CPUID_REVISION_MASK (0x0000000Fu) - #define SCS_CPUID_REVISION_BIT (0) - #define SCS_CPUID_REVISION_BITS (4) +/* IMPLEMENTER field */ +#define SCS_CPUID_IMPLEMENTER (0xFF000000u) +#define SCS_CPUID_IMPLEMENTER_MASK (0xFF000000u) +#define SCS_CPUID_IMPLEMENTER_BIT (24) +#define SCS_CPUID_IMPLEMENTER_BITS (8) +/* VARIANT field */ +#define SCS_CPUID_VARIANT (0x00F00000u) +#define SCS_CPUID_VARIANT_MASK (0x00F00000u) +#define SCS_CPUID_VARIANT_BIT (20) +#define SCS_CPUID_VARIANT_BITS (4) +/* CONSTANT field */ +#define SCS_CPUID_CONSTANT (0x000F0000u) +#define SCS_CPUID_CONSTANT_MASK (0x000F0000u) +#define SCS_CPUID_CONSTANT_BIT (16) +#define SCS_CPUID_CONSTANT_BITS (4) +/* PARTNO field */ +#define SCS_CPUID_PARTNO (0x0000FFF0u) +#define SCS_CPUID_PARTNO_MASK (0x0000FFF0u) +#define SCS_CPUID_PARTNO_BIT (4) +#define SCS_CPUID_PARTNO_BITS (12) +/* REVISION field */ +#define SCS_CPUID_REVISION (0x0000000Fu) +#define SCS_CPUID_REVISION_MASK (0x0000000Fu) +#define SCS_CPUID_REVISION_BIT (0) +#define SCS_CPUID_REVISION_BITS (4) #define SCS_ICSR *((volatile uint32_t *)0xE000ED04u) #define SCS_ICSR_REG *((volatile uint32_t *)0xE000ED04u) #define SCS_ICSR_ADDR (0xE000ED04u) #define SCS_ICSR_RESET (0x00000000u) - /* NMIPENDSET field */ - #define SCS_ICSR_NMIPENDSET (0x80000000u) - #define SCS_ICSR_NMIPENDSET_MASK (0x80000000u) - #define SCS_ICSR_NMIPENDSET_BIT (31) - #define SCS_ICSR_NMIPENDSET_BITS (1) - /* PENDSVSET field */ - #define SCS_ICSR_PENDSVSET (0x10000000u) - #define SCS_ICSR_PENDSVSET_MASK (0x10000000u) - #define SCS_ICSR_PENDSVSET_BIT (28) - #define SCS_ICSR_PENDSVSET_BITS (1) - /* PENDSVCLR field */ - #define SCS_ICSR_PENDSVCLR (0x08000000u) - #define SCS_ICSR_PENDSVCLR_MASK (0x08000000u) - #define SCS_ICSR_PENDSVCLR_BIT (27) - #define SCS_ICSR_PENDSVCLR_BITS (1) - /* PENDSTSET field */ - #define SCS_ICSR_PENDSTSET (0x04000000u) - #define SCS_ICSR_PENDSTSET_MASK (0x04000000u) - #define SCS_ICSR_PENDSTSET_BIT (26) - #define SCS_ICSR_PENDSTSET_BITS (1) - /* PENDSTCLR field */ - #define SCS_ICSR_PENDSTCLR (0x02000000u) - #define SCS_ICSR_PENDSTCLR_MASK (0x02000000u) - #define SCS_ICSR_PENDSTCLR_BIT (25) - #define SCS_ICSR_PENDSTCLR_BITS (1) - /* ISRPREEMPT field */ - #define SCS_ICSR_ISRPREEMPT (0x00800000u) - #define SCS_ICSR_ISRPREEMPT_MASK (0x00800000u) - #define SCS_ICSR_ISRPREEMPT_BIT (23) - #define SCS_ICSR_ISRPREEMPT_BITS (1) - /* ISRPENDING field */ - #define SCS_ICSR_ISRPENDING (0x00400000u) - #define SCS_ICSR_ISRPENDING_MASK (0x00400000u) - #define SCS_ICSR_ISRPENDING_BIT (22) - #define SCS_ICSR_ISRPENDING_BITS (1) - /* VECTPENDING field */ - #define SCS_ICSR_VECTPENDING (0x001FF000u) - #define SCS_ICSR_VECTPENDING_MASK (0x001FF000u) - #define SCS_ICSR_VECTPENDING_BIT (12) - #define SCS_ICSR_VECTPENDING_BITS (9) - /* RETTOBASE field */ - #define SCS_ICSR_RETTOBASE (0x00000800u) - #define SCS_ICSR_RETTOBASE_MASK (0x00000800u) - #define SCS_ICSR_RETTOBASE_BIT (11) - #define SCS_ICSR_RETTOBASE_BITS (1) - /* VECACTIVE field */ - #define SCS_ICSR_VECACTIVE (0x000001FFu) - #define SCS_ICSR_VECACTIVE_MASK (0x000001FFu) - #define SCS_ICSR_VECACTIVE_BIT (0) - #define SCS_ICSR_VECACTIVE_BITS (9) +/* NMIPENDSET field */ +#define SCS_ICSR_NMIPENDSET (0x80000000u) +#define SCS_ICSR_NMIPENDSET_MASK (0x80000000u) +#define SCS_ICSR_NMIPENDSET_BIT (31) +#define SCS_ICSR_NMIPENDSET_BITS (1) +/* PENDSVSET field */ +#define SCS_ICSR_PENDSVSET (0x10000000u) +#define SCS_ICSR_PENDSVSET_MASK (0x10000000u) +#define SCS_ICSR_PENDSVSET_BIT (28) +#define SCS_ICSR_PENDSVSET_BITS (1) +/* PENDSVCLR field */ +#define SCS_ICSR_PENDSVCLR (0x08000000u) +#define SCS_ICSR_PENDSVCLR_MASK (0x08000000u) +#define SCS_ICSR_PENDSVCLR_BIT (27) +#define SCS_ICSR_PENDSVCLR_BITS (1) +/* PENDSTSET field */ +#define SCS_ICSR_PENDSTSET (0x04000000u) +#define SCS_ICSR_PENDSTSET_MASK (0x04000000u) +#define SCS_ICSR_PENDSTSET_BIT (26) +#define SCS_ICSR_PENDSTSET_BITS (1) +/* PENDSTCLR field */ +#define SCS_ICSR_PENDSTCLR (0x02000000u) +#define SCS_ICSR_PENDSTCLR_MASK (0x02000000u) +#define SCS_ICSR_PENDSTCLR_BIT (25) +#define SCS_ICSR_PENDSTCLR_BITS (1) +/* ISRPREEMPT field */ +#define SCS_ICSR_ISRPREEMPT (0x00800000u) +#define SCS_ICSR_ISRPREEMPT_MASK (0x00800000u) +#define SCS_ICSR_ISRPREEMPT_BIT (23) +#define SCS_ICSR_ISRPREEMPT_BITS (1) +/* ISRPENDING field */ +#define SCS_ICSR_ISRPENDING (0x00400000u) +#define SCS_ICSR_ISRPENDING_MASK (0x00400000u) +#define SCS_ICSR_ISRPENDING_BIT (22) +#define SCS_ICSR_ISRPENDING_BITS (1) +/* VECTPENDING field */ +#define SCS_ICSR_VECTPENDING (0x001FF000u) +#define SCS_ICSR_VECTPENDING_MASK (0x001FF000u) +#define SCS_ICSR_VECTPENDING_BIT (12) +#define SCS_ICSR_VECTPENDING_BITS (9) +/* RETTOBASE field */ +#define SCS_ICSR_RETTOBASE (0x00000800u) +#define SCS_ICSR_RETTOBASE_MASK (0x00000800u) +#define SCS_ICSR_RETTOBASE_BIT (11) +#define SCS_ICSR_RETTOBASE_BITS (1) +/* VECACTIVE field */ +#define SCS_ICSR_VECACTIVE (0x000001FFu) +#define SCS_ICSR_VECACTIVE_MASK (0x000001FFu) +#define SCS_ICSR_VECACTIVE_BIT (0) +#define SCS_ICSR_VECACTIVE_BITS (9) #define SCS_VTOR *((volatile uint32_t *)0xE000ED08u) #define SCS_VTOR_REG *((volatile uint32_t *)0xE000ED08u) #define SCS_VTOR_ADDR (0xE000ED08u) #define SCS_VTOR_RESET (0x00000000u) - /* TBLBASE field */ - #define SCS_VTOR_TBLBASE (0x20000000u) - #define SCS_VTOR_TBLBASE_MASK (0x20000000u) - #define SCS_VTOR_TBLBASE_BIT (29) - #define SCS_VTOR_TBLBASE_BITS (1) - /* TBLOFF field */ - #define SCS_VTOR_TBLOFF (0x1FFFFF00u) - #define SCS_VTOR_TBLOFF_MASK (0x1FFFFF00u) - #define SCS_VTOR_TBLOFF_BIT (8) - #define SCS_VTOR_TBLOFF_BITS (21) +/* TBLBASE field */ +#define SCS_VTOR_TBLBASE (0x20000000u) +#define SCS_VTOR_TBLBASE_MASK (0x20000000u) +#define SCS_VTOR_TBLBASE_BIT (29) +#define SCS_VTOR_TBLBASE_BITS (1) +/* TBLOFF field */ +#define SCS_VTOR_TBLOFF (0x1FFFFF00u) +#define SCS_VTOR_TBLOFF_MASK (0x1FFFFF00u) +#define SCS_VTOR_TBLOFF_BIT (8) +#define SCS_VTOR_TBLOFF_BITS (21) #define SCS_AIRCR *((volatile uint32_t *)0xE000ED0Cu) #define SCS_AIRCR_REG *((volatile uint32_t *)0xE000ED0Cu) #define SCS_AIRCR_ADDR (0xE000ED0Cu) #define SCS_AIRCR_RESET (0x00000000u) - /* VECTKEYSTAT field */ - #define SCS_AIRCR_VECTKEYSTAT (0xFFFF0000u) - #define SCS_AIRCR_VECTKEYSTAT_MASK (0xFFFF0000u) - #define SCS_AIRCR_VECTKEYSTAT_BIT (16) - #define SCS_AIRCR_VECTKEYSTAT_BITS (16) - /* VECTKEY field */ - #define SCS_AIRCR_VECTKEY (0xFFFF0000u) - #define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u) - #define SCS_AIRCR_VECTKEY_BIT (16) - #define SCS_AIRCR_VECTKEY_BITS (16) - /* ENDIANESS field */ - #define SCS_AIRCR_ENDIANESS (0x00008000u) - #define SCS_AIRCR_ENDIANESS_MASK (0x00008000u) - #define SCS_AIRCR_ENDIANESS_BIT (15) - #define SCS_AIRCR_ENDIANESS_BITS (1) - /* PRIGROUP field */ - #define SCS_AIRCR_PRIGROUP (0x00000700u) - #define SCS_AIRCR_PRIGROUP_MASK (0x00000700u) - #define SCS_AIRCR_PRIGROUP_BIT (8) - #define SCS_AIRCR_PRIGROUP_BITS (3) - /* SYSRESETREQ field */ - #define SCS_AIRCR_SYSRESETREQ (0x00000004u) - #define SCS_AIRCR_SYSRESETREQ_MASK (0x00000004u) - #define SCS_AIRCR_SYSRESETREQ_BIT (2) - #define SCS_AIRCR_SYSRESETREQ_BITS (1) - /* VECTCLRACTIVE field */ - #define SCS_AIRCR_VECTCLRACTIVE (0x00000002u) - #define SCS_AIRCR_VECTCLRACTIVE_MASK (0x00000002u) - #define SCS_AIRCR_VECTCLRACTIVE_BIT (1) - #define SCS_AIRCR_VECTCLRACTIVE_BITS (1) - /* VECTRESET field */ - #define SCS_AIRCR_VECTRESET (0x00000001u) - #define SCS_AIRCR_VECTRESET_MASK (0x00000001u) - #define SCS_AIRCR_VECTRESET_BIT (0) - #define SCS_AIRCR_VECTRESET_BITS (1) +/* VECTKEYSTAT field */ +#define SCS_AIRCR_VECTKEYSTAT (0xFFFF0000u) +#define SCS_AIRCR_VECTKEYSTAT_MASK (0xFFFF0000u) +#define SCS_AIRCR_VECTKEYSTAT_BIT (16) +#define SCS_AIRCR_VECTKEYSTAT_BITS (16) +/* VECTKEY field */ +#define SCS_AIRCR_VECTKEY (0xFFFF0000u) +#define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u) +#define SCS_AIRCR_VECTKEY_BIT (16) +#define SCS_AIRCR_VECTKEY_BITS (16) +/* ENDIANESS field */ +#define SCS_AIRCR_ENDIANESS (0x00008000u) +#define SCS_AIRCR_ENDIANESS_MASK (0x00008000u) +#define SCS_AIRCR_ENDIANESS_BIT (15) +#define SCS_AIRCR_ENDIANESS_BITS (1) +/* PRIGROUP field */ +#define SCS_AIRCR_PRIGROUP (0x00000700u) +#define SCS_AIRCR_PRIGROUP_MASK (0x00000700u) +#define SCS_AIRCR_PRIGROUP_BIT (8) +#define SCS_AIRCR_PRIGROUP_BITS (3) +/* SYSRESETREQ field */ +#define SCS_AIRCR_SYSRESETREQ (0x00000004u) +#define SCS_AIRCR_SYSRESETREQ_MASK (0x00000004u) +#define SCS_AIRCR_SYSRESETREQ_BIT (2) +#define SCS_AIRCR_SYSRESETREQ_BITS (1) +/* VECTCLRACTIVE field */ +#define SCS_AIRCR_VECTCLRACTIVE (0x00000002u) +#define SCS_AIRCR_VECTCLRACTIVE_MASK (0x00000002u) +#define SCS_AIRCR_VECTCLRACTIVE_BIT (1) +#define SCS_AIRCR_VECTCLRACTIVE_BITS (1) +/* VECTRESET field */ +#define SCS_AIRCR_VECTRESET (0x00000001u) +#define SCS_AIRCR_VECTRESET_MASK (0x00000001u) +#define SCS_AIRCR_VECTRESET_BIT (0) +#define SCS_AIRCR_VECTRESET_BITS (1) #define SCS_SCR *((volatile uint32_t *)0xE000ED10u) #define SCS_SCR_REG *((volatile uint32_t *)0xE000ED10u) #define SCS_SCR_ADDR (0xE000ED10u) #define SCS_SCR_RESET (0x00000000u) - /* SEVONPEND field */ - #define SCS_SCR_SEVONPEND (0x00000010u) - #define SCS_SCR_SEVONPEND_MASK (0x00000010u) - #define SCS_SCR_SEVONPEND_BIT (4) - #define SCS_SCR_SEVONPEND_BITS (1) - /* SLEEPDEEP field */ - #define SCS_SCR_SLEEPDEEP (0x00000004u) - #define SCS_SCR_SLEEPDEEP_MASK (0x00000004u) - #define SCS_SCR_SLEEPDEEP_BIT (2) - #define SCS_SCR_SLEEPDEEP_BITS (1) - /* SLEEPONEXIT field */ - #define SCS_SCR_SLEEPONEXIT (0x00000002u) - #define SCS_SCR_SLEEPONEXIT_MASK (0x00000002u) - #define SCS_SCR_SLEEPONEXIT_BIT (1) - #define SCS_SCR_SLEEPONEXIT_BITS (1) +/* SEVONPEND field */ +#define SCS_SCR_SEVONPEND (0x00000010u) +#define SCS_SCR_SEVONPEND_MASK (0x00000010u) +#define SCS_SCR_SEVONPEND_BIT (4) +#define SCS_SCR_SEVONPEND_BITS (1) +/* SLEEPDEEP field */ +#define SCS_SCR_SLEEPDEEP (0x00000004u) +#define SCS_SCR_SLEEPDEEP_MASK (0x00000004u) +#define SCS_SCR_SLEEPDEEP_BIT (2) +#define SCS_SCR_SLEEPDEEP_BITS (1) +/* SLEEPONEXIT field */ +#define SCS_SCR_SLEEPONEXIT (0x00000002u) +#define SCS_SCR_SLEEPONEXIT_MASK (0x00000002u) +#define SCS_SCR_SLEEPONEXIT_BIT (1) +#define SCS_SCR_SLEEPONEXIT_BITS (1) #define SCS_CCR *((volatile uint32_t *)0xE000ED14u) #define SCS_CCR_REG *((volatile uint32_t *)0xE000ED14u) #define SCS_CCR_ADDR (0xE000ED14u) #define SCS_CCR_RESET (0x00000000u) - /* STKALIGN field */ - #define SCS_CCR_STKALIGN (0x00000200u) - #define SCS_CCR_STKALIGN_MASK (0x00000200u) - #define SCS_CCR_STKALIGN_BIT (9) - #define SCS_CCR_STKALIGN_BITS (1) - /* BFHFNMIGN field */ - #define SCS_CCR_BFHFNMIGN (0x00000100u) - #define SCS_CCR_BFHFNMIGN_MASK (0x00000100u) - #define SCS_CCR_BFHFNMIGN_BIT (8) - #define SCS_CCR_BFHFNMIGN_BITS (1) - /* DIV_0_TRP field */ - #define SCS_CCR_DIV_0_TRP (0x00000010u) - #define SCS_CCR_DIV_0_TRP_MASK (0x00000010u) - #define SCS_CCR_DIV_0_TRP_BIT (4) - #define SCS_CCR_DIV_0_TRP_BITS (1) - /* UNALIGN_TRP field */ - #define SCS_CCR_UNALIGN_TRP (0x00000008u) - #define SCS_CCR_UNALIGN_TRP_MASK (0x00000008u) - #define SCS_CCR_UNALIGN_TRP_BIT (3) - #define SCS_CCR_UNALIGN_TRP_BITS (1) - /* USERSETMPEND field */ - #define SCS_CCR_USERSETMPEND (0x00000002u) - #define SCS_CCR_USERSETMPEND_MASK (0x00000002u) - #define SCS_CCR_USERSETMPEND_BIT (1) - #define SCS_CCR_USERSETMPEND_BITS (1) - /* NONBASETHRDENA field */ - #define SCS_CCR_NONBASETHRDENA (0x00000001u) - #define SCS_CCR_NONBASETHRDENA_MASK (0x00000001u) - #define SCS_CCR_NONBASETHRDENA_BIT (0) - #define SCS_CCR_NONBASETHRDENA_BITS (1) +/* STKALIGN field */ +#define SCS_CCR_STKALIGN (0x00000200u) +#define SCS_CCR_STKALIGN_MASK (0x00000200u) +#define SCS_CCR_STKALIGN_BIT (9) +#define SCS_CCR_STKALIGN_BITS (1) +/* BFHFNMIGN field */ +#define SCS_CCR_BFHFNMIGN (0x00000100u) +#define SCS_CCR_BFHFNMIGN_MASK (0x00000100u) +#define SCS_CCR_BFHFNMIGN_BIT (8) +#define SCS_CCR_BFHFNMIGN_BITS (1) +/* DIV_0_TRP field */ +#define SCS_CCR_DIV_0_TRP (0x00000010u) +#define SCS_CCR_DIV_0_TRP_MASK (0x00000010u) +#define SCS_CCR_DIV_0_TRP_BIT (4) +#define SCS_CCR_DIV_0_TRP_BITS (1) +/* UNALIGN_TRP field */ +#define SCS_CCR_UNALIGN_TRP (0x00000008u) +#define SCS_CCR_UNALIGN_TRP_MASK (0x00000008u) +#define SCS_CCR_UNALIGN_TRP_BIT (3) +#define SCS_CCR_UNALIGN_TRP_BITS (1) +/* USERSETMPEND field */ +#define SCS_CCR_USERSETMPEND (0x00000002u) +#define SCS_CCR_USERSETMPEND_MASK (0x00000002u) +#define SCS_CCR_USERSETMPEND_BIT (1) +#define SCS_CCR_USERSETMPEND_BITS (1) +/* NONBASETHRDENA field */ +#define SCS_CCR_NONBASETHRDENA (0x00000001u) +#define SCS_CCR_NONBASETHRDENA_MASK (0x00000001u) +#define SCS_CCR_NONBASETHRDENA_BIT (0) +#define SCS_CCR_NONBASETHRDENA_BITS (1) #define SCS_SHPR_7to4 *((volatile uint32_t *)0xE000ED18u) #define SCS_SHPR_7to4_REG *((volatile uint32_t *)0xE000ED18u) #define SCS_SHPR_7to4_ADDR (0xE000ED18u) #define SCS_SHPR_7to4_RESET (0x00000000u) - /* PRI_7 field */ - #define SCS_SHPR_7to4_PRI_7 (0xFF000000u) - #define SCS_SHPR_7to4_PRI_7_MASK (0xFF000000u) - #define SCS_SHPR_7to4_PRI_7_BIT (24) - #define SCS_SHPR_7to4_PRI_7_BITS (8) - /* PRI_6 field */ - #define SCS_SHPR_7to4_PRI_6 (0x00FF0000u) - #define SCS_SHPR_7to4_PRI_6_MASK (0x00FF0000u) - #define SCS_SHPR_7to4_PRI_6_BIT (16) - #define SCS_SHPR_7to4_PRI_6_BITS (8) - /* PRI_5 field */ - #define SCS_SHPR_7to4_PRI_5 (0x0000FF00u) - #define SCS_SHPR_7to4_PRI_5_MASK (0x0000FF00u) - #define SCS_SHPR_7to4_PRI_5_BIT (8) - #define SCS_SHPR_7to4_PRI_5_BITS (8) - /* PRI_4 field */ - #define SCS_SHPR_7to4_PRI_4 (0x000000FFu) - #define SCS_SHPR_7to4_PRI_4_MASK (0x000000FFu) - #define SCS_SHPR_7to4_PRI_4_BIT (0) - #define SCS_SHPR_7to4_PRI_4_BITS (8) +/* PRI_7 field */ +#define SCS_SHPR_7to4_PRI_7 (0xFF000000u) +#define SCS_SHPR_7to4_PRI_7_MASK (0xFF000000u) +#define SCS_SHPR_7to4_PRI_7_BIT (24) +#define SCS_SHPR_7to4_PRI_7_BITS (8) +/* PRI_6 field */ +#define SCS_SHPR_7to4_PRI_6 (0x00FF0000u) +#define SCS_SHPR_7to4_PRI_6_MASK (0x00FF0000u) +#define SCS_SHPR_7to4_PRI_6_BIT (16) +#define SCS_SHPR_7to4_PRI_6_BITS (8) +/* PRI_5 field */ +#define SCS_SHPR_7to4_PRI_5 (0x0000FF00u) +#define SCS_SHPR_7to4_PRI_5_MASK (0x0000FF00u) +#define SCS_SHPR_7to4_PRI_5_BIT (8) +#define SCS_SHPR_7to4_PRI_5_BITS (8) +/* PRI_4 field */ +#define SCS_SHPR_7to4_PRI_4 (0x000000FFu) +#define SCS_SHPR_7to4_PRI_4_MASK (0x000000FFu) +#define SCS_SHPR_7to4_PRI_4_BIT (0) +#define SCS_SHPR_7to4_PRI_4_BITS (8) #define SCS_SHPR_11to8 *((volatile uint32_t *)0xE000ED1Cu) #define SCS_SHPR_11to8_REG *((volatile uint32_t *)0xE000ED1Cu) #define SCS_SHPR_11to8_ADDR (0xE000ED1Cu) #define SCS_SHPR_11to8_RESET (0x00000000u) - /* PRI_11 field */ - #define SCS_SHPR_11to8_PRI_11 (0xFF000000u) - #define SCS_SHPR_11to8_PRI_11_MASK (0xFF000000u) - #define SCS_SHPR_11to8_PRI_11_BIT (24) - #define SCS_SHPR_11to8_PRI_11_BITS (8) - /* PRI_10 field */ - #define SCS_SHPR_11to8_PRI_10 (0x00FF0000u) - #define SCS_SHPR_11to8_PRI_10_MASK (0x00FF0000u) - #define SCS_SHPR_11to8_PRI_10_BIT (16) - #define SCS_SHPR_11to8_PRI_10_BITS (8) - /* PRI_9 field */ - #define SCS_SHPR_11to8_PRI_9 (0x0000FF00u) - #define SCS_SHPR_11to8_PRI_9_MASK (0x0000FF00u) - #define SCS_SHPR_11to8_PRI_9_BIT (8) - #define SCS_SHPR_11to8_PRI_9_BITS (8) - /* PRI_8 field */ - #define SCS_SHPR_11to8_PRI_8 (0x000000FFu) - #define SCS_SHPR_11to8_PRI_8_MASK (0x000000FFu) - #define SCS_SHPR_11to8_PRI_8_BIT (0) - #define SCS_SHPR_11to8_PRI_8_BITS (8) +/* PRI_11 field */ +#define SCS_SHPR_11to8_PRI_11 (0xFF000000u) +#define SCS_SHPR_11to8_PRI_11_MASK (0xFF000000u) +#define SCS_SHPR_11to8_PRI_11_BIT (24) +#define SCS_SHPR_11to8_PRI_11_BITS (8) +/* PRI_10 field */ +#define SCS_SHPR_11to8_PRI_10 (0x00FF0000u) +#define SCS_SHPR_11to8_PRI_10_MASK (0x00FF0000u) +#define SCS_SHPR_11to8_PRI_10_BIT (16) +#define SCS_SHPR_11to8_PRI_10_BITS (8) +/* PRI_9 field */ +#define SCS_SHPR_11to8_PRI_9 (0x0000FF00u) +#define SCS_SHPR_11to8_PRI_9_MASK (0x0000FF00u) +#define SCS_SHPR_11to8_PRI_9_BIT (8) +#define SCS_SHPR_11to8_PRI_9_BITS (8) +/* PRI_8 field */ +#define SCS_SHPR_11to8_PRI_8 (0x000000FFu) +#define SCS_SHPR_11to8_PRI_8_MASK (0x000000FFu) +#define SCS_SHPR_11to8_PRI_8_BIT (0) +#define SCS_SHPR_11to8_PRI_8_BITS (8) #define SCS_SHPR_15to12 *((volatile uint32_t *)0xE000ED20u) #define SCS_SHPR_15to12_REG *((volatile uint32_t *)0xE000ED20u) #define SCS_SHPR_15to12_ADDR (0xE000ED20u) #define SCS_SHPR_15to12_RESET (0x00000000u) - /* PRI_15 field */ - #define SCS_SHPR_15to12_PRI_15 (0xFF000000u) - #define SCS_SHPR_15to12_PRI_15_MASK (0xFF000000u) - #define SCS_SHPR_15to12_PRI_15_BIT (24) - #define SCS_SHPR_15to12_PRI_15_BITS (8) - /* PRI_14 field */ - #define SCS_SHPR_15to12_PRI_14 (0x00FF0000u) - #define SCS_SHPR_15to12_PRI_14_MASK (0x00FF0000u) - #define SCS_SHPR_15to12_PRI_14_BIT (16) - #define SCS_SHPR_15to12_PRI_14_BITS (8) - /* PRI_13 field */ - #define SCS_SHPR_15to12_PRI_13 (0x0000FF00u) - #define SCS_SHPR_15to12_PRI_13_MASK (0x0000FF00u) - #define SCS_SHPR_15to12_PRI_13_BIT (8) - #define SCS_SHPR_15to12_PRI_13_BITS (8) - /* PRI_12 field */ - #define SCS_SHPR_15to12_PRI_12 (0x000000FFu) - #define SCS_SHPR_15to12_PRI_12_MASK (0x000000FFu) - #define SCS_SHPR_15to12_PRI_12_BIT (0) - #define SCS_SHPR_15to12_PRI_12_BITS (8) +/* PRI_15 field */ +#define SCS_SHPR_15to12_PRI_15 (0xFF000000u) +#define SCS_SHPR_15to12_PRI_15_MASK (0xFF000000u) +#define SCS_SHPR_15to12_PRI_15_BIT (24) +#define SCS_SHPR_15to12_PRI_15_BITS (8) +/* PRI_14 field */ +#define SCS_SHPR_15to12_PRI_14 (0x00FF0000u) +#define SCS_SHPR_15to12_PRI_14_MASK (0x00FF0000u) +#define SCS_SHPR_15to12_PRI_14_BIT (16) +#define SCS_SHPR_15to12_PRI_14_BITS (8) +/* PRI_13 field */ +#define SCS_SHPR_15to12_PRI_13 (0x0000FF00u) +#define SCS_SHPR_15to12_PRI_13_MASK (0x0000FF00u) +#define SCS_SHPR_15to12_PRI_13_BIT (8) +#define SCS_SHPR_15to12_PRI_13_BITS (8) +/* PRI_12 field */ +#define SCS_SHPR_15to12_PRI_12 (0x000000FFu) +#define SCS_SHPR_15to12_PRI_12_MASK (0x000000FFu) +#define SCS_SHPR_15to12_PRI_12_BIT (0) +#define SCS_SHPR_15to12_PRI_12_BITS (8) #define SCS_SHCSR *((volatile uint32_t *)0xE000ED24u) #define SCS_SHCSR_REG *((volatile uint32_t *)0xE000ED24u) #define SCS_SHCSR_ADDR (0xE000ED24u) #define SCS_SHCSR_RESET (0x00000000u) - /* USGFAULTENA field */ - #define SCS_SHCSR_USGFAULTENA (0x00040000u) - #define SCS_SHCSR_USGFAULTENA_MASK (0x00040000u) - #define SCS_SHCSR_USGFAULTENA_BIT (18) - #define SCS_SHCSR_USGFAULTENA_BITS (1) - /* BUSFAULTENA field */ - #define SCS_SHCSR_BUSFAULTENA (0x00020000u) - #define SCS_SHCSR_BUSFAULTENA_MASK (0x00020000u) - #define SCS_SHCSR_BUSFAULTENA_BIT (17) - #define SCS_SHCSR_BUSFAULTENA_BITS (1) - /* MEMFAULTENA field */ - #define SCS_SHCSR_MEMFAULTENA (0x00010000u) - #define SCS_SHCSR_MEMFAULTENA_MASK (0x00010000u) - #define SCS_SHCSR_MEMFAULTENA_BIT (16) - #define SCS_SHCSR_MEMFAULTENA_BITS (1) - /* SVCALLPENDED field */ - #define SCS_SHCSR_SVCALLPENDED (0x00008000u) - #define SCS_SHCSR_SVCALLPENDED_MASK (0x00008000u) - #define SCS_SHCSR_SVCALLPENDED_BIT (15) - #define SCS_SHCSR_SVCALLPENDED_BITS (1) - /* BUSFAULTPENDED field */ - #define SCS_SHCSR_BUSFAULTPENDED (0x00004000u) - #define SCS_SHCSR_BUSFAULTPENDED_MASK (0x00004000u) - #define SCS_SHCSR_BUSFAULTPENDED_BIT (14) - #define SCS_SHCSR_BUSFAULTPENDED_BITS (1) - /* MEMFAULTPENDED field */ - #define SCS_SHCSR_MEMFAULTPENDED (0x00002000u) - #define SCS_SHCSR_MEMFAULTPENDED_MASK (0x00002000u) - #define SCS_SHCSR_MEMFAULTPENDED_BIT (13) - #define SCS_SHCSR_MEMFAULTPENDED_BITS (1) - /* USGFAULTPENDED field */ - #define SCS_SHCSR_USGFAULTPENDED (0x00001000u) - #define SCS_SHCSR_USGFAULTPENDED_MASK (0x00001000u) - #define SCS_SHCSR_USGFAULTPENDED_BIT (12) - #define SCS_SHCSR_USGFAULTPENDED_BITS (1) - /* SYSTICKACT field */ - #define SCS_SHCSR_SYSTICKACT (0x00000800u) - #define SCS_SHCSR_SYSTICKACT_MASK (0x00000800u) - #define SCS_SHCSR_SYSTICKACT_BIT (11) - #define SCS_SHCSR_SYSTICKACT_BITS (1) - /* PENDSVACT field */ - #define SCS_SHCSR_PENDSVACT (0x00000400u) - #define SCS_SHCSR_PENDSVACT_MASK (0x00000400u) - #define SCS_SHCSR_PENDSVACT_BIT (10) - #define SCS_SHCSR_PENDSVACT_BITS (1) - /* MONITORACT field */ - #define SCS_SHCSR_MONITORACT (0x00000100u) - #define SCS_SHCSR_MONITORACT_MASK (0x00000100u) - #define SCS_SHCSR_MONITORACT_BIT (8) - #define SCS_SHCSR_MONITORACT_BITS (1) - /* SVCALLACT field */ - #define SCS_SHCSR_SVCALLACT (0x00000080u) - #define SCS_SHCSR_SVCALLACT_MASK (0x00000080u) - #define SCS_SHCSR_SVCALLACT_BIT (7) - #define SCS_SHCSR_SVCALLACT_BITS (1) - /* USGFAULTACT field */ - #define SCS_SHCSR_USGFAULTACT (0x00000008u) - #define SCS_SHCSR_USGFAULTACT_MASK (0x00000008u) - #define SCS_SHCSR_USGFAULTACT_BIT (3) - #define SCS_SHCSR_USGFAULTACT_BITS (1) - /* BUSFAULTACT field */ - #define SCS_SHCSR_BUSFAULTACT (0x00000002u) - #define SCS_SHCSR_BUSFAULTACT_MASK (0x00000002u) - #define SCS_SHCSR_BUSFAULTACT_BIT (1) - #define SCS_SHCSR_BUSFAULTACT_BITS (1) - /* MEMFAULTACT field */ - #define SCS_SHCSR_MEMFAULTACT (0x00000001u) - #define SCS_SHCSR_MEMFAULTACT_MASK (0x00000001u) - #define SCS_SHCSR_MEMFAULTACT_BIT (0) - #define SCS_SHCSR_MEMFAULTACT_BITS (1) +/* USGFAULTENA field */ +#define SCS_SHCSR_USGFAULTENA (0x00040000u) +#define SCS_SHCSR_USGFAULTENA_MASK (0x00040000u) +#define SCS_SHCSR_USGFAULTENA_BIT (18) +#define SCS_SHCSR_USGFAULTENA_BITS (1) +/* BUSFAULTENA field */ +#define SCS_SHCSR_BUSFAULTENA (0x00020000u) +#define SCS_SHCSR_BUSFAULTENA_MASK (0x00020000u) +#define SCS_SHCSR_BUSFAULTENA_BIT (17) +#define SCS_SHCSR_BUSFAULTENA_BITS (1) +/* MEMFAULTENA field */ +#define SCS_SHCSR_MEMFAULTENA (0x00010000u) +#define SCS_SHCSR_MEMFAULTENA_MASK (0x00010000u) +#define SCS_SHCSR_MEMFAULTENA_BIT (16) +#define SCS_SHCSR_MEMFAULTENA_BITS (1) +/* SVCALLPENDED field */ +#define SCS_SHCSR_SVCALLPENDED (0x00008000u) +#define SCS_SHCSR_SVCALLPENDED_MASK (0x00008000u) +#define SCS_SHCSR_SVCALLPENDED_BIT (15) +#define SCS_SHCSR_SVCALLPENDED_BITS (1) +/* BUSFAULTPENDED field */ +#define SCS_SHCSR_BUSFAULTPENDED (0x00004000u) +#define SCS_SHCSR_BUSFAULTPENDED_MASK (0x00004000u) +#define SCS_SHCSR_BUSFAULTPENDED_BIT (14) +#define SCS_SHCSR_BUSFAULTPENDED_BITS (1) +/* MEMFAULTPENDED field */ +#define SCS_SHCSR_MEMFAULTPENDED (0x00002000u) +#define SCS_SHCSR_MEMFAULTPENDED_MASK (0x00002000u) +#define SCS_SHCSR_MEMFAULTPENDED_BIT (13) +#define SCS_SHCSR_MEMFAULTPENDED_BITS (1) +/* USGFAULTPENDED field */ +#define SCS_SHCSR_USGFAULTPENDED (0x00001000u) +#define SCS_SHCSR_USGFAULTPENDED_MASK (0x00001000u) +#define SCS_SHCSR_USGFAULTPENDED_BIT (12) +#define SCS_SHCSR_USGFAULTPENDED_BITS (1) +/* SYSTICKACT field */ +#define SCS_SHCSR_SYSTICKACT (0x00000800u) +#define SCS_SHCSR_SYSTICKACT_MASK (0x00000800u) +#define SCS_SHCSR_SYSTICKACT_BIT (11) +#define SCS_SHCSR_SYSTICKACT_BITS (1) +/* PENDSVACT field */ +#define SCS_SHCSR_PENDSVACT (0x00000400u) +#define SCS_SHCSR_PENDSVACT_MASK (0x00000400u) +#define SCS_SHCSR_PENDSVACT_BIT (10) +#define SCS_SHCSR_PENDSVACT_BITS (1) +/* MONITORACT field */ +#define SCS_SHCSR_MONITORACT (0x00000100u) +#define SCS_SHCSR_MONITORACT_MASK (0x00000100u) +#define SCS_SHCSR_MONITORACT_BIT (8) +#define SCS_SHCSR_MONITORACT_BITS (1) +/* SVCALLACT field */ +#define SCS_SHCSR_SVCALLACT (0x00000080u) +#define SCS_SHCSR_SVCALLACT_MASK (0x00000080u) +#define SCS_SHCSR_SVCALLACT_BIT (7) +#define SCS_SHCSR_SVCALLACT_BITS (1) +/* USGFAULTACT field */ +#define SCS_SHCSR_USGFAULTACT (0x00000008u) +#define SCS_SHCSR_USGFAULTACT_MASK (0x00000008u) +#define SCS_SHCSR_USGFAULTACT_BIT (3) +#define SCS_SHCSR_USGFAULTACT_BITS (1) +/* BUSFAULTACT field */ +#define SCS_SHCSR_BUSFAULTACT (0x00000002u) +#define SCS_SHCSR_BUSFAULTACT_MASK (0x00000002u) +#define SCS_SHCSR_BUSFAULTACT_BIT (1) +#define SCS_SHCSR_BUSFAULTACT_BITS (1) +/* MEMFAULTACT field */ +#define SCS_SHCSR_MEMFAULTACT (0x00000001u) +#define SCS_SHCSR_MEMFAULTACT_MASK (0x00000001u) +#define SCS_SHCSR_MEMFAULTACT_BIT (0) +#define SCS_SHCSR_MEMFAULTACT_BITS (1) #define SCS_CFSR *((volatile uint32_t *)0xE000ED28u) #define SCS_CFSR_REG *((volatile uint32_t *)0xE000ED28u) #define SCS_CFSR_ADDR (0xE000ED28u) #define SCS_CFSR_RESET (0x00000000u) - /* DIVBYZERO field */ - #define SCS_CFSR_DIVBYZERO (0x02000000u) - #define SCS_CFSR_DIVBYZERO_MASK (0x02000000u) - #define SCS_CFSR_DIVBYZERO_BIT (25) - #define SCS_CFSR_DIVBYZERO_BITS (1) - /* UNALIGNED field */ - #define SCS_CFSR_UNALIGNED (0x01000000u) - #define SCS_CFSR_UNALIGNED_MASK (0x01000000u) - #define SCS_CFSR_UNALIGNED_BIT (24) - #define SCS_CFSR_UNALIGNED_BITS (1) - /* NOCP field */ - #define SCS_CFSR_NOCP (0x00080000u) - #define SCS_CFSR_NOCP_MASK (0x00080000u) - #define SCS_CFSR_NOCP_BIT (19) - #define SCS_CFSR_NOCP_BITS (1) - /* INVPC field */ - #define SCS_CFSR_INVPC (0x00040000u) - #define SCS_CFSR_INVPC_MASK (0x00040000u) - #define SCS_CFSR_INVPC_BIT (18) - #define SCS_CFSR_INVPC_BITS (1) - /* INVSTATE field */ - #define SCS_CFSR_INVSTATE (0x00020000u) - #define SCS_CFSR_INVSTATE_MASK (0x00020000u) - #define SCS_CFSR_INVSTATE_BIT (17) - #define SCS_CFSR_INVSTATE_BITS (1) - /* UNDEFINSTR field */ - #define SCS_CFSR_UNDEFINSTR (0x00010000u) - #define SCS_CFSR_UNDEFINSTR_MASK (0x00010000u) - #define SCS_CFSR_UNDEFINSTR_BIT (16) - #define SCS_CFSR_UNDEFINSTR_BITS (1) - /* BFARVALID field */ - #define SCS_CFSR_BFARVALID (0x00008000u) - #define SCS_CFSR_BFARVALID_MASK (0x00008000u) - #define SCS_CFSR_BFARVALID_BIT (15) - #define SCS_CFSR_BFARVALID_BITS (1) - /* STKERR field */ - #define SCS_CFSR_STKERR (0x00001000u) - #define SCS_CFSR_STKERR_MASK (0x00001000u) - #define SCS_CFSR_STKERR_BIT (12) - #define SCS_CFSR_STKERR_BITS (1) - /* UNSTKERR field */ - #define SCS_CFSR_UNSTKERR (0x00000800u) - #define SCS_CFSR_UNSTKERR_MASK (0x00000800u) - #define SCS_CFSR_UNSTKERR_BIT (11) - #define SCS_CFSR_UNSTKERR_BITS (1) - /* IMPRECISERR field */ - #define SCS_CFSR_IMPRECISERR (0x00000400u) - #define SCS_CFSR_IMPRECISERR_MASK (0x00000400u) - #define SCS_CFSR_IMPRECISERR_BIT (10) - #define SCS_CFSR_IMPRECISERR_BITS (1) - /* PRECISERR field */ - #define SCS_CFSR_PRECISERR (0x00000200u) - #define SCS_CFSR_PRECISERR_MASK (0x00000200u) - #define SCS_CFSR_PRECISERR_BIT (9) - #define SCS_CFSR_PRECISERR_BITS (1) - /* IBUSERR field */ - #define SCS_CFSR_IBUSERR (0x00000100u) - #define SCS_CFSR_IBUSERR_MASK (0x00000100u) - #define SCS_CFSR_IBUSERR_BIT (8) - #define SCS_CFSR_IBUSERR_BITS (1) - /* MMARVALID field */ - #define SCS_CFSR_MMARVALID (0x00000080u) - #define SCS_CFSR_MMARVALID_MASK (0x00000080u) - #define SCS_CFSR_MMARVALID_BIT (7) - #define SCS_CFSR_MMARVALID_BITS (1) - /* MSTKERR field */ - #define SCS_CFSR_MSTKERR (0x00000010u) - #define SCS_CFSR_MSTKERR_MASK (0x00000010u) - #define SCS_CFSR_MSTKERR_BIT (4) - #define SCS_CFSR_MSTKERR_BITS (1) - /* MUNSTKERR field */ - #define SCS_CFSR_MUNSTKERR (0x00000008u) - #define SCS_CFSR_MUNSTKERR_MASK (0x00000008u) - #define SCS_CFSR_MUNSTKERR_BIT (3) - #define SCS_CFSR_MUNSTKERR_BITS (1) - /* DACCVIOL field */ - #define SCS_CFSR_DACCVIOL (0x00000002u) - #define SCS_CFSR_DACCVIOL_MASK (0x00000002u) - #define SCS_CFSR_DACCVIOL_BIT (1) - #define SCS_CFSR_DACCVIOL_BITS (1) - /* IACCVIOL field */ - #define SCS_CFSR_IACCVIOL (0x00000001u) - #define SCS_CFSR_IACCVIOL_MASK (0x00000001u) - #define SCS_CFSR_IACCVIOL_BIT (0) - #define SCS_CFSR_IACCVIOL_BITS (1) +/* DIVBYZERO field */ +#define SCS_CFSR_DIVBYZERO (0x02000000u) +#define SCS_CFSR_DIVBYZERO_MASK (0x02000000u) +#define SCS_CFSR_DIVBYZERO_BIT (25) +#define SCS_CFSR_DIVBYZERO_BITS (1) +/* UNALIGNED field */ +#define SCS_CFSR_UNALIGNED (0x01000000u) +#define SCS_CFSR_UNALIGNED_MASK (0x01000000u) +#define SCS_CFSR_UNALIGNED_BIT (24) +#define SCS_CFSR_UNALIGNED_BITS (1) +/* NOCP field */ +#define SCS_CFSR_NOCP (0x00080000u) +#define SCS_CFSR_NOCP_MASK (0x00080000u) +#define SCS_CFSR_NOCP_BIT (19) +#define SCS_CFSR_NOCP_BITS (1) +/* INVPC field */ +#define SCS_CFSR_INVPC (0x00040000u) +#define SCS_CFSR_INVPC_MASK (0x00040000u) +#define SCS_CFSR_INVPC_BIT (18) +#define SCS_CFSR_INVPC_BITS (1) +/* INVSTATE field */ +#define SCS_CFSR_INVSTATE (0x00020000u) +#define SCS_CFSR_INVSTATE_MASK (0x00020000u) +#define SCS_CFSR_INVSTATE_BIT (17) +#define SCS_CFSR_INVSTATE_BITS (1) +/* UNDEFINSTR field */ +#define SCS_CFSR_UNDEFINSTR (0x00010000u) +#define SCS_CFSR_UNDEFINSTR_MASK (0x00010000u) +#define SCS_CFSR_UNDEFINSTR_BIT (16) +#define SCS_CFSR_UNDEFINSTR_BITS (1) +/* BFARVALID field */ +#define SCS_CFSR_BFARVALID (0x00008000u) +#define SCS_CFSR_BFARVALID_MASK (0x00008000u) +#define SCS_CFSR_BFARVALID_BIT (15) +#define SCS_CFSR_BFARVALID_BITS (1) +/* STKERR field */ +#define SCS_CFSR_STKERR (0x00001000u) +#define SCS_CFSR_STKERR_MASK (0x00001000u) +#define SCS_CFSR_STKERR_BIT (12) +#define SCS_CFSR_STKERR_BITS (1) +/* UNSTKERR field */ +#define SCS_CFSR_UNSTKERR (0x00000800u) +#define SCS_CFSR_UNSTKERR_MASK (0x00000800u) +#define SCS_CFSR_UNSTKERR_BIT (11) +#define SCS_CFSR_UNSTKERR_BITS (1) +/* IMPRECISERR field */ +#define SCS_CFSR_IMPRECISERR (0x00000400u) +#define SCS_CFSR_IMPRECISERR_MASK (0x00000400u) +#define SCS_CFSR_IMPRECISERR_BIT (10) +#define SCS_CFSR_IMPRECISERR_BITS (1) +/* PRECISERR field */ +#define SCS_CFSR_PRECISERR (0x00000200u) +#define SCS_CFSR_PRECISERR_MASK (0x00000200u) +#define SCS_CFSR_PRECISERR_BIT (9) +#define SCS_CFSR_PRECISERR_BITS (1) +/* IBUSERR field */ +#define SCS_CFSR_IBUSERR (0x00000100u) +#define SCS_CFSR_IBUSERR_MASK (0x00000100u) +#define SCS_CFSR_IBUSERR_BIT (8) +#define SCS_CFSR_IBUSERR_BITS (1) +/* MMARVALID field */ +#define SCS_CFSR_MMARVALID (0x00000080u) +#define SCS_CFSR_MMARVALID_MASK (0x00000080u) +#define SCS_CFSR_MMARVALID_BIT (7) +#define SCS_CFSR_MMARVALID_BITS (1) +/* MSTKERR field */ +#define SCS_CFSR_MSTKERR (0x00000010u) +#define SCS_CFSR_MSTKERR_MASK (0x00000010u) +#define SCS_CFSR_MSTKERR_BIT (4) +#define SCS_CFSR_MSTKERR_BITS (1) +/* MUNSTKERR field */ +#define SCS_CFSR_MUNSTKERR (0x00000008u) +#define SCS_CFSR_MUNSTKERR_MASK (0x00000008u) +#define SCS_CFSR_MUNSTKERR_BIT (3) +#define SCS_CFSR_MUNSTKERR_BITS (1) +/* DACCVIOL field */ +#define SCS_CFSR_DACCVIOL (0x00000002u) +#define SCS_CFSR_DACCVIOL_MASK (0x00000002u) +#define SCS_CFSR_DACCVIOL_BIT (1) +#define SCS_CFSR_DACCVIOL_BITS (1) +/* IACCVIOL field */ +#define SCS_CFSR_IACCVIOL (0x00000001u) +#define SCS_CFSR_IACCVIOL_MASK (0x00000001u) +#define SCS_CFSR_IACCVIOL_BIT (0) +#define SCS_CFSR_IACCVIOL_BITS (1) #define SCS_HFSR *((volatile uint32_t *)0xE000ED2Cu) #define SCS_HFSR_REG *((volatile uint32_t *)0xE000ED2Cu) #define SCS_HFSR_ADDR (0xE000ED2Cu) #define SCS_HFSR_RESET (0x00000000u) - /* DEBUGEVT field */ - #define SCS_HFSR_DEBUGEVT (0x80000000u) - #define SCS_HFSR_DEBUGEVT_MASK (0x80000000u) - #define SCS_HFSR_DEBUGEVT_BIT (31) - #define SCS_HFSR_DEBUGEVT_BITS (1) - /* FORCED field */ - #define SCS_HFSR_FORCED (0x40000000u) - #define SCS_HFSR_FORCED_MASK (0x40000000u) - #define SCS_HFSR_FORCED_BIT (30) - #define SCS_HFSR_FORCED_BITS (1) - /* VECTTBL field */ - #define SCS_HFSR_VECTTBL (0x00000002u) - #define SCS_HFSR_VECTTBL_MASK (0x00000002u) - #define SCS_HFSR_VECTTBL_BIT (1) - #define SCS_HFSR_VECTTBL_BITS (1) +/* DEBUGEVT field */ +#define SCS_HFSR_DEBUGEVT (0x80000000u) +#define SCS_HFSR_DEBUGEVT_MASK (0x80000000u) +#define SCS_HFSR_DEBUGEVT_BIT (31) +#define SCS_HFSR_DEBUGEVT_BITS (1) +/* FORCED field */ +#define SCS_HFSR_FORCED (0x40000000u) +#define SCS_HFSR_FORCED_MASK (0x40000000u) +#define SCS_HFSR_FORCED_BIT (30) +#define SCS_HFSR_FORCED_BITS (1) +/* VECTTBL field */ +#define SCS_HFSR_VECTTBL (0x00000002u) +#define SCS_HFSR_VECTTBL_MASK (0x00000002u) +#define SCS_HFSR_VECTTBL_BIT (1) +#define SCS_HFSR_VECTTBL_BITS (1) #define SCS_DFSR *((volatile uint32_t *)0xE000ED30u) #define SCS_DFSR_REG *((volatile uint32_t *)0xE000ED30u) #define SCS_DFSR_ADDR (0xE000ED30u) #define SCS_DFSR_RESET (0x00000000u) - /* EXTERNAL field */ - #define SCS_DFSR_EXTERNAL (0x00000010u) - #define SCS_DFSR_EXTERNAL_MASK (0x00000010u) - #define SCS_DFSR_EXTERNAL_BIT (4) - #define SCS_DFSR_EXTERNAL_BITS (1) - /* VCATCH field */ - #define SCS_DFSR_VCATCH (0x00000008u) - #define SCS_DFSR_VCATCH_MASK (0x00000008u) - #define SCS_DFSR_VCATCH_BIT (3) - #define SCS_DFSR_VCATCH_BITS (1) - /* DWTTRAP field */ - #define SCS_DFSR_DWTTRAP (0x00000004u) - #define SCS_DFSR_DWTTRAP_MASK (0x00000004u) - #define SCS_DFSR_DWTTRAP_BIT (2) - #define SCS_DFSR_DWTTRAP_BITS (1) - /* BKPT field */ - #define SCS_DFSR_BKPT (0x00000002u) - #define SCS_DFSR_BKPT_MASK (0x00000002u) - #define SCS_DFSR_BKPT_BIT (1) - #define SCS_DFSR_BKPT_BITS (1) - /* HALTED field */ - #define SCS_DFSR_HALTED (0x00000001u) - #define SCS_DFSR_HALTED_MASK (0x00000001u) - #define SCS_DFSR_HALTED_BIT (0) - #define SCS_DFSR_HALTED_BITS (1) +/* EXTERNAL field */ +#define SCS_DFSR_EXTERNAL (0x00000010u) +#define SCS_DFSR_EXTERNAL_MASK (0x00000010u) +#define SCS_DFSR_EXTERNAL_BIT (4) +#define SCS_DFSR_EXTERNAL_BITS (1) +/* VCATCH field */ +#define SCS_DFSR_VCATCH (0x00000008u) +#define SCS_DFSR_VCATCH_MASK (0x00000008u) +#define SCS_DFSR_VCATCH_BIT (3) +#define SCS_DFSR_VCATCH_BITS (1) +/* DWTTRAP field */ +#define SCS_DFSR_DWTTRAP (0x00000004u) +#define SCS_DFSR_DWTTRAP_MASK (0x00000004u) +#define SCS_DFSR_DWTTRAP_BIT (2) +#define SCS_DFSR_DWTTRAP_BITS (1) +/* BKPT field */ +#define SCS_DFSR_BKPT (0x00000002u) +#define SCS_DFSR_BKPT_MASK (0x00000002u) +#define SCS_DFSR_BKPT_BIT (1) +#define SCS_DFSR_BKPT_BITS (1) +/* HALTED field */ +#define SCS_DFSR_HALTED (0x00000001u) +#define SCS_DFSR_HALTED_MASK (0x00000001u) +#define SCS_DFSR_HALTED_BIT (0) +#define SCS_DFSR_HALTED_BITS (1) #define SCS_MMAR *((volatile uint32_t *)0xE000ED34u) #define SCS_MMAR_REG *((volatile uint32_t *)0xE000ED34u) #define SCS_MMAR_ADDR (0xE000ED34u) #define SCS_MMAR_RESET (0x00000000u) - /* ADDRESS field */ - #define SCS_MMAR_ADDRESS (0xFFFFFFFFu) - #define SCS_MMAR_ADDRESS_MASK (0xFFFFFFFFu) - #define SCS_MMAR_ADDRESS_BIT (0) - #define SCS_MMAR_ADDRESS_BITS (32) +/* ADDRESS field */ +#define SCS_MMAR_ADDRESS (0xFFFFFFFFu) +#define SCS_MMAR_ADDRESS_MASK (0xFFFFFFFFu) +#define SCS_MMAR_ADDRESS_BIT (0) +#define SCS_MMAR_ADDRESS_BITS (32) #define SCS_BFAR *((volatile uint32_t *)0xE000ED38u) #define SCS_BFAR_REG *((volatile uint32_t *)0xE000ED38u) #define SCS_BFAR_ADDR (0xE000ED38u) #define SCS_BFAR_RESET (0x00000000u) - /* ADDRESS field */ - #define SCS_BFAR_ADDRESS (0xFFFFFFFFu) - #define SCS_BFAR_ADDRESS_MASK (0xFFFFFFFFu) - #define SCS_BFAR_ADDRESS_BIT (0) - #define SCS_BFAR_ADDRESS_BITS (32) +/* ADDRESS field */ +#define SCS_BFAR_ADDRESS (0xFFFFFFFFu) +#define SCS_BFAR_ADDRESS_MASK (0xFFFFFFFFu) +#define SCS_BFAR_ADDRESS_BIT (0) +#define SCS_BFAR_ADDRESS_BITS (32) #define SCS_AFSR *((volatile uint32_t *)0xE000ED3Cu) #define SCS_AFSR_REG *((volatile uint32_t *)0xE000ED3Cu) #define SCS_AFSR_ADDR (0xE000ED3Cu) #define SCS_AFSR_RESET (0x00000000u) - /* WRONGSIZE field */ - #define SCS_AFSR_WRONGSIZE (0x00000008u) - #define SCS_AFSR_WRONGSIZE_MASK (0x00000008u) - #define SCS_AFSR_WRONGSIZE_BIT (3) - #define SCS_AFSR_WRONGSIZE_BITS (1) - /* PROTECTED field */ - #define SCS_AFSR_PROTECTED (0x00000004u) - #define SCS_AFSR_PROTECTED_MASK (0x00000004u) - #define SCS_AFSR_PROTECTED_BIT (2) - #define SCS_AFSR_PROTECTED_BITS (1) - /* RESERVED field */ - #define SCS_AFSR_RESERVED (0x00000002u) - #define SCS_AFSR_RESERVED_MASK (0x00000002u) - #define SCS_AFSR_RESERVED_BIT (1) - #define SCS_AFSR_RESERVED_BITS (1) - /* MISSED field */ - #define SCS_AFSR_MISSED (0x00000001u) - #define SCS_AFSR_MISSED_MASK (0x00000001u) - #define SCS_AFSR_MISSED_BIT (0) - #define SCS_AFSR_MISSED_BITS (1) +/* WRONGSIZE field */ +#define SCS_AFSR_WRONGSIZE (0x00000008u) +#define SCS_AFSR_WRONGSIZE_MASK (0x00000008u) +#define SCS_AFSR_WRONGSIZE_BIT (3) +#define SCS_AFSR_WRONGSIZE_BITS (1) +/* PROTECTED field */ +#define SCS_AFSR_PROTECTED (0x00000004u) +#define SCS_AFSR_PROTECTED_MASK (0x00000004u) +#define SCS_AFSR_PROTECTED_BIT (2) +#define SCS_AFSR_PROTECTED_BITS (1) +/* RESERVED field */ +#define SCS_AFSR_RESERVED (0x00000002u) +#define SCS_AFSR_RESERVED_MASK (0x00000002u) +#define SCS_AFSR_RESERVED_BIT (1) +#define SCS_AFSR_RESERVED_BITS (1) +/* MISSED field */ +#define SCS_AFSR_MISSED (0x00000001u) +#define SCS_AFSR_MISSED_MASK (0x00000001u) +#define SCS_AFSR_MISSED_BIT (0) +#define SCS_AFSR_MISSED_BITS (1) #define SCS_PFR0 *((volatile uint32_t *)0xE000ED40u) #define SCS_PFR0_REG *((volatile uint32_t *)0xE000ED40u) #define SCS_PFR0_ADDR (0xE000ED40u) #define SCS_PFR0_RESET (0x00000030u) - /* FEATURE field */ - #define SCS_PFR0_FEATURE (0xFFFFFFFFu) - #define SCS_PFR0_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_PFR0_FEATURE_BIT (0) - #define SCS_PFR0_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_PFR0_FEATURE (0xFFFFFFFFu) +#define SCS_PFR0_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_PFR0_FEATURE_BIT (0) +#define SCS_PFR0_FEATURE_BITS (32) #define SCS_PFR1 *((volatile uint32_t *)0xE000ED44u) #define SCS_PFR1_REG *((volatile uint32_t *)0xE000ED44u) #define SCS_PFR1_ADDR (0xE000ED44u) #define SCS_PFR1_RESET (0x00000200u) - /* FEATURE field */ - #define SCS_PFR1_FEATURE (0xFFFFFFFFu) - #define SCS_PFR1_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_PFR1_FEATURE_BIT (0) - #define SCS_PFR1_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_PFR1_FEATURE (0xFFFFFFFFu) +#define SCS_PFR1_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_PFR1_FEATURE_BIT (0) +#define SCS_PFR1_FEATURE_BITS (32) #define SCS_DFR0 *((volatile uint32_t *)0xE000ED48u) #define SCS_DFR0_REG *((volatile uint32_t *)0xE000ED48u) #define SCS_DFR0_ADDR (0xE000ED48u) #define SCS_DFR0_RESET (0x00100000u) - /* FEATURE field */ - #define SCS_DFR0_FEATURE (0xFFFFFFFFu) - #define SCS_DFR0_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_DFR0_FEATURE_BIT (0) - #define SCS_DFR0_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_DFR0_FEATURE (0xFFFFFFFFu) +#define SCS_DFR0_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_DFR0_FEATURE_BIT (0) +#define SCS_DFR0_FEATURE_BITS (32) #define SCS_AFR0 *((volatile uint32_t *)0xE000ED4Cu) #define SCS_AFR0_REG *((volatile uint32_t *)0xE000ED4Cu) #define SCS_AFR0_ADDR (0xE000ED4Cu) #define SCS_AFR0_RESET (0x00000000u) - /* FEATURE field */ - #define SCS_AFR0_FEATURE (0xFFFFFFFFu) - #define SCS_AFR0_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_AFR0_FEATURE_BIT (0) - #define SCS_AFR0_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_AFR0_FEATURE (0xFFFFFFFFu) +#define SCS_AFR0_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_AFR0_FEATURE_BIT (0) +#define SCS_AFR0_FEATURE_BITS (32) #define SCS_MMFR0 *((volatile uint32_t *)0xE000ED50u) #define SCS_MMFR0_REG *((volatile uint32_t *)0xE000ED50u) #define SCS_MMFR0_ADDR (0xE000ED50u) #define SCS_MMFR0_RESET (0x00000030u) - /* FEATURE field */ - #define SCS_MMFR0_FEATURE (0xFFFFFFFFu) - #define SCS_MMFR0_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_MMFR0_FEATURE_BIT (0) - #define SCS_MMFR0_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_MMFR0_FEATURE (0xFFFFFFFFu) +#define SCS_MMFR0_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_MMFR0_FEATURE_BIT (0) +#define SCS_MMFR0_FEATURE_BITS (32) #define SCS_MMFR1 *((volatile uint32_t *)0xE000ED54u) #define SCS_MMFR1_REG *((volatile uint32_t *)0xE000ED54u) #define SCS_MMFR1_ADDR (0xE000ED54u) #define SCS_MMFR1_RESET (0x00000000u) - /* FEATURE field */ - #define SCS_MMFR1_FEATURE (0xFFFFFFFFu) - #define SCS_MMFR1_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_MMFR1_FEATURE_BIT (0) - #define SCS_MMFR1_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_MMFR1_FEATURE (0xFFFFFFFFu) +#define SCS_MMFR1_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_MMFR1_FEATURE_BIT (0) +#define SCS_MMFR1_FEATURE_BITS (32) #define SCS_MMFR2 *((volatile uint32_t *)0xE000ED58u) #define SCS_MMFR2_REG *((volatile uint32_t *)0xE000ED58u) #define SCS_MMFR2_ADDR (0xE000ED58u) #define SCS_MMFR2_RESET (0x00000000u) - /* FEATURE field */ - #define SCS_MMFR2_FEATURE (0xFFFFFFFFu) - #define SCS_MMFR2_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_MMFR2_FEATURE_BIT (0) - #define SCS_MMFR2_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_MMFR2_FEATURE (0xFFFFFFFFu) +#define SCS_MMFR2_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_MMFR2_FEATURE_BIT (0) +#define SCS_MMFR2_FEATURE_BITS (32) #define SCS_MMFR3 *((volatile uint32_t *)0xE000ED5Cu) #define SCS_MMFR3_REG *((volatile uint32_t *)0xE000ED5Cu) #define SCS_MMFR3_ADDR (0xE000ED5Cu) #define SCS_MMFR3_RESET (0x00000000u) - /* FEATURE field */ - #define SCS_MMFR3_FEATURE (0xFFFFFFFFu) - #define SCS_MMFR3_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_MMFR3_FEATURE_BIT (0) - #define SCS_MMFR3_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_MMFR3_FEATURE (0xFFFFFFFFu) +#define SCS_MMFR3_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_MMFR3_FEATURE_BIT (0) +#define SCS_MMFR3_FEATURE_BITS (32) #define SCS_ISAFR0 *((volatile uint32_t *)0xE000ED60u) #define SCS_ISAFR0_REG *((volatile uint32_t *)0xE000ED60u) #define SCS_ISAFR0_ADDR (0xE000ED60u) #define SCS_ISAFR0_RESET (0x01141110u) - /* FEATURE field */ - #define SCS_ISAFR0_FEATURE (0xFFFFFFFFu) - #define SCS_ISAFR0_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_ISAFR0_FEATURE_BIT (0) - #define SCS_ISAFR0_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_ISAFR0_FEATURE (0xFFFFFFFFu) +#define SCS_ISAFR0_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_ISAFR0_FEATURE_BIT (0) +#define SCS_ISAFR0_FEATURE_BITS (32) #define SCS_ISAFR1 *((volatile uint32_t *)0xE000ED64u) #define SCS_ISAFR1_REG *((volatile uint32_t *)0xE000ED64u) #define SCS_ISAFR1_ADDR (0xE000ED64u) #define SCS_ISAFR1_RESET (0x02111000u) - /* FEATURE field */ - #define SCS_ISAFR1_FEATURE (0xFFFFFFFFu) - #define SCS_ISAFR1_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_ISAFR1_FEATURE_BIT (0) - #define SCS_ISAFR1_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_ISAFR1_FEATURE (0xFFFFFFFFu) +#define SCS_ISAFR1_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_ISAFR1_FEATURE_BIT (0) +#define SCS_ISAFR1_FEATURE_BITS (32) #define SCS_ISAFR2 *((volatile uint32_t *)0xE000ED68u) #define SCS_ISAFR2_REG *((volatile uint32_t *)0xE000ED68u) #define SCS_ISAFR2_ADDR (0xE000ED68u) #define SCS_ISAFR2_RESET (0x21112231u) - /* FEATURE field */ - #define SCS_ISAFR2_FEATURE (0xFFFFFFFFu) - #define SCS_ISAFR2_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_ISAFR2_FEATURE_BIT (0) - #define SCS_ISAFR2_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_ISAFR2_FEATURE (0xFFFFFFFFu) +#define SCS_ISAFR2_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_ISAFR2_FEATURE_BIT (0) +#define SCS_ISAFR2_FEATURE_BITS (32) #define SCS_ISAFR3 *((volatile uint32_t *)0xE000ED6Cu) #define SCS_ISAFR3_REG *((volatile uint32_t *)0xE000ED6Cu) #define SCS_ISAFR3_ADDR (0xE000ED6Cu) #define SCS_ISAFR3_RESET (0x11111110u) - /* FEATURE field */ - #define SCS_ISAFR3_FEATURE (0xFFFFFFFFu) - #define SCS_ISAFR3_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_ISAFR3_FEATURE_BIT (0) - #define SCS_ISAFR3_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_ISAFR3_FEATURE (0xFFFFFFFFu) +#define SCS_ISAFR3_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_ISAFR3_FEATURE_BIT (0) +#define SCS_ISAFR3_FEATURE_BITS (32) #define SCS_ISAFR4 *((volatile uint32_t *)0xE000ED70u) #define SCS_ISAFR4_REG *((volatile uint32_t *)0xE000ED70u) #define SCS_ISAFR4_ADDR (0xE000ED70u) #define SCS_ISAFR4_RESET (0x01310102u) - /* FEATURE field */ - #define SCS_ISAFR4_FEATURE (0xFFFFFFFFu) - #define SCS_ISAFR4_FEATURE_MASK (0xFFFFFFFFu) - #define SCS_ISAFR4_FEATURE_BIT (0) - #define SCS_ISAFR4_FEATURE_BITS (32) +/* FEATURE field */ +#define SCS_ISAFR4_FEATURE (0xFFFFFFFFu) +#define SCS_ISAFR4_FEATURE_MASK (0xFFFFFFFFu) +#define SCS_ISAFR4_FEATURE_BIT (0) +#define SCS_ISAFR4_FEATURE_BITS (32) #define MPU_TYPE *((volatile uint32_t *)0xE000ED90u) #define MPU_TYPE_REG *((volatile uint32_t *)0xE000ED90u) #define MPU_TYPE_ADDR (0xE000ED90u) #define MPU_TYPE_RESET (0x00000800u) - /* IREGION field */ - #define MPU_TYPE_IREGION (0x00FF0000u) - #define MPU_TYPE_IREGION_MASK (0x00FF0000u) - #define MPU_TYPE_IREGION_BIT (16) - #define MPU_TYPE_IREGION_BITS (8) - /* DREGION field */ - #define MPU_TYPE_DREGION (0x0000FF00u) - #define MPU_TYPE_DREGION_MASK (0x0000FF00u) - #define MPU_TYPE_DREGION_BIT (8) - #define MPU_TYPE_DREGION_BITS (8) +/* IREGION field */ +#define MPU_TYPE_IREGION (0x00FF0000u) +#define MPU_TYPE_IREGION_MASK (0x00FF0000u) +#define MPU_TYPE_IREGION_BIT (16) +#define MPU_TYPE_IREGION_BITS (8) +/* DREGION field */ +#define MPU_TYPE_DREGION (0x0000FF00u) +#define MPU_TYPE_DREGION_MASK (0x0000FF00u) +#define MPU_TYPE_DREGION_BIT (8) +#define MPU_TYPE_DREGION_BITS (8) #define MPU_CTRL *((volatile uint32_t *)0xE000ED94u) #define MPU_CTRL_REG *((volatile uint32_t *)0xE000ED94u) #define MPU_CTRL_ADDR (0xE000ED94u) #define MPU_CTRL_RESET (0x00000000u) - /* PRIVDEFENA field */ - #define MPU_CTRL_PRIVDEFENA (0x00000004u) - #define MPU_CTRL_PRIVDEFENA_MASK (0x00000004u) - #define MPU_CTRL_PRIVDEFENA_BIT (2) - #define MPU_CTRL_PRIVDEFENA_BITS (1) - /* HFNMIENA field */ - #define MPU_CTRL_HFNMIENA (0x00000002u) - #define MPU_CTRL_HFNMIENA_MASK (0x00000002u) - #define MPU_CTRL_HFNMIENA_BIT (1) - #define MPU_CTRL_HFNMIENA_BITS (1) - /* ENABLE field */ - #define MPU_CTRL_ENABLE (0x00000001u) - #define MPU_CTRL_ENABLE_MASK (0x00000001u) - #define MPU_CTRL_ENABLE_BIT (0) - #define MPU_CTRL_ENABLE_BITS (1) +/* PRIVDEFENA field */ +#define MPU_CTRL_PRIVDEFENA (0x00000004u) +#define MPU_CTRL_PRIVDEFENA_MASK (0x00000004u) +#define MPU_CTRL_PRIVDEFENA_BIT (2) +#define MPU_CTRL_PRIVDEFENA_BITS (1) +/* HFNMIENA field */ +#define MPU_CTRL_HFNMIENA (0x00000002u) +#define MPU_CTRL_HFNMIENA_MASK (0x00000002u) +#define MPU_CTRL_HFNMIENA_BIT (1) +#define MPU_CTRL_HFNMIENA_BITS (1) +/* ENABLE field */ +#define MPU_CTRL_ENABLE (0x00000001u) +#define MPU_CTRL_ENABLE_MASK (0x00000001u) +#define MPU_CTRL_ENABLE_BIT (0) +#define MPU_CTRL_ENABLE_BITS (1) #define MPU_REGION *((volatile uint32_t *)0xE000ED98u) #define MPU_REGION_REG *((volatile uint32_t *)0xE000ED98u) #define MPU_REGION_ADDR (0xE000ED98u) #define MPU_REGION_RESET (0x00000000u) - /* REGION field */ - #define MPU_REGION_REGION (0x000000FFu) - #define MPU_REGION_REGION_MASK (0x000000FFu) - #define MPU_REGION_REGION_BIT (0) - #define MPU_REGION_REGION_BITS (8) +/* REGION field */ +#define MPU_REGION_REGION (0x000000FFu) +#define MPU_REGION_REGION_MASK (0x000000FFu) +#define MPU_REGION_REGION_BIT (0) +#define MPU_REGION_REGION_BITS (8) #define MPU_BASE *((volatile uint32_t *)0xE000ED9Cu) #define MPU_BASE_REG *((volatile uint32_t *)0xE000ED9Cu) #define MPU_BASE_ADDR (0xE000ED9Cu) #define MPU_BASE_RESET (0x00000000u) - /* ADDRESS field */ - #define MPU_BASE_ADDRESS (0xFFFFFFE0u) - #define MPU_BASE_ADDRESS_MASK (0xFFFFFFE0u) - #define MPU_BASE_ADDRESS_BIT (5) - #define MPU_BASE_ADDRESS_BITS (27) - /* VALID field */ - #define MPU_BASE_VALID (0x00000010u) - #define MPU_BASE_VALID_MASK (0x00000010u) - #define MPU_BASE_VALID_BIT (4) - #define MPU_BASE_VALID_BITS (1) - /* REGION field */ - #define MPU_BASE_REGION (0x0000000Fu) - #define MPU_BASE_REGION_MASK (0x0000000Fu) - #define MPU_BASE_REGION_BIT (0) - #define MPU_BASE_REGION_BITS (4) +/* ADDRESS field */ +#define MPU_BASE_ADDRESS (0xFFFFFFE0u) +#define MPU_BASE_ADDRESS_MASK (0xFFFFFFE0u) +#define MPU_BASE_ADDRESS_BIT (5) +#define MPU_BASE_ADDRESS_BITS (27) +/* VALID field */ +#define MPU_BASE_VALID (0x00000010u) +#define MPU_BASE_VALID_MASK (0x00000010u) +#define MPU_BASE_VALID_BIT (4) +#define MPU_BASE_VALID_BITS (1) +/* REGION field */ +#define MPU_BASE_REGION (0x0000000Fu) +#define MPU_BASE_REGION_MASK (0x0000000Fu) +#define MPU_BASE_REGION_BIT (0) +#define MPU_BASE_REGION_BITS (4) #define MPU_ATTR *((volatile uint32_t *)0xE000EDA0u) #define MPU_ATTR_REG *((volatile uint32_t *)0xE000EDA0u) #define MPU_ATTR_ADDR (0xE000EDA0u) #define MPU_ATTR_RESET (0x00000000u) - /* XN field */ - #define MPU_ATTR_XN (0x10000000u) - #define MPU_ATTR_XN_MASK (0x10000000u) - #define MPU_ATTR_XN_BIT (28) - #define MPU_ATTR_XN_BITS (1) - /* AP field */ - #define MPU_ATTR_AP (0x07000000u) - #define MPU_ATTR_AP_MASK (0x07000000u) - #define MPU_ATTR_AP_BIT (24) - #define MPU_ATTR_AP_BITS (3) - /* TEX field */ - #define MPU_ATTR_TEX (0x00380000u) - #define MPU_ATTR_TEX_MASK (0x00380000u) - #define MPU_ATTR_TEX_BIT (19) - #define MPU_ATTR_TEX_BITS (3) - /* S field */ - #define MPU_ATTR_S (0x00040000u) - #define MPU_ATTR_S_MASK (0x00040000u) - #define MPU_ATTR_S_BIT (18) - #define MPU_ATTR_S_BITS (1) - /* C field */ - #define MPU_ATTR_C (0x00020000u) - #define MPU_ATTR_C_MASK (0x00020000u) - #define MPU_ATTR_C_BIT (17) - #define MPU_ATTR_C_BITS (1) - /* B field */ - #define MPU_ATTR_B (0x00010000u) - #define MPU_ATTR_B_MASK (0x00010000u) - #define MPU_ATTR_B_BIT (16) - #define MPU_ATTR_B_BITS (1) - /* SRD field */ - #define MPU_ATTR_SRD (0x0000FF00u) - #define MPU_ATTR_SRD_MASK (0x0000FF00u) - #define MPU_ATTR_SRD_BIT (8) - #define MPU_ATTR_SRD_BITS (8) - /* SIZE field */ - #define MPU_ATTR_SIZE (0x0000003Eu) - #define MPU_ATTR_SIZE_MASK (0x0000003Eu) - #define MPU_ATTR_SIZE_BIT (1) - #define MPU_ATTR_SIZE_BITS (5) - /* ENABLE field */ - #define MPU_ATTR_ENABLE (0x00000001u) - #define MPU_ATTR_ENABLE_MASK (0x00000001u) - #define MPU_ATTR_ENABLE_BIT (0) - #define MPU_ATTR_ENABLE_BITS (1) +/* XN field */ +#define MPU_ATTR_XN (0x10000000u) +#define MPU_ATTR_XN_MASK (0x10000000u) +#define MPU_ATTR_XN_BIT (28) +#define MPU_ATTR_XN_BITS (1) +/* AP field */ +#define MPU_ATTR_AP (0x07000000u) +#define MPU_ATTR_AP_MASK (0x07000000u) +#define MPU_ATTR_AP_BIT (24) +#define MPU_ATTR_AP_BITS (3) +/* TEX field */ +#define MPU_ATTR_TEX (0x00380000u) +#define MPU_ATTR_TEX_MASK (0x00380000u) +#define MPU_ATTR_TEX_BIT (19) +#define MPU_ATTR_TEX_BITS (3) +/* S field */ +#define MPU_ATTR_S (0x00040000u) +#define MPU_ATTR_S_MASK (0x00040000u) +#define MPU_ATTR_S_BIT (18) +#define MPU_ATTR_S_BITS (1) +/* C field */ +#define MPU_ATTR_C (0x00020000u) +#define MPU_ATTR_C_MASK (0x00020000u) +#define MPU_ATTR_C_BIT (17) +#define MPU_ATTR_C_BITS (1) +/* B field */ +#define MPU_ATTR_B (0x00010000u) +#define MPU_ATTR_B_MASK (0x00010000u) +#define MPU_ATTR_B_BIT (16) +#define MPU_ATTR_B_BITS (1) +/* SRD field */ +#define MPU_ATTR_SRD (0x0000FF00u) +#define MPU_ATTR_SRD_MASK (0x0000FF00u) +#define MPU_ATTR_SRD_BIT (8) +#define MPU_ATTR_SRD_BITS (8) +/* SIZE field */ +#define MPU_ATTR_SIZE (0x0000003Eu) +#define MPU_ATTR_SIZE_MASK (0x0000003Eu) +#define MPU_ATTR_SIZE_BIT (1) +#define MPU_ATTR_SIZE_BITS (5) +/* ENABLE field */ +#define MPU_ATTR_ENABLE (0x00000001u) +#define MPU_ATTR_ENABLE_MASK (0x00000001u) +#define MPU_ATTR_ENABLE_BIT (0) +#define MPU_ATTR_ENABLE_BITS (1) #define MPU_BASE1 *((volatile uint32_t *)0xE000EDA4u) #define MPU_BASE1_REG *((volatile uint32_t *)0xE000EDA4u) #define MPU_BASE1_ADDR (0xE000EDA4u) #define MPU_BASE1_RESET (0x00000000u) - /* ADDRESS field */ - #define MPU_BASE1_ADDRESS (0xFFFFFFE0u) - #define MPU_BASE1_ADDRESS_MASK (0xFFFFFFE0u) - #define MPU_BASE1_ADDRESS_BIT (5) - #define MPU_BASE1_ADDRESS_BITS (27) - /* VALID field */ - #define MPU_BASE1_VALID (0x00000010u) - #define MPU_BASE1_VALID_MASK (0x00000010u) - #define MPU_BASE1_VALID_BIT (4) - #define MPU_BASE1_VALID_BITS (1) - /* REGION field */ - #define MPU_BASE1_REGION (0x0000000Fu) - #define MPU_BASE1_REGION_MASK (0x0000000Fu) - #define MPU_BASE1_REGION_BIT (0) - #define MPU_BASE1_REGION_BITS (4) +/* ADDRESS field */ +#define MPU_BASE1_ADDRESS (0xFFFFFFE0u) +#define MPU_BASE1_ADDRESS_MASK (0xFFFFFFE0u) +#define MPU_BASE1_ADDRESS_BIT (5) +#define MPU_BASE1_ADDRESS_BITS (27) +/* VALID field */ +#define MPU_BASE1_VALID (0x00000010u) +#define MPU_BASE1_VALID_MASK (0x00000010u) +#define MPU_BASE1_VALID_BIT (4) +#define MPU_BASE1_VALID_BITS (1) +/* REGION field */ +#define MPU_BASE1_REGION (0x0000000Fu) +#define MPU_BASE1_REGION_MASK (0x0000000Fu) +#define MPU_BASE1_REGION_BIT (0) +#define MPU_BASE1_REGION_BITS (4) #define MPU_ATTR1 *((volatile uint32_t *)0xE000EDA8u) #define MPU_ATTR1_REG *((volatile uint32_t *)0xE000EDA8u) #define MPU_ATTR1_ADDR (0xE000EDA8u) #define MPU_ATTR1_RESET (0x00000000u) - /* XN field */ - #define MPU_ATTR1_XN (0x10000000u) - #define MPU_ATTR1_XN_MASK (0x10000000u) - #define MPU_ATTR1_XN_BIT (28) - #define MPU_ATTR1_XN_BITS (1) - /* AP field */ - #define MPU_ATTR1_AP (0x07000000u) - #define MPU_ATTR1_AP_MASK (0x07000000u) - #define MPU_ATTR1_AP_BIT (24) - #define MPU_ATTR1_AP_BITS (3) - /* TEX field */ - #define MPU_ATTR1_TEX (0x00380000u) - #define MPU_ATTR1_TEX_MASK (0x00380000u) - #define MPU_ATTR1_TEX_BIT (19) - #define MPU_ATTR1_TEX_BITS (3) - /* S field */ - #define MPU_ATTR1_S (0x00040000u) - #define MPU_ATTR1_S_MASK (0x00040000u) - #define MPU_ATTR1_S_BIT (18) - #define MPU_ATTR1_S_BITS (1) - /* C field */ - #define MPU_ATTR1_C (0x00020000u) - #define MPU_ATTR1_C_MASK (0x00020000u) - #define MPU_ATTR1_C_BIT (17) - #define MPU_ATTR1_C_BITS (1) - /* B field */ - #define MPU_ATTR1_B (0x00010000u) - #define MPU_ATTR1_B_MASK (0x00010000u) - #define MPU_ATTR1_B_BIT (16) - #define MPU_ATTR1_B_BITS (1) - /* SRD field */ - #define MPU_ATTR1_SRD (0x0000FF00u) - #define MPU_ATTR1_SRD_MASK (0x0000FF00u) - #define MPU_ATTR1_SRD_BIT (8) - #define MPU_ATTR1_SRD_BITS (8) - /* SIZE field */ - #define MPU_ATTR1_SIZE (0x0000003Eu) - #define MPU_ATTR1_SIZE_MASK (0x0000003Eu) - #define MPU_ATTR1_SIZE_BIT (1) - #define MPU_ATTR1_SIZE_BITS (5) - /* ENABLE field */ - #define MPU_ATTR1_ENABLE (0x00000001u) - #define MPU_ATTR1_ENABLE_MASK (0x00000001u) - #define MPU_ATTR1_ENABLE_BIT (0) - #define MPU_ATTR1_ENABLE_BITS (1) +/* XN field */ +#define MPU_ATTR1_XN (0x10000000u) +#define MPU_ATTR1_XN_MASK (0x10000000u) +#define MPU_ATTR1_XN_BIT (28) +#define MPU_ATTR1_XN_BITS (1) +/* AP field */ +#define MPU_ATTR1_AP (0x07000000u) +#define MPU_ATTR1_AP_MASK (0x07000000u) +#define MPU_ATTR1_AP_BIT (24) +#define MPU_ATTR1_AP_BITS (3) +/* TEX field */ +#define MPU_ATTR1_TEX (0x00380000u) +#define MPU_ATTR1_TEX_MASK (0x00380000u) +#define MPU_ATTR1_TEX_BIT (19) +#define MPU_ATTR1_TEX_BITS (3) +/* S field */ +#define MPU_ATTR1_S (0x00040000u) +#define MPU_ATTR1_S_MASK (0x00040000u) +#define MPU_ATTR1_S_BIT (18) +#define MPU_ATTR1_S_BITS (1) +/* C field */ +#define MPU_ATTR1_C (0x00020000u) +#define MPU_ATTR1_C_MASK (0x00020000u) +#define MPU_ATTR1_C_BIT (17) +#define MPU_ATTR1_C_BITS (1) +/* B field */ +#define MPU_ATTR1_B (0x00010000u) +#define MPU_ATTR1_B_MASK (0x00010000u) +#define MPU_ATTR1_B_BIT (16) +#define MPU_ATTR1_B_BITS (1) +/* SRD field */ +#define MPU_ATTR1_SRD (0x0000FF00u) +#define MPU_ATTR1_SRD_MASK (0x0000FF00u) +#define MPU_ATTR1_SRD_BIT (8) +#define MPU_ATTR1_SRD_BITS (8) +/* SIZE field */ +#define MPU_ATTR1_SIZE (0x0000003Eu) +#define MPU_ATTR1_SIZE_MASK (0x0000003Eu) +#define MPU_ATTR1_SIZE_BIT (1) +#define MPU_ATTR1_SIZE_BITS (5) +/* ENABLE field */ +#define MPU_ATTR1_ENABLE (0x00000001u) +#define MPU_ATTR1_ENABLE_MASK (0x00000001u) +#define MPU_ATTR1_ENABLE_BIT (0) +#define MPU_ATTR1_ENABLE_BITS (1) #define MPU_BASE2 *((volatile uint32_t *)0xE000EDACu) #define MPU_BASE2_REG *((volatile uint32_t *)0xE000EDACu) #define MPU_BASE2_ADDR (0xE000EDACu) #define MPU_BASE2_RESET (0x00000000u) - /* ADDRESS field */ - #define MPU_BASE2_ADDRESS (0xFFFFFFE0u) - #define MPU_BASE2_ADDRESS_MASK (0xFFFFFFE0u) - #define MPU_BASE2_ADDRESS_BIT (5) - #define MPU_BASE2_ADDRESS_BITS (27) - /* VALID field */ - #define MPU_BASE2_VALID (0x00000010u) - #define MPU_BASE2_VALID_MASK (0x00000010u) - #define MPU_BASE2_VALID_BIT (4) - #define MPU_BASE2_VALID_BITS (1) - /* REGION field */ - #define MPU_BASE2_REGION (0x0000000Fu) - #define MPU_BASE2_REGION_MASK (0x0000000Fu) - #define MPU_BASE2_REGION_BIT (0) - #define MPU_BASE2_REGION_BITS (4) +/* ADDRESS field */ +#define MPU_BASE2_ADDRESS (0xFFFFFFE0u) +#define MPU_BASE2_ADDRESS_MASK (0xFFFFFFE0u) +#define MPU_BASE2_ADDRESS_BIT (5) +#define MPU_BASE2_ADDRESS_BITS (27) +/* VALID field */ +#define MPU_BASE2_VALID (0x00000010u) +#define MPU_BASE2_VALID_MASK (0x00000010u) +#define MPU_BASE2_VALID_BIT (4) +#define MPU_BASE2_VALID_BITS (1) +/* REGION field */ +#define MPU_BASE2_REGION (0x0000000Fu) +#define MPU_BASE2_REGION_MASK (0x0000000Fu) +#define MPU_BASE2_REGION_BIT (0) +#define MPU_BASE2_REGION_BITS (4) #define MPU_ATTR2 *((volatile uint32_t *)0xE000EDB0u) #define MPU_ATTR2_REG *((volatile uint32_t *)0xE000EDB0u) #define MPU_ATTR2_ADDR (0xE000EDB0u) #define MPU_ATTR2_RESET (0x00000000u) - /* XN field */ - #define MPU_ATTR2_XN (0x10000000u) - #define MPU_ATTR2_XN_MASK (0x10000000u) - #define MPU_ATTR2_XN_BIT (28) - #define MPU_ATTR2_XN_BITS (1) - /* AP field */ - #define MPU_ATTR2_AP (0x1F000000u) - #define MPU_ATTR2_AP_MASK (0x1F000000u) - #define MPU_ATTR2_AP_BIT (24) - #define MPU_ATTR2_AP_BITS (5) - /* TEX field */ - #define MPU_ATTR2_TEX (0x00380000u) - #define MPU_ATTR2_TEX_MASK (0x00380000u) - #define MPU_ATTR2_TEX_BIT (19) - #define MPU_ATTR2_TEX_BITS (3) - /* S field */ - #define MPU_ATTR2_S (0x00040000u) - #define MPU_ATTR2_S_MASK (0x00040000u) - #define MPU_ATTR2_S_BIT (18) - #define MPU_ATTR2_S_BITS (1) - /* C field */ - #define MPU_ATTR2_C (0x00020000u) - #define MPU_ATTR2_C_MASK (0x00020000u) - #define MPU_ATTR2_C_BIT (17) - #define MPU_ATTR2_C_BITS (1) - /* B field */ - #define MPU_ATTR2_B (0x00010000u) - #define MPU_ATTR2_B_MASK (0x00010000u) - #define MPU_ATTR2_B_BIT (16) - #define MPU_ATTR2_B_BITS (1) - /* SRD field */ - #define MPU_ATTR2_SRD (0x0000FF00u) - #define MPU_ATTR2_SRD_MASK (0x0000FF00u) - #define MPU_ATTR2_SRD_BIT (8) - #define MPU_ATTR2_SRD_BITS (8) - /* SIZE field */ - #define MPU_ATTR2_SIZE (0x0000003Eu) - #define MPU_ATTR2_SIZE_MASK (0x0000003Eu) - #define MPU_ATTR2_SIZE_BIT (1) - #define MPU_ATTR2_SIZE_BITS (5) - /* ENABLE field */ - #define MPU_ATTR2_ENABLE (0x00000003u) - #define MPU_ATTR2_ENABLE_MASK (0x00000003u) - #define MPU_ATTR2_ENABLE_BIT (0) - #define MPU_ATTR2_ENABLE_BITS (2) +/* XN field */ +#define MPU_ATTR2_XN (0x10000000u) +#define MPU_ATTR2_XN_MASK (0x10000000u) +#define MPU_ATTR2_XN_BIT (28) +#define MPU_ATTR2_XN_BITS (1) +/* AP field */ +#define MPU_ATTR2_AP (0x1F000000u) +#define MPU_ATTR2_AP_MASK (0x1F000000u) +#define MPU_ATTR2_AP_BIT (24) +#define MPU_ATTR2_AP_BITS (5) +/* TEX field */ +#define MPU_ATTR2_TEX (0x00380000u) +#define MPU_ATTR2_TEX_MASK (0x00380000u) +#define MPU_ATTR2_TEX_BIT (19) +#define MPU_ATTR2_TEX_BITS (3) +/* S field */ +#define MPU_ATTR2_S (0x00040000u) +#define MPU_ATTR2_S_MASK (0x00040000u) +#define MPU_ATTR2_S_BIT (18) +#define MPU_ATTR2_S_BITS (1) +/* C field */ +#define MPU_ATTR2_C (0x00020000u) +#define MPU_ATTR2_C_MASK (0x00020000u) +#define MPU_ATTR2_C_BIT (17) +#define MPU_ATTR2_C_BITS (1) +/* B field */ +#define MPU_ATTR2_B (0x00010000u) +#define MPU_ATTR2_B_MASK (0x00010000u) +#define MPU_ATTR2_B_BIT (16) +#define MPU_ATTR2_B_BITS (1) +/* SRD field */ +#define MPU_ATTR2_SRD (0x0000FF00u) +#define MPU_ATTR2_SRD_MASK (0x0000FF00u) +#define MPU_ATTR2_SRD_BIT (8) +#define MPU_ATTR2_SRD_BITS (8) +/* SIZE field */ +#define MPU_ATTR2_SIZE (0x0000003Eu) +#define MPU_ATTR2_SIZE_MASK (0x0000003Eu) +#define MPU_ATTR2_SIZE_BIT (1) +#define MPU_ATTR2_SIZE_BITS (5) +/* ENABLE field */ +#define MPU_ATTR2_ENABLE (0x00000003u) +#define MPU_ATTR2_ENABLE_MASK (0x00000003u) +#define MPU_ATTR2_ENABLE_BIT (0) +#define MPU_ATTR2_ENABLE_BITS (2) #define MPU_BASE3 *((volatile uint32_t *)0xE000EDB4u) #define MPU_BASE3_REG *((volatile uint32_t *)0xE000EDB4u) #define MPU_BASE3_ADDR (0xE000EDB4u) #define MPU_BASE3_RESET (0x00000000u) - /* ADDRESS field */ - #define MPU_BASE3_ADDRESS (0xFFFFFFE0u) - #define MPU_BASE3_ADDRESS_MASK (0xFFFFFFE0u) - #define MPU_BASE3_ADDRESS_BIT (5) - #define MPU_BASE3_ADDRESS_BITS (27) - /* VALID field */ - #define MPU_BASE3_VALID (0x00000010u) - #define MPU_BASE3_VALID_MASK (0x00000010u) - #define MPU_BASE3_VALID_BIT (4) - #define MPU_BASE3_VALID_BITS (1) - /* REGION field */ - #define MPU_BASE3_REGION (0x0000000Fu) - #define MPU_BASE3_REGION_MASK (0x0000000Fu) - #define MPU_BASE3_REGION_BIT (0) - #define MPU_BASE3_REGION_BITS (4) +/* ADDRESS field */ +#define MPU_BASE3_ADDRESS (0xFFFFFFE0u) +#define MPU_BASE3_ADDRESS_MASK (0xFFFFFFE0u) +#define MPU_BASE3_ADDRESS_BIT (5) +#define MPU_BASE3_ADDRESS_BITS (27) +/* VALID field */ +#define MPU_BASE3_VALID (0x00000010u) +#define MPU_BASE3_VALID_MASK (0x00000010u) +#define MPU_BASE3_VALID_BIT (4) +#define MPU_BASE3_VALID_BITS (1) +/* REGION field */ +#define MPU_BASE3_REGION (0x0000000Fu) +#define MPU_BASE3_REGION_MASK (0x0000000Fu) +#define MPU_BASE3_REGION_BIT (0) +#define MPU_BASE3_REGION_BITS (4) #define MPU_ATTR3 *((volatile uint32_t *)0xE000EDBCu) #define MPU_ATTR3_REG *((volatile uint32_t *)0xE000EDBCu) #define MPU_ATTR3_ADDR (0xE000EDBCu) #define MPU_ATTR3_RESET (0x00000000u) - /* XN field */ - #define MPU_ATTR3_XN (0x10000000u) - #define MPU_ATTR3_XN_MASK (0x10000000u) - #define MPU_ATTR3_XN_BIT (28) - #define MPU_ATTR3_XN_BITS (1) - /* AP field */ - #define MPU_ATTR3_AP (0x1F000000u) - #define MPU_ATTR3_AP_MASK (0x1F000000u) - #define MPU_ATTR3_AP_BIT (24) - #define MPU_ATTR3_AP_BITS (5) - /* TEX field */ - #define MPU_ATTR3_TEX (0x00380000u) - #define MPU_ATTR3_TEX_MASK (0x00380000u) - #define MPU_ATTR3_TEX_BIT (19) - #define MPU_ATTR3_TEX_BITS (3) - /* S field */ - #define MPU_ATTR3_S (0x00040000u) - #define MPU_ATTR3_S_MASK (0x00040000u) - #define MPU_ATTR3_S_BIT (18) - #define MPU_ATTR3_S_BITS (1) - /* C field */ - #define MPU_ATTR3_C (0x00020000u) - #define MPU_ATTR3_C_MASK (0x00020000u) - #define MPU_ATTR3_C_BIT (17) - #define MPU_ATTR3_C_BITS (1) - /* B field */ - #define MPU_ATTR3_B (0x00010000u) - #define MPU_ATTR3_B_MASK (0x00010000u) - #define MPU_ATTR3_B_BIT (16) - #define MPU_ATTR3_B_BITS (1) - /* SRD field */ - #define MPU_ATTR3_SRD (0x0000FF00u) - #define MPU_ATTR3_SRD_MASK (0x0000FF00u) - #define MPU_ATTR3_SRD_BIT (8) - #define MPU_ATTR3_SRD_BITS (8) - /* SIZE field */ - #define MPU_ATTR3_SIZE (0x0000003Eu) - #define MPU_ATTR3_SIZE_MASK (0x0000003Eu) - #define MPU_ATTR3_SIZE_BIT (1) - #define MPU_ATTR3_SIZE_BITS (5) - /* ENABLE field */ - #define MPU_ATTR3_ENABLE (0x00000003u) - #define MPU_ATTR3_ENABLE_MASK (0x00000003u) - #define MPU_ATTR3_ENABLE_BIT (0) - #define MPU_ATTR3_ENABLE_BITS (2) +/* XN field */ +#define MPU_ATTR3_XN (0x10000000u) +#define MPU_ATTR3_XN_MASK (0x10000000u) +#define MPU_ATTR3_XN_BIT (28) +#define MPU_ATTR3_XN_BITS (1) +/* AP field */ +#define MPU_ATTR3_AP (0x1F000000u) +#define MPU_ATTR3_AP_MASK (0x1F000000u) +#define MPU_ATTR3_AP_BIT (24) +#define MPU_ATTR3_AP_BITS (5) +/* TEX field */ +#define MPU_ATTR3_TEX (0x00380000u) +#define MPU_ATTR3_TEX_MASK (0x00380000u) +#define MPU_ATTR3_TEX_BIT (19) +#define MPU_ATTR3_TEX_BITS (3) +/* S field */ +#define MPU_ATTR3_S (0x00040000u) +#define MPU_ATTR3_S_MASK (0x00040000u) +#define MPU_ATTR3_S_BIT (18) +#define MPU_ATTR3_S_BITS (1) +/* C field */ +#define MPU_ATTR3_C (0x00020000u) +#define MPU_ATTR3_C_MASK (0x00020000u) +#define MPU_ATTR3_C_BIT (17) +#define MPU_ATTR3_C_BITS (1) +/* B field */ +#define MPU_ATTR3_B (0x00010000u) +#define MPU_ATTR3_B_MASK (0x00010000u) +#define MPU_ATTR3_B_BIT (16) +#define MPU_ATTR3_B_BITS (1) +/* SRD field */ +#define MPU_ATTR3_SRD (0x0000FF00u) +#define MPU_ATTR3_SRD_MASK (0x0000FF00u) +#define MPU_ATTR3_SRD_BIT (8) +#define MPU_ATTR3_SRD_BITS (8) +/* SIZE field */ +#define MPU_ATTR3_SIZE (0x0000003Eu) +#define MPU_ATTR3_SIZE_MASK (0x0000003Eu) +#define MPU_ATTR3_SIZE_BIT (1) +#define MPU_ATTR3_SIZE_BITS (5) +/* ENABLE field */ +#define MPU_ATTR3_ENABLE (0x00000003u) +#define MPU_ATTR3_ENABLE_MASK (0x00000003u) +#define MPU_ATTR3_ENABLE_BIT (0) +#define MPU_ATTR3_ENABLE_BITS (2) #define DEBUG_HCSR *((volatile uint32_t *)0xE000EDF0u) #define DEBUG_HCSR_REG *((volatile uint32_t *)0xE000EDF0u) #define DEBUG_HCSR_ADDR (0xE000EDF0u) #define DEBUG_HCSR_RESET (0x00000000u) - /* S_RESET_ST field */ - #define DEBUG_HCSR_S_RESET_ST (0x02000000u) - #define DEBUG_HCSR_S_RESET_ST_MASK (0x02000000u) - #define DEBUG_HCSR_S_RESET_ST_BIT (25) - #define DEBUG_HCSR_S_RESET_ST_BITS (1) - /* S_RETIRE_ST field */ - #define DEBUG_HCSR_S_RETIRE_ST (0x01000000u) - #define DEBUG_HCSR_S_RETIRE_ST_MASK (0x01000000u) - #define DEBUG_HCSR_S_RETIRE_ST_BIT (24) - #define DEBUG_HCSR_S_RETIRE_ST_BITS (1) - /* S_LOCKUP field */ - #define DEBUG_HCSR_S_LOCKUP (0x00080000u) - #define DEBUG_HCSR_S_LOCKUP_MASK (0x00080000u) - #define DEBUG_HCSR_S_LOCKUP_BIT (19) - #define DEBUG_HCSR_S_LOCKUP_BITS (1) - /* S_SLEEP field */ - #define DEBUG_HCSR_S_SLEEP (0x00040000u) - #define DEBUG_HCSR_S_SLEEP_MASK (0x00040000u) - #define DEBUG_HCSR_S_SLEEP_BIT (18) - #define DEBUG_HCSR_S_SLEEP_BITS (1) - /* S_HALT field */ - #define DEBUG_HCSR_S_HALT (0x00020000u) - #define DEBUG_HCSR_S_HALT_MASK (0x00020000u) - #define DEBUG_HCSR_S_HALT_BIT (17) - #define DEBUG_HCSR_S_HALT_BITS (1) - /* S_REGRDY field */ - #define DEBUG_HCSR_S_REGRDY (0x00010000u) - #define DEBUG_HCSR_S_REGRDY_MASK (0x00010000u) - #define DEBUG_HCSR_S_REGRDY_BIT (16) - #define DEBUG_HCSR_S_REGRDY_BITS (1) - /* DBGKEY field */ - #define DEBUG_HCSR_DBGKEY (0xFFFF0000u) - #define DEBUG_HCSR_DBGKEY_MASK (0xFFFF0000u) - #define DEBUG_HCSR_DBGKEY_BIT (16) - #define DEBUG_HCSR_DBGKEY_BITS (16) - /* C_SNAPSTALL field */ - #define DEBUG_HCSR_C_SNAPSTALL (0x00000020u) - #define DEBUG_HCSR_C_SNAPSTALL_MASK (0x00000020u) - #define DEBUG_HCSR_C_SNAPSTALL_BIT (5) - #define DEBUG_HCSR_C_SNAPSTALL_BITS (1) - /* C_MASKINTS field */ - #define DEBUG_HCSR_C_MASKINTS (0x00000008u) - #define DEBUG_HCSR_C_MASKINTS_MASK (0x00000008u) - #define DEBUG_HCSR_C_MASKINTS_BIT (3) - #define DEBUG_HCSR_C_MASKINTS_BITS (1) - /* C_STEP field */ - #define DEBUG_HCSR_C_STEP (0x00000004u) - #define DEBUG_HCSR_C_STEP_MASK (0x00000004u) - #define DEBUG_HCSR_C_STEP_BIT (2) - #define DEBUG_HCSR_C_STEP_BITS (1) - /* C_HALT field */ - #define DEBUG_HCSR_C_HALT (0x00000002u) - #define DEBUG_HCSR_C_HALT_MASK (0x00000002u) - #define DEBUG_HCSR_C_HALT_BIT (1) - #define DEBUG_HCSR_C_HALT_BITS (1) - /* C_DEBUGEN field */ - #define DEBUG_HCSR_C_DEBUGEN (0x00000001u) - #define DEBUG_HCSR_C_DEBUGEN_MASK (0x00000001u) - #define DEBUG_HCSR_C_DEBUGEN_BIT (0) - #define DEBUG_HCSR_C_DEBUGEN_BITS (1) +/* S_RESET_ST field */ +#define DEBUG_HCSR_S_RESET_ST (0x02000000u) +#define DEBUG_HCSR_S_RESET_ST_MASK (0x02000000u) +#define DEBUG_HCSR_S_RESET_ST_BIT (25) +#define DEBUG_HCSR_S_RESET_ST_BITS (1) +/* S_RETIRE_ST field */ +#define DEBUG_HCSR_S_RETIRE_ST (0x01000000u) +#define DEBUG_HCSR_S_RETIRE_ST_MASK (0x01000000u) +#define DEBUG_HCSR_S_RETIRE_ST_BIT (24) +#define DEBUG_HCSR_S_RETIRE_ST_BITS (1) +/* S_LOCKUP field */ +#define DEBUG_HCSR_S_LOCKUP (0x00080000u) +#define DEBUG_HCSR_S_LOCKUP_MASK (0x00080000u) +#define DEBUG_HCSR_S_LOCKUP_BIT (19) +#define DEBUG_HCSR_S_LOCKUP_BITS (1) +/* S_SLEEP field */ +#define DEBUG_HCSR_S_SLEEP (0x00040000u) +#define DEBUG_HCSR_S_SLEEP_MASK (0x00040000u) +#define DEBUG_HCSR_S_SLEEP_BIT (18) +#define DEBUG_HCSR_S_SLEEP_BITS (1) +/* S_HALT field */ +#define DEBUG_HCSR_S_HALT (0x00020000u) +#define DEBUG_HCSR_S_HALT_MASK (0x00020000u) +#define DEBUG_HCSR_S_HALT_BIT (17) +#define DEBUG_HCSR_S_HALT_BITS (1) +/* S_REGRDY field */ +#define DEBUG_HCSR_S_REGRDY (0x00010000u) +#define DEBUG_HCSR_S_REGRDY_MASK (0x00010000u) +#define DEBUG_HCSR_S_REGRDY_BIT (16) +#define DEBUG_HCSR_S_REGRDY_BITS (1) +/* DBGKEY field */ +#define DEBUG_HCSR_DBGKEY (0xFFFF0000u) +#define DEBUG_HCSR_DBGKEY_MASK (0xFFFF0000u) +#define DEBUG_HCSR_DBGKEY_BIT (16) +#define DEBUG_HCSR_DBGKEY_BITS (16) +/* C_SNAPSTALL field */ +#define DEBUG_HCSR_C_SNAPSTALL (0x00000020u) +#define DEBUG_HCSR_C_SNAPSTALL_MASK (0x00000020u) +#define DEBUG_HCSR_C_SNAPSTALL_BIT (5) +#define DEBUG_HCSR_C_SNAPSTALL_BITS (1) +/* C_MASKINTS field */ +#define DEBUG_HCSR_C_MASKINTS (0x00000008u) +#define DEBUG_HCSR_C_MASKINTS_MASK (0x00000008u) +#define DEBUG_HCSR_C_MASKINTS_BIT (3) +#define DEBUG_HCSR_C_MASKINTS_BITS (1) +/* C_STEP field */ +#define DEBUG_HCSR_C_STEP (0x00000004u) +#define DEBUG_HCSR_C_STEP_MASK (0x00000004u) +#define DEBUG_HCSR_C_STEP_BIT (2) +#define DEBUG_HCSR_C_STEP_BITS (1) +/* C_HALT field */ +#define DEBUG_HCSR_C_HALT (0x00000002u) +#define DEBUG_HCSR_C_HALT_MASK (0x00000002u) +#define DEBUG_HCSR_C_HALT_BIT (1) +#define DEBUG_HCSR_C_HALT_BITS (1) +/* C_DEBUGEN field */ +#define DEBUG_HCSR_C_DEBUGEN (0x00000001u) +#define DEBUG_HCSR_C_DEBUGEN_MASK (0x00000001u) +#define DEBUG_HCSR_C_DEBUGEN_BIT (0) +#define DEBUG_HCSR_C_DEBUGEN_BITS (1) #define DEBUG_CRSR *((volatile uint32_t *)0xE000EDF4u) #define DEBUG_CRSR_REG *((volatile uint32_t *)0xE000EDF4u) #define DEBUG_CRSR_ADDR (0xE000EDF4u) #define DEBUG_CRSR_RESET (0x00000000u) - /* REGWnR field */ - #define DEBUG_CRSR_REGWnR (0x00010000u) - #define DEBUG_CRSR_REGWnR_MASK (0x00010000u) - #define DEBUG_CRSR_REGWnR_BIT (16) - #define DEBUG_CRSR_REGWnR_BITS (1) - /* REGSEL field */ - #define DEBUG_CRSR_REGSEL (0x0000001Fu) - #define DEBUG_CRSR_REGSEL_MASK (0x0000001Fu) - #define DEBUG_CRSR_REGSEL_BIT (0) - #define DEBUG_CRSR_REGSEL_BITS (5) +/* REGWnR field */ +#define DEBUG_CRSR_REGWnR (0x00010000u) +#define DEBUG_CRSR_REGWnR_MASK (0x00010000u) +#define DEBUG_CRSR_REGWnR_BIT (16) +#define DEBUG_CRSR_REGWnR_BITS (1) +/* REGSEL field */ +#define DEBUG_CRSR_REGSEL (0x0000001Fu) +#define DEBUG_CRSR_REGSEL_MASK (0x0000001Fu) +#define DEBUG_CRSR_REGSEL_BIT (0) +#define DEBUG_CRSR_REGSEL_BITS (5) #define DEBUG_CRDR *((volatile uint32_t *)0xE000EDF8u) #define DEBUG_CRDR_REG *((volatile uint32_t *)0xE000EDF8u) #define DEBUG_CRDR_ADDR (0xE000EDF8u) #define DEBUG_CRDR_RESET (0x00000000u) - /* DBGTMP field */ - #define DEBUG_CRDR_DBGTMP (0xFFFFFFFFu) - #define DEBUG_CRDR_DBGTMP_MASK (0xFFFFFFFFu) - #define DEBUG_CRDR_DBGTMP_BIT (0) - #define DEBUG_CRDR_DBGTMP_BITS (32) +/* DBGTMP field */ +#define DEBUG_CRDR_DBGTMP (0xFFFFFFFFu) +#define DEBUG_CRDR_DBGTMP_MASK (0xFFFFFFFFu) +#define DEBUG_CRDR_DBGTMP_BIT (0) +#define DEBUG_CRDR_DBGTMP_BITS (32) #define DEBUG_EMCR *((volatile uint32_t *)0xE000EDFCu) #define DEBUG_EMCR_REG *((volatile uint32_t *)0xE000EDFCu) #define DEBUG_EMCR_ADDR (0xE000EDFCu) #define DEBUG_EMCR_RESET (0x00000000u) - /* TRCENA field */ - #define DEBUG_EMCR_TRCENA (0x01000000u) - #define DEBUG_EMCR_TRCENA_MASK (0x01000000u) - #define DEBUG_EMCR_TRCENA_BIT (24) - #define DEBUG_EMCR_TRCENA_BITS (1) - /* MON_REQ field */ - #define DEBUG_EMCR_MON_REQ (0x00080000u) - #define DEBUG_EMCR_MON_REQ_MASK (0x00080000u) - #define DEBUG_EMCR_MON_REQ_BIT (19) - #define DEBUG_EMCR_MON_REQ_BITS (1) - /* MON_STEP field */ - #define DEBUG_EMCR_MON_STEP (0x00040000u) - #define DEBUG_EMCR_MON_STEP_MASK (0x00040000u) - #define DEBUG_EMCR_MON_STEP_BIT (18) - #define DEBUG_EMCR_MON_STEP_BITS (1) - /* MON_PEND field */ - #define DEBUG_EMCR_MON_PEND (0x00020000u) - #define DEBUG_EMCR_MON_PEND_MASK (0x00020000u) - #define DEBUG_EMCR_MON_PEND_BIT (17) - #define DEBUG_EMCR_MON_PEND_BITS (1) - /* MON_EN field */ - #define DEBUG_EMCR_MON_EN (0x00010000u) - #define DEBUG_EMCR_MON_EN_MASK (0x00010000u) - #define DEBUG_EMCR_MON_EN_BIT (16) - #define DEBUG_EMCR_MON_EN_BITS (1) - /* VC_HARDERR field */ - #define DEBUG_EMCR_VC_HARDERR (0x00000400u) - #define DEBUG_EMCR_VC_HARDERR_MASK (0x00000400u) - #define DEBUG_EMCR_VC_HARDERR_BIT (10) - #define DEBUG_EMCR_VC_HARDERR_BITS (1) - /* VC_INTERR field */ - #define DEBUG_EMCR_VC_INTERR (0x00000200u) - #define DEBUG_EMCR_VC_INTERR_MASK (0x00000200u) - #define DEBUG_EMCR_VC_INTERR_BIT (9) - #define DEBUG_EMCR_VC_INTERR_BITS (1) - /* VC_BUSERR field */ - #define DEBUG_EMCR_VC_BUSERR (0x00000100u) - #define DEBUG_EMCR_VC_BUSERR_MASK (0x00000100u) - #define DEBUG_EMCR_VC_BUSERR_BIT (8) - #define DEBUG_EMCR_VC_BUSERR_BITS (1) - /* VC_STATERR field */ - #define DEBUG_EMCR_VC_STATERR (0x00000080u) - #define DEBUG_EMCR_VC_STATERR_MASK (0x00000080u) - #define DEBUG_EMCR_VC_STATERR_BIT (7) - #define DEBUG_EMCR_VC_STATERR_BITS (1) - /* VC_CHKERR field */ - #define DEBUG_EMCR_VC_CHKERR (0x00000040u) - #define DEBUG_EMCR_VC_CHKERR_MASK (0x00000040u) - #define DEBUG_EMCR_VC_CHKERR_BIT (6) - #define DEBUG_EMCR_VC_CHKERR_BITS (1) - /* VC_NOCPERR field */ - #define DEBUG_EMCR_VC_NOCPERR (0x00000020u) - #define DEBUG_EMCR_VC_NOCPERR_MASK (0x00000020u) - #define DEBUG_EMCR_VC_NOCPERR_BIT (5) - #define DEBUG_EMCR_VC_NOCPERR_BITS (1) - /* VC_MMERR field */ - #define DEBUG_EMCR_VC_MMERR (0x00000010u) - #define DEBUG_EMCR_VC_MMERR_MASK (0x00000010u) - #define DEBUG_EMCR_VC_MMERR_BIT (4) - #define DEBUG_EMCR_VC_MMERR_BITS (1) - /* VC_CORERESET field */ - #define DEBUG_EMCR_VC_CORERESET (0x00000001u) - #define DEBUG_EMCR_VC_CORERESET_MASK (0x00000001u) - #define DEBUG_EMCR_VC_CORERESET_BIT (0) - #define DEBUG_EMCR_VC_CORERESET_BITS (1) +/* TRCENA field */ +#define DEBUG_EMCR_TRCENA (0x01000000u) +#define DEBUG_EMCR_TRCENA_MASK (0x01000000u) +#define DEBUG_EMCR_TRCENA_BIT (24) +#define DEBUG_EMCR_TRCENA_BITS (1) +/* MON_REQ field */ +#define DEBUG_EMCR_MON_REQ (0x00080000u) +#define DEBUG_EMCR_MON_REQ_MASK (0x00080000u) +#define DEBUG_EMCR_MON_REQ_BIT (19) +#define DEBUG_EMCR_MON_REQ_BITS (1) +/* MON_STEP field */ +#define DEBUG_EMCR_MON_STEP (0x00040000u) +#define DEBUG_EMCR_MON_STEP_MASK (0x00040000u) +#define DEBUG_EMCR_MON_STEP_BIT (18) +#define DEBUG_EMCR_MON_STEP_BITS (1) +/* MON_PEND field */ +#define DEBUG_EMCR_MON_PEND (0x00020000u) +#define DEBUG_EMCR_MON_PEND_MASK (0x00020000u) +#define DEBUG_EMCR_MON_PEND_BIT (17) +#define DEBUG_EMCR_MON_PEND_BITS (1) +/* MON_EN field */ +#define DEBUG_EMCR_MON_EN (0x00010000u) +#define DEBUG_EMCR_MON_EN_MASK (0x00010000u) +#define DEBUG_EMCR_MON_EN_BIT (16) +#define DEBUG_EMCR_MON_EN_BITS (1) +/* VC_HARDERR field */ +#define DEBUG_EMCR_VC_HARDERR (0x00000400u) +#define DEBUG_EMCR_VC_HARDERR_MASK (0x00000400u) +#define DEBUG_EMCR_VC_HARDERR_BIT (10) +#define DEBUG_EMCR_VC_HARDERR_BITS (1) +/* VC_INTERR field */ +#define DEBUG_EMCR_VC_INTERR (0x00000200u) +#define DEBUG_EMCR_VC_INTERR_MASK (0x00000200u) +#define DEBUG_EMCR_VC_INTERR_BIT (9) +#define DEBUG_EMCR_VC_INTERR_BITS (1) +/* VC_BUSERR field */ +#define DEBUG_EMCR_VC_BUSERR (0x00000100u) +#define DEBUG_EMCR_VC_BUSERR_MASK (0x00000100u) +#define DEBUG_EMCR_VC_BUSERR_BIT (8) +#define DEBUG_EMCR_VC_BUSERR_BITS (1) +/* VC_STATERR field */ +#define DEBUG_EMCR_VC_STATERR (0x00000080u) +#define DEBUG_EMCR_VC_STATERR_MASK (0x00000080u) +#define DEBUG_EMCR_VC_STATERR_BIT (7) +#define DEBUG_EMCR_VC_STATERR_BITS (1) +/* VC_CHKERR field */ +#define DEBUG_EMCR_VC_CHKERR (0x00000040u) +#define DEBUG_EMCR_VC_CHKERR_MASK (0x00000040u) +#define DEBUG_EMCR_VC_CHKERR_BIT (6) +#define DEBUG_EMCR_VC_CHKERR_BITS (1) +/* VC_NOCPERR field */ +#define DEBUG_EMCR_VC_NOCPERR (0x00000020u) +#define DEBUG_EMCR_VC_NOCPERR_MASK (0x00000020u) +#define DEBUG_EMCR_VC_NOCPERR_BIT (5) +#define DEBUG_EMCR_VC_NOCPERR_BITS (1) +/* VC_MMERR field */ +#define DEBUG_EMCR_VC_MMERR (0x00000010u) +#define DEBUG_EMCR_VC_MMERR_MASK (0x00000010u) +#define DEBUG_EMCR_VC_MMERR_BIT (4) +#define DEBUG_EMCR_VC_MMERR_BITS (1) +/* VC_CORERESET field */ +#define DEBUG_EMCR_VC_CORERESET (0x00000001u) +#define DEBUG_EMCR_VC_CORERESET_MASK (0x00000001u) +#define DEBUG_EMCR_VC_CORERESET_BIT (0) +#define DEBUG_EMCR_VC_CORERESET_BITS (1) #define NVIC_STIR *((volatile uint32_t *)0xE000EF00u) #define NVIC_STIR_REG *((volatile uint32_t *)0xE000EF00u) #define NVIC_STIR_ADDR (0xE000EF00u) #define NVIC_STIR_RESET (0x00000000u) - /* INTID field */ - #define NVIC_STIR_INTID (0x000003FFu) - #define NVIC_STIR_INTID_MASK (0x000003FFu) - #define NVIC_STIR_INTID_BIT (0) - #define NVIC_STIR_INTID_BITS (10) +/* INTID field */ +#define NVIC_STIR_INTID (0x000003FFu) +#define NVIC_STIR_INTID_MASK (0x000003FFu) +#define NVIC_STIR_INTID_BIT (0) +#define NVIC_STIR_INTID_BITS (10) #define NVIC_PERIPHID4 *((volatile uint32_t *)0xE000EFD0u) #define NVIC_PERIPHID4_REG *((volatile uint32_t *)0xE000EFD0u) #define NVIC_PERIPHID4_ADDR (0xE000EFD0u) #define NVIC_PERIPHID4_RESET (0x00000004u) - /* PERIPHID field */ - #define NVIC_PERIPHID4_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID4_PERIPHID_BIT (0) - #define NVIC_PERIPHID4_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID4_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID4_PERIPHID_BIT (0) +#define NVIC_PERIPHID4_PERIPHID_BITS (32) #define NVIC_PERIPHID5 *((volatile uint32_t *)0xE000EFD4u) #define NVIC_PERIPHID5_REG *((volatile uint32_t *)0xE000EFD4u) #define NVIC_PERIPHID5_ADDR (0xE000EFD4u) #define NVIC_PERIPHID5_RESET (0x00000000u) - /* PERIPHID field */ - #define NVIC_PERIPHID5_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID5_PERIPHID_BIT (0) - #define NVIC_PERIPHID5_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID5_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID5_PERIPHID_BIT (0) +#define NVIC_PERIPHID5_PERIPHID_BITS (32) #define NVIC_PERIPHID6 *((volatile uint32_t *)0xE000EFD8u) #define NVIC_PERIPHID6_REG *((volatile uint32_t *)0xE000EFD8u) #define NVIC_PERIPHID6_ADDR (0xE000EFD8u) #define NVIC_PERIPHID6_RESET (0x00000000u) - /* PERIPHID field */ - #define NVIC_PERIPHID6_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID6_PERIPHID_BIT (0) - #define NVIC_PERIPHID6_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID6_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID6_PERIPHID_BIT (0) +#define NVIC_PERIPHID6_PERIPHID_BITS (32) #define NVIC_PERIPHID7 *((volatile uint32_t *)0xE000EFDCu) #define NVIC_PERIPHID7_REG *((volatile uint32_t *)0xE000EFDCu) #define NVIC_PERIPHID7_ADDR (0xE000EFDCu) #define NVIC_PERIPHID7_RESET (0x00000000u) - /* PERIPHID field */ - #define NVIC_PERIPHID7_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID7_PERIPHID_BIT (0) - #define NVIC_PERIPHID7_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID7_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID7_PERIPHID_BIT (0) +#define NVIC_PERIPHID7_PERIPHID_BITS (32) #define NVIC_PERIPHID0 *((volatile uint32_t *)0xE000EFE0u) #define NVIC_PERIPHID0_REG *((volatile uint32_t *)0xE000EFE0u) #define NVIC_PERIPHID0_ADDR (0xE000EFE0u) #define NVIC_PERIPHID0_RESET (0x00000000u) - /* PERIPHID field */ - #define NVIC_PERIPHID0_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID0_PERIPHID_BIT (0) - #define NVIC_PERIPHID0_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID0_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID0_PERIPHID_BIT (0) +#define NVIC_PERIPHID0_PERIPHID_BITS (32) #define NVIC_PERIPHID1 *((volatile uint32_t *)0xE000EFE4u) #define NVIC_PERIPHID1_REG *((volatile uint32_t *)0xE000EFE4u) #define NVIC_PERIPHID1_ADDR (0xE000EFE4u) #define NVIC_PERIPHID1_RESET (0x000000B0u) - /* PERIPHID field */ - #define NVIC_PERIPHID1_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID1_PERIPHID_BIT (0) - #define NVIC_PERIPHID1_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID1_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID1_PERIPHID_BIT (0) +#define NVIC_PERIPHID1_PERIPHID_BITS (32) #define NVIC_PERIPHID2 *((volatile uint32_t *)0xE000EFE8u) #define NVIC_PERIPHID2_REG *((volatile uint32_t *)0xE000EFE8u) #define NVIC_PERIPHID2_ADDR (0xE000EFE8u) #define NVIC_PERIPHID2_RESET (0x0000001Bu) - /* PERIPHID field */ - #define NVIC_PERIPHID2_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID2_PERIPHID_BIT (0) - #define NVIC_PERIPHID2_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID2_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID2_PERIPHID_BIT (0) +#define NVIC_PERIPHID2_PERIPHID_BITS (32) #define NVIC_PERIPHID3 *((volatile uint32_t *)0xE000EFECu) #define NVIC_PERIPHID3_REG *((volatile uint32_t *)0xE000EFECu) #define NVIC_PERIPHID3_ADDR (0xE000EFECu) #define NVIC_PERIPHID3_RESET (0x00000000u) - /* PERIPHID field */ - #define NVIC_PERIPHID3_PERIPHID (0xFFFFFFFFu) - #define NVIC_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) - #define NVIC_PERIPHID3_PERIPHID_BIT (0) - #define NVIC_PERIPHID3_PERIPHID_BITS (32) +/* PERIPHID field */ +#define NVIC_PERIPHID3_PERIPHID (0xFFFFFFFFu) +#define NVIC_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFu) +#define NVIC_PERIPHID3_PERIPHID_BIT (0) +#define NVIC_PERIPHID3_PERIPHID_BITS (32) #define NVIC_PCELLID0 *((volatile uint32_t *)0xE000EFF0u) #define NVIC_PCELLID0_REG *((volatile uint32_t *)0xE000EFF0u) #define NVIC_PCELLID0_ADDR (0xE000EFF0u) #define NVIC_PCELLID0_RESET (0x0000000Du) - /* PCELLID field */ - #define NVIC_PCELLID0_PCELLID (0xFFFFFFFFu) - #define NVIC_PCELLID0_PCELLID_MASK (0xFFFFFFFFu) - #define NVIC_PCELLID0_PCELLID_BIT (0) - #define NVIC_PCELLID0_PCELLID_BITS (32) +/* PCELLID field */ +#define NVIC_PCELLID0_PCELLID (0xFFFFFFFFu) +#define NVIC_PCELLID0_PCELLID_MASK (0xFFFFFFFFu) +#define NVIC_PCELLID0_PCELLID_BIT (0) +#define NVIC_PCELLID0_PCELLID_BITS (32) #define NVIC_PCELLID1 *((volatile uint32_t *)0xE000EFF4u) #define NVIC_PCELLID1_REG *((volatile uint32_t *)0xE000EFF4u) #define NVIC_PCELLID1_ADDR (0xE000EFF4u) #define NVIC_PCELLID1_RESET (0x000000E0u) - /* PCELLID field */ - #define NVIC_PCELLID1_PCELLID (0xFFFFFFFFu) - #define NVIC_PCELLID1_PCELLID_MASK (0xFFFFFFFFu) - #define NVIC_PCELLID1_PCELLID_BIT (0) - #define NVIC_PCELLID1_PCELLID_BITS (32) +/* PCELLID field */ +#define NVIC_PCELLID1_PCELLID (0xFFFFFFFFu) +#define NVIC_PCELLID1_PCELLID_MASK (0xFFFFFFFFu) +#define NVIC_PCELLID1_PCELLID_BIT (0) +#define NVIC_PCELLID1_PCELLID_BITS (32) #define NVIC_PCELLID2 *((volatile uint32_t *)0xE000EFF8u) #define NVIC_PCELLID2_REG *((volatile uint32_t *)0xE000EFF8u) #define NVIC_PCELLID2_ADDR (0xE000EFF8u) #define NVIC_PCELLID2_RESET (0x00000005u) - /* PCELLID field */ - #define NVIC_PCELLID2_PCELLID (0xFFFFFFFFu) - #define NVIC_PCELLID2_PCELLID_MASK (0xFFFFFFFFu) - #define NVIC_PCELLID2_PCELLID_BIT (0) - #define NVIC_PCELLID2_PCELLID_BITS (32) +/* PCELLID field */ +#define NVIC_PCELLID2_PCELLID (0xFFFFFFFFu) +#define NVIC_PCELLID2_PCELLID_MASK (0xFFFFFFFFu) +#define NVIC_PCELLID2_PCELLID_BIT (0) +#define NVIC_PCELLID2_PCELLID_BITS (32) #define NVIC_PCELLID3 *((volatile uint32_t *)0xE000EFFCu) #define NVIC_PCELLID3_REG *((volatile uint32_t *)0xE000EFFCu) #define NVIC_PCELLID3_ADDR (0xE000EFFCu) #define NVIC_PCELLID3_RESET (0x000000B1u) - /* PCELLID field */ - #define NVIC_PCELLID3_PCELLID (0xFFFFFFFFu) - #define NVIC_PCELLID3_PCELLID_MASK (0xFFFFFFFFu) - #define NVIC_PCELLID3_PCELLID_BIT (0) - #define NVIC_PCELLID3_PCELLID_BITS (32) +/* PCELLID field */ +#define NVIC_PCELLID3_PCELLID (0xFFFFFFFFu) +#define NVIC_PCELLID3_PCELLID_MASK (0xFFFFFFFFu) +#define NVIC_PCELLID3_PCELLID_BIT (0) +#define NVIC_PCELLID3_PCELLID_BITS (32) /* TPIU block */ #define DATA_TPIU_BASE (0xE0040000u) @@ -11159,141 +11159,141 @@ #define TPIU_SPS_REG *((volatile uint32_t *)0xE0040000u) #define TPIU_SPS_ADDR (0xE0040000u) #define TPIU_SPS_RESET (0x00000000u) - /* SPS_04 field */ - #define TPIU_SPS_SPS_04 (0x00000008u) - #define TPIU_SPS_SPS_04_MASK (0x00000008u) - #define TPIU_SPS_SPS_04_BIT (3) - #define TPIU_SPS_SPS_04_BITS (1) - /* SPS_03 field */ - #define TPIU_SPS_SPS_03 (0x00000004u) - #define TPIU_SPS_SPS_03_MASK (0x00000004u) - #define TPIU_SPS_SPS_03_BIT (2) - #define TPIU_SPS_SPS_03_BITS (1) - /* SPS_02 field */ - #define TPIU_SPS_SPS_02 (0x00000002u) - #define TPIU_SPS_SPS_02_MASK (0x00000002u) - #define TPIU_SPS_SPS_02_BIT (1) - #define TPIU_SPS_SPS_02_BITS (1) - /* SPS_01 field */ - #define TPIU_SPS_SPS_01 (0x00000001u) - #define TPIU_SPS_SPS_01_MASK (0x00000001u) - #define TPIU_SPS_SPS_01_BIT (0) - #define TPIU_SPS_SPS_01_BITS (1) +/* SPS_04 field */ +#define TPIU_SPS_SPS_04 (0x00000008u) +#define TPIU_SPS_SPS_04_MASK (0x00000008u) +#define TPIU_SPS_SPS_04_BIT (3) +#define TPIU_SPS_SPS_04_BITS (1) +/* SPS_03 field */ +#define TPIU_SPS_SPS_03 (0x00000004u) +#define TPIU_SPS_SPS_03_MASK (0x00000004u) +#define TPIU_SPS_SPS_03_BIT (2) +#define TPIU_SPS_SPS_03_BITS (1) +/* SPS_02 field */ +#define TPIU_SPS_SPS_02 (0x00000002u) +#define TPIU_SPS_SPS_02_MASK (0x00000002u) +#define TPIU_SPS_SPS_02_BIT (1) +#define TPIU_SPS_SPS_02_BITS (1) +/* SPS_01 field */ +#define TPIU_SPS_SPS_01 (0x00000001u) +#define TPIU_SPS_SPS_01_MASK (0x00000001u) +#define TPIU_SPS_SPS_01_BIT (0) +#define TPIU_SPS_SPS_01_BITS (1) #define TPIU_CPS *((volatile uint32_t *)0xE0040004u) #define TPIU_CPS_REG *((volatile uint32_t *)0xE0040004u) #define TPIU_CPS_ADDR (0xE0040004u) #define TPIU_CPS_RESET (0x00000001u) - /* CPS_04 field */ - #define TPIU_CPS_CPS_04 (0x00000008u) - #define TPIU_CPS_CPS_04_MASK (0x00000008u) - #define TPIU_CPS_CPS_04_BIT (3) - #define TPIU_CPS_CPS_04_BITS (1) - /* CPS_03 field */ - #define TPIU_CPS_CPS_03 (0x00000004u) - #define TPIU_CPS_CPS_03_MASK (0x00000004u) - #define TPIU_CPS_CPS_03_BIT (2) - #define TPIU_CPS_CPS_03_BITS (1) - /* CPS_02 field */ - #define TPIU_CPS_CPS_02 (0x00000002u) - #define TPIU_CPS_CPS_02_MASK (0x00000002u) - #define TPIU_CPS_CPS_02_BIT (1) - #define TPIU_CPS_CPS_02_BITS (1) - /* CPS_01 field */ - #define TPIU_CPS_CPS_01 (0x00000001u) - #define TPIU_CPS_CPS_01_MASK (0x00000001u) - #define TPIU_CPS_CPS_01_BIT (0) - #define TPIU_CPS_CPS_01_BITS (1) +/* CPS_04 field */ +#define TPIU_CPS_CPS_04 (0x00000008u) +#define TPIU_CPS_CPS_04_MASK (0x00000008u) +#define TPIU_CPS_CPS_04_BIT (3) +#define TPIU_CPS_CPS_04_BITS (1) +/* CPS_03 field */ +#define TPIU_CPS_CPS_03 (0x00000004u) +#define TPIU_CPS_CPS_03_MASK (0x00000004u) +#define TPIU_CPS_CPS_03_BIT (2) +#define TPIU_CPS_CPS_03_BITS (1) +/* CPS_02 field */ +#define TPIU_CPS_CPS_02 (0x00000002u) +#define TPIU_CPS_CPS_02_MASK (0x00000002u) +#define TPIU_CPS_CPS_02_BIT (1) +#define TPIU_CPS_CPS_02_BITS (1) +/* CPS_01 field */ +#define TPIU_CPS_CPS_01 (0x00000001u) +#define TPIU_CPS_CPS_01_MASK (0x00000001u) +#define TPIU_CPS_CPS_01_BIT (0) +#define TPIU_CPS_CPS_01_BITS (1) #define TPIU_COSD *((volatile uint32_t *)0xE0040010u) #define TPIU_COSD_REG *((volatile uint32_t *)0xE0040010u) #define TPIU_COSD_ADDR (0xE0040010u) #define TPIU_COSD_RESET (0x00000000u) - /* PRESCALER field */ - #define TPIU_COSD_PRESCALER (0x00001FFFu) - #define TPIU_COSD_PRESCALER_MASK (0x00001FFFu) - #define TPIU_COSD_PRESCALER_BIT (0) - #define TPIU_COSD_PRESCALER_BITS (13) +/* PRESCALER field */ +#define TPIU_COSD_PRESCALER (0x00001FFFu) +#define TPIU_COSD_PRESCALER_MASK (0x00001FFFu) +#define TPIU_COSD_PRESCALER_BIT (0) +#define TPIU_COSD_PRESCALER_BITS (13) #define TPIU_SPP *((volatile uint32_t *)0xE00400F0u) #define TPIU_SPP_REG *((volatile uint32_t *)0xE00400F0u) #define TPIU_SPP_ADDR (0xE00400F0u) #define TPIU_SPP_RESET (0x00000001u) - /* PROTOCOL field */ - #define TPIU_SPP_PROTOCOL (0x00000003u) - #define TPIU_SPP_PROTOCOL_MASK (0x00000003u) - #define TPIU_SPP_PROTOCOL_BIT (0) - #define TPIU_SPP_PROTOCOL_BITS (2) +/* PROTOCOL field */ +#define TPIU_SPP_PROTOCOL (0x00000003u) +#define TPIU_SPP_PROTOCOL_MASK (0x00000003u) +#define TPIU_SPP_PROTOCOL_BIT (0) +#define TPIU_SPP_PROTOCOL_BITS (2) #define TPIU_FFS *((volatile uint32_t *)0xE0040300u) #define TPIU_FFS_REG *((volatile uint32_t *)0xE0040300u) #define TPIU_FFS_ADDR (0xE0040300u) #define TPIU_FFS_RESET (0x00000008u) - /* FTNONSTOP field */ - #define TPIU_FFS_FTNONSTOP (0x00000008u) - #define TPIU_FFS_FTNONSTOP_MASK (0x00000008u) - #define TPIU_FFS_FTNONSTOP_BIT (3) - #define TPIU_FFS_FTNONSTOP_BITS (1) - /* TCPRESENT field */ - #define TPIU_FFS_TCPRESENT (0x00000004u) - #define TPIU_FFS_TCPRESENT_MASK (0x00000004u) - #define TPIU_FFS_TCPRESENT_BIT (2) - #define TPIU_FFS_TCPRESENT_BITS (1) - /* FTSTOPPED field */ - #define TPIU_FFS_FTSTOPPED (0x00000002u) - #define TPIU_FFS_FTSTOPPED_MASK (0x00000002u) - #define TPIU_FFS_FTSTOPPED_BIT (1) - #define TPIU_FFS_FTSTOPPED_BITS (1) - /* FLINPROG field */ - #define TPIU_FFS_FLINPROG (0x00000001u) - #define TPIU_FFS_FLINPROG_MASK (0x00000001u) - #define TPIU_FFS_FLINPROG_BIT (0) - #define TPIU_FFS_FLINPROG_BITS (1) +/* FTNONSTOP field */ +#define TPIU_FFS_FTNONSTOP (0x00000008u) +#define TPIU_FFS_FTNONSTOP_MASK (0x00000008u) +#define TPIU_FFS_FTNONSTOP_BIT (3) +#define TPIU_FFS_FTNONSTOP_BITS (1) +/* TCPRESENT field */ +#define TPIU_FFS_TCPRESENT (0x00000004u) +#define TPIU_FFS_TCPRESENT_MASK (0x00000004u) +#define TPIU_FFS_TCPRESENT_BIT (2) +#define TPIU_FFS_TCPRESENT_BITS (1) +/* FTSTOPPED field */ +#define TPIU_FFS_FTSTOPPED (0x00000002u) +#define TPIU_FFS_FTSTOPPED_MASK (0x00000002u) +#define TPIU_FFS_FTSTOPPED_BIT (1) +#define TPIU_FFS_FTSTOPPED_BITS (1) +/* FLINPROG field */ +#define TPIU_FFS_FLINPROG (0x00000001u) +#define TPIU_FFS_FLINPROG_MASK (0x00000001u) +#define TPIU_FFS_FLINPROG_BIT (0) +#define TPIU_FFS_FLINPROG_BITS (1) #define TPIU_FFC *((volatile uint32_t *)0xE0040304u) #define TPIU_FFC_REG *((volatile uint32_t *)0xE0040304u) #define TPIU_FFC_ADDR (0xE0040304u) #define TPIU_FFC_RESET (0x00000102u) - /* TRIGIN field */ - #define TPIU_FFC_TRIGIN (0x00000100u) - #define TPIU_FFC_TRIGIN_MASK (0x00000100u) - #define TPIU_FFC_TRIGIN_BIT (8) - #define TPIU_FFC_TRIGIN_BITS (1) - /* ENFCONT field */ - #define TPIU_FFC_ENFCONT (0x00000002u) - #define TPIU_FFC_ENFCONT_MASK (0x00000002u) - #define TPIU_FFC_ENFCONT_BIT (1) - #define TPIU_FFC_ENFCONT_BITS (1) +/* TRIGIN field */ +#define TPIU_FFC_TRIGIN (0x00000100u) +#define TPIU_FFC_TRIGIN_MASK (0x00000100u) +#define TPIU_FFC_TRIGIN_BIT (8) +#define TPIU_FFC_TRIGIN_BITS (1) +/* ENFCONT field */ +#define TPIU_FFC_ENFCONT (0x00000002u) +#define TPIU_FFC_ENFCONT_MASK (0x00000002u) +#define TPIU_FFC_ENFCONT_BIT (1) +#define TPIU_FFC_ENFCONT_BITS (1) #define TPIU_FSC *((volatile uint32_t *)0xE0040308u) #define TPIU_FSC_REG *((volatile uint32_t *)0xE0040308u) #define TPIU_FSC_ADDR (0xE0040308u) #define TPIU_FSC_RESET (0x00000000u) - /* FSC field */ - #define TPIU_FSC_FSC (0xFFFFFFFFu) - #define TPIU_FSC_FSC_MASK (0xFFFFFFFFu) - #define TPIU_FSC_FSC_BIT (0) - #define TPIU_FSC_FSC_BITS (32) +/* FSC field */ +#define TPIU_FSC_FSC (0xFFFFFFFFu) +#define TPIU_FSC_FSC_MASK (0xFFFFFFFFu) +#define TPIU_FSC_FSC_BIT (0) +#define TPIU_FSC_FSC_BITS (32) #define TPIU_ITATBCTR2 *((volatile uint32_t *)0xE0040EF0u) #define TPIU_ITATBCTR2_REG *((volatile uint32_t *)0xE0040EF0u) #define TPIU_ITATBCTR2_ADDR (0xE0040EF0u) #define TPIU_ITATBCTR2_RESET (0x00000000u) - /* ATREADY1 field */ - #define TPIU_ITATBCTR2_ATREADY1 (0x00000001u) - #define TPIU_ITATBCTR2_ATREADY1_MASK (0x00000001u) - #define TPIU_ITATBCTR2_ATREADY1_BIT (0) - #define TPIU_ITATBCTR2_ATREADY1_BITS (1) +/* ATREADY1 field */ +#define TPIU_ITATBCTR2_ATREADY1 (0x00000001u) +#define TPIU_ITATBCTR2_ATREADY1_MASK (0x00000001u) +#define TPIU_ITATBCTR2_ATREADY1_BIT (0) +#define TPIU_ITATBCTR2_ATREADY1_BITS (1) #define TPIU_ITATBCTR0 *((volatile uint32_t *)0xE0040EF8u) #define TPIU_ITATBCTR0_REG *((volatile uint32_t *)0xE0040EF8u) #define TPIU_ITATBCTR0_ADDR (0xE0040EF8u) #define TPIU_ITATBCTR0_RESET (0x00000000u) - /* ATREADY1 field */ - #define TPIU_ITATBCTR0_ATREADY1 (0x00000001u) - #define TPIU_ITATBCTR0_ATREADY1_MASK (0x00000001u) - #define TPIU_ITATBCTR0_ATREADY1_BIT (0) - #define TPIU_ITATBCTR0_ATREADY1_BITS (1) +/* ATREADY1 field */ +#define TPIU_ITATBCTR0_ATREADY1 (0x00000001u) +#define TPIU_ITATBCTR0_ATREADY1_MASK (0x00000001u) +#define TPIU_ITATBCTR0_ATREADY1_BIT (0) +#define TPIU_ITATBCTR0_ATREADY1_BITS (1) /* ETM block */ #define DATA_ETM_BASE (0xE0041000u) @@ -11309,261 +11309,261 @@ #define ROM_SCS_REG *((volatile uint32_t *)0xE00FF000u) #define ROM_SCS_ADDR (0xE00FF000u) #define ROM_SCS_RESET (0xFFF0F003u) - /* ADDR_OFF field */ - #define ROM_SCS_ADDR_OFF (0xFFFFF000u) - #define ROM_SCS_ADDR_OFF_MASK (0xFFFFF000u) - #define ROM_SCS_ADDR_OFF_BIT (12) - #define ROM_SCS_ADDR_OFF_BITS (20) - /* FORMAT field */ - #define ROM_SCS_FORMAT (0x00000002u) - #define ROM_SCS_FORMAT_MASK (0x00000002u) - #define ROM_SCS_FORMAT_BIT (1) - #define ROM_SCS_FORMAT_BITS (1) - /* ENTRY_PRES field */ - #define ROM_SCS_ENTRY_PRES (0x00000001u) - #define ROM_SCS_ENTRY_PRES_MASK (0x00000001u) - #define ROM_SCS_ENTRY_PRES_BIT (0) - #define ROM_SCS_ENTRY_PRES_BITS (1) +/* ADDR_OFF field */ +#define ROM_SCS_ADDR_OFF (0xFFFFF000u) +#define ROM_SCS_ADDR_OFF_MASK (0xFFFFF000u) +#define ROM_SCS_ADDR_OFF_BIT (12) +#define ROM_SCS_ADDR_OFF_BITS (20) +/* FORMAT field */ +#define ROM_SCS_FORMAT (0x00000002u) +#define ROM_SCS_FORMAT_MASK (0x00000002u) +#define ROM_SCS_FORMAT_BIT (1) +#define ROM_SCS_FORMAT_BITS (1) +/* ENTRY_PRES field */ +#define ROM_SCS_ENTRY_PRES (0x00000001u) +#define ROM_SCS_ENTRY_PRES_MASK (0x00000001u) +#define ROM_SCS_ENTRY_PRES_BIT (0) +#define ROM_SCS_ENTRY_PRES_BITS (1) #define ROM_DWT *((volatile uint32_t *)0xE00FF004u) #define ROM_DWT_REG *((volatile uint32_t *)0xE00FF004u) #define ROM_DWT_ADDR (0xE00FF004u) #define ROM_DWT_RESET (0xFFF02003u) - /* ADDR_OFF field */ - #define ROM_DWT_ADDR_OFF (0xFFFFF000u) - #define ROM_DWT_ADDR_OFF_MASK (0xFFFFF000u) - #define ROM_DWT_ADDR_OFF_BIT (12) - #define ROM_DWT_ADDR_OFF_BITS (20) - /* FORMAT field */ - #define ROM_DWT_FORMAT (0x00000002u) - #define ROM_DWT_FORMAT_MASK (0x00000002u) - #define ROM_DWT_FORMAT_BIT (1) - #define ROM_DWT_FORMAT_BITS (1) - /* ENTRY_PRES field */ - #define ROM_DWT_ENTRY_PRES (0x00000001u) - #define ROM_DWT_ENTRY_PRES_MASK (0x00000001u) - #define ROM_DWT_ENTRY_PRES_BIT (0) - #define ROM_DWT_ENTRY_PRES_BITS (1) +/* ADDR_OFF field */ +#define ROM_DWT_ADDR_OFF (0xFFFFF000u) +#define ROM_DWT_ADDR_OFF_MASK (0xFFFFF000u) +#define ROM_DWT_ADDR_OFF_BIT (12) +#define ROM_DWT_ADDR_OFF_BITS (20) +/* FORMAT field */ +#define ROM_DWT_FORMAT (0x00000002u) +#define ROM_DWT_FORMAT_MASK (0x00000002u) +#define ROM_DWT_FORMAT_BIT (1) +#define ROM_DWT_FORMAT_BITS (1) +/* ENTRY_PRES field */ +#define ROM_DWT_ENTRY_PRES (0x00000001u) +#define ROM_DWT_ENTRY_PRES_MASK (0x00000001u) +#define ROM_DWT_ENTRY_PRES_BIT (0) +#define ROM_DWT_ENTRY_PRES_BITS (1) #define ROM_FPB *((volatile uint32_t *)0xE00FF008u) #define ROM_FPB_REG *((volatile uint32_t *)0xE00FF008u) #define ROM_FPB_ADDR (0xE00FF008u) #define ROM_FPB_RESET (0xFFF03003u) - /* ADDR_OFF field */ - #define ROM_FPB_ADDR_OFF (0xFFFFF000u) - #define ROM_FPB_ADDR_OFF_MASK (0xFFFFF000u) - #define ROM_FPB_ADDR_OFF_BIT (12) - #define ROM_FPB_ADDR_OFF_BITS (20) - /* FORMAT field */ - #define ROM_FPB_FORMAT (0x00000002u) - #define ROM_FPB_FORMAT_MASK (0x00000002u) - #define ROM_FPB_FORMAT_BIT (1) - #define ROM_FPB_FORMAT_BITS (1) - /* ENTRY_PRES field */ - #define ROM_FPB_ENTRY_PRES (0x00000001u) - #define ROM_FPB_ENTRY_PRES_MASK (0x00000001u) - #define ROM_FPB_ENTRY_PRES_BIT (0) - #define ROM_FPB_ENTRY_PRES_BITS (1) +/* ADDR_OFF field */ +#define ROM_FPB_ADDR_OFF (0xFFFFF000u) +#define ROM_FPB_ADDR_OFF_MASK (0xFFFFF000u) +#define ROM_FPB_ADDR_OFF_BIT (12) +#define ROM_FPB_ADDR_OFF_BITS (20) +/* FORMAT field */ +#define ROM_FPB_FORMAT (0x00000002u) +#define ROM_FPB_FORMAT_MASK (0x00000002u) +#define ROM_FPB_FORMAT_BIT (1) +#define ROM_FPB_FORMAT_BITS (1) +/* ENTRY_PRES field */ +#define ROM_FPB_ENTRY_PRES (0x00000001u) +#define ROM_FPB_ENTRY_PRES_MASK (0x00000001u) +#define ROM_FPB_ENTRY_PRES_BIT (0) +#define ROM_FPB_ENTRY_PRES_BITS (1) #define ROM_ITM *((volatile uint32_t *)0xE00FF00Cu) #define ROM_ITM_REG *((volatile uint32_t *)0xE00FF00Cu) #define ROM_ITM_ADDR (0xE00FF00Cu) #define ROM_ITM_RESET (0xFFF01003u) - /* ADDR_OFF field */ - #define ROM_ITM_ADDR_OFF (0xFFFFF000u) - #define ROM_ITM_ADDR_OFF_MASK (0xFFFFF000u) - #define ROM_ITM_ADDR_OFF_BIT (12) - #define ROM_ITM_ADDR_OFF_BITS (20) - /* FORMAT field */ - #define ROM_ITM_FORMAT (0x00000002u) - #define ROM_ITM_FORMAT_MASK (0x00000002u) - #define ROM_ITM_FORMAT_BIT (1) - #define ROM_ITM_FORMAT_BITS (1) - /* ENTRY_PRES field */ - #define ROM_ITM_ENTRY_PRES (0x00000001u) - #define ROM_ITM_ENTRY_PRES_MASK (0x00000001u) - #define ROM_ITM_ENTRY_PRES_BIT (0) - #define ROM_ITM_ENTRY_PRES_BITS (1) +/* ADDR_OFF field */ +#define ROM_ITM_ADDR_OFF (0xFFFFF000u) +#define ROM_ITM_ADDR_OFF_MASK (0xFFFFF000u) +#define ROM_ITM_ADDR_OFF_BIT (12) +#define ROM_ITM_ADDR_OFF_BITS (20) +/* FORMAT field */ +#define ROM_ITM_FORMAT (0x00000002u) +#define ROM_ITM_FORMAT_MASK (0x00000002u) +#define ROM_ITM_FORMAT_BIT (1) +#define ROM_ITM_FORMAT_BITS (1) +/* ENTRY_PRES field */ +#define ROM_ITM_ENTRY_PRES (0x00000001u) +#define ROM_ITM_ENTRY_PRES_MASK (0x00000001u) +#define ROM_ITM_ENTRY_PRES_BIT (0) +#define ROM_ITM_ENTRY_PRES_BITS (1) #define ROM_TPIU *((volatile uint32_t *)0xE00FF010u) #define ROM_TPIU_REG *((volatile uint32_t *)0xE00FF010u) #define ROM_TPIU_ADDR (0xE00FF010u) #define ROM_TPIU_RESET (0xFFF0F003u) - /* ADDR_OFF field */ - #define ROM_TPIU_ADDR_OFF (0xFFFFF000u) - #define ROM_TPIU_ADDR_OFF_MASK (0xFFFFF000u) - #define ROM_TPIU_ADDR_OFF_BIT (12) - #define ROM_TPIU_ADDR_OFF_BITS (20) - /* FORMAT field */ - #define ROM_TPIU_FORMAT (0x00000002u) - #define ROM_TPIU_FORMAT_MASK (0x00000002u) - #define ROM_TPIU_FORMAT_BIT (1) - #define ROM_TPIU_FORMAT_BITS (1) - /* ENTRY_PRES field */ - #define ROM_TPIU_ENTRY_PRES (0x00000001u) - #define ROM_TPIU_ENTRY_PRES_MASK (0x00000001u) - #define ROM_TPIU_ENTRY_PRES_BIT (0) - #define ROM_TPIU_ENTRY_PRES_BITS (1) +/* ADDR_OFF field */ +#define ROM_TPIU_ADDR_OFF (0xFFFFF000u) +#define ROM_TPIU_ADDR_OFF_MASK (0xFFFFF000u) +#define ROM_TPIU_ADDR_OFF_BIT (12) +#define ROM_TPIU_ADDR_OFF_BITS (20) +/* FORMAT field */ +#define ROM_TPIU_FORMAT (0x00000002u) +#define ROM_TPIU_FORMAT_MASK (0x00000002u) +#define ROM_TPIU_FORMAT_BIT (1) +#define ROM_TPIU_FORMAT_BITS (1) +/* ENTRY_PRES field */ +#define ROM_TPIU_ENTRY_PRES (0x00000001u) +#define ROM_TPIU_ENTRY_PRES_MASK (0x00000001u) +#define ROM_TPIU_ENTRY_PRES_BIT (0) +#define ROM_TPIU_ENTRY_PRES_BITS (1) #define ROM_ETM *((volatile uint32_t *)0xE00FF014u) #define ROM_ETM_REG *((volatile uint32_t *)0xE00FF014u) #define ROM_ETM_ADDR (0xE00FF014u) #define ROM_ETM_RESET (0xFFF0F002u) - /* ADDR_OFF field */ - #define ROM_ETM_ADDR_OFF (0xFFFFF000u) - #define ROM_ETM_ADDR_OFF_MASK (0xFFFFF000u) - #define ROM_ETM_ADDR_OFF_BIT (12) - #define ROM_ETM_ADDR_OFF_BITS (20) - /* FORMAT field */ - #define ROM_ETM_FORMAT (0x00000002u) - #define ROM_ETM_FORMAT_MASK (0x00000002u) - #define ROM_ETM_FORMAT_BIT (1) - #define ROM_ETM_FORMAT_BITS (1) - /* ENTRY_PRES field */ - #define ROM_ETM_ENTRY_PRES (0x00000001u) - #define ROM_ETM_ENTRY_PRES_MASK (0x00000001u) - #define ROM_ETM_ENTRY_PRES_BIT (0) - #define ROM_ETM_ENTRY_PRES_BITS (1) +/* ADDR_OFF field */ +#define ROM_ETM_ADDR_OFF (0xFFFFF000u) +#define ROM_ETM_ADDR_OFF_MASK (0xFFFFF000u) +#define ROM_ETM_ADDR_OFF_BIT (12) +#define ROM_ETM_ADDR_OFF_BITS (20) +/* FORMAT field */ +#define ROM_ETM_FORMAT (0x00000002u) +#define ROM_ETM_FORMAT_MASK (0x00000002u) +#define ROM_ETM_FORMAT_BIT (1) +#define ROM_ETM_FORMAT_BITS (1) +/* ENTRY_PRES field */ +#define ROM_ETM_ENTRY_PRES (0x00000001u) +#define ROM_ETM_ENTRY_PRES_MASK (0x00000001u) +#define ROM_ETM_ENTRY_PRES_BIT (0) +#define ROM_ETM_ENTRY_PRES_BITS (1) #define ROM_END *((volatile uint32_t *)0xE00FF018u) #define ROM_END_REG *((volatile uint32_t *)0xE00FF018u) #define ROM_END_ADDR (0xE00FF018u) #define ROM_END_RESET (0x00000000u) - /* END field */ - #define ROM_END_END (0xFFFFFFFFu) - #define ROM_END_END_MASK (0xFFFFFFFFu) - #define ROM_END_END_BIT (0) - #define ROM_END_END_BITS (32) +/* END field */ +#define ROM_END_END (0xFFFFFFFFu) +#define ROM_END_END_MASK (0xFFFFFFFFu) +#define ROM_END_END_BIT (0) +#define ROM_END_END_BITS (32) #define ROM_MEMTYPE *((volatile uint32_t *)0xE00FFFCCu) #define ROM_MEMTYPE_REG *((volatile uint32_t *)0xE00FFFCCu) #define ROM_MEMTYPE_ADDR (0xE00FFFCCu) #define ROM_MEMTYPE_RESET (0x00000001u) - /* MEMTYPE field */ - #define ROM_MEMTYPE_MEMTYPE (0x00000001u) - #define ROM_MEMTYPE_MEMTYPE_MASK (0x00000001u) - #define ROM_MEMTYPE_MEMTYPE_BIT (0) - #define ROM_MEMTYPE_MEMTYPE_BITS (1) +/* MEMTYPE field */ +#define ROM_MEMTYPE_MEMTYPE (0x00000001u) +#define ROM_MEMTYPE_MEMTYPE_MASK (0x00000001u) +#define ROM_MEMTYPE_MEMTYPE_BIT (0) +#define ROM_MEMTYPE_MEMTYPE_BITS (1) #define ROM_PID4 *((volatile uint32_t *)0xE00FFFD0u) #define ROM_PID4_REG *((volatile uint32_t *)0xE00FFFD0u) #define ROM_PID4_ADDR (0xE00FFFD0u) #define ROM_PID4_RESET (0x00000000u) - /* PID field */ - #define ROM_PID4_PID (0x0000000Fu) - #define ROM_PID4_PID_MASK (0x0000000Fu) - #define ROM_PID4_PID_BIT (0) - #define ROM_PID4_PID_BITS (4) +/* PID field */ +#define ROM_PID4_PID (0x0000000Fu) +#define ROM_PID4_PID_MASK (0x0000000Fu) +#define ROM_PID4_PID_BIT (0) +#define ROM_PID4_PID_BITS (4) #define ROM_PID5 *((volatile uint32_t *)0xE00FFFD4u) #define ROM_PID5_REG *((volatile uint32_t *)0xE00FFFD4u) #define ROM_PID5_ADDR (0xE00FFFD4u) #define ROM_PID5_RESET (0x00000000u) - /* PID field */ - #define ROM_PID5_PID (0x0000000Fu) - #define ROM_PID5_PID_MASK (0x0000000Fu) - #define ROM_PID5_PID_BIT (0) - #define ROM_PID5_PID_BITS (4) +/* PID field */ +#define ROM_PID5_PID (0x0000000Fu) +#define ROM_PID5_PID_MASK (0x0000000Fu) +#define ROM_PID5_PID_BIT (0) +#define ROM_PID5_PID_BITS (4) #define ROM_PID6 *((volatile uint32_t *)0xE00FFFD8u) #define ROM_PID6_REG *((volatile uint32_t *)0xE00FFFD8u) #define ROM_PID6_ADDR (0xE00FFFD8u) #define ROM_PID6_RESET (0x00000000u) - /* PID field */ - #define ROM_PID6_PID (0x0000000Fu) - #define ROM_PID6_PID_MASK (0x0000000Fu) - #define ROM_PID6_PID_BIT (0) - #define ROM_PID6_PID_BITS (4) +/* PID field */ +#define ROM_PID6_PID (0x0000000Fu) +#define ROM_PID6_PID_MASK (0x0000000Fu) +#define ROM_PID6_PID_BIT (0) +#define ROM_PID6_PID_BITS (4) #define ROM_PID7 *((volatile uint32_t *)0xE00FFFDCu) #define ROM_PID7_REG *((volatile uint32_t *)0xE00FFFDCu) #define ROM_PID7_ADDR (0xE00FFFDCu) #define ROM_PID7_RESET (0x00000000u) - /* PID field */ - #define ROM_PID7_PID (0x0000000Fu) - #define ROM_PID7_PID_MASK (0x0000000Fu) - #define ROM_PID7_PID_BIT (0) - #define ROM_PID7_PID_BITS (4) +/* PID field */ +#define ROM_PID7_PID (0x0000000Fu) +#define ROM_PID7_PID_MASK (0x0000000Fu) +#define ROM_PID7_PID_BIT (0) +#define ROM_PID7_PID_BITS (4) #define ROM_PID0 *((volatile uint32_t *)0xE00FFFE0u) #define ROM_PID0_REG *((volatile uint32_t *)0xE00FFFE0u) #define ROM_PID0_ADDR (0xE00FFFE0u) #define ROM_PID0_RESET (0x00000000u) - /* PID field */ - #define ROM_PID0_PID (0x0000000Fu) - #define ROM_PID0_PID_MASK (0x0000000Fu) - #define ROM_PID0_PID_BIT (0) - #define ROM_PID0_PID_BITS (4) +/* PID field */ +#define ROM_PID0_PID (0x0000000Fu) +#define ROM_PID0_PID_MASK (0x0000000Fu) +#define ROM_PID0_PID_BIT (0) +#define ROM_PID0_PID_BITS (4) #define ROM_PID1 *((volatile uint32_t *)0xE00FFFE4u) #define ROM_PID1_REG *((volatile uint32_t *)0xE00FFFE4u) #define ROM_PID1_ADDR (0xE00FFFE4u) #define ROM_PID1_RESET (0x00000000u) - /* PID field */ - #define ROM_PID1_PID (0x0000000Fu) - #define ROM_PID1_PID_MASK (0x0000000Fu) - #define ROM_PID1_PID_BIT (0) - #define ROM_PID1_PID_BITS (4) +/* PID field */ +#define ROM_PID1_PID (0x0000000Fu) +#define ROM_PID1_PID_MASK (0x0000000Fu) +#define ROM_PID1_PID_BIT (0) +#define ROM_PID1_PID_BITS (4) #define ROM_PID2 *((volatile uint32_t *)0xE00FFFE8u) #define ROM_PID2_REG *((volatile uint32_t *)0xE00FFFE8u) #define ROM_PID2_ADDR (0xE00FFFE8u) #define ROM_PID2_RESET (0x00000000u) - /* PID field */ - #define ROM_PID2_PID (0x0000000Fu) - #define ROM_PID2_PID_MASK (0x0000000Fu) - #define ROM_PID2_PID_BIT (0) - #define ROM_PID2_PID_BITS (4) +/* PID field */ +#define ROM_PID2_PID (0x0000000Fu) +#define ROM_PID2_PID_MASK (0x0000000Fu) +#define ROM_PID2_PID_BIT (0) +#define ROM_PID2_PID_BITS (4) #define ROM_PID3 *((volatile uint32_t *)0xE00FFFECu) #define ROM_PID3_REG *((volatile uint32_t *)0xE00FFFECu) #define ROM_PID3_ADDR (0xE00FFFECu) #define ROM_PID3_RESET (0x00000000u) - /* PID field */ - #define ROM_PID3_PID (0x0000000Fu) - #define ROM_PID3_PID_MASK (0x0000000Fu) - #define ROM_PID3_PID_BIT (0) - #define ROM_PID3_PID_BITS (4) +/* PID field */ +#define ROM_PID3_PID (0x0000000Fu) +#define ROM_PID3_PID_MASK (0x0000000Fu) +#define ROM_PID3_PID_BIT (0) +#define ROM_PID3_PID_BITS (4) #define ROM_CID0 *((volatile uint32_t *)0xE00FFFF0u) #define ROM_CID0_REG *((volatile uint32_t *)0xE00FFFF0u) #define ROM_CID0_ADDR (0xE00FFFF0u) #define ROM_CID0_RESET (0x0000000Du) - /* CID field */ - #define ROM_CID0_CID (0x000000FFu) - #define ROM_CID0_CID_MASK (0x000000FFu) - #define ROM_CID0_CID_BIT (0) - #define ROM_CID0_CID_BITS (8) +/* CID field */ +#define ROM_CID0_CID (0x000000FFu) +#define ROM_CID0_CID_MASK (0x000000FFu) +#define ROM_CID0_CID_BIT (0) +#define ROM_CID0_CID_BITS (8) #define ROM_CID1 *((volatile uint32_t *)0xE00FFFF4u) #define ROM_CID1_REG *((volatile uint32_t *)0xE00FFFF4u) #define ROM_CID1_ADDR (0xE00FFFF4u) #define ROM_CID1_RESET (0x00000010u) - /* CID field */ - #define ROM_CID1_CID (0x000000FFu) - #define ROM_CID1_CID_MASK (0x000000FFu) - #define ROM_CID1_CID_BIT (0) - #define ROM_CID1_CID_BITS (8) +/* CID field */ +#define ROM_CID1_CID (0x000000FFu) +#define ROM_CID1_CID_MASK (0x000000FFu) +#define ROM_CID1_CID_BIT (0) +#define ROM_CID1_CID_BITS (8) #define ROM_CID2 *((volatile uint32_t *)0xE00FFFF8u) #define ROM_CID2_REG *((volatile uint32_t *)0xE00FFFF8u) #define ROM_CID2_ADDR (0xE00FFFF8u) #define ROM_CID2_RESET (0x00000005u) - /* CID field */ - #define ROM_CID2_CID (0x000000FFu) - #define ROM_CID2_CID_MASK (0x000000FFu) - #define ROM_CID2_CID_BIT (0) - #define ROM_CID2_CID_BITS (8) +/* CID field */ +#define ROM_CID2_CID (0x000000FFu) +#define ROM_CID2_CID_MASK (0x000000FFu) +#define ROM_CID2_CID_BIT (0) +#define ROM_CID2_CID_BITS (8) #define ROM_CID3 *((volatile uint32_t *)0xE00FFFFCu) #define ROM_CID3_REG *((volatile uint32_t *)0xE00FFFFCu) #define ROM_CID3_ADDR (0xE00FFFFCu) #define ROM_CID3_RESET (0x000000B1u) - /* CID field */ - #define ROM_CID3_CID (0x000000FFu) - #define ROM_CID3_CID_MASK (0x000000FFu) - #define ROM_CID3_CID_BIT (0) - #define ROM_CID3_CID_BITS (8) +/* CID field */ +#define ROM_CID3_CID (0x000000FFu) +#define ROM_CID3_CID_MASK (0x000000FFu) +#define ROM_CID3_CID_BIT (0) +#define ROM_CID3_CID_BITS (8) /* VENDOR block */ #define DATA_VENDOR_BASE (0xE0100000u) @@ -11571,5 +11571,5 @@ #define DATA_VENDOR_SIZE (DATA_VENDOR_END - DATA_VENDOR_BASE + 1) /*---------------------------------------------------------------------------*/ -#endif /*REGS_H_*/ +#endif /*REGS_H_*/ /*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/rtimer-arch.c b/cpu/arm/stm32l152/rtimer-arch.c index 33922703e..cd786969c 100644 --- a/cpu/arm/stm32l152/rtimer-arch.c +++ b/cpu/arm/stm32l152/rtimer-arch.c @@ -1,104 +1,105 @@ -/* -* Copyright (c) 2012, STMicroelectronics. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the Institute nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -* -*/ -/*---------------------------------------------------------------------------*/ -#include "contiki.h" -#include "platform-conf.h" - -#include "sys/rtimer.h" -#include "sys/process.h" -#include "dev/watchdog.h" - -#include "stm32l1xx.h" -#include "stm32l1xx_hal_gpio.h" -#include "stm32l1xx_hal_rcc.h" -#include "stm32l1xx_hal_tim.h" -#include "stm32l1xx_hal_cortex.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -volatile uint32_t rtimer_clock = 0uL; -/*---------------------------------------------------------------------------*/ -st_lib_tim_handle_typedef htim2; -/*---------------------------------------------------------------------------*/ -void st_lib_tim2_irq_handler(void) -{ - /* clear interrupt pending flag */ - st_lib_hal_tim_clear_it(&htim2, TIM_IT_UPDATE); - - rtimer_clock++; -} -/*---------------------------------------------------------------------------*/ -void rtimer_arch_init(void) -{ - st_lib_tim_clock_config_typedef s_clock_source_config; - st_lib_tim_oc_init_typedef s_config_oc; - - st_lib_tim2_clk_enable(); - htim2.Instance = TIM2; - htim2.Init.Prescaler = PRESCALER; - htim2.Init.CounterMode = TIM_COUNTERMODE_UP; - htim2.Init.Period = 1; - - st_lib_hal_tim_base_init(&htim2); - st_lib_hal_tim_base_start_it(&htim2); - - s_clock_source_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - st_lib_hal_tim_config_clock_source(&htim2, &s_clock_source_config); - - st_lib_hal_tim_oc_init(&htim2); - - s_config_oc.OCMode = TIM_OCMODE_TIMING; - s_config_oc.Pulse = 0; - s_config_oc.OCPolarity = TIM_OCPOLARITY_HIGH; - st_lib_hal_tim_oc_config_channel(&htim2, &s_config_oc, TIM_CHANNEL_1); - - - st_lib_hal_tim_clear_flag(&htim2, TIM_FLAG_UPDATE); - - /* Enable TIM2 Update interrupt */ - st_lib_hal_tim_enable_it(&htim2, TIM_IT_UPDATE); - - st_lib_hal_tim_enable(&htim2); - - st_lib_hal_nvic_set_priority((st_lib_irq_n_type) TIM2_IRQn, 0, 0); - st_lib_hal_nvic_enable_irq((st_lib_irq_n_type)(TIM2_IRQn)); - -} -/*---------------------------------------------------------------------------*/ -rtimer_clock_t rtimer_arch_now(void) -{ - return rtimer_clock; -} -/*---------------------------------------------------------------------------*/ -void rtimer_arch_schedule(rtimer_clock_t t) -{ - -} -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#include "contiki.h" +#include "platform-conf.h" + +#include "sys/rtimer.h" +#include "sys/process.h" +#include "dev/watchdog.h" + +#include "stm32l1xx.h" +#include "stm32l1xx_hal_gpio.h" +#include "stm32l1xx_hal_rcc.h" +#include "stm32l1xx_hal_tim.h" +#include "stm32l1xx_hal_cortex.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +volatile uint32_t rtimer_clock = 0uL; +/*---------------------------------------------------------------------------*/ +st_lib_tim_handle_typedef htim2; +/*---------------------------------------------------------------------------*/ +void +st_lib_tim2_irq_handler(void) +{ + /* clear interrupt pending flag */ + st_lib_hal_tim_clear_it(&htim2, TIM_IT_UPDATE); + + rtimer_clock++; +} +/*---------------------------------------------------------------------------*/ +void +rtimer_arch_init(void) +{ + st_lib_tim_clock_config_typedef s_clock_source_config; + st_lib_tim_oc_init_typedef s_config_oc; + + st_lib_tim2_clk_enable(); + htim2.Instance = TIM2; + htim2.Init.Prescaler = PRESCALER; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 1; + + st_lib_hal_tim_base_init(&htim2); + st_lib_hal_tim_base_start_it(&htim2); + + s_clock_source_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + st_lib_hal_tim_config_clock_source(&htim2, &s_clock_source_config); + + st_lib_hal_tim_oc_init(&htim2); + + s_config_oc.OCMode = TIM_OCMODE_TIMING; + s_config_oc.Pulse = 0; + s_config_oc.OCPolarity = TIM_OCPOLARITY_HIGH; + st_lib_hal_tim_oc_config_channel(&htim2, &s_config_oc, TIM_CHANNEL_1); + + st_lib_hal_tim_clear_flag(&htim2, TIM_FLAG_UPDATE); + + /* Enable TIM2 Update interrupt */ + st_lib_hal_tim_enable_it(&htim2, TIM_IT_UPDATE); + + st_lib_hal_tim_enable(&htim2); + + st_lib_hal_nvic_set_priority((st_lib_irq_n_type)TIM2_IRQn, 0, 0); + st_lib_hal_nvic_enable_irq((st_lib_irq_n_type)(TIM2_IRQn)); +} +/*---------------------------------------------------------------------------*/ +rtimer_clock_t +rtimer_arch_now(void) +{ + return rtimer_clock; +} +/*---------------------------------------------------------------------------*/ +void +rtimer_arch_schedule(rtimer_clock_t t) +{ +} +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/rtimer-arch.h b/cpu/arm/stm32l152/rtimer-arch.h index 1f8dd08fc..555c1f6df 100644 --- a/cpu/arm/stm32l152/rtimer-arch.h +++ b/cpu/arm/stm32l152/rtimer-arch.h @@ -1,45 +1,45 @@ -/* - * Copyright (c) 2010, STMicroelectronics. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the Contiki OS - * - */ -/*---------------------------------------------------------------------------*/ -#ifndef __RTIMER_ARCH_H__ -#define __RTIMER_ARCH_H__ -/*---------------------------------------------------------------------------*/ -#include "contiki-conf.h" -#include "sys/clock.h" -/*---------------------------------------------------------------------------*/ -rtimer_clock_t rtimer_arch_now(void); -void rtimer_arch_disable_irq(void); -void rtimer_arch_enable_irq(void); -/*---------------------------------------------------------------------------*/ -#endif /* __RTIMER_ARCH_H__ */ -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + */ +/*---------------------------------------------------------------------------*/ +#ifndef __RTIMER_ARCH_H__ +#define __RTIMER_ARCH_H__ +/*---------------------------------------------------------------------------*/ +#include "contiki-conf.h" +#include "sys/clock.h" +/*---------------------------------------------------------------------------*/ +rtimer_clock_t rtimer_arch_now(void); +void rtimer_arch_disable_irq(void); +void rtimer_arch_enable_irq(void); +/*---------------------------------------------------------------------------*/ +#endif /* __RTIMER_ARCH_H__ */ +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/syscalls.c b/cpu/arm/stm32l152/syscalls.c new file mode 100644 index 000000000..8390ecc99 --- /dev/null +++ b/cpu/arm/stm32l152/syscalls.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/* + * Function implementation taken and adapted from: + * cpu/stm32w108/e_stdio/src/syscalls.c + */ +/*---------------------------------------------------------------------------*/ +#include +#include +/*---------------------------------------------------------------------------*/ +extern int errno; +/*---------------------------------------------------------------------------*/ +/* Register name faking - works in collusion with the linker. */ +register char *stack_ptr asm ("sp"); +/*---------------------------------------------------------------------------*/ +caddr_t +_sbrk(int incr) +{ + extern char end; /* Defined by the linker */ + static char *heap_end; + char *prev_heap_end; + + if(heap_end == 0) { + heap_end = &end; + } + prev_heap_end = heap_end; + if(heap_end + incr > stack_ptr) { + _write(1, "Heap and stack collision\n", 25); + /*abort ();*/ + errno = ENOMEM; + return (caddr_t)-1; + } + + heap_end += incr; + return (caddr_t)prev_heap_end; +} +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/stm32l152/sysmem.c b/cpu/arm/stm32l152/sysmem.c deleted file mode 100644 index 384407fc8..000000000 --- a/cpu/arm/stm32l152/sysmem.c +++ /dev/null @@ -1,67 +0,0 @@ -/** -***************************************************************************** -** -** File : sysmem.c -** -** Author : Ac6 -** -** Abstract : System Workbench Minimal System Memory calls file -** -** For more information about which c-functions -** need which of these lowlevel functions -** please consult the Newlib libc-manual -** -** Environment : System Workbench for MCU -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright System Workbench for MCU. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. System Workbench for MCU permit registered System Workbench(R) users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the System Workbench for MCU toolchain. -** -***************************************************************************** -*/ - -/* Includes */ -/*---------------------------------------------------------------------------*/ -#include -#include -/*---------------------------------------------------------------------------*/ -/* Variables */ -extern int errno; -register char * stack_ptr asm("sp"); -/*---------------------------------------------------------------------------*/ -/* Functions */ - -/*---------------------------------------------------------------------------*/ -/** - _sbrk - Increase program data space. Malloc and related functions depend on this -**/ -caddr_t _sbrk(int incr) -{ - extern char end asm("end"); - static char *heap_end; - char *prev_heap_end; - - if (heap_end == 0) { - heap_end = &end; - } - - prev_heap_end = heap_end; - if (heap_end + incr > stack_ptr) { - errno = ENOMEM; - return (caddr_t) -1; - } - - heap_end += incr; - - return (caddr_t) prev_heap_end; -} -/*---------------------------------------------------------------------------*/ - diff --git a/cpu/arm/stm32l152/uart.c b/cpu/arm/stm32l152/uart.c index 74c577764..4f79465e4 100644 --- a/cpu/arm/stm32l152/uart.c +++ b/cpu/arm/stm32l152/uart.c @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file cpu/arm/stm32l152/uart.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Source file for UART read/write -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ #include "console.h" #include @@ -43,8 +37,8 @@ _write(int handle, const unsigned char *buffer, size_t size) { int data_idx; - for (data_idx = 0; data_idx < size; data_idx++) { - __io_putchar( *buffer++ ); + for(data_idx = 0; data_idx < size; data_idx++) { + __io_putchar(*buffer++); } return size; } diff --git a/cpu/arm/stm32l152/watchdog.c b/cpu/arm/stm32l152/watchdog.c index b5efb2663..ab0193ac4 100644 --- a/cpu/arm/stm32l152/watchdog.c +++ b/cpu/arm/stm32l152/watchdog.c @@ -1,66 +1,61 @@ -/* - * Copyright (c) 2010, STMicroelectronics. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the Contiki OS - * - */ -/*---------------------------------------------------------------------------*/ -#include -#include "dev/watchdog.h" -/*---------------------------------------------------------------------------*/ -void -watchdog_init(void) -{ - -} -/*---------------------------------------------------------------------------*/ -void -watchdog_start(void) -{ - -} -/*---------------------------------------------------------------------------*/ -void -watchdog_periodic(void) -{ - -} -/*---------------------------------------------------------------------------*/ -void -watchdog_stop(void) -{ - -} -/*---------------------------------------------------------------------------*/ -void -watchdog_reboot(void) -{ - -} -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki OS + * + */ +/*---------------------------------------------------------------------------*/ +#include +#include "dev/watchdog.h" +/*---------------------------------------------------------------------------*/ +void +watchdog_init(void) +{ +} +/*---------------------------------------------------------------------------*/ +void +watchdog_start(void) +{ +} +/*---------------------------------------------------------------------------*/ +void +watchdog_periodic(void) +{ +} +/*---------------------------------------------------------------------------*/ +void +watchdog_stop(void) +{ +} +/*---------------------------------------------------------------------------*/ +void +watchdog_reboot(void) +{ +} +/*---------------------------------------------------------------------------*/ diff --git a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c index 0884e3da8..c8c3df6db 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c +++ b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c @@ -1,39 +1,39 @@ /** -****************************************************************************** -* @file contiki-spirit1-main.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Contiki main file for SPIRIT1 platform -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ + ****************************************************************************** + * @file contiki-spirit1-main.c + * @author System LAB + * @version V1.0.0 + * @date 17-June-2015 + * @brief Contiki main file for SPIRIT1 platform + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ /** * \file * A very simple Contiki application showing sensor values for ST Nucleo @@ -66,7 +66,7 @@ #define DEBUG DEBUG_PRINT #include "net/ip/uip-debug.h" -#define PRINT_INTERVAL 5*CLOCK_SECOND +#define PRINT_INTERVAL 5 * CLOCK_SECOND /*---------------------------------------------------------------------------*/ PROCESS(sensor_demo_process, "Sensor demo process"); @@ -76,7 +76,7 @@ PROCESS_THREAD(sensor_demo_process, ev, data) { static struct etimer etimer; static unsigned long _button_pressed; - static int sensor_value = 0; + static int sensor_value = 0; PROCESS_BEGIN(); PROCESS_PAUSE(); @@ -94,64 +94,61 @@ PROCESS_THREAD(sensor_demo_process, ev, data) SENSORS_ACTIVATE(gyroscope_sensor); #endif - while(1) - { + while(1) { etimer_set(&etimer, PRINT_INTERVAL); - + PROCESS_WAIT_EVENT(); - if (ev == sensors_event && data == &button_sensor) - { + if(ev == sensors_event && data == &button_sensor) { printf("Sensor event detected: Button Pressed.\n\n"); printf("Toggling Leds\n"); _button_pressed++; leds_toggle(LEDS_ALL); } - - printf("Button state:\t%s (pressed %lu times)\n", button_sensor.value(0)?"Released":"Pressed", - _button_pressed); + printf("Button state:\t%s (pressed %lu times)\n", button_sensor.value(0) ? "Released" : "Pressed", + _button_pressed); #ifdef COMPILE_SENSORS - printf("LEDs status:\tRED:n/a GREEN:%s\n", leds_get()&LEDS_GREEN?"on":"off"); + printf("LEDs status:\tRED:n/a GREEN:%s\n", leds_get() & LEDS_GREEN ? "on" : "off"); #else - printf("LEDs status:\tRED:%s GREEN:%s\n", leds_get()&LEDS_RED?"on":"off", - leds_get()&LEDS_GREEN?"on":"off"); + printf("LEDs status:\tRED:%s GREEN:%s\n", leds_get() & LEDS_RED ? "on" : "off", + leds_get() & LEDS_GREEN ? "on" : "off"); #endif /*COMPILE_SENSORS*/ sensor_value = radio_sensor.value(RADIO_SENSOR_LAST_PACKET); - printf("Radio (RSSI):\t%d.%d dBm\n", sensor_value/10, ABS_VALUE(sensor_value)%10); + printf("Radio (RSSI):\t%d.%d dBm\n", sensor_value / 10, ABS_VALUE(sensor_value) % 10); printf("Radio (LQI):\t%d\n", radio_sensor.value(RADIO_SENSOR_LAST_VALUE)); #ifdef COMPILE_SENSORS sensor_value = temperature_sensor.value(0); - printf("Temperature:\t%d.%d C\n", sensor_value/10, ABS_VALUE(sensor_value)%10); + printf("Temperature:\t%d.%d C\n", sensor_value / 10, ABS_VALUE(sensor_value) % 10); sensor_value = humidity_sensor.value(0); - printf("Humidity:\t%d.%d rH\n", sensor_value/10, ABS_VALUE(sensor_value)%10); + printf("Humidity:\t%d.%d rH\n", sensor_value / 10, ABS_VALUE(sensor_value) % 10); sensor_value = pressure_sensor.value(0); - printf("Pressure:\t%d.%d mbar\n", sensor_value/10, ABS_VALUE(sensor_value)%10); + printf("Pressure:\t%d.%d mbar\n", sensor_value / 10, ABS_VALUE(sensor_value) % 10); - /* NOTE: this demo uses the mapping of ST Nucleo sensors on Contiki sensor API. - * For a real use case of sensors like acceleration, magneto and gyroscope, - * it is better to directly call the ST lib to get the three value (X/Y/Z) - * at once. - */ + /* NOTE: this demo uses the mapping of ST Nucleo sensors on Contiki sensor API. + * For a real use case of sensors like acceleration, magneto and gyroscope, + * it is better to directly call the ST lib to get the three value (X/Y/Z) + * at once. + */ printf("Magneto:\t%d/%d/%d (X/Y/Z) mgauss\n", magneto_sensor.value(X_AXIS), - magneto_sensor.value(Y_AXIS), - magneto_sensor.value(Z_AXIS)); + magneto_sensor.value(Y_AXIS), + magneto_sensor.value(Z_AXIS)); printf("Acceleration:\t%d/%d/%d (X/Y/Z) mg\n", acceleration_sensor.value(X_AXIS), - acceleration_sensor.value(Y_AXIS), - acceleration_sensor.value(Z_AXIS)); + acceleration_sensor.value(Y_AXIS), + acceleration_sensor.value(Z_AXIS)); printf("Gyroscope:\t%d/%d/%d (X/Y/Z) mdps\n", gyroscope_sensor.value(X_AXIS), - gyroscope_sensor.value(Y_AXIS), - gyroscope_sensor.value(Z_AXIS)); + gyroscope_sensor.value(Y_AXIS), + gyroscope_sensor.value(Z_AXIS)); #endif - printf ("\n"); + printf("\n"); } - + PROCESS_END(); } /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/contiki-conf.h b/platform/stm32nucleo-spirit1/contiki-conf.h index d6c5e87ad..14baa8d97 100644 --- a/platform/stm32nucleo-spirit1/contiki-conf.h +++ b/platform/stm32nucleo-spirit1/contiki-conf.h @@ -1,152 +1,140 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/contiki-conf.h -* @author System LAB -* @version V1.0.0 -* @date 17-May-2015 -* @brief Contiki configuration parameters -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/*---------------------------------------------------------------------------*/ -#ifndef __CONTIKI_CONF_H__ -#define __CONTIKI_CONF_H__ -/*---------------------------------------------------------------------------*/ -#include "platform-conf.h" -/*---------------------------------------------------------------------------*/ -#define SLIP_BRIDGE_CONF_NO_PUTCHAR 1 - -#define NETSTACK_CONF_RDC_CHANNEL_CHECK_RATE 8 -#define NULLRDC_CONF_802154_AUTOACK 0 -#define NETSTACK_CONF_FRAMER framer_802154 -#define NETSTACK_CONF_NETWORK sicslowpan_driver - -#undef NETSTACK_CONF_RDC -#define NETSTACK_CONF_RDC nullrdc_driver -#define NETSTACK_RDC_HEADER_LEN 0 - -#undef NETSTACK_CONF_MAC -#define NETSTACK_CONF_MAC csma_driver -#define NETSTACK_MAC_HEADER_LEN 0 - -#define SICSLOWPAN_CONF_MAC_MAX_PAYLOAD \ - (NETSTACK_RADIO_MAX_PAYLOAD_LEN - NETSTACK_MAC_HEADER_LEN - \ - NETSTACK_RDC_HEADER_LEN ) - -#define RIMESTATS_CONF_ENABLED 0 -#define RIMESTATS_CONF_ON 0 - - -/* Network setup for IPv6 */ - -#define CXMAC_CONF_ANNOUNCEMENTS 0 - - -/* A trick to resolve a compilation error with IAR. */ -#ifdef __ICCARM__ -#define UIP_CONF_DS6_AADDR_NBU 1 -#endif - -/* radio driver blocks until ACK is received */ -#define NULLRDC_CONF_ACK_WAIT_TIME (0) -#define CONTIKIMAC_CONF_BROADCAST_RATE_LIMIT 0 -#define IEEE802154_CONF_PANID 0xABCD - -#define AODV_COMPLIANCE - -#define WITH_ASCII 1 - -#define PROCESS_CONF_NUMEVENTS 8 -#define PROCESS_CONF_STATS 1 -/*#define PROCESS_CONF_FASTPOLL 4*/ - - -#define LINKADDR_CONF_SIZE 8 - -#define UIP_CONF_LL_802154 1 -#define UIP_CONF_LLH_LEN 0 - -#define UIP_CONF_ROUTER 1 - -/* configure number of neighbors and routes */ -#ifndef UIP_CONF_DS6_ROUTE_NBU -#define UIP_CONF_DS6_ROUTE_NBU 30 -#endif /* UIP_CONF_DS6_ROUTE_NBU */ - -#define UIP_CONF_ND6_SEND_RA 0 -#define UIP_CONF_ND6_REACHABLE_TIME 600000 //90000// 600000 -#define UIP_CONF_ND6_RETRANS_TIMER 10000 - - -#define UIP_CONF_IPV6 1 -#ifndef UIP_CONF_IPV6_QUEUE_PKT -#define UIP_CONF_IPV6_QUEUE_PKT 0 -#endif /* UIP_CONF_IPV6_QUEUE_PKT */ -#define UIP_CONF_IP_FORWARD 0 -#ifndef UIP_CONF_BUFFER_SIZE -#define UIP_CONF_BUFFER_SIZE 280 -//#define UIP_CONF_BUFFER_SIZE 600 -#endif - -#define SICSLOWPAN_CONF_MAXAGE 4 -#define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS 2 - - -#ifndef SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS -#define SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS 5 -#endif /* SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS */ - -#define UIP_CONF_ICMP_DEST_UNREACH 1 - -#define UIP_CONF_DHCP_LIGHT -#define UIP_CONF_LLH_LEN 0 -#ifndef UIP_CONF_RECEIVE_WINDOW -#define UIP_CONF_RECEIVE_WINDOW 150 -#endif -#ifndef UIP_CONF_TCP_MSS -#define UIP_CONF_TCP_MSS UIP_CONF_RECEIVE_WINDOW -#endif -#define UIP_CONF_MAX_CONNECTIONS 4 -#define UIP_CONF_MAX_LISTENPORTS 8 -#define UIP_CONF_UDP_CONNS 12 -#define UIP_CONF_FWCACHE_SIZE 30 -#define UIP_CONF_BROADCAST 1 -#define UIP_ARCH_IPCHKSUM 0 -#define UIP_CONF_UDP 1 -#define UIP_CONF_UDP_CHECKSUMS 1 -#define UIP_CONF_TCP 1 -/*---------------------------------------------------------------------------*/ -/* include the project config */ -/* PROJECT_CONF_H might be defined in the project Makefile */ -#ifdef PROJECT_CONF_H -#include PROJECT_CONF_H -#endif /* PROJECT_CONF_H */ -/*---------------------------------------------------------------------------*/ -#endif /* CONTIKI_CONF_H */ -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#ifndef __CONTIKI_CONF_H__ +#define __CONTIKI_CONF_H__ +/*---------------------------------------------------------------------------*/ +#include "platform-conf.h" +/*---------------------------------------------------------------------------*/ +#define SLIP_BRIDGE_CONF_NO_PUTCHAR 1 + +#define NETSTACK_CONF_RDC_CHANNEL_CHECK_RATE 8 +#define NULLRDC_CONF_802154_AUTOACK 0 +#define NETSTACK_CONF_FRAMER framer_802154 +#define NETSTACK_CONF_NETWORK sicslowpan_driver + +#undef NETSTACK_CONF_RDC +#define NETSTACK_CONF_RDC nullrdc_driver +#define NETSTACK_RDC_HEADER_LEN 0 + +#undef NETSTACK_CONF_MAC +#define NETSTACK_CONF_MAC csma_driver +#define NETSTACK_MAC_HEADER_LEN 0 + +#define SICSLOWPAN_CONF_MAC_MAX_PAYLOAD \ + (NETSTACK_RADIO_MAX_PAYLOAD_LEN - NETSTACK_MAC_HEADER_LEN - \ + NETSTACK_RDC_HEADER_LEN) + +#define RIMESTATS_CONF_ENABLED 0 +#define RIMESTATS_CONF_ON 0 + +/* Network setup for IPv6 */ +#define CXMAC_CONF_ANNOUNCEMENTS 0 + +/* A trick to resolve a compilation error with IAR. */ +#ifdef __ICCARM__ +#define UIP_CONF_DS6_AADDR_NBU 1 +#endif + +/* radio driver blocks until ACK is received */ +#define NULLRDC_CONF_ACK_WAIT_TIME (0) +#define CONTIKIMAC_CONF_BROADCAST_RATE_LIMIT 0 +#define IEEE802154_CONF_PANID 0xABCD + +#define AODV_COMPLIANCE + +#define WITH_ASCII 1 + +#define PROCESS_CONF_NUMEVENTS 8 +#define PROCESS_CONF_STATS 1 +/*#define PROCESS_CONF_FASTPOLL 4*/ + +#define LINKADDR_CONF_SIZE 8 + +#define UIP_CONF_LL_802154 1 +#define UIP_CONF_LLH_LEN 0 + +#define UIP_CONF_ROUTER 1 + +/* configure number of neighbors and routes */ +#ifndef UIP_CONF_DS6_ROUTE_NBU +#define UIP_CONF_DS6_ROUTE_NBU 30 +#endif /* UIP_CONF_DS6_ROUTE_NBU */ + +#define UIP_CONF_ND6_SEND_RA 0 +#define UIP_CONF_ND6_REACHABLE_TIME 600000 /* 90000// 600000 */ +#define UIP_CONF_ND6_RETRANS_TIMER 10000 + +#define UIP_CONF_IPV6 1 +#ifndef UIP_CONF_IPV6_QUEUE_PKT +#define UIP_CONF_IPV6_QUEUE_PKT 0 +#endif /* UIP_CONF_IPV6_QUEUE_PKT */ +#define UIP_CONF_IP_FORWARD 0 +#ifndef UIP_CONF_BUFFER_SIZE +#define UIP_CONF_BUFFER_SIZE 280 +/* #define UIP_CONF_BUFFER_SIZE 600 */ +#endif + +#define SICSLOWPAN_CONF_MAXAGE 4 +#define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS 2 + +#ifndef SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS +#define SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS 5 +#endif /* SICSLOWPAN_CONF_MAX_MAC_TRANSMISSIONS */ + +#define UIP_CONF_ICMP_DEST_UNREACH 1 + +#define UIP_CONF_DHCP_LIGHT +#define UIP_CONF_LLH_LEN 0 +#ifndef UIP_CONF_RECEIVE_WINDOW +#define UIP_CONF_RECEIVE_WINDOW 150 +#endif +#ifndef UIP_CONF_TCP_MSS +#define UIP_CONF_TCP_MSS UIP_CONF_RECEIVE_WINDOW +#endif +#define UIP_CONF_MAX_CONNECTIONS 4 +#define UIP_CONF_MAX_LISTENPORTS 8 +#define UIP_CONF_UDP_CONNS 12 +#define UIP_CONF_FWCACHE_SIZE 30 +#define UIP_CONF_BROADCAST 1 +#define UIP_ARCH_IPCHKSUM 0 +#define UIP_CONF_UDP 1 +#define UIP_CONF_UDP_CHECKSUMS 1 +#define UIP_CONF_TCP 1 +/*---------------------------------------------------------------------------*/ +/* include the project config */ +/* PROJECT_CONF_H might be defined in the project Makefile */ +#ifdef PROJECT_CONF_H +#include PROJECT_CONF_H +#endif /* PROJECT_CONF_H */ +/*---------------------------------------------------------------------------*/ +#endif /* CONTIKI_CONF_H */ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c index 237e8e101..2342e8254 100644 --- a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c +++ b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c @@ -1,198 +1,195 @@ -/** -****************************************************************************** -* @file contiki-spirit1-main.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Contiki main file for stm32nucleo-spirit1 platform -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/** - * \addtogroup stm32nucleo-spirit1 - * @{ - * - * \file - * main file for stm32nucleo-spirit1 platform - */ -/*---------------------------------------------------------------------------*/ -#include -#include -#include "stm32cube_hal_init.h" -#include "contiki.h" -#include "contiki-net.h" -#include "sys/autostart.h" -#include "dev/leds.h" -#include "dev/serial-line.h" -#include "dev/slip.h" -#include "dev/watchdog.h" -#include "dev/xmem.h" -#include "lib/random.h" -#include "net/netstack.h" -#include "net/ip/uip.h" -#include "net/mac/frame802154.h" -#include "net/rime/rime.h" -#include "stm32l1xx.h" -#include "SPIRIT_Config.h" -#include "SPIRIT_Management.h" -#include "spirit1.h" -#include "spirit1-arch.h" -#include "node-id.h" -#include "hw-config.h" -#include "stdbool.h" -#include "dev/button-sensor.h" -#include "dev/radio-sensor.h" -/*---------------------------------------------------------------------------*/ -#if NETSTACK_CONF_WITH_IPV6 -#include "net/ipv6/uip-ds6.h" -#endif /*NETSTACK_CONF_WITH_IPV6*/ -/*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS -extern const struct sensors_sensor temperature_sensor; -extern const struct sensors_sensor humidity_sensor; -extern const struct sensors_sensor pressure_sensor; -extern const struct sensors_sensor magneto_sensor; -extern const struct sensors_sensor acceleration_sensor; -extern const struct sensors_sensor gyroscope_sensor; -SENSORS(&button_sensor, - &radio_sensor, - &temperature_sensor, - &humidity_sensor, - &pressure_sensor, - &magneto_sensor, - &acceleration_sensor, - &gyroscope_sensor); -#else /*COMPILE_SENSORS*/ -SENSORS(&button_sensor, - &radio_sensor); -#endif /*COMPILE_SENSORS*/ -/*---------------------------------------------------------------------------*/ -extern unsigned char node_mac[8]; -/*---------------------------------------------------------------------------*/ -#ifdef __GNUC__ -/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf -set to 'Yes') calls __io_putchar() */ -#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) -#else -#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) -#endif /* __GNUC__ */ -/*---------------------------------------------------------------------------*/ -#if NETSTACK_CONF_WITH_IPV6 -PROCINIT(&etimer_process, &tcpip_process); -#else /*NETSTACK_CONF_WITH_IPV6*/ -PROCINIT(&etimer_process); -#warning "No TCP/IP process!" -#endif /*NETSTACK_CONF_WITH_IPV6*/ -/*---------------------------------------------------------------------------*/ -#define BUSYWAIT_UNTIL(cond, max_time) \ -do { \ - rtimer_clock_t t0; \ - t0 = RTIMER_NOW(); \ - while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ -} while(0) -/*---------------------------------------------------------------------------*/ -static void set_rime_addr(void); -void stm32cube_hal_init(); -/*---------------------------------------------------------------------------*/ -#if 0 -static void panic_main(void) -{ - volatile uint16_t k; - while(1) { - leds_toggle(LEDS_ALL); - for(k = 0; k < 0xffff/8; k += 1) { } - } -} -#endif -/*---------------------------------------------------------------------------*/ -int main (int argc, char *argv[]) -{ - stm32cube_hal_init(); - - /* init LEDs */ - leds_init(); - - /* Initialize Contiki and our processes. */ - clock_init(); - ctimer_init(); - rtimer_init(); - watchdog_init(); - process_init(); - process_start(&etimer_process, NULL); - - - /* Restore node id if such has been stored in external mem */ - node_id_restore(); /* also configures node_mac[] */ - - set_rime_addr(); - random_init(node_id); - - netstack_init(); - spirit_radio_driver.on(); - - energest_init(); - - -#if NETSTACK_CONF_WITH_IPV6 - memcpy(&uip_lladdr.addr, node_mac, sizeof(uip_lladdr.addr)); - - queuebuf_init(); - process_start(&tcpip_process, NULL); - - uip_ipaddr_t ipaddr; - uip_ip6addr(&ipaddr, 0xfc00, 0, 0, 0, 0, 0, 0, 0); - uip_ds6_set_addr_iid(&ipaddr, &uip_lladdr); - uip_ds6_addr_add(&ipaddr, 0, ADDR_AUTOCONF); -#endif /* NETSTACK_CONF_WITH_IPV6*/ - - process_start(&sensors_process, NULL); - - autostart_start(autostart_processes); - - watchdog_start(); - - while(1) { - int r = 0; - do { - r = process_run(); - } while(r > 0); - } -} -/*---------------------------------------------------------------------------*/ -static void set_rime_addr(void) -{ - linkaddr_t addr; - - memset(&addr, 0, sizeof(linkaddr_t)); - memcpy(addr.u8, node_mac, sizeof(addr.u8)); - - linkaddr_set_node_addr(&addr); -} -/*---------------------------------------------------------------------------*/ -/** @} */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1 + * @{ + * + * \file + * main file for stm32nucleo-spirit1 platform + */ +/*---------------------------------------------------------------------------*/ +#include +#include +#include "stm32cube_hal_init.h" +#include "contiki.h" +#include "contiki-net.h" +#include "sys/autostart.h" +#include "dev/leds.h" +#include "dev/serial-line.h" +#include "dev/slip.h" +#include "dev/watchdog.h" +#include "dev/xmem.h" +#include "lib/random.h" +#include "net/netstack.h" +#include "net/ip/uip.h" +#include "net/mac/frame802154.h" +#include "net/rime/rime.h" +#include "stm32l1xx.h" +#include "SPIRIT_Config.h" +#include "SPIRIT_Management.h" +#include "spirit1.h" +#include "spirit1-arch.h" +#include "node-id.h" +#include "hw-config.h" +#include "stdbool.h" +#include "dev/button-sensor.h" +#include "dev/radio-sensor.h" +/*---------------------------------------------------------------------------*/ +#if NETSTACK_CONF_WITH_IPV6 +#include "net/ipv6/uip-ds6.h" +#endif /*NETSTACK_CONF_WITH_IPV6*/ +/*---------------------------------------------------------------------------*/ +#if COMPILE_SENSORS +extern const struct sensors_sensor temperature_sensor; +extern const struct sensors_sensor humidity_sensor; +extern const struct sensors_sensor pressure_sensor; +extern const struct sensors_sensor magneto_sensor; +extern const struct sensors_sensor acceleration_sensor; +extern const struct sensors_sensor gyroscope_sensor; +SENSORS(&button_sensor, + &radio_sensor, + &temperature_sensor, + &humidity_sensor, + &pressure_sensor, + &magneto_sensor, + &acceleration_sensor, + &gyroscope_sensor); +#else /*COMPILE_SENSORS*/ +SENSORS(&button_sensor, + &radio_sensor); +#endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ +extern unsigned char node_mac[8]; +/*---------------------------------------------------------------------------*/ +#ifdef __GNUC__ +/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE * f) +#endif /* __GNUC__ */ +/*---------------------------------------------------------------------------*/ +#if NETSTACK_CONF_WITH_IPV6 +PROCINIT(&etimer_process, &tcpip_process); +#else /*NETSTACK_CONF_WITH_IPV6*/ +PROCINIT(&etimer_process); +#warning "No TCP/IP process!" +#endif /*NETSTACK_CONF_WITH_IPV6*/ +/*---------------------------------------------------------------------------*/ +#define BUSYWAIT_UNTIL(cond, max_time) \ + do { \ + rtimer_clock_t t0; \ + t0 = RTIMER_NOW(); \ + while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))) ; \ + } while(0) +/*---------------------------------------------------------------------------*/ +static void set_rime_addr(void); +void stm32cube_hal_init(); +/*---------------------------------------------------------------------------*/ +#if 0 +static void +panic_main(void) +{ + volatile uint16_t k; + while(1) { + leds_toggle(LEDS_ALL); + for(k = 0; k < 0xffff / 8; k += 1) { + } + } +} +#endif +/*---------------------------------------------------------------------------*/ +int +main(int argc, char *argv[]) +{ + stm32cube_hal_init(); + + /* init LEDs */ + leds_init(); + + /* Initialize Contiki and our processes. */ + clock_init(); + ctimer_init(); + rtimer_init(); + watchdog_init(); + process_init(); + process_start(&etimer_process, NULL); + + /* Restore node id if such has been stored in external mem */ + node_id_restore(); /* also configures node_mac[] */ + + set_rime_addr(); + random_init(node_id); + + netstack_init(); + spirit_radio_driver.on(); + + energest_init(); + +#if NETSTACK_CONF_WITH_IPV6 + memcpy(&uip_lladdr.addr, node_mac, sizeof(uip_lladdr.addr)); + + queuebuf_init(); + process_start(&tcpip_process, NULL); + + uip_ipaddr_t ipaddr; + uip_ip6addr(&ipaddr, 0xfc00, 0, 0, 0, 0, 0, 0, 0); + uip_ds6_set_addr_iid(&ipaddr, &uip_lladdr); + uip_ds6_addr_add(&ipaddr, 0, ADDR_AUTOCONF); +#endif /* NETSTACK_CONF_WITH_IPV6*/ + + process_start(&sensors_process, NULL); + + autostart_start(autostart_processes); + + watchdog_start(); + + while(1) { + int r = 0; + do { + r = process_run(); + } while(r > 0); + } +} +/*---------------------------------------------------------------------------*/ +static void +set_rime_addr(void) +{ + linkaddr_t addr; + + memset(&addr, 0, sizeof(linkaddr_t)); + memcpy(addr.u8, node_mac, sizeof(addr.u8)); + + linkaddr_set_node_addr(&addr); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c index e41761dea..3b6e5bc56 100644 --- a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c @@ -1,39 +1,34 @@ -/** -****************************************************************************** -* @file acceleration-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable aceleration sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-temperature-sensor * @{ @@ -50,32 +45,37 @@ /*---------------------------------------------------------------------------*/ static int _active = 1; /*---------------------------------------------------------------------------*/ -static void init(void) +static void +init(void) { /*Acceleration and Gyroscope sensors share the same hw*/ - if (!st_lib_bsp_imu_6axes_is_initialized()) { - if (IMU_6AXES_OK == st_lib_bsp_imu_6axes_init()) { + if(!st_lib_bsp_imu_6axes_is_initialized()) { + if(IMU_6AXES_OK == st_lib_bsp_imu_6axes_init()) { _active = 1; } } } /*---------------------------------------------------------------------------*/ -static void activate(void) +static void +activate(void) { _active = 1; } /*---------------------------------------------------------------------------*/ -static void deactivate(void) +static void +deactivate(void) { _active = 0; } /*---------------------------------------------------------------------------*/ -static int active(void) +static int +active(void) { return _active; } /*---------------------------------------------------------------------------*/ -static int value(int type) +static int +value(int type) { int32_t ret_val = 0; volatile st_lib_axes_raw_typedef axes_raw_data; @@ -87,48 +87,50 @@ static int value(int type) */ st_lib_bsp_imu_6axes_x_get_axes_raw(&axes_raw_data); - switch (type) { - case X_AXIS: - ret_val = axes_raw_data.AXIS_X ; - break; - case Y_AXIS: - ret_val = axes_raw_data.AXIS_Y ; - break; - case Z_AXIS: - ret_val = axes_raw_data.AXIS_Z ; - break; - default: - break; + switch(type) { + case X_AXIS: + ret_val = axes_raw_data.AXIS_X; + break; + case Y_AXIS: + ret_val = axes_raw_data.AXIS_Y; + break; + case Z_AXIS: + ret_val = axes_raw_data.AXIS_Z; + break; + default: + break; } return ret_val; } /*---------------------------------------------------------------------------*/ -static int configure(int type, int value) +static int +configure(int type, int value) { switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } /*---------------------------------------------------------------------------*/ -static int status(int type) +static int +status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } - + return 0; } /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h index 818eb979f..32b168f9f 100644 --- a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file acceleration-sensor.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable aceleration sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals diff --git a/platform/stm32nucleo-spirit1/dev/button-sensor.c b/platform/stm32nucleo-spirit1/dev/button-sensor.c index 9a1e7c8a8..58e6c6a41 100644 --- a/platform/stm32nucleo-spirit1/dev/button-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/button-sensor.c @@ -1,109 +1,111 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/dev/button-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable button sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/** - * \addtogroup stm32nucleo-spirit1-peripherals - * @{ - * - * \file - * Driver for the stm32nucleo-spirit1 User Button - */ -/*---------------------------------------------------------------------------*/ -#include "dev/button-sensor.h" -#include "lib/sensors.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -static int _active = 0 ; -/*---------------------------------------------------------------------------*/ -static void init(void) -{ - /* See spirit1_appli.c for the Callback: it triggers the relevant - * sensors_changed event - */ - st_lib_bsp_pb_init(BUTTON_USER, BUTTON_MODE_EXTI); -} -/*---------------------------------------------------------------------------*/ -static void activate(void) -{ - _active = 1; -} -/*---------------------------------------------------------------------------*/ -static void deactivate(void) -{ - _active = 0; -} -/*---------------------------------------------------------------------------*/ -static int active(void) -{ - return active; -} -/*---------------------------------------------------------------------------*/ -static int value(int type) -{ - return st_lib_bsp_pb_get_state(BUTTON_USER); -} -/*---------------------------------------------------------------------------*/ -static int configure(int type, int value) -{ - switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; - } - - return 0; -} -/*---------------------------------------------------------------------------*/ -static int status(int type) -{ - switch(type) { - case SENSORS_READY: - return active(); - } - - return 0; -} -/*---------------------------------------------------------------------------*/ -SENSORS_SENSOR(button_sensor, BUTTON_SENSOR, value, configure, status); -/*---------------------------------------------------------------------------*/ -/** @} */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 User Button + */ +/*---------------------------------------------------------------------------*/ +#include "dev/button-sensor.h" +#include "lib/sensors.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +static int _active = 0; +/*---------------------------------------------------------------------------*/ +static void +init(void) +{ + /* See spirit1_appli.c for the Callback: it triggers the relevant + * sensors_changed event + */ + st_lib_bsp_pb_init(BUTTON_USER, BUTTON_MODE_EXTI); +} +/*---------------------------------------------------------------------------*/ +static void +activate(void) +{ + _active = 1; +} +/*---------------------------------------------------------------------------*/ +static void +deactivate(void) +{ + _active = 0; +} +/*---------------------------------------------------------------------------*/ +static int +active(void) +{ + return active; +} +/*---------------------------------------------------------------------------*/ +static int +value(int type) +{ + return st_lib_bsp_pb_get_state(BUTTON_USER); +} +/*---------------------------------------------------------------------------*/ +static int +configure(int type, int value) +{ + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +static int +status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(button_sensor, BUTTON_SENSOR, value, configure, status); +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c index 485a98120..31b79085f 100644 --- a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c @@ -1,39 +1,34 @@ -/** -****************************************************************************** -* @file gyroscope-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable aceleration sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-gyroscope-sensor * @{ @@ -50,32 +45,37 @@ /*---------------------------------------------------------------------------*/ static int _active = 1; /*---------------------------------------------------------------------------*/ -static void init(void) +static void +init(void) { /*Acceleration and Gyroscope sensors share the same hw*/ - if (!st_lib_bsp_imu_6axes_is_initialized()) { - if (IMU_6AXES_OK == st_lib_bsp_imu_6axes_init()) { + if(!st_lib_bsp_imu_6axes_is_initialized()) { + if(IMU_6AXES_OK == st_lib_bsp_imu_6axes_init()) { _active = 1; } } } /*---------------------------------------------------------------------------*/ -static void activate(void) +static void +activate(void) { _active = 1; } /*---------------------------------------------------------------------------*/ -static void deactivate(void) +static void +deactivate(void) { _active = 0; } /*---------------------------------------------------------------------------*/ -static int active(void) +static int +active(void) { return _active; } /*---------------------------------------------------------------------------*/ -static int value(int type) +static int +value(int type) { int32_t ret_val = 0; volatile st_lib_axes_raw_typedef axes_raw_data; @@ -87,48 +87,50 @@ static int value(int type) */ st_lib_bsp_imu_6axes_g_get_axes_raw(&axes_raw_data); - switch (type) { - case X_AXIS: - ret_val = axes_raw_data.AXIS_X ; - break; - case Y_AXIS: - ret_val = axes_raw_data.AXIS_Y ; - break; - case Z_AXIS: - ret_val = axes_raw_data.AXIS_Z ; - break; - default: - break; + switch(type) { + case X_AXIS: + ret_val = axes_raw_data.AXIS_X; + break; + case Y_AXIS: + ret_val = axes_raw_data.AXIS_Y; + break; + case Z_AXIS: + ret_val = axes_raw_data.AXIS_Z; + break; + default: + break; } return ret_val; } /*---------------------------------------------------------------------------*/ -static int configure(int type, int value) +static int +configure(int type, int value) { switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } /*---------------------------------------------------------------------------*/ -static int status(int type) +static int +status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } - + return 0; } /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h index 43bc4ce64..1db7ad764 100644 --- a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file gyroscope-sensor.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable aceleration sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals diff --git a/platform/stm32nucleo-spirit1/dev/humidity-sensor.c b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c index 54256a332..76f22656a 100644 --- a/platform/stm32nucleo-spirit1/dev/humidity-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c @@ -1,120 +1,122 @@ -/** -****************************************************************************** -* @file humidity-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable humidity sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/** - * \addtogroup stm32nucleo-spirit1-humidity-sensor - * @{ - * - * \file - * Driver for the stm32nucleo-spirit1 Humidity sensor (on expansion board) - */ -/*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS -/*---------------------------------------------------------------------------*/ -#include "lib/sensors.h" -#include "humidity-sensor.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -static int _active = 1; -/*---------------------------------------------------------------------------*/ -static void init(void) -{ - /*Temperature and Humity sensors share the same hw*/ - if (!st_lib_bsp_hum_temp_is_initialized()) { - st_lib_bsp_hum_temp_init(); - _active=1; - } -} -/*---------------------------------------------------------------------------*/ -static void activate(void) -{ - _active = 1; -} -/*---------------------------------------------------------------------------*/ -static void deactivate(void) -{ - _active = 0; -} -/*---------------------------------------------------------------------------*/ -static int active(void) -{ - return _active; -} -/*---------------------------------------------------------------------------*/ -static int value(int type) -{ - uint32_t humidity; - volatile float humidity_value; - - st_lib_bsp_hum_temp_get_humidity((float *)&humidity_value); - - humidity = humidity_value * 10; - return humidity; -} -/*---------------------------------------------------------------------------*/ -static int configure(int type, int value) -{ - switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; - } - - return 0; -} -/*---------------------------------------------------------------------------*/ -static int status(int type) -{ - switch(type) { - case SENSORS_READY: - return active(); - } - - return 0; -} -/*---------------------------------------------------------------------------*/ -SENSORS_SENSOR(humidity_sensor, HUMIDITY_SENSOR, value, configure, status); -/*---------------------------------------------------------------------------*/ -#endif /*COMPILE_SENSORS*/ -/*---------------------------------------------------------------------------*/ -/** @} */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-humidity-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Humidity sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ +#if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ +#include "lib/sensors.h" +#include "humidity-sensor.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +static int _active = 1; +/*---------------------------------------------------------------------------*/ +static void +init(void) +{ + /*Temperature and Humity sensors share the same hw*/ + if(!st_lib_bsp_hum_temp_is_initialized()) { + st_lib_bsp_hum_temp_init(); + _active = 1; + } +} +/*---------------------------------------------------------------------------*/ +static void +activate(void) +{ + _active = 1; +} +/*---------------------------------------------------------------------------*/ +static void +deactivate(void) +{ + _active = 0; +} +/*---------------------------------------------------------------------------*/ +static int +active(void) +{ + return _active; +} +/*---------------------------------------------------------------------------*/ +static int +value(int type) +{ + uint32_t humidity; + volatile float humidity_value; + + st_lib_bsp_hum_temp_get_humidity((float *)&humidity_value); + + humidity = humidity_value * 10; + return humidity; +} +/*---------------------------------------------------------------------------*/ +static int +configure(int type, int value) +{ + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +static int +status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(humidity_sensor, HUMIDITY_SENSOR, value, configure, status); +/*---------------------------------------------------------------------------*/ +#endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/humidity-sensor.h b/platform/stm32nucleo-spirit1/dev/humidity-sensor.h index 3de0b0687..49c8c0f69 100644 --- a/platform/stm32nucleo-spirit1/dev/humidity-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/humidity-sensor.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file humidity-sensor.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable humidity sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals diff --git a/platform/stm32nucleo-spirit1/dev/leds-arch.c b/platform/stm32nucleo-spirit1/dev/leds-arch.c index a05fe0832..6fadf21bd 100644 --- a/platform/stm32nucleo-spirit1/dev/leds-arch.c +++ b/platform/stm32nucleo-spirit1/dev/leds-arch.c @@ -1,39 +1,34 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/dev/leds-arch.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Contiki LEDs API binding for the boards in use: Nucleo and SPIRIT1 -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals * @{ @@ -50,14 +45,15 @@ /* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT * used, becasue of a pin conflict. */ -extern st_lib_gpio_typedef* st_lib_a_led_gpio_port[]; +extern st_lib_gpio_typedef *st_lib_a_led_gpio_port[]; extern const uint16_t st_lib_a_led_gpio_pin[]; #endif /*COMPILE_SENSORS*/ -extern st_lib_gpio_typedef* st_lib_gpio_port[]; +extern st_lib_gpio_typedef *st_lib_gpio_port[]; extern const uint16_t st_lib_gpio_pin[]; /*---------------------------------------------------------------------------*/ -void leds_arch_init(void) +void +leds_arch_init(void) { /* We have at least one led, the one on the Nucleo (GREEN)*/ st_lib_bsp_led_init(LED2); @@ -72,10 +68,11 @@ void leds_arch_init(void) #endif /*COMPILE_SENSORS*/ } /*---------------------------------------------------------------------------*/ -unsigned char leds_arch_get(void) +unsigned char +leds_arch_get(void) { - unsigned char ret = 0 ; - if (st_lib_hal_gpio_read_pin(st_lib_gpio_port[LED2],st_lib_gpio_pin[LED2])) { + unsigned char ret = 0; + if(st_lib_hal_gpio_read_pin(st_lib_gpio_port[LED2], st_lib_gpio_pin[LED2])) { ret |= LEDS_GREEN; } @@ -83,8 +80,8 @@ unsigned char leds_arch_get(void) /* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT * used, becasue of a pin conflict. */ - if (st_lib_hal_gpio_read_pin(st_lib_a_led_gpio_port[RADIO_SHIELD_LED], - st_lib_a_led_gpio_pin[RADIO_SHIELD_LED])) { + if(st_lib_hal_gpio_read_pin(st_lib_a_led_gpio_port[RADIO_SHIELD_LED], + st_lib_a_led_gpio_pin[RADIO_SHIELD_LED])) { ret |= LEDS_RED; } #endif /*COMPILE_SENSORS*/ @@ -92,9 +89,10 @@ unsigned char leds_arch_get(void) return ret; } /*---------------------------------------------------------------------------*/ -void leds_arch_set(unsigned char leds) +void +leds_arch_set(unsigned char leds) { - if (leds & LEDS_GREEN) { + if(leds & LEDS_GREEN) { st_lib_bsp_led_on(LED2); } else { st_lib_bsp_led_off(LED2); @@ -104,7 +102,7 @@ void leds_arch_set(unsigned char leds) /* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT * used, becasue of a pin conflict. */ - if (leds & LEDS_RED) { + if(leds & LEDS_RED) { st_lib_radio_shield_led_on(RADIO_SHIELD_LED); } else { st_lib_radio_shield_led_off(RADIO_SHIELD_LED); diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c index deda61954..d57668c33 100644 --- a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c @@ -1,39 +1,34 @@ -/** -****************************************************************************** -* @file magneto-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable magneto sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-magneto-sensor * @{ @@ -50,28 +45,33 @@ /*---------------------------------------------------------------------------*/ static int _active = 1; /*---------------------------------------------------------------------------*/ -static void init(void) +static void +init(void) { BSP_MAGNETO_Init(); _active = 1; } /*---------------------------------------------------------------------------*/ -static void activate(void) +static void +activate(void) { _active = 1; } /*---------------------------------------------------------------------------*/ -static void deactivate(void) +static void +deactivate(void) { _active = 0; } /*---------------------------------------------------------------------------*/ -static int active(void) +static int +active(void) { return _active; } /*---------------------------------------------------------------------------*/ -static int value(int type) +static int +value(int type) { int32_t ret_val = 0; volatile st_lib_axes_raw_typedef axes_raw_data; @@ -83,48 +83,50 @@ static int value(int type) */ st_lib_bsp_magneto_m_get_axes_raw(&axes_raw_data); - switch (type) { - case X_AXIS: - ret_val = axes_raw_data.AXIS_X ; - break; - case Y_AXIS: - ret_val = axes_raw_data.AXIS_Y ; - break; - case Z_AXIS: - ret_val = axes_raw_data.AXIS_Z ; - break; - default: - break; + switch(type) { + case X_AXIS: + ret_val = axes_raw_data.AXIS_X; + break; + case Y_AXIS: + ret_val = axes_raw_data.AXIS_Y; + break; + case Z_AXIS: + ret_val = axes_raw_data.AXIS_Z; + break; + default: + break; } return ret_val; } /*---------------------------------------------------------------------------*/ -static int configure(int type, int value) +static int +configure(int type, int value) { switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } /*---------------------------------------------------------------------------*/ -static int status(int type) +static int +status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } - + return 0; } /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.h b/platform/stm32nucleo-spirit1/dev/magneto-sensor.h index b75d47292..50376d488 100644 --- a/platform/stm32nucleo-spirit1/dev/magneto-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file magneto-sensor.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable magneto sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals diff --git a/platform/stm32nucleo-spirit1/dev/pressure-sensor.c b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c index df1e752da..8f92b01bc 100644 --- a/platform/stm32nucleo-spirit1/dev/pressure-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c @@ -1,39 +1,34 @@ -/** -****************************************************************************** -* @file pressure-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable pressure sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-pressure-sensor * @{ @@ -50,63 +45,70 @@ /*---------------------------------------------------------------------------*/ static int _active = 1; /*---------------------------------------------------------------------------*/ -static void init(void) +static void +init(void) { st_lib_bsp_pressure_init(); - _active =1; + _active = 1; } /*---------------------------------------------------------------------------*/ -static void activate(void) +static void +activate(void) { _active = 1; } /*---------------------------------------------------------------------------*/ -static void deactivate(void) +static void +deactivate(void) { _active = 0; } /*---------------------------------------------------------------------------*/ -static int active(void) +static int +active(void) { return _active; } /*---------------------------------------------------------------------------*/ -static int value(int type) +static int +value(int type) { uint16_t pressure; volatile float pressure_value; - + st_lib_bsp_pressure_get_pressure((float *)&pressure_value); pressure = pressure_value * 10; return pressure; } /*---------------------------------------------------------------------------*/ -static int configure(int type, int value) +static int +configure(int type, int value) { switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } /*---------------------------------------------------------------------------*/ -static int status(int type) +static int +status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } - + return 0; } /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/dev/pressure-sensor.h b/platform/stm32nucleo-spirit1/dev/pressure-sensor.h index d226f1de5..79d9b9402 100644 --- a/platform/stm32nucleo-spirit1/dev/pressure-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/pressure-sensor.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file pressure-sensor.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable pressure sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals diff --git a/platform/stm32nucleo-spirit1/dev/radio-sensor.c b/platform/stm32nucleo-spirit1/dev/radio-sensor.c index 34a0f3b98..4413c0498 100644 --- a/platform/stm32nucleo-spirit1/dev/radio-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/radio-sensor.c @@ -1,39 +1,34 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/dev/radio-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 7-September-2015 -* @brief Enable radio sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals * @{ @@ -50,76 +45,84 @@ /*---------------------------------------------------------------------------*/ static int _active; /*---------------------------------------------------------------------------*/ -static void init(void) +static void +init(void) { /*Nothing to do at the moment, can be used in the future.*/ } /*---------------------------------------------------------------------------*/ -static void activate(void) +static void +activate(void) { _active = 1; } /*---------------------------------------------------------------------------*/ -static void deactivate(void) +static void +deactivate(void) { _active = 0; } /*---------------------------------------------------------------------------*/ -static int active(void) +static int +active(void) { return _active; } /*---------------------------------------------------------------------------*/ -static int value(int type) +static int +value(int type) { int32_t radio_sensor; - float radio_sensor_value; + float radio_sensor_value; switch(type) { - case RADIO_SENSOR_LAST_PACKET: - /*TODO: check which method of getting these value is more appropriate */ - radio_sensor_value = DBM_VALUE(packetbuf_attr(PACKETBUF_ATTR_RSSI)); - //radio_sensor_value = st_lib_spirit_qi_get_rssi_dbm(); - radio_sensor = (int32_t) (radio_sensor_value * 10); - break; - case RADIO_SENSOR_LAST_VALUE: - default: - /*TODO: check which method of getting these value is more appropriate */ - radio_sensor = packetbuf_attr(PACKETBUF_ATTR_LINK_QUALITY); - //radio_sensor = (int32_t) st_lib_spirit_qi_get_lqi(); + case RADIO_SENSOR_LAST_PACKET: + /*TODO: check which method of getting these value is more appropriate */ + radio_sensor_value = DBM_VALUE(packetbuf_attr(PACKETBUF_ATTR_RSSI)); + /* radio_sensor_value = st_lib_spirit_qi_get_rssi_dbm(); */ + radio_sensor = (int32_t)(radio_sensor_value * 10); + break; + case RADIO_SENSOR_LAST_VALUE: + default: + /*TODO: check which method of getting these value is more appropriate */ + radio_sensor = packetbuf_attr(PACKETBUF_ATTR_LINK_QUALITY); + /* radio_sensor = (int32_t) st_lib_spirit_qi_get_lqi(); */ } return radio_sensor; } /*---------------------------------------------------------------------------*/ -static int configure(int type, int value) +static int +configure(int type, int value) { switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; } - + return 0; } /*---------------------------------------------------------------------------*/ -static int status(int type) +static int +status(int type) { switch(type) { - case SENSORS_READY: - return active(); + case SENSORS_READY: + return active(); } - + return 0; } /*---------------------------------------------------------------------------*/ SENSORS_SENSOR(radio_sensor, RADIO_SENSOR, value, configure, status); /*---------------------------------------------------------------------------*/ /** @} */ + diff --git a/platform/stm32nucleo-spirit1/dev/sensor-common.h b/platform/stm32nucleo-spirit1/dev/sensor-common.h index dad78cac9..c4672a4d3 100644 --- a/platform/stm32nucleo-spirit1/dev/sensor-common.h +++ b/platform/stm32nucleo-spirit1/dev/sensor-common.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/dev/sensor-common.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Common defines for sensors data structurers -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals @@ -51,8 +45,8 @@ #define Y_AXIS 0x01 #define Z_AXIS 0x02 -#define ABS_VALUE(x) (((x)>0)?(x):(-(x))) -#define DBM_VALUE(x) (-120.0+((float)((x)-20))/2) +#define ABS_VALUE(x) (((x) > 0) ? (x) : (-(x))) +#define DBM_VALUE(x) (-120.0 + ((float)((x) - 20)) / 2) /*---------------------------------------------------------------------------*/ #endif /*SENSOR_COMMON_H_*/ /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/dev/temperature-sensor.c b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c index 7370b33d0..29e82e069 100644 --- a/platform/stm32nucleo-spirit1/dev/temperature-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c @@ -1,119 +1,121 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/dev/temperature-sensor.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable temperature sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/** - * \addtogroup stm32nucleo-spirit1-temperature-sensor - * @{ - * - * \file - * Driver for the stm32nucleo-spirit1 Temperature sensor (on expansion board) - */ -/*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS -/*---------------------------------------------------------------------------*/ -#include "lib/sensors.h" -#include "temperature-sensor.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -static int _active = 0; -/*---------------------------------------------------------------------------*/ -static void init(void) -{ - /*Temperature and Humity sensors share the same hw*/ - if (!st_lib_bsp_hum_temp_is_initialized()) { - st_lib_bsp_hum_temp_init(); - _active=1; - } -} -/*---------------------------------------------------------------------------*/ -static void activate(void) -{ - _active = 1; -} -/*---------------------------------------------------------------------------*/ -static void deactivate(void) -{ - _active = 0; -} -/*---------------------------------------------------------------------------*/ -static int active(void) -{ - return _active; -} -/*---------------------------------------------------------------------------*/ -static int value(int type) -{ - int32_t temperature; - volatile float temperature_value; - - st_lib_bsp_hum_temp_get_temperature((float *)&temperature_value); - temperature = temperature_value * 10; - return temperature; -} -/*---------------------------------------------------------------------------*/ -static int configure(int type, int value) -{ - switch(type) { - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - if(value) { - activate(); - } else { - deactivate(); - } - return 1; - } - - return 0; -} -/*---------------------------------------------------------------------------*/ -static int status(int type) -{ - switch(type) { - case SENSORS_READY: - return active(); - } - - return 0; -} -/*---------------------------------------------------------------------------*/ -SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, - value, configure, status); -#endif /*COMPILE_SENSORS*/ -/*---------------------------------------------------------------------------*/ -/** @} */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-temperature-sensor + * @{ + * + * \file + * Driver for the stm32nucleo-spirit1 Temperature sensor (on expansion board) + */ +/*---------------------------------------------------------------------------*/ +#if COMPILE_SENSORS +/*---------------------------------------------------------------------------*/ +#include "lib/sensors.h" +#include "temperature-sensor.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +static int _active = 0; +/*---------------------------------------------------------------------------*/ +static void +init(void) +{ + /*Temperature and Humity sensors share the same hw*/ + if(!st_lib_bsp_hum_temp_is_initialized()) { + st_lib_bsp_hum_temp_init(); + _active = 1; + } +} +/*---------------------------------------------------------------------------*/ +static void +activate(void) +{ + _active = 1; +} +/*---------------------------------------------------------------------------*/ +static void +deactivate(void) +{ + _active = 0; +} +/*---------------------------------------------------------------------------*/ +static int +active(void) +{ + return _active; +} +/*---------------------------------------------------------------------------*/ +static int +value(int type) +{ + int32_t temperature; + volatile float temperature_value; + + st_lib_bsp_hum_temp_get_temperature((float *)&temperature_value); + temperature = temperature_value * 10; + return temperature; +} +/*---------------------------------------------------------------------------*/ +static int +configure(int type, int value) +{ + switch(type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + if(value) { + activate(); + } else { + deactivate(); + } + return 1; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +static int +status(int type) +{ + switch(type) { + case SENSORS_READY: + return active(); + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, + value, configure, status); +#endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/temperature-sensor.h b/platform/stm32nucleo-spirit1/dev/temperature-sensor.h index eb6fd2376..ca453b9b0 100644 --- a/platform/stm32nucleo-spirit1/dev/temperature-sensor.h +++ b/platform/stm32nucleo-spirit1/dev/temperature-sensor.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/dev/temperature-sensor.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Enable temperature sensor functionality -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \addtogroup stm32nucleo-spirit1-peripherals diff --git a/platform/stm32nucleo-spirit1/dev/uart1.h b/platform/stm32nucleo-spirit1/dev/uart1.h index a1d719083..9706ab226 100644 --- a/platform/stm32nucleo-spirit1/dev/uart1.h +++ b/platform/stm32nucleo-spirit1/dev/uart1.h @@ -1,54 +1,48 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/dev/uart1.h -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Include file for BAUD2UBR macro -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/*---------------------------------------------------------------------------*/ -/** - * \addtogroup stm32nucleo-spirit1-peripherals - * @{ - * - * - * \file - * Header file for UART related definitions. - */ -/*---------------------------------------------------------------------------*/ -#ifndef UART1_H_ -#define UART1_H_ -/*---------------------------------------------------------------------------*/ -#define BAUD2UBR(baud) baud -/*---------------------------------------------------------------------------*/ -#endif /* UART1_H_ */ -/*---------------------------------------------------------------------------*/ -/** @} */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1-peripherals + * @{ + * + * + * \file + * Header file for UART related definitions. + */ +/*---------------------------------------------------------------------------*/ +#ifndef UART1_H_ +#define UART1_H_ +/*---------------------------------------------------------------------------*/ +#define BAUD2UBR(baud) baud +/*---------------------------------------------------------------------------*/ +#endif /* UART1_H_ */ +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/stm32nucleo-spirit1/hw-config.h b/platform/stm32nucleo-spirit1/hw-config.h index 951704b64..4a4554bd6 100644 --- a/platform/stm32nucleo-spirit1/hw-config.h +++ b/platform/stm32nucleo-spirit1/hw-config.h @@ -1,125 +1,117 @@ - /** - ****************************************************************************** - * @file hw-config.h - * @author System LAB - * @version V1.0.0 - * @date 17-May-2015 - * @brief Header file for Hardware Configuration & Setup - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/*---------------------------------------------------------------------------*/ -#ifndef __HW_CONFIG_H -#define __HW_CONFIG_H -/*---------------------------------------------------------------------------*/ -#include "stm32l-spirit1-config.h" -/*---------------------------------------------------------------------------*/ -#define UART_RxBufferSize 512 -/*---------------------------------------------------------------------------*/ -#define I2Cx I2C1 -#define I2Cx_CLK_ENABLE() __I2C1_CLK_ENABLE() -#define I2Cx_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -#define I2Cx_SCL_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -/*---------------------------------------------------------------------------*/ -#define I2Cx_FORCE_RESET() __I2C1_FORCE_RESET() -#define I2Cx_RELEASE_RESET() __I2C1_RELEASE_RESET() -/*---------------------------------------------------------------------------*/ -/* Definition for I2Cx Pins */ -#define I2Cx_SCL_PIN GPIO_PIN_8 -#define I2Cx_SCL_GPIO_PORT GPIOB -#define I2Cx_SDA_PIN GPIO_PIN_9 -#define I2Cx_SDA_GPIO_PORT GPIOB -#define I2Cx_SCL_SDA_AF GPIO_AF4_I2C1 - -/* Definition for I2Cx's NVIC */ -#define I2Cx_EV_IRQn I2C1_EV_IRQn -#define I2Cx_ER_IRQn I2C1_ER_IRQn -#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler -#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler - - -#define I2Cx I2C1 -#define I2Cx_CLK_ENABLE() __I2C1_CLK_ENABLE() -#define I2Cx_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() -#define I2Cx_SCL_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() - -#define I2Cx_FORCE_RESET() __I2C1_FORCE_RESET() -#define I2Cx_RELEASE_RESET() __I2C1_RELEASE_RESET() - -/* Definition for I2Cx Pins */ -#define I2Cx_SCL_PIN GPIO_PIN_8 -#define I2Cx_SCL_GPIO_PORT GPIOB -#define I2Cx_SDA_PIN GPIO_PIN_9 -#define I2Cx_SDA_GPIO_PORT GPIOB -#define I2Cx_SCL_SDA_AF GPIO_AF4_I2C1 - -/* Definition for I2Cx's NVIC */ -#define I2Cx_EV_IRQn I2C1_EV_IRQn -#define I2Cx_ER_IRQn I2C1_ER_IRQn -#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler -#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler - -/* User can use this section to tailor USARTx/UARTx instance used and associated - resources */ -/* Definition for USARTx clock resources */ -#define USARTx USART2 -#define USARTx_CLK_ENABLE() __USART2_CLK_ENABLE(); -#define DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE() -#define USARTx_RX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() -#define USARTx_TX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() - -#define USARTx_FORCE_RESET() __USART2_FORCE_RESET() -#define USARTx_RELEASE_RESET() __USART2_RELEASE_RESET() - -/* Definition for USARTx Pins */ -#define USARTx_TX_PIN GPIO_PIN_2 -#define USARTx_TX_GPIO_PORT GPIOA - -#define USARTx_RX_PIN GPIO_PIN_3 -#define USARTx_RX_GPIO_PORT GPIOA - - /* Definition for USARTx's NVIC */ -#define USARTx_IRQn USART2_IRQn -#define USARTx_IRQHandler USART2_IRQHandler - -#define USARTx_TX_AF GPIO_AF7_USART2 -#define USARTx_RX_AF GPIO_AF7_USART2 - - - /* Enable sensor mask */ -#define PRESSURE_SENSOR 0x00000001 -#define TEMPERATURE_SENSOR 0x00000002 -#define HUMIDITY_SENSOR 0x00000004 -#define UV_SENSOR 0x00000008 -#define ACCELEROMETER_SENSOR 0x00000010 -#define GYROSCOPE_SENSOR 0x00000020 -#define MAGNETIC_SENSOR 0x00000040 -/*---------------------------------------------------------------------------*/ -#endif /*__HW_CONFIG_H*/ -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#ifndef __HW_CONFIG_H +#define __HW_CONFIG_H +/*---------------------------------------------------------------------------*/ +#include "stm32l-spirit1-config.h" +/*---------------------------------------------------------------------------*/ +#define UART_RxBufferSize 512 +/*---------------------------------------------------------------------------*/ +#define I2Cx I2C1 +#define I2Cx_CLK_ENABLE() __I2C1_CLK_ENABLE() +#define I2Cx_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define I2Cx_SCL_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +/*---------------------------------------------------------------------------*/ +#define I2Cx_FORCE_RESET() __I2C1_FORCE_RESET() +#define I2Cx_RELEASE_RESET() __I2C1_RELEASE_RESET() +/*---------------------------------------------------------------------------*/ +/* Definition for I2Cx Pins */ +#define I2Cx_SCL_PIN GPIO_PIN_8 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SDA_PIN GPIO_PIN_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SCL_SDA_AF GPIO_AF4_I2C1 + +/* Definition for I2Cx's NVIC */ +#define I2Cx_EV_IRQn I2C1_EV_IRQn +#define I2Cx_ER_IRQn I2C1_ER_IRQn +#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler +#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler + +#define I2Cx I2C1 +#define I2Cx_CLK_ENABLE() __I2C1_CLK_ENABLE() +#define I2Cx_SDA_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() +#define I2Cx_SCL_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE() + +#define I2Cx_FORCE_RESET() __I2C1_FORCE_RESET() +#define I2Cx_RELEASE_RESET() __I2C1_RELEASE_RESET() + +/* Definition for I2Cx Pins */ +#define I2Cx_SCL_PIN GPIO_PIN_8 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SDA_PIN GPIO_PIN_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SCL_SDA_AF GPIO_AF4_I2C1 + +/* Definition for I2Cx's NVIC */ +#define I2Cx_EV_IRQn I2C1_EV_IRQn +#define I2Cx_ER_IRQn I2C1_ER_IRQn +#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler +#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler + +/* User can use this section to tailor USARTx/UARTx instance used and associated + resources */ +/* Definition for USARTx clock resources */ +#define USARTx USART2 +#define USARTx_CLK_ENABLE() __USART2_CLK_ENABLE(); +#define DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE() +#define USARTx_RX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define USARTx_TX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE() + +#define USARTx_FORCE_RESET() __USART2_FORCE_RESET() +#define USARTx_RELEASE_RESET() __USART2_RELEASE_RESET() + +/* Definition for USARTx Pins */ +#define USARTx_TX_PIN GPIO_PIN_2 +#define USARTx_TX_GPIO_PORT GPIOA + +#define USARTx_RX_PIN GPIO_PIN_3 +#define USARTx_RX_GPIO_PORT GPIOA + +/* Definition for USARTx's NVIC */ +#define USARTx_IRQn USART2_IRQn +#define USARTx_IRQHandler USART2_IRQHandler + +#define USARTx_TX_AF GPIO_AF7_USART2 +#define USARTx_RX_AF GPIO_AF7_USART2 + +/* Enable sensor mask */ +#define PRESSURE_SENSOR 0x00000001 +#define TEMPERATURE_SENSOR 0x00000002 +#define HUMIDITY_SENSOR 0x00000004 +#define UV_SENSOR 0x00000008 +#define ACCELEROMETER_SENSOR 0x00000010 +#define GYROSCOPE_SENSOR 0x00000020 +#define MAGNETIC_SENSOR 0x00000040 +/*---------------------------------------------------------------------------*/ +#endif /*__HW_CONFIG_H*/ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/node-id.c b/platform/stm32nucleo-spirit1/node-id.c index ab6286791..2c629354d 100644 --- a/platform/stm32nucleo-spirit1/node-id.c +++ b/platform/stm32nucleo-spirit1/node-id.c @@ -1,60 +1,55 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/node-id.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Source file for node Id -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/*---------------------------------------------------------------------------*/ -#include "node-id.h" -#include "contiki-conf.h" -#include -/*---------------------------------------------------------------------------*/ -unsigned short node_id = 0; -unsigned char node_mac[8]; -volatile uint32_t device_id[3]; -/*---------------------------------------------------------------------------*/ -#define DEVICE_ID_REG0 (*((volatile uint32_t *) 0x1FF80050)) -#define DEVICE_ID_REG1 (*((volatile uint32_t *) 0x1FF80054)) -#define DEVICE_ID_REG2 (*((volatile uint32_t *) 0x1FF80064)) -/*---------------------------------------------------------------------------*/ -void node_id_restore(void) -{ - device_id[0] = DEVICE_ID_REG0; - device_id[1] = DEVICE_ID_REG1; - device_id[2] = DEVICE_ID_REG2; - - (*(uint32_t*)node_mac)=DEVICE_ID_REG1; - (*(((uint32_t*)node_mac)+1))=DEVICE_ID_REG2+DEVICE_ID_REG0; - node_id = (unsigned short) DEVICE_ID_REG2; -} -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#include "node-id.h" +#include "contiki-conf.h" +#include +/*---------------------------------------------------------------------------*/ +unsigned short node_id = 0; +unsigned char node_mac[8]; +volatile uint32_t device_id[3]; +/*---------------------------------------------------------------------------*/ +#define DEVICE_ID_REG0 (*((volatile uint32_t *)0x1FF80050)) +#define DEVICE_ID_REG1 (*((volatile uint32_t *)0x1FF80054)) +#define DEVICE_ID_REG2 (*((volatile uint32_t *)0x1FF80064)) +/*---------------------------------------------------------------------------*/ +void +node_id_restore(void) +{ + device_id[0] = DEVICE_ID_REG0; + device_id[1] = DEVICE_ID_REG1; + device_id[2] = DEVICE_ID_REG2; + + (*(uint32_t *)node_mac) = DEVICE_ID_REG1; + (*(((uint32_t *)node_mac) + 1)) = DEVICE_ID_REG2 + DEVICE_ID_REG0; + node_id = (unsigned short)DEVICE_ID_REG2; +} +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/platform-conf.h b/platform/stm32nucleo-spirit1/platform-conf.h index ed80ca010..ea32741ea 100644 --- a/platform/stm32nucleo-spirit1/platform-conf.h +++ b/platform/stm32nucleo-spirit1/platform-conf.h @@ -1,115 +1,109 @@ -/** -****************************************************************************** -* @file platform/stm32nucleo-spirit1/platform-conf.h -* @author System LAB -* @version V1.0.0 -* @date 17-May-2015 -* @brief Configuration parameters -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/*---------------------------------------------------------------------------*/ -/** - * \addtogroup stm32nucleo-spirit1 - * @{ - * - * \defgroup stm32nucleo-spirit1-peripherals User Button on STM32 Nucleo - * - * Defines some of the platforms capabilities - * @{ - * - * \file - * Header file for the stm32nucleo-spirit1 platform configuration - */ -/*---------------------------------------------------------------------------*/ -#ifndef __PLATFORM_CONF_H__ -#define __PLATFORM_CONF_H__ -/*---------------------------------------------------------------------------*/ -#include -#include -/*---------------------------------------------------------------------------*/ -#define PLATFORM_HAS_LEDS 1 -#define PLATFORM_HAS_BUTTON 1 -#define PLATFORM_HAS_RADIO 1 - -#define LEDS_GREEN 1 /*Nucleo LED*/ -#define LEDS_RED 2 /*SPIRIT1 LED*/ - -#ifdef COMPILE_SENSORS -#define LEDS_CONF_ALL 1 /*Can't use SPIRIT1 LED in this case*/ -#else -#define LEDS_CONF_ALL 3 /*No sensors -> we can use SPIRIT1 LED in this case*/ -#endif /*COMPILE_SENSORS*/ -/*---------------------------------------------------------------------------*/ -#define F_CPU 32000000ul -#define RTIMER_ARCH_SECOND 32768 -#define PRESCALER ((F_CPU / (RTIMER_ARCH_SECOND*2))) - -#define UART1_CONF_TX_WITH_INTERRUPT 0 -#define WITH_SERIAL_LINE_INPUT 1 -#define TELNETD_CONF_NUMLINES 6 -#define NETSTACK_CONF_RADIO spirit_radio_driver -#define NETSTACK_RADIO_MAX_PAYLOAD_LEN 96 /* spirit1-config.h */ - -/*---------------------------------------------------------------------------*/ -/* define ticks/second for slow and fast clocks. Notice that these should be a - power of two, eg 64,128,256,512 etc, for efficiency as POT's can be optimized - well. */ -#define CLOCK_CONF_SECOND 128 -/* One tick: 62.5 ms */ - -#define RTIMER_CLOCK_LT(a,b) ((signed short)((a)-(b)) < 0) -/*---------------------------------------------------------------------------*/ -typedef unsigned long clock_time_t; -typedef unsigned long long rtimer_clock_t; -/*---------------------------------------------------------------------------*/ -#define CC_CONF_REGISTER_ARGS 0 -#define CC_CONF_FUNCTION_POINTER_ARGS 1 -#define CC_CONF_FASTCALL -#define CC_CONF_VA_ARGS 1 -#define CC_CONF_INLINE inline - -#define CCIF -#define CLIF -/*---------------------------------------------------------------------------*/ -typedef uint8_t u8_t; -typedef uint16_t u16_t; -typedef uint32_t u32_t; -typedef int32_t s32_t; -typedef unsigned short uip_stats_t; -/*---------------------------------------------------------------------------*/ -#define MULTICHAN_CONF_SET_CHANNEL(x) -#define MULTICHAN_CONF_READ_RSSI(x) 0 -/*---------------------------------------------------------------------------*/ -#endif /* __PLATFORM_CONF_H__ */ -/*---------------------------------------------------------------------------*/ -/** - * @} - * @} - */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup stm32nucleo-spirit1 + * @{ + * + * \defgroup stm32nucleo-spirit1-peripherals User Button on STM32 Nucleo + * + * Defines some of the platforms capabilities + * @{ + * + * \file + * Header file for the stm32nucleo-spirit1 platform configuration + */ +/*---------------------------------------------------------------------------*/ +#ifndef __PLATFORM_CONF_H__ +#define __PLATFORM_CONF_H__ +/*---------------------------------------------------------------------------*/ +#include +#include +/*---------------------------------------------------------------------------*/ +#define PLATFORM_HAS_LEDS 1 +#define PLATFORM_HAS_BUTTON 1 +#define PLATFORM_HAS_RADIO 1 + +#define LEDS_GREEN 1 /*Nucleo LED*/ +#define LEDS_RED 2 /*SPIRIT1 LED*/ + +#ifdef COMPILE_SENSORS +#define LEDS_CONF_ALL 1 /*Can't use SPIRIT1 LED in this case*/ +#else +#define LEDS_CONF_ALL 3 /*No sensors -> we can use SPIRIT1 LED in this case*/ +#endif /*COMPILE_SENSORS*/ +/*---------------------------------------------------------------------------*/ +#define F_CPU 32000000ul +#define RTIMER_ARCH_SECOND 32768 +#define PRESCALER ((F_CPU / (RTIMER_ARCH_SECOND * 2))) + +#define UART1_CONF_TX_WITH_INTERRUPT 0 +#define WITH_SERIAL_LINE_INPUT 1 +#define TELNETD_CONF_NUMLINES 6 +#define NETSTACK_CONF_RADIO spirit_radio_driver +#define NETSTACK_RADIO_MAX_PAYLOAD_LEN 96 /* spirit1-config.h */ + +/*---------------------------------------------------------------------------*/ +/* define ticks/second for slow and fast clocks. Notice that these should be a + power of two, eg 64,128,256,512 etc, for efficiency as POT's can be optimized + well. */ +#define CLOCK_CONF_SECOND 128 +/* One tick: 62.5 ms */ + +#define RTIMER_CLOCK_LT(a, b) ((signed short)((a) - (b)) < 0) +/*---------------------------------------------------------------------------*/ +typedef unsigned long clock_time_t; +typedef unsigned long long rtimer_clock_t; +/*---------------------------------------------------------------------------*/ +#define CC_CONF_REGISTER_ARGS 0 +#define CC_CONF_FUNCTION_POINTER_ARGS 1 +#define CC_CONF_FASTCALL +#define CC_CONF_VA_ARGS 1 +#define CC_CONF_INLINE inline + +#define CCIF +#define CLIF +/*---------------------------------------------------------------------------*/ +typedef uint8_t u8_t; +typedef uint16_t u16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +typedef unsigned short uip_stats_t; +/*---------------------------------------------------------------------------*/ +#define MULTICHAN_CONF_SET_CHANNEL(x) +#define MULTICHAN_CONF_READ_RSSI(x) 0 +/*---------------------------------------------------------------------------*/ +#endif /* __PLATFORM_CONF_H__ */ +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ diff --git a/platform/stm32nucleo-spirit1/spirit1-arch.c b/platform/stm32nucleo-spirit1/spirit1-arch.c index 762399d11..6ea68bf3d 100644 --- a/platform/stm32nucleo-spirit1/spirit1-arch.c +++ b/platform/stm32nucleo-spirit1/spirit1-arch.c @@ -1,86 +1,78 @@ -/** -****************************************************************************** -* @file main.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Source file for SPIRIT1 -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/*---------------------------------------------------------------------------*/ -#include "stm32l1xx.h" -#include "spirit1-arch.h" -#include "spirit1.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -extern void spirit1_interrupt_callback(void); -st_lib_spirit_bool spiritdk_timer_expired = S_FALSE; -/*---------------------------------------------------------------------------*/ -/* use the SPI-port to acquire the status bytes from the radio. */ -#define CS_TO_SCLK_DELAY 0x0100 -/*---------------------------------------------------------------------------*/ -extern st_lib_spi_handle_typedef st_lib_p_spi_handle; -/*---------------------------------------------------------------------------*/ -uint16_t -spirit1_arch_refresh_status(void) -{ - volatile uint16_t mcstate = 0x0000; - uint8_t header[2]; - header[0]=0x01; - header[1]=MC_STATE1_BASE; - uint32_t spi_timeout = ((uint32_t)1000); /*IDR & RADIO_SPI_CS_PIN)) -#define SPIRIT1_STATUS() (spirit1_arch_refresh_status() & SPIRIT1_STATE_STATEBITS) -/*---------------------------------------------------------------------------*/ -uint16_t spirit1_arch_refresh_status(void); -/*---------------------------------------------------------------------------*/ -#endif /* __SPIRIT1_ARCH_H__ */ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + */ +/*---------------------------------------------------------------------------*/ +#ifndef __SPIRIT1_ARCH_H__ +#define __SPIRIT1_ARCH_H__ +/*---------------------------------------------------------------------------*/ +#include "string.h" +#include "SPIRIT_Management.h" +#include "radio_gpio.h" +#include "radio_spi.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +#define IRQ_ENABLE() st_lib_radio_gpio_interrupt_cmd(RADIO_GPIO_IRQ, 0x0F, 0x0F, ENABLE); +#define IRQ_DISABLE() st_lib_radio_gpio_interrupt_cmd(RADIO_GPIO_IRQ, 0x0F, 0x0F, DISABLE); +#define spirit_spi_busy() (!(RADIO_SPI_CS_PORT->IDR & RADIO_SPI_CS_PIN)) +#define SPIRIT1_STATUS() (spirit1_arch_refresh_status() & SPIRIT1_STATE_STATEBITS) +/*---------------------------------------------------------------------------*/ +uint16_t spirit1_arch_refresh_status(void); +/*---------------------------------------------------------------------------*/ +#endif /* __SPIRIT1_ARCH_H__ */ diff --git a/platform/stm32nucleo-spirit1/spirit1-config.h b/platform/stm32nucleo-spirit1/spirit1-config.h index 44ba6ac52..4c89fe33e 100644 --- a/platform/stm32nucleo-spirit1/spirit1-config.h +++ b/platform/stm32nucleo-spirit1/spirit1-config.h @@ -1,59 +1,59 @@ -/* - * Copyright (c) 2012, STMicroelectronics. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the Contiki operating system. - * - */ -/*---------------------------------------------------------------------------*/ -#ifndef __SPIRIT1_CONFIG_H__ -#define __SPIRIT1_CONFIG_H__ -/*---------------------------------------------------------------------------*/ -#include "radio.h" -#include "SPIRIT_Config.h" -#include "spirit1-const.h" -/*---------------------------------------------------------------------------*/ -#define CCA_THRESHOLD -98.0 /* dBm */ -#define XTAL_FREQUENCY 50000000 /* Hz */ -#define SPIRIT_MAX_FIFO_LEN 96 -/*---------------------------------------------------------------------------*/ - -/** - * The MAX_PACKET_LEN is an arbitrary value used to define the two array - * spirit_txbuf and spirit_rxbuf. - * The SPIRIT1 supports with its packet handler a length of 65,535 bytes, - * and in direct mode (without packet handler) there is no limit of data. - */ -#define MAX_PACKET_LEN SPIRIT_MAX_FIFO_LEN -/*---------------------------------------------------------------------------*/ -/** - * Spirit1 IC version - */ -#define SPIRIT1_VERSION SPIRIT_VERSION_3_0 -/*---------------------------------------------------------------------------*/ -#endif /* __SPIRIT1_CONFIG_H__ */ -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + */ +/*---------------------------------------------------------------------------*/ +#ifndef __SPIRIT1_CONFIG_H__ +#define __SPIRIT1_CONFIG_H__ +/*---------------------------------------------------------------------------*/ +#include "radio.h" +#include "SPIRIT_Config.h" +#include "spirit1-const.h" +/*---------------------------------------------------------------------------*/ +#define CCA_THRESHOLD -98.0 /* dBm */ +#define XTAL_FREQUENCY 50000000 /* Hz */ +#define SPIRIT_MAX_FIFO_LEN 96 +/*---------------------------------------------------------------------------*/ + +/** + * The MAX_PACKET_LEN is an arbitrary value used to define the two array + * spirit_txbuf and spirit_rxbuf. + * The SPIRIT1 supports with its packet handler a length of 65,535 bytes, + * and in direct mode (without packet handler) there is no limit of data. + */ +#define MAX_PACKET_LEN SPIRIT_MAX_FIFO_LEN +/*---------------------------------------------------------------------------*/ +/** + * Spirit1 IC version + */ +#define SPIRIT1_VERSION SPIRIT_VERSION_3_0 +/*---------------------------------------------------------------------------*/ +#endif /* __SPIRIT1_CONFIG_H__ */ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/spirit1-const.h b/platform/stm32nucleo-spirit1/spirit1-const.h index e1ab6cd5d..84294e343 100644 --- a/platform/stm32nucleo-spirit1/spirit1-const.h +++ b/platform/stm32nucleo-spirit1/spirit1-const.h @@ -1,65 +1,65 @@ -/* - * Copyright (c) 2012, STMicroelectronics. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/*---------------------------------------------------------------------------*/ -#ifndef __SPIRIT1_CONST_H__ -#define __SPIRIT1_CONST_H__ -/*---------------------------------------------------------------------------*/ -/* The state bitfield and values for different states, as read from MC_STATE[1:0] registers, -which are returned on any SPI read or write operation. */ -#define SPIRIT1_STATE_STATEBITS (0x00FE) -/*---------------------------------------------------------------------------*/ - -#define SPIRIT1_STATE_STANDBY ((0x0040)<<1) -#define SPIRIT1_STATE_SLEEP ((0x0036)<<1) -#define SPIRIT1_STATE_READY ((0x0003)<<1) -#define SPIRIT1_STATE_LOCK ((0x000F)<<1) -#define SPIRIT1_STATE_RX ((0x0033)<<1) -#define SPIRIT1_STATE_TX ((0x005F)<<1) -/* NB the below states were extracted from ST drivers, but are not specified in the datasheet */ -#define SPIRIT1_STATE_PM_SETUP ((0x003D)<<1) -#define SPIRIT1_STATE_XO_SETTLING ((0x0023)<<1) -#define SPIRIT1_STATE_SYNTH_SETUP ((0x0053)<<1) -#define SPIRIT1_STATE_PROTOCOL ((0x001F)<<1) -#define SPIRIT1_STATE_SYNTH_CALIBRATION ((0x004F)<<1) -/*---------------------------------------------------------------------------*/ -/* strobe commands */ -#define SPIRIT1_STROBE_TX 0x60 -#define SPIRIT1_STROBE_RX 0x61 -#define SPIRIT1_STROBE_READY 0x62 -#define SPIRIT1_STROBE_STANDBY 0x63 -#define SPIRIT1_STROBE_SLEEP 0x64 -#define SPIRIT1_STROBE_SABORT 0x67 -#define SPIRIT1_STROBE_SRES 0x70 -#define SPIRIT1_STROBE_FRX 0x71 -#define SPIRIT1_STROBE_FTX 0x72 -/*---------------------------------------------------------------------------*/ -#endif /* __SPIRIT1_CONST_H__ */ -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#ifndef __SPIRIT1_CONST_H__ +#define __SPIRIT1_CONST_H__ +/*---------------------------------------------------------------------------*/ +/* The state bitfield and values for different states, as read from MC_STATE[1:0] registers, + which are returned on any SPI read or write operation. */ +#define SPIRIT1_STATE_STATEBITS (0x00FE) +/*---------------------------------------------------------------------------*/ + +#define SPIRIT1_STATE_STANDBY ((0x0040) << 1) +#define SPIRIT1_STATE_SLEEP ((0x0036) << 1) +#define SPIRIT1_STATE_READY ((0x0003) << 1) +#define SPIRIT1_STATE_LOCK ((0x000F) << 1) +#define SPIRIT1_STATE_RX ((0x0033) << 1) +#define SPIRIT1_STATE_TX ((0x005F) << 1) +/* NB the below states were extracted from ST drivers, but are not specified in the datasheet */ +#define SPIRIT1_STATE_PM_SETUP ((0x003D) << 1) +#define SPIRIT1_STATE_XO_SETTLING ((0x0023) << 1) +#define SPIRIT1_STATE_SYNTH_SETUP ((0x0053) << 1) +#define SPIRIT1_STATE_PROTOCOL ((0x001F) << 1) +#define SPIRIT1_STATE_SYNTH_CALIBRATION ((0x004F) << 1) +/*---------------------------------------------------------------------------*/ +/* strobe commands */ +#define SPIRIT1_STROBE_TX 0x60 +#define SPIRIT1_STROBE_RX 0x61 +#define SPIRIT1_STROBE_READY 0x62 +#define SPIRIT1_STROBE_STANDBY 0x63 +#define SPIRIT1_STROBE_SLEEP 0x64 +#define SPIRIT1_STROBE_SABORT 0x67 +#define SPIRIT1_STROBE_SRES 0x70 +#define SPIRIT1_STROBE_FRX 0x71 +#define SPIRIT1_STROBE_FTX 0x72 +/*---------------------------------------------------------------------------*/ +#endif /* __SPIRIT1_CONST_H__ */ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/spirit1.c b/platform/stm32nucleo-spirit1/spirit1.c index 0006bb993..5bca4195f 100644 --- a/platform/stm32nucleo-spirit1/spirit1.c +++ b/platform/stm32nucleo-spirit1/spirit1.c @@ -1,719 +1,713 @@ -/** -****************************************************************************** -* @file spirit1.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -* @brief Source file for SPIRIT1 -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/*---------------------------------------------------------------------------*/ -#include "spirit1.h" -#include "spirit1-arch.h" -#include "stm32l1xx.h" -#include "contiki.h" -#include "net/mac/frame802154.h" -#include "net/netstack.h" -#include "net/packetbuf.h" -#include "net/rime/rimestats.h" -#include "spirit1-arch.h" -#include -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -//MGR extern st_lib_spirit_irqs st_lib_x_irq_status; -extern volatile st_lib_spirit_flag_status rx_timeout; -/*---------------------------------------------------------------------------*/ -#define XXX_ACK_WORKAROUND 1 -/*---------------------------------------------------------------------------*/ -#define DEBUG 0 -#if DEBUG -#include -#define PRINTF(...) printf(__VA_ARGS__) -#else -#define PRINTF(...) -#endif - -/*---------------------------------------------------------------------------*/ -#define BUSYWAIT_UNTIL(cond, max_time) \ - do { \ - rtimer_clock_t t0; \ - t0 = RTIMER_NOW(); \ - while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ - } while(0) - -/*---------------------------------------------------------------------------*/ -#define CLEAR_TXBUF() (spirit_txbuf[0] = 0) -#define CLEAR_RXBUF() (spirit_rxbuf[0] = 0) -#define IS_TXBUF_EMPTY() (spirit_txbuf[0] == 0) -#define IS_RXBUF_EMPTY() (spirit_rxbuf[0] == 0) -#define IS_RXBUF_FULL() (spirit_rxbuf[0] != 0) -/*---------------------------------------------------------------------------*/ -/* transceiver state. */ -#define ON 0 -#define OFF 1 -/*---------------------------------------------------------------------------*/ -static volatile unsigned int spirit_on = OFF; -static volatile uint8_t receiving_packet = 0; -static packetbuf_attr_t last_rssi = 0 ; //MGR -static packetbuf_attr_t last_lqi = 0 ; //MGR -/*---------------------------------------------------------------------------*/ -/* -* The buffers which hold incoming data. -* The +1 because of the first byte, -* which will contain the length of the packet. -*/ -static uint8_t spirit_rxbuf[MAX_PACKET_LEN+1]; -static uint8_t spirit_txbuf[MAX_PACKET_LEN+1-SPIRIT_MAX_FIFO_LEN]; -void st_lib_spirit_management_set_frequency_base(uint32_t); -/*---------------------------------------------------------------------------*/ -static int just_got_an_ack = 0; /* Interrupt callback just detected an ack */ -#if NULLRDC_CONF_802154_AUTOACK -#define ACK_LEN 3 -static int wants_an_ack = 0; /* The packet sent expects an ack */ -//static int just_got_an_ack = 0; /* Interrupt callback just detected an ack */ -//#define ACKPRINTF printf -#define ACKPRINTF(...) -#endif /* NULLRDC_CONF_802154_AUTOACK */ -/*---------------------------------------------------------------------------*/ -static int packet_is_prepared = 0; -/*---------------------------------------------------------------------------*/ -PROCESS(spirit_radio_process, "SPIRIT radio driver"); -/*---------------------------------------------------------------------------*/ -static int spirit_radio_init(void); -static int spirit_radio_prepare(const void *payload, unsigned short payload_len); -static int spirit_radio_transmit(unsigned short payload_len); -static int spirit_radio_send(const void *data, unsigned short len); -static int spirit_radio_read(void *buf, unsigned short bufsize); -static int spirit_radio_channel_clear(void); -static int spirit_radio_receiving_packet(void); -static int spirit_radio_pending_packet(void); -static int spirit_radio_on(void); -static int spirit_radio_off(void); -/*---------------------------------------------------------------------------*/ -const struct radio_driver spirit_radio_driver = -{ - spirit_radio_init, - spirit_radio_prepare, - spirit_radio_transmit, - spirit_radio_send, - spirit_radio_read, - spirit_radio_channel_clear, - spirit_radio_receiving_packet, - spirit_radio_pending_packet, - spirit_radio_on, - spirit_radio_off, -}; -/*---------------------------------------------------------------------------*/ -void -spirit1_printstatus(void) -{ - int s = SPIRIT1_STATUS(); - if(s == SPIRIT1_STATE_STANDBY) { - printf("spirit1: SPIRIT1_STATE_STANDBY\n"); - } else if(s == SPIRIT1_STATE_READY) { - printf("spirit1: SPIRIT1_STATE_READY\n"); - } else if(s == SPIRIT1_STATE_TX) { - printf("spirit1: SPIRIT1_STATE_TX\n"); - } else if(s == SPIRIT1_STATE_RX) { - printf("spirit1: SPIRIT1_STATE_RX\n"); - } else { - printf("spirit1: status: %d\n", s); - } -} -/*---------------------------------------------------------------------------*/ -/* Strobe a command. The rationale for this is to clean up the messy legacy code. */ -static void -spirit1_strobe(uint8_t s) -{ - st_lib_spirit_cmd_strobe_command(s); -} -/*---------------------------------------------------------------------------*/ -void spirit_set_ready_state(void) -{ - PRINTF("READY IN\n"); - - st_lib_spirit_irq_clear_status(); - IRQ_DISABLE(); - - if(SPIRIT1_STATUS() == SPIRIT1_STATE_STANDBY) { - spirit1_strobe(SPIRIT1_STROBE_READY); - } else if(SPIRIT1_STATUS() == SPIRIT1_STATE_RX) { - spirit1_strobe(SPIRIT1_STROBE_SABORT); - st_lib_spirit_irq_clear_status(); - } - - IRQ_ENABLE(); - - PRINTF("READY OUT\n"); -} -/*---------------------------------------------------------------------------*/ -static int -spirit_radio_init(void) -{ - - PRINTF("RADIO INIT IN\n"); - - st_lib_spirit_spi_init(); - - /* Configure radio shut-down (SDN) pin and activate radio */ - st_lib_radio_gpio_init(RADIO_GPIO_SDN, RADIO_MODE_GPIO_OUT); - - /* Configures the SPIRIT1 library */ - st_lib_spirit_radio_set_xtal_frequency(XTAL_FREQUENCY); - st_lib_spirit_management_set_frequency_base(XTAL_FREQUENCY); - - /* wake up to READY state */ - /* weirdly enough, this *should* actually *set* the pin, not clear it! The pins is declared as GPIO_pin13 == 0x2000 */ - RADIO_GPIO_SDN_PORT->BSRR = RADIO_GPIO_SDN_PIN; - st_lib_hal_gpio_write_pin(RADIO_GPIO_SDN_PORT, RADIO_GPIO_SDN_PIN,GPIO_PIN_RESET); - - /* wait minimum 1.5 ms to allow SPIRIT1 a proper boot-up sequence */ - BUSYWAIT_UNTIL(0, 3 * RTIMER_SECOND/2000); - - /* Soft reset of core */ - spirit1_strobe(SPIRIT1_STROBE_SRES); - - /* Configures the SPIRIT1 radio part */ - st_lib_s_radio_init x_radio_init = { - // XTAL_FREQUENCY, - XTAL_OFFSET_PPM, - BASE_FREQUENCY, - CHANNEL_SPACE, - CHANNEL_NUMBER, - MODULATION_SELECT, - DATARATE, - FREQ_DEVIATION, - BANDWIDTH - }; - st_lib_spirit_radio_init(&x_radio_init); - st_lib_spirit_radio_set_xtal_frequency(XTAL_FREQUENCY); - st_lib_spirit_radio_set_pa_level_dbm(0,POWER_DBM); - st_lib_spirit_radio_set_pa_level_max_index(0); - - /* Configures the SPIRIT1 packet handler part*/ - st_lib_pkt_basic_init x_basic_init = { - PREAMBLE_LENGTH, - SYNC_LENGTH, - SYNC_WORD, - LENGTH_TYPE, - LENGTH_WIDTH, - CRC_MODE, - CONTROL_LENGTH, - EN_ADDRESS, - EN_FEC, - EN_WHITENING - }; - st_lib_spirit_pkt_basic_init(&x_basic_init); - - /* Enable the following interrupt sources, routed to GPIO */ - st_lib_spirit_irq_de_init(NULL); - st_lib_spirit_irq_clear_status(); - st_lib_spirit_irq(TX_DATA_SENT, S_ENABLE); - st_lib_spirit_irq(RX_DATA_READY,S_ENABLE); - st_lib_spirit_irq(VALID_SYNC,S_ENABLE); - st_lib_spirit_irq(RX_DATA_DISC, S_ENABLE); - st_lib_spirit_irq(TX_FIFO_ERROR, S_ENABLE); - st_lib_spirit_irq(RX_FIFO_ERROR, S_ENABLE); - - /* Configure Spirit1 */ - st_lib_spirit_radio_persisten_rx(S_ENABLE); - st_lib_spirit_qi_set_sqi_threshold(SQI_TH_0); - st_lib_spirit_qi_sqi_check(S_ENABLE); - st_lib_spirit_qi_set_rssi_threshold_dbm(CCA_THRESHOLD); - st_lib_spirit_timer_set_rx_timeout_stop_condition(SQI_ABOVE_THRESHOLD); - SET_INFINITE_RX_TIMEOUT(); - st_lib_spirit_radio_afc_freeze_on_sync(S_ENABLE); - - /* Puts the SPIRIT1 in STANDBY mode (125us -> rx/tx) */ - spirit1_strobe(SPIRIT1_STROBE_STANDBY); - spirit_on = OFF; - CLEAR_RXBUF(); - CLEAR_TXBUF(); - - /* Initializes the mcu pin as input, used for IRQ */ - st_lib_radio_gpio_init(RADIO_GPIO_IRQ, RADIO_MODE_EXTI_IN); - - /* Configure the radio to route the IRQ signal to its GPIO 3 */ - st_lib_spirit_gpio_init(&(st_lib_s_gpio_init){SPIRIT_GPIO_IRQ, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, SPIRIT_GPIO_DIG_OUT_IRQ}); - - process_start(&spirit_radio_process, NULL); - - PRINTF("Spirit1 init done\n"); - return 0; -} -/*---------------------------------------------------------------------------*/ -static int -spirit_radio_prepare(const void *payload, unsigned short payload_len) -{ - PRINTF("Spirit1: prep %u\n", payload_len); - packet_is_prepared = 0; - - /* Checks if the payload length is supported */ - if(payload_len > MAX_PACKET_LEN) { - return RADIO_TX_ERR; - } - - /* Should we delay for an ack? */ -#if NULLRDC_CONF_802154_AUTOACK - frame802154_t info154; - wants_an_ack = 0; - if(payload_len > ACK_LEN - && frame802154_parse((char*)payload, payload_len, &info154) != 0) { - if(info154.fcf.frame_type == FRAME802154_DATAFRAME - && info154.fcf.ack_required != 0) { - wants_an_ack = 1; - } - } -#endif /* NULLRDC_CONF_802154_AUTOACK */ - - /* Sets the length of the packet to send */ - IRQ_DISABLE(); - spirit1_strobe(SPIRIT1_STROBE_FTX); - st_lib_spirit_pkt_basic_set_payload_length(payload_len); - st_lib_spirit_spi_write_linear_fifo(payload_len, (uint8_t *)payload); - IRQ_ENABLE(); - - PRINTF("PREPARE OUT\n"); - - packet_is_prepared = 1; - return RADIO_TX_OK; -} -/*---------------------------------------------------------------------------*/ -static int -spirit_radio_transmit(unsigned short payload_len) -{ - /* This function blocks until the packet has been transmitted */ - rtimer_clock_t rtimer_txdone, rtimer_rxack; - - PRINTF("TRANSMIT IN\n"); - if(!packet_is_prepared) { - return RADIO_TX_ERR; - } - - /* Stores the length of the packet to send */ - /* Others spirit_radio_prepare will be in hold */ - spirit_txbuf[0] = payload_len; - - /* Puts the SPIRIT1 in TX state */ - receiving_packet = 0; - spirit_set_ready_state(); - spirit1_strobe(SPIRIT1_STROBE_TX); - just_got_an_ack = 0; - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); - //BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 4 * RTIMER_SECOND/1000); //For GFSK with high data rate - BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 50 * RTIMER_SECOND/1000); //For FSK with low data rate - - /* Reset radio - needed for immediate RX of ack */ - CLEAR_TXBUF(); - CLEAR_RXBUF(); - IRQ_DISABLE(); - st_lib_spirit_irq_clear_status(); - spirit1_strobe(SPIRIT1_STROBE_SABORT); - BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); - spirit1_strobe(SPIRIT1_STROBE_READY); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 1 * RTIMER_SECOND/1000); - spirit1_strobe(SPIRIT1_STROBE_RX); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND/1000); - IRQ_ENABLE(); - -#if XXX_ACK_WORKAROUND - just_got_an_ack = 1; -#endif /* XXX_ACK_WORKAROUND */ - -#if NULLRDC_CONF_802154_AUTOACK - if (wants_an_ack) { - rtimer_txdone = RTIMER_NOW(); - BUSYWAIT_UNTIL(just_got_an_ack, 2 * RTIMER_SECOND/1000); - rtimer_rxack = RTIMER_NOW(); - - if(just_got_an_ack) { - ACKPRINTF("debug_ack: ack received after %u/%u ticks\n", - (uint32_t)(rtimer_rxack - rtimer_txdone), 2 * RTIMER_SECOND/1000); - } else { - ACKPRINTF("debug_ack: no ack received\n"); - } - } -#endif /* NULLRDC_CONF_802154_AUTOACK */ - - PRINTF("TRANSMIT OUT\n"); - - CLEAR_TXBUF(); - - packet_is_prepared = 0; - - clock_wait(1); - - return RADIO_TX_OK; -} -/*---------------------------------------------------------------------------*/ -static int spirit_radio_send(const void *payload, unsigned short payload_len) -{ - if(spirit_radio_prepare(payload, payload_len) == RADIO_TX_ERR) { - return RADIO_TX_ERR; - } - return spirit_radio_transmit(payload_len); - -} -/*---------------------------------------------------------------------------*/ -static int spirit_radio_read(void *buf, unsigned short bufsize) -{ - PRINTF("READ IN\n"); - - /* Checks if the RX buffer is empty */ - if(IS_RXBUF_EMPTY()) { - IRQ_DISABLE(); - CLEAR_RXBUF(); - spirit1_strobe(SPIRIT1_STROBE_SABORT); - BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); - spirit1_strobe(SPIRIT1_STROBE_READY); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 1 * RTIMER_SECOND/1000); - spirit1_strobe(SPIRIT1_STROBE_RX); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND/1000); - PRINTF("READ OUT RX BUF EMPTY\n"); - IRQ_ENABLE(); - return 0; - } - - if(bufsize < spirit_rxbuf[0]) { - /* If buf has the correct size */ - PRINTF("TOO SMALL BUF\n"); - return 0; - } else { - /* Copies the packet received */ - memcpy(buf, spirit_rxbuf + 1, spirit_rxbuf[0]); - - packetbuf_set_attr(PACKETBUF_ATTR_RSSI, last_rssi); //MGR - packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, last_lqi); //MGR - bufsize = spirit_rxbuf[0]; - CLEAR_RXBUF(); - - PRINTF("READ OUT\n"); - - return bufsize; - } - -} -/*---------------------------------------------------------------------------*/ -static int -spirit_radio_channel_clear(void) -{ - float rssi_value; - /* Local variable used to memorize the SPIRIT1 state */ - uint8_t spirit_state = ON; - - PRINTF("CHANNEL CLEAR IN\n"); - - if(spirit_on == OFF) { - /* Wakes up the SPIRIT1 */ - spirit_radio_on(); - spirit_state = OFF; - } - - /* */ - IRQ_DISABLE(); - spirit1_strobe(SPIRIT1_STROBE_SABORT); -/* SpiritCmdStrobeSabort();*/ - st_lib_spirit_irq_clear_status(); - IRQ_ENABLE(); - { - rtimer_clock_t timeout = RTIMER_NOW() + 5 * RTIMER_SECOND/1000; - do { - st_lib_spirit_refresh_status(); - } while((st_lib_g_x_status.MC_STATE != MC_STATE_READY) && (RTIMER_NOW() < timeout)); - if(RTIMER_NOW() < timeout) { - return 1; - } - } - - /* Stores the RSSI value */ - rssi_value = st_lib_spirit_qi_get_rssi_dbm(); - - /* Puts the SPIRIT1 in its previous state */ - if(spirit_state==OFF) { - spirit_radio_off(); - } else { - spirit1_strobe(SPIRIT1_STROBE_RX); -/* SpiritCmdStrobeRx();*/ - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 5 * RTIMER_SECOND/1000); - } - - PRINTF("CHANNEL CLEAR OUT\n"); - - /* Checks the RSSI value with the threshold */ - if(rssi_valueoff\n"); - if(spirit_on == ON) { - /* Disables the mcu to get IRQ from the SPIRIT1 */ - IRQ_DISABLE(); - - /* first stop rx/tx */ - spirit1_strobe(SPIRIT1_STROBE_SABORT); - - /* Clear any pending irqs */ - st_lib_spirit_irq_clear_status(); - - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND/1000); - if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) { - PRINTF("Spirit1: failed off->ready\n"); - return 1; - } - - /* Puts the SPIRIT1 in STANDBY */ - spirit1_strobe(SPIRIT1_STROBE_STANDBY); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_STANDBY, 5 * RTIMER_SECOND/1000); - if(SPIRIT1_STATUS() != SPIRIT1_STATE_STANDBY) { - PRINTF("Spirit1: failed off->stdby\n"); - return 1; - } - - spirit_on = OFF; - CLEAR_TXBUF(); - CLEAR_RXBUF(); - } - PRINTF("Spirit1: off.\n"); - return 0; -} -/*---------------------------------------------------------------------------*/ -static int spirit_radio_on(void) -{ - - PRINTF("Spirit1: on\n"); - spirit1_strobe(SPIRIT1_STROBE_SABORT); - BUSYWAIT_UNTIL(0, RTIMER_SECOND/2500); - if(spirit_on == OFF) { - IRQ_DISABLE(); - /* ensure we are in READY state as we go from there to Rx */ - spirit1_strobe(SPIRIT1_STROBE_READY); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND/1000); - if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) { - PRINTF("Spirit1: failed to turn on\n"); - while(1); - //return 1; - } - - /* now we go to Rx */ - spirit1_strobe(SPIRIT1_STROBE_RX); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 5 * RTIMER_SECOND/1000); - if(SPIRIT1_STATUS() != SPIRIT1_STATE_RX) { - PRINTF("Spirit1: failed to enter rx\n"); - while(1); - //return 1; - } - - /* Enables the mcu to get IRQ from the SPIRIT1 */ - IRQ_ENABLE(); - spirit_on = ON; - } - - return 0; -} -/*---------------------------------------------------------------------------*/ -static int interrupt_callback_in_progress = 0; -static int interrupt_callback_wants_poll = 0; -PROCESS_THREAD(spirit_radio_process, ev, data) -{ - PROCESS_BEGIN(); - PRINTF("Spirit1: process started\n"); - - while(1) { - int len; - - PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL); - PRINTF("Spirit1: polled\n"); - - packetbuf_clear(); - len = spirit_radio_read(packetbuf_dataptr(), PACKETBUF_SIZE); - - if(len > 0) { - -#if NULLRDC_CONF_802154_AUTOACK - /* Check if the packet has an ACK request */ - frame802154_t info154; - if(len > ACK_LEN && - frame802154_parse((char*)packetbuf_dataptr(), len, &info154) != 0) { - if(info154.fcf.frame_type == FRAME802154_DATAFRAME && - info154.fcf.ack_required != 0 && - linkaddr_cmp((linkaddr_t *)&info154.dest_addr, - &linkaddr_node_addr)) { - - -#if !XXX_ACK_WORKAROUND - /* Send an ACK packet */ - uint8_t ack_frame[ACK_LEN] = { - FRAME802154_ACKFRAME, - 0x00, - info154.seq - }; - IRQ_DISABLE(); - spirit1_strobe(SPIRIT1_STROBE_FTX); - st_lib_spirit_pkt_basic_set_payload_length((uint16_t) ACK_LEN); - st_lib_spirit_spi_write_linear_fifo((uint16_t) ACK_LEN, (uint8_t *) ack_frame); - - spirit_set_ready_state(); - IRQ_ENABLE(); - spirit1_strobe(SPIRIT1_STROBE_TX); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 1 * RTIMER_SECOND/1000); - ACKPRINTF("debug_ack: sent ack %d\n", ack_frame[2]); -#endif /* !XXX_ACK_WORKAROUND */ - } - } -#endif /* NULLRDC_CONF_802154_AUTOACK */ - - packetbuf_set_datalen(len); - NETSTACK_RDC.input(); - } - - if(!IS_RXBUF_EMPTY()) { - process_poll(&spirit_radio_process); - } - - if(interrupt_callback_wants_poll) { - spirit1_interrupt_callback(); - - if(SPIRIT1_STATUS() == SPIRIT1_STATE_READY) { - spirit1_strobe(SPIRIT1_STROBE_RX); - BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND/1000); - } - } - } - - PROCESS_END(); -} -/*---------------------------------------------------------------------------*/ -void -spirit1_interrupt_callback(void) -{ -#define INTPRINTF(...) // PRINTF - st_lib_spirit_irqs x_irq_status; - if (spirit_spi_busy() || interrupt_callback_in_progress) { - process_poll(&spirit_radio_process); - interrupt_callback_wants_poll = 1; - return; - } - - interrupt_callback_wants_poll = 0; - interrupt_callback_in_progress = 1; - - /* get interrupt source from radio */ - st_lib_spirit_irq_get_status(&x_irq_status); - st_lib_spirit_irq_clear_status(); - - if(x_irq_status.IRQ_RX_FIFO_ERROR) { - receiving_packet = 0; - interrupt_callback_in_progress = 0; - spirit1_strobe(SPIRIT1_STROBE_FRX); - return; - } - - if(x_irq_status.IRQ_TX_FIFO_ERROR) { - receiving_packet = 0; - interrupt_callback_in_progress = 0; - spirit1_strobe(SPIRIT1_STROBE_FTX); - return; - } - - /* The IRQ_VALID_SYNC is used to notify a new packet is coming */ - if(x_irq_status.IRQ_VALID_SYNC) { - INTPRINTF("SYNC\n"); - receiving_packet = 1; - } - - /* The IRQ_TX_DATA_SENT notifies the packet received. Puts the SPIRIT1 in RX */ - if(x_irq_status.IRQ_TX_DATA_SENT) { - spirit1_strobe(SPIRIT1_STROBE_RX); -/* SpiritCmdStrobeRx();*/ - INTPRINTF("SENT\n"); - CLEAR_TXBUF(); - interrupt_callback_in_progress = 0; - return; - } - - /* The IRQ_RX_DATA_READY notifies a new packet arrived */ - if(x_irq_status.IRQ_RX_DATA_READY) { - st_lib_spirit_spi_read_linear_fifo(st_lib_spirit_linear_fifo_read_num_elements_rx_fifo(), - &spirit_rxbuf[1]); - spirit_rxbuf[0] = st_lib_spirit_pkt_basic_get_received_pkt_length(); - spirit1_strobe(SPIRIT1_STROBE_FRX); - - INTPRINTF("RECEIVED\n"); - - process_poll(&spirit_radio_process); - - last_rssi = (packetbuf_attr_t) st_lib_spirit_qi_get_rssi(); //MGR - last_lqi = (packetbuf_attr_t) st_lib_spirit_qi_get_lqi(); //MGR - - receiving_packet = 0; - -#if NULLRDC_CONF_802154_AUTOACK - if (spirit_rxbuf[0] == ACK_LEN) { - /* For debugging purposes we assume this is an ack for us */ - just_got_an_ack = 1; - } -#endif /* NULLRDC_CONF_802154_AUTOACK */ - - interrupt_callback_in_progress = 0; - return; - } - - if(x_irq_status.IRQ_RX_DATA_DISC) - { - /* RX command - to ensure the device will be ready for the next reception */ - if(x_irq_status.IRQ_RX_TIMEOUT) { - st_lib_spirit_cmd_strobe_flush_rx_fifo(); - rx_timeout = SET; - } - } - - interrupt_callback_in_progress = 0; -} -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#include "spirit1.h" +#include "spirit1-arch.h" +#include "stm32l1xx.h" +#include "contiki.h" +#include "net/mac/frame802154.h" +#include "net/netstack.h" +#include "net/packetbuf.h" +#include "net/rime/rimestats.h" +#include "spirit1-arch.h" +#include +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +/* MGR extern st_lib_spirit_irqs st_lib_x_irq_status; */ +extern volatile st_lib_spirit_flag_status rx_timeout; +/*---------------------------------------------------------------------------*/ +#define XXX_ACK_WORKAROUND 1 +/*---------------------------------------------------------------------------*/ +#define DEBUG 0 +#if DEBUG +#include +#define PRINTF(...) printf(__VA_ARGS__) +#else +#define PRINTF(...) +#endif + +/*---------------------------------------------------------------------------*/ +#define BUSYWAIT_UNTIL(cond, max_time) \ + do { \ + rtimer_clock_t t0; \ + t0 = RTIMER_NOW(); \ + while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))) ; \ + } while(0) + +/*---------------------------------------------------------------------------*/ +#define CLEAR_TXBUF() (spirit_txbuf[0] = 0) +#define CLEAR_RXBUF() (spirit_rxbuf[0] = 0) +#define IS_TXBUF_EMPTY() (spirit_txbuf[0] == 0) +#define IS_RXBUF_EMPTY() (spirit_rxbuf[0] == 0) +#define IS_RXBUF_FULL() (spirit_rxbuf[0] != 0) +/*---------------------------------------------------------------------------*/ +/* transceiver state. */ +#define ON 0 +#define OFF 1 +/*---------------------------------------------------------------------------*/ +static volatile unsigned int spirit_on = OFF; +static volatile uint8_t receiving_packet = 0; +static packetbuf_attr_t last_rssi = 0; /* MGR */ +static packetbuf_attr_t last_lqi = 0; /* MGR */ +/*---------------------------------------------------------------------------*/ +/* + * The buffers which hold incoming data. + * The +1 because of the first byte, + * which will contain the length of the packet. + */ +static uint8_t spirit_rxbuf[MAX_PACKET_LEN + 1]; +static uint8_t spirit_txbuf[MAX_PACKET_LEN + 1 - SPIRIT_MAX_FIFO_LEN]; +void st_lib_spirit_management_set_frequency_base(uint32_t); +/*---------------------------------------------------------------------------*/ +static int just_got_an_ack = 0; /* Interrupt callback just detected an ack */ +#if NULLRDC_CONF_802154_AUTOACK +#define ACK_LEN 3 +static int wants_an_ack = 0; /* The packet sent expects an ack */ +/* static int just_got_an_ack = 0; / * Interrupt callback just detected an ack * / */ +/* #define ACKPRINTF printf */ +#define ACKPRINTF(...) +#endif /* NULLRDC_CONF_802154_AUTOACK */ +/*---------------------------------------------------------------------------*/ +static int packet_is_prepared = 0; +/*---------------------------------------------------------------------------*/ +PROCESS(spirit_radio_process, "SPIRIT radio driver"); +/*---------------------------------------------------------------------------*/ +static int spirit_radio_init(void); +static int spirit_radio_prepare(const void *payload, unsigned short payload_len); +static int spirit_radio_transmit(unsigned short payload_len); +static int spirit_radio_send(const void *data, unsigned short len); +static int spirit_radio_read(void *buf, unsigned short bufsize); +static int spirit_radio_channel_clear(void); +static int spirit_radio_receiving_packet(void); +static int spirit_radio_pending_packet(void); +static int spirit_radio_on(void); +static int spirit_radio_off(void); +/*---------------------------------------------------------------------------*/ +const struct radio_driver spirit_radio_driver = +{ + spirit_radio_init, + spirit_radio_prepare, + spirit_radio_transmit, + spirit_radio_send, + spirit_radio_read, + spirit_radio_channel_clear, + spirit_radio_receiving_packet, + spirit_radio_pending_packet, + spirit_radio_on, + spirit_radio_off, +}; +/*---------------------------------------------------------------------------*/ +void +spirit1_printstatus(void) +{ + int s = SPIRIT1_STATUS(); + if(s == SPIRIT1_STATE_STANDBY) { + printf("spirit1: SPIRIT1_STATE_STANDBY\n"); + } else if(s == SPIRIT1_STATE_READY) { + printf("spirit1: SPIRIT1_STATE_READY\n"); + } else if(s == SPIRIT1_STATE_TX) { + printf("spirit1: SPIRIT1_STATE_TX\n"); + } else if(s == SPIRIT1_STATE_RX) { + printf("spirit1: SPIRIT1_STATE_RX\n"); + } else { + printf("spirit1: status: %d\n", s); + } +} +/*---------------------------------------------------------------------------*/ +/* Strobe a command. The rationale for this is to clean up the messy legacy code. */ +static void +spirit1_strobe(uint8_t s) +{ + st_lib_spirit_cmd_strobe_command(s); +} +/*---------------------------------------------------------------------------*/ +void +spirit_set_ready_state(void) +{ + PRINTF("READY IN\n"); + + st_lib_spirit_irq_clear_status(); + IRQ_DISABLE(); + + if(SPIRIT1_STATUS() == SPIRIT1_STATE_STANDBY) { + spirit1_strobe(SPIRIT1_STROBE_READY); + } else if(SPIRIT1_STATUS() == SPIRIT1_STATE_RX) { + spirit1_strobe(SPIRIT1_STROBE_SABORT); + st_lib_spirit_irq_clear_status(); + } + + IRQ_ENABLE(); + + PRINTF("READY OUT\n"); +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_init(void) +{ + + PRINTF("RADIO INIT IN\n"); + + st_lib_spirit_spi_init(); + + /* Configure radio shut-down (SDN) pin and activate radio */ + st_lib_radio_gpio_init(RADIO_GPIO_SDN, RADIO_MODE_GPIO_OUT); + + /* Configures the SPIRIT1 library */ + st_lib_spirit_radio_set_xtal_frequency(XTAL_FREQUENCY); + st_lib_spirit_management_set_frequency_base(XTAL_FREQUENCY); + + /* wake up to READY state */ + /* weirdly enough, this *should* actually *set* the pin, not clear it! The pins is declared as GPIO_pin13 == 0x2000 */ + RADIO_GPIO_SDN_PORT->BSRR = RADIO_GPIO_SDN_PIN; + st_lib_hal_gpio_write_pin(RADIO_GPIO_SDN_PORT, RADIO_GPIO_SDN_PIN, GPIO_PIN_RESET); + + /* wait minimum 1.5 ms to allow SPIRIT1 a proper boot-up sequence */ + BUSYWAIT_UNTIL(0, 3 * RTIMER_SECOND / 2000); + + /* Soft reset of core */ + spirit1_strobe(SPIRIT1_STROBE_SRES); + + /* Configures the SPIRIT1 radio part */ + st_lib_s_radio_init x_radio_init = { + /* XTAL_FREQUENCY, */ + XTAL_OFFSET_PPM, + BASE_FREQUENCY, + CHANNEL_SPACE, + CHANNEL_NUMBER, + MODULATION_SELECT, + DATARATE, + FREQ_DEVIATION, + BANDWIDTH + }; + st_lib_spirit_radio_init(&x_radio_init); + st_lib_spirit_radio_set_xtal_frequency(XTAL_FREQUENCY); + st_lib_spirit_radio_set_pa_level_dbm(0, POWER_DBM); + st_lib_spirit_radio_set_pa_level_max_index(0); + + /* Configures the SPIRIT1 packet handler part*/ + st_lib_pkt_basic_init x_basic_init = { + PREAMBLE_LENGTH, + SYNC_LENGTH, + SYNC_WORD, + LENGTH_TYPE, + LENGTH_WIDTH, + CRC_MODE, + CONTROL_LENGTH, + EN_ADDRESS, + EN_FEC, + EN_WHITENING + }; + st_lib_spirit_pkt_basic_init(&x_basic_init); + + /* Enable the following interrupt sources, routed to GPIO */ + st_lib_spirit_irq_de_init(NULL); + st_lib_spirit_irq_clear_status(); + st_lib_spirit_irq(TX_DATA_SENT, S_ENABLE); + st_lib_spirit_irq(RX_DATA_READY, S_ENABLE); + st_lib_spirit_irq(VALID_SYNC, S_ENABLE); + st_lib_spirit_irq(RX_DATA_DISC, S_ENABLE); + st_lib_spirit_irq(TX_FIFO_ERROR, S_ENABLE); + st_lib_spirit_irq(RX_FIFO_ERROR, S_ENABLE); + + /* Configure Spirit1 */ + st_lib_spirit_radio_persisten_rx(S_ENABLE); + st_lib_spirit_qi_set_sqi_threshold(SQI_TH_0); + st_lib_spirit_qi_sqi_check(S_ENABLE); + st_lib_spirit_qi_set_rssi_threshold_dbm(CCA_THRESHOLD); + st_lib_spirit_timer_set_rx_timeout_stop_condition(SQI_ABOVE_THRESHOLD); + SET_INFINITE_RX_TIMEOUT(); + st_lib_spirit_radio_afc_freeze_on_sync(S_ENABLE); + + /* Puts the SPIRIT1 in STANDBY mode (125us -> rx/tx) */ + spirit1_strobe(SPIRIT1_STROBE_STANDBY); + spirit_on = OFF; + CLEAR_RXBUF(); + CLEAR_TXBUF(); + + /* Initializes the mcu pin as input, used for IRQ */ + st_lib_radio_gpio_init(RADIO_GPIO_IRQ, RADIO_MODE_EXTI_IN); + + /* Configure the radio to route the IRQ signal to its GPIO 3 */ + st_lib_spirit_gpio_init(&(st_lib_s_gpio_init){SPIRIT_GPIO_IRQ, SPIRIT_GPIO_MODE_DIGITAL_OUTPUT_LP, SPIRIT_GPIO_DIG_OUT_IRQ }); + + process_start(&spirit_radio_process, NULL); + + PRINTF("Spirit1 init done\n"); + return 0; +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_prepare(const void *payload, unsigned short payload_len) +{ + PRINTF("Spirit1: prep %u\n", payload_len); + packet_is_prepared = 0; + + /* Checks if the payload length is supported */ + if(payload_len > MAX_PACKET_LEN) { + return RADIO_TX_ERR; + } + + /* Should we delay for an ack? */ +#if NULLRDC_CONF_802154_AUTOACK + frame802154_t info154; + wants_an_ack = 0; + if(payload_len > ACK_LEN + && frame802154_parse((char *)payload, payload_len, &info154) != 0) { + if(info154.fcf.frame_type == FRAME802154_DATAFRAME + && info154.fcf.ack_required != 0) { + wants_an_ack = 1; + } + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + /* Sets the length of the packet to send */ + IRQ_DISABLE(); + spirit1_strobe(SPIRIT1_STROBE_FTX); + st_lib_spirit_pkt_basic_set_payload_length(payload_len); + st_lib_spirit_spi_write_linear_fifo(payload_len, (uint8_t *)payload); + IRQ_ENABLE(); + + PRINTF("PREPARE OUT\n"); + + packet_is_prepared = 1; + return RADIO_TX_OK; +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_transmit(unsigned short payload_len) +{ + /* This function blocks until the packet has been transmitted */ + rtimer_clock_t rtimer_txdone, rtimer_rxack; + + PRINTF("TRANSMIT IN\n"); + if(!packet_is_prepared) { + return RADIO_TX_ERR; + } + + /* Stores the length of the packet to send */ + /* Others spirit_radio_prepare will be in hold */ + spirit_txbuf[0] = payload_len; + + /* Puts the SPIRIT1 in TX state */ + receiving_packet = 0; + spirit_set_ready_state(); + spirit1_strobe(SPIRIT1_STROBE_TX); + just_got_an_ack = 0; + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND / 1000); + /* BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 4 * RTIMER_SECOND/1000); //For GFSK with high data rate */ + BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 50 * RTIMER_SECOND / 1000); /* For FSK with low data rate */ + + /* Reset radio - needed for immediate RX of ack */ + CLEAR_TXBUF(); + CLEAR_RXBUF(); + IRQ_DISABLE(); + st_lib_spirit_irq_clear_status(); + spirit1_strobe(SPIRIT1_STROBE_SABORT); + BUSYWAIT_UNTIL(0, RTIMER_SECOND / 2500); + spirit1_strobe(SPIRIT1_STROBE_READY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 1 * RTIMER_SECOND / 1000); + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND / 1000); + IRQ_ENABLE(); + +#if XXX_ACK_WORKAROUND + just_got_an_ack = 1; +#endif /* XXX_ACK_WORKAROUND */ + +#if NULLRDC_CONF_802154_AUTOACK + if(wants_an_ack) { + rtimer_txdone = RTIMER_NOW(); + BUSYWAIT_UNTIL(just_got_an_ack, 2 * RTIMER_SECOND / 1000); + rtimer_rxack = RTIMER_NOW(); + + if(just_got_an_ack) { + ACKPRINTF("debug_ack: ack received after %u/%u ticks\n", + (uint32_t)(rtimer_rxack - rtimer_txdone), 2 * RTIMER_SECOND / 1000); + } else { + ACKPRINTF("debug_ack: no ack received\n"); + } + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + PRINTF("TRANSMIT OUT\n"); + + CLEAR_TXBUF(); + + packet_is_prepared = 0; + + clock_wait(1); + + return RADIO_TX_OK; +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_send(const void *payload, unsigned short payload_len) +{ + if(spirit_radio_prepare(payload, payload_len) == RADIO_TX_ERR) { + return RADIO_TX_ERR; + } + return spirit_radio_transmit(payload_len); +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_read(void *buf, unsigned short bufsize) +{ + PRINTF("READ IN\n"); + + /* Checks if the RX buffer is empty */ + if(IS_RXBUF_EMPTY()) { + IRQ_DISABLE(); + CLEAR_RXBUF(); + spirit1_strobe(SPIRIT1_STROBE_SABORT); + BUSYWAIT_UNTIL(0, RTIMER_SECOND / 2500); + spirit1_strobe(SPIRIT1_STROBE_READY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 1 * RTIMER_SECOND / 1000); + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND / 1000); + PRINTF("READ OUT RX BUF EMPTY\n"); + IRQ_ENABLE(); + return 0; + } + + if(bufsize < spirit_rxbuf[0]) { + /* If buf has the correct size */ + PRINTF("TOO SMALL BUF\n"); + return 0; + } else { + /* Copies the packet received */ + memcpy(buf, spirit_rxbuf + 1, spirit_rxbuf[0]); + + packetbuf_set_attr(PACKETBUF_ATTR_RSSI, last_rssi); /* MGR */ + packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, last_lqi); /* MGR */ + bufsize = spirit_rxbuf[0]; + CLEAR_RXBUF(); + + PRINTF("READ OUT\n"); + + return bufsize; + } +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_channel_clear(void) +{ + float rssi_value; + /* Local variable used to memorize the SPIRIT1 state */ + uint8_t spirit_state = ON; + + PRINTF("CHANNEL CLEAR IN\n"); + + if(spirit_on == OFF) { + /* Wakes up the SPIRIT1 */ + spirit_radio_on(); + spirit_state = OFF; + } + + /* */ + IRQ_DISABLE(); + spirit1_strobe(SPIRIT1_STROBE_SABORT); +/* SpiritCmdStrobeSabort();*/ + st_lib_spirit_irq_clear_status(); + IRQ_ENABLE(); + { + rtimer_clock_t timeout = RTIMER_NOW() + 5 * RTIMER_SECOND / 1000; + do { + st_lib_spirit_refresh_status(); + } while((st_lib_g_x_status.MC_STATE != MC_STATE_READY) && (RTIMER_NOW() < timeout)); + if(RTIMER_NOW() < timeout) { + return 1; + } + } + + /* Stores the RSSI value */ + rssi_value = st_lib_spirit_qi_get_rssi_dbm(); + + /* Puts the SPIRIT1 in its previous state */ + if(spirit_state == OFF) { + spirit_radio_off(); + } else { + spirit1_strobe(SPIRIT1_STROBE_RX); +/* SpiritCmdStrobeRx();*/ + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 5 * RTIMER_SECOND / 1000); + } + + PRINTF("CHANNEL CLEAR OUT\n"); + + /* Checks the RSSI value with the threshold */ + if(rssi_value < CCA_THRESHOLD) { + return 0; + } else { + return 1; + } +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_receiving_packet(void) +{ + return receiving_packet; +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_pending_packet(void) +{ + PRINTF("PENDING PACKET\n"); + return !IS_RXBUF_EMPTY(); +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_off(void) +{ + PRINTF("Spirit1: ->off\n"); + if(spirit_on == ON) { + /* Disables the mcu to get IRQ from the SPIRIT1 */ + IRQ_DISABLE(); + + /* first stop rx/tx */ + spirit1_strobe(SPIRIT1_STROBE_SABORT); + + /* Clear any pending irqs */ + st_lib_spirit_irq_clear_status(); + + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND / 1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) { + PRINTF("Spirit1: failed off->ready\n"); + return 1; + } + + /* Puts the SPIRIT1 in STANDBY */ + spirit1_strobe(SPIRIT1_STROBE_STANDBY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_STANDBY, 5 * RTIMER_SECOND / 1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_STANDBY) { + PRINTF("Spirit1: failed off->stdby\n"); + return 1; + } + + spirit_on = OFF; + CLEAR_TXBUF(); + CLEAR_RXBUF(); + } + PRINTF("Spirit1: off.\n"); + return 0; +} +/*---------------------------------------------------------------------------*/ +static int +spirit_radio_on(void) +{ + + PRINTF("Spirit1: on\n"); + spirit1_strobe(SPIRIT1_STROBE_SABORT); + BUSYWAIT_UNTIL(0, RTIMER_SECOND / 2500); + if(spirit_on == OFF) { + IRQ_DISABLE(); + /* ensure we are in READY state as we go from there to Rx */ + spirit1_strobe(SPIRIT1_STROBE_READY); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_READY, 5 * RTIMER_SECOND / 1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_READY) { + PRINTF("Spirit1: failed to turn on\n"); + while(1) ; + /* return 1; */ + } + + /* now we go to Rx */ + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 5 * RTIMER_SECOND / 1000); + if(SPIRIT1_STATUS() != SPIRIT1_STATE_RX) { + PRINTF("Spirit1: failed to enter rx\n"); + while(1) ; + /* return 1; */ + } + + /* Enables the mcu to get IRQ from the SPIRIT1 */ + IRQ_ENABLE(); + spirit_on = ON; + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +static int interrupt_callback_in_progress = 0; +static int interrupt_callback_wants_poll = 0; +PROCESS_THREAD(spirit_radio_process, ev, data) +{ + PROCESS_BEGIN(); + PRINTF("Spirit1: process started\n"); + + while(1) { + int len; + + PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL); + PRINTF("Spirit1: polled\n"); + + packetbuf_clear(); + len = spirit_radio_read(packetbuf_dataptr(), PACKETBUF_SIZE); + + if(len > 0) { + +#if NULLRDC_CONF_802154_AUTOACK + /* Check if the packet has an ACK request */ + frame802154_t info154; + if(len > ACK_LEN && + frame802154_parse((char *)packetbuf_dataptr(), len, &info154) != 0) { + if(info154.fcf.frame_type == FRAME802154_DATAFRAME && + info154.fcf.ack_required != 0 && + linkaddr_cmp((linkaddr_t *)&info154.dest_addr, + &linkaddr_node_addr)) { + +#if !XXX_ACK_WORKAROUND + /* Send an ACK packet */ + uint8_t ack_frame[ACK_LEN] = { + FRAME802154_ACKFRAME, + 0x00, + info154.seq + }; + IRQ_DISABLE(); + spirit1_strobe(SPIRIT1_STROBE_FTX); + st_lib_spirit_pkt_basic_set_payload_length((uint16_t)ACK_LEN); + st_lib_spirit_spi_write_linear_fifo((uint16_t)ACK_LEN, (uint8_t *)ack_frame); + + spirit_set_ready_state(); + IRQ_ENABLE(); + spirit1_strobe(SPIRIT1_STROBE_TX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_TX, 1 * RTIMER_SECOND / 1000); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() != SPIRIT1_STATE_TX, 1 * RTIMER_SECOND / 1000); + ACKPRINTF("debug_ack: sent ack %d\n", ack_frame[2]); +#endif /* !XXX_ACK_WORKAROUND */ + } + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + packetbuf_set_datalen(len); + NETSTACK_RDC.input(); + } + + if(!IS_RXBUF_EMPTY()) { + process_poll(&spirit_radio_process); + } + + if(interrupt_callback_wants_poll) { + spirit1_interrupt_callback(); + + if(SPIRIT1_STATUS() == SPIRIT1_STATE_READY) { + spirit1_strobe(SPIRIT1_STROBE_RX); + BUSYWAIT_UNTIL(SPIRIT1_STATUS() == SPIRIT1_STATE_RX, 1 * RTIMER_SECOND / 1000); + } + } + } + + PROCESS_END(); +} +/*---------------------------------------------------------------------------*/ +void +spirit1_interrupt_callback(void) +{ +#define INTPRINTF(...) /* PRINTF */ + st_lib_spirit_irqs x_irq_status; + if(spirit_spi_busy() || interrupt_callback_in_progress) { + process_poll(&spirit_radio_process); + interrupt_callback_wants_poll = 1; + return; + } + + interrupt_callback_wants_poll = 0; + interrupt_callback_in_progress = 1; + + /* get interrupt source from radio */ + st_lib_spirit_irq_get_status(&x_irq_status); + st_lib_spirit_irq_clear_status(); + + if(x_irq_status.IRQ_RX_FIFO_ERROR) { + receiving_packet = 0; + interrupt_callback_in_progress = 0; + spirit1_strobe(SPIRIT1_STROBE_FRX); + return; + } + + if(x_irq_status.IRQ_TX_FIFO_ERROR) { + receiving_packet = 0; + interrupt_callback_in_progress = 0; + spirit1_strobe(SPIRIT1_STROBE_FTX); + return; + } + + /* The IRQ_VALID_SYNC is used to notify a new packet is coming */ + if(x_irq_status.IRQ_VALID_SYNC) { + INTPRINTF("SYNC\n"); + receiving_packet = 1; + } + + /* The IRQ_TX_DATA_SENT notifies the packet received. Puts the SPIRIT1 in RX */ + if(x_irq_status.IRQ_TX_DATA_SENT) { + spirit1_strobe(SPIRIT1_STROBE_RX); +/* SpiritCmdStrobeRx();*/ + INTPRINTF("SENT\n"); + CLEAR_TXBUF(); + interrupt_callback_in_progress = 0; + return; + } + + /* The IRQ_RX_DATA_READY notifies a new packet arrived */ + if(x_irq_status.IRQ_RX_DATA_READY) { + st_lib_spirit_spi_read_linear_fifo(st_lib_spirit_linear_fifo_read_num_elements_rx_fifo(), + &spirit_rxbuf[1]); + spirit_rxbuf[0] = st_lib_spirit_pkt_basic_get_received_pkt_length(); + spirit1_strobe(SPIRIT1_STROBE_FRX); + + INTPRINTF("RECEIVED\n"); + + process_poll(&spirit_radio_process); + + last_rssi = (packetbuf_attr_t)st_lib_spirit_qi_get_rssi(); /* MGR */ + last_lqi = (packetbuf_attr_t)st_lib_spirit_qi_get_lqi(); /* MGR */ + + receiving_packet = 0; + +#if NULLRDC_CONF_802154_AUTOACK + if(spirit_rxbuf[0] == ACK_LEN) { + /* For debugging purposes we assume this is an ack for us */ + just_got_an_ack = 1; + } +#endif /* NULLRDC_CONF_802154_AUTOACK */ + + interrupt_callback_in_progress = 0; + return; + } + + if(x_irq_status.IRQ_RX_DATA_DISC) { + /* RX command - to ensure the device will be ready for the next reception */ + if(x_irq_status.IRQ_RX_TIMEOUT) { + st_lib_spirit_cmd_strobe_flush_rx_fifo(); + rx_timeout = SET; + } + } + + interrupt_callback_in_progress = 0; +} +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/spirit1.h b/platform/stm32nucleo-spirit1/spirit1.h index 5f151846b..6e95bd3d1 100644 --- a/platform/stm32nucleo-spirit1/spirit1.h +++ b/platform/stm32nucleo-spirit1/spirit1.h @@ -1,46 +1,46 @@ -/* - * Copyright (c) 2012, STMicroelectronics. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the Contiki operating system. - * - */ -/*---------------------------------------------------------------------------*/ -#ifndef __SPIRIT_H__ -#define __SPIRIT_H__ -/*---------------------------------------------------------------------------*/ -#include "radio.h" -#include "SPIRIT_Config.h" -#include "spirit1-config.h" -#include "spirit1_appli.h" -#include "spirit1-const.h" -/*---------------------------------------------------------------------------*/ -extern const struct radio_driver spirit_radio_driver; -void spirit1_interrupt_callback(void); -/*---------------------------------------------------------------------------*/ -#endif /* __SPIRIT_H__ */ -/*---------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the Contiki operating system. + * + */ +/*---------------------------------------------------------------------------*/ +#ifndef __SPIRIT_H__ +#define __SPIRIT_H__ +/*---------------------------------------------------------------------------*/ +#include "radio.h" +#include "SPIRIT_Config.h" +#include "spirit1-config.h" +#include "spirit1_appli.h" +#include "spirit1-const.h" +/*---------------------------------------------------------------------------*/ +extern const struct radio_driver spirit_radio_driver; +void spirit1_interrupt_callback(void); +/*---------------------------------------------------------------------------*/ +#endif /* __SPIRIT_H__ */ +/*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/st-lib.h b/platform/stm32nucleo-spirit1/st-lib.h index cf6930110..d49b810b5 100644 --- a/platform/stm32nucleo-spirit1/st-lib.h +++ b/platform/stm32nucleo-spirit1/st-lib.h @@ -1,39 +1,33 @@ -/** -****************************************************************************** -* @file st-lib.h -* @author System LAB -* @version V1.0.0 -* @date 30-July-2015 -* @brief Contiki style wrapping library for STM32Cube HAL APIs -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ /*---------------------------------------------------------------------------*/ /** * \defgroup stm32nucleo-spirit1 STM32Cube HAL APIs @@ -73,7 +67,6 @@ #define st_lib_spirit_spi_write_linear_fifo(...) SpiritSpiWriteLinearFifo(__VA_ARGS__) /*---------------------------------------------------------------------------*/ - /*---------------------------------------------------------------------------*/ /* radio_gpio.h */ #include "radio_gpio.h" @@ -241,7 +234,6 @@ /* stm32l1xx_hal_rcc.h */ #include "stm32l1xx_hal_rcc.h" - #define st_lib_tim2_clk_enable(...) __TIM2_CLK_ENABLE(__VA_ARGS__) /*---------------------------------------------------------------------------*/ @@ -274,7 +266,6 @@ #define st_lib_hal_tim_oc_config_channel(...) HAL_TIM_OC_ConfigChannel(__VA_ARGS__) /*---------------------------------------------------------------------------*/ - /*---------------------------------------------------------------------------*/ /* stm32l1xx_hal_uart.h */ #include "stm32l1xx_hal_uart.h" diff --git a/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h b/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h index f8d3a60ee..77ff95ca6 100644 --- a/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h +++ b/platform/stm32nucleo-spirit1/stm32l-spirit1-config.h @@ -1,98 +1,102 @@ -/** - ****************************************************************************** - * @file stm32l-spirit1-config.h - * @author MCD Application Team - * @version V3.4.0 - * @date 29-June-2012 - * @brief Evaluation board specific configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L_SPIRIT1_CONFIG_H -#define __STM32L_SPIRIT1_CONFIG_H - -/* Includes ------------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* Define the STM32F10x hardware depending on the used evaluation board */ -#ifdef USE_STM3210B_EVAL - #define USB_DISCONNECT GPIOD - #define USB_DISCONNECT_PIN GPIO_PIN_9 - #define RCC_APB2Periph_GPIO_DISCONNECT RCC_APB2Periph_GPIOD - #define EVAL_COM1_IRQHandler USART1_IRQHandler - -#elif defined (USE_STM3210E_EVAL) - #define USB_DISCONNECT GPIOB - #define USB_DISCONNECT_PIN GPIO_PIN_14 - #define RCC_APB2Periph_GPIO_DISCONNECT RCC_APB2Periph_GPIOB - #define EVAL_COM1_IRQHandler USART1_IRQHandler - -#elif defined (USE_STM3210C_EVAL) - #define USB_DISCONNECT 0 - #define USB_DISCONNECT_PIN 0 - #define RCC_APB2Periph_GPIO_DISCONNECT 0 - #define EVAL_COM1_IRQHandler USART2_IRQHandler - -#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL) - /* - For STM32L15xx devices it is possible to use the internal USB pullup - controlled by register SYSCFG_PMC (refer to RM0038 reference manual for - more details). - It is also possible to use external pullup (and disable the internal pullup) - by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h - and configuring the right pin to be used for the external pull up configuration. - To have more details on how to use an external pull up, please refer to - STM3210E-EVAL evaluation board manuals. - */ - /* Uncomment the following define to use an external pull up instead of the - integrated STM32L15xx internal pull up. In this case make sure to set up - correctly the external required hardware and the GPIO defines below.*/ -/* #define USB_USE_EXTERNAL_PULLUP */ - - #if !defined(USB_USE_EXTERNAL_PULLUP) - #define STM32L15_USB_CONNECT SYSCFG_USBPuCmd(ENABLE) - #define STM32L15_USB_DISCONNECT SYSCFG_USBPuCmd(DISABLE) - - #elif defined(USB_USE_EXTERNAL_PULLUP) - /* PA0 is chosen just as illustrating example, you should modify the defines - below according to your hardware configuration. */ - #define USB_DISCONNECT GPIOA - #define USB_DISCONNECT_PIN GPIO_PIN_0 - #define RCC_AHBPeriph_GPIO_DISCONNECT RCC_AHBPeriph_GPIOA - #define STM32L15_USB_CONNECT GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN) - #define STM32L15_USB_DISCONNECT GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN) - #endif /* USB_USE_EXTERNAL_PULLUP */ - -#ifdef USE_STM32L152_EVAL - #define EVAL_COM1_IRQHandler USART2_IRQHandler -#elif defined (USE_STM32L152D_EVAL) - #define EVAL_COM1_IRQHandler USART1_IRQHandler -#endif /*USE_STM32L152_EVAL*/ - -#endif /* USE_STM3210B_EVAL */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __STM32L_SPIRIT1_CONFIG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*----------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L_SPIRIT1_CONFIG_H +#define __STM32L_SPIRIT1_CONFIG_H + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Define the STM32F10x hardware depending on the used evaluation board */ +#ifdef USE_STM3210B_EVAL +#define USB_DISCONNECT GPIOD +#define USB_DISCONNECT_PIN GPIO_PIN_9 +#define RCC_APB2Periph_GPIO_DISCONNECT RCC_APB2Periph_GPIOD +#define EVAL_COM1_IRQHandler USART1_IRQHandler + +#elif defined(USE_STM3210E_EVAL) +#define USB_DISCONNECT GPIOB +#define USB_DISCONNECT_PIN GPIO_PIN_14 +#define RCC_APB2Periph_GPIO_DISCONNECT RCC_APB2Periph_GPIOB +#define EVAL_COM1_IRQHandler USART1_IRQHandler + +#elif defined(USE_STM3210C_EVAL) +#define USB_DISCONNECT 0 +#define USB_DISCONNECT_PIN 0 +#define RCC_APB2Periph_GPIO_DISCONNECT 0 +#define EVAL_COM1_IRQHandler USART2_IRQHandler + +#elif defined(USE_STM32L152_EVAL) || defined(USE_STM32L152D_EVAL) +/* + For STM32L15xx devices it is possible to use the internal USB pullup + controlled by register SYSCFG_PMC (refer to RM0038 reference manual for + more details). + It is also possible to use external pullup (and disable the internal pullup) + by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h + and configuring the right pin to be used for the external pull up configuration. + To have more details on how to use an external pull up, please refer to + STM3210E-EVAL evaluation board manuals. + */ +/* Uncomment the following define to use an external pull up instead of the + integrated STM32L15xx internal pull up. In this case make sure to set up + correctly the external required hardware and the GPIO defines below.*/ +/* #define USB_USE_EXTERNAL_PULLUP */ + +#if !defined(USB_USE_EXTERNAL_PULLUP) +#define STM32L15_USB_CONNECT SYSCFG_USBPuCmd(ENABLE) +#define STM32L15_USB_DISCONNECT SYSCFG_USBPuCmd(DISABLE) + +#elif defined(USB_USE_EXTERNAL_PULLUP) +/* PA0 is chosen just as illustrating example, you should modify the defines + below according to your hardware configuration. */ +#define USB_DISCONNECT GPIOA +#define USB_DISCONNECT_PIN GPIO_PIN_0 +#define RCC_AHBPeriph_GPIO_DISCONNECT RCC_AHBPeriph_GPIOA +#define STM32L15_USB_CONNECT GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN) +#define STM32L15_USB_DISCONNECT GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN) +#endif /* USB_USE_EXTERNAL_PULLUP */ + +#ifdef USE_STM32L152_EVAL +#define EVAL_COM1_IRQHandler USART2_IRQHandler +#elif defined(USE_STM32L152D_EVAL) +#define EVAL_COM1_IRQHandler USART1_IRQHandler +#endif /*USE_STM32L152_EVAL*/ + +#endif /* USE_STM3210B_EVAL */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32L_SPIRIT1_CONFIG_H */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/stm32nucleo-spirit1/uart-msg.c b/platform/stm32nucleo-spirit1/uart-msg.c index 84e552ea1..ebb703785 100644 --- a/platform/stm32nucleo-spirit1/uart-msg.c +++ b/platform/stm32nucleo-spirit1/uart-msg.c @@ -1,93 +1,90 @@ -/** -****************************************************************************** -* @file uart-msg.c -* @author System LAB -* @version V1.0.0 -* @date 17-June-2015 -****************************************************************************** -* @attention -* -*

© COPYRIGHT(c) 2014 STMicroelectronics

-* -* Redistribution and use in source and binary forms, with or without modification, -* are permitted provided that the following conditions are met: -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* 3. Neither the name of STMicroelectronics nor the names of its contributors -* may be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -*/ -/*---------------------------------------------------------------------------*/ -#include "contiki.h" -#include "dev/leds.h" -#include "stm32l1xx_nucleo.h" -#include "platform-conf.h" -#include -#include "dev/slip.h" -#include "hw-config.h" -#include "stm32l1xx_hal.h" -#include "st-lib.h" -/*---------------------------------------------------------------------------*/ -void uart_send_msg(char *); -extern st_lib_uart_handle_typedef st_lib_uart_handle; -/*---------------------------------------------------------------------------*/ -static unsigned char databyte[1] = {0}; -/*---------------------------------------------------------------------------*/ -/** -* @brief Rx Transfer completed callbacks. -* @param huart: Pointer to a st_lib_uart_handle_typedef structure that contains -* the configuration information for the specified UART module. -* @retval None -*/ -void st_lib_hal_uart_rx_cplt_callback(st_lib_uart_handle_typedef *huart) -{ - slip_input_byte(databyte[0]); - st_lib_hal_uart_receive_it(&st_lib_uart_handle, databyte, 1); -} -/*---------------------------------------------------------------------------*/ -void -uart1_set_input(int (*input) (unsigned char c)) -{ - st_lib_hal_uart_receive_it(&st_lib_uart_handle, databyte, 1); -} -/*--------------------------------------------------------------------------*/ -void -slip_arch_init(unsigned long ubr) -{ - st_lib_hal_uart_enable_it(&st_lib_uart_handle, UART_IT_RXNE); - //uart1_set_input(slip_input_byte); -} -/*--------------------------------------------------------------------------*/ -void -slip_arch_writeb(unsigned char c) -{ - uart_send_msg(&c); -} -/*--------------------------------------------------------------------------*/ - -/** - * @brief Send a message via UART - * @param msg the pointer to the message to be sent - * @retval None - */ -void uart_send_msg(char *msg) -{ - st_lib_hal_uart_transmit(&st_lib_uart_handle, (uint8_t*)msg, 1, 5000); -} -/*--------------------------------------------------------------------------*/ +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + */ +/*---------------------------------------------------------------------------*/ +#include "contiki.h" +#include "dev/leds.h" +#include "stm32l1xx_nucleo.h" +#include "platform-conf.h" +#include +#include "dev/slip.h" +#include "hw-config.h" +#include "stm32l1xx_hal.h" +#include "st-lib.h" +/*---------------------------------------------------------------------------*/ +void uart_send_msg(char *); +extern st_lib_uart_handle_typedef st_lib_uart_handle; +/*---------------------------------------------------------------------------*/ +static unsigned char databyte[1] = { 0 }; +/*---------------------------------------------------------------------------*/ +/** + * @brief Rx Transfer completed callbacks. + * @param huart: Pointer to a st_lib_uart_handle_typedef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void +st_lib_hal_uart_rx_cplt_callback(st_lib_uart_handle_typedef *huart) +{ + slip_input_byte(databyte[0]); + st_lib_hal_uart_receive_it(&st_lib_uart_handle, databyte, 1); +} +/*---------------------------------------------------------------------------*/ +void +uart1_set_input(int (*input)(unsigned char c)) +{ + st_lib_hal_uart_receive_it(&st_lib_uart_handle, databyte, 1); +} +/*--------------------------------------------------------------------------*/ +void +slip_arch_init(unsigned long ubr) +{ + st_lib_hal_uart_enable_it(&st_lib_uart_handle, UART_IT_RXNE); + /* uart1_set_input(slip_input_byte); */ +} +/*--------------------------------------------------------------------------*/ +void +slip_arch_writeb(unsigned char c) +{ + uart_send_msg(&c); +} +/*--------------------------------------------------------------------------*/ + +/** + * @brief Send a message via UART + * @param msg the pointer to the message to be sent + * @retval None + */ +void +uart_send_msg(char *msg) +{ + st_lib_hal_uart_transmit(&st_lib_uart_handle, (uint8_t *)msg, 1, 5000); +} +/*--------------------------------------------------------------------------*/ From 4e81c87c3a756a627c81582150651bc4e6a4e61f Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Tue, 13 Oct 2015 12:21:21 +0200 Subject: [PATCH 18/23] Fix to sensor-demo license and Readme file. --- .../stm32nucleo-spirit1/sensor-demo/README.md | 14 +++-- .../sensor-demo/sensor-demo.c | 62 ++++++++----------- 2 files changed, 34 insertions(+), 42 deletions(-) diff --git a/examples/stm32nucleo-spirit1/sensor-demo/README.md b/examples/stm32nucleo-spirit1/sensor-demo/README.md index ee0213df9..2ed16ddb7 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/README.md +++ b/examples/stm32nucleo-spirit1/sensor-demo/README.md @@ -1,15 +1,17 @@ -Sensors Demo +Sensor Demo ============ -The sensors demo can be used to read the value of all sensors and print it every 5 seconds on the terminal. +The sensor demo can be used to read the values of all sensors and print them every 5 seconds on the terminal. -In order to use this example the X-NUCLEO-IKS01A1 expansion board featuring ST environmental and motions sensors -must used. It needs to be connected on top of the STM32 Nucleo L1 and the X-NUCLEO-IDS01A4 (or A5) -sub-1GHz RF communication boards. +In order to use this example the X-NUCLEO-IKS01A1 expansion board featuring ST environmental and motion MEMS sensors +must be used. It needs to be connected on top of the NUCLEO-L152RE (MCU) and the X-NUCLEO-IDS01Ax +(sub-1GHz RF communication) boards. To build the example type: make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 USE_SENSOR_BOARD=1 +or + make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A5 USE_SENSOR_BOARD=1 - +depending on the sub GHz board you have. diff --git a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c index c8c3df6db..18fa9e308 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c +++ b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c @@ -1,44 +1,34 @@ -/** - ****************************************************************************** - * @file contiki-spirit1-main.c - * @author System LAB - * @version V1.0.0 - * @date 17-June-2015 - * @brief Contiki main file for SPIRIT1 platform - ****************************************************************************** - * @attention +/* + * Copyright (c) 2012, STMicroelectronics. + * All rights reserved. * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * * - ****************************************************************************** */ -/** - * \file - * A very simple Contiki application showing sensor values for ST Nucleo - */ - +/*---------------------------------------------------------------------------*/ #include "contiki.h" #include /* For printf() */ From e261cda8dcc36cb3ef315bcafc398ad721e48d0b Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Tue, 27 Oct 2015 12:12:59 +0100 Subject: [PATCH 19/23] Compilation flags update: BOARD=ids01a4/5 SENSORBOARD=iks01a1 --- .../stm32nucleo-spirit1/sensor-demo/Makefile | 2 +- .../stm32nucleo-spirit1/sensor-demo/README.md | 6 +- .../sensor-demo/sensor-demo.c | 16 ++--- platform/stm32nucleo-spirit1/Makefile.ids01a4 | 2 + platform/stm32nucleo-spirit1/Makefile.ids01a5 | 2 + platform/stm32nucleo-spirit1/Makefile.iks01a1 | 23 +++++++ .../Makefile.stm32nucleo-spirit1 | 61 ++++++------------- platform/stm32nucleo-spirit1/README.md | 12 ++-- .../contiki-spirit1-main.c | 6 +- .../dev/acceleration-sensor.c | 4 +- .../dev/gyroscope-sensor.c | 4 +- .../stm32nucleo-spirit1/dev/humidity-sensor.c | 4 +- platform/stm32nucleo-spirit1/dev/leds-arch.c | 32 +++++----- .../stm32nucleo-spirit1/dev/magneto-sensor.c | 4 +- .../stm32nucleo-spirit1/dev/pressure-sensor.c | 4 +- .../dev/temperature-sensor.c | 4 +- platform/stm32nucleo-spirit1/platform-conf.h | 4 +- platform/stm32nucleo-spirit1/st-lib.h | 4 +- platform/stm32nucleo-spirit1/stm32cube-lib | 2 +- regression-tests/Makefile.compile-test | 2 +- 20 files changed, 101 insertions(+), 97 deletions(-) create mode 100644 platform/stm32nucleo-spirit1/Makefile.ids01a4 create mode 100644 platform/stm32nucleo-spirit1/Makefile.ids01a5 create mode 100644 platform/stm32nucleo-spirit1/Makefile.iks01a1 diff --git a/examples/stm32nucleo-spirit1/sensor-demo/Makefile b/examples/stm32nucleo-spirit1/sensor-demo/Makefile index 2c980b1ec..0ec14cccd 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/Makefile +++ b/examples/stm32nucleo-spirit1/sensor-demo/Makefile @@ -2,7 +2,7 @@ CONTIKI_PROJECT = sensor-demo all: $(CONTIKI_PROJECT) TARGET=stm32nucleo-spirit1 -USE_SENSOR_BOARD=1 +SENSORBOARD=iks01a1 CONTIKI = ../../.. include $(CONTIKI)/Makefile.include diff --git a/examples/stm32nucleo-spirit1/sensor-demo/README.md b/examples/stm32nucleo-spirit1/sensor-demo/README.md index 2ed16ddb7..b9cdc9caf 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/README.md +++ b/examples/stm32nucleo-spirit1/sensor-demo/README.md @@ -9,9 +9,9 @@ must be used. It needs to be connected on top of the NUCLEO-L152RE (MCU) and the To build the example type: - make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 USE_SENSOR_BOARD=1 + make TARGET=stm32nucleo-spirit1 BOARD=ids01a4 SENSORBOARD=iks01a1 or - make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A5 USE_SENSOR_BOARD=1 + make TARGET=stm32nucleo-spirit1 BOARD=ids01a5 SENSORBOARD=iks01a1 -depending on the sub GHz board you have. +depending on the X-NUCLEO-IDS01Ax expansion board for sub GHz radio connectivity you have. diff --git a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c index 18fa9e308..18bea17bf 100644 --- a/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c +++ b/examples/stm32nucleo-spirit1/sensor-demo/sensor-demo.c @@ -44,14 +44,14 @@ #include "st-lib.h" -#ifdef COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 #include "dev/temperature-sensor.h" #include "dev/humidity-sensor.h" #include "dev/pressure-sensor.h" #include "dev/magneto-sensor.h" #include "dev/acceleration-sensor.h" #include "dev/gyroscope-sensor.h" -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ #define DEBUG DEBUG_PRINT #include "net/ip/uip-debug.h" @@ -75,14 +75,14 @@ PROCESS_THREAD(sensor_demo_process, ev, data) SENSORS_ACTIVATE(radio_sensor); -#ifdef COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 SENSORS_ACTIVATE(temperature_sensor); SENSORS_ACTIVATE(humidity_sensor); SENSORS_ACTIVATE(pressure_sensor); SENSORS_ACTIVATE(magneto_sensor); SENSORS_ACTIVATE(acceleration_sensor); SENSORS_ACTIVATE(gyroscope_sensor); -#endif +#endif /*X_NUCLEO_IKS01A1*/ while(1) { etimer_set(&etimer, PRINT_INTERVAL); @@ -98,17 +98,17 @@ PROCESS_THREAD(sensor_demo_process, ev, data) printf("Button state:\t%s (pressed %lu times)\n", button_sensor.value(0) ? "Released" : "Pressed", _button_pressed); -#ifdef COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 printf("LEDs status:\tRED:n/a GREEN:%s\n", leds_get() & LEDS_GREEN ? "on" : "off"); #else printf("LEDs status:\tRED:%s GREEN:%s\n", leds_get() & LEDS_RED ? "on" : "off", leds_get() & LEDS_GREEN ? "on" : "off"); -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ sensor_value = radio_sensor.value(RADIO_SENSOR_LAST_PACKET); printf("Radio (RSSI):\t%d.%d dBm\n", sensor_value / 10, ABS_VALUE(sensor_value) % 10); printf("Radio (LQI):\t%d\n", radio_sensor.value(RADIO_SENSOR_LAST_VALUE)); -#ifdef COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 sensor_value = temperature_sensor.value(0); printf("Temperature:\t%d.%d C\n", sensor_value / 10, ABS_VALUE(sensor_value) % 10); @@ -134,7 +134,7 @@ PROCESS_THREAD(sensor_demo_process, ev, data) printf("Gyroscope:\t%d/%d/%d (X/Y/Z) mdps\n", gyroscope_sensor.value(X_AXIS), gyroscope_sensor.value(Y_AXIS), gyroscope_sensor.value(Z_AXIS)); -#endif +#endif /*X_NUCLEO_IKS01A1*/ printf("\n"); } diff --git a/platform/stm32nucleo-spirit1/Makefile.ids01a4 b/platform/stm32nucleo-spirit1/Makefile.ids01a4 new file mode 100644 index 000000000..ef2dfb9ac --- /dev/null +++ b/platform/stm32nucleo-spirit1/Makefile.ids01a4 @@ -0,0 +1,2 @@ +#Simply set the correct flag +CFLAGS += -DX_NUCLEO_IDS01A4 diff --git a/platform/stm32nucleo-spirit1/Makefile.ids01a5 b/platform/stm32nucleo-spirit1/Makefile.ids01a5 new file mode 100644 index 000000000..b696c713c --- /dev/null +++ b/platform/stm32nucleo-spirit1/Makefile.ids01a5 @@ -0,0 +1,2 @@ +#Simply set the correct flag +CFLAGS += -DX_NUCLEO_IDS01A5 diff --git a/platform/stm32nucleo-spirit1/Makefile.iks01a1 b/platform/stm32nucleo-spirit1/Makefile.iks01a1 new file mode 100644 index 000000000..c36138a69 --- /dev/null +++ b/platform/stm32nucleo-spirit1/Makefile.iks01a1 @@ -0,0 +1,23 @@ +CFLAGS += -DX_NUCLEO_IKS01A1 + +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/x_nucleo_iks01a1 +CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/sensors/hts221 stm32cube-lib/drivers/sensors/lps25h stm32cube-lib/drivers/sensors/lps25hb\ + stm32cube-lib/drivers/sensors/lsm6ds0 stm32cube-lib/drivers/sensors/lsm6ds3 stm32cube-lib/drivers/sensors/lis3mdl + +ARCH_DEV_SENSORS = temperature-sensor.c humidity-sensor.c pressure-sensor.c magneto-sensor.c acceleration-sensor.c gyroscope-sensor.c + +ARCH_DRIVERS_IKS01A1 = x_nucleo_iks01a1.c x_nucleo_iks01a1_hum_temp.c x_nucleo_iks01a1_imu_6axes.c \ + x_nucleo_iks01a1_magneto.c x_nucleo_iks01a1_pressure.c + + +ARCH_DRIVERS_SENSORS = hts221.c \ + lis3mdl.c \ + lps25h.c \ + lps25hb.c \ + lsm6ds0.c \ + lsm6ds3.c + +ARCH+=$(ARCH_DEV_SENSORS) +ARCH+=$(ARCH_DRIVERS_IKS01A1) +ARCH+=$(ARCH_DRIVERS_SENSORS) + diff --git a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 index c24b0b4c2..27cc1f6d2 100644 --- a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 +++ b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 @@ -1,30 +1,32 @@ CONTIKI_TARGET_DIRS = . - -ifeq ($(USE_SENSOR_BOARD),1) - COMPILE_SENSORS=TRUE - CFLAGS += -DCOMPILE_SENSORS - ${info Compiling with Sensor Files} -else - COMPILE_SENSORS=FALSE - ${info NOT compiling Sensor Files} -endif - - -ifeq ($(USE_SUBGHZ_BOARD),IDS01A4) - CFLAGS += -DX_NUCLEO_IDS01A4 +ifeq ($(BOARD),ids01a4) ${info Using 868 MHz SPIRIT1 Board} -else ifeq ($(USE_SUBGHZ_BOARD),IDS01A5) - CFLAGS += -DX_NUCLEO_IDS01A5 +else ifeq ($(BOARD),ids01a5) ${info Using 915 MHz SPIRIT1 Board} else ${info You must specify which SPIRIT1 board you use:} - ${info make USE_SUBGHZ_BOARD=IDS01A4 for 868 MHz} - ${info make USE_SUBGHZ_BOARD=IDS01A5 for 915 MHz} + ${info make BOARD=ids01a4 for X-NUCLEO-IDS01A4 (868 MHz)} + ${info make BOARD=ids01a5 for X-NUCLEO-IDS01A5 (915 MHz)} ${error } endif +### Include the board-specific makefile +PLATFORM_ROOT_DIR = $(CONTIKI)/platform/$(TARGET) +-include $(PLATFORM_ROOT_DIR)/Makefile.$(BOARD) + +ifeq ($(SENSORBOARD),iks01a1) + ${info Compiling with X-NUCLEO-IKS01A1 sensors files} + -include $(PLATFORM_ROOT_DIR)/Makefile.$(SENSORBOARD) +else ifeq ($(SENSORBOARD),) + ${info NOT compiling files for any sensors expansion board} +else + ${info Error: SENSORBOARD can be: iks01a1} + ${error } +endif + + #Currently we support only GCC GCC=1 @@ -41,17 +43,8 @@ CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/STM32L1xx_HAL_Driver/Src CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/STM32L1xx_HAL_Driver/Inc -ifeq ($(COMPILE_SENSORS),TRUE) -CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/x_nucleo_iks01a1 -CONTIKI_TARGET_DIRS += stm32cube-lib/drivers/sensors/hts221 stm32cube-lib/drivers/sensors/lps25h stm32cube-lib/drivers/sensors/lps25hb\ - stm32cube-lib/drivers/sensors/lsm6ds0 stm32cube-lib/drivers/sensors/lsm6ds3 stm32cube-lib/drivers/sensors/lis3mdl -endif - - ARCH_DEV = button-sensor.c leds-arch.c radio-sensor.c -ARCH_DEV_SENSORS = temperature-sensor.c humidity-sensor.c pressure-sensor.c magneto-sensor.c acceleration-sensor.c gyroscope-sensor.c - ARCH_NUCLEOSPIRIT1 = contiki-spirit1-main.c uart-msg.c spirit1-arch.c spirit1.c node-id.c ARCH_NUCLEOSPIRIT1_STM32CUBEHAL = spirit1_appli.c stm32l1xx_hal_msp.c stm32l1xx_it.c stm32cube_hal_init.c @@ -81,16 +74,6 @@ ARCH_DRIVERS_SPIRIT1 = \ SPIRIT_Timer.c \ SPIRIT_Types.c -ARCH_DRIVERS_IKS01A1 = x_nucleo_iks01a1.c x_nucleo_iks01a1_hum_temp.c x_nucleo_iks01a1_imu_6axes.c \ - x_nucleo_iks01a1_magneto.c x_nucleo_iks01a1_pressure.c - -ARCH_DRIVERS_SENSORS = hts221.c \ - lis3mdl.c \ - lps25h.c \ - lps25hb.c \ - lsm6ds0.c \ - lsm6ds3.c - STM32L1XX_HAL =\ stm32l1xx_hal.c\ stm32l1xx_hal_adc_ex.c\ @@ -144,12 +127,6 @@ ARCH+=$(ARCH_DRIVERS_IDS01AX) ARCH+=$(ARCH_DRIVERS_SPIRIT1) ARCH+=$(STM32L1XX_HAL) -ifeq ($(COMPILE_SENSORS),TRUE) - ARCH+=$(ARCH_DEV_SENSORS) - ARCH+=$(ARCH_DRIVERS_IKS01A1) - ARCH+=$(ARCH_DRIVERS_SENSORS) -endif - CFLAGS += -DUSE_STM32L152_EVAL \ -DSTM32L152xE \ -DUSE_STM32L1XX_NUCLEO \ diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index d94771eca..4641c8be3 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -7,7 +7,7 @@ Port Feature ============ The port supports the following boards from ST: -- NUCLEO-L152RE board, based on the STM32L152RET6 ultra-low power microcontroller +- NUCLEO-L152RE board, based on the STM32L152RET6 ultra-low power microcontroller - X-NUCLEO-IDS01A4 based on sub-1GHz SPSGRF-868 SPIRIT1 module (operating at 868 MHz) - X-NUCLEO-IDS01A5 based on sub-1GHz SPSGRF-915 SPIRIT1 module (operating at 915 MHz) - X-NUCLEO-IKS01A1 featuring motion MEMS and environmental sensors (optional) @@ -102,13 +102,13 @@ For example, go to examples/ipv6/simple-udp-rpl directory. If the X-NUCLEO-IDS01A4 sub-1GHz RF expansion board is used, the following must be run: - make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 clean - make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 + make TARGET=stm32nucleo-spirit1 BOARD=ids01a4 clean + make TARGET=stm32nucleo-spirit1 BOARD=ids01a4 If the X-NUCLEO-IDS01A5 sub-1GHz RF expansion board is used, the following must be run: - make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A5 clean - make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A5 + make TARGET=stm32nucleo-spirit1 BOARD=ids01a5 clean + make TARGET=stm32nucleo-spirit1 BOARD=ids01a5 This will create executables for UDP sender and receiver nodes. @@ -125,7 +125,7 @@ In case you need to build an example that uses the additional sensors expansion (for example, considering a system made of NUCLEO-L152RE, X-NUCLEO-IDS01A4 and X-NUCLEO-IKS01A1) then the command to be run would be: - make TARGET=stm32nucleo-spirit1 USE_SUBGHZ_BOARD=IDS01A4 USE_SENSOR_BOARD=1 + make TARGET=stm32nucleo-spirit1 BOARD=ids01a4 SENSORBOARD=iks01a1 System setup ============ diff --git a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c index 2342e8254..5d5e5413e 100644 --- a/platform/stm32nucleo-spirit1/contiki-spirit1-main.c +++ b/platform/stm32nucleo-spirit1/contiki-spirit1-main.c @@ -68,7 +68,7 @@ #include "net/ipv6/uip-ds6.h" #endif /*NETSTACK_CONF_WITH_IPV6*/ /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 extern const struct sensors_sensor temperature_sensor; extern const struct sensors_sensor humidity_sensor; extern const struct sensors_sensor pressure_sensor; @@ -83,10 +83,10 @@ SENSORS(&button_sensor, &magneto_sensor, &acceleration_sensor, &gyroscope_sensor); -#else /*COMPILE_SENSORS*/ +#else /*X_NUCLEO_IKS01A1*/ SENSORS(&button_sensor, &radio_sensor); -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ extern unsigned char node_mac[8]; /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c index 3b6e5bc56..104cfe8b8 100644 --- a/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/acceleration-sensor.c @@ -37,7 +37,7 @@ * Driver for the stm32nucleo-spirit1 Temperature sensor (on expansion board) */ /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 /*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "acceleration-sensor.h" @@ -137,6 +137,6 @@ status(int type) SENSORS_SENSOR(acceleration_sensor, ACCELERATION_SENSOR, value, configure, status); /*---------------------------------------------------------------------------*/ -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c index 31b79085f..cfa699827 100644 --- a/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/gyroscope-sensor.c @@ -37,7 +37,7 @@ * Driver for the stm32nucleo-spirit1 Gyroscope sensor (on expansion board) */ /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 /*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "gyroscope-sensor.h" @@ -136,6 +136,6 @@ status(int type) /*---------------------------------------------------------------------------*/ SENSORS_SENSOR(gyroscope_sensor, GYROSCOPE_SENSOR, value, configure, status); /*---------------------------------------------------------------------------*/ -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/humidity-sensor.c b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c index 76f22656a..843b35a91 100644 --- a/platform/stm32nucleo-spirit1/dev/humidity-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/humidity-sensor.c @@ -37,7 +37,7 @@ * Driver for the stm32nucleo-spirit1 Humidity sensor (on expansion board) */ /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 /*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "humidity-sensor.h" @@ -117,6 +117,6 @@ status(int type) /*---------------------------------------------------------------------------*/ SENSORS_SENSOR(humidity_sensor, HUMIDITY_SENSOR, value, configure, status); /*---------------------------------------------------------------------------*/ -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/leds-arch.c b/platform/stm32nucleo-spirit1/dev/leds-arch.c index 6fadf21bd..7c9b198fe 100644 --- a/platform/stm32nucleo-spirit1/dev/leds-arch.c +++ b/platform/stm32nucleo-spirit1/dev/leds-arch.c @@ -41,13 +41,13 @@ #include "dev/leds.h" #include "st-lib.h" /*---------------------------------------------------------------------------*/ -#ifndef COMPILE_SENSORS -/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT - * used, becasue of a pin conflict. +#ifndef X_NUCLEO_IKS01A1 +/* The Red LED (on SPIRIT1 exp board) is exposed only if the + * X-NUCLEO-IKS01A1 sensor board is NOT used, becasue of a pin conflict. */ extern st_lib_gpio_typedef *st_lib_a_led_gpio_port[]; extern const uint16_t st_lib_a_led_gpio_pin[]; -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ extern st_lib_gpio_typedef *st_lib_gpio_port[]; extern const uint16_t st_lib_gpio_pin[]; @@ -59,13 +59,13 @@ leds_arch_init(void) st_lib_bsp_led_init(LED2); st_lib_bsp_led_off(LED2); -#ifndef COMPILE_SENSORS -/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT - * used, becasue of a pin conflict. +#ifndef X_NUCLEO_IKS01A1 +/* The Red LED (on SPIRIT1 exp board) is exposed only if the + * X-NUCLEO-IKS01A1 sensor board is NOT used, becasue of a pin conflict. */ st_lib_radio_shield_led_init(RADIO_SHIELD_LED); st_lib_radio_shield_led_off(RADIO_SHIELD_LED); -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ } /*---------------------------------------------------------------------------*/ unsigned char @@ -76,15 +76,15 @@ leds_arch_get(void) ret |= LEDS_GREEN; } -#ifndef COMPILE_SENSORS -/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT - * used, becasue of a pin conflict. +#ifndef X_NUCLEO_IKS01A1 +/* The Red LED (on SPIRIT1 exp board) is exposed only if the + * X-NUCLEO-IKS01A1 sensor board is NOT used, becasue of a pin conflict. */ if(st_lib_hal_gpio_read_pin(st_lib_a_led_gpio_port[RADIO_SHIELD_LED], st_lib_a_led_gpio_pin[RADIO_SHIELD_LED])) { ret |= LEDS_RED; } -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ return ret; } @@ -98,16 +98,16 @@ leds_arch_set(unsigned char leds) st_lib_bsp_led_off(LED2); } -#ifndef COMPILE_SENSORS -/* The Red LED (on SPIRIT1 exp board) is exposed only if the sensor board is NOT - * used, becasue of a pin conflict. +#ifndef X_NUCLEO_IKS01A1 +/* The Red LED (on SPIRIT1 exp board) is exposed only if the + * X-NUCLEO-IKS01A1 sensor board is NOT used, becasue of a pin conflict. */ if(leds & LEDS_RED) { st_lib_radio_shield_led_on(RADIO_SHIELD_LED); } else { st_lib_radio_shield_led_off(RADIO_SHIELD_LED); } -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ } /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c index d57668c33..753bfba33 100644 --- a/platform/stm32nucleo-spirit1/dev/magneto-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/magneto-sensor.c @@ -37,7 +37,7 @@ * Driver for the stm32nucleo-spirit1 Magneto sensor (on expansion board) */ /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 /*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "magneto-sensor.h" @@ -132,6 +132,6 @@ status(int type) /*---------------------------------------------------------------------------*/ SENSORS_SENSOR(magneto_sensor, MAGNETO_SENSOR, value, configure, status); /*---------------------------------------------------------------------------*/ -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/pressure-sensor.c b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c index 8f92b01bc..a7cce6621 100644 --- a/platform/stm32nucleo-spirit1/dev/pressure-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/pressure-sensor.c @@ -37,7 +37,7 @@ * Driver for the stm32nucleo-spirit1 Pressure sensor (on expansion board) */ /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 /*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "pressure-sensor.h" @@ -114,5 +114,5 @@ status(int type) /*---------------------------------------------------------------------------*/ SENSORS_SENSOR(pressure_sensor, PRESSURE_SENSOR, value, configure, status); /*---------------------------------------------------------------------------*/ -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/dev/temperature-sensor.c b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c index 29e82e069..87a75b983 100644 --- a/platform/stm32nucleo-spirit1/dev/temperature-sensor.c +++ b/platform/stm32nucleo-spirit1/dev/temperature-sensor.c @@ -37,7 +37,7 @@ * Driver for the stm32nucleo-spirit1 Temperature sensor (on expansion board) */ /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 /*---------------------------------------------------------------------------*/ #include "lib/sensors.h" #include "temperature-sensor.h" @@ -116,6 +116,6 @@ status(int type) /*---------------------------------------------------------------------------*/ SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, value, configure, status); -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/platform/stm32nucleo-spirit1/platform-conf.h b/platform/stm32nucleo-spirit1/platform-conf.h index ea32741ea..dede0bdeb 100644 --- a/platform/stm32nucleo-spirit1/platform-conf.h +++ b/platform/stm32nucleo-spirit1/platform-conf.h @@ -55,11 +55,11 @@ #define LEDS_GREEN 1 /*Nucleo LED*/ #define LEDS_RED 2 /*SPIRIT1 LED*/ -#ifdef COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 #define LEDS_CONF_ALL 1 /*Can't use SPIRIT1 LED in this case*/ #else #define LEDS_CONF_ALL 3 /*No sensors -> we can use SPIRIT1 LED in this case*/ -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ #define F_CPU 32000000ul #define RTIMER_ARCH_SECOND 32768 diff --git a/platform/stm32nucleo-spirit1/st-lib.h b/platform/stm32nucleo-spirit1/st-lib.h index d49b810b5..6a7e2ee0f 100644 --- a/platform/stm32nucleo-spirit1/st-lib.h +++ b/platform/stm32nucleo-spirit1/st-lib.h @@ -297,7 +297,7 @@ #define st_lib_hal_gpio_write_pin(...) HAL_GPIO_WritePin(__VA_ARGS__) /*---------------------------------------------------------------------------*/ -#if COMPILE_SENSORS +#ifdef X_NUCLEO_IKS01A1 /*---------------------------------------------------------------------------*/ /* x_nucleo_iks01a1.h */ #include "x_nucleo_iks01a1.h" @@ -340,7 +340,7 @@ #define st_lib_bsp_pressure_get_pressure(...) BSP_PRESSURE_GetPressure(__VA_ARGS__) /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ -#endif /*COMPILE_SENSORS*/ +#endif /*X_NUCLEO_IKS01A1*/ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ #endif /*ST_LIB_H_*/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-lib b/platform/stm32nucleo-spirit1/stm32cube-lib index 6ff4221d0..66b672b5c 160000 --- a/platform/stm32nucleo-spirit1/stm32cube-lib +++ b/platform/stm32nucleo-spirit1/stm32cube-lib @@ -1 +1 @@ -Subproject commit 6ff4221d03963844364616e6499e9401c0321c28 +Subproject commit 66b672b5cc25fabc853510cd8ae4db40357d748e diff --git a/regression-tests/Makefile.compile-test b/regression-tests/Makefile.compile-test index c32705434..10b01cf7e 100644 --- a/regression-tests/Makefile.compile-test +++ b/regression-tests/Makefile.compile-test @@ -41,7 +41,7 @@ define dooneexample @echo Building example $(3): $(1) for target $(2) @((cd $(EXAMPLESDIR)/$(1); \ export STM32W_CPUREV=CC; \ - export USE_SUBGHZ_BOARD=IDS01A5; \ + export BOARD=ids01a5; \ make TARGET=$(2) clean && make TARGET=$(2)) > \ $(3)-$(subst /,-,$(1))$(2).report 2>&1 && \ (echo $(1) $(2): OK | tee $(3)-$(subst /,-,$(1))$(2).summary) || \ From 527903ee1055ce844ab380c71223b69b538c448b Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Wed, 11 Nov 2015 13:48:38 +0100 Subject: [PATCH 20/23] Added default BOARD value to let regression tests compile for any platform. --- .../Makefile.stm32nucleo-spirit1 | 26 ++++++++++++++----- regression-tests/Makefile.compile-test | 1 - 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 index 27cc1f6d2..ebc188377 100644 --- a/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 +++ b/platform/stm32nucleo-spirit1/Makefile.stm32nucleo-spirit1 @@ -1,14 +1,25 @@ CONTIKI_TARGET_DIRS = . -ifeq ($(BOARD),ids01a4) - ${info Using 868 MHz SPIRIT1 Board} +ifeq ($(BOARD),) + BOARD=ids01a4 + ${info ***************************************************} + ${info BOARD not specified, default to ids01a4 (868 MHz)!} + ${info ***************************************************} +else ifeq ($(BOARD),ids01a4) + ${info ***************************************************} + ${info Using ids01a4 SPIRIT1 expansion board (868 MHz)} + ${info ***************************************************} else ifeq ($(BOARD),ids01a5) - ${info Using 915 MHz SPIRIT1 Board} + ${info ***************************************************} + ${info Using ids01a5 SPIRIT1 expansion board (915 MHz)} + ${info ***************************************************} else - ${info You must specify which SPIRIT1 board you use:} - ${info make BOARD=ids01a4 for X-NUCLEO-IDS01A4 (868 MHz)} - ${info make BOARD=ids01a5 for X-NUCLEO-IDS01A5 (915 MHz)} + ${info ***************************************************} + ${info You must specify a valid SPIRIT1 board to use:} + ${info make BOARD=ids01a4 for X-NUCLEO-IDS01A4 (868 MHz)} + ${info make BOARD=ids01a5 for X-NUCLEO-IDS01A5 (915 MHz)} + ${info ***************************************************} ${error } endif @@ -18,11 +29,14 @@ PLATFORM_ROOT_DIR = $(CONTIKI)/platform/$(TARGET) ifeq ($(SENSORBOARD),iks01a1) ${info Compiling with X-NUCLEO-IKS01A1 sensors files} + ${info ***************************************************} -include $(PLATFORM_ROOT_DIR)/Makefile.$(SENSORBOARD) else ifeq ($(SENSORBOARD),) ${info NOT compiling files for any sensors expansion board} + ${info ***************************************************} else ${info Error: SENSORBOARD can be: iks01a1} + ${info ***************************************************} ${error } endif diff --git a/regression-tests/Makefile.compile-test b/regression-tests/Makefile.compile-test index 1793321ee..60eaf4279 100644 --- a/regression-tests/Makefile.compile-test +++ b/regression-tests/Makefile.compile-test @@ -41,7 +41,6 @@ define dooneexample @echo Building example $(3): $(1) for target $(2) @((cd $(EXAMPLESDIR)/$(1); \ export STM32W_CPUREV=CC; \ - export BOARD=ids01a5; \ make TARGET=$(2) clean && make TARGET=$(2) WERROR=1) > \ $(3)-$(subst /,-,$(1))$(2).report 2>&1 && \ (echo $(1) $(2): OK | tee $(3)-$(subst /,-,$(1))$(2).summary) || \ From 267d51aceeb84dd4c943633735e72fdaceede16e Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Wed, 11 Nov 2015 13:53:58 +0100 Subject: [PATCH 21/23] Modified radio parameters to increase communication range. --- platform/stm32nucleo-spirit1/spirit1-config.h | 2 +- platform/stm32nucleo-spirit1/stm32cube-lib | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/stm32nucleo-spirit1/spirit1-config.h b/platform/stm32nucleo-spirit1/spirit1-config.h index 4c89fe33e..5124aef24 100644 --- a/platform/stm32nucleo-spirit1/spirit1-config.h +++ b/platform/stm32nucleo-spirit1/spirit1-config.h @@ -37,7 +37,7 @@ #include "SPIRIT_Config.h" #include "spirit1-const.h" /*---------------------------------------------------------------------------*/ -#define CCA_THRESHOLD -98.0 /* dBm */ +#define CCA_THRESHOLD -120.0 /* dBm */ #define XTAL_FREQUENCY 50000000 /* Hz */ #define SPIRIT_MAX_FIFO_LEN 96 /*---------------------------------------------------------------------------*/ diff --git a/platform/stm32nucleo-spirit1/stm32cube-lib b/platform/stm32nucleo-spirit1/stm32cube-lib index 66b672b5c..e68b57aa1 160000 --- a/platform/stm32nucleo-spirit1/stm32cube-lib +++ b/platform/stm32nucleo-spirit1/stm32cube-lib @@ -1 +1 @@ -Subproject commit 66b672b5cc25fabc853510cd8ae4db40357d748e +Subproject commit e68b57aa153059ebfaf013ecdb051fc0d6729450 From 7e7c201c409a3923f785743b7a155c02e01aeead Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Wed, 11 Nov 2015 18:50:38 +0100 Subject: [PATCH 22/23] Updated radio parameters (in the submodule repo), to have more radio range. --- platform/stm32nucleo-spirit1/stm32cube-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/stm32nucleo-spirit1/stm32cube-lib b/platform/stm32nucleo-spirit1/stm32cube-lib index e68b57aa1..34e784ff3 160000 --- a/platform/stm32nucleo-spirit1/stm32cube-lib +++ b/platform/stm32nucleo-spirit1/stm32cube-lib @@ -1 +1 @@ -Subproject commit e68b57aa153059ebfaf013ecdb051fc0d6729450 +Subproject commit 34e784ff39a5dc4da288ce696235f41b1db4bf5c From 65e1fed1bc2ec7a5b03a8f7351acbafe4ed25dd1 Mon Sep 17 00:00:00 2001 From: Marco Grella Date: Wed, 25 Nov 2015 12:56:42 +0100 Subject: [PATCH 23/23] Added contacts for stm32nucleo-spirit1 platform. --- platform/stm32nucleo-spirit1/README.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/platform/stm32nucleo-spirit1/README.md b/platform/stm32nucleo-spirit1/README.md index 4641c8be3..80d178dfa 100644 --- a/platform/stm32nucleo-spirit1/README.md +++ b/platform/stm32nucleo-spirit1/README.md @@ -3,6 +3,18 @@ Getting Started with Contiki for STM32 Nucleo equipped with sub-1GHz SPIRIT1 exp This guide explains how to get started with the STM32 Nucleo and expansion boards port to Contiki. +Maintainers and Contacts +======================== + +Long-term maintainers: +* Marco Grella, marco.grella@st.com, github user: [STclab](https://github.com/STclab) +* Alok Mittal, alok.mittal@st.com, github user: [STclab](https://github.com/STclab) +* Indar Prakash Singhal, indar.singhal@st.com, github user: [STclab](https://github.com/STclab) + +Contributors: +* David Siorpaes, david.siorpaes@st.com, github user: [siorpaes](https://github.com/siorpaes) +* Luca Celetto, luca.celetto@st.com + Port Feature ============