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Updated to use the watchdog API
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@ -29,7 +29,7 @@
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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* OF SUCH DAMAGE.
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*
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*
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* $Id: flash.c,v 1.1 2006/06/17 22:41:21 adamdunkels Exp $
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* $Id: flash.c,v 1.2 2007/11/17 10:28:04 adamdunkels Exp $
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*
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*
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* Author: Adam Dunkels <adam@sics.se>
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* Author: Adam Dunkels <adam@sics.se>
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*
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*
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@ -40,6 +40,7 @@
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#include <signal.h>
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#include <signal.h>
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#include "dev/flash.h"
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#include "dev/flash.h"
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#include "dev/watchdog.h"
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#define FLASH_TIMEOUT 30
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#define FLASH_TIMEOUT 30
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#define FLASH_REQ_TIMEOUT 150
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#define FLASH_REQ_TIMEOUT 150
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@ -57,7 +58,7 @@ flash_setup(void)
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IFG1 = 0;
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IFG1 = 0;
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/* Stop watchdog. */
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/* Stop watchdog. */
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WDTCTL = 0x5A80;
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watchdog_stop();
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/* DCO(SMCLK) is 2,4576MHz, /6 = 409600 Hz
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/* DCO(SMCLK) is 2,4576MHz, /6 = 409600 Hz
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select SMCLK for flash timing, divider 5+1 */
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select SMCLK for flash timing, divider 5+1 */
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@ -81,6 +82,7 @@ flash_done(void)
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IE1 = ie1;
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IE1 = ie1;
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IE2 = ie2;
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IE2 = ie2;
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_EINT();
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_EINT();
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watchdog_start();
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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@ -28,12 +28,12 @@
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*
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*
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* This file is part of the Contiki operating system.
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* This file is part of the Contiki operating system.
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*
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*
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* @(#)$Id: msp430.c,v 1.6 2007/05/21 15:29:46 bg- Exp $
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* @(#)$Id: msp430.c,v 1.7 2007/11/17 10:28:18 adamdunkels Exp $
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*/
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*/
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#include <io.h>
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#include <io.h>
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#include <signal.h>
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#include <signal.h>
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#include <sys/unistd.h>
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#include <sys/unistd.h>
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#include "dev/watchdog.h"
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#include "net/uip.h"
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#include "net/uip.h"
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -53,7 +53,6 @@ msp430_init_dco(void)
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BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
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BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
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crystal DCO frquenzy = 2,4576 MHz */
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crystal DCO frquenzy = 2,4576 MHz */
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WDTCTL = WDTPW + WDTHOLD; /* Stop WDT */
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BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
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BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
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for(i = 0xffff; i > 0; i--); /* Delay for XTAL to settle */
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for(i = 0xffff; i > 0; i--); /* Delay for XTAL to settle */
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@ -156,6 +155,7 @@ void
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msp430_cpu_init(void)
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msp430_cpu_init(void)
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{
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{
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dint();
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dint();
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watchdog_stop();
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init_ports();
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init_ports();
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msp430_init_dco();
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msp430_init_dco();
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eint();
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eint();
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