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Updated to use the watchdog API

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This commit is contained in:
adamdunkels 2007-11-17 10:28:04 +00:00
parent 19b7bd9217
commit 2132462716
2 changed files with 8 additions and 6 deletions
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8
cpu/msp430/flash.c
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@ -29,7 +29,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE. * OF SUCH DAMAGE.
* *
* $Id: flash.c,v 1.1 2006/06/17 22:41:21 adamdunkels Exp $ * $Id: flash.c,v 1.2 2007/11/17 10:28:04 adamdunkels Exp $
* *
* Author: Adam Dunkels <adam@sics.se> * Author: Adam Dunkels <adam@sics.se>
* *
@ -40,6 +40,7 @@
#include <signal.h> #include <signal.h>
#include "dev/flash.h" #include "dev/flash.h"
#include "dev/watchdog.h"
#define FLASH_TIMEOUT 30 #define FLASH_TIMEOUT 30
#define FLASH_REQ_TIMEOUT 150 #define FLASH_REQ_TIMEOUT 150
@ -57,7 +58,7 @@ flash_setup(void)
IFG1 = 0; IFG1 = 0;
/* Stop watchdog. */ /* Stop watchdog. */
WDTCTL = 0x5A80; watchdog_stop();
/* DCO(SMCLK) is 2,4576MHz, /6 = 409600 Hz /* DCO(SMCLK) is 2,4576MHz, /6 = 409600 Hz
select SMCLK for flash timing, divider 5+1 */ select SMCLK for flash timing, divider 5+1 */
@ -80,7 +81,8 @@ flash_done(void)
/* Enable interrupts. */ /* Enable interrupts. */
IE1 = ie1; IE1 = ie1;
IE2 = ie2; IE2 = ie2;
_EINT(); _EINT();
watchdog_start();
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void

6
cpu/msp430/msp430.c
View File

@ -28,12 +28,12 @@
* *
* This file is part of the Contiki operating system. * This file is part of the Contiki operating system.
* *
* @(#)$Id: msp430.c,v 1.6 2007/05/21 15:29:46 bg- Exp $ * @(#)$Id: msp430.c,v 1.7 2007/11/17 10:28:18 adamdunkels Exp $
*/ */
#include <io.h> #include <io.h>
#include <signal.h> #include <signal.h>
#include <sys/unistd.h> #include <sys/unistd.h>
#include "dev/watchdog.h"
#include "net/uip.h" #include "net/uip.h"
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
@ -53,7 +53,6 @@ msp430_init_dco(void)
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */ crystal DCO frquenzy = 2,4576 MHz */
WDTCTL = WDTPW + WDTHOLD; /* Stop WDT */
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */ BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--); /* Delay for XTAL to settle */ for(i = 0xffff; i > 0; i--); /* Delay for XTAL to settle */
@ -156,6 +155,7 @@ void
msp430_cpu_init(void) msp430_cpu_init(void)
{ {
dint(); dint();
watchdog_stop();
init_ports(); init_ports();
msp430_init_dco(); msp430_init_dco();
eint(); eint();