mirror of
https://github.com/oliverschmidt/contiki.git
synced 2024-12-21 19:29:18 +00:00
Merge pull request #691 from hexluthor/rts-cts
CC2538: Add hardware flow control (RTS/CTS) support on UART1.
This commit is contained in:
commit
2e166a83c7
@ -287,10 +287,6 @@ uart_init(uint8_t uart)
|
||||
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
|
||||
GPIO_PIN_MASK(regs->rx.pin));
|
||||
|
||||
if(regs->cts.port >= 0 || regs->rts.port >= 0) {
|
||||
/* TODO Hardware flow control */
|
||||
}
|
||||
|
||||
/*
|
||||
* UART Interrupt Masks:
|
||||
* Acknowledge RX and RX Timeout
|
||||
@ -312,6 +308,24 @@ uart_init(uint8_t uart)
|
||||
/* UART Control: 8N1 with FIFOs */
|
||||
REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
|
||||
|
||||
/*
|
||||
* Enable hardware flow control (RTS/CTS) if requested.
|
||||
* Note that hardware flow control is available only on UART1.
|
||||
*/
|
||||
if(regs->cts.port >= 0) {
|
||||
REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
|
||||
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
|
||||
ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
|
||||
REG(UART_1_BASE | UART_CTL) |= UART_CTL_CTSEN;
|
||||
}
|
||||
|
||||
if(regs->rts.port >= 0) {
|
||||
ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
|
||||
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
|
||||
ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
|
||||
REG(UART_1_BASE | UART_CTL) |= UART_CTL_RTSEN;
|
||||
}
|
||||
|
||||
/* UART Enable */
|
||||
REG(regs->base | UART_CTL) |= UART_CTL_UARTEN;
|
||||
|
||||
|
@ -165,6 +165,8 @@
|
||||
/** \name UART_CTL Register Bit-Masks
|
||||
* @{
|
||||
*/
|
||||
#define UART_CTL_CTSEN 0x00008000 /**< UART CTS flow-control enable (UART1 only) */
|
||||
#define UART_CTL_RTSEN 0x00004000 /**< UART RTS flow-control enable (UART1 only) */
|
||||
#define UART_CTL_RXE 0x00000200 /**< UART receive enable */
|
||||
#define UART_CTL_TXE 0x00000100 /**< UART transmit enable */
|
||||
#define UART_CTL_LBE 0x00000080 /**< UART loop back enable */
|
||||
|
Loading…
Reference in New Issue
Block a user